1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "debug.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "ps.h" 10 #include "reg.h" 11 #include "sar.h" 12 #include "coex.h" 13 14 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 15 const struct rtw89_ra_report *report) 16 { 17 u32 bit_rate = report->bit_rate; 18 19 /* lower than ofdm, do not aggregate */ 20 if (bit_rate < 550) 21 return 1; 22 23 /* avoid AMSDU for legacy rate */ 24 if (report->might_fallback_legacy) 25 return 1; 26 27 /* lower than 20M vht 2ss mcs8, make it small */ 28 if (bit_rate < 1800) 29 return 1200; 30 31 /* lower than 40M vht 2ss mcs9, make it medium */ 32 if (bit_rate < 4000) 33 return 2600; 34 35 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 36 if (bit_rate < 7000) 37 return 3500; 38 39 return rtwdev->chip->max_amsdu_limit; 40 } 41 42 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 43 { 44 u64 ra_mask = 0; 45 u8 mcs_cap; 46 int i, nss; 47 48 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 49 mcs_cap = mcs_map & 0x3; 50 switch (mcs_cap) { 51 case 2: 52 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 53 break; 54 case 1: 55 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 56 break; 57 case 0: 58 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 59 break; 60 default: 61 break; 62 } 63 } 64 65 return ra_mask; 66 } 67 68 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 69 { 70 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 71 u16 mcs_map; 72 73 switch (sta->deflink.bandwidth) { 74 case IEEE80211_STA_RX_BW_160: 75 if (cap.he_cap_elem.phy_cap_info[0] & 76 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 77 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 78 else 79 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 80 break; 81 default: 82 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 83 } 84 85 /* MCS11, MCS9, MCS7 */ 86 return get_mcs_ra_mask(mcs_map, 11, 2); 87 } 88 89 #define RA_FLOOR_TABLE_SIZE 7 90 #define RA_FLOOR_UP_GAP 3 91 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 92 u8 ratr_state) 93 { 94 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 95 u8 rssi_lv = 0; 96 u8 i; 97 98 rssi >>= 1; 99 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 100 if (i >= ratr_state) 101 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 102 if (rssi < rssi_lv_t[i]) { 103 rssi_lv = i; 104 break; 105 } 106 } 107 if (rssi_lv == 0) 108 return 0xffffffffffffffffULL; 109 else if (rssi_lv == 1) 110 return 0xfffffffffffffff0ULL; 111 else if (rssi_lv == 2) 112 return 0xffffffffffffefe0ULL; 113 else if (rssi_lv == 3) 114 return 0xffffffffffffcfc0ULL; 115 else if (rssi_lv == 4) 116 return 0xffffffffffff8f80ULL; 117 else if (rssi_lv >= 5) 118 return 0xffffffffffff0f00ULL; 119 120 return 0xffffffffffffffffULL; 121 } 122 123 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 124 { 125 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 126 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 127 128 if (ra_mask == 0) 129 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 130 131 return ra_mask; 132 } 133 134 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 135 { 136 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 137 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 138 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 139 enum nl80211_band band; 140 u64 cfg_mask; 141 142 if (!rtwsta->use_cfg_mask) 143 return -1; 144 145 switch (chan->band_type) { 146 case RTW89_BAND_2G: 147 band = NL80211_BAND_2GHZ; 148 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 149 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 150 break; 151 case RTW89_BAND_5G: 152 band = NL80211_BAND_5GHZ; 153 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 154 RA_MASK_OFDM_RATES); 155 break; 156 case RTW89_BAND_6G: 157 band = NL80211_BAND_6GHZ; 158 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 159 RA_MASK_OFDM_RATES); 160 break; 161 default: 162 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 163 return -1; 164 } 165 166 if (sta->deflink.he_cap.has_he) { 167 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 168 RA_MASK_HE_1SS_RATES); 169 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 170 RA_MASK_HE_2SS_RATES); 171 } else if (sta->deflink.vht_cap.vht_supported) { 172 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 173 RA_MASK_VHT_1SS_RATES); 174 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 175 RA_MASK_VHT_2SS_RATES); 176 } else if (sta->deflink.ht_cap.ht_supported) { 177 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 178 RA_MASK_HT_1SS_RATES); 179 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 180 RA_MASK_HT_2SS_RATES); 181 } 182 183 return cfg_mask; 184 } 185 186 static const u64 187 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 188 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 189 static const u64 190 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 191 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 192 static const u64 193 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 194 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 195 196 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 197 struct rtw89_sta *rtwsta, 198 bool *fix_giltf_en, u8 *fix_giltf) 199 { 200 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 201 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 202 u8 band = chan->band_type; 203 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 204 u8 he_gi = mask->control[nl_band].he_gi; 205 u8 he_ltf = mask->control[nl_band].he_ltf; 206 207 if (!rtwsta->use_cfg_mask) 208 return; 209 210 if (he_ltf == 2 && he_gi == 2) { 211 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 212 } else if (he_ltf == 2 && he_gi == 0) { 213 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 214 } else if (he_ltf == 1 && he_gi == 1) { 215 *fix_giltf = RTW89_GILTF_2XHE16; 216 } else if (he_ltf == 1 && he_gi == 0) { 217 *fix_giltf = RTW89_GILTF_2XHE08; 218 } else if (he_ltf == 0 && he_gi == 1) { 219 *fix_giltf = RTW89_GILTF_1XHE16; 220 } else if (he_ltf == 0 && he_gi == 0) { 221 *fix_giltf = RTW89_GILTF_1XHE08; 222 } else { 223 *fix_giltf_en = false; 224 return; 225 } 226 227 *fix_giltf_en = true; 228 } 229 230 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 231 struct ieee80211_sta *sta, bool csi) 232 { 233 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 234 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 235 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 236 struct rtw89_ra_info *ra = &rtwsta->ra; 237 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 238 struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); 239 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 240 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 241 u64 ra_mask = 0; 242 u64 ra_mask_bak; 243 u8 mode = 0; 244 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 245 u8 bw_mode = 0; 246 u8 stbc_en = 0; 247 u8 ldpc_en = 0; 248 u8 fix_giltf = 0; 249 u8 i; 250 bool sgi = false; 251 bool fix_giltf_en = false; 252 253 memset(ra, 0, sizeof(*ra)); 254 /* Set the ra mask from sta's capability */ 255 if (sta->deflink.he_cap.has_he) { 256 mode |= RTW89_RA_MODE_HE; 257 csi_mode = RTW89_RA_RPT_MODE_HE; 258 ra_mask |= get_he_ra_mask(sta); 259 high_rate_masks = rtw89_ra_mask_he_rates; 260 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 261 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 262 stbc_en = 1; 263 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 264 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 265 ldpc_en = 1; 266 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, &fix_giltf_en, &fix_giltf); 267 } else if (sta->deflink.vht_cap.vht_supported) { 268 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 269 270 mode |= RTW89_RA_MODE_VHT; 271 csi_mode = RTW89_RA_RPT_MODE_VHT; 272 /* MCS9, MCS8, MCS7 */ 273 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 274 high_rate_masks = rtw89_ra_mask_vht_rates; 275 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 276 stbc_en = 1; 277 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 278 ldpc_en = 1; 279 } else if (sta->deflink.ht_cap.ht_supported) { 280 mode |= RTW89_RA_MODE_HT; 281 csi_mode = RTW89_RA_RPT_MODE_HT; 282 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 283 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 284 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 285 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 286 high_rate_masks = rtw89_ra_mask_ht_rates; 287 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 288 stbc_en = 1; 289 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 290 ldpc_en = 1; 291 } 292 293 switch (chan->band_type) { 294 case RTW89_BAND_2G: 295 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 296 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xf) 297 mode |= RTW89_RA_MODE_CCK; 298 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xff0) 299 mode |= RTW89_RA_MODE_OFDM; 300 break; 301 case RTW89_BAND_5G: 302 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 303 mode |= RTW89_RA_MODE_OFDM; 304 break; 305 case RTW89_BAND_6G: 306 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 307 mode |= RTW89_RA_MODE_OFDM; 308 break; 309 default: 310 rtw89_err(rtwdev, "Unknown band type\n"); 311 break; 312 } 313 314 ra_mask_bak = ra_mask; 315 316 if (mode >= RTW89_RA_MODE_HT) { 317 u64 mask = 0; 318 for (i = 0; i < rtwdev->hal.tx_nss; i++) 319 mask |= high_rate_masks[i]; 320 if (mode & RTW89_RA_MODE_OFDM) 321 mask |= RA_MASK_SUBOFDM_RATES; 322 if (mode & RTW89_RA_MODE_CCK) 323 mask |= RA_MASK_SUBCCK_RATES; 324 ra_mask &= mask; 325 } else if (mode & RTW89_RA_MODE_OFDM) { 326 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 327 } 328 329 if (mode != RTW89_RA_MODE_CCK) 330 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 331 332 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 333 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 334 335 switch (sta->deflink.bandwidth) { 336 case IEEE80211_STA_RX_BW_160: 337 bw_mode = RTW89_CHANNEL_WIDTH_160; 338 sgi = sta->deflink.vht_cap.vht_supported && 339 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 340 break; 341 case IEEE80211_STA_RX_BW_80: 342 bw_mode = RTW89_CHANNEL_WIDTH_80; 343 sgi = sta->deflink.vht_cap.vht_supported && 344 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 345 break; 346 case IEEE80211_STA_RX_BW_40: 347 bw_mode = RTW89_CHANNEL_WIDTH_40; 348 sgi = sta->deflink.ht_cap.ht_supported && 349 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 350 break; 351 default: 352 bw_mode = RTW89_CHANNEL_WIDTH_20; 353 sgi = sta->deflink.ht_cap.ht_supported && 354 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 355 break; 356 } 357 358 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 359 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 360 ra->dcm_cap = 1; 361 362 if (rate_pattern->enable && !vif->p2p) { 363 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 364 ra_mask &= rate_pattern->ra_mask; 365 mode = rate_pattern->ra_mode; 366 } 367 368 ra->bw_cap = bw_mode; 369 ra->mode_ctrl = mode; 370 ra->macid = rtwsta->mac_id; 371 ra->stbc_cap = stbc_en; 372 ra->ldpc_cap = ldpc_en; 373 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 374 ra->en_sgi = sgi; 375 ra->ra_mask = ra_mask; 376 ra->fix_giltf_en = fix_giltf_en; 377 ra->fix_giltf = fix_giltf; 378 379 if (!csi) 380 return; 381 382 ra->fixed_csi_rate_en = false; 383 ra->ra_csi_rate_en = true; 384 ra->cr_tbl_sel = false; 385 ra->band_num = rtwvif->phy_idx; 386 ra->csi_bw = bw_mode; 387 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 388 ra->csi_mcs_ss_idx = 5; 389 ra->csi_mode = csi_mode; 390 } 391 392 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 393 u32 changed) 394 { 395 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 396 struct rtw89_ra_info *ra = &rtwsta->ra; 397 398 rtw89_phy_ra_sta_update(rtwdev, sta, false); 399 400 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 401 ra->upd_mask = 1; 402 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 403 ra->upd_bw_nss_mask = 1; 404 405 rtw89_debug(rtwdev, RTW89_DBG_RA, 406 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 407 ra->macid, 408 ra->bw_cap, 409 ra->ss_num, 410 ra->en_sgi, 411 ra->giltf); 412 413 rtw89_fw_h2c_ra(rtwdev, ra, false); 414 } 415 416 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 417 u16 rate_base, u64 ra_mask, u8 ra_mode, 418 u32 rate_ctrl, u32 ctrl_skip, bool force) 419 { 420 u8 n, c; 421 422 if (rate_ctrl == ctrl_skip) 423 return true; 424 425 n = hweight32(rate_ctrl); 426 if (n == 0) 427 return true; 428 429 if (force && n != 1) 430 return false; 431 432 if (next->enable) 433 return false; 434 435 c = __fls(rate_ctrl); 436 next->rate = rate_base + c; 437 next->ra_mode = ra_mode; 438 next->ra_mask = ra_mask; 439 next->enable = true; 440 441 return true; 442 } 443 444 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 445 struct ieee80211_vif *vif, 446 const struct cfg80211_bitrate_mask *mask) 447 { 448 struct ieee80211_supported_band *sband; 449 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 450 struct rtw89_phy_rate_pattern next_pattern = {0}; 451 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 452 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0, 453 RTW89_HW_RATE_HE_NSS2_MCS0, 454 RTW89_HW_RATE_HE_NSS3_MCS0, 455 RTW89_HW_RATE_HE_NSS4_MCS0}; 456 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0, 457 RTW89_HW_RATE_VHT_NSS2_MCS0, 458 RTW89_HW_RATE_VHT_NSS3_MCS0, 459 RTW89_HW_RATE_VHT_NSS4_MCS0}; 460 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0, 461 RTW89_HW_RATE_MCS8, 462 RTW89_HW_RATE_MCS16, 463 RTW89_HW_RATE_MCS24}; 464 u8 band = chan->band_type; 465 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 466 u8 tx_nss = rtwdev->hal.tx_nss; 467 u8 i; 468 469 for (i = 0; i < tx_nss; i++) 470 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i], 471 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 472 mask->control[nl_band].he_mcs[i], 473 0, true)) 474 goto out; 475 476 for (i = 0; i < tx_nss; i++) 477 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i], 478 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 479 mask->control[nl_band].vht_mcs[i], 480 0, true)) 481 goto out; 482 483 for (i = 0; i < tx_nss; i++) 484 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i], 485 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 486 mask->control[nl_band].ht_mcs[i], 487 0, true)) 488 goto out; 489 490 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 491 * require at least one basic rate for ieee80211_set_bitrate_mask, 492 * so the decision just depends on if all bitrates are set or not. 493 */ 494 sband = rtwdev->hw->wiphy->bands[nl_band]; 495 if (band == RTW89_BAND_2G) { 496 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 497 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 498 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 499 mask->control[nl_band].legacy, 500 BIT(sband->n_bitrates) - 1, false)) 501 goto out; 502 } else { 503 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 504 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 505 mask->control[nl_band].legacy, 506 BIT(sband->n_bitrates) - 1, false)) 507 goto out; 508 } 509 510 if (!next_pattern.enable) 511 goto out; 512 513 rtwvif->rate_pattern = next_pattern; 514 rtw89_debug(rtwdev, RTW89_DBG_RA, 515 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 516 next_pattern.rate, 517 next_pattern.ra_mask, 518 next_pattern.ra_mode); 519 return; 520 521 out: 522 rtwvif->rate_pattern.enable = false; 523 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 524 } 525 526 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 527 { 528 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 529 530 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 531 } 532 533 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 534 { 535 ieee80211_iterate_stations_atomic(rtwdev->hw, 536 rtw89_phy_ra_updata_sta_iter, 537 rtwdev); 538 } 539 540 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 541 { 542 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 543 struct rtw89_ra_info *ra = &rtwsta->ra; 544 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 545 bool csi = rtw89_sta_has_beamformer_cap(sta); 546 547 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 548 549 if (rssi > 40) 550 ra->init_rate_lv = 1; 551 else if (rssi > 20) 552 ra->init_rate_lv = 2; 553 else if (rssi > 1) 554 ra->init_rate_lv = 3; 555 else 556 ra->init_rate_lv = 0; 557 ra->upd_all = 1; 558 rtw89_debug(rtwdev, RTW89_DBG_RA, 559 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 560 ra->macid, 561 ra->mode_ctrl, 562 ra->bw_cap, 563 ra->ss_num, 564 ra->init_rate_lv); 565 rtw89_debug(rtwdev, RTW89_DBG_RA, 566 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 567 ra->dcm_cap, 568 ra->er_cap, 569 ra->ldpc_cap, 570 ra->stbc_cap, 571 ra->en_sgi, 572 ra->giltf); 573 574 rtw89_fw_h2c_ra(rtwdev, ra, csi); 575 } 576 577 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 578 const struct rtw89_chan *chan, 579 enum rtw89_bandwidth dbw) 580 { 581 enum rtw89_bandwidth cbw = chan->band_width; 582 u8 pri_ch = chan->primary_channel; 583 u8 central_ch = chan->channel; 584 u8 txsc_idx = 0; 585 u8 tmp = 0; 586 587 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 588 return txsc_idx; 589 590 switch (cbw) { 591 case RTW89_CHANNEL_WIDTH_40: 592 txsc_idx = pri_ch > central_ch ? 1 : 2; 593 break; 594 case RTW89_CHANNEL_WIDTH_80: 595 if (dbw == RTW89_CHANNEL_WIDTH_20) { 596 if (pri_ch > central_ch) 597 txsc_idx = (pri_ch - central_ch) >> 1; 598 else 599 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 600 } else { 601 txsc_idx = pri_ch > central_ch ? 9 : 10; 602 } 603 break; 604 case RTW89_CHANNEL_WIDTH_160: 605 if (pri_ch > central_ch) 606 tmp = (pri_ch - central_ch) >> 1; 607 else 608 tmp = ((central_ch - pri_ch) >> 1) + 1; 609 610 if (dbw == RTW89_CHANNEL_WIDTH_20) { 611 txsc_idx = tmp; 612 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 613 if (tmp == 1 || tmp == 3) 614 txsc_idx = 9; 615 else if (tmp == 5 || tmp == 7) 616 txsc_idx = 11; 617 else if (tmp == 2 || tmp == 4) 618 txsc_idx = 10; 619 else if (tmp == 6 || tmp == 8) 620 txsc_idx = 12; 621 else 622 return 0xff; 623 } else { 624 txsc_idx = pri_ch > central_ch ? 13 : 14; 625 } 626 break; 627 case RTW89_CHANNEL_WIDTH_80_80: 628 if (dbw == RTW89_CHANNEL_WIDTH_20) { 629 if (pri_ch > central_ch) 630 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 631 else 632 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 633 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 634 txsc_idx = pri_ch > central_ch ? 10 : 12; 635 } else { 636 txsc_idx = 14; 637 } 638 break; 639 default: 640 break; 641 } 642 643 return txsc_idx; 644 } 645 EXPORT_SYMBOL(rtw89_phy_get_txsc); 646 647 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 648 { 649 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 650 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 651 } 652 653 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 654 u32 addr, u32 mask) 655 { 656 const struct rtw89_chip_info *chip = rtwdev->chip; 657 const u32 *base_addr = chip->rf_base_addr; 658 u32 val, direct_addr; 659 660 if (rf_path >= rtwdev->chip->rf_path_num) { 661 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 662 return INV_RF_DATA; 663 } 664 665 addr &= 0xff; 666 direct_addr = base_addr[rf_path] + (addr << 2); 667 mask &= RFREG_MASK; 668 669 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 670 671 return val; 672 } 673 EXPORT_SYMBOL(rtw89_phy_read_rf); 674 675 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 676 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 677 { 678 bool busy; 679 bool done; 680 u32 val; 681 int ret; 682 683 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 684 1, 30, false, rtwdev); 685 if (ret) { 686 rtw89_err(rtwdev, "read rf busy swsi\n"); 687 return INV_RF_DATA; 688 } 689 690 mask &= RFREG_MASK; 691 692 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 693 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 694 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 695 udelay(2); 696 697 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 698 30, false, rtwdev, R_SWSI_V1, 699 B_SWSI_R_DATA_DONE_V1); 700 if (ret) { 701 rtw89_err(rtwdev, "read swsi busy\n"); 702 return INV_RF_DATA; 703 } 704 705 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 706 } 707 708 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 709 u32 addr, u32 mask) 710 { 711 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 712 713 if (rf_path >= rtwdev->chip->rf_path_num) { 714 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 715 return INV_RF_DATA; 716 } 717 718 if (ad_sel) 719 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 720 else 721 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 722 } 723 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 724 725 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 726 u32 addr, u32 mask, u32 data) 727 { 728 const struct rtw89_chip_info *chip = rtwdev->chip; 729 const u32 *base_addr = chip->rf_base_addr; 730 u32 direct_addr; 731 732 if (rf_path >= rtwdev->chip->rf_path_num) { 733 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 734 return false; 735 } 736 737 addr &= 0xff; 738 direct_addr = base_addr[rf_path] + (addr << 2); 739 mask &= RFREG_MASK; 740 741 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 742 743 /* delay to ensure writing properly */ 744 udelay(1); 745 746 return true; 747 } 748 EXPORT_SYMBOL(rtw89_phy_write_rf); 749 750 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 751 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 752 u32 data) 753 { 754 u8 bit_shift; 755 u32 val; 756 bool busy, b_msk_en = false; 757 int ret; 758 759 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 760 1, 30, false, rtwdev); 761 if (ret) { 762 rtw89_err(rtwdev, "write rf busy swsi\n"); 763 return false; 764 } 765 766 data &= RFREG_MASK; 767 mask &= RFREG_MASK; 768 769 if (mask != RFREG_MASK) { 770 b_msk_en = true; 771 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 772 mask); 773 bit_shift = __ffs(mask); 774 data = (data << bit_shift) & RFREG_MASK; 775 } 776 777 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 778 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 779 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 780 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 781 782 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 783 784 return true; 785 } 786 787 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 788 u32 addr, u32 mask, u32 data) 789 { 790 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 791 792 if (rf_path >= rtwdev->chip->rf_path_num) { 793 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 794 return false; 795 } 796 797 if (ad_sel) 798 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 799 else 800 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 801 } 802 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 803 804 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 805 { 806 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; 807 } 808 809 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 810 enum rtw89_phy_idx phy_idx) 811 { 812 const struct rtw89_chip_info *chip = rtwdev->chip; 813 814 chip->ops->bb_reset(rtwdev, phy_idx); 815 } 816 817 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 818 const struct rtw89_reg2_def *reg, 819 enum rtw89_rf_path rf_path, 820 void *extra_data) 821 { 822 if (reg->addr == 0xfe) 823 mdelay(50); 824 else if (reg->addr == 0xfd) 825 mdelay(5); 826 else if (reg->addr == 0xfc) 827 mdelay(1); 828 else if (reg->addr == 0xfb) 829 udelay(50); 830 else if (reg->addr == 0xfa) 831 udelay(5); 832 else if (reg->addr == 0xf9) 833 udelay(1); 834 else 835 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 836 } 837 838 union rtw89_phy_bb_gain_arg { 839 u32 addr; 840 struct { 841 union { 842 u8 type; 843 struct { 844 u8 rxsc_start:4; 845 u8 bw:4; 846 }; 847 }; 848 u8 path; 849 u8 gain_band; 850 u8 cfg_type; 851 }; 852 } __packed; 853 854 static void 855 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 856 union rtw89_phy_bb_gain_arg arg, u32 data) 857 { 858 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 859 u8 type = arg.type; 860 u8 path = arg.path; 861 u8 gband = arg.gain_band; 862 int i; 863 864 switch (type) { 865 case 0: 866 for (i = 0; i < 4; i++, data >>= 8) 867 gain->lna_gain[gband][path][i] = data & 0xff; 868 break; 869 case 1: 870 for (i = 4; i < 7; i++, data >>= 8) 871 gain->lna_gain[gband][path][i] = data & 0xff; 872 break; 873 case 2: 874 for (i = 0; i < 2; i++, data >>= 8) 875 gain->tia_gain[gband][path][i] = data & 0xff; 876 break; 877 default: 878 rtw89_warn(rtwdev, 879 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 880 arg.addr, data, type); 881 break; 882 } 883 } 884 885 enum rtw89_phy_bb_rxsc_start_idx { 886 RTW89_BB_RXSC_START_IDX_FULL = 0, 887 RTW89_BB_RXSC_START_IDX_20 = 1, 888 RTW89_BB_RXSC_START_IDX_20_1 = 5, 889 RTW89_BB_RXSC_START_IDX_40 = 9, 890 RTW89_BB_RXSC_START_IDX_80 = 13, 891 }; 892 893 static void 894 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 895 union rtw89_phy_bb_gain_arg arg, u32 data) 896 { 897 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 898 u8 rxsc_start = arg.rxsc_start; 899 u8 bw = arg.bw; 900 u8 path = arg.path; 901 u8 gband = arg.gain_band; 902 u8 rxsc; 903 s8 ofst; 904 int i; 905 906 switch (bw) { 907 case RTW89_CHANNEL_WIDTH_20: 908 gain->rpl_ofst_20[gband][path] = (s8)data; 909 break; 910 case RTW89_CHANNEL_WIDTH_40: 911 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 912 gain->rpl_ofst_40[gband][path][0] = (s8)data; 913 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 914 for (i = 0; i < 2; i++, data >>= 8) { 915 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 916 ofst = (s8)(data & 0xff); 917 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 918 } 919 } 920 break; 921 case RTW89_CHANNEL_WIDTH_80: 922 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 923 gain->rpl_ofst_80[gband][path][0] = (s8)data; 924 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 925 for (i = 0; i < 4; i++, data >>= 8) { 926 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 927 ofst = (s8)(data & 0xff); 928 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 929 } 930 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 931 for (i = 0; i < 2; i++, data >>= 8) { 932 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 933 ofst = (s8)(data & 0xff); 934 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 935 } 936 } 937 break; 938 case RTW89_CHANNEL_WIDTH_160: 939 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 940 gain->rpl_ofst_160[gband][path][0] = (s8)data; 941 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 942 for (i = 0; i < 4; i++, data >>= 8) { 943 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 944 ofst = (s8)(data & 0xff); 945 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 946 } 947 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 948 for (i = 0; i < 4; i++, data >>= 8) { 949 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 950 ofst = (s8)(data & 0xff); 951 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 952 } 953 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 954 for (i = 0; i < 4; i++, data >>= 8) { 955 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 956 ofst = (s8)(data & 0xff); 957 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 958 } 959 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 960 for (i = 0; i < 2; i++, data >>= 8) { 961 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 962 ofst = (s8)(data & 0xff); 963 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 964 } 965 } 966 break; 967 default: 968 rtw89_warn(rtwdev, 969 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 970 arg.addr, data, bw); 971 break; 972 } 973 } 974 975 static void 976 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 977 union rtw89_phy_bb_gain_arg arg, u32 data) 978 { 979 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 980 u8 type = arg.type; 981 u8 path = arg.path; 982 u8 gband = arg.gain_band; 983 int i; 984 985 switch (type) { 986 case 0: 987 for (i = 0; i < 4; i++, data >>= 8) 988 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 989 break; 990 case 1: 991 for (i = 4; i < 7; i++, data >>= 8) 992 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 993 break; 994 default: 995 rtw89_warn(rtwdev, 996 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 997 arg.addr, data, type); 998 break; 999 } 1000 } 1001 1002 static void 1003 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 1004 union rtw89_phy_bb_gain_arg arg, u32 data) 1005 { 1006 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 1007 u8 type = arg.type; 1008 u8 path = arg.path; 1009 u8 gband = arg.gain_band; 1010 int i; 1011 1012 switch (type) { 1013 case 0: 1014 for (i = 0; i < 4; i++, data >>= 8) 1015 gain->lna_op1db[gband][path][i] = data & 0xff; 1016 break; 1017 case 1: 1018 for (i = 4; i < 7; i++, data >>= 8) 1019 gain->lna_op1db[gband][path][i] = data & 0xff; 1020 break; 1021 case 2: 1022 for (i = 0; i < 4; i++, data >>= 8) 1023 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1024 break; 1025 case 3: 1026 for (i = 4; i < 8; i++, data >>= 8) 1027 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1028 break; 1029 default: 1030 rtw89_warn(rtwdev, 1031 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1032 arg.addr, data, type); 1033 break; 1034 } 1035 } 1036 1037 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev, 1038 const struct rtw89_reg2_def *reg, 1039 enum rtw89_rf_path rf_path, 1040 void *extra_data) 1041 { 1042 const struct rtw89_chip_info *chip = rtwdev->chip; 1043 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1044 struct rtw89_efuse *efuse = &rtwdev->efuse; 1045 1046 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1047 return; 1048 1049 if (arg.path >= chip->rf_path_num) 1050 return; 1051 1052 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1053 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1054 return; 1055 } 1056 1057 switch (arg.cfg_type) { 1058 case 0: 1059 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1060 break; 1061 case 1: 1062 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1063 break; 1064 case 2: 1065 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1066 break; 1067 case 3: 1068 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1069 break; 1070 case 4: 1071 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 1072 if (efuse->rfe_type < 50) 1073 break; 1074 fallthrough; 1075 default: 1076 rtw89_warn(rtwdev, 1077 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1078 arg.addr, reg->data, arg.cfg_type); 1079 break; 1080 } 1081 } 1082 1083 static void 1084 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1085 const struct rtw89_reg2_def *reg, 1086 enum rtw89_rf_path rf_path, 1087 struct rtw89_fw_h2c_rf_reg_info *info) 1088 { 1089 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1090 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1091 1092 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1093 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1094 rf_path, info->curr_idx); 1095 return; 1096 } 1097 1098 info->rtw89_phy_config_rf_h2c[page][idx] = 1099 cpu_to_le32((reg->addr << 20) | reg->data); 1100 info->curr_idx++; 1101 } 1102 1103 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1104 struct rtw89_fw_h2c_rf_reg_info *info) 1105 { 1106 u16 remain = info->curr_idx; 1107 u16 len = 0; 1108 u8 i; 1109 int ret = 0; 1110 1111 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1112 rtw89_warn(rtwdev, 1113 "rf reg h2c total len %d larger than %d\n", 1114 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1115 ret = -EINVAL; 1116 goto out; 1117 } 1118 1119 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1120 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1121 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1122 if (ret) 1123 goto out; 1124 } 1125 out: 1126 info->curr_idx = 0; 1127 1128 return ret; 1129 } 1130 1131 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev, 1132 const struct rtw89_reg2_def *reg, 1133 enum rtw89_rf_path rf_path, 1134 void *extra_data) 1135 { 1136 u32 addr = reg->addr; 1137 1138 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || 1139 addr == 0xfa || addr == 0xf9) 1140 return; 1141 1142 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100) 1143 return; 1144 1145 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1146 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1147 } 1148 1149 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1150 const struct rtw89_reg2_def *reg, 1151 enum rtw89_rf_path rf_path, 1152 void *extra_data) 1153 { 1154 if (reg->addr == 0xfe) { 1155 mdelay(50); 1156 } else if (reg->addr == 0xfd) { 1157 mdelay(5); 1158 } else if (reg->addr == 0xfc) { 1159 mdelay(1); 1160 } else if (reg->addr == 0xfb) { 1161 udelay(50); 1162 } else if (reg->addr == 0xfa) { 1163 udelay(5); 1164 } else if (reg->addr == 0xf9) { 1165 udelay(1); 1166 } else { 1167 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1168 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1169 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1170 } 1171 } 1172 1173 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1174 const struct rtw89_reg2_def *reg, 1175 enum rtw89_rf_path rf_path, 1176 void *extra_data) 1177 { 1178 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1179 1180 if (reg->addr < 0x100) 1181 return; 1182 1183 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1184 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1185 } 1186 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1187 1188 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1189 const struct rtw89_phy_table *table, 1190 u32 *headline_size, u32 *headline_idx, 1191 u8 rfe, u8 cv) 1192 { 1193 const struct rtw89_reg2_def *reg; 1194 u32 headline; 1195 u32 compare, target; 1196 u8 rfe_para, cv_para; 1197 u8 cv_max = 0; 1198 bool case_matched = false; 1199 u32 i; 1200 1201 for (i = 0; i < table->n_regs; i++) { 1202 reg = &table->regs[i]; 1203 headline = get_phy_headline(reg->addr); 1204 if (headline != PHY_HEADLINE_VALID) 1205 break; 1206 } 1207 *headline_size = i; 1208 if (*headline_size == 0) 1209 return 0; 1210 1211 /* case 1: RFE match, CV match */ 1212 compare = get_phy_compare(rfe, cv); 1213 for (i = 0; i < *headline_size; i++) { 1214 reg = &table->regs[i]; 1215 target = get_phy_target(reg->addr); 1216 if (target == compare) { 1217 *headline_idx = i; 1218 return 0; 1219 } 1220 } 1221 1222 /* case 2: RFE match, CV don't care */ 1223 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1224 for (i = 0; i < *headline_size; i++) { 1225 reg = &table->regs[i]; 1226 target = get_phy_target(reg->addr); 1227 if (target == compare) { 1228 *headline_idx = i; 1229 return 0; 1230 } 1231 } 1232 1233 /* case 3: RFE match, CV max in table */ 1234 for (i = 0; i < *headline_size; i++) { 1235 reg = &table->regs[i]; 1236 rfe_para = get_phy_cond_rfe(reg->addr); 1237 cv_para = get_phy_cond_cv(reg->addr); 1238 if (rfe_para == rfe) { 1239 if (cv_para >= cv_max) { 1240 cv_max = cv_para; 1241 *headline_idx = i; 1242 case_matched = true; 1243 } 1244 } 1245 } 1246 1247 if (case_matched) 1248 return 0; 1249 1250 /* case 4: RFE don't care, CV max in table */ 1251 for (i = 0; i < *headline_size; i++) { 1252 reg = &table->regs[i]; 1253 rfe_para = get_phy_cond_rfe(reg->addr); 1254 cv_para = get_phy_cond_cv(reg->addr); 1255 if (rfe_para == PHY_COND_DONT_CARE) { 1256 if (cv_para >= cv_max) { 1257 cv_max = cv_para; 1258 *headline_idx = i; 1259 case_matched = true; 1260 } 1261 } 1262 } 1263 1264 if (case_matched) 1265 return 0; 1266 1267 return -EINVAL; 1268 } 1269 1270 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1271 const struct rtw89_phy_table *table, 1272 void (*config)(struct rtw89_dev *rtwdev, 1273 const struct rtw89_reg2_def *reg, 1274 enum rtw89_rf_path rf_path, 1275 void *data), 1276 void *extra_data) 1277 { 1278 const struct rtw89_reg2_def *reg; 1279 enum rtw89_rf_path rf_path = table->rf_path; 1280 u8 rfe = rtwdev->efuse.rfe_type; 1281 u8 cv = rtwdev->hal.cv; 1282 u32 i; 1283 u32 headline_size = 0, headline_idx = 0; 1284 u32 target = 0, cfg_target; 1285 u8 cond; 1286 bool is_matched = true; 1287 bool target_found = false; 1288 int ret; 1289 1290 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1291 &headline_idx, rfe, cv); 1292 if (ret) { 1293 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1294 return; 1295 } 1296 1297 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1298 for (i = headline_size; i < table->n_regs; i++) { 1299 reg = &table->regs[i]; 1300 cond = get_phy_cond(reg->addr); 1301 switch (cond) { 1302 case PHY_COND_BRANCH_IF: 1303 case PHY_COND_BRANCH_ELIF: 1304 target = get_phy_target(reg->addr); 1305 break; 1306 case PHY_COND_BRANCH_ELSE: 1307 is_matched = false; 1308 if (!target_found) { 1309 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1310 reg->addr, reg->data); 1311 return; 1312 } 1313 break; 1314 case PHY_COND_BRANCH_END: 1315 is_matched = true; 1316 target_found = false; 1317 break; 1318 case PHY_COND_CHECK: 1319 if (target_found) { 1320 is_matched = false; 1321 break; 1322 } 1323 1324 if (target == cfg_target) { 1325 is_matched = true; 1326 target_found = true; 1327 } else { 1328 is_matched = false; 1329 target_found = false; 1330 } 1331 break; 1332 default: 1333 if (is_matched) 1334 config(rtwdev, reg, rf_path, extra_data); 1335 break; 1336 } 1337 } 1338 } 1339 1340 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1341 { 1342 const struct rtw89_chip_info *chip = rtwdev->chip; 1343 const struct rtw89_phy_table *bb_table = chip->bb_table; 1344 const struct rtw89_phy_table *bb_gain_table = chip->bb_gain_table; 1345 1346 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1347 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1348 if (bb_gain_table) 1349 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1350 rtw89_phy_config_bb_gain, NULL); 1351 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1352 } 1353 1354 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1355 { 1356 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1357 udelay(1); 1358 return rtw89_phy_read32(rtwdev, 0x8080); 1359 } 1360 1361 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio) 1362 { 1363 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1364 enum rtw89_rf_path rf_path, void *data); 1365 const struct rtw89_chip_info *chip = rtwdev->chip; 1366 const struct rtw89_phy_table *rf_table; 1367 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1368 u8 path; 1369 1370 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1371 if (!rf_reg_info) 1372 return; 1373 1374 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1375 rf_table = chip->rf_table[path]; 1376 rf_reg_info->rf_path = rf_table->rf_path; 1377 if (noio) 1378 config = rtw89_phy_config_rf_reg_noio; 1379 else 1380 config = rf_table->config ? rf_table->config : 1381 rtw89_phy_config_rf_reg; 1382 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1383 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1384 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1385 rf_reg_info->rf_path); 1386 } 1387 kfree(rf_reg_info); 1388 } 1389 1390 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1391 { 1392 const struct rtw89_chip_info *chip = rtwdev->chip; 1393 const struct rtw89_phy_table *nctl_table; 1394 u32 val; 1395 int ret; 1396 1397 /* IQK/DPK clock & reset */ 1398 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3); 1399 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1); 1400 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000); 1401 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000); 1402 if (chip->chip_id == RTL8852B) 1403 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2); 1404 1405 /* check 0x8080 */ 1406 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8); 1407 1408 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1409 1000, false, rtwdev); 1410 if (ret) 1411 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1412 1413 nctl_table = chip->nctl_table; 1414 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1415 } 1416 1417 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1418 { 1419 u32 phy_page = addr >> 8; 1420 u32 ofst = 0; 1421 1422 switch (phy_page) { 1423 case 0x6: 1424 case 0x7: 1425 case 0x8: 1426 case 0x9: 1427 case 0xa: 1428 case 0xb: 1429 case 0xc: 1430 case 0xd: 1431 case 0x19: 1432 case 0x1a: 1433 case 0x1b: 1434 ofst = 0x2000; 1435 break; 1436 default: 1437 /* warning case */ 1438 ofst = 0; 1439 break; 1440 } 1441 1442 if (phy_page >= 0x40 && phy_page <= 0x4f) 1443 ofst = 0x2000; 1444 1445 return ofst; 1446 } 1447 1448 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1449 u32 data, enum rtw89_phy_idx phy_idx) 1450 { 1451 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1452 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1453 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1454 } 1455 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1456 1457 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1458 enum rtw89_phy_idx phy_idx) 1459 { 1460 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1461 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1462 return rtw89_phy_read32_mask(rtwdev, addr, mask); 1463 } 1464 EXPORT_SYMBOL(rtw89_phy_read32_idx); 1465 1466 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1467 u32 val) 1468 { 1469 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1470 1471 if (!rtwdev->dbcc_en) 1472 return; 1473 1474 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1475 } 1476 1477 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1478 const struct rtw89_phy_reg3_tbl *tbl) 1479 { 1480 const struct rtw89_reg3_def *reg3; 1481 int i; 1482 1483 for (i = 0; i < tbl->size; i++) { 1484 reg3 = &tbl->reg3[i]; 1485 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1486 } 1487 } 1488 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1489 1490 static const u8 rtw89_rs_idx_max[] = { 1491 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, 1492 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, 1493 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, 1494 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, 1495 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, 1496 }; 1497 1498 static const u8 rtw89_rs_nss_max[] = { 1499 [RTW89_RS_CCK] = 1, 1500 [RTW89_RS_OFDM] = 1, 1501 [RTW89_RS_MCS] = RTW89_NSS_MAX, 1502 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, 1503 [RTW89_RS_OFFSET] = 1, 1504 }; 1505 1506 static const u8 _byr_of_rs[] = { 1507 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), 1508 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), 1509 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), 1510 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), 1511 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), 1512 }; 1513 1514 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) 1515 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) 1516 #define _byr_chk(rs, nss, idx) \ 1517 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) 1518 1519 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1520 const struct rtw89_txpwr_table *tbl) 1521 { 1522 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1523 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1524 s8 *byr; 1525 u32 data; 1526 u8 i, idx; 1527 1528 for (; cfg < end; cfg++) { 1529 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); 1530 data = cfg->data; 1531 1532 for (i = 0; i < cfg->len; i++, data >>= 8) { 1533 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); 1534 byr[idx] = (s8)(data & 0xff); 1535 } 1536 } 1537 } 1538 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1539 1540 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ 1541 ({ \ 1542 const struct rtw89_chip_info *__c = (rtwdev)->chip; \ 1543 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ 1544 }) 1545 1546 static 1547 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, 1548 const struct rtw89_rate_desc *rate_desc) 1549 { 1550 s8 *byr; 1551 u8 idx; 1552 1553 if (rate_desc->rs == RTW89_RS_CCK) 1554 band = RTW89_BAND_2G; 1555 1556 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { 1557 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1558 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", 1559 rate_desc->rs, rate_desc->nss, rate_desc->idx); 1560 1561 return 0; 1562 } 1563 1564 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); 1565 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); 1566 1567 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); 1568 } 1569 1570 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1571 { 1572 switch (channel_6g) { 1573 case 1 ... 29: 1574 return (channel_6g - 1) / 2; 1575 case 33 ... 61: 1576 return (channel_6g - 3) / 2; 1577 case 65 ... 93: 1578 return (channel_6g - 5) / 2; 1579 case 97 ... 125: 1580 return (channel_6g - 7) / 2; 1581 case 129 ... 157: 1582 return (channel_6g - 9) / 2; 1583 case 161 ... 189: 1584 return (channel_6g - 11) / 2; 1585 case 193 ... 221: 1586 return (channel_6g - 13) / 2; 1587 case 225 ... 253: 1588 return (channel_6g - 15) / 2; 1589 default: 1590 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1591 return 0; 1592 } 1593 } 1594 1595 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1596 { 1597 if (band == RTW89_BAND_6G) 1598 return rtw89_channel_6g_to_idx(rtwdev, channel); 1599 1600 switch (channel) { 1601 case 1 ... 14: 1602 return channel - 1; 1603 case 36 ... 64: 1604 return (channel - 36) / 2; 1605 case 100 ... 144: 1606 return ((channel - 100) / 2) + 15; 1607 case 149 ... 177: 1608 return ((channel - 149) / 2) + 38; 1609 default: 1610 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1611 return 0; 1612 } 1613 } 1614 1615 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1616 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1617 { 1618 const struct rtw89_chip_info *chip = rtwdev->chip; 1619 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1620 u8 regd = rtw89_regd_get(rtwdev, band); 1621 s8 lmt = 0, sar; 1622 1623 switch (band) { 1624 case RTW89_BAND_2G: 1625 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx]; 1626 if (!lmt) 1627 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf] 1628 [RTW89_WW][ch_idx]; 1629 break; 1630 case RTW89_BAND_5G: 1631 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx]; 1632 if (!lmt) 1633 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf] 1634 [RTW89_WW][ch_idx]; 1635 break; 1636 case RTW89_BAND_6G: 1637 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf][regd][ch_idx]; 1638 if (!lmt) 1639 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf] 1640 [RTW89_WW][ch_idx]; 1641 break; 1642 default: 1643 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1644 return 0; 1645 } 1646 1647 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); 1648 sar = rtw89_query_sar(rtwdev); 1649 1650 return min(lmt, sar); 1651 } 1652 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1653 1654 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 1655 do { \ 1656 u8 __i; \ 1657 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1658 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1659 band, \ 1660 bw, ntx, \ 1661 rs, __i, \ 1662 (ch)); \ 1663 } while (0) 1664 1665 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, 1666 struct rtw89_txpwr_limit *lmt, 1667 u8 band, u8 ntx, u8 ch) 1668 { 1669 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1670 ntx, RTW89_RS_CCK, ch); 1671 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1672 ntx, RTW89_RS_CCK, ch); 1673 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1674 ntx, RTW89_RS_OFDM, ch); 1675 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1676 RTW89_CHANNEL_WIDTH_20, 1677 ntx, RTW89_RS_MCS, ch); 1678 } 1679 1680 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, 1681 struct rtw89_txpwr_limit *lmt, 1682 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1683 { 1684 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1685 ntx, RTW89_RS_CCK, ch - 2); 1686 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1687 ntx, RTW89_RS_CCK, ch); 1688 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1689 ntx, RTW89_RS_OFDM, pri_ch); 1690 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1691 RTW89_CHANNEL_WIDTH_20, 1692 ntx, RTW89_RS_MCS, ch - 2); 1693 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1694 RTW89_CHANNEL_WIDTH_20, 1695 ntx, RTW89_RS_MCS, ch + 2); 1696 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1697 RTW89_CHANNEL_WIDTH_40, 1698 ntx, RTW89_RS_MCS, ch); 1699 } 1700 1701 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, 1702 struct rtw89_txpwr_limit *lmt, 1703 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1704 { 1705 s8 val_0p5_n[RTW89_BF_NUM]; 1706 s8 val_0p5_p[RTW89_BF_NUM]; 1707 u8 i; 1708 1709 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1710 ntx, RTW89_RS_OFDM, pri_ch); 1711 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1712 RTW89_CHANNEL_WIDTH_20, 1713 ntx, RTW89_RS_MCS, ch - 6); 1714 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1715 RTW89_CHANNEL_WIDTH_20, 1716 ntx, RTW89_RS_MCS, ch - 2); 1717 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1718 RTW89_CHANNEL_WIDTH_20, 1719 ntx, RTW89_RS_MCS, ch + 2); 1720 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1721 RTW89_CHANNEL_WIDTH_20, 1722 ntx, RTW89_RS_MCS, ch + 6); 1723 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1724 RTW89_CHANNEL_WIDTH_40, 1725 ntx, RTW89_RS_MCS, ch - 4); 1726 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1727 RTW89_CHANNEL_WIDTH_40, 1728 ntx, RTW89_RS_MCS, ch + 4); 1729 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1730 RTW89_CHANNEL_WIDTH_80, 1731 ntx, RTW89_RS_MCS, ch); 1732 1733 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1734 ntx, RTW89_RS_MCS, ch - 4); 1735 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1736 ntx, RTW89_RS_MCS, ch + 4); 1737 1738 for (i = 0; i < RTW89_BF_NUM; i++) 1739 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1740 } 1741 1742 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev, 1743 struct rtw89_txpwr_limit *lmt, 1744 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1745 { 1746 s8 val_0p5_n[RTW89_BF_NUM]; 1747 s8 val_0p5_p[RTW89_BF_NUM]; 1748 s8 val_2p5_n[RTW89_BF_NUM]; 1749 s8 val_2p5_p[RTW89_BF_NUM]; 1750 u8 i; 1751 1752 /* fill ofdm section */ 1753 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1754 ntx, RTW89_RS_OFDM, pri_ch); 1755 1756 /* fill mcs 20m section */ 1757 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1758 RTW89_CHANNEL_WIDTH_20, 1759 ntx, RTW89_RS_MCS, ch - 14); 1760 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1761 RTW89_CHANNEL_WIDTH_20, 1762 ntx, RTW89_RS_MCS, ch - 10); 1763 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1764 RTW89_CHANNEL_WIDTH_20, 1765 ntx, RTW89_RS_MCS, ch - 6); 1766 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1767 RTW89_CHANNEL_WIDTH_20, 1768 ntx, RTW89_RS_MCS, ch - 2); 1769 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 1770 RTW89_CHANNEL_WIDTH_20, 1771 ntx, RTW89_RS_MCS, ch + 2); 1772 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 1773 RTW89_CHANNEL_WIDTH_20, 1774 ntx, RTW89_RS_MCS, ch + 6); 1775 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 1776 RTW89_CHANNEL_WIDTH_20, 1777 ntx, RTW89_RS_MCS, ch + 10); 1778 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 1779 RTW89_CHANNEL_WIDTH_20, 1780 ntx, RTW89_RS_MCS, ch + 14); 1781 1782 /* fill mcs 40m section */ 1783 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1784 RTW89_CHANNEL_WIDTH_40, 1785 ntx, RTW89_RS_MCS, ch - 12); 1786 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1787 RTW89_CHANNEL_WIDTH_40, 1788 ntx, RTW89_RS_MCS, ch - 4); 1789 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 1790 RTW89_CHANNEL_WIDTH_40, 1791 ntx, RTW89_RS_MCS, ch + 4); 1792 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 1793 RTW89_CHANNEL_WIDTH_40, 1794 ntx, RTW89_RS_MCS, ch + 12); 1795 1796 /* fill mcs 80m section */ 1797 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1798 RTW89_CHANNEL_WIDTH_80, 1799 ntx, RTW89_RS_MCS, ch - 8); 1800 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 1801 RTW89_CHANNEL_WIDTH_80, 1802 ntx, RTW89_RS_MCS, ch + 8); 1803 1804 /* fill mcs 160m section */ 1805 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 1806 RTW89_CHANNEL_WIDTH_160, 1807 ntx, RTW89_RS_MCS, ch); 1808 1809 /* fill mcs 40m 0p5 section */ 1810 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1811 ntx, RTW89_RS_MCS, ch - 4); 1812 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1813 ntx, RTW89_RS_MCS, ch + 4); 1814 1815 for (i = 0; i < RTW89_BF_NUM; i++) 1816 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1817 1818 /* fill mcs 40m 2p5 section */ 1819 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 1820 ntx, RTW89_RS_MCS, ch - 8); 1821 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 1822 ntx, RTW89_RS_MCS, ch + 8); 1823 1824 for (i = 0; i < RTW89_BF_NUM; i++) 1825 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1826 } 1827 1828 static 1829 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 1830 const struct rtw89_chan *chan, 1831 struct rtw89_txpwr_limit *lmt, 1832 u8 ntx) 1833 { 1834 u8 band = chan->band_type; 1835 u8 pri_ch = chan->primary_channel; 1836 u8 ch = chan->channel; 1837 u8 bw = chan->band_width; 1838 1839 memset(lmt, 0, sizeof(*lmt)); 1840 1841 switch (bw) { 1842 case RTW89_CHANNEL_WIDTH_20: 1843 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, band, ntx, ch); 1844 break; 1845 case RTW89_CHANNEL_WIDTH_40: 1846 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, band, ntx, ch, 1847 pri_ch); 1848 break; 1849 case RTW89_CHANNEL_WIDTH_80: 1850 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, band, ntx, ch, 1851 pri_ch); 1852 break; 1853 case RTW89_CHANNEL_WIDTH_160: 1854 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, band, ntx, ch, 1855 pri_ch); 1856 break; 1857 } 1858 } 1859 1860 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 1861 u8 ru, u8 ntx, u8 ch) 1862 { 1863 const struct rtw89_chip_info *chip = rtwdev->chip; 1864 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1865 u8 regd = rtw89_regd_get(rtwdev, band); 1866 s8 lmt_ru = 0, sar; 1867 1868 switch (band) { 1869 case RTW89_BAND_2G: 1870 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx]; 1871 if (!lmt_ru) 1872 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx] 1873 [RTW89_WW][ch_idx]; 1874 break; 1875 case RTW89_BAND_5G: 1876 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx]; 1877 if (!lmt_ru) 1878 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx] 1879 [RTW89_WW][ch_idx]; 1880 break; 1881 case RTW89_BAND_6G: 1882 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx][regd][ch_idx]; 1883 if (!lmt_ru) 1884 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx] 1885 [RTW89_WW][ch_idx]; 1886 break; 1887 default: 1888 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1889 return 0; 1890 } 1891 1892 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1893 sar = rtw89_query_sar(rtwdev); 1894 1895 return min(lmt_ru, sar); 1896 } 1897 1898 static void 1899 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, 1900 struct rtw89_txpwr_limit_ru *lmt_ru, 1901 u8 band, u8 ntx, u8 ch) 1902 { 1903 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1904 RTW89_RU26, 1905 ntx, ch); 1906 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1907 RTW89_RU52, 1908 ntx, ch); 1909 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1910 RTW89_RU106, 1911 ntx, ch); 1912 } 1913 1914 static void 1915 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, 1916 struct rtw89_txpwr_limit_ru *lmt_ru, 1917 u8 band, u8 ntx, u8 ch) 1918 { 1919 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1920 RTW89_RU26, 1921 ntx, ch - 2); 1922 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1923 RTW89_RU26, 1924 ntx, ch + 2); 1925 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1926 RTW89_RU52, 1927 ntx, ch - 2); 1928 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1929 RTW89_RU52, 1930 ntx, ch + 2); 1931 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1932 RTW89_RU106, 1933 ntx, ch - 2); 1934 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1935 RTW89_RU106, 1936 ntx, ch + 2); 1937 } 1938 1939 static void 1940 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, 1941 struct rtw89_txpwr_limit_ru *lmt_ru, 1942 u8 band, u8 ntx, u8 ch) 1943 { 1944 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1945 RTW89_RU26, 1946 ntx, ch - 6); 1947 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1948 RTW89_RU26, 1949 ntx, ch - 2); 1950 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1951 RTW89_RU26, 1952 ntx, ch + 2); 1953 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1954 RTW89_RU26, 1955 ntx, ch + 6); 1956 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1957 RTW89_RU52, 1958 ntx, ch - 6); 1959 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1960 RTW89_RU52, 1961 ntx, ch - 2); 1962 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1963 RTW89_RU52, 1964 ntx, ch + 2); 1965 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1966 RTW89_RU52, 1967 ntx, ch + 6); 1968 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1969 RTW89_RU106, 1970 ntx, ch - 6); 1971 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1972 RTW89_RU106, 1973 ntx, ch - 2); 1974 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1975 RTW89_RU106, 1976 ntx, ch + 2); 1977 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1978 RTW89_RU106, 1979 ntx, ch + 6); 1980 } 1981 1982 static void 1983 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, 1984 struct rtw89_txpwr_limit_ru *lmt_ru, 1985 u8 band, u8 ntx, u8 ch) 1986 { 1987 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 1988 int i; 1989 1990 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); 1991 for (i = 0; i < RTW89_RU_SEC_NUM; i++) { 1992 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1993 RTW89_RU26, 1994 ntx, 1995 ch + ofst[i]); 1996 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1997 RTW89_RU52, 1998 ntx, 1999 ch + ofst[i]); 2000 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2001 RTW89_RU106, 2002 ntx, 2003 ch + ofst[i]); 2004 } 2005 } 2006 2007 static 2008 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 2009 const struct rtw89_chan *chan, 2010 struct rtw89_txpwr_limit_ru *lmt_ru, 2011 u8 ntx) 2012 { 2013 u8 band = chan->band_type; 2014 u8 ch = chan->channel; 2015 u8 bw = chan->band_width; 2016 2017 memset(lmt_ru, 0, sizeof(*lmt_ru)); 2018 2019 switch (bw) { 2020 case RTW89_CHANNEL_WIDTH_20: 2021 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, band, ntx, 2022 ch); 2023 break; 2024 case RTW89_CHANNEL_WIDTH_40: 2025 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, band, ntx, 2026 ch); 2027 break; 2028 case RTW89_CHANNEL_WIDTH_80: 2029 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, band, ntx, 2030 ch); 2031 break; 2032 case RTW89_CHANNEL_WIDTH_160: 2033 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, band, ntx, 2034 ch); 2035 break; 2036 } 2037 } 2038 2039 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 2040 const struct rtw89_chan *chan, 2041 enum rtw89_phy_idx phy_idx) 2042 { 2043 static const u8 rs[] = { 2044 RTW89_RS_CCK, 2045 RTW89_RS_OFDM, 2046 RTW89_RS_MCS, 2047 RTW89_RS_HEDCM, 2048 }; 2049 struct rtw89_rate_desc cur; 2050 u8 band = chan->band_type; 2051 u8 ch = chan->channel; 2052 u32 addr, val; 2053 s8 v[4] = {}; 2054 u8 i; 2055 2056 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2057 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 2058 2059 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_CCK] % 4); 2060 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_OFDM] % 4); 2061 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_MCS] % 4); 2062 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_HEDCM] % 4); 2063 2064 addr = R_AX_PWR_BY_RATE; 2065 for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) { 2066 for (i = 0; i < ARRAY_SIZE(rs); i++) { 2067 if (cur.nss >= rtw89_rs_nss_max[rs[i]]) 2068 continue; 2069 2070 cur.rs = rs[i]; 2071 for (cur.idx = 0; cur.idx < rtw89_rs_idx_max[rs[i]]; 2072 cur.idx++) { 2073 v[cur.idx % 4] = 2074 rtw89_phy_read_txpwr_byrate(rtwdev, 2075 band, 2076 &cur); 2077 2078 if ((cur.idx + 1) % 4) 2079 continue; 2080 2081 val = FIELD_PREP(GENMASK(7, 0), v[0]) | 2082 FIELD_PREP(GENMASK(15, 8), v[1]) | 2083 FIELD_PREP(GENMASK(23, 16), v[2]) | 2084 FIELD_PREP(GENMASK(31, 24), v[3]); 2085 2086 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 2087 val); 2088 addr += 4; 2089 } 2090 } 2091 } 2092 } 2093 EXPORT_SYMBOL(rtw89_phy_set_txpwr_byrate); 2094 2095 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 2096 const struct rtw89_chan *chan, 2097 enum rtw89_phy_idx phy_idx) 2098 { 2099 struct rtw89_rate_desc desc = { 2100 .nss = RTW89_NSS_1, 2101 .rs = RTW89_RS_OFFSET, 2102 }; 2103 u8 band = chan->band_type; 2104 s8 v[RTW89_RATE_OFFSET_MAX] = {}; 2105 u32 val; 2106 2107 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 2108 2109 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) 2110 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc); 2111 2112 BUILD_BUG_ON(RTW89_RATE_OFFSET_MAX != 5); 2113 val = FIELD_PREP(GENMASK(3, 0), v[0]) | 2114 FIELD_PREP(GENMASK(7, 4), v[1]) | 2115 FIELD_PREP(GENMASK(11, 8), v[2]) | 2116 FIELD_PREP(GENMASK(15, 12), v[3]) | 2117 FIELD_PREP(GENMASK(19, 16), v[4]); 2118 2119 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 2120 GENMASK(19, 0), val); 2121 } 2122 EXPORT_SYMBOL(rtw89_phy_set_txpwr_offset); 2123 2124 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 2125 const struct rtw89_chan *chan, 2126 enum rtw89_phy_idx phy_idx) 2127 { 2128 struct rtw89_txpwr_limit lmt; 2129 u8 ch = chan->channel; 2130 u8 bw = chan->band_width; 2131 const s8 *ptr; 2132 u32 addr, val; 2133 u8 i, j; 2134 2135 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2136 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 2137 2138 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit) != 2139 RTW89_TXPWR_LMT_PAGE_SIZE); 2140 2141 addr = R_AX_PWR_LMT; 2142 for (i = 0; i < RTW89_NTX_NUM; i++) { 2143 rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt, i); 2144 2145 ptr = (s8 *)&lmt; 2146 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE; 2147 j += 4, addr += 4, ptr += 4) { 2148 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2149 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2150 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2151 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2152 2153 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2154 } 2155 } 2156 } 2157 EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit); 2158 2159 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 2160 const struct rtw89_chan *chan, 2161 enum rtw89_phy_idx phy_idx) 2162 { 2163 struct rtw89_txpwr_limit_ru lmt_ru; 2164 u8 ch = chan->channel; 2165 u8 bw = chan->band_width; 2166 const s8 *ptr; 2167 u32 addr, val; 2168 u8 i, j; 2169 2170 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2171 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 2172 2173 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru) != 2174 RTW89_TXPWR_LMT_RU_PAGE_SIZE); 2175 2176 addr = R_AX_PWR_RU_LMT; 2177 for (i = 0; i < RTW89_NTX_NUM; i++) { 2178 rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru, i); 2179 2180 ptr = (s8 *)&lmt_ru; 2181 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE; 2182 j += 4, addr += 4, ptr += 4) { 2183 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2184 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2185 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2186 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2187 2188 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2189 } 2190 } 2191 } 2192 EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit_ru); 2193 2194 struct rtw89_phy_iter_ra_data { 2195 struct rtw89_dev *rtwdev; 2196 struct sk_buff *c2h; 2197 }; 2198 2199 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 2200 { 2201 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 2202 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2203 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2204 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 2205 struct sk_buff *c2h = ra_data->c2h; 2206 u8 mode, rate, bw, giltf, mac_id; 2207 u16 legacy_bitrate; 2208 bool valid; 2209 u8 mcs = 0; 2210 2211 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); 2212 if (mac_id != rtwsta->mac_id) 2213 return; 2214 2215 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); 2216 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); 2217 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); 2218 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); 2219 2220 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2221 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2222 if (!valid) 2223 return; 2224 } 2225 2226 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2227 2228 switch (mode) { 2229 case RTW89_RA_RPT_MODE_LEGACY: 2230 ra_report->txrate.legacy = legacy_bitrate; 2231 break; 2232 case RTW89_RA_RPT_MODE_HT: 2233 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2234 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2235 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2236 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2237 else 2238 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2239 ra_report->txrate.mcs = rate; 2240 if (giltf) 2241 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2242 mcs = ra_report->txrate.mcs & 0x07; 2243 break; 2244 case RTW89_RA_RPT_MODE_VHT: 2245 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2246 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2247 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2248 if (giltf) 2249 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2250 mcs = ra_report->txrate.mcs; 2251 break; 2252 case RTW89_RA_RPT_MODE_HE: 2253 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2254 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2255 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2256 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2257 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2258 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2259 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2260 else 2261 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2262 mcs = ra_report->txrate.mcs; 2263 break; 2264 } 2265 2266 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2267 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2268 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | 2269 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); 2270 ra_report->might_fallback_legacy = mcs <= 2; 2271 sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2272 rtwsta->max_agg_wait = sta->deflink.agg.max_rc_amsdu_len / 1500 - 1; 2273 } 2274 2275 static void 2276 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2277 { 2278 struct rtw89_phy_iter_ra_data ra_data; 2279 2280 ra_data.rtwdev = rtwdev; 2281 ra_data.c2h = c2h; 2282 ieee80211_iterate_stations_atomic(rtwdev->hw, 2283 rtw89_phy_c2h_ra_rpt_iter, 2284 &ra_data); 2285 } 2286 2287 static 2288 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2289 struct sk_buff *c2h, u32 len) = { 2290 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2291 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2292 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2293 }; 2294 2295 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2296 u32 len, u8 class, u8 func) 2297 { 2298 void (*handler)(struct rtw89_dev *rtwdev, 2299 struct sk_buff *c2h, u32 len) = NULL; 2300 2301 switch (class) { 2302 case RTW89_PHY_C2H_CLASS_RA: 2303 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 2304 handler = rtw89_phy_c2h_ra_handler[func]; 2305 break; 2306 case RTW89_PHY_C2H_CLASS_DM: 2307 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY) 2308 return; 2309 fallthrough; 2310 default: 2311 rtw89_info(rtwdev, "c2h class %d not support\n", class); 2312 return; 2313 } 2314 if (!handler) { 2315 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 2316 func); 2317 return; 2318 } 2319 handler(rtwdev, skb, len); 2320 } 2321 2322 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 2323 { 2324 u32 reg_mask; 2325 2326 if (sc_xo) 2327 reg_mask = B_AX_XTAL_SC_XO_MASK; 2328 else 2329 reg_mask = B_AX_XTAL_SC_XI_MASK; 2330 2331 return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask); 2332 } 2333 2334 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 2335 u8 val) 2336 { 2337 u32 reg_mask; 2338 2339 if (sc_xo) 2340 reg_mask = B_AX_XTAL_SC_XO_MASK; 2341 else 2342 reg_mask = B_AX_XTAL_SC_XI_MASK; 2343 2344 rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val); 2345 } 2346 2347 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 2348 u8 crystal_cap, bool force) 2349 { 2350 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2351 const struct rtw89_chip_info *chip = rtwdev->chip; 2352 u8 sc_xi_val, sc_xo_val; 2353 2354 if (!force && cfo->crystal_cap == crystal_cap) 2355 return; 2356 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 2357 if (chip->chip_id == RTL8852A) { 2358 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 2359 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 2360 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 2361 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 2362 } else { 2363 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 2364 crystal_cap, XTAL_SC_XO_MASK); 2365 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 2366 crystal_cap, XTAL_SC_XI_MASK); 2367 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 2368 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 2369 } 2370 cfo->crystal_cap = sc_xi_val; 2371 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 2372 2373 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 2374 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 2375 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 2376 cfo->x_cap_ofst); 2377 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 2378 } 2379 2380 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 2381 { 2382 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2383 u8 cap; 2384 2385 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 2386 cfo->is_adjust = false; 2387 if (cfo->crystal_cap == cfo->def_x_cap) 2388 return; 2389 cap = cfo->crystal_cap; 2390 cap += (cap > cfo->def_x_cap ? -1 : 1); 2391 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 2392 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2393 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 2394 cfo->def_x_cap); 2395 } 2396 2397 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 2398 { 2399 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 2400 bool is_linked = rtwdev->total_sta_assoc > 0; 2401 s32 cfo_avg_312; 2402 s32 dcfo_comp_val; 2403 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 2404 int sign; 2405 2406 if (!is_linked) { 2407 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 2408 is_linked); 2409 return; 2410 } 2411 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 2412 if (curr_cfo == 0) 2413 return; 2414 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 2415 sign = curr_cfo > 0 ? 1 : -1; 2416 cfo_avg_312 = (curr_cfo << dcfo_comp_sft) / 5 + sign * dcfo_comp_val; 2417 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312); 2418 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2419 cfo_avg_312 = -cfo_avg_312; 2420 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 2421 cfo_avg_312); 2422 } 2423 2424 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 2425 { 2426 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 2427 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 2428 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 2429 } 2430 2431 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 2432 { 2433 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2434 struct rtw89_efuse *efuse = &rtwdev->efuse; 2435 2436 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 2437 cfo->crystal_cap = cfo->crystal_cap_default; 2438 cfo->def_x_cap = cfo->crystal_cap; 2439 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 2440 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 2441 cfo->is_adjust = false; 2442 cfo->divergence_lock_en = false; 2443 cfo->x_cap_ofst = 0; 2444 cfo->lock_cnt = 0; 2445 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 2446 cfo->apply_compensation = false; 2447 cfo->residual_cfo_acc = 0; 2448 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 2449 cfo->crystal_cap_default); 2450 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 2451 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 2452 rtw89_dcfo_comp_init(rtwdev); 2453 cfo->cfo_timer_ms = 2000; 2454 cfo->cfo_trig_by_timer_en = false; 2455 cfo->phy_cfo_trk_cnt = 0; 2456 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2457 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 2458 } 2459 2460 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 2461 s32 curr_cfo) 2462 { 2463 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2464 s8 crystal_cap = cfo->crystal_cap; 2465 s32 cfo_abs = abs(curr_cfo); 2466 int sign; 2467 2468 if (!cfo->is_adjust) { 2469 if (cfo_abs > CFO_TRK_ENABLE_TH) 2470 cfo->is_adjust = true; 2471 } else { 2472 if (cfo_abs < CFO_TRK_STOP_TH) 2473 cfo->is_adjust = false; 2474 } 2475 if (!cfo->is_adjust) { 2476 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 2477 return; 2478 } 2479 sign = curr_cfo > 0 ? 1 : -1; 2480 if (cfo_abs > CFO_TRK_STOP_TH_4) 2481 crystal_cap += 7 * sign; 2482 else if (cfo_abs > CFO_TRK_STOP_TH_3) 2483 crystal_cap += 5 * sign; 2484 else if (cfo_abs > CFO_TRK_STOP_TH_2) 2485 crystal_cap += 3 * sign; 2486 else if (cfo_abs > CFO_TRK_STOP_TH_1) 2487 crystal_cap += 1 * sign; 2488 else 2489 return; 2490 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 2491 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2492 "X_cap{Curr,Default}={0x%x,0x%x}\n", 2493 cfo->crystal_cap, cfo->def_x_cap); 2494 } 2495 2496 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 2497 { 2498 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2499 s32 cfo_khz_all = 0; 2500 s32 cfo_cnt_all = 0; 2501 s32 cfo_all_avg = 0; 2502 u8 i; 2503 2504 if (rtwdev->total_sta_assoc != 1) 2505 return 0; 2506 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 2507 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2508 if (cfo->cfo_cnt[i] == 0) 2509 continue; 2510 cfo_khz_all += cfo->cfo_tail[i]; 2511 cfo_cnt_all += cfo->cfo_cnt[i]; 2512 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 2513 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2514 } 2515 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2516 "CFO track for macid = %d\n", i); 2517 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2518 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 2519 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 2520 return cfo_all_avg; 2521 } 2522 2523 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 2524 { 2525 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2526 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2527 s32 target_cfo = 0; 2528 s32 cfo_khz_all = 0; 2529 s32 cfo_khz_all_tp_wgt = 0; 2530 s32 cfo_avg = 0; 2531 s32 max_cfo_lb = BIT(31); 2532 s32 min_cfo_ub = GENMASK(30, 0); 2533 u16 cfo_cnt_all = 0; 2534 u8 active_entry_cnt = 0; 2535 u8 sta_cnt = 0; 2536 u32 tp_all = 0; 2537 u8 i; 2538 u8 cfo_tol = 0; 2539 2540 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 2541 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 2542 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 2543 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2544 if (cfo->cfo_cnt[i] == 0) 2545 continue; 2546 cfo_khz_all += cfo->cfo_tail[i]; 2547 cfo_cnt_all += cfo->cfo_cnt[i]; 2548 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 2549 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2550 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 2551 cfo_khz_all, cfo_cnt_all, cfo_avg); 2552 target_cfo = cfo_avg; 2553 } 2554 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 2555 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 2556 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2557 if (cfo->cfo_cnt[i] == 0) 2558 continue; 2559 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2560 (s32)cfo->cfo_cnt[i]); 2561 cfo_khz_all += cfo->cfo_avg[i]; 2562 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2563 "Macid=%d, cfo_avg=%d\n", i, 2564 cfo->cfo_avg[i]); 2565 } 2566 sta_cnt = rtwdev->total_sta_assoc; 2567 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 2568 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2569 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 2570 cfo_khz_all, sta_cnt, cfo_avg); 2571 target_cfo = cfo_avg; 2572 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 2573 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 2574 cfo_tol = cfo->sta_cfo_tolerance; 2575 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2576 sta_cnt++; 2577 if (cfo->cfo_cnt[i] != 0) { 2578 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2579 (s32)cfo->cfo_cnt[i]); 2580 active_entry_cnt++; 2581 } else { 2582 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 2583 } 2584 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 2585 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 2586 cfo_khz_all += cfo->cfo_avg[i]; 2587 /* need tp for each entry */ 2588 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2589 "[%d] cfo_avg=%d, tp=tbd\n", 2590 i, cfo->cfo_avg[i]); 2591 if (sta_cnt >= rtwdev->total_sta_assoc) 2592 break; 2593 } 2594 tp_all = stats->rx_throughput; /* need tp for each entry */ 2595 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 2596 2597 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 2598 sta_cnt); 2599 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 2600 active_entry_cnt); 2601 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2602 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 2603 cfo_khz_all_tp_wgt, cfo_avg); 2604 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 2605 max_cfo_lb, min_cfo_ub); 2606 if (max_cfo_lb <= min_cfo_ub) { 2607 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2608 "cfo win_size=%d\n", 2609 min_cfo_ub - max_cfo_lb); 2610 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 2611 } else { 2612 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2613 "No intersection of cfo tolerance windows\n"); 2614 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 2615 } 2616 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 2617 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2618 } 2619 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 2620 return target_cfo; 2621 } 2622 2623 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 2624 { 2625 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2626 2627 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 2628 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 2629 cfo->packet_count = 0; 2630 cfo->packet_count_pre = 0; 2631 cfo->cfo_avg_pre = 0; 2632 } 2633 2634 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 2635 { 2636 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2637 s32 new_cfo = 0; 2638 bool x_cap_update = false; 2639 u8 pre_x_cap = cfo->crystal_cap; 2640 2641 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 2642 rtwdev->total_sta_assoc); 2643 if (rtwdev->total_sta_assoc == 0) { 2644 rtw89_phy_cfo_reset(rtwdev); 2645 return; 2646 } 2647 if (cfo->packet_count == 0) { 2648 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 2649 return; 2650 } 2651 if (cfo->packet_count == cfo->packet_count_pre) { 2652 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 2653 return; 2654 } 2655 if (rtwdev->total_sta_assoc == 1) 2656 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 2657 else 2658 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 2659 if (new_cfo == 0) { 2660 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2661 return; 2662 } 2663 if (cfo->divergence_lock_en) { 2664 cfo->lock_cnt++; 2665 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 2666 cfo->divergence_lock_en = false; 2667 cfo->lock_cnt = 0; 2668 } else { 2669 rtw89_phy_cfo_reset(rtwdev); 2670 } 2671 return; 2672 } 2673 if (cfo->crystal_cap >= cfo->x_cap_ub || 2674 cfo->crystal_cap <= cfo->x_cap_lb) { 2675 cfo->divergence_lock_en = true; 2676 rtw89_phy_cfo_reset(rtwdev); 2677 return; 2678 } 2679 2680 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 2681 cfo->cfo_avg_pre = new_cfo; 2682 x_cap_update = cfo->crystal_cap != pre_x_cap; 2683 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 2684 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 2685 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 2686 cfo->x_cap_ofst); 2687 if (x_cap_update) { 2688 if (new_cfo > 0) 2689 new_cfo -= CFO_SW_COMP_FINE_TUNE; 2690 else 2691 new_cfo += CFO_SW_COMP_FINE_TUNE; 2692 } 2693 rtw89_dcfo_comp(rtwdev, new_cfo); 2694 rtw89_phy_cfo_statistics_reset(rtwdev); 2695 } 2696 2697 void rtw89_phy_cfo_track_work(struct work_struct *work) 2698 { 2699 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2700 cfo_track_work.work); 2701 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2702 2703 mutex_lock(&rtwdev->mutex); 2704 if (!cfo->cfo_trig_by_timer_en) 2705 goto out; 2706 rtw89_leave_ps_mode(rtwdev); 2707 rtw89_phy_cfo_dm(rtwdev); 2708 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2709 msecs_to_jiffies(cfo->cfo_timer_ms)); 2710 out: 2711 mutex_unlock(&rtwdev->mutex); 2712 } 2713 2714 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 2715 { 2716 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2717 2718 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2719 msecs_to_jiffies(cfo->cfo_timer_ms)); 2720 } 2721 2722 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 2723 { 2724 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2725 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2726 bool is_ul_ofdma = false, ofdma_acc_en = false; 2727 2728 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 2729 is_ul_ofdma = true; 2730 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 2731 is_ul_ofdma) 2732 ofdma_acc_en = true; 2733 2734 switch (cfo->phy_cfo_status) { 2735 case RTW89_PHY_DCFO_STATE_NORMAL: 2736 if (stats->tx_throughput >= CFO_TP_UPPER) { 2737 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 2738 cfo->cfo_trig_by_timer_en = true; 2739 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 2740 rtw89_phy_cfo_start_work(rtwdev); 2741 } 2742 break; 2743 case RTW89_PHY_DCFO_STATE_ENHANCE: 2744 if (stats->tx_throughput <= CFO_TP_LOWER) 2745 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2746 else if (ofdma_acc_en && 2747 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 2748 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 2749 else 2750 cfo->phy_cfo_trk_cnt++; 2751 2752 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 2753 cfo->phy_cfo_trk_cnt = 0; 2754 cfo->cfo_trig_by_timer_en = false; 2755 } 2756 break; 2757 case RTW89_PHY_DCFO_STATE_HOLD: 2758 if (stats->tx_throughput <= CFO_TP_LOWER) { 2759 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2760 cfo->phy_cfo_trk_cnt = 0; 2761 cfo->cfo_trig_by_timer_en = false; 2762 } else { 2763 cfo->phy_cfo_trk_cnt++; 2764 } 2765 break; 2766 default: 2767 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2768 cfo->phy_cfo_trk_cnt = 0; 2769 break; 2770 } 2771 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2772 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 2773 stats->tx_throughput, cfo->phy_cfo_status, 2774 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 2775 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 2776 if (cfo->cfo_trig_by_timer_en) 2777 return; 2778 rtw89_phy_cfo_dm(rtwdev); 2779 } 2780 2781 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 2782 struct rtw89_rx_phy_ppdu *phy_ppdu) 2783 { 2784 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2785 u8 macid = phy_ppdu->mac_id; 2786 2787 if (macid >= CFO_TRACK_MAX_USER) { 2788 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 2789 return; 2790 } 2791 2792 cfo->cfo_tail[macid] += cfo_val; 2793 cfo->cfo_cnt[macid]++; 2794 cfo->packet_count++; 2795 } 2796 2797 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 2798 { 2799 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2800 int i; 2801 u8 th; 2802 2803 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 2804 th = rtw89_chip_get_thermal(rtwdev, i); 2805 if (th) 2806 ewma_thermal_add(&phystat->avg_thermal[i], th); 2807 2808 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2809 "path(%d) thermal cur=%u avg=%ld", i, th, 2810 ewma_thermal_read(&phystat->avg_thermal[i])); 2811 } 2812 } 2813 2814 struct rtw89_phy_iter_rssi_data { 2815 struct rtw89_dev *rtwdev; 2816 struct rtw89_phy_ch_info *ch_info; 2817 bool rssi_changed; 2818 }; 2819 2820 static void rtw89_phy_stat_rssi_update_iter(void *data, 2821 struct ieee80211_sta *sta) 2822 { 2823 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2824 struct rtw89_phy_iter_rssi_data *rssi_data = 2825 (struct rtw89_phy_iter_rssi_data *)data; 2826 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 2827 unsigned long rssi_curr; 2828 2829 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 2830 2831 if (rssi_curr < ch_info->rssi_min) { 2832 ch_info->rssi_min = rssi_curr; 2833 ch_info->rssi_min_macid = rtwsta->mac_id; 2834 } 2835 2836 if (rtwsta->prev_rssi == 0) { 2837 rtwsta->prev_rssi = rssi_curr; 2838 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 2839 rtwsta->prev_rssi = rssi_curr; 2840 rssi_data->rssi_changed = true; 2841 } 2842 } 2843 2844 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 2845 { 2846 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 2847 2848 rssi_data.rtwdev = rtwdev; 2849 rssi_data.ch_info = &rtwdev->ch_info; 2850 rssi_data.ch_info->rssi_min = U8_MAX; 2851 ieee80211_iterate_stations_atomic(rtwdev->hw, 2852 rtw89_phy_stat_rssi_update_iter, 2853 &rssi_data); 2854 if (rssi_data.rssi_changed) 2855 rtw89_btc_ntfy_wl_sta(rtwdev); 2856 } 2857 2858 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 2859 { 2860 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2861 int i; 2862 2863 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2864 ewma_thermal_init(&phystat->avg_thermal[i]); 2865 2866 rtw89_phy_stat_thermal_update(rtwdev); 2867 2868 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2869 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 2870 } 2871 2872 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 2873 { 2874 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2875 2876 rtw89_phy_stat_thermal_update(rtwdev); 2877 rtw89_phy_stat_rssi_update(rtwdev); 2878 2879 phystat->last_pkt_stat = phystat->cur_pkt_stat; 2880 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2881 } 2882 2883 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 2884 { 2885 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2886 2887 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2888 } 2889 2890 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 2891 { 2892 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2893 2894 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2895 } 2896 2897 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 2898 { 2899 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2900 2901 env->ccx_manual_ctrl = false; 2902 env->ccx_ongoing = false; 2903 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2904 env->ccx_rpt_stamp = 0; 2905 env->ccx_period = 0; 2906 env->ccx_unit_idx = RTW89_CCX_32_US; 2907 env->ccx_trigger_time = 0; 2908 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; 2909 2910 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); 2911 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); 2912 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2913 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, 2914 RTW89_CCX_EDCCA_BW20_0); 2915 } 2916 2917 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 2918 u16 score) 2919 { 2920 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2921 u32 numer = 0; 2922 u16 ret = 0; 2923 2924 numer = report * score + (env->ccx_period >> 1); 2925 if (env->ccx_period) 2926 ret = numer / env->ccx_period; 2927 2928 return ret >= score ? score - 1 : ret; 2929 } 2930 2931 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 2932 u16 time_ms, u32 *period, 2933 u32 *unit_idx) 2934 { 2935 u32 idx; 2936 u8 quotient; 2937 2938 if (time_ms >= CCX_MAX_PERIOD) 2939 time_ms = CCX_MAX_PERIOD; 2940 2941 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 2942 2943 if (quotient < 4) 2944 idx = RTW89_CCX_4_US; 2945 else if (quotient < 8) 2946 idx = RTW89_CCX_8_US; 2947 else if (quotient < 16) 2948 idx = RTW89_CCX_16_US; 2949 else 2950 idx = RTW89_CCX_32_US; 2951 2952 *unit_idx = idx; 2953 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 2954 2955 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2956 "[Trigger Time] period:%d, unit_idx:%d\n", 2957 *period, *unit_idx); 2958 } 2959 2960 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 2961 { 2962 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2963 2964 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2965 "lv:(%d)->(0)\n", env->ccx_rac_lv); 2966 2967 env->ccx_ongoing = false; 2968 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2969 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2970 } 2971 2972 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 2973 struct rtw89_ccx_para_info *para) 2974 { 2975 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2976 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 2977 u8 i = 0; 2978 u16 *ifs_th_l = env->ifs_clm_th_l; 2979 u16 *ifs_th_h = env->ifs_clm_th_h; 2980 u32 ifs_th0_us = 0, ifs_th_times = 0; 2981 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 2982 2983 if (!is_update) 2984 goto ifs_update_finished; 2985 2986 switch (para->ifs_clm_app) { 2987 case RTW89_IFS_CLM_INIT: 2988 case RTW89_IFS_CLM_BACKGROUND: 2989 case RTW89_IFS_CLM_ACS: 2990 case RTW89_IFS_CLM_DBG: 2991 case RTW89_IFS_CLM_DIG: 2992 case RTW89_IFS_CLM_TDMA_DIG: 2993 ifs_th0_us = IFS_CLM_TH0_UPPER; 2994 ifs_th_times = IFS_CLM_TH_MUL; 2995 break; 2996 case RTW89_IFS_CLM_DBG_MANUAL: 2997 ifs_th0_us = para->ifs_clm_manual_th0; 2998 ifs_th_times = para->ifs_clm_manual_th_times; 2999 break; 3000 default: 3001 break; 3002 } 3003 3004 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 3005 * low[i] = high[i-1] + 1 3006 * high[i] = high[i-1] * ifs_th_times 3007 */ 3008 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 3009 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 3010 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 3011 ifs_th0_us); 3012 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 3013 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 3014 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 3015 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 3016 } 3017 3018 ifs_update_finished: 3019 if (!is_update) 3020 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3021 "No need to update IFS_TH\n"); 3022 3023 return is_update; 3024 } 3025 3026 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 3027 { 3028 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3029 u8 i = 0; 3030 3031 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, 3032 env->ifs_clm_th_l[0]); 3033 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, 3034 env->ifs_clm_th_l[1]); 3035 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, 3036 env->ifs_clm_th_l[2]); 3037 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, 3038 env->ifs_clm_th_l[3]); 3039 3040 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, 3041 env->ifs_clm_th_h[0]); 3042 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, 3043 env->ifs_clm_th_h[1]); 3044 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, 3045 env->ifs_clm_th_h[2]); 3046 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, 3047 env->ifs_clm_th_h[3]); 3048 3049 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3050 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3051 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 3052 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 3053 } 3054 3055 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 3056 { 3057 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3058 struct rtw89_ccx_para_info para = {0}; 3059 3060 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3061 env->ifs_clm_mntr_time = 0; 3062 3063 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 3064 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 3065 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3066 3067 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, 3068 true); 3069 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); 3070 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); 3071 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); 3072 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); 3073 } 3074 3075 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 3076 enum rtw89_env_racing_lv level) 3077 { 3078 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3079 int ret = 0; 3080 3081 if (level >= RTW89_RAC_MAX_NUM) { 3082 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3083 "[WARNING] Wrong LV=%d\n", level); 3084 return -EINVAL; 3085 } 3086 3087 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3088 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 3089 env->ccx_rac_lv, level); 3090 3091 if (env->ccx_ongoing) { 3092 if (level <= env->ccx_rac_lv) 3093 ret = -EINVAL; 3094 else 3095 env->ccx_ongoing = false; 3096 } 3097 3098 if (ret == 0) 3099 env->ccx_rac_lv = level; 3100 3101 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 3102 !ret); 3103 3104 return ret; 3105 } 3106 3107 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 3108 { 3109 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3110 3111 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); 3112 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); 3113 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); 3114 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 3115 3116 env->ccx_rpt_stamp++; 3117 env->ccx_ongoing = true; 3118 } 3119 3120 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 3121 { 3122 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3123 u8 i = 0; 3124 u32 res = 0; 3125 3126 env->ifs_clm_tx_ratio = 3127 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 3128 env->ifs_clm_edcca_excl_cca_ratio = 3129 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 3130 PERCENT); 3131 env->ifs_clm_cck_fa_ratio = 3132 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 3133 env->ifs_clm_ofdm_fa_ratio = 3134 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 3135 env->ifs_clm_cck_cca_excl_fa_ratio = 3136 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 3137 PERCENT); 3138 env->ifs_clm_ofdm_cca_excl_fa_ratio = 3139 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 3140 PERCENT); 3141 env->ifs_clm_cck_fa_permil = 3142 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 3143 env->ifs_clm_ofdm_fa_permil = 3144 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 3145 3146 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 3147 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 3148 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 3149 } else { 3150 env->ifs_clm_ifs_avg[i] = 3151 rtw89_phy_ccx_idx_to_us(rtwdev, 3152 env->ifs_clm_avg[i]); 3153 } 3154 3155 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 3156 res += env->ifs_clm_his[i] >> 1; 3157 if (env->ifs_clm_his[i]) 3158 res /= env->ifs_clm_his[i]; 3159 else 3160 res = 0; 3161 env->ifs_clm_cca_avg[i] = res; 3162 } 3163 3164 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3165 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3166 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 3167 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3168 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 3169 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 3170 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3171 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 3172 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 3173 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3174 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 3175 env->ifs_clm_cck_cca_excl_fa_ratio, 3176 env->ifs_clm_ofdm_cca_excl_fa_ratio); 3177 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3178 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 3179 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3180 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 3181 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 3182 env->ifs_clm_cca_avg[i]); 3183 } 3184 3185 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 3186 { 3187 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3188 u8 i = 0; 3189 3190 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { 3191 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3192 "Get IFS_CLM report Fail\n"); 3193 return false; 3194 } 3195 3196 env->ifs_clm_tx = 3197 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 3198 B_IFS_CLM_TX_CNT_MSK); 3199 env->ifs_clm_edcca_excl_cca = 3200 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 3201 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); 3202 env->ifs_clm_cckcca_excl_fa = 3203 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3204 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); 3205 env->ifs_clm_ofdmcca_excl_fa = 3206 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3207 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); 3208 env->ifs_clm_cckfa = 3209 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3210 B_IFS_CLM_CCK_FA_MSK); 3211 env->ifs_clm_ofdmfa = 3212 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3213 B_IFS_CLM_OFDM_FA_MSK); 3214 3215 env->ifs_clm_his[0] = 3216 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); 3217 env->ifs_clm_his[1] = 3218 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); 3219 env->ifs_clm_his[2] = 3220 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); 3221 env->ifs_clm_his[3] = 3222 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); 3223 3224 env->ifs_clm_avg[0] = 3225 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); 3226 env->ifs_clm_avg[1] = 3227 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); 3228 env->ifs_clm_avg[2] = 3229 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); 3230 env->ifs_clm_avg[3] = 3231 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); 3232 3233 env->ifs_clm_cca[0] = 3234 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); 3235 env->ifs_clm_cca[1] = 3236 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); 3237 env->ifs_clm_cca[2] = 3238 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); 3239 env->ifs_clm_cca[3] = 3240 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); 3241 3242 env->ifs_clm_total_ifs = 3243 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); 3244 3245 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 3246 env->ifs_clm_total_ifs); 3247 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3248 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3249 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 3250 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3251 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 3252 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 3253 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3254 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 3255 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 3256 3257 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 3258 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3259 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3260 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 3261 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 3262 3263 rtw89_phy_ifs_clm_get_utility(rtwdev); 3264 3265 return true; 3266 } 3267 3268 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 3269 struct rtw89_ccx_para_info *para) 3270 { 3271 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3272 u32 period = 0; 3273 u32 unit_idx = 0; 3274 3275 if (para->mntr_time == 0) { 3276 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3277 "[WARN] MNTR_TIME is 0\n"); 3278 return -EINVAL; 3279 } 3280 3281 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 3282 return -EINVAL; 3283 3284 if (para->mntr_time != env->ifs_clm_mntr_time) { 3285 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 3286 &period, &unit_idx); 3287 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3288 B_IFS_CLM_PERIOD_MSK, period); 3289 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3290 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); 3291 3292 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3293 "Update IFS-CLM time ((%d)) -> ((%d))\n", 3294 env->ifs_clm_mntr_time, para->mntr_time); 3295 3296 env->ifs_clm_mntr_time = para->mntr_time; 3297 env->ccx_period = (u16)period; 3298 env->ccx_unit_idx = (u8)unit_idx; 3299 } 3300 3301 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 3302 env->ifs_clm_app = para->ifs_clm_app; 3303 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3304 } 3305 3306 return 0; 3307 } 3308 3309 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 3310 { 3311 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3312 struct rtw89_ccx_para_info para = {0}; 3313 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3314 3315 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3316 if (env->ccx_manual_ctrl) { 3317 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3318 "CCX in manual ctrl\n"); 3319 return; 3320 } 3321 3322 /* only ifs_clm for now */ 3323 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 3324 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3325 3326 rtw89_phy_ccx_racing_release(rtwdev); 3327 para.mntr_time = 1900; 3328 para.rac_lv = RTW89_RAC_LV_1; 3329 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3330 3331 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 3332 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3333 if (chk_result) 3334 rtw89_phy_ccx_trigger(rtwdev); 3335 3336 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3337 "get_result=0x%x, chk_result:0x%x\n", 3338 env->ccx_watchdog_result, chk_result); 3339 } 3340 3341 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 3342 { 3343 if (*ie_page > RTW89_PHYSTS_BITMAP_NUM || 3344 *ie_page == RTW89_RSVD_9) 3345 return false; 3346 else if (*ie_page > RTW89_RSVD_9) 3347 *ie_page -= 1; 3348 3349 return true; 3350 } 3351 3352 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 3353 { 3354 static const u8 ie_page_shift = 2; 3355 3356 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 3357 } 3358 3359 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 3360 enum rtw89_phy_status_bitmap ie_page) 3361 { 3362 u32 addr; 3363 3364 if (!rtw89_physts_ie_page_valid(&ie_page)) 3365 return 0; 3366 3367 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3368 3369 return rtw89_phy_read32(rtwdev, addr); 3370 } 3371 3372 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 3373 enum rtw89_phy_status_bitmap ie_page, 3374 u32 val) 3375 { 3376 const struct rtw89_chip_info *chip = rtwdev->chip; 3377 u32 addr; 3378 3379 if (!rtw89_physts_ie_page_valid(&ie_page)) 3380 return; 3381 3382 if (chip->chip_id == RTL8852A) 3383 val &= B_PHY_STS_BITMAP_MSK_52A; 3384 3385 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3386 rtw89_phy_write32(rtwdev, addr, val); 3387 } 3388 3389 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 3390 enum rtw89_phy_status_bitmap bitmap, 3391 enum rtw89_phy_status_ie_type ie, 3392 bool enable) 3393 { 3394 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 3395 3396 if (enable) 3397 val |= BIT(ie); 3398 else 3399 val &= ~BIT(ie); 3400 3401 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 3402 } 3403 3404 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 3405 bool enable, 3406 enum rtw89_phy_idx phy_idx) 3407 { 3408 if (enable) { 3409 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3410 B_STS_DIS_TRIG_BY_FAIL); 3411 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3412 B_STS_DIS_TRIG_BY_BRK); 3413 } else { 3414 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3415 B_STS_DIS_TRIG_BY_FAIL); 3416 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3417 B_STS_DIS_TRIG_BY_BRK); 3418 } 3419 } 3420 3421 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 3422 { 3423 u8 i; 3424 3425 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 3426 3427 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 3428 if (i >= RTW89_CCK_PKT) 3429 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3430 RTW89_PHYSTS_IE09_FTR_0, 3431 true); 3432 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 3433 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 3434 continue; 3435 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3436 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 3437 true); 3438 } 3439 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 3440 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3441 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 3442 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3443 3444 /* force IE01 for channel index, only channel field is valid */ 3445 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 3446 RTW89_PHYSTS_IE01_CMN_OFDM, true); 3447 } 3448 3449 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 3450 { 3451 const struct rtw89_chip_info *chip = rtwdev->chip; 3452 struct rtw89_dig_info *dig = &rtwdev->dig; 3453 const struct rtw89_phy_dig_gain_cfg *cfg; 3454 const char *msg; 3455 u8 i; 3456 s8 gain_base; 3457 s8 *gain_arr; 3458 u32 tmp; 3459 3460 switch (type) { 3461 case RTW89_DIG_GAIN_LNA_G: 3462 gain_arr = dig->lna_gain_g; 3463 gain_base = LNA0_GAIN; 3464 cfg = chip->dig_table->cfg_lna_g; 3465 msg = "lna_gain_g"; 3466 break; 3467 case RTW89_DIG_GAIN_TIA_G: 3468 gain_arr = dig->tia_gain_g; 3469 gain_base = TIA0_GAIN_G; 3470 cfg = chip->dig_table->cfg_tia_g; 3471 msg = "tia_gain_g"; 3472 break; 3473 case RTW89_DIG_GAIN_LNA_A: 3474 gain_arr = dig->lna_gain_a; 3475 gain_base = LNA0_GAIN; 3476 cfg = chip->dig_table->cfg_lna_a; 3477 msg = "lna_gain_a"; 3478 break; 3479 case RTW89_DIG_GAIN_TIA_A: 3480 gain_arr = dig->tia_gain_a; 3481 gain_base = TIA0_GAIN_A; 3482 cfg = chip->dig_table->cfg_tia_a; 3483 msg = "tia_gain_a"; 3484 break; 3485 default: 3486 return; 3487 } 3488 3489 for (i = 0; i < cfg->size; i++) { 3490 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 3491 cfg->table[i].mask); 3492 tmp >>= DIG_GAIN_SHIFT; 3493 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 3494 gain_base += DIG_GAIN; 3495 3496 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 3497 msg, i, gain_arr[i]); 3498 } 3499 } 3500 3501 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 3502 { 3503 struct rtw89_dig_info *dig = &rtwdev->dig; 3504 u32 tmp; 3505 u8 i; 3506 3507 if (!rtwdev->hal.support_igi) 3508 return; 3509 3510 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 3511 B_PATH0_IB_PKPW_MSK); 3512 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 3513 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 3514 B_PATH0_IB_PBK_MSK); 3515 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 3516 dig->ib_pkpwr, dig->ib_pbk); 3517 3518 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 3519 rtw89_phy_dig_read_gain_table(rtwdev, i); 3520 } 3521 3522 static const u8 rssi_nolink = 22; 3523 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 3524 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 3525 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 3526 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 3527 3528 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 3529 { 3530 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 3531 struct rtw89_dig_info *dig = &rtwdev->dig; 3532 bool is_linked = rtwdev->total_sta_assoc > 0; 3533 3534 if (is_linked) { 3535 dig->igi_rssi = ch_info->rssi_min >> 1; 3536 } else { 3537 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 3538 dig->igi_rssi = rssi_nolink; 3539 } 3540 } 3541 3542 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 3543 { 3544 struct rtw89_dig_info *dig = &rtwdev->dig; 3545 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3546 bool is_linked = rtwdev->total_sta_assoc > 0; 3547 const u16 *fa_th_src = NULL; 3548 3549 switch (chan->band_type) { 3550 case RTW89_BAND_2G: 3551 dig->lna_gain = dig->lna_gain_g; 3552 dig->tia_gain = dig->tia_gain_g; 3553 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 3554 dig->force_gaincode_idx_en = false; 3555 dig->dyn_pd_th_en = true; 3556 break; 3557 case RTW89_BAND_5G: 3558 default: 3559 dig->lna_gain = dig->lna_gain_a; 3560 dig->tia_gain = dig->tia_gain_a; 3561 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 3562 dig->force_gaincode_idx_en = true; 3563 dig->dyn_pd_th_en = true; 3564 break; 3565 } 3566 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 3567 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 3568 } 3569 3570 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 3571 static const u8 igi_max_performance_mode = 0x5a; 3572 static const u8 dynamic_pd_threshold_max; 3573 3574 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 3575 { 3576 struct rtw89_dig_info *dig = &rtwdev->dig; 3577 3578 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 3579 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 3580 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 3581 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 3582 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 3583 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 3584 3585 dig->dyn_igi_max = igi_max_performance_mode; 3586 dig->dyn_igi_min = dynamic_igi_min; 3587 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 3588 dig->pd_low_th_ofst = pd_low_th_offset; 3589 dig->is_linked_pre = false; 3590 } 3591 3592 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 3593 { 3594 rtw89_phy_dig_update_gain_para(rtwdev); 3595 rtw89_phy_dig_reset(rtwdev); 3596 } 3597 3598 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3599 { 3600 struct rtw89_dig_info *dig = &rtwdev->dig; 3601 u8 lna_idx; 3602 3603 if (rssi < dig->igi_rssi_th[0]) 3604 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 3605 else if (rssi < dig->igi_rssi_th[1]) 3606 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 3607 else if (rssi < dig->igi_rssi_th[2]) 3608 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 3609 else if (rssi < dig->igi_rssi_th[3]) 3610 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 3611 else if (rssi < dig->igi_rssi_th[4]) 3612 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 3613 else 3614 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 3615 3616 return lna_idx; 3617 } 3618 3619 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3620 { 3621 struct rtw89_dig_info *dig = &rtwdev->dig; 3622 u8 tia_idx; 3623 3624 if (rssi < dig->igi_rssi_th[0]) 3625 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 3626 else 3627 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 3628 3629 return tia_idx; 3630 } 3631 3632 #define IB_PBK_BASE 110 3633 #define WB_RSSI_BASE 10 3634 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3635 struct rtw89_agc_gaincode_set *set) 3636 { 3637 struct rtw89_dig_info *dig = &rtwdev->dig; 3638 s8 lna_gain = dig->lna_gain[set->lna_idx]; 3639 s8 tia_gain = dig->tia_gain[set->tia_idx]; 3640 s32 wb_rssi = rssi + lna_gain + tia_gain; 3641 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 3642 u8 rxb_idx; 3643 3644 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 3645 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 3646 3647 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 3648 wb_rssi, rxb_idx_tmp); 3649 3650 return rxb_idx; 3651 } 3652 3653 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3654 struct rtw89_agc_gaincode_set *set) 3655 { 3656 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 3657 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 3658 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 3659 3660 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3661 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 3662 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 3663 } 3664 3665 #define IGI_OFFSET_MAX 25 3666 #define IGI_OFFSET_MUL 2 3667 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 3668 { 3669 struct rtw89_dig_info *dig = &rtwdev->dig; 3670 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3671 enum rtw89_dig_noisy_level noisy_lv; 3672 u8 igi_offset = dig->fa_rssi_ofst; 3673 u16 fa_ratio = 0; 3674 3675 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 3676 3677 if (fa_ratio < dig->fa_th[0]) 3678 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 3679 else if (fa_ratio < dig->fa_th[1]) 3680 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 3681 else if (fa_ratio < dig->fa_th[2]) 3682 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 3683 else if (fa_ratio < dig->fa_th[3]) 3684 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 3685 else 3686 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 3687 3688 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 3689 igi_offset = 0; 3690 else 3691 igi_offset += noisy_lv * IGI_OFFSET_MUL; 3692 3693 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 3694 dig->fa_rssi_ofst = igi_offset; 3695 3696 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3697 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 3698 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 3699 3700 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3701 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 3702 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 3703 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 3704 noisy_lv, igi_offset); 3705 } 3706 3707 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 3708 { 3709 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3710 3711 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr, 3712 dig_regs->p0_lna_init.mask, lna_idx); 3713 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr, 3714 dig_regs->p1_lna_init.mask, lna_idx); 3715 } 3716 3717 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 3718 { 3719 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3720 3721 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr, 3722 dig_regs->p0_tia_init.mask, tia_idx); 3723 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr, 3724 dig_regs->p1_tia_init.mask, tia_idx); 3725 } 3726 3727 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 3728 { 3729 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3730 3731 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr, 3732 dig_regs->p0_rxb_init.mask, rxb_idx); 3733 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr, 3734 dig_regs->p1_rxb_init.mask, rxb_idx); 3735 } 3736 3737 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 3738 const struct rtw89_agc_gaincode_set set) 3739 { 3740 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 3741 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 3742 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 3743 3744 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 3745 set.lna_idx, set.tia_idx, set.rxb_idx); 3746 } 3747 3748 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 3749 bool enable) 3750 { 3751 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3752 3753 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 3754 dig_regs->p0_p20_pagcugc_en.mask, enable); 3755 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 3756 dig_regs->p0_s20_pagcugc_en.mask, enable); 3757 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 3758 dig_regs->p1_p20_pagcugc_en.mask, enable); 3759 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 3760 dig_regs->p1_s20_pagcugc_en.mask, enable); 3761 3762 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 3763 } 3764 3765 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 3766 { 3767 struct rtw89_dig_info *dig = &rtwdev->dig; 3768 3769 if (!rtwdev->hal.support_igi) 3770 return; 3771 3772 if (dig->force_gaincode_idx_en) { 3773 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3774 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3775 "Force gaincode index enabled.\n"); 3776 } else { 3777 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 3778 &dig->cur_gaincode); 3779 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 3780 } 3781 } 3782 3783 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 3784 bool enable) 3785 { 3786 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3787 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3788 enum rtw89_bandwidth cbw = chan->band_width; 3789 struct rtw89_dig_info *dig = &rtwdev->dig; 3790 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 3791 u8 ofdm_cca_th; 3792 s8 cck_cca_th; 3793 u32 pd_val = 0; 3794 3795 under_region += PD_TH_SB_FLTR_CMP_VAL; 3796 3797 switch (cbw) { 3798 case RTW89_CHANNEL_WIDTH_40: 3799 under_region += PD_TH_BW40_CMP_VAL; 3800 break; 3801 case RTW89_CHANNEL_WIDTH_80: 3802 under_region += PD_TH_BW80_CMP_VAL; 3803 break; 3804 case RTW89_CHANNEL_WIDTH_160: 3805 under_region += PD_TH_BW160_CMP_VAL; 3806 break; 3807 case RTW89_CHANNEL_WIDTH_20: 3808 fallthrough; 3809 default: 3810 under_region += PD_TH_BW20_CMP_VAL; 3811 break; 3812 } 3813 3814 dig->dyn_pd_th_max = dig->igi_rssi; 3815 3816 final_rssi = min_t(u8, rssi, dig->igi_rssi); 3817 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 3818 PD_TH_MAX_RSSI + under_region); 3819 3820 if (enable) { 3821 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 3822 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3823 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 3824 final_rssi, ofdm_cca_th, under_region, pd_val); 3825 } else { 3826 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3827 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 3828 } 3829 3830 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 3831 dig_regs->pd_lower_bound_mask, pd_val); 3832 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 3833 dig_regs->pd_spatial_reuse_en, enable); 3834 3835 if (!rtwdev->hal.support_cckpd) 3836 return; 3837 3838 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 3839 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 3840 3841 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3842 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 3843 final_rssi, cck_cca_th, under_region, pd_val); 3844 3845 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1, 3846 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable); 3847 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1, 3848 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val); 3849 } 3850 3851 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 3852 { 3853 struct rtw89_dig_info *dig = &rtwdev->dig; 3854 3855 dig->bypass_dig = false; 3856 rtw89_phy_dig_para_reset(rtwdev); 3857 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3858 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 3859 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3860 rtw89_phy_dig_update_para(rtwdev); 3861 } 3862 3863 #define IGI_RSSI_MIN 10 3864 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 3865 { 3866 struct rtw89_dig_info *dig = &rtwdev->dig; 3867 bool is_linked = rtwdev->total_sta_assoc > 0; 3868 3869 if (unlikely(dig->bypass_dig)) { 3870 dig->bypass_dig = false; 3871 return; 3872 } 3873 3874 if (!dig->is_linked_pre && is_linked) { 3875 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 3876 rtw89_phy_dig_update_para(rtwdev); 3877 } else if (dig->is_linked_pre && !is_linked) { 3878 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 3879 rtw89_phy_dig_update_para(rtwdev); 3880 } 3881 dig->is_linked_pre = is_linked; 3882 3883 rtw89_phy_dig_igi_offset_by_env(rtwdev); 3884 rtw89_phy_dig_update_rssi_info(rtwdev); 3885 3886 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 3887 dig->igi_rssi - IGI_RSSI_MIN : 0; 3888 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 3889 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 3890 3891 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 3892 dig->dyn_igi_max); 3893 3894 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3895 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 3896 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 3897 dig->igi_fa_rssi); 3898 3899 rtw89_phy_dig_config_igi(rtwdev); 3900 3901 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 3902 3903 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 3904 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 3905 else 3906 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3907 } 3908 3909 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 3910 { 3911 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3912 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3913 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 3914 struct rtw89_hal *hal = &rtwdev->hal; 3915 bool *done = data; 3916 u8 rssi_a, rssi_b; 3917 u32 candidate; 3918 3919 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || sta->tdls) 3920 return; 3921 3922 if (*done) 3923 return; 3924 3925 *done = true; 3926 3927 rssi_a = ewma_rssi_read(&rtwsta->rssi[RF_PATH_A]); 3928 rssi_b = ewma_rssi_read(&rtwsta->rssi[RF_PATH_B]); 3929 3930 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 3931 candidate = RF_A; 3932 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 3933 candidate = RF_B; 3934 else 3935 return; 3936 3937 if (hal->antenna_tx == candidate) 3938 return; 3939 3940 hal->antenna_tx = candidate; 3941 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta); 3942 3943 if (hal->antenna_tx == RF_A) { 3944 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 3945 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 3946 } else if (hal->antenna_tx == RF_B) { 3947 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 3948 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 3949 } 3950 } 3951 3952 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 3953 { 3954 struct rtw89_hal *hal = &rtwdev->hal; 3955 bool done = false; 3956 3957 if (!hal->tx_path_diversity) 3958 return; 3959 3960 ieee80211_iterate_stations_atomic(rtwdev->hw, 3961 rtw89_phy_tx_path_div_sta_iter, 3962 &done); 3963 } 3964 3965 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 3966 { 3967 rtw89_phy_ccx_top_setting_init(rtwdev); 3968 rtw89_phy_ifs_clm_setting_init(rtwdev); 3969 } 3970 3971 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 3972 { 3973 const struct rtw89_chip_info *chip = rtwdev->chip; 3974 3975 rtw89_phy_stat_init(rtwdev); 3976 3977 rtw89_chip_bb_sethw(rtwdev); 3978 3979 rtw89_phy_env_monitor_init(rtwdev); 3980 rtw89_physts_parsing_init(rtwdev); 3981 rtw89_phy_dig_init(rtwdev); 3982 rtw89_phy_cfo_init(rtwdev); 3983 3984 rtw89_phy_init_rf_nctl(rtwdev); 3985 rtw89_chip_rfk_init(rtwdev); 3986 rtw89_load_txpwr_table(rtwdev, chip->byr_table); 3987 rtw89_chip_set_txpwr_ctrl(rtwdev); 3988 rtw89_chip_power_trim(rtwdev); 3989 rtw89_chip_cfg_txrx_path(rtwdev); 3990 } 3991 3992 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3993 { 3994 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 3995 u8 bss_color; 3996 3997 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 3998 return; 3999 4000 bss_color = vif->bss_conf.he_bss_color.color; 4001 4002 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1, 4003 phy_idx); 4004 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color, 4005 phy_idx); 4006 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID, 4007 vif->cfg.aid, phy_idx); 4008 } 4009 4010 static void 4011 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4012 { 4013 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 4014 } 4015 4016 static void 4017 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4018 { 4019 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 4020 } 4021 4022 static void 4023 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4024 { 4025 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 4026 } 4027 4028 static void 4029 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4030 { 4031 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 4032 } 4033 4034 static void 4035 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4036 { 4037 udelay(def->data); 4038 } 4039 4040 static void 4041 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 4042 [RTW89_RFK_F_WRF] = _rfk_write_rf, 4043 [RTW89_RFK_F_WM] = _rfk_write32_mask, 4044 [RTW89_RFK_F_WS] = _rfk_write32_set, 4045 [RTW89_RFK_F_WC] = _rfk_write32_clr, 4046 [RTW89_RFK_F_DELAY] = _rfk_delay, 4047 }; 4048 4049 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 4050 4051 void 4052 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 4053 { 4054 const struct rtw89_reg5_def *p = tbl->defs; 4055 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 4056 4057 for (; p < end; p++) 4058 _rfk_handler[p->flag](rtwdev, p); 4059 } 4060 EXPORT_SYMBOL(rtw89_rfk_parser); 4061 4062 #define RTW89_TSSI_FAST_MODE_NUM 4 4063 4064 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 4065 {0xD934, 0xff0000}, 4066 {0xD934, 0xff000000}, 4067 {0xD938, 0xff}, 4068 {0xD934, 0xff00}, 4069 }; 4070 4071 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 4072 {0xD930, 0xff0000}, 4073 {0xD930, 0xff000000}, 4074 {0xD934, 0xff}, 4075 {0xD930, 0xff00}, 4076 }; 4077 4078 static 4079 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 4080 enum rtw89_mac_idx mac_idx, 4081 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 4082 u32 val) 4083 { 4084 const struct rtw89_reg_def *regs; 4085 u32 reg; 4086 int i; 4087 4088 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4089 regs = rtw89_tssi_fastmode_regs_flat; 4090 else 4091 regs = rtw89_tssi_fastmode_regs_level; 4092 4093 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 4094 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 4095 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 4096 } 4097 } 4098 4099 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 4100 {0xD91C, 0xff000000}, 4101 {0xD920, 0xff}, 4102 {0xD920, 0xff00}, 4103 {0xD920, 0xff0000}, 4104 {0xD920, 0xff000000}, 4105 {0xD924, 0xff}, 4106 {0xD924, 0xff00}, 4107 {0xD914, 0xff000000}, 4108 {0xD918, 0xff}, 4109 {0xD918, 0xff00}, 4110 {0xD918, 0xff0000}, 4111 {0xD918, 0xff000000}, 4112 {0xD91C, 0xff}, 4113 {0xD91C, 0xff00}, 4114 {0xD91C, 0xff0000}, 4115 }; 4116 4117 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 4118 {0xD910, 0xff}, 4119 {0xD910, 0xff00}, 4120 {0xD910, 0xff0000}, 4121 {0xD910, 0xff000000}, 4122 {0xD914, 0xff}, 4123 {0xD914, 0xff00}, 4124 {0xD914, 0xff0000}, 4125 {0xD908, 0xff}, 4126 {0xD908, 0xff00}, 4127 {0xD908, 0xff0000}, 4128 {0xD908, 0xff000000}, 4129 {0xD90C, 0xff}, 4130 {0xD90C, 0xff00}, 4131 {0xD90C, 0xff0000}, 4132 {0xD90C, 0xff000000}, 4133 }; 4134 4135 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 4136 enum rtw89_mac_idx mac_idx, 4137 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 4138 { 4139 const struct rtw89_chip_info *chip = rtwdev->chip; 4140 const struct rtw89_reg_def *regs; 4141 const u32 *data; 4142 u32 reg; 4143 int i; 4144 4145 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 4146 return; 4147 4148 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4149 regs = rtw89_tssi_bandedge_regs_flat; 4150 else 4151 regs = rtw89_tssi_bandedge_regs_level; 4152 4153 data = chip->tssi_dbw_table->data[bandedge_cfg]; 4154 4155 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 4156 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 4157 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 4158 } 4159 4160 reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx); 4161 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 4162 4163 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 4164 data[RTW89_TSSI_SBW20]); 4165 } 4166 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 4167