1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "ps.h" 11 #include "reg.h" 12 #include "sar.h" 13 #include "txrx.h" 14 #include "util.h" 15 16 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 17 const struct rtw89_ra_report *report) 18 { 19 u32 bit_rate = report->bit_rate; 20 21 /* lower than ofdm, do not aggregate */ 22 if (bit_rate < 550) 23 return 1; 24 25 /* avoid AMSDU for legacy rate */ 26 if (report->might_fallback_legacy) 27 return 1; 28 29 /* lower than 20M vht 2ss mcs8, make it small */ 30 if (bit_rate < 1800) 31 return 1200; 32 33 /* lower than 40M vht 2ss mcs9, make it medium */ 34 if (bit_rate < 4000) 35 return 2600; 36 37 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 38 if (bit_rate < 7000) 39 return 3500; 40 41 return rtwdev->chip->max_amsdu_limit; 42 } 43 44 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 45 { 46 u64 ra_mask = 0; 47 u8 mcs_cap; 48 int i, nss; 49 50 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 51 mcs_cap = mcs_map & 0x3; 52 switch (mcs_cap) { 53 case 2: 54 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 55 break; 56 case 1: 57 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 58 break; 59 case 0: 60 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 61 break; 62 default: 63 break; 64 } 65 } 66 67 return ra_mask; 68 } 69 70 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 71 { 72 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 73 u16 mcs_map; 74 75 switch (sta->deflink.bandwidth) { 76 case IEEE80211_STA_RX_BW_160: 77 if (cap.he_cap_elem.phy_cap_info[0] & 78 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 79 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 80 else 81 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 82 break; 83 default: 84 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 85 } 86 87 /* MCS11, MCS9, MCS7 */ 88 return get_mcs_ra_mask(mcs_map, 11, 2); 89 } 90 91 static u64 get_eht_mcs_ra_mask(u8 *max_nss, u8 start_mcs, u8 n_nss) 92 { 93 u64 nss_mcs_shift; 94 u64 nss_mcs_val; 95 u64 mask = 0; 96 int i, j; 97 u8 nss; 98 99 for (i = 0; i < n_nss; i++) { 100 nss = u8_get_bits(max_nss[i], IEEE80211_EHT_MCS_NSS_RX); 101 if (!nss) 102 continue; 103 104 nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0); 105 106 for (j = 0, nss_mcs_shift = 12; j < nss; j++, nss_mcs_shift += 16) 107 mask |= nss_mcs_val << nss_mcs_shift; 108 } 109 110 return mask; 111 } 112 113 static u64 get_eht_ra_mask(struct ieee80211_sta *sta) 114 { 115 struct ieee80211_sta_eht_cap *eht_cap = &sta->deflink.eht_cap; 116 struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs_nss_20mhz; 117 struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss; 118 119 switch (sta->deflink.bandwidth) { 120 case IEEE80211_STA_RX_BW_320: 121 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320; 122 /* MCS 9, 11, 13 */ 123 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 124 case IEEE80211_STA_RX_BW_160: 125 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160; 126 /* MCS 9, 11, 13 */ 127 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 128 case IEEE80211_STA_RX_BW_80: 129 default: 130 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80; 131 /* MCS 9, 11, 13 */ 132 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 133 case IEEE80211_STA_RX_BW_20: 134 mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz; 135 /* MCS 7, 9, 11, 13 */ 136 return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4); 137 } 138 } 139 140 #define RA_FLOOR_TABLE_SIZE 7 141 #define RA_FLOOR_UP_GAP 3 142 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 143 u8 ratr_state) 144 { 145 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 146 u8 rssi_lv = 0; 147 u8 i; 148 149 rssi >>= 1; 150 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 151 if (i >= ratr_state) 152 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 153 if (rssi < rssi_lv_t[i]) { 154 rssi_lv = i; 155 break; 156 } 157 } 158 if (rssi_lv == 0) 159 return 0xffffffffffffffffULL; 160 else if (rssi_lv == 1) 161 return 0xfffffffffffffff0ULL; 162 else if (rssi_lv == 2) 163 return 0xffffffffffffefe0ULL; 164 else if (rssi_lv == 3) 165 return 0xffffffffffffcfc0ULL; 166 else if (rssi_lv == 4) 167 return 0xffffffffffff8f80ULL; 168 else if (rssi_lv >= 5) 169 return 0xffffffffffff0f00ULL; 170 171 return 0xffffffffffffffffULL; 172 } 173 174 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 175 { 176 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 177 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 178 179 if (ra_mask == 0) 180 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 181 182 return ra_mask; 183 } 184 185 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 186 const struct rtw89_chan *chan) 187 { 188 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 189 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 190 enum nl80211_band band; 191 u64 cfg_mask; 192 193 if (!rtwsta->use_cfg_mask) 194 return -1; 195 196 switch (chan->band_type) { 197 case RTW89_BAND_2G: 198 band = NL80211_BAND_2GHZ; 199 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 200 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 201 break; 202 case RTW89_BAND_5G: 203 band = NL80211_BAND_5GHZ; 204 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 205 RA_MASK_OFDM_RATES); 206 break; 207 case RTW89_BAND_6G: 208 band = NL80211_BAND_6GHZ; 209 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 210 RA_MASK_OFDM_RATES); 211 break; 212 default: 213 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 214 return -1; 215 } 216 217 if (sta->deflink.he_cap.has_he) { 218 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 219 RA_MASK_HE_1SS_RATES); 220 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 221 RA_MASK_HE_2SS_RATES); 222 } else if (sta->deflink.vht_cap.vht_supported) { 223 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 224 RA_MASK_VHT_1SS_RATES); 225 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 226 RA_MASK_VHT_2SS_RATES); 227 } else if (sta->deflink.ht_cap.ht_supported) { 228 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 229 RA_MASK_HT_1SS_RATES); 230 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 231 RA_MASK_HT_2SS_RATES); 232 } 233 234 return cfg_mask; 235 } 236 237 static const u64 238 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 239 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 240 static const u64 241 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 242 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 243 static const u64 244 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 245 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 246 static const u64 247 rtw89_ra_mask_eht_rates[4] = {RA_MASK_EHT_1SS_RATES, RA_MASK_EHT_2SS_RATES, 248 RA_MASK_EHT_3SS_RATES, RA_MASK_EHT_4SS_RATES}; 249 250 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 251 struct rtw89_sta *rtwsta, 252 const struct rtw89_chan *chan, 253 bool *fix_giltf_en, u8 *fix_giltf) 254 { 255 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 256 u8 band = chan->band_type; 257 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 258 u8 he_gi = mask->control[nl_band].he_gi; 259 u8 he_ltf = mask->control[nl_band].he_ltf; 260 261 if (!rtwsta->use_cfg_mask) 262 return; 263 264 if (he_ltf == 2 && he_gi == 2) { 265 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 266 } else if (he_ltf == 2 && he_gi == 0) { 267 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 268 } else if (he_ltf == 1 && he_gi == 1) { 269 *fix_giltf = RTW89_GILTF_2XHE16; 270 } else if (he_ltf == 1 && he_gi == 0) { 271 *fix_giltf = RTW89_GILTF_2XHE08; 272 } else if (he_ltf == 0 && he_gi == 1) { 273 *fix_giltf = RTW89_GILTF_1XHE16; 274 } else if (he_ltf == 0 && he_gi == 0) { 275 *fix_giltf = RTW89_GILTF_1XHE08; 276 } else { 277 *fix_giltf_en = false; 278 return; 279 } 280 281 *fix_giltf_en = true; 282 } 283 284 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 285 struct ieee80211_sta *sta, bool csi) 286 { 287 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 288 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 289 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 290 struct rtw89_ra_info *ra = &rtwsta->ra; 291 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 292 rtwvif->sub_entity_idx); 293 struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); 294 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 295 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 296 u64 ra_mask = 0; 297 u64 ra_mask_bak; 298 u8 mode = 0; 299 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 300 u8 bw_mode = 0; 301 u8 stbc_en = 0; 302 u8 ldpc_en = 0; 303 u8 fix_giltf = 0; 304 u8 i; 305 bool sgi = false; 306 bool fix_giltf_en = false; 307 308 memset(ra, 0, sizeof(*ra)); 309 /* Set the ra mask from sta's capability */ 310 if (sta->deflink.eht_cap.has_eht) { 311 mode |= RTW89_RA_MODE_EHT; 312 ra_mask |= get_eht_ra_mask(sta); 313 high_rate_masks = rtw89_ra_mask_eht_rates; 314 } else if (sta->deflink.he_cap.has_he) { 315 mode |= RTW89_RA_MODE_HE; 316 csi_mode = RTW89_RA_RPT_MODE_HE; 317 ra_mask |= get_he_ra_mask(sta); 318 high_rate_masks = rtw89_ra_mask_he_rates; 319 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 320 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 321 stbc_en = 1; 322 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 323 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 324 ldpc_en = 1; 325 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, chan, &fix_giltf_en, &fix_giltf); 326 } else if (sta->deflink.vht_cap.vht_supported) { 327 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 328 329 mode |= RTW89_RA_MODE_VHT; 330 csi_mode = RTW89_RA_RPT_MODE_VHT; 331 /* MCS9, MCS8, MCS7 */ 332 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 333 high_rate_masks = rtw89_ra_mask_vht_rates; 334 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 335 stbc_en = 1; 336 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 337 ldpc_en = 1; 338 } else if (sta->deflink.ht_cap.ht_supported) { 339 mode |= RTW89_RA_MODE_HT; 340 csi_mode = RTW89_RA_RPT_MODE_HT; 341 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 342 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 343 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 344 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 345 high_rate_masks = rtw89_ra_mask_ht_rates; 346 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 347 stbc_en = 1; 348 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 349 ldpc_en = 1; 350 } 351 352 switch (chan->band_type) { 353 case RTW89_BAND_2G: 354 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 355 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xf) 356 mode |= RTW89_RA_MODE_CCK; 357 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xff0) 358 mode |= RTW89_RA_MODE_OFDM; 359 break; 360 case RTW89_BAND_5G: 361 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 362 mode |= RTW89_RA_MODE_OFDM; 363 break; 364 case RTW89_BAND_6G: 365 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 366 mode |= RTW89_RA_MODE_OFDM; 367 break; 368 default: 369 rtw89_err(rtwdev, "Unknown band type\n"); 370 break; 371 } 372 373 ra_mask_bak = ra_mask; 374 375 if (mode >= RTW89_RA_MODE_HT) { 376 u64 mask = 0; 377 for (i = 0; i < rtwdev->hal.tx_nss; i++) 378 mask |= high_rate_masks[i]; 379 if (mode & RTW89_RA_MODE_OFDM) 380 mask |= RA_MASK_SUBOFDM_RATES; 381 if (mode & RTW89_RA_MODE_CCK) 382 mask |= RA_MASK_SUBCCK_RATES; 383 ra_mask &= mask; 384 } else if (mode & RTW89_RA_MODE_OFDM) { 385 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 386 } 387 388 if (mode != RTW89_RA_MODE_CCK) 389 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 390 391 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 392 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan); 393 394 switch (sta->deflink.bandwidth) { 395 case IEEE80211_STA_RX_BW_160: 396 bw_mode = RTW89_CHANNEL_WIDTH_160; 397 sgi = sta->deflink.vht_cap.vht_supported && 398 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 399 break; 400 case IEEE80211_STA_RX_BW_80: 401 bw_mode = RTW89_CHANNEL_WIDTH_80; 402 sgi = sta->deflink.vht_cap.vht_supported && 403 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 404 break; 405 case IEEE80211_STA_RX_BW_40: 406 bw_mode = RTW89_CHANNEL_WIDTH_40; 407 sgi = sta->deflink.ht_cap.ht_supported && 408 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 409 break; 410 default: 411 bw_mode = RTW89_CHANNEL_WIDTH_20; 412 sgi = sta->deflink.ht_cap.ht_supported && 413 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 414 break; 415 } 416 417 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 418 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 419 ra->dcm_cap = 1; 420 421 if (rate_pattern->enable && !vif->p2p) { 422 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan); 423 ra_mask &= rate_pattern->ra_mask; 424 mode = rate_pattern->ra_mode; 425 } 426 427 ra->bw_cap = bw_mode; 428 ra->er_cap = rtwsta->er_cap; 429 ra->mode_ctrl = mode; 430 ra->macid = rtwsta->mac_id; 431 ra->stbc_cap = stbc_en; 432 ra->ldpc_cap = ldpc_en; 433 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 434 ra->en_sgi = sgi; 435 ra->ra_mask = ra_mask; 436 ra->fix_giltf_en = fix_giltf_en; 437 ra->fix_giltf = fix_giltf; 438 439 if (!csi) 440 return; 441 442 ra->fixed_csi_rate_en = false; 443 ra->ra_csi_rate_en = true; 444 ra->cr_tbl_sel = false; 445 ra->band_num = rtwvif->phy_idx; 446 ra->csi_bw = bw_mode; 447 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 448 ra->csi_mcs_ss_idx = 5; 449 ra->csi_mode = csi_mode; 450 } 451 452 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 453 u32 changed) 454 { 455 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 456 struct rtw89_ra_info *ra = &rtwsta->ra; 457 458 rtw89_phy_ra_sta_update(rtwdev, sta, false); 459 460 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 461 ra->upd_mask = 1; 462 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 463 ra->upd_bw_nss_mask = 1; 464 465 rtw89_debug(rtwdev, RTW89_DBG_RA, 466 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 467 ra->macid, 468 ra->bw_cap, 469 ra->ss_num, 470 ra->en_sgi, 471 ra->giltf); 472 473 rtw89_fw_h2c_ra(rtwdev, ra, false); 474 } 475 476 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 477 u16 rate_base, u64 ra_mask, u8 ra_mode, 478 u32 rate_ctrl, u32 ctrl_skip, bool force) 479 { 480 u8 n, c; 481 482 if (rate_ctrl == ctrl_skip) 483 return true; 484 485 n = hweight32(rate_ctrl); 486 if (n == 0) 487 return true; 488 489 if (force && n != 1) 490 return false; 491 492 if (next->enable) 493 return false; 494 495 c = __fls(rate_ctrl); 496 next->rate = rate_base + c; 497 next->ra_mode = ra_mode; 498 next->ra_mask = ra_mask; 499 next->enable = true; 500 501 return true; 502 } 503 504 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \ 505 { \ 506 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \ 507 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \ 508 } 509 510 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 511 struct ieee80211_vif *vif, 512 const struct cfg80211_bitrate_mask *mask) 513 { 514 struct ieee80211_supported_band *sband; 515 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 516 struct rtw89_phy_rate_pattern next_pattern = {0}; 517 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 518 rtwvif->sub_entity_idx); 519 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = { 520 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0), 521 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0), 522 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0), 523 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0), 524 }; 525 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = { 526 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0), 527 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0), 528 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0), 529 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0), 530 }; 531 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = { 532 RTW89_HW_RATE_BY_CHIP_GEN(MCS0), 533 RTW89_HW_RATE_BY_CHIP_GEN(MCS8), 534 RTW89_HW_RATE_BY_CHIP_GEN(MCS16), 535 RTW89_HW_RATE_BY_CHIP_GEN(MCS24), 536 }; 537 u8 band = chan->band_type; 538 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 539 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 540 u8 tx_nss = rtwdev->hal.tx_nss; 541 u8 i; 542 543 for (i = 0; i < tx_nss; i++) 544 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen], 545 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 546 mask->control[nl_band].he_mcs[i], 547 0, true)) 548 goto out; 549 550 for (i = 0; i < tx_nss; i++) 551 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen], 552 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 553 mask->control[nl_band].vht_mcs[i], 554 0, true)) 555 goto out; 556 557 for (i = 0; i < tx_nss; i++) 558 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen], 559 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 560 mask->control[nl_band].ht_mcs[i], 561 0, true)) 562 goto out; 563 564 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 565 * require at least one basic rate for ieee80211_set_bitrate_mask, 566 * so the decision just depends on if all bitrates are set or not. 567 */ 568 sband = rtwdev->hw->wiphy->bands[nl_band]; 569 if (band == RTW89_BAND_2G) { 570 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 571 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 572 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 573 mask->control[nl_band].legacy, 574 BIT(sband->n_bitrates) - 1, false)) 575 goto out; 576 } else { 577 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 578 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 579 mask->control[nl_band].legacy, 580 BIT(sband->n_bitrates) - 1, false)) 581 goto out; 582 } 583 584 if (!next_pattern.enable) 585 goto out; 586 587 rtwvif->rate_pattern = next_pattern; 588 rtw89_debug(rtwdev, RTW89_DBG_RA, 589 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 590 next_pattern.rate, 591 next_pattern.ra_mask, 592 next_pattern.ra_mode); 593 return; 594 595 out: 596 rtwvif->rate_pattern.enable = false; 597 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 598 } 599 600 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 601 { 602 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 603 604 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 605 } 606 607 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 608 { 609 ieee80211_iterate_stations_atomic(rtwdev->hw, 610 rtw89_phy_ra_updata_sta_iter, 611 rtwdev); 612 } 613 614 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 615 { 616 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 617 struct rtw89_ra_info *ra = &rtwsta->ra; 618 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 619 bool csi = rtw89_sta_has_beamformer_cap(sta); 620 621 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 622 623 if (rssi > 40) 624 ra->init_rate_lv = 1; 625 else if (rssi > 20) 626 ra->init_rate_lv = 2; 627 else if (rssi > 1) 628 ra->init_rate_lv = 3; 629 else 630 ra->init_rate_lv = 0; 631 ra->upd_all = 1; 632 rtw89_debug(rtwdev, RTW89_DBG_RA, 633 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 634 ra->macid, 635 ra->mode_ctrl, 636 ra->bw_cap, 637 ra->ss_num, 638 ra->init_rate_lv); 639 rtw89_debug(rtwdev, RTW89_DBG_RA, 640 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 641 ra->dcm_cap, 642 ra->er_cap, 643 ra->ldpc_cap, 644 ra->stbc_cap, 645 ra->en_sgi, 646 ra->giltf); 647 648 rtw89_fw_h2c_ra(rtwdev, ra, csi); 649 } 650 651 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 652 const struct rtw89_chan *chan, 653 enum rtw89_bandwidth dbw) 654 { 655 enum rtw89_bandwidth cbw = chan->band_width; 656 u8 pri_ch = chan->primary_channel; 657 u8 central_ch = chan->channel; 658 u8 txsc_idx = 0; 659 u8 tmp = 0; 660 661 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 662 return txsc_idx; 663 664 switch (cbw) { 665 case RTW89_CHANNEL_WIDTH_40: 666 txsc_idx = pri_ch > central_ch ? 1 : 2; 667 break; 668 case RTW89_CHANNEL_WIDTH_80: 669 if (dbw == RTW89_CHANNEL_WIDTH_20) { 670 if (pri_ch > central_ch) 671 txsc_idx = (pri_ch - central_ch) >> 1; 672 else 673 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 674 } else { 675 txsc_idx = pri_ch > central_ch ? 9 : 10; 676 } 677 break; 678 case RTW89_CHANNEL_WIDTH_160: 679 if (pri_ch > central_ch) 680 tmp = (pri_ch - central_ch) >> 1; 681 else 682 tmp = ((central_ch - pri_ch) >> 1) + 1; 683 684 if (dbw == RTW89_CHANNEL_WIDTH_20) { 685 txsc_idx = tmp; 686 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 687 if (tmp == 1 || tmp == 3) 688 txsc_idx = 9; 689 else if (tmp == 5 || tmp == 7) 690 txsc_idx = 11; 691 else if (tmp == 2 || tmp == 4) 692 txsc_idx = 10; 693 else if (tmp == 6 || tmp == 8) 694 txsc_idx = 12; 695 else 696 return 0xff; 697 } else { 698 txsc_idx = pri_ch > central_ch ? 13 : 14; 699 } 700 break; 701 case RTW89_CHANNEL_WIDTH_80_80: 702 if (dbw == RTW89_CHANNEL_WIDTH_20) { 703 if (pri_ch > central_ch) 704 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 705 else 706 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 707 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 708 txsc_idx = pri_ch > central_ch ? 10 : 12; 709 } else { 710 txsc_idx = 14; 711 } 712 break; 713 default: 714 break; 715 } 716 717 return txsc_idx; 718 } 719 EXPORT_SYMBOL(rtw89_phy_get_txsc); 720 721 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 722 { 723 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 724 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 725 } 726 727 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 728 u32 addr, u32 mask) 729 { 730 const struct rtw89_chip_info *chip = rtwdev->chip; 731 const u32 *base_addr = chip->rf_base_addr; 732 u32 val, direct_addr; 733 734 if (rf_path >= rtwdev->chip->rf_path_num) { 735 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 736 return INV_RF_DATA; 737 } 738 739 addr &= 0xff; 740 direct_addr = base_addr[rf_path] + (addr << 2); 741 mask &= RFREG_MASK; 742 743 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 744 745 return val; 746 } 747 EXPORT_SYMBOL(rtw89_phy_read_rf); 748 749 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 750 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 751 { 752 bool busy; 753 bool done; 754 u32 val; 755 int ret; 756 757 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 758 1, 30, false, rtwdev); 759 if (ret) { 760 rtw89_err(rtwdev, "read rf busy swsi\n"); 761 return INV_RF_DATA; 762 } 763 764 mask &= RFREG_MASK; 765 766 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 767 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 768 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 769 udelay(2); 770 771 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 772 30, false, rtwdev, R_SWSI_V1, 773 B_SWSI_R_DATA_DONE_V1); 774 if (ret) { 775 rtw89_err(rtwdev, "read swsi busy\n"); 776 return INV_RF_DATA; 777 } 778 779 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 780 } 781 782 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 783 u32 addr, u32 mask) 784 { 785 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 786 787 if (rf_path >= rtwdev->chip->rf_path_num) { 788 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 789 return INV_RF_DATA; 790 } 791 792 if (ad_sel) 793 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 794 else 795 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 796 } 797 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 798 799 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 800 u32 addr, u32 mask, u32 data) 801 { 802 const struct rtw89_chip_info *chip = rtwdev->chip; 803 const u32 *base_addr = chip->rf_base_addr; 804 u32 direct_addr; 805 806 if (rf_path >= rtwdev->chip->rf_path_num) { 807 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 808 return false; 809 } 810 811 addr &= 0xff; 812 direct_addr = base_addr[rf_path] + (addr << 2); 813 mask &= RFREG_MASK; 814 815 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 816 817 /* delay to ensure writing properly */ 818 udelay(1); 819 820 return true; 821 } 822 EXPORT_SYMBOL(rtw89_phy_write_rf); 823 824 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 825 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 826 u32 data) 827 { 828 u8 bit_shift; 829 u32 val; 830 bool busy, b_msk_en = false; 831 int ret; 832 833 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 834 1, 30, false, rtwdev); 835 if (ret) { 836 rtw89_err(rtwdev, "write rf busy swsi\n"); 837 return false; 838 } 839 840 data &= RFREG_MASK; 841 mask &= RFREG_MASK; 842 843 if (mask != RFREG_MASK) { 844 b_msk_en = true; 845 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 846 mask); 847 bit_shift = __ffs(mask); 848 data = (data << bit_shift) & RFREG_MASK; 849 } 850 851 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 852 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 853 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 854 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 855 856 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 857 858 return true; 859 } 860 861 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 862 u32 addr, u32 mask, u32 data) 863 { 864 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 865 866 if (rf_path >= rtwdev->chip->rf_path_num) { 867 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 868 return false; 869 } 870 871 if (ad_sel) 872 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 873 else 874 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 875 } 876 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 877 878 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 879 { 880 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; 881 } 882 883 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 884 enum rtw89_phy_idx phy_idx) 885 { 886 const struct rtw89_chip_info *chip = rtwdev->chip; 887 888 chip->ops->bb_reset(rtwdev, phy_idx); 889 } 890 891 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 892 const struct rtw89_reg2_def *reg, 893 enum rtw89_rf_path rf_path, 894 void *extra_data) 895 { 896 if (reg->addr == 0xfe) 897 mdelay(50); 898 else if (reg->addr == 0xfd) 899 mdelay(5); 900 else if (reg->addr == 0xfc) 901 mdelay(1); 902 else if (reg->addr == 0xfb) 903 udelay(50); 904 else if (reg->addr == 0xfa) 905 udelay(5); 906 else if (reg->addr == 0xf9) 907 udelay(1); 908 else if (reg->data == BYPASS_CR_DATA) 909 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr); 910 else 911 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 912 } 913 914 union rtw89_phy_bb_gain_arg { 915 u32 addr; 916 struct { 917 union { 918 u8 type; 919 struct { 920 u8 rxsc_start:4; 921 u8 bw:4; 922 }; 923 }; 924 u8 path; 925 u8 gain_band; 926 u8 cfg_type; 927 }; 928 } __packed; 929 930 static void 931 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 932 union rtw89_phy_bb_gain_arg arg, u32 data) 933 { 934 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 935 u8 type = arg.type; 936 u8 path = arg.path; 937 u8 gband = arg.gain_band; 938 int i; 939 940 switch (type) { 941 case 0: 942 for (i = 0; i < 4; i++, data >>= 8) 943 gain->lna_gain[gband][path][i] = data & 0xff; 944 break; 945 case 1: 946 for (i = 4; i < 7; i++, data >>= 8) 947 gain->lna_gain[gband][path][i] = data & 0xff; 948 break; 949 case 2: 950 for (i = 0; i < 2; i++, data >>= 8) 951 gain->tia_gain[gband][path][i] = data & 0xff; 952 break; 953 default: 954 rtw89_warn(rtwdev, 955 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 956 arg.addr, data, type); 957 break; 958 } 959 } 960 961 enum rtw89_phy_bb_rxsc_start_idx { 962 RTW89_BB_RXSC_START_IDX_FULL = 0, 963 RTW89_BB_RXSC_START_IDX_20 = 1, 964 RTW89_BB_RXSC_START_IDX_20_1 = 5, 965 RTW89_BB_RXSC_START_IDX_40 = 9, 966 RTW89_BB_RXSC_START_IDX_80 = 13, 967 }; 968 969 static void 970 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 971 union rtw89_phy_bb_gain_arg arg, u32 data) 972 { 973 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 974 u8 rxsc_start = arg.rxsc_start; 975 u8 bw = arg.bw; 976 u8 path = arg.path; 977 u8 gband = arg.gain_band; 978 u8 rxsc; 979 s8 ofst; 980 int i; 981 982 switch (bw) { 983 case RTW89_CHANNEL_WIDTH_20: 984 gain->rpl_ofst_20[gband][path] = (s8)data; 985 break; 986 case RTW89_CHANNEL_WIDTH_40: 987 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 988 gain->rpl_ofst_40[gband][path][0] = (s8)data; 989 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 990 for (i = 0; i < 2; i++, data >>= 8) { 991 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 992 ofst = (s8)(data & 0xff); 993 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 994 } 995 } 996 break; 997 case RTW89_CHANNEL_WIDTH_80: 998 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 999 gain->rpl_ofst_80[gband][path][0] = (s8)data; 1000 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1001 for (i = 0; i < 4; i++, data >>= 8) { 1002 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1003 ofst = (s8)(data & 0xff); 1004 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 1005 } 1006 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 1007 for (i = 0; i < 2; i++, data >>= 8) { 1008 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 1009 ofst = (s8)(data & 0xff); 1010 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 1011 } 1012 } 1013 break; 1014 case RTW89_CHANNEL_WIDTH_160: 1015 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1016 gain->rpl_ofst_160[gband][path][0] = (s8)data; 1017 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1018 for (i = 0; i < 4; i++, data >>= 8) { 1019 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1020 ofst = (s8)(data & 0xff); 1021 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1022 } 1023 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 1024 for (i = 0; i < 4; i++, data >>= 8) { 1025 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 1026 ofst = (s8)(data & 0xff); 1027 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1028 } 1029 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 1030 for (i = 0; i < 4; i++, data >>= 8) { 1031 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 1032 ofst = (s8)(data & 0xff); 1033 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1034 } 1035 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 1036 for (i = 0; i < 2; i++, data >>= 8) { 1037 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 1038 ofst = (s8)(data & 0xff); 1039 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1040 } 1041 } 1042 break; 1043 default: 1044 rtw89_warn(rtwdev, 1045 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 1046 arg.addr, data, bw); 1047 break; 1048 } 1049 } 1050 1051 static void 1052 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 1053 union rtw89_phy_bb_gain_arg arg, u32 data) 1054 { 1055 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1056 u8 type = arg.type; 1057 u8 path = arg.path; 1058 u8 gband = arg.gain_band; 1059 int i; 1060 1061 switch (type) { 1062 case 0: 1063 for (i = 0; i < 4; i++, data >>= 8) 1064 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1065 break; 1066 case 1: 1067 for (i = 4; i < 7; i++, data >>= 8) 1068 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1069 break; 1070 default: 1071 rtw89_warn(rtwdev, 1072 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 1073 arg.addr, data, type); 1074 break; 1075 } 1076 } 1077 1078 static void 1079 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 1080 union rtw89_phy_bb_gain_arg arg, u32 data) 1081 { 1082 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1083 u8 type = arg.type; 1084 u8 path = arg.path; 1085 u8 gband = arg.gain_band; 1086 int i; 1087 1088 switch (type) { 1089 case 0: 1090 for (i = 0; i < 4; i++, data >>= 8) 1091 gain->lna_op1db[gband][path][i] = data & 0xff; 1092 break; 1093 case 1: 1094 for (i = 4; i < 7; i++, data >>= 8) 1095 gain->lna_op1db[gband][path][i] = data & 0xff; 1096 break; 1097 case 2: 1098 for (i = 0; i < 4; i++, data >>= 8) 1099 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1100 break; 1101 case 3: 1102 for (i = 4; i < 8; i++, data >>= 8) 1103 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1104 break; 1105 default: 1106 rtw89_warn(rtwdev, 1107 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1108 arg.addr, data, type); 1109 break; 1110 } 1111 } 1112 1113 static void rtw89_phy_config_bb_gain_ax(struct rtw89_dev *rtwdev, 1114 const struct rtw89_reg2_def *reg, 1115 enum rtw89_rf_path rf_path, 1116 void *extra_data) 1117 { 1118 const struct rtw89_chip_info *chip = rtwdev->chip; 1119 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1120 struct rtw89_efuse *efuse = &rtwdev->efuse; 1121 1122 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1123 return; 1124 1125 if (arg.path >= chip->rf_path_num) 1126 return; 1127 1128 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1129 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1130 return; 1131 } 1132 1133 switch (arg.cfg_type) { 1134 case 0: 1135 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1136 break; 1137 case 1: 1138 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1139 break; 1140 case 2: 1141 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1142 break; 1143 case 3: 1144 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1145 break; 1146 case 4: 1147 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 1148 if (efuse->rfe_type < 50) 1149 break; 1150 fallthrough; 1151 default: 1152 rtw89_warn(rtwdev, 1153 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1154 arg.addr, reg->data, arg.cfg_type); 1155 break; 1156 } 1157 } 1158 1159 static void 1160 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1161 const struct rtw89_reg2_def *reg, 1162 enum rtw89_rf_path rf_path, 1163 struct rtw89_fw_h2c_rf_reg_info *info) 1164 { 1165 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1166 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1167 1168 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1169 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1170 rf_path, info->curr_idx); 1171 return; 1172 } 1173 1174 info->rtw89_phy_config_rf_h2c[page][idx] = 1175 cpu_to_le32((reg->addr << 20) | reg->data); 1176 info->curr_idx++; 1177 } 1178 1179 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1180 struct rtw89_fw_h2c_rf_reg_info *info) 1181 { 1182 u16 remain = info->curr_idx; 1183 u16 len = 0; 1184 u8 i; 1185 int ret = 0; 1186 1187 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1188 rtw89_warn(rtwdev, 1189 "rf reg h2c total len %d larger than %d\n", 1190 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1191 ret = -EINVAL; 1192 goto out; 1193 } 1194 1195 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1196 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1197 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1198 if (ret) 1199 goto out; 1200 } 1201 out: 1202 info->curr_idx = 0; 1203 1204 return ret; 1205 } 1206 1207 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev, 1208 const struct rtw89_reg2_def *reg, 1209 enum rtw89_rf_path rf_path, 1210 void *extra_data) 1211 { 1212 u32 addr = reg->addr; 1213 1214 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || 1215 addr == 0xfa || addr == 0xf9) 1216 return; 1217 1218 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100) 1219 return; 1220 1221 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1222 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1223 } 1224 1225 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1226 const struct rtw89_reg2_def *reg, 1227 enum rtw89_rf_path rf_path, 1228 void *extra_data) 1229 { 1230 if (reg->addr == 0xfe) { 1231 mdelay(50); 1232 } else if (reg->addr == 0xfd) { 1233 mdelay(5); 1234 } else if (reg->addr == 0xfc) { 1235 mdelay(1); 1236 } else if (reg->addr == 0xfb) { 1237 udelay(50); 1238 } else if (reg->addr == 0xfa) { 1239 udelay(5); 1240 } else if (reg->addr == 0xf9) { 1241 udelay(1); 1242 } else { 1243 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1244 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1245 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1246 } 1247 } 1248 1249 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1250 const struct rtw89_reg2_def *reg, 1251 enum rtw89_rf_path rf_path, 1252 void *extra_data) 1253 { 1254 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1255 1256 if (reg->addr < 0x100) 1257 return; 1258 1259 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1260 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1261 } 1262 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1263 1264 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1265 const struct rtw89_phy_table *table, 1266 u32 *headline_size, u32 *headline_idx, 1267 u8 rfe, u8 cv) 1268 { 1269 const struct rtw89_reg2_def *reg; 1270 u32 headline; 1271 u32 compare, target; 1272 u8 rfe_para, cv_para; 1273 u8 cv_max = 0; 1274 bool case_matched = false; 1275 u32 i; 1276 1277 for (i = 0; i < table->n_regs; i++) { 1278 reg = &table->regs[i]; 1279 headline = get_phy_headline(reg->addr); 1280 if (headline != PHY_HEADLINE_VALID) 1281 break; 1282 } 1283 *headline_size = i; 1284 if (*headline_size == 0) 1285 return 0; 1286 1287 /* case 1: RFE match, CV match */ 1288 compare = get_phy_compare(rfe, cv); 1289 for (i = 0; i < *headline_size; i++) { 1290 reg = &table->regs[i]; 1291 target = get_phy_target(reg->addr); 1292 if (target == compare) { 1293 *headline_idx = i; 1294 return 0; 1295 } 1296 } 1297 1298 /* case 2: RFE match, CV don't care */ 1299 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1300 for (i = 0; i < *headline_size; i++) { 1301 reg = &table->regs[i]; 1302 target = get_phy_target(reg->addr); 1303 if (target == compare) { 1304 *headline_idx = i; 1305 return 0; 1306 } 1307 } 1308 1309 /* case 3: RFE match, CV max in table */ 1310 for (i = 0; i < *headline_size; i++) { 1311 reg = &table->regs[i]; 1312 rfe_para = get_phy_cond_rfe(reg->addr); 1313 cv_para = get_phy_cond_cv(reg->addr); 1314 if (rfe_para == rfe) { 1315 if (cv_para >= cv_max) { 1316 cv_max = cv_para; 1317 *headline_idx = i; 1318 case_matched = true; 1319 } 1320 } 1321 } 1322 1323 if (case_matched) 1324 return 0; 1325 1326 /* case 4: RFE don't care, CV max in table */ 1327 for (i = 0; i < *headline_size; i++) { 1328 reg = &table->regs[i]; 1329 rfe_para = get_phy_cond_rfe(reg->addr); 1330 cv_para = get_phy_cond_cv(reg->addr); 1331 if (rfe_para == PHY_COND_DONT_CARE) { 1332 if (cv_para >= cv_max) { 1333 cv_max = cv_para; 1334 *headline_idx = i; 1335 case_matched = true; 1336 } 1337 } 1338 } 1339 1340 if (case_matched) 1341 return 0; 1342 1343 return -EINVAL; 1344 } 1345 1346 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1347 const struct rtw89_phy_table *table, 1348 void (*config)(struct rtw89_dev *rtwdev, 1349 const struct rtw89_reg2_def *reg, 1350 enum rtw89_rf_path rf_path, 1351 void *data), 1352 void *extra_data) 1353 { 1354 const struct rtw89_reg2_def *reg; 1355 enum rtw89_rf_path rf_path = table->rf_path; 1356 u8 rfe = rtwdev->efuse.rfe_type; 1357 u8 cv = rtwdev->hal.cv; 1358 u32 i; 1359 u32 headline_size = 0, headline_idx = 0; 1360 u32 target = 0, cfg_target; 1361 u8 cond; 1362 bool is_matched = true; 1363 bool target_found = false; 1364 int ret; 1365 1366 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1367 &headline_idx, rfe, cv); 1368 if (ret) { 1369 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1370 return; 1371 } 1372 1373 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1374 for (i = headline_size; i < table->n_regs; i++) { 1375 reg = &table->regs[i]; 1376 cond = get_phy_cond(reg->addr); 1377 switch (cond) { 1378 case PHY_COND_BRANCH_IF: 1379 case PHY_COND_BRANCH_ELIF: 1380 target = get_phy_target(reg->addr); 1381 break; 1382 case PHY_COND_BRANCH_ELSE: 1383 is_matched = false; 1384 if (!target_found) { 1385 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1386 reg->addr, reg->data); 1387 return; 1388 } 1389 break; 1390 case PHY_COND_BRANCH_END: 1391 is_matched = true; 1392 target_found = false; 1393 break; 1394 case PHY_COND_CHECK: 1395 if (target_found) { 1396 is_matched = false; 1397 break; 1398 } 1399 1400 if (target == cfg_target) { 1401 is_matched = true; 1402 target_found = true; 1403 } else { 1404 is_matched = false; 1405 target_found = false; 1406 } 1407 break; 1408 default: 1409 if (is_matched) 1410 config(rtwdev, reg, rf_path, extra_data); 1411 break; 1412 } 1413 } 1414 } 1415 1416 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1417 { 1418 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1419 const struct rtw89_chip_info *chip = rtwdev->chip; 1420 const struct rtw89_phy_table *bb_table; 1421 const struct rtw89_phy_table *bb_gain_table; 1422 1423 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table; 1424 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1425 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1426 1427 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table; 1428 if (bb_gain_table) 1429 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1430 chip->phy_def->config_bb_gain, NULL); 1431 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1432 } 1433 1434 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1435 { 1436 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1437 udelay(1); 1438 return rtw89_phy_read32(rtwdev, 0x8080); 1439 } 1440 1441 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio) 1442 { 1443 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1444 enum rtw89_rf_path rf_path, void *data); 1445 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1446 const struct rtw89_chip_info *chip = rtwdev->chip; 1447 const struct rtw89_phy_table *rf_table; 1448 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1449 u8 path; 1450 1451 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1452 if (!rf_reg_info) 1453 return; 1454 1455 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1456 rf_table = elm_info->rf_radio[path] ? 1457 elm_info->rf_radio[path] : chip->rf_table[path]; 1458 rf_reg_info->rf_path = rf_table->rf_path; 1459 if (noio) 1460 config = rtw89_phy_config_rf_reg_noio; 1461 else 1462 config = rf_table->config ? rf_table->config : 1463 rtw89_phy_config_rf_reg; 1464 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1465 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1466 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1467 rf_reg_info->rf_path); 1468 } 1469 kfree(rf_reg_info); 1470 } 1471 1472 static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev) 1473 { 1474 const struct rtw89_chip_info *chip = rtwdev->chip; 1475 u32 val; 1476 int ret; 1477 1478 /* IQK/DPK clock & reset */ 1479 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3); 1480 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1); 1481 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000); 1482 if (chip->chip_id != RTL8851B) 1483 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000); 1484 if (chip->chip_id == RTL8852B) 1485 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2); 1486 1487 /* check 0x8080 */ 1488 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8); 1489 1490 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1491 1000, false, rtwdev); 1492 if (ret) 1493 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1494 } 1495 1496 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1497 { 1498 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1499 const struct rtw89_chip_info *chip = rtwdev->chip; 1500 const struct rtw89_phy_table *nctl_table; 1501 1502 rtw89_phy_preinit_rf_nctl(rtwdev); 1503 1504 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table; 1505 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1506 1507 if (chip->nctl_post_table) 1508 rtw89_rfk_parser(rtwdev, chip->nctl_post_table); 1509 } 1510 1511 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1512 { 1513 u32 phy_page = addr >> 8; 1514 u32 ofst = 0; 1515 1516 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1517 return addr < 0x10000 ? 0x20000 : 0; 1518 1519 switch (phy_page) { 1520 case 0x6: 1521 case 0x7: 1522 case 0x8: 1523 case 0x9: 1524 case 0xa: 1525 case 0xb: 1526 case 0xc: 1527 case 0xd: 1528 case 0x19: 1529 case 0x1a: 1530 case 0x1b: 1531 ofst = 0x2000; 1532 break; 1533 default: 1534 /* warning case */ 1535 ofst = 0; 1536 break; 1537 } 1538 1539 if (phy_page >= 0x40 && phy_page <= 0x4f) 1540 ofst = 0x2000; 1541 1542 return ofst; 1543 } 1544 1545 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1546 u32 data, enum rtw89_phy_idx phy_idx) 1547 { 1548 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1549 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1550 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1551 } 1552 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1553 1554 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1555 enum rtw89_phy_idx phy_idx) 1556 { 1557 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1558 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1559 return rtw89_phy_read32_mask(rtwdev, addr, mask); 1560 } 1561 EXPORT_SYMBOL(rtw89_phy_read32_idx); 1562 1563 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1564 u32 val) 1565 { 1566 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1567 1568 if (!rtwdev->dbcc_en) 1569 return; 1570 1571 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1572 } 1573 EXPORT_SYMBOL(rtw89_phy_set_phy_regs); 1574 1575 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1576 const struct rtw89_phy_reg3_tbl *tbl) 1577 { 1578 const struct rtw89_reg3_def *reg3; 1579 int i; 1580 1581 for (i = 0; i < tbl->size; i++) { 1582 reg3 = &tbl->reg3[i]; 1583 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1584 } 1585 } 1586 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1587 1588 static const u8 rtw89_rs_idx_num_ax[] = { 1589 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM, 1590 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM, 1591 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX, 1592 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM, 1593 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX, 1594 }; 1595 1596 static const u8 rtw89_rs_nss_num_ax[] = { 1597 [RTW89_RS_CCK] = 1, 1598 [RTW89_RS_OFDM] = 1, 1599 [RTW89_RS_MCS] = RTW89_NSS_NUM, 1600 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM, 1601 [RTW89_RS_OFFSET] = 1, 1602 }; 1603 1604 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, 1605 struct rtw89_txpwr_byrate *head, 1606 const struct rtw89_rate_desc *desc) 1607 { 1608 switch (desc->rs) { 1609 case RTW89_RS_CCK: 1610 return &head->cck[desc->idx]; 1611 case RTW89_RS_OFDM: 1612 return &head->ofdm[desc->idx]; 1613 case RTW89_RS_MCS: 1614 return &head->mcs[desc->ofdma][desc->nss][desc->idx]; 1615 case RTW89_RS_HEDCM: 1616 return &head->hedcm[desc->ofdma][desc->nss][desc->idx]; 1617 case RTW89_RS_OFFSET: 1618 return &head->offset[desc->idx]; 1619 default: 1620 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs); 1621 return &head->trap; 1622 } 1623 } 1624 1625 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1626 const struct rtw89_txpwr_table *tbl) 1627 { 1628 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1629 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1630 struct rtw89_txpwr_byrate *byr_head; 1631 struct rtw89_rate_desc desc = {}; 1632 s8 *byr; 1633 u32 data; 1634 u8 i; 1635 1636 for (; cfg < end; cfg++) { 1637 byr_head = &rtwdev->byr[cfg->band][0]; 1638 desc.rs = cfg->rs; 1639 desc.nss = cfg->nss; 1640 data = cfg->data; 1641 1642 for (i = 0; i < cfg->len; i++, data >>= 8) { 1643 desc.idx = cfg->shf + i; 1644 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc); 1645 *byr = data & 0xff; 1646 } 1647 } 1648 } 1649 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1650 1651 static s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf) 1652 { 1653 const struct rtw89_chip_info *chip = rtwdev->chip; 1654 1655 return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac); 1656 } 1657 1658 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, 1659 const struct rtw89_rate_desc *rate_desc) 1660 { 1661 struct rtw89_txpwr_byrate *byr_head; 1662 s8 *byr; 1663 1664 if (rate_desc->rs == RTW89_RS_CCK) 1665 band = RTW89_BAND_2G; 1666 1667 byr_head = &rtwdev->byr[band][bw]; 1668 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc); 1669 1670 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr); 1671 } 1672 1673 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1674 { 1675 switch (channel_6g) { 1676 case 1 ... 29: 1677 return (channel_6g - 1) / 2; 1678 case 33 ... 61: 1679 return (channel_6g - 3) / 2; 1680 case 65 ... 93: 1681 return (channel_6g - 5) / 2; 1682 case 97 ... 125: 1683 return (channel_6g - 7) / 2; 1684 case 129 ... 157: 1685 return (channel_6g - 9) / 2; 1686 case 161 ... 189: 1687 return (channel_6g - 11) / 2; 1688 case 193 ... 221: 1689 return (channel_6g - 13) / 2; 1690 case 225 ... 253: 1691 return (channel_6g - 15) / 2; 1692 default: 1693 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1694 return 0; 1695 } 1696 } 1697 1698 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1699 { 1700 if (band == RTW89_BAND_6G) 1701 return rtw89_channel_6g_to_idx(rtwdev, channel); 1702 1703 switch (channel) { 1704 case 1 ... 14: 1705 return channel - 1; 1706 case 36 ... 64: 1707 return (channel - 36) / 2; 1708 case 100 ... 144: 1709 return ((channel - 100) / 2) + 15; 1710 case 149 ... 177: 1711 return ((channel - 149) / 2) + 38; 1712 default: 1713 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1714 return 0; 1715 } 1716 } 1717 1718 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1719 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1720 { 1721 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1722 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 1723 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 1724 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 1725 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1726 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 1727 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 1728 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1729 u8 regd = rtw89_regd_get(rtwdev, band); 1730 u8 reg6 = regulatory->reg_6ghz_power; 1731 s8 lmt = 0, sar; 1732 1733 switch (band) { 1734 case RTW89_BAND_2G: 1735 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1736 if (lmt) 1737 break; 1738 1739 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1740 break; 1741 case RTW89_BAND_5G: 1742 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1743 if (lmt) 1744 break; 1745 1746 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1747 break; 1748 case RTW89_BAND_6G: 1749 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx]; 1750 if (lmt) 1751 break; 1752 1753 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW] 1754 [RTW89_REG_6GHZ_POWER_DFLT] 1755 [ch_idx]; 1756 break; 1757 default: 1758 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1759 return 0; 1760 } 1761 1762 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt); 1763 sar = rtw89_query_sar(rtwdev, freq); 1764 1765 return min(lmt, sar); 1766 } 1767 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1768 1769 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 1770 do { \ 1771 u8 __i; \ 1772 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1773 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1774 band, \ 1775 bw, ntx, \ 1776 rs, __i, \ 1777 (ch)); \ 1778 } while (0) 1779 1780 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev, 1781 struct rtw89_txpwr_limit_ax *lmt, 1782 u8 band, u8 ntx, u8 ch) 1783 { 1784 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1785 ntx, RTW89_RS_CCK, ch); 1786 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1787 ntx, RTW89_RS_CCK, ch); 1788 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1789 ntx, RTW89_RS_OFDM, ch); 1790 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1791 RTW89_CHANNEL_WIDTH_20, 1792 ntx, RTW89_RS_MCS, ch); 1793 } 1794 1795 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev, 1796 struct rtw89_txpwr_limit_ax *lmt, 1797 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1798 { 1799 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1800 ntx, RTW89_RS_CCK, ch - 2); 1801 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1802 ntx, RTW89_RS_CCK, ch); 1803 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1804 ntx, RTW89_RS_OFDM, pri_ch); 1805 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1806 RTW89_CHANNEL_WIDTH_20, 1807 ntx, RTW89_RS_MCS, ch - 2); 1808 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1809 RTW89_CHANNEL_WIDTH_20, 1810 ntx, RTW89_RS_MCS, ch + 2); 1811 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1812 RTW89_CHANNEL_WIDTH_40, 1813 ntx, RTW89_RS_MCS, ch); 1814 } 1815 1816 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev, 1817 struct rtw89_txpwr_limit_ax *lmt, 1818 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1819 { 1820 s8 val_0p5_n[RTW89_BF_NUM]; 1821 s8 val_0p5_p[RTW89_BF_NUM]; 1822 u8 i; 1823 1824 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1825 ntx, RTW89_RS_OFDM, pri_ch); 1826 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1827 RTW89_CHANNEL_WIDTH_20, 1828 ntx, RTW89_RS_MCS, ch - 6); 1829 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1830 RTW89_CHANNEL_WIDTH_20, 1831 ntx, RTW89_RS_MCS, ch - 2); 1832 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1833 RTW89_CHANNEL_WIDTH_20, 1834 ntx, RTW89_RS_MCS, ch + 2); 1835 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1836 RTW89_CHANNEL_WIDTH_20, 1837 ntx, RTW89_RS_MCS, ch + 6); 1838 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1839 RTW89_CHANNEL_WIDTH_40, 1840 ntx, RTW89_RS_MCS, ch - 4); 1841 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1842 RTW89_CHANNEL_WIDTH_40, 1843 ntx, RTW89_RS_MCS, ch + 4); 1844 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1845 RTW89_CHANNEL_WIDTH_80, 1846 ntx, RTW89_RS_MCS, ch); 1847 1848 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1849 ntx, RTW89_RS_MCS, ch - 4); 1850 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1851 ntx, RTW89_RS_MCS, ch + 4); 1852 1853 for (i = 0; i < RTW89_BF_NUM; i++) 1854 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1855 } 1856 1857 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev, 1858 struct rtw89_txpwr_limit_ax *lmt, 1859 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1860 { 1861 s8 val_0p5_n[RTW89_BF_NUM]; 1862 s8 val_0p5_p[RTW89_BF_NUM]; 1863 s8 val_2p5_n[RTW89_BF_NUM]; 1864 s8 val_2p5_p[RTW89_BF_NUM]; 1865 u8 i; 1866 1867 /* fill ofdm section */ 1868 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1869 ntx, RTW89_RS_OFDM, pri_ch); 1870 1871 /* fill mcs 20m section */ 1872 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1873 RTW89_CHANNEL_WIDTH_20, 1874 ntx, RTW89_RS_MCS, ch - 14); 1875 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1876 RTW89_CHANNEL_WIDTH_20, 1877 ntx, RTW89_RS_MCS, ch - 10); 1878 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1879 RTW89_CHANNEL_WIDTH_20, 1880 ntx, RTW89_RS_MCS, ch - 6); 1881 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1882 RTW89_CHANNEL_WIDTH_20, 1883 ntx, RTW89_RS_MCS, ch - 2); 1884 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 1885 RTW89_CHANNEL_WIDTH_20, 1886 ntx, RTW89_RS_MCS, ch + 2); 1887 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 1888 RTW89_CHANNEL_WIDTH_20, 1889 ntx, RTW89_RS_MCS, ch + 6); 1890 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 1891 RTW89_CHANNEL_WIDTH_20, 1892 ntx, RTW89_RS_MCS, ch + 10); 1893 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 1894 RTW89_CHANNEL_WIDTH_20, 1895 ntx, RTW89_RS_MCS, ch + 14); 1896 1897 /* fill mcs 40m section */ 1898 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1899 RTW89_CHANNEL_WIDTH_40, 1900 ntx, RTW89_RS_MCS, ch - 12); 1901 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1902 RTW89_CHANNEL_WIDTH_40, 1903 ntx, RTW89_RS_MCS, ch - 4); 1904 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 1905 RTW89_CHANNEL_WIDTH_40, 1906 ntx, RTW89_RS_MCS, ch + 4); 1907 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 1908 RTW89_CHANNEL_WIDTH_40, 1909 ntx, RTW89_RS_MCS, ch + 12); 1910 1911 /* fill mcs 80m section */ 1912 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1913 RTW89_CHANNEL_WIDTH_80, 1914 ntx, RTW89_RS_MCS, ch - 8); 1915 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 1916 RTW89_CHANNEL_WIDTH_80, 1917 ntx, RTW89_RS_MCS, ch + 8); 1918 1919 /* fill mcs 160m section */ 1920 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 1921 RTW89_CHANNEL_WIDTH_160, 1922 ntx, RTW89_RS_MCS, ch); 1923 1924 /* fill mcs 40m 0p5 section */ 1925 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1926 ntx, RTW89_RS_MCS, ch - 4); 1927 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1928 ntx, RTW89_RS_MCS, ch + 4); 1929 1930 for (i = 0; i < RTW89_BF_NUM; i++) 1931 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1932 1933 /* fill mcs 40m 2p5 section */ 1934 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 1935 ntx, RTW89_RS_MCS, ch - 8); 1936 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 1937 ntx, RTW89_RS_MCS, ch + 8); 1938 1939 for (i = 0; i < RTW89_BF_NUM; i++) 1940 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1941 } 1942 1943 static 1944 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev, 1945 const struct rtw89_chan *chan, 1946 struct rtw89_txpwr_limit_ax *lmt, 1947 u8 ntx) 1948 { 1949 u8 band = chan->band_type; 1950 u8 pri_ch = chan->primary_channel; 1951 u8 ch = chan->channel; 1952 u8 bw = chan->band_width; 1953 1954 memset(lmt, 0, sizeof(*lmt)); 1955 1956 switch (bw) { 1957 case RTW89_CHANNEL_WIDTH_20: 1958 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch); 1959 break; 1960 case RTW89_CHANNEL_WIDTH_40: 1961 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch, 1962 pri_ch); 1963 break; 1964 case RTW89_CHANNEL_WIDTH_80: 1965 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch, 1966 pri_ch); 1967 break; 1968 case RTW89_CHANNEL_WIDTH_160: 1969 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch, 1970 pri_ch); 1971 break; 1972 } 1973 } 1974 1975 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 1976 u8 ru, u8 ntx, u8 ch) 1977 { 1978 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1979 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 1980 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 1981 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 1982 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1983 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 1984 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 1985 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1986 u8 regd = rtw89_regd_get(rtwdev, band); 1987 u8 reg6 = regulatory->reg_6ghz_power; 1988 s8 lmt_ru = 0, sar; 1989 1990 switch (band) { 1991 case RTW89_BAND_2G: 1992 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 1993 if (lmt_ru) 1994 break; 1995 1996 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 1997 break; 1998 case RTW89_BAND_5G: 1999 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 2000 if (lmt_ru) 2001 break; 2002 2003 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 2004 break; 2005 case RTW89_BAND_6G: 2006 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx]; 2007 if (lmt_ru) 2008 break; 2009 2010 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW] 2011 [RTW89_REG_6GHZ_POWER_DFLT] 2012 [ch_idx]; 2013 break; 2014 default: 2015 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 2016 return 0; 2017 } 2018 2019 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 2020 sar = rtw89_query_sar(rtwdev, freq); 2021 2022 return min(lmt_ru, sar); 2023 } 2024 2025 static void 2026 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev, 2027 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2028 u8 band, u8 ntx, u8 ch) 2029 { 2030 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2031 RTW89_RU26, 2032 ntx, ch); 2033 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2034 RTW89_RU52, 2035 ntx, ch); 2036 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2037 RTW89_RU106, 2038 ntx, ch); 2039 } 2040 2041 static void 2042 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev, 2043 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2044 u8 band, u8 ntx, u8 ch) 2045 { 2046 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2047 RTW89_RU26, 2048 ntx, ch - 2); 2049 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2050 RTW89_RU26, 2051 ntx, ch + 2); 2052 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2053 RTW89_RU52, 2054 ntx, ch - 2); 2055 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2056 RTW89_RU52, 2057 ntx, ch + 2); 2058 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2059 RTW89_RU106, 2060 ntx, ch - 2); 2061 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2062 RTW89_RU106, 2063 ntx, ch + 2); 2064 } 2065 2066 static void 2067 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev, 2068 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2069 u8 band, u8 ntx, u8 ch) 2070 { 2071 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2072 RTW89_RU26, 2073 ntx, ch - 6); 2074 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2075 RTW89_RU26, 2076 ntx, ch - 2); 2077 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2078 RTW89_RU26, 2079 ntx, ch + 2); 2080 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2081 RTW89_RU26, 2082 ntx, ch + 6); 2083 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2084 RTW89_RU52, 2085 ntx, ch - 6); 2086 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2087 RTW89_RU52, 2088 ntx, ch - 2); 2089 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2090 RTW89_RU52, 2091 ntx, ch + 2); 2092 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2093 RTW89_RU52, 2094 ntx, ch + 6); 2095 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2096 RTW89_RU106, 2097 ntx, ch - 6); 2098 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2099 RTW89_RU106, 2100 ntx, ch - 2); 2101 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2102 RTW89_RU106, 2103 ntx, ch + 2); 2104 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2105 RTW89_RU106, 2106 ntx, ch + 6); 2107 } 2108 2109 static void 2110 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev, 2111 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2112 u8 band, u8 ntx, u8 ch) 2113 { 2114 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 2115 int i; 2116 2117 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX); 2118 for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) { 2119 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2120 RTW89_RU26, 2121 ntx, 2122 ch + ofst[i]); 2123 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2124 RTW89_RU52, 2125 ntx, 2126 ch + ofst[i]); 2127 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2128 RTW89_RU106, 2129 ntx, 2130 ch + ofst[i]); 2131 } 2132 } 2133 2134 static 2135 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2136 const struct rtw89_chan *chan, 2137 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2138 u8 ntx) 2139 { 2140 u8 band = chan->band_type; 2141 u8 ch = chan->channel; 2142 u8 bw = chan->band_width; 2143 2144 memset(lmt_ru, 0, sizeof(*lmt_ru)); 2145 2146 switch (bw) { 2147 case RTW89_CHANNEL_WIDTH_20: 2148 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx, 2149 ch); 2150 break; 2151 case RTW89_CHANNEL_WIDTH_40: 2152 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx, 2153 ch); 2154 break; 2155 case RTW89_CHANNEL_WIDTH_80: 2156 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx, 2157 ch); 2158 break; 2159 case RTW89_CHANNEL_WIDTH_160: 2160 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx, 2161 ch); 2162 break; 2163 } 2164 } 2165 2166 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev, 2167 const struct rtw89_chan *chan, 2168 enum rtw89_phy_idx phy_idx) 2169 { 2170 u8 max_nss_num = rtwdev->chip->rf_path_num; 2171 static const u8 rs[] = { 2172 RTW89_RS_CCK, 2173 RTW89_RS_OFDM, 2174 RTW89_RS_MCS, 2175 RTW89_RS_HEDCM, 2176 }; 2177 struct rtw89_rate_desc cur = {}; 2178 u8 band = chan->band_type; 2179 u8 ch = chan->channel; 2180 u32 addr, val; 2181 s8 v[4] = {}; 2182 u8 i; 2183 2184 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2185 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 2186 2187 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4); 2188 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4); 2189 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4); 2190 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4); 2191 2192 addr = R_AX_PWR_BY_RATE; 2193 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) { 2194 for (i = 0; i < ARRAY_SIZE(rs); i++) { 2195 if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]]) 2196 continue; 2197 2198 cur.rs = rs[i]; 2199 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]]; 2200 cur.idx++) { 2201 v[cur.idx % 4] = 2202 rtw89_phy_read_txpwr_byrate(rtwdev, 2203 band, 0, 2204 &cur); 2205 2206 if ((cur.idx + 1) % 4) 2207 continue; 2208 2209 val = FIELD_PREP(GENMASK(7, 0), v[0]) | 2210 FIELD_PREP(GENMASK(15, 8), v[1]) | 2211 FIELD_PREP(GENMASK(23, 16), v[2]) | 2212 FIELD_PREP(GENMASK(31, 24), v[3]); 2213 2214 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 2215 val); 2216 addr += 4; 2217 } 2218 } 2219 } 2220 } 2221 2222 static 2223 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev, 2224 const struct rtw89_chan *chan, 2225 enum rtw89_phy_idx phy_idx) 2226 { 2227 struct rtw89_rate_desc desc = { 2228 .nss = RTW89_NSS_1, 2229 .rs = RTW89_RS_OFFSET, 2230 }; 2231 u8 band = chan->band_type; 2232 s8 v[RTW89_RATE_OFFSET_NUM_AX] = {}; 2233 u32 val; 2234 2235 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 2236 2237 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_AX; desc.idx++) 2238 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc); 2239 2240 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM_AX != 5); 2241 val = FIELD_PREP(GENMASK(3, 0), v[0]) | 2242 FIELD_PREP(GENMASK(7, 4), v[1]) | 2243 FIELD_PREP(GENMASK(11, 8), v[2]) | 2244 FIELD_PREP(GENMASK(15, 12), v[3]) | 2245 FIELD_PREP(GENMASK(19, 16), v[4]); 2246 2247 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 2248 GENMASK(19, 0), val); 2249 } 2250 2251 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev, 2252 const struct rtw89_chan *chan, 2253 enum rtw89_phy_idx phy_idx) 2254 { 2255 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2256 struct rtw89_txpwr_limit_ax lmt; 2257 u8 ch = chan->channel; 2258 u8 bw = chan->band_width; 2259 const s8 *ptr; 2260 u32 addr, val; 2261 u8 i, j; 2262 2263 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2264 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 2265 2266 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ax) != 2267 RTW89_TXPWR_LMT_PAGE_SIZE_AX); 2268 2269 addr = R_AX_PWR_LMT; 2270 for (i = 0; i < max_ntx_num; i++) { 2271 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i); 2272 2273 ptr = (s8 *)&lmt; 2274 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_AX; 2275 j += 4, addr += 4, ptr += 4) { 2276 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2277 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2278 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2279 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2280 2281 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2282 } 2283 } 2284 } 2285 2286 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2287 const struct rtw89_chan *chan, 2288 enum rtw89_phy_idx phy_idx) 2289 { 2290 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2291 struct rtw89_txpwr_limit_ru_ax lmt_ru; 2292 u8 ch = chan->channel; 2293 u8 bw = chan->band_width; 2294 const s8 *ptr; 2295 u32 addr, val; 2296 u8 i, j; 2297 2298 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2299 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 2300 2301 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) != 2302 RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX); 2303 2304 addr = R_AX_PWR_RU_LMT; 2305 for (i = 0; i < max_ntx_num; i++) { 2306 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i); 2307 2308 ptr = (s8 *)&lmt_ru; 2309 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX; 2310 j += 4, addr += 4, ptr += 4) { 2311 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2312 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2313 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2314 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2315 2316 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2317 } 2318 } 2319 } 2320 2321 struct rtw89_phy_iter_ra_data { 2322 struct rtw89_dev *rtwdev; 2323 struct sk_buff *c2h; 2324 }; 2325 2326 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 2327 { 2328 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 2329 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2330 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2331 const struct rtw89_c2h_ra_rpt *c2h = 2332 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data; 2333 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 2334 const struct rtw89_chip_info *chip = rtwdev->chip; 2335 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE; 2336 u8 mode, rate, bw, giltf, mac_id; 2337 u16 legacy_bitrate; 2338 bool valid; 2339 u8 mcs = 0; 2340 u8 t; 2341 2342 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID); 2343 if (mac_id != rtwsta->mac_id) 2344 return; 2345 2346 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS); 2347 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW); 2348 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF); 2349 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL); 2350 2351 if (format_v1) { 2352 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7); 2353 rate |= u8_encode_bits(t, BIT(7)); 2354 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2); 2355 bw |= u8_encode_bits(t, BIT(2)); 2356 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2); 2357 mode |= u8_encode_bits(t, BIT(2)); 2358 } 2359 2360 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2361 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2362 if (!valid) 2363 return; 2364 } 2365 2366 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2367 2368 switch (mode) { 2369 case RTW89_RA_RPT_MODE_LEGACY: 2370 ra_report->txrate.legacy = legacy_bitrate; 2371 break; 2372 case RTW89_RA_RPT_MODE_HT: 2373 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2374 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2375 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2376 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2377 else 2378 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2379 ra_report->txrate.mcs = rate; 2380 if (giltf) 2381 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2382 mcs = ra_report->txrate.mcs & 0x07; 2383 break; 2384 case RTW89_RA_RPT_MODE_VHT: 2385 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2386 ra_report->txrate.mcs = format_v1 ? 2387 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2388 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2389 ra_report->txrate.nss = format_v1 ? 2390 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2391 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2392 if (giltf) 2393 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2394 mcs = ra_report->txrate.mcs; 2395 break; 2396 case RTW89_RA_RPT_MODE_HE: 2397 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2398 ra_report->txrate.mcs = format_v1 ? 2399 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2400 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2401 ra_report->txrate.nss = format_v1 ? 2402 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2403 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2404 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2405 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2406 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2407 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2408 else 2409 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2410 mcs = ra_report->txrate.mcs; 2411 break; 2412 case RTW89_RA_RPT_MODE_EHT: 2413 ra_report->txrate.flags |= RATE_INFO_FLAGS_EHT_MCS; 2414 ra_report->txrate.mcs = u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1); 2415 ra_report->txrate.nss = u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1; 2416 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2417 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_0_8; 2418 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2419 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_1_6; 2420 else 2421 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_3_2; 2422 mcs = ra_report->txrate.mcs; 2423 break; 2424 } 2425 2426 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2427 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2428 ra_report->hw_rate = format_v1 ? 2429 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) | 2430 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) : 2431 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) | 2432 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL); 2433 ra_report->might_fallback_legacy = mcs <= 2; 2434 sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2435 rtwsta->max_agg_wait = sta->deflink.agg.max_rc_amsdu_len / 1500 - 1; 2436 } 2437 2438 static void 2439 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2440 { 2441 struct rtw89_phy_iter_ra_data ra_data; 2442 2443 ra_data.rtwdev = rtwdev; 2444 ra_data.c2h = c2h; 2445 ieee80211_iterate_stations_atomic(rtwdev->hw, 2446 rtw89_phy_c2h_ra_rpt_iter, 2447 &ra_data); 2448 } 2449 2450 static 2451 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2452 struct sk_buff *c2h, u32 len) = { 2453 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2454 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2455 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2456 }; 2457 2458 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, 2459 enum rtw89_phy_c2h_rfk_log_func func, 2460 void *content, u16 len) 2461 { 2462 struct rtw89_c2h_rf_txgapk_rpt_log *txgapk; 2463 struct rtw89_c2h_rf_rxdck_rpt_log *rxdck; 2464 struct rtw89_c2h_rf_dack_rpt_log *dack; 2465 struct rtw89_c2h_rf_dpk_rpt_log *dpk; 2466 2467 switch (func) { 2468 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: 2469 if (len != sizeof(*dpk)) 2470 goto out; 2471 2472 dpk = content; 2473 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2474 "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n", 2475 dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok); 2476 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2477 "DPK txagc:%2ph ther:%2ph gs:%2ph dc_i:%4ph dc_q:%4ph\n", 2478 dpk->txagc, dpk->ther, dpk->gs, dpk->dc_i, dpk->dc_q); 2479 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2480 "DPK corr_v:%2ph corr_i:%2ph to:%2ph ov:%2ph\n", 2481 dpk->corr_val, dpk->corr_idx, dpk->is_timeout, dpk->rxbb_ov); 2482 return; 2483 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK: 2484 if (len != sizeof(*dack)) 2485 goto out; 2486 2487 dack = content; 2488 2489 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ver=0x%x 0x%x\n", 2490 dack->fwdack_ver, dack->fwdack_rpt_ver); 2491 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK ic = [0x%x, 0x%x]\n", 2492 dack->cdack_d[0][0][0], dack->cdack_d[0][0][1]); 2493 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK qc = [0x%x, 0x%x]\n", 2494 dack->cdack_d[0][1][0], dack->cdack_d[0][1][1]); 2495 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK ic = [0x%x, 0x%x]\n", 2496 dack->cdack_d[1][0][0], dack->cdack_d[1][0][1]); 2497 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK qc = [0x%x, 0x%x]\n", 2498 dack->cdack_d[1][1][0], dack->cdack_d[1][1][1]); 2499 2500 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = [0x%x, 0x%x]\n", 2501 dack->addck2_d[0][0][0], dack->addck2_d[0][0][1]); 2502 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK qc = [0x%x, 0x%x]\n", 2503 dack->addck2_d[0][1][0], dack->addck2_d[0][1][1]); 2504 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK ic = [0x%x, 0x%x]\n", 2505 dack->addck2_d[1][0][0], dack->addck2_d[1][0][1]); 2506 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK qc = [0x%x, 0x%x]\n", 2507 dack->addck2_d[1][1][0], dack->addck2_d[1][1][1]); 2508 2509 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_GAINK ic = 0x%x, qc = 0x%x\n", 2510 dack->adgaink_d[0][0], dack->adgaink_d[0][1]); 2511 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_GAINK ic = 0x%x, qc = 0x%x\n", 2512 dack->adgaink_d[1][0], dack->adgaink_d[1][1]); 2513 2514 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n", 2515 dack->dadck_d[0][0], dack->dadck_d[0][1]); 2516 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n", 2517 dack->dadck_d[1][0], dack->dadck_d[1][1]); 2518 2519 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask iqc = 0x%x\n", 2520 dack->biask_d[0][0]); 2521 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 biask iqc = 0x%x\n", 2522 dack->biask_d[1][0]); 2523 2524 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic: %*ph\n", 2525 (int)sizeof(dack->msbk_d[0][0]), dack->msbk_d[0][0]); 2526 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc: %*ph\n", 2527 (int)sizeof(dack->msbk_d[0][1]), dack->msbk_d[0][1]); 2528 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic: %*ph\n", 2529 (int)sizeof(dack->msbk_d[1][0]), dack->msbk_d[1][0]); 2530 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc: %*ph\n", 2531 (int)sizeof(dack->msbk_d[1][1]), dack->msbk_d[1][1]); 2532 return; 2533 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: 2534 if (len != sizeof(*rxdck)) 2535 goto out; 2536 2537 rxdck = content; 2538 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2539 "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n", 2540 rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch, 2541 rxdck->timeout); 2542 return; 2543 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: 2544 if (len != sizeof(*txgapk)) 2545 goto out; 2546 2547 txgapk = content; 2548 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2549 "[TXGAPK]rpt r0x8010[0]=0x%x, r0x8010[1]=0x%x\n", 2550 le32_to_cpu(txgapk->r0x8010[0]), 2551 le32_to_cpu(txgapk->r0x8010[1])); 2552 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_id = %d\n", 2553 txgapk->chk_id); 2554 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_cnt = %d\n", 2555 le32_to_cpu(txgapk->chk_cnt)); 2556 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n", 2557 txgapk->ver); 2558 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n", 2559 txgapk->rsv1); 2560 2561 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n", 2562 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]); 2563 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[0] = %*ph\n", 2564 (int)sizeof(txgapk->power_d[0]), txgapk->power_d[0]); 2565 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[1] = %*ph\n", 2566 (int)sizeof(txgapk->track_d[1]), txgapk->track_d[1]); 2567 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n", 2568 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]); 2569 return; 2570 default: 2571 break; 2572 } 2573 2574 out: 2575 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2576 "unexpected RFK func %d report log with length %d\n", func, len); 2577 } 2578 2579 static bool rtw89_phy_c2h_rfk_run_log(struct rtw89_dev *rtwdev, 2580 enum rtw89_phy_c2h_rfk_log_func func, 2581 void *content, u16 len) 2582 { 2583 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 2584 const struct rtw89_c2h_rf_run_log *log = content; 2585 const struct rtw89_fw_element_hdr *elm; 2586 u32 fmt_idx; 2587 u16 offset; 2588 2589 if (sizeof(*log) != len) 2590 return false; 2591 2592 if (!elm_info->rfk_log_fmt) 2593 return false; 2594 2595 elm = elm_info->rfk_log_fmt->elm[func]; 2596 fmt_idx = le32_to_cpu(log->fmt_idx); 2597 if (!elm || fmt_idx >= elm->u.rfk_log_fmt.nr) 2598 return false; 2599 2600 offset = le16_to_cpu(elm->u.rfk_log_fmt.offset[fmt_idx]); 2601 if (offset == 0) 2602 return false; 2603 2604 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset], 2605 le32_to_cpu(log->arg[0]), le32_to_cpu(log->arg[1]), 2606 le32_to_cpu(log->arg[2]), le32_to_cpu(log->arg[3])); 2607 2608 return true; 2609 } 2610 2611 static void rtw89_phy_c2h_rfk_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 2612 u32 len, enum rtw89_phy_c2h_rfk_log_func func, 2613 const char *rfk_name) 2614 { 2615 struct rtw89_c2h_hdr *c2h_hdr = (struct rtw89_c2h_hdr *)c2h->data; 2616 struct rtw89_c2h_rf_log_hdr *log_hdr; 2617 void *log_ptr = c2h_hdr; 2618 u16 content_len; 2619 u16 chunk_len; 2620 bool handled; 2621 2622 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK)) 2623 return; 2624 2625 log_ptr += sizeof(*c2h_hdr); 2626 len -= sizeof(*c2h_hdr); 2627 2628 while (len > sizeof(*log_hdr)) { 2629 log_hdr = log_ptr; 2630 content_len = le16_to_cpu(log_hdr->len); 2631 chunk_len = content_len + sizeof(*log_hdr); 2632 2633 if (chunk_len > len) 2634 break; 2635 2636 switch (log_hdr->type) { 2637 case RTW89_RF_RUN_LOG: 2638 handled = rtw89_phy_c2h_rfk_run_log(rtwdev, func, 2639 log_hdr->content, content_len); 2640 if (handled) 2641 break; 2642 2643 rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s run: %*ph\n", 2644 rfk_name, content_len, log_hdr->content); 2645 break; 2646 case RTW89_RF_RPT_LOG: 2647 rtw89_phy_c2h_rfk_rpt_log(rtwdev, func, 2648 log_hdr->content, content_len); 2649 break; 2650 default: 2651 return; 2652 } 2653 2654 log_ptr += chunk_len; 2655 len -= chunk_len; 2656 } 2657 } 2658 2659 static void 2660 rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2661 { 2662 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2663 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK, "IQK"); 2664 } 2665 2666 static void 2667 rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2668 { 2669 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2670 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK, "DPK"); 2671 } 2672 2673 static void 2674 rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2675 { 2676 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2677 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK, "DACK"); 2678 } 2679 2680 static void 2681 rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2682 { 2683 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2684 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK, "RX_DCK"); 2685 } 2686 2687 static void 2688 rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2689 { 2690 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2691 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI, "TSSI"); 2692 } 2693 2694 static void 2695 rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2696 { 2697 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2698 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK, "TXGAPK"); 2699 } 2700 2701 static 2702 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev, 2703 struct sk_buff *c2h, u32 len) = { 2704 [RTW89_PHY_C2H_RFK_LOG_FUNC_IQK] = rtw89_phy_c2h_rfk_log_iqk, 2705 [RTW89_PHY_C2H_RFK_LOG_FUNC_DPK] = rtw89_phy_c2h_rfk_log_dpk, 2706 [RTW89_PHY_C2H_RFK_LOG_FUNC_DACK] = rtw89_phy_c2h_rfk_log_dack, 2707 [RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK] = rtw89_phy_c2h_rfk_log_rxdck, 2708 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi, 2709 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk, 2710 }; 2711 2712 static void 2713 rtw89_phy_c2h_rfk_report_state(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2714 { 2715 } 2716 2717 static 2718 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev, 2719 struct sk_buff *c2h, u32 len) = { 2720 [RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE] = rtw89_phy_c2h_rfk_report_state, 2721 }; 2722 2723 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 2724 { 2725 switch (class) { 2726 case RTW89_PHY_C2H_RFK_LOG: 2727 switch (func) { 2728 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK: 2729 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: 2730 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK: 2731 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: 2732 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI: 2733 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: 2734 return true; 2735 default: 2736 return false; 2737 } 2738 case RTW89_PHY_C2H_RFK_REPORT: 2739 switch (func) { 2740 case RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE: 2741 return true; 2742 default: 2743 return false; 2744 } 2745 default: 2746 return false; 2747 } 2748 } 2749 2750 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2751 u32 len, u8 class, u8 func) 2752 { 2753 void (*handler)(struct rtw89_dev *rtwdev, 2754 struct sk_buff *c2h, u32 len) = NULL; 2755 2756 switch (class) { 2757 case RTW89_PHY_C2H_CLASS_RA: 2758 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 2759 handler = rtw89_phy_c2h_ra_handler[func]; 2760 break; 2761 case RTW89_PHY_C2H_RFK_LOG: 2762 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_log_handler)) 2763 handler = rtw89_phy_c2h_rfk_log_handler[func]; 2764 break; 2765 case RTW89_PHY_C2H_RFK_REPORT: 2766 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_report_handler)) 2767 handler = rtw89_phy_c2h_rfk_report_handler[func]; 2768 break; 2769 case RTW89_PHY_C2H_CLASS_DM: 2770 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY) 2771 return; 2772 fallthrough; 2773 default: 2774 rtw89_info(rtwdev, "c2h class %d not support\n", class); 2775 return; 2776 } 2777 if (!handler) { 2778 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 2779 func); 2780 return; 2781 } 2782 handler(rtwdev, skb, len); 2783 } 2784 2785 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 2786 { 2787 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 2788 u32 reg_mask; 2789 2790 if (sc_xo) 2791 reg_mask = xtal->sc_xo_mask; 2792 else 2793 reg_mask = xtal->sc_xi_mask; 2794 2795 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask); 2796 } 2797 2798 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 2799 u8 val) 2800 { 2801 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 2802 u32 reg_mask; 2803 2804 if (sc_xo) 2805 reg_mask = xtal->sc_xo_mask; 2806 else 2807 reg_mask = xtal->sc_xi_mask; 2808 2809 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val); 2810 } 2811 2812 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 2813 u8 crystal_cap, bool force) 2814 { 2815 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2816 const struct rtw89_chip_info *chip = rtwdev->chip; 2817 u8 sc_xi_val, sc_xo_val; 2818 2819 if (!force && cfo->crystal_cap == crystal_cap) 2820 return; 2821 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 2822 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) { 2823 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 2824 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 2825 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 2826 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 2827 } else { 2828 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 2829 crystal_cap, XTAL_SC_XO_MASK); 2830 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 2831 crystal_cap, XTAL_SC_XI_MASK); 2832 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 2833 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 2834 } 2835 cfo->crystal_cap = sc_xi_val; 2836 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 2837 2838 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 2839 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 2840 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 2841 cfo->x_cap_ofst); 2842 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 2843 } 2844 2845 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 2846 { 2847 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2848 u8 cap; 2849 2850 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 2851 cfo->is_adjust = false; 2852 if (cfo->crystal_cap == cfo->def_x_cap) 2853 return; 2854 cap = cfo->crystal_cap; 2855 cap += (cap > cfo->def_x_cap ? -1 : 1); 2856 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 2857 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2858 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 2859 cfo->def_x_cap); 2860 } 2861 2862 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 2863 { 2864 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 2865 bool is_linked = rtwdev->total_sta_assoc > 0; 2866 s32 cfo_avg_312; 2867 s32 dcfo_comp_val; 2868 int sign; 2869 2870 if (rtwdev->chip->chip_id == RTL8922A) 2871 return; 2872 2873 if (!is_linked) { 2874 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 2875 is_linked); 2876 return; 2877 } 2878 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 2879 if (curr_cfo == 0) 2880 return; 2881 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 2882 sign = curr_cfo > 0 ? 1 : -1; 2883 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val; 2884 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312); 2885 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2886 cfo_avg_312 = -cfo_avg_312; 2887 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 2888 cfo_avg_312); 2889 } 2890 2891 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 2892 { 2893 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 2894 const struct rtw89_chip_info *chip = rtwdev->chip; 2895 const struct rtw89_cfo_regs *cfo = phy->cfo; 2896 2897 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1); 2898 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8); 2899 2900 if (chip->chip_gen == RTW89_CHIP_AX) { 2901 if (chip->cfo_hw_comp) { 2902 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2, 2903 B_AX_PWR_UL_CFO_MASK, 0x6); 2904 } else { 2905 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 2906 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, 2907 B_AX_PWR_UL_CFO_MASK); 2908 } 2909 } 2910 } 2911 2912 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 2913 { 2914 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2915 struct rtw89_efuse *efuse = &rtwdev->efuse; 2916 2917 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 2918 cfo->crystal_cap = cfo->crystal_cap_default; 2919 cfo->def_x_cap = cfo->crystal_cap; 2920 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 2921 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 2922 cfo->is_adjust = false; 2923 cfo->divergence_lock_en = false; 2924 cfo->x_cap_ofst = 0; 2925 cfo->lock_cnt = 0; 2926 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 2927 cfo->apply_compensation = false; 2928 cfo->residual_cfo_acc = 0; 2929 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 2930 cfo->crystal_cap_default); 2931 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 2932 rtw89_dcfo_comp_init(rtwdev); 2933 cfo->cfo_timer_ms = 2000; 2934 cfo->cfo_trig_by_timer_en = false; 2935 cfo->phy_cfo_trk_cnt = 0; 2936 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2937 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 2938 } 2939 2940 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 2941 s32 curr_cfo) 2942 { 2943 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2944 s8 crystal_cap = cfo->crystal_cap; 2945 s32 cfo_abs = abs(curr_cfo); 2946 int sign; 2947 2948 if (curr_cfo == 0) { 2949 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2950 return; 2951 } 2952 if (!cfo->is_adjust) { 2953 if (cfo_abs > CFO_TRK_ENABLE_TH) 2954 cfo->is_adjust = true; 2955 } else { 2956 if (cfo_abs <= CFO_TRK_STOP_TH) 2957 cfo->is_adjust = false; 2958 } 2959 if (!cfo->is_adjust) { 2960 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 2961 return; 2962 } 2963 sign = curr_cfo > 0 ? 1 : -1; 2964 if (cfo_abs > CFO_TRK_STOP_TH_4) 2965 crystal_cap += 7 * sign; 2966 else if (cfo_abs > CFO_TRK_STOP_TH_3) 2967 crystal_cap += 5 * sign; 2968 else if (cfo_abs > CFO_TRK_STOP_TH_2) 2969 crystal_cap += 3 * sign; 2970 else if (cfo_abs > CFO_TRK_STOP_TH_1) 2971 crystal_cap += 1 * sign; 2972 else 2973 return; 2974 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 2975 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2976 "X_cap{Curr,Default}={0x%x,0x%x}\n", 2977 cfo->crystal_cap, cfo->def_x_cap); 2978 } 2979 2980 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 2981 { 2982 const struct rtw89_chip_info *chip = rtwdev->chip; 2983 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2984 s32 cfo_khz_all = 0; 2985 s32 cfo_cnt_all = 0; 2986 s32 cfo_all_avg = 0; 2987 u8 i; 2988 2989 if (rtwdev->total_sta_assoc != 1) 2990 return 0; 2991 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 2992 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2993 if (cfo->cfo_cnt[i] == 0) 2994 continue; 2995 cfo_khz_all += cfo->cfo_tail[i]; 2996 cfo_cnt_all += cfo->cfo_cnt[i]; 2997 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 2998 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2999 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft, 3000 cfo_cnt_all); 3001 } 3002 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3003 "CFO track for macid = %d\n", i); 3004 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3005 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 3006 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 3007 return cfo_all_avg; 3008 } 3009 3010 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 3011 { 3012 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3013 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3014 s32 target_cfo = 0; 3015 s32 cfo_khz_all = 0; 3016 s32 cfo_khz_all_tp_wgt = 0; 3017 s32 cfo_avg = 0; 3018 s32 max_cfo_lb = BIT(31); 3019 s32 min_cfo_ub = GENMASK(30, 0); 3020 u16 cfo_cnt_all = 0; 3021 u8 active_entry_cnt = 0; 3022 u8 sta_cnt = 0; 3023 u32 tp_all = 0; 3024 u8 i; 3025 u8 cfo_tol = 0; 3026 3027 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 3028 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 3029 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 3030 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 3031 if (cfo->cfo_cnt[i] == 0) 3032 continue; 3033 cfo_khz_all += cfo->cfo_tail[i]; 3034 cfo_cnt_all += cfo->cfo_cnt[i]; 3035 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 3036 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3037 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 3038 cfo_khz_all, cfo_cnt_all, cfo_avg); 3039 target_cfo = cfo_avg; 3040 } 3041 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 3042 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 3043 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 3044 if (cfo->cfo_cnt[i] == 0) 3045 continue; 3046 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 3047 (s32)cfo->cfo_cnt[i]); 3048 cfo_khz_all += cfo->cfo_avg[i]; 3049 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3050 "Macid=%d, cfo_avg=%d\n", i, 3051 cfo->cfo_avg[i]); 3052 } 3053 sta_cnt = rtwdev->total_sta_assoc; 3054 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 3055 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3056 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 3057 cfo_khz_all, sta_cnt, cfo_avg); 3058 target_cfo = cfo_avg; 3059 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 3060 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 3061 cfo_tol = cfo->sta_cfo_tolerance; 3062 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 3063 sta_cnt++; 3064 if (cfo->cfo_cnt[i] != 0) { 3065 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 3066 (s32)cfo->cfo_cnt[i]); 3067 active_entry_cnt++; 3068 } else { 3069 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 3070 } 3071 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 3072 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 3073 cfo_khz_all += cfo->cfo_avg[i]; 3074 /* need tp for each entry */ 3075 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3076 "[%d] cfo_avg=%d, tp=tbd\n", 3077 i, cfo->cfo_avg[i]); 3078 if (sta_cnt >= rtwdev->total_sta_assoc) 3079 break; 3080 } 3081 tp_all = stats->rx_throughput; /* need tp for each entry */ 3082 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 3083 3084 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 3085 sta_cnt); 3086 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 3087 active_entry_cnt); 3088 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3089 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 3090 cfo_khz_all_tp_wgt, cfo_avg); 3091 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 3092 max_cfo_lb, min_cfo_ub); 3093 if (max_cfo_lb <= min_cfo_ub) { 3094 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3095 "cfo win_size=%d\n", 3096 min_cfo_ub - max_cfo_lb); 3097 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 3098 } else { 3099 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3100 "No intersection of cfo tolerance windows\n"); 3101 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 3102 } 3103 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 3104 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 3105 } 3106 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 3107 return target_cfo; 3108 } 3109 3110 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 3111 { 3112 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3113 3114 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 3115 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 3116 cfo->packet_count = 0; 3117 cfo->packet_count_pre = 0; 3118 cfo->cfo_avg_pre = 0; 3119 } 3120 3121 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 3122 { 3123 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3124 s32 new_cfo = 0; 3125 bool x_cap_update = false; 3126 u8 pre_x_cap = cfo->crystal_cap; 3127 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 3128 3129 cfo->dcfo_avg = 0; 3130 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 3131 rtwdev->total_sta_assoc); 3132 if (rtwdev->total_sta_assoc == 0) { 3133 rtw89_phy_cfo_reset(rtwdev); 3134 return; 3135 } 3136 if (cfo->packet_count == 0) { 3137 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 3138 return; 3139 } 3140 if (cfo->packet_count == cfo->packet_count_pre) { 3141 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 3142 return; 3143 } 3144 if (rtwdev->total_sta_assoc == 1) 3145 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 3146 else 3147 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 3148 if (cfo->divergence_lock_en) { 3149 cfo->lock_cnt++; 3150 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 3151 cfo->divergence_lock_en = false; 3152 cfo->lock_cnt = 0; 3153 } else { 3154 rtw89_phy_cfo_reset(rtwdev); 3155 } 3156 return; 3157 } 3158 if (cfo->crystal_cap >= cfo->x_cap_ub || 3159 cfo->crystal_cap <= cfo->x_cap_lb) { 3160 cfo->divergence_lock_en = true; 3161 rtw89_phy_cfo_reset(rtwdev); 3162 return; 3163 } 3164 3165 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 3166 cfo->cfo_avg_pre = new_cfo; 3167 cfo->dcfo_avg_pre = cfo->dcfo_avg; 3168 x_cap_update = cfo->crystal_cap != pre_x_cap; 3169 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 3170 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 3171 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 3172 cfo->x_cap_ofst); 3173 if (x_cap_update) { 3174 if (cfo->dcfo_avg > 0) 3175 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 3176 else 3177 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 3178 } 3179 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg); 3180 rtw89_phy_cfo_statistics_reset(rtwdev); 3181 } 3182 3183 void rtw89_phy_cfo_track_work(struct work_struct *work) 3184 { 3185 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3186 cfo_track_work.work); 3187 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3188 3189 mutex_lock(&rtwdev->mutex); 3190 if (!cfo->cfo_trig_by_timer_en) 3191 goto out; 3192 rtw89_leave_ps_mode(rtwdev); 3193 rtw89_phy_cfo_dm(rtwdev); 3194 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 3195 msecs_to_jiffies(cfo->cfo_timer_ms)); 3196 out: 3197 mutex_unlock(&rtwdev->mutex); 3198 } 3199 3200 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 3201 { 3202 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3203 3204 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 3205 msecs_to_jiffies(cfo->cfo_timer_ms)); 3206 } 3207 3208 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 3209 { 3210 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3211 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3212 bool is_ul_ofdma = false, ofdma_acc_en = false; 3213 3214 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 3215 is_ul_ofdma = true; 3216 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 3217 is_ul_ofdma) 3218 ofdma_acc_en = true; 3219 3220 switch (cfo->phy_cfo_status) { 3221 case RTW89_PHY_DCFO_STATE_NORMAL: 3222 if (stats->tx_throughput >= CFO_TP_UPPER) { 3223 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 3224 cfo->cfo_trig_by_timer_en = true; 3225 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 3226 rtw89_phy_cfo_start_work(rtwdev); 3227 } 3228 break; 3229 case RTW89_PHY_DCFO_STATE_ENHANCE: 3230 if (stats->tx_throughput <= CFO_TP_LOWER) 3231 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 3232 else if (ofdma_acc_en && 3233 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 3234 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 3235 else 3236 cfo->phy_cfo_trk_cnt++; 3237 3238 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 3239 cfo->phy_cfo_trk_cnt = 0; 3240 cfo->cfo_trig_by_timer_en = false; 3241 } 3242 break; 3243 case RTW89_PHY_DCFO_STATE_HOLD: 3244 if (stats->tx_throughput <= CFO_TP_LOWER) { 3245 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 3246 cfo->phy_cfo_trk_cnt = 0; 3247 cfo->cfo_trig_by_timer_en = false; 3248 } else { 3249 cfo->phy_cfo_trk_cnt++; 3250 } 3251 break; 3252 default: 3253 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 3254 cfo->phy_cfo_trk_cnt = 0; 3255 break; 3256 } 3257 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3258 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 3259 stats->tx_throughput, cfo->phy_cfo_status, 3260 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 3261 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 3262 if (cfo->cfo_trig_by_timer_en) 3263 return; 3264 rtw89_phy_cfo_dm(rtwdev); 3265 } 3266 3267 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 3268 struct rtw89_rx_phy_ppdu *phy_ppdu) 3269 { 3270 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3271 u8 macid = phy_ppdu->mac_id; 3272 3273 if (macid >= CFO_TRACK_MAX_USER) { 3274 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 3275 return; 3276 } 3277 3278 cfo->cfo_tail[macid] += cfo_val; 3279 cfo->cfo_cnt[macid]++; 3280 cfo->packet_count++; 3281 } 3282 3283 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3284 { 3285 const struct rtw89_chip_info *chip = rtwdev->chip; 3286 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 3287 rtwvif->sub_entity_idx); 3288 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 3289 3290 if (!chip->ul_tb_waveform_ctrl) 3291 return; 3292 3293 rtwvif->def_tri_idx = 3294 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG); 3295 3296 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV) 3297 rtwvif->dyn_tb_bedge_en = false; 3298 else if (chan->band_type >= RTW89_BAND_5G && 3299 chan->band_width >= RTW89_CHANNEL_WIDTH_40) 3300 rtwvif->dyn_tb_bedge_en = true; 3301 else 3302 rtwvif->dyn_tb_bedge_en = false; 3303 3304 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 3305 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n", 3306 ul_tb_info->def_if_bandedge, rtwvif->def_tri_idx); 3307 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 3308 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n", 3309 rtwvif->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en); 3310 } 3311 3312 struct rtw89_phy_ul_tb_check_data { 3313 bool valid; 3314 bool high_tf_client; 3315 bool low_tf_client; 3316 bool dyn_tb_bedge_en; 3317 u8 def_tri_idx; 3318 }; 3319 3320 struct rtw89_phy_power_diff { 3321 u32 q_00; 3322 u32 q_11; 3323 u32 q_matrix_en; 3324 u32 ultb_1t_norm_160; 3325 u32 ultb_2t_norm_160; 3326 u32 com1_norm_1sts; 3327 u32 com2_resp_1sts_path; 3328 }; 3329 3330 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev, 3331 struct rtw89_vif *rtwvif) 3332 { 3333 static const struct rtw89_phy_power_diff table[2] = { 3334 {0x0, 0x0, 0x0, 0x0, 0xf4, 0x3, 0x3}, 3335 {0xb50, 0xb50, 0x1, 0xc, 0x0, 0x1, 0x1}, 3336 }; 3337 const struct rtw89_phy_power_diff *param; 3338 u32 reg; 3339 3340 if (!rtwdev->chip->ul_tb_pwr_diff) 3341 return; 3342 3343 if (rtwvif->pwr_diff_en == rtwvif->pre_pwr_diff_en) { 3344 rtwvif->pwr_diff_en = false; 3345 return; 3346 } 3347 3348 rtwvif->pre_pwr_diff_en = rtwvif->pwr_diff_en; 3349 param = &table[rtwvif->pwr_diff_en]; 3350 3351 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL, 3352 param->q_00); 3353 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL, 3354 param->q_11); 3355 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX, 3356 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en); 3357 3358 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif->mac_idx); 3359 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160, 3360 param->ultb_1t_norm_160); 3361 3362 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif->mac_idx); 3363 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160, 3364 param->ultb_2t_norm_160); 3365 3366 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif->mac_idx); 3367 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS, 3368 param->com1_norm_1sts); 3369 3370 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif->mac_idx); 3371 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH, 3372 param->com2_resp_1sts_path); 3373 } 3374 3375 static 3376 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev, 3377 struct rtw89_vif *rtwvif, 3378 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 3379 { 3380 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3381 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3382 3383 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 3384 return; 3385 3386 if (!vif->cfg.assoc) 3387 return; 3388 3389 if (rtwdev->chip->ul_tb_waveform_ctrl) { 3390 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH) 3391 ul_tb_data->high_tf_client = true; 3392 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH) 3393 ul_tb_data->low_tf_client = true; 3394 3395 ul_tb_data->valid = true; 3396 ul_tb_data->def_tri_idx = rtwvif->def_tri_idx; 3397 ul_tb_data->dyn_tb_bedge_en = rtwvif->dyn_tb_bedge_en; 3398 } 3399 3400 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif); 3401 } 3402 3403 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev, 3404 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 3405 { 3406 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 3407 3408 if (!rtwdev->chip->ul_tb_waveform_ctrl) 3409 return; 3410 3411 if (ul_tb_data->dyn_tb_bedge_en) { 3412 if (ul_tb_data->high_tf_client) { 3413 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0); 3414 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 3415 "[ULTB] Turn off if_bandedge\n"); 3416 } else if (ul_tb_data->low_tf_client) { 3417 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 3418 ul_tb_info->def_if_bandedge); 3419 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 3420 "[ULTB] Set to default if_bandedge = %d\n", 3421 ul_tb_info->def_if_bandedge); 3422 } 3423 } 3424 3425 if (ul_tb_info->dyn_tb_tri_en) { 3426 if (ul_tb_data->high_tf_client) { 3427 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 3428 B_TXSHAPE_TRIANGULAR_CFG, 0); 3429 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 3430 "[ULTB] Turn off Tx triangle\n"); 3431 } else if (ul_tb_data->low_tf_client) { 3432 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 3433 B_TXSHAPE_TRIANGULAR_CFG, 3434 ul_tb_data->def_tri_idx); 3435 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 3436 "[ULTB] Set to default tx_shap_idx = %d\n", 3437 ul_tb_data->def_tri_idx); 3438 } 3439 } 3440 } 3441 3442 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev) 3443 { 3444 const struct rtw89_chip_info *chip = rtwdev->chip; 3445 struct rtw89_phy_ul_tb_check_data ul_tb_data = {}; 3446 struct rtw89_vif *rtwvif; 3447 3448 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff) 3449 return; 3450 3451 if (rtwdev->total_sta_assoc != 1) 3452 return; 3453 3454 rtw89_for_each_rtwvif(rtwdev, rtwvif) 3455 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data); 3456 3457 if (!ul_tb_data.valid) 3458 return; 3459 3460 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data); 3461 } 3462 3463 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev) 3464 { 3465 const struct rtw89_chip_info *chip = rtwdev->chip; 3466 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 3467 3468 if (!chip->ul_tb_waveform_ctrl) 3469 return; 3470 3471 ul_tb_info->dyn_tb_tri_en = true; 3472 ul_tb_info->def_if_bandedge = 3473 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN); 3474 } 3475 3476 static 3477 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts) 3478 { 3479 ewma_rssi_init(&antdiv_sts->cck_rssi_avg); 3480 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg); 3481 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg); 3482 antdiv_sts->pkt_cnt_cck = 0; 3483 antdiv_sts->pkt_cnt_ofdm = 0; 3484 antdiv_sts->pkt_cnt_non_legacy = 0; 3485 antdiv_sts->evm = 0; 3486 } 3487 3488 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev, 3489 struct rtw89_rx_phy_ppdu *phy_ppdu, 3490 struct rtw89_antdiv_stats *stats) 3491 { 3492 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) { 3493 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) { 3494 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg); 3495 stats->pkt_cnt_cck++; 3496 } else { 3497 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg); 3498 stats->pkt_cnt_ofdm++; 3499 stats->evm += phy_ppdu->ofdm.evm_min; 3500 } 3501 } else { 3502 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg); 3503 stats->pkt_cnt_non_legacy++; 3504 stats->evm += phy_ppdu->ofdm.evm_min; 3505 } 3506 } 3507 3508 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats) 3509 { 3510 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck && 3511 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm) 3512 return ewma_rssi_read(&stats->non_legacy_rssi_avg); 3513 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck && 3514 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy) 3515 return ewma_rssi_read(&stats->ofdm_rssi_avg); 3516 else 3517 return ewma_rssi_read(&stats->cck_rssi_avg); 3518 } 3519 3520 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats) 3521 { 3522 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm); 3523 } 3524 3525 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 3526 struct rtw89_rx_phy_ppdu *phy_ppdu) 3527 { 3528 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3529 struct rtw89_hal *hal = &rtwdev->hal; 3530 3531 if (!hal->ant_diversity || hal->ant_diversity_fixed) 3532 return; 3533 3534 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats); 3535 3536 if (!antdiv->get_stats) 3537 return; 3538 3539 if (hal->antenna_rx == RF_A) 3540 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats); 3541 else if (hal->antenna_rx == RF_B) 3542 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats); 3543 } 3544 3545 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev) 3546 { 3547 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN, 3548 0x0, RTW89_PHY_0); 3549 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL, 3550 0x0, RTW89_PHY_0); 3551 3552 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND, 3553 0x0, RTW89_PHY_0); 3554 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT, 3555 0x0, RTW89_PHY_0); 3556 3557 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN, 3558 0x0, RTW89_PHY_0); 3559 3560 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING, 3561 0x0100, RTW89_PHY_0); 3562 3563 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX, 3564 0x1, RTW89_PHY_0); 3565 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL, 3566 0x0, RTW89_PHY_0); 3567 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G, 3568 0x0, RTW89_PHY_0); 3569 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G, 3570 0x0, RTW89_PHY_0); 3571 } 3572 3573 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev) 3574 { 3575 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3576 3577 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 3578 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats); 3579 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats); 3580 } 3581 3582 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev) 3583 { 3584 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3585 struct rtw89_hal *hal = &rtwdev->hal; 3586 3587 if (!hal->ant_diversity) 3588 return; 3589 3590 antdiv->get_stats = false; 3591 antdiv->rssi_pre = 0; 3592 rtw89_phy_antdiv_sts_reset(rtwdev); 3593 rtw89_phy_antdiv_reg_init(rtwdev); 3594 } 3595 3596 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 3597 { 3598 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3599 int i; 3600 u8 th; 3601 3602 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 3603 th = rtw89_chip_get_thermal(rtwdev, i); 3604 if (th) 3605 ewma_thermal_add(&phystat->avg_thermal[i], th); 3606 3607 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 3608 "path(%d) thermal cur=%u avg=%ld", i, th, 3609 ewma_thermal_read(&phystat->avg_thermal[i])); 3610 } 3611 } 3612 3613 struct rtw89_phy_iter_rssi_data { 3614 struct rtw89_dev *rtwdev; 3615 struct rtw89_phy_ch_info *ch_info; 3616 bool rssi_changed; 3617 }; 3618 3619 static void rtw89_phy_stat_rssi_update_iter(void *data, 3620 struct ieee80211_sta *sta) 3621 { 3622 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3623 struct rtw89_phy_iter_rssi_data *rssi_data = 3624 (struct rtw89_phy_iter_rssi_data *)data; 3625 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 3626 unsigned long rssi_curr; 3627 3628 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 3629 3630 if (rssi_curr < ch_info->rssi_min) { 3631 ch_info->rssi_min = rssi_curr; 3632 ch_info->rssi_min_macid = rtwsta->mac_id; 3633 } 3634 3635 if (rtwsta->prev_rssi == 0) { 3636 rtwsta->prev_rssi = rssi_curr; 3637 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 3638 rtwsta->prev_rssi = rssi_curr; 3639 rssi_data->rssi_changed = true; 3640 } 3641 } 3642 3643 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 3644 { 3645 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 3646 3647 rssi_data.rtwdev = rtwdev; 3648 rssi_data.ch_info = &rtwdev->ch_info; 3649 rssi_data.ch_info->rssi_min = U8_MAX; 3650 ieee80211_iterate_stations_atomic(rtwdev->hw, 3651 rtw89_phy_stat_rssi_update_iter, 3652 &rssi_data); 3653 if (rssi_data.rssi_changed) 3654 rtw89_btc_ntfy_wl_sta(rtwdev); 3655 } 3656 3657 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 3658 { 3659 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3660 int i; 3661 3662 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 3663 ewma_thermal_init(&phystat->avg_thermal[i]); 3664 3665 rtw89_phy_stat_thermal_update(rtwdev); 3666 3667 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 3668 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 3669 } 3670 3671 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 3672 { 3673 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3674 3675 rtw89_phy_stat_thermal_update(rtwdev); 3676 rtw89_phy_stat_rssi_update(rtwdev); 3677 3678 phystat->last_pkt_stat = phystat->cur_pkt_stat; 3679 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 3680 } 3681 3682 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 3683 { 3684 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3685 3686 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3687 } 3688 3689 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 3690 { 3691 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3692 3693 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3694 } 3695 3696 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 3697 { 3698 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3699 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3700 const struct rtw89_ccx_regs *ccx = phy->ccx; 3701 3702 env->ccx_manual_ctrl = false; 3703 env->ccx_ongoing = false; 3704 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3705 env->ccx_period = 0; 3706 env->ccx_unit_idx = RTW89_CCX_32_US; 3707 3708 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->en_mask, 1); 3709 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1); 3710 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1); 3711 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask, 3712 RTW89_CCX_EDCCA_BW20_0); 3713 } 3714 3715 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 3716 u16 score) 3717 { 3718 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3719 u32 numer = 0; 3720 u16 ret = 0; 3721 3722 numer = report * score + (env->ccx_period >> 1); 3723 if (env->ccx_period) 3724 ret = numer / env->ccx_period; 3725 3726 return ret >= score ? score - 1 : ret; 3727 } 3728 3729 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 3730 u16 time_ms, u32 *period, 3731 u32 *unit_idx) 3732 { 3733 u32 idx; 3734 u8 quotient; 3735 3736 if (time_ms >= CCX_MAX_PERIOD) 3737 time_ms = CCX_MAX_PERIOD; 3738 3739 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 3740 3741 if (quotient < 4) 3742 idx = RTW89_CCX_4_US; 3743 else if (quotient < 8) 3744 idx = RTW89_CCX_8_US; 3745 else if (quotient < 16) 3746 idx = RTW89_CCX_16_US; 3747 else 3748 idx = RTW89_CCX_32_US; 3749 3750 *unit_idx = idx; 3751 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 3752 3753 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3754 "[Trigger Time] period:%d, unit_idx:%d\n", 3755 *period, *unit_idx); 3756 } 3757 3758 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 3759 { 3760 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3761 3762 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3763 "lv:(%d)->(0)\n", env->ccx_rac_lv); 3764 3765 env->ccx_ongoing = false; 3766 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3767 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3768 } 3769 3770 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 3771 struct rtw89_ccx_para_info *para) 3772 { 3773 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3774 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 3775 u8 i = 0; 3776 u16 *ifs_th_l = env->ifs_clm_th_l; 3777 u16 *ifs_th_h = env->ifs_clm_th_h; 3778 u32 ifs_th0_us = 0, ifs_th_times = 0; 3779 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 3780 3781 if (!is_update) 3782 goto ifs_update_finished; 3783 3784 switch (para->ifs_clm_app) { 3785 case RTW89_IFS_CLM_INIT: 3786 case RTW89_IFS_CLM_BACKGROUND: 3787 case RTW89_IFS_CLM_ACS: 3788 case RTW89_IFS_CLM_DBG: 3789 case RTW89_IFS_CLM_DIG: 3790 case RTW89_IFS_CLM_TDMA_DIG: 3791 ifs_th0_us = IFS_CLM_TH0_UPPER; 3792 ifs_th_times = IFS_CLM_TH_MUL; 3793 break; 3794 case RTW89_IFS_CLM_DBG_MANUAL: 3795 ifs_th0_us = para->ifs_clm_manual_th0; 3796 ifs_th_times = para->ifs_clm_manual_th_times; 3797 break; 3798 default: 3799 break; 3800 } 3801 3802 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 3803 * low[i] = high[i-1] + 1 3804 * high[i] = high[i-1] * ifs_th_times 3805 */ 3806 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 3807 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 3808 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 3809 ifs_th0_us); 3810 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 3811 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 3812 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 3813 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 3814 } 3815 3816 ifs_update_finished: 3817 if (!is_update) 3818 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3819 "No need to update IFS_TH\n"); 3820 3821 return is_update; 3822 } 3823 3824 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 3825 { 3826 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3827 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3828 const struct rtw89_ccx_regs *ccx = phy->ccx; 3829 u8 i = 0; 3830 3831 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask, 3832 env->ifs_clm_th_l[0]); 3833 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask, 3834 env->ifs_clm_th_l[1]); 3835 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask, 3836 env->ifs_clm_th_l[2]); 3837 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask, 3838 env->ifs_clm_th_l[3]); 3839 3840 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask, 3841 env->ifs_clm_th_h[0]); 3842 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask, 3843 env->ifs_clm_th_h[1]); 3844 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask, 3845 env->ifs_clm_th_h[2]); 3846 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask, 3847 env->ifs_clm_th_h[3]); 3848 3849 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3850 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3851 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 3852 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 3853 } 3854 3855 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 3856 { 3857 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3858 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3859 const struct rtw89_ccx_regs *ccx = phy->ccx; 3860 struct rtw89_ccx_para_info para = {0}; 3861 3862 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3863 env->ifs_clm_mntr_time = 0; 3864 3865 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 3866 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 3867 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3868 3869 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true); 3870 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true); 3871 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true); 3872 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true); 3873 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true); 3874 } 3875 3876 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 3877 enum rtw89_env_racing_lv level) 3878 { 3879 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3880 int ret = 0; 3881 3882 if (level >= RTW89_RAC_MAX_NUM) { 3883 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3884 "[WARNING] Wrong LV=%d\n", level); 3885 return -EINVAL; 3886 } 3887 3888 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3889 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 3890 env->ccx_rac_lv, level); 3891 3892 if (env->ccx_ongoing) { 3893 if (level <= env->ccx_rac_lv) 3894 ret = -EINVAL; 3895 else 3896 env->ccx_ongoing = false; 3897 } 3898 3899 if (ret == 0) 3900 env->ccx_rac_lv = level; 3901 3902 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 3903 !ret); 3904 3905 return ret; 3906 } 3907 3908 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 3909 { 3910 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3911 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3912 const struct rtw89_ccx_regs *ccx = phy->ccx; 3913 3914 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0); 3915 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0); 3916 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1); 3917 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1); 3918 3919 env->ccx_ongoing = true; 3920 } 3921 3922 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 3923 { 3924 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3925 u8 i = 0; 3926 u32 res = 0; 3927 3928 env->ifs_clm_tx_ratio = 3929 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 3930 env->ifs_clm_edcca_excl_cca_ratio = 3931 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 3932 PERCENT); 3933 env->ifs_clm_cck_fa_ratio = 3934 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 3935 env->ifs_clm_ofdm_fa_ratio = 3936 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 3937 env->ifs_clm_cck_cca_excl_fa_ratio = 3938 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 3939 PERCENT); 3940 env->ifs_clm_ofdm_cca_excl_fa_ratio = 3941 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 3942 PERCENT); 3943 env->ifs_clm_cck_fa_permil = 3944 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 3945 env->ifs_clm_ofdm_fa_permil = 3946 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 3947 3948 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 3949 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 3950 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 3951 } else { 3952 env->ifs_clm_ifs_avg[i] = 3953 rtw89_phy_ccx_idx_to_us(rtwdev, 3954 env->ifs_clm_avg[i]); 3955 } 3956 3957 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 3958 res += env->ifs_clm_his[i] >> 1; 3959 if (env->ifs_clm_his[i]) 3960 res /= env->ifs_clm_his[i]; 3961 else 3962 res = 0; 3963 env->ifs_clm_cca_avg[i] = res; 3964 } 3965 3966 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3967 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3968 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 3969 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3970 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 3971 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 3972 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3973 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 3974 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 3975 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3976 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 3977 env->ifs_clm_cck_cca_excl_fa_ratio, 3978 env->ifs_clm_ofdm_cca_excl_fa_ratio); 3979 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3980 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 3981 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3982 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 3983 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 3984 env->ifs_clm_cca_avg[i]); 3985 } 3986 3987 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 3988 { 3989 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3990 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3991 const struct rtw89_ccx_regs *ccx = phy->ccx; 3992 u8 i = 0; 3993 3994 if (rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr, 3995 ccx->ifs_cnt_done_mask) == 0) { 3996 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3997 "Get IFS_CLM report Fail\n"); 3998 return false; 3999 } 4000 4001 env->ifs_clm_tx = 4002 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr, 4003 ccx->ifs_clm_tx_cnt_msk); 4004 env->ifs_clm_edcca_excl_cca = 4005 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr, 4006 ccx->ifs_clm_edcca_excl_cca_fa_mask); 4007 env->ifs_clm_cckcca_excl_fa = 4008 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr, 4009 ccx->ifs_clm_cckcca_excl_fa_mask); 4010 env->ifs_clm_ofdmcca_excl_fa = 4011 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr, 4012 ccx->ifs_clm_ofdmcca_excl_fa_mask); 4013 env->ifs_clm_cckfa = 4014 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr, 4015 ccx->ifs_clm_cck_fa_mask); 4016 env->ifs_clm_ofdmfa = 4017 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr, 4018 ccx->ifs_clm_ofdm_fa_mask); 4019 4020 env->ifs_clm_his[0] = 4021 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 4022 ccx->ifs_t1_his_mask); 4023 env->ifs_clm_his[1] = 4024 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 4025 ccx->ifs_t2_his_mask); 4026 env->ifs_clm_his[2] = 4027 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 4028 ccx->ifs_t3_his_mask); 4029 env->ifs_clm_his[3] = 4030 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 4031 ccx->ifs_t4_his_mask); 4032 4033 env->ifs_clm_avg[0] = 4034 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr, 4035 ccx->ifs_t1_avg_mask); 4036 env->ifs_clm_avg[1] = 4037 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr, 4038 ccx->ifs_t2_avg_mask); 4039 env->ifs_clm_avg[2] = 4040 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr, 4041 ccx->ifs_t3_avg_mask); 4042 env->ifs_clm_avg[3] = 4043 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr, 4044 ccx->ifs_t4_avg_mask); 4045 4046 env->ifs_clm_cca[0] = 4047 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr, 4048 ccx->ifs_t1_cca_mask); 4049 env->ifs_clm_cca[1] = 4050 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr, 4051 ccx->ifs_t2_cca_mask); 4052 env->ifs_clm_cca[2] = 4053 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr, 4054 ccx->ifs_t3_cca_mask); 4055 env->ifs_clm_cca[3] = 4056 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr, 4057 ccx->ifs_t4_cca_mask); 4058 4059 env->ifs_clm_total_ifs = 4060 rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr, 4061 ccx->ifs_total_mask); 4062 4063 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 4064 env->ifs_clm_total_ifs); 4065 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4066 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 4067 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 4068 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4069 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 4070 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 4071 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4072 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 4073 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 4074 4075 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 4076 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 4077 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4078 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 4079 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 4080 4081 rtw89_phy_ifs_clm_get_utility(rtwdev); 4082 4083 return true; 4084 } 4085 4086 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 4087 struct rtw89_ccx_para_info *para) 4088 { 4089 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4090 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4091 const struct rtw89_ccx_regs *ccx = phy->ccx; 4092 u32 period = 0; 4093 u32 unit_idx = 0; 4094 4095 if (para->mntr_time == 0) { 4096 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4097 "[WARN] MNTR_TIME is 0\n"); 4098 return -EINVAL; 4099 } 4100 4101 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 4102 return -EINVAL; 4103 4104 if (para->mntr_time != env->ifs_clm_mntr_time) { 4105 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 4106 &period, &unit_idx); 4107 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, 4108 ccx->ifs_clm_period_mask, period); 4109 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, 4110 ccx->ifs_clm_cnt_unit_mask, 4111 unit_idx); 4112 4113 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4114 "Update IFS-CLM time ((%d)) -> ((%d))\n", 4115 env->ifs_clm_mntr_time, para->mntr_time); 4116 4117 env->ifs_clm_mntr_time = para->mntr_time; 4118 env->ccx_period = (u16)period; 4119 env->ccx_unit_idx = (u8)unit_idx; 4120 } 4121 4122 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 4123 env->ifs_clm_app = para->ifs_clm_app; 4124 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 4125 } 4126 4127 return 0; 4128 } 4129 4130 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 4131 { 4132 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4133 struct rtw89_ccx_para_info para = {0}; 4134 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 4135 4136 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 4137 if (env->ccx_manual_ctrl) { 4138 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4139 "CCX in manual ctrl\n"); 4140 return; 4141 } 4142 4143 /* only ifs_clm for now */ 4144 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 4145 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 4146 4147 rtw89_phy_ccx_racing_release(rtwdev); 4148 para.mntr_time = 1900; 4149 para.rac_lv = RTW89_RAC_LV_1; 4150 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 4151 4152 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 4153 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 4154 if (chk_result) 4155 rtw89_phy_ccx_trigger(rtwdev); 4156 4157 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4158 "get_result=0x%x, chk_result:0x%x\n", 4159 env->ccx_watchdog_result, chk_result); 4160 } 4161 4162 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 4163 { 4164 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM || 4165 *ie_page == RTW89_RSVD_9) 4166 return false; 4167 else if (*ie_page > RTW89_RSVD_9) 4168 *ie_page -= 1; 4169 4170 return true; 4171 } 4172 4173 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 4174 { 4175 static const u8 ie_page_shift = 2; 4176 4177 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 4178 } 4179 4180 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 4181 enum rtw89_phy_status_bitmap ie_page) 4182 { 4183 u32 addr; 4184 4185 if (!rtw89_physts_ie_page_valid(&ie_page)) 4186 return 0; 4187 4188 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 4189 4190 return rtw89_phy_read32(rtwdev, addr); 4191 } 4192 4193 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 4194 enum rtw89_phy_status_bitmap ie_page, 4195 u32 val) 4196 { 4197 const struct rtw89_chip_info *chip = rtwdev->chip; 4198 u32 addr; 4199 4200 if (!rtw89_physts_ie_page_valid(&ie_page)) 4201 return; 4202 4203 if (chip->chip_id == RTL8852A) 4204 val &= B_PHY_STS_BITMAP_MSK_52A; 4205 4206 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 4207 rtw89_phy_write32(rtwdev, addr, val); 4208 } 4209 4210 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 4211 enum rtw89_phy_status_bitmap bitmap, 4212 enum rtw89_phy_status_ie_type ie, 4213 bool enable) 4214 { 4215 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 4216 4217 if (enable) 4218 val |= BIT(ie); 4219 else 4220 val &= ~BIT(ie); 4221 4222 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 4223 } 4224 4225 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 4226 bool enable, 4227 enum rtw89_phy_idx phy_idx) 4228 { 4229 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4230 const struct rtw89_physts_regs *physts = phy->physts; 4231 4232 if (enable) { 4233 rtw89_phy_write32_clr(rtwdev, physts->setting_addr, 4234 physts->dis_trigger_fail_mask); 4235 rtw89_phy_write32_clr(rtwdev, physts->setting_addr, 4236 physts->dis_trigger_brk_mask); 4237 } else { 4238 rtw89_phy_write32_set(rtwdev, physts->setting_addr, 4239 physts->dis_trigger_fail_mask); 4240 rtw89_phy_write32_set(rtwdev, physts->setting_addr, 4241 physts->dis_trigger_brk_mask); 4242 } 4243 } 4244 4245 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 4246 { 4247 u8 i; 4248 4249 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 4250 4251 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 4252 if (i >= RTW89_CCK_PKT) 4253 rtw89_physts_enable_ie_bitmap(rtwdev, i, 4254 RTW89_PHYSTS_IE09_FTR_0, 4255 true); 4256 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 4257 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 4258 continue; 4259 rtw89_physts_enable_ie_bitmap(rtwdev, i, 4260 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 4261 true); 4262 } 4263 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 4264 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 4265 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 4266 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 4267 4268 /* force IE01 for channel index, only channel field is valid */ 4269 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 4270 RTW89_PHYSTS_IE01_CMN_OFDM, true); 4271 } 4272 4273 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 4274 { 4275 const struct rtw89_chip_info *chip = rtwdev->chip; 4276 struct rtw89_dig_info *dig = &rtwdev->dig; 4277 const struct rtw89_phy_dig_gain_cfg *cfg; 4278 const char *msg; 4279 u8 i; 4280 s8 gain_base; 4281 s8 *gain_arr; 4282 u32 tmp; 4283 4284 switch (type) { 4285 case RTW89_DIG_GAIN_LNA_G: 4286 gain_arr = dig->lna_gain_g; 4287 gain_base = LNA0_GAIN; 4288 cfg = chip->dig_table->cfg_lna_g; 4289 msg = "lna_gain_g"; 4290 break; 4291 case RTW89_DIG_GAIN_TIA_G: 4292 gain_arr = dig->tia_gain_g; 4293 gain_base = TIA0_GAIN_G; 4294 cfg = chip->dig_table->cfg_tia_g; 4295 msg = "tia_gain_g"; 4296 break; 4297 case RTW89_DIG_GAIN_LNA_A: 4298 gain_arr = dig->lna_gain_a; 4299 gain_base = LNA0_GAIN; 4300 cfg = chip->dig_table->cfg_lna_a; 4301 msg = "lna_gain_a"; 4302 break; 4303 case RTW89_DIG_GAIN_TIA_A: 4304 gain_arr = dig->tia_gain_a; 4305 gain_base = TIA0_GAIN_A; 4306 cfg = chip->dig_table->cfg_tia_a; 4307 msg = "tia_gain_a"; 4308 break; 4309 default: 4310 return; 4311 } 4312 4313 for (i = 0; i < cfg->size; i++) { 4314 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 4315 cfg->table[i].mask); 4316 tmp >>= DIG_GAIN_SHIFT; 4317 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 4318 gain_base += DIG_GAIN; 4319 4320 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 4321 msg, i, gain_arr[i]); 4322 } 4323 } 4324 4325 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 4326 { 4327 struct rtw89_dig_info *dig = &rtwdev->dig; 4328 u32 tmp; 4329 u8 i; 4330 4331 if (!rtwdev->hal.support_igi) 4332 return; 4333 4334 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 4335 B_PATH0_IB_PKPW_MSK); 4336 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 4337 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 4338 B_PATH0_IB_PBK_MSK); 4339 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 4340 dig->ib_pkpwr, dig->ib_pbk); 4341 4342 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 4343 rtw89_phy_dig_read_gain_table(rtwdev, i); 4344 } 4345 4346 static const u8 rssi_nolink = 22; 4347 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 4348 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 4349 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 4350 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 4351 4352 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 4353 { 4354 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 4355 struct rtw89_dig_info *dig = &rtwdev->dig; 4356 bool is_linked = rtwdev->total_sta_assoc > 0; 4357 4358 if (is_linked) { 4359 dig->igi_rssi = ch_info->rssi_min >> 1; 4360 } else { 4361 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 4362 dig->igi_rssi = rssi_nolink; 4363 } 4364 } 4365 4366 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 4367 { 4368 struct rtw89_dig_info *dig = &rtwdev->dig; 4369 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 4370 bool is_linked = rtwdev->total_sta_assoc > 0; 4371 const u16 *fa_th_src = NULL; 4372 4373 switch (chan->band_type) { 4374 case RTW89_BAND_2G: 4375 dig->lna_gain = dig->lna_gain_g; 4376 dig->tia_gain = dig->tia_gain_g; 4377 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 4378 dig->force_gaincode_idx_en = false; 4379 dig->dyn_pd_th_en = true; 4380 break; 4381 case RTW89_BAND_5G: 4382 default: 4383 dig->lna_gain = dig->lna_gain_a; 4384 dig->tia_gain = dig->tia_gain_a; 4385 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 4386 dig->force_gaincode_idx_en = true; 4387 dig->dyn_pd_th_en = true; 4388 break; 4389 } 4390 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 4391 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 4392 } 4393 4394 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 4395 static const u8 igi_max_performance_mode = 0x5a; 4396 static const u8 dynamic_pd_threshold_max; 4397 4398 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 4399 { 4400 struct rtw89_dig_info *dig = &rtwdev->dig; 4401 4402 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 4403 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 4404 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 4405 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 4406 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 4407 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 4408 4409 dig->dyn_igi_max = igi_max_performance_mode; 4410 dig->dyn_igi_min = dynamic_igi_min; 4411 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 4412 dig->pd_low_th_ofst = pd_low_th_offset; 4413 dig->is_linked_pre = false; 4414 } 4415 4416 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 4417 { 4418 rtw89_phy_dig_update_gain_para(rtwdev); 4419 rtw89_phy_dig_reset(rtwdev); 4420 } 4421 4422 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 4423 { 4424 struct rtw89_dig_info *dig = &rtwdev->dig; 4425 u8 lna_idx; 4426 4427 if (rssi < dig->igi_rssi_th[0]) 4428 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 4429 else if (rssi < dig->igi_rssi_th[1]) 4430 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 4431 else if (rssi < dig->igi_rssi_th[2]) 4432 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 4433 else if (rssi < dig->igi_rssi_th[3]) 4434 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 4435 else if (rssi < dig->igi_rssi_th[4]) 4436 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 4437 else 4438 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 4439 4440 return lna_idx; 4441 } 4442 4443 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 4444 { 4445 struct rtw89_dig_info *dig = &rtwdev->dig; 4446 u8 tia_idx; 4447 4448 if (rssi < dig->igi_rssi_th[0]) 4449 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 4450 else 4451 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 4452 4453 return tia_idx; 4454 } 4455 4456 #define IB_PBK_BASE 110 4457 #define WB_RSSI_BASE 10 4458 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 4459 struct rtw89_agc_gaincode_set *set) 4460 { 4461 struct rtw89_dig_info *dig = &rtwdev->dig; 4462 s8 lna_gain = dig->lna_gain[set->lna_idx]; 4463 s8 tia_gain = dig->tia_gain[set->tia_idx]; 4464 s32 wb_rssi = rssi + lna_gain + tia_gain; 4465 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 4466 u8 rxb_idx; 4467 4468 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 4469 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 4470 4471 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 4472 wb_rssi, rxb_idx_tmp); 4473 4474 return rxb_idx; 4475 } 4476 4477 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 4478 struct rtw89_agc_gaincode_set *set) 4479 { 4480 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 4481 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 4482 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 4483 4484 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4485 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 4486 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 4487 } 4488 4489 #define IGI_OFFSET_MAX 25 4490 #define IGI_OFFSET_MUL 2 4491 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 4492 { 4493 struct rtw89_dig_info *dig = &rtwdev->dig; 4494 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4495 enum rtw89_dig_noisy_level noisy_lv; 4496 u8 igi_offset = dig->fa_rssi_ofst; 4497 u16 fa_ratio = 0; 4498 4499 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 4500 4501 if (fa_ratio < dig->fa_th[0]) 4502 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 4503 else if (fa_ratio < dig->fa_th[1]) 4504 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 4505 else if (fa_ratio < dig->fa_th[2]) 4506 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 4507 else if (fa_ratio < dig->fa_th[3]) 4508 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 4509 else 4510 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 4511 4512 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 4513 igi_offset = 0; 4514 else 4515 igi_offset += noisy_lv * IGI_OFFSET_MUL; 4516 4517 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 4518 dig->fa_rssi_ofst = igi_offset; 4519 4520 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4521 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 4522 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 4523 4524 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4525 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 4526 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 4527 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 4528 noisy_lv, igi_offset); 4529 } 4530 4531 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 4532 { 4533 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4534 4535 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr, 4536 dig_regs->p0_lna_init.mask, lna_idx); 4537 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr, 4538 dig_regs->p1_lna_init.mask, lna_idx); 4539 } 4540 4541 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 4542 { 4543 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4544 4545 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr, 4546 dig_regs->p0_tia_init.mask, tia_idx); 4547 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr, 4548 dig_regs->p1_tia_init.mask, tia_idx); 4549 } 4550 4551 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 4552 { 4553 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4554 4555 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr, 4556 dig_regs->p0_rxb_init.mask, rxb_idx); 4557 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr, 4558 dig_regs->p1_rxb_init.mask, rxb_idx); 4559 } 4560 4561 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 4562 const struct rtw89_agc_gaincode_set set) 4563 { 4564 if (!rtwdev->hal.support_igi) 4565 return; 4566 4567 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 4568 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 4569 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 4570 4571 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 4572 set.lna_idx, set.tia_idx, set.rxb_idx); 4573 } 4574 4575 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 4576 bool enable) 4577 { 4578 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4579 4580 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 4581 dig_regs->p0_p20_pagcugc_en.mask, enable); 4582 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 4583 dig_regs->p0_s20_pagcugc_en.mask, enable); 4584 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 4585 dig_regs->p1_p20_pagcugc_en.mask, enable); 4586 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 4587 dig_regs->p1_s20_pagcugc_en.mask, enable); 4588 4589 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 4590 } 4591 4592 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 4593 { 4594 struct rtw89_dig_info *dig = &rtwdev->dig; 4595 4596 if (!rtwdev->hal.support_igi) 4597 return; 4598 4599 if (dig->force_gaincode_idx_en) { 4600 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 4601 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4602 "Force gaincode index enabled.\n"); 4603 } else { 4604 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 4605 &dig->cur_gaincode); 4606 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 4607 } 4608 } 4609 4610 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 4611 bool enable) 4612 { 4613 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 4614 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4615 enum rtw89_bandwidth cbw = chan->band_width; 4616 struct rtw89_dig_info *dig = &rtwdev->dig; 4617 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 4618 u8 ofdm_cca_th; 4619 s8 cck_cca_th; 4620 u32 pd_val = 0; 4621 4622 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX) 4623 under_region += PD_TH_SB_FLTR_CMP_VAL; 4624 4625 switch (cbw) { 4626 case RTW89_CHANNEL_WIDTH_40: 4627 under_region += PD_TH_BW40_CMP_VAL; 4628 break; 4629 case RTW89_CHANNEL_WIDTH_80: 4630 under_region += PD_TH_BW80_CMP_VAL; 4631 break; 4632 case RTW89_CHANNEL_WIDTH_160: 4633 under_region += PD_TH_BW160_CMP_VAL; 4634 break; 4635 case RTW89_CHANNEL_WIDTH_20: 4636 fallthrough; 4637 default: 4638 under_region += PD_TH_BW20_CMP_VAL; 4639 break; 4640 } 4641 4642 dig->dyn_pd_th_max = dig->igi_rssi; 4643 4644 final_rssi = min_t(u8, rssi, dig->igi_rssi); 4645 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 4646 PD_TH_MAX_RSSI + under_region); 4647 4648 if (enable) { 4649 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 4650 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4651 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 4652 final_rssi, ofdm_cca_th, under_region, pd_val); 4653 } else { 4654 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4655 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 4656 } 4657 4658 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 4659 dig_regs->pd_lower_bound_mask, pd_val); 4660 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 4661 dig_regs->pd_spatial_reuse_en, enable); 4662 4663 if (!rtwdev->hal.support_cckpd) 4664 return; 4665 4666 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 4667 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 4668 4669 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4670 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 4671 final_rssi, cck_cca_th, under_region, pd_val); 4672 4673 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_reg, 4674 dig_regs->bmode_cca_rssi_limit_en, enable); 4675 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_lower_bound_reg, 4676 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val); 4677 } 4678 4679 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 4680 { 4681 struct rtw89_dig_info *dig = &rtwdev->dig; 4682 4683 dig->bypass_dig = false; 4684 rtw89_phy_dig_para_reset(rtwdev); 4685 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 4686 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 4687 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 4688 rtw89_phy_dig_update_para(rtwdev); 4689 } 4690 4691 #define IGI_RSSI_MIN 10 4692 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 4693 { 4694 struct rtw89_dig_info *dig = &rtwdev->dig; 4695 bool is_linked = rtwdev->total_sta_assoc > 0; 4696 4697 if (unlikely(dig->bypass_dig)) { 4698 dig->bypass_dig = false; 4699 return; 4700 } 4701 4702 if (!dig->is_linked_pre && is_linked) { 4703 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 4704 rtw89_phy_dig_update_para(rtwdev); 4705 } else if (dig->is_linked_pre && !is_linked) { 4706 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 4707 rtw89_phy_dig_update_para(rtwdev); 4708 } 4709 dig->is_linked_pre = is_linked; 4710 4711 rtw89_phy_dig_igi_offset_by_env(rtwdev); 4712 rtw89_phy_dig_update_rssi_info(rtwdev); 4713 4714 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 4715 dig->igi_rssi - IGI_RSSI_MIN : 0; 4716 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 4717 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 4718 4719 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 4720 dig->dyn_igi_max); 4721 4722 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4723 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 4724 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 4725 dig->igi_fa_rssi); 4726 4727 rtw89_phy_dig_config_igi(rtwdev); 4728 4729 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 4730 4731 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 4732 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 4733 else 4734 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 4735 } 4736 4737 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 4738 { 4739 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 4740 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4741 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4742 struct rtw89_hal *hal = &rtwdev->hal; 4743 bool *done = data; 4744 u8 rssi_a, rssi_b; 4745 u32 candidate; 4746 4747 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || sta->tdls) 4748 return; 4749 4750 if (*done) 4751 return; 4752 4753 *done = true; 4754 4755 rssi_a = ewma_rssi_read(&rtwsta->rssi[RF_PATH_A]); 4756 rssi_b = ewma_rssi_read(&rtwsta->rssi[RF_PATH_B]); 4757 4758 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 4759 candidate = RF_A; 4760 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 4761 candidate = RF_B; 4762 else 4763 return; 4764 4765 if (hal->antenna_tx == candidate) 4766 return; 4767 4768 hal->antenna_tx = candidate; 4769 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta); 4770 4771 if (hal->antenna_tx == RF_A) { 4772 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 4773 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 4774 } else if (hal->antenna_tx == RF_B) { 4775 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 4776 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 4777 } 4778 } 4779 4780 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 4781 { 4782 struct rtw89_hal *hal = &rtwdev->hal; 4783 bool done = false; 4784 4785 if (!hal->tx_path_diversity) 4786 return; 4787 4788 ieee80211_iterate_stations_atomic(rtwdev->hw, 4789 rtw89_phy_tx_path_div_sta_iter, 4790 &done); 4791 } 4792 4793 #define ANTDIV_MAIN 0 4794 #define ANTDIV_AUX 1 4795 4796 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev) 4797 { 4798 struct rtw89_hal *hal = &rtwdev->hal; 4799 u8 default_ant, optional_ant; 4800 4801 if (!hal->ant_diversity || hal->antenna_tx == 0) 4802 return; 4803 4804 if (hal->antenna_tx == RF_B) { 4805 default_ant = ANTDIV_AUX; 4806 optional_ant = ANTDIV_MAIN; 4807 } else { 4808 default_ant = ANTDIV_MAIN; 4809 optional_ant = ANTDIV_AUX; 4810 } 4811 4812 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL, 4813 default_ant, RTW89_PHY_0); 4814 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI, 4815 default_ant, RTW89_PHY_0); 4816 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT, 4817 optional_ant, RTW89_PHY_0); 4818 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI, 4819 default_ant, RTW89_PHY_0); 4820 } 4821 4822 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev) 4823 { 4824 struct rtw89_hal *hal = &rtwdev->hal; 4825 4826 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A; 4827 hal->antenna_tx = hal->antenna_rx; 4828 } 4829 4830 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev) 4831 { 4832 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4833 struct rtw89_hal *hal = &rtwdev->hal; 4834 bool no_change = false; 4835 u8 main_rssi, aux_rssi; 4836 u8 main_evm, aux_evm; 4837 u32 candidate; 4838 4839 antdiv->get_stats = false; 4840 antdiv->training_count = 0; 4841 4842 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats); 4843 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats); 4844 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats); 4845 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats); 4846 4847 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH) 4848 candidate = RF_A; 4849 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH) 4850 candidate = RF_B; 4851 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 4852 candidate = RF_A; 4853 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 4854 candidate = RF_B; 4855 else 4856 no_change = true; 4857 4858 if (no_change) { 4859 /* swap back from training antenna to original */ 4860 rtw89_phy_swap_hal_antenna(rtwdev); 4861 return; 4862 } 4863 4864 hal->antenna_tx = candidate; 4865 hal->antenna_rx = candidate; 4866 } 4867 4868 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev) 4869 { 4870 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4871 u64 state_period; 4872 4873 if (antdiv->training_count % 2 == 0) { 4874 if (antdiv->training_count == 0) 4875 rtw89_phy_antdiv_sts_reset(rtwdev); 4876 4877 antdiv->get_stats = true; 4878 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL); 4879 } else { 4880 antdiv->get_stats = false; 4881 state_period = msecs_to_jiffies(ANTDIV_DELAY); 4882 4883 rtw89_phy_swap_hal_antenna(rtwdev); 4884 rtw89_phy_antdiv_set_ant(rtwdev); 4885 } 4886 4887 antdiv->training_count++; 4888 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 4889 state_period); 4890 } 4891 4892 void rtw89_phy_antdiv_work(struct work_struct *work) 4893 { 4894 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4895 antdiv_work.work); 4896 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4897 4898 mutex_lock(&rtwdev->mutex); 4899 4900 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) { 4901 rtw89_phy_antdiv_training_state(rtwdev); 4902 } else { 4903 rtw89_phy_antdiv_decision_state(rtwdev); 4904 rtw89_phy_antdiv_set_ant(rtwdev); 4905 } 4906 4907 mutex_unlock(&rtwdev->mutex); 4908 } 4909 4910 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev) 4911 { 4912 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4913 struct rtw89_hal *hal = &rtwdev->hal; 4914 u8 rssi, rssi_pre; 4915 4916 if (!hal->ant_diversity || hal->ant_diversity_fixed) 4917 return; 4918 4919 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats); 4920 rssi_pre = antdiv->rssi_pre; 4921 antdiv->rssi_pre = rssi; 4922 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 4923 4924 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH) 4925 return; 4926 4927 antdiv->training_count = 0; 4928 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 0); 4929 } 4930 4931 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 4932 { 4933 rtw89_phy_ccx_top_setting_init(rtwdev); 4934 rtw89_phy_ifs_clm_setting_init(rtwdev); 4935 } 4936 4937 static void rtw89_phy_edcca_init(struct rtw89_dev *rtwdev) 4938 { 4939 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 4940 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak; 4941 4942 memset(edcca_bak, 0, sizeof(*edcca_bak)); 4943 4944 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) { 4945 rtw89_phy_set_phy_regs(rtwdev, R_TXGATING, B_TXGATING_EN, 0); 4946 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_VAL, 2); 4947 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_ON, 1); 4948 rtw89_phy_set_phy_regs(rtwdev, R_SPOOF_CG, B_SPOOF_CG_EN, 0); 4949 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_CG_EN, 0); 4950 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 0); 4951 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 0); 4952 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 1); 4953 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 1); 4954 } 4955 4956 rtw89_phy_write32_mask(rtwdev, edcca_regs->tx_collision_t2r_st, 4957 edcca_regs->tx_collision_t2r_st_mask, 0x29); 4958 } 4959 4960 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 4961 { 4962 rtw89_phy_stat_init(rtwdev); 4963 4964 rtw89_chip_bb_sethw(rtwdev); 4965 4966 rtw89_phy_env_monitor_init(rtwdev); 4967 rtw89_physts_parsing_init(rtwdev); 4968 rtw89_phy_dig_init(rtwdev); 4969 rtw89_phy_cfo_init(rtwdev); 4970 rtw89_phy_bb_wrap_init(rtwdev); 4971 rtw89_phy_edcca_init(rtwdev); 4972 rtw89_phy_ch_info_init(rtwdev); 4973 rtw89_phy_ul_tb_info_init(rtwdev); 4974 rtw89_phy_antdiv_init(rtwdev); 4975 rtw89_chip_rfe_gpio(rtwdev); 4976 rtw89_phy_antdiv_set_ant(rtwdev); 4977 4978 rtw89_phy_init_rf_nctl(rtwdev); 4979 rtw89_chip_rfk_init(rtwdev); 4980 rtw89_chip_set_txpwr_ctrl(rtwdev); 4981 rtw89_chip_power_trim(rtwdev); 4982 rtw89_chip_cfg_txrx_path(rtwdev); 4983 } 4984 4985 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 4986 { 4987 const struct rtw89_chip_info *chip = rtwdev->chip; 4988 const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld; 4989 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 4990 u8 bss_color; 4991 4992 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4993 return; 4994 4995 bss_color = vif->bss_conf.he_bss_color.color; 4996 4997 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1, 4998 phy_idx); 4999 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT, 5000 bss_color, phy_idx); 5001 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID, 5002 vif->cfg.aid, phy_idx); 5003 } 5004 5005 static void 5006 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 5007 { 5008 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 5009 } 5010 5011 static void 5012 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 5013 { 5014 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 5015 } 5016 5017 static void 5018 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 5019 { 5020 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 5021 } 5022 5023 static void 5024 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 5025 { 5026 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 5027 } 5028 5029 static void 5030 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 5031 { 5032 udelay(def->data); 5033 } 5034 5035 static void 5036 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 5037 [RTW89_RFK_F_WRF] = _rfk_write_rf, 5038 [RTW89_RFK_F_WM] = _rfk_write32_mask, 5039 [RTW89_RFK_F_WS] = _rfk_write32_set, 5040 [RTW89_RFK_F_WC] = _rfk_write32_clr, 5041 [RTW89_RFK_F_DELAY] = _rfk_delay, 5042 }; 5043 5044 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 5045 5046 void 5047 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 5048 { 5049 const struct rtw89_reg5_def *p = tbl->defs; 5050 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 5051 5052 for (; p < end; p++) 5053 _rfk_handler[p->flag](rtwdev, p); 5054 } 5055 EXPORT_SYMBOL(rtw89_rfk_parser); 5056 5057 #define RTW89_TSSI_FAST_MODE_NUM 4 5058 5059 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 5060 {0xD934, 0xff0000}, 5061 {0xD934, 0xff000000}, 5062 {0xD938, 0xff}, 5063 {0xD934, 0xff00}, 5064 }; 5065 5066 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 5067 {0xD930, 0xff0000}, 5068 {0xD930, 0xff000000}, 5069 {0xD934, 0xff}, 5070 {0xD930, 0xff00}, 5071 }; 5072 5073 static 5074 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 5075 enum rtw89_mac_idx mac_idx, 5076 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 5077 u32 val) 5078 { 5079 const struct rtw89_reg_def *regs; 5080 u32 reg; 5081 int i; 5082 5083 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 5084 regs = rtw89_tssi_fastmode_regs_flat; 5085 else 5086 regs = rtw89_tssi_fastmode_regs_level; 5087 5088 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 5089 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 5090 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 5091 } 5092 } 5093 5094 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 5095 {0xD91C, 0xff000000}, 5096 {0xD920, 0xff}, 5097 {0xD920, 0xff00}, 5098 {0xD920, 0xff0000}, 5099 {0xD920, 0xff000000}, 5100 {0xD924, 0xff}, 5101 {0xD924, 0xff00}, 5102 {0xD914, 0xff000000}, 5103 {0xD918, 0xff}, 5104 {0xD918, 0xff00}, 5105 {0xD918, 0xff0000}, 5106 {0xD918, 0xff000000}, 5107 {0xD91C, 0xff}, 5108 {0xD91C, 0xff00}, 5109 {0xD91C, 0xff0000}, 5110 }; 5111 5112 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 5113 {0xD910, 0xff}, 5114 {0xD910, 0xff00}, 5115 {0xD910, 0xff0000}, 5116 {0xD910, 0xff000000}, 5117 {0xD914, 0xff}, 5118 {0xD914, 0xff00}, 5119 {0xD914, 0xff0000}, 5120 {0xD908, 0xff}, 5121 {0xD908, 0xff00}, 5122 {0xD908, 0xff0000}, 5123 {0xD908, 0xff000000}, 5124 {0xD90C, 0xff}, 5125 {0xD90C, 0xff00}, 5126 {0xD90C, 0xff0000}, 5127 {0xD90C, 0xff000000}, 5128 }; 5129 5130 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 5131 enum rtw89_mac_idx mac_idx, 5132 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 5133 { 5134 const struct rtw89_chip_info *chip = rtwdev->chip; 5135 const struct rtw89_reg_def *regs; 5136 const u32 *data; 5137 u32 reg; 5138 int i; 5139 5140 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 5141 return; 5142 5143 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 5144 regs = rtw89_tssi_bandedge_regs_flat; 5145 else 5146 regs = rtw89_tssi_bandedge_regs_level; 5147 5148 data = chip->tssi_dbw_table->data[bandedge_cfg]; 5149 5150 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 5151 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 5152 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 5153 } 5154 5155 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx); 5156 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 5157 5158 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 5159 data[RTW89_TSSI_SBW20]); 5160 } 5161 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 5162 5163 static 5164 const u8 rtw89_ch_base_table[16] = {1, 0xff, 5165 36, 100, 132, 149, 0xff, 5166 1, 33, 65, 97, 129, 161, 193, 225, 0xff}; 5167 #define RTW89_CH_BASE_IDX_2G 0 5168 #define RTW89_CH_BASE_IDX_5G_FIRST 2 5169 #define RTW89_CH_BASE_IDX_5G_LAST 5 5170 #define RTW89_CH_BASE_IDX_6G_FIRST 7 5171 #define RTW89_CH_BASE_IDX_6G_LAST 14 5172 5173 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4) 5174 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0) 5175 5176 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band) 5177 { 5178 u8 chan_idx; 5179 u8 last, first; 5180 u8 idx; 5181 5182 switch (band) { 5183 case RTW89_BAND_2G: 5184 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) | 5185 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch); 5186 return chan_idx; 5187 case RTW89_BAND_5G: 5188 first = RTW89_CH_BASE_IDX_5G_FIRST; 5189 last = RTW89_CH_BASE_IDX_5G_LAST; 5190 break; 5191 case RTW89_BAND_6G: 5192 first = RTW89_CH_BASE_IDX_6G_FIRST; 5193 last = RTW89_CH_BASE_IDX_6G_LAST; 5194 break; 5195 default: 5196 rtw89_warn(rtwdev, "Unsupported band %d\n", band); 5197 return 0; 5198 } 5199 5200 for (idx = last; idx >= first; idx--) 5201 if (central_ch >= rtw89_ch_base_table[idx]) 5202 break; 5203 5204 if (idx < first) { 5205 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch); 5206 return 0; 5207 } 5208 5209 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) | 5210 FIELD_PREP(RTW89_CH_OFFSET_MASK, 5211 (central_ch - rtw89_ch_base_table[idx]) >> 1); 5212 return chan_idx; 5213 } 5214 EXPORT_SYMBOL(rtw89_encode_chan_idx); 5215 5216 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 5217 u8 *ch, enum nl80211_band *band) 5218 { 5219 u8 idx, offset; 5220 5221 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx); 5222 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx); 5223 5224 if (idx == RTW89_CH_BASE_IDX_2G) { 5225 *band = NL80211_BAND_2GHZ; 5226 *ch = offset; 5227 return; 5228 } 5229 5230 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ; 5231 *ch = rtw89_ch_base_table[idx] + (offset << 1); 5232 } 5233 EXPORT_SYMBOL(rtw89_decode_chan_idx); 5234 5235 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan) 5236 { 5237 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 5238 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak; 5239 5240 if (scan) { 5241 edcca_bak->a = 5242 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level, 5243 edcca_regs->edcca_mask); 5244 edcca_bak->p = 5245 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level, 5246 edcca_regs->edcca_p_mask); 5247 edcca_bak->ppdu = 5248 rtw89_phy_read32_mask(rtwdev, edcca_regs->ppdu_level, 5249 edcca_regs->ppdu_mask); 5250 5251 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 5252 edcca_regs->edcca_mask, EDCCA_MAX); 5253 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 5254 edcca_regs->edcca_p_mask, EDCCA_MAX); 5255 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level, 5256 edcca_regs->ppdu_mask, EDCCA_MAX); 5257 } else { 5258 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 5259 edcca_regs->edcca_mask, 5260 edcca_bak->a); 5261 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 5262 edcca_regs->edcca_p_mask, 5263 edcca_bak->p); 5264 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level, 5265 edcca_regs->ppdu_mask, 5266 edcca_bak->ppdu); 5267 } 5268 } 5269 5270 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev) 5271 { 5272 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 5273 bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80; 5274 s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80; 5275 u8 path, per20_bitmap; 5276 u8 pwdb[8]; 5277 u32 tmp; 5278 5279 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA)) 5280 return; 5281 5282 if (rtwdev->chip->chip_id == RTL8922A) 5283 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 5284 edcca_regs->rpt_sel_be_mask, 0); 5285 5286 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 5287 edcca_regs->rpt_sel_mask, 0); 5288 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 5289 path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK); 5290 flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80); 5291 flag_s40 = u32_get_bits(tmp, B_EDCCA_RPT_B_S40); 5292 flag_s20 = u32_get_bits(tmp, B_EDCCA_RPT_B_S20); 5293 flag_p20 = u32_get_bits(tmp, B_EDCCA_RPT_B_P20); 5294 flag_fb = u32_get_bits(tmp, B_EDCCA_RPT_B_FB); 5295 pwdb_s20 = u32_get_bits(tmp, MASKBYTE1); 5296 pwdb_p20 = u32_get_bits(tmp, MASKBYTE2); 5297 pwdb_fb = u32_get_bits(tmp, MASKBYTE3); 5298 5299 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 5300 edcca_regs->rpt_sel_mask, 4); 5301 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 5302 pwdb_s80 = u32_get_bits(tmp, MASKBYTE1); 5303 pwdb_s40 = u32_get_bits(tmp, MASKBYTE2); 5304 5305 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_regs->rpt_a, 5306 MASKBYTE0); 5307 5308 if (rtwdev->chip->chip_id == RTL8922A) { 5309 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 5310 edcca_regs->rpt_sel_be_mask, 4); 5311 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 5312 pwdb[0] = u32_get_bits(tmp, MASKBYTE3); 5313 pwdb[1] = u32_get_bits(tmp, MASKBYTE2); 5314 pwdb[2] = u32_get_bits(tmp, MASKBYTE1); 5315 pwdb[3] = u32_get_bits(tmp, MASKBYTE0); 5316 5317 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 5318 edcca_regs->rpt_sel_be_mask, 5); 5319 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 5320 pwdb[4] = u32_get_bits(tmp, MASKBYTE3); 5321 pwdb[5] = u32_get_bits(tmp, MASKBYTE2); 5322 pwdb[6] = u32_get_bits(tmp, MASKBYTE1); 5323 pwdb[7] = u32_get_bits(tmp, MASKBYTE0); 5324 } else { 5325 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 5326 edcca_regs->rpt_sel_mask, 0); 5327 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 5328 pwdb[0] = u32_get_bits(tmp, MASKBYTE3); 5329 pwdb[1] = u32_get_bits(tmp, MASKBYTE2); 5330 5331 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 5332 edcca_regs->rpt_sel_mask, 1); 5333 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 5334 pwdb[2] = u32_get_bits(tmp, MASKBYTE3); 5335 pwdb[3] = u32_get_bits(tmp, MASKBYTE2); 5336 5337 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 5338 edcca_regs->rpt_sel_mask, 2); 5339 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 5340 pwdb[4] = u32_get_bits(tmp, MASKBYTE3); 5341 pwdb[5] = u32_get_bits(tmp, MASKBYTE2); 5342 5343 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 5344 edcca_regs->rpt_sel_mask, 3); 5345 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 5346 pwdb[6] = u32_get_bits(tmp, MASKBYTE3); 5347 pwdb[7] = u32_get_bits(tmp, MASKBYTE2); 5348 } 5349 5350 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 5351 "[EDCCA]: edcca_bitmap = %04x\n", per20_bitmap); 5352 5353 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 5354 "[EDCCA]: pwdb per20{0,1,2,3,4,5,6,7} = {%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n", 5355 pwdb[0], pwdb[1], pwdb[2], pwdb[3], pwdb[4], pwdb[5], 5356 pwdb[6], pwdb[7]); 5357 5358 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 5359 "[EDCCA]: path=%d, flag {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}\n", 5360 path, flag_fb, flag_p20, flag_s20, flag_s40, flag_s80); 5361 5362 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 5363 "[EDCCA]: pwdb {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}(dBm)\n", 5364 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80); 5365 } 5366 5367 static u8 rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev *rtwdev) 5368 { 5369 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 5370 bool is_linked = rtwdev->total_sta_assoc > 0; 5371 u8 rssi_min = ch_info->rssi_min >> 1; 5372 u8 edcca_thre; 5373 5374 if (!is_linked) { 5375 edcca_thre = EDCCA_MAX; 5376 } else { 5377 edcca_thre = rssi_min - RSSI_UNIT_CONVER + EDCCA_UNIT_CONVER - 5378 EDCCA_TH_REF; 5379 edcca_thre = max_t(u8, edcca_thre, EDCCA_TH_L2H_LB); 5380 } 5381 5382 return edcca_thre; 5383 } 5384 5385 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev) 5386 { 5387 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 5388 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak; 5389 u8 th; 5390 5391 th = rtw89_phy_edcca_get_thre_by_rssi(rtwdev); 5392 if (th == edcca_bak->th_old) 5393 return; 5394 5395 edcca_bak->th_old = th; 5396 5397 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 5398 "[EDCCA]: Normal Mode, EDCCA_th = %d\n", th); 5399 5400 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 5401 edcca_regs->edcca_mask, th); 5402 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 5403 edcca_regs->edcca_p_mask, th); 5404 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level, 5405 edcca_regs->ppdu_mask, th); 5406 } 5407 5408 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev) 5409 { 5410 struct rtw89_hal *hal = &rtwdev->hal; 5411 5412 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DYNAMIC_EDCCA)) 5413 return; 5414 5415 rtw89_phy_edcca_thre_calc(rtwdev); 5416 rtw89_phy_edcca_log(rtwdev); 5417 } 5418 5419 static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = { 5420 .setting_addr = R_CCX, 5421 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK, 5422 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, 5423 .trig_opt_mask = B_CCX_TRIG_OPT_MSK, 5424 .en_mask = B_CCX_EN_MSK, 5425 .ifs_cnt_addr = R_IFS_COUNTER, 5426 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, 5427 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, 5428 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, 5429 .ifs_collect_en_mask = B_IFS_COLLECT_EN, 5430 .ifs_t1_addr = R_IFS_T1, 5431 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, 5432 .ifs_t1_en_mask = B_IFS_T1_EN_MSK, 5433 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, 5434 .ifs_t2_addr = R_IFS_T2, 5435 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, 5436 .ifs_t2_en_mask = B_IFS_T2_EN_MSK, 5437 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, 5438 .ifs_t3_addr = R_IFS_T3, 5439 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, 5440 .ifs_t3_en_mask = B_IFS_T3_EN_MSK, 5441 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, 5442 .ifs_t4_addr = R_IFS_T4, 5443 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, 5444 .ifs_t4_en_mask = B_IFS_T4_EN_MSK, 5445 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, 5446 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT, 5447 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, 5448 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, 5449 .ifs_clm_cca_addr = R_IFS_CLM_CCA, 5450 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, 5451 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, 5452 .ifs_clm_fa_addr = R_IFS_CLM_FA, 5453 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, 5454 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, 5455 .ifs_his_addr = R_IFS_HIS, 5456 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, 5457 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, 5458 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, 5459 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK, 5460 .ifs_avg_l_addr = R_IFS_AVG_L, 5461 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK, 5462 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK, 5463 .ifs_avg_h_addr = R_IFS_AVG_H, 5464 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK, 5465 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK, 5466 .ifs_cca_l_addr = R_IFS_CCA_L, 5467 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK, 5468 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK, 5469 .ifs_cca_h_addr = R_IFS_CCA_H, 5470 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK, 5471 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK, 5472 .ifs_total_addr = R_IFSCNT, 5473 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK, 5474 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK, 5475 }; 5476 5477 static const struct rtw89_physts_regs rtw89_physts_regs_ax = { 5478 .setting_addr = R_PLCP_HISTOGRAM, 5479 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, 5480 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, 5481 }; 5482 5483 static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = { 5484 .comp = R_DCFO_WEIGHT, 5485 .weighting_mask = B_DCFO_WEIGHT_MSK, 5486 .comp_seg0 = R_DCFO_OPT, 5487 .valid_0_mask = B_DCFO_OPT_EN, 5488 }; 5489 5490 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = { 5491 .cr_base = 0x10000, 5492 .ccx = &rtw89_ccx_regs_ax, 5493 .physts = &rtw89_physts_regs_ax, 5494 .cfo = &rtw89_cfo_regs_ax, 5495 .config_bb_gain = rtw89_phy_config_bb_gain_ax, 5496 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax, 5497 .bb_wrap_init = NULL, 5498 .ch_info_init = NULL, 5499 5500 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax, 5501 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax, 5502 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax, 5503 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax, 5504 }; 5505 EXPORT_SYMBOL(rtw89_phy_gen_ax); 5506