1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "chan.h" 6 #include "coex.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "phy.h" 11 #include "ps.h" 12 #include "reg.h" 13 #include "sar.h" 14 #include "txrx.h" 15 #include "util.h" 16 17 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 18 { 19 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 20 21 return phy->phy0_phy1_offset(rtwdev, addr); 22 } 23 24 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 25 const struct rtw89_ra_report *report) 26 { 27 u32 bit_rate = report->bit_rate; 28 29 /* lower than ofdm, do not aggregate */ 30 if (bit_rate < 550) 31 return 1; 32 33 /* avoid AMSDU for legacy rate */ 34 if (report->might_fallback_legacy) 35 return 1; 36 37 /* lower than 20M vht 2ss mcs8, make it small */ 38 if (bit_rate < 1800) 39 return 1200; 40 41 /* lower than 40M vht 2ss mcs9, make it medium */ 42 if (bit_rate < 4000) 43 return 2600; 44 45 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 46 if (bit_rate < 7000) 47 return 3500; 48 49 return rtwdev->chip->max_amsdu_limit; 50 } 51 52 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 53 { 54 u64 ra_mask = 0; 55 u8 mcs_cap; 56 int i, nss; 57 58 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 59 mcs_cap = mcs_map & 0x3; 60 switch (mcs_cap) { 61 case 2: 62 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 63 break; 64 case 1: 65 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 66 break; 67 case 0: 68 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 69 break; 70 default: 71 break; 72 } 73 } 74 75 return ra_mask; 76 } 77 78 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 79 { 80 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 81 u16 mcs_map; 82 83 switch (sta->deflink.bandwidth) { 84 case IEEE80211_STA_RX_BW_160: 85 if (cap.he_cap_elem.phy_cap_info[0] & 86 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 87 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 88 else 89 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 90 break; 91 default: 92 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 93 } 94 95 /* MCS11, MCS9, MCS7 */ 96 return get_mcs_ra_mask(mcs_map, 11, 2); 97 } 98 99 static u64 get_eht_mcs_ra_mask(u8 *max_nss, u8 start_mcs, u8 n_nss) 100 { 101 u64 nss_mcs_shift; 102 u64 nss_mcs_val; 103 u64 mask = 0; 104 int i, j; 105 u8 nss; 106 107 for (i = 0; i < n_nss; i++) { 108 nss = u8_get_bits(max_nss[i], IEEE80211_EHT_MCS_NSS_RX); 109 if (!nss) 110 continue; 111 112 nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0); 113 114 for (j = 0, nss_mcs_shift = 12; j < nss; j++, nss_mcs_shift += 16) 115 mask |= nss_mcs_val << nss_mcs_shift; 116 } 117 118 return mask; 119 } 120 121 static u64 get_eht_ra_mask(struct ieee80211_sta *sta) 122 { 123 struct ieee80211_sta_eht_cap *eht_cap = &sta->deflink.eht_cap; 124 struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs_nss_20mhz; 125 struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss; 126 u8 *he_phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 127 128 switch (sta->deflink.bandwidth) { 129 case IEEE80211_STA_RX_BW_320: 130 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320; 131 /* MCS 9, 11, 13 */ 132 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 133 case IEEE80211_STA_RX_BW_160: 134 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160; 135 /* MCS 9, 11, 13 */ 136 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 137 case IEEE80211_STA_RX_BW_20: 138 if (!(he_phy_cap[0] & 139 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) { 140 mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz; 141 /* MCS 7, 9, 11, 13 */ 142 return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4); 143 } 144 fallthrough; 145 case IEEE80211_STA_RX_BW_80: 146 default: 147 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80; 148 /* MCS 9, 11, 13 */ 149 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 150 } 151 } 152 153 #define RA_FLOOR_TABLE_SIZE 7 154 #define RA_FLOOR_UP_GAP 3 155 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 156 u8 ratr_state) 157 { 158 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 159 u8 rssi_lv = 0; 160 u8 i; 161 162 rssi >>= 1; 163 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 164 if (i >= ratr_state) 165 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 166 if (rssi < rssi_lv_t[i]) { 167 rssi_lv = i; 168 break; 169 } 170 } 171 if (rssi_lv == 0) 172 return 0xffffffffffffffffULL; 173 else if (rssi_lv == 1) 174 return 0xfffffffffffffff0ULL; 175 else if (rssi_lv == 2) 176 return 0xffffffffffffefe0ULL; 177 else if (rssi_lv == 3) 178 return 0xffffffffffffcfc0ULL; 179 else if (rssi_lv == 4) 180 return 0xffffffffffff8f80ULL; 181 else if (rssi_lv >= 5) 182 return 0xffffffffffff0f00ULL; 183 184 return 0xffffffffffffffffULL; 185 } 186 187 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 188 { 189 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 190 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 191 192 if (ra_mask == 0) 193 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 194 195 return ra_mask; 196 } 197 198 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 199 const struct rtw89_chan *chan) 200 { 201 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 202 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 203 enum nl80211_band band; 204 u64 cfg_mask; 205 206 if (!rtwsta->use_cfg_mask) 207 return -1; 208 209 switch (chan->band_type) { 210 case RTW89_BAND_2G: 211 band = NL80211_BAND_2GHZ; 212 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 213 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 214 break; 215 case RTW89_BAND_5G: 216 band = NL80211_BAND_5GHZ; 217 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 218 RA_MASK_OFDM_RATES); 219 break; 220 case RTW89_BAND_6G: 221 band = NL80211_BAND_6GHZ; 222 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 223 RA_MASK_OFDM_RATES); 224 break; 225 default: 226 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 227 return -1; 228 } 229 230 if (sta->deflink.he_cap.has_he) { 231 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 232 RA_MASK_HE_1SS_RATES); 233 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 234 RA_MASK_HE_2SS_RATES); 235 } else if (sta->deflink.vht_cap.vht_supported) { 236 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 237 RA_MASK_VHT_1SS_RATES); 238 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 239 RA_MASK_VHT_2SS_RATES); 240 } else if (sta->deflink.ht_cap.ht_supported) { 241 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 242 RA_MASK_HT_1SS_RATES); 243 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 244 RA_MASK_HT_2SS_RATES); 245 } 246 247 return cfg_mask; 248 } 249 250 static const u64 251 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 252 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 253 static const u64 254 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 255 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 256 static const u64 257 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 258 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 259 static const u64 260 rtw89_ra_mask_eht_rates[4] = {RA_MASK_EHT_1SS_RATES, RA_MASK_EHT_2SS_RATES, 261 RA_MASK_EHT_3SS_RATES, RA_MASK_EHT_4SS_RATES}; 262 263 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 264 struct rtw89_sta *rtwsta, 265 const struct rtw89_chan *chan, 266 bool *fix_giltf_en, u8 *fix_giltf) 267 { 268 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 269 u8 band = chan->band_type; 270 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 271 u8 he_gi = mask->control[nl_band].he_gi; 272 u8 he_ltf = mask->control[nl_band].he_ltf; 273 274 if (!rtwsta->use_cfg_mask) 275 return; 276 277 if (he_ltf == 2 && he_gi == 2) { 278 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 279 } else if (he_ltf == 2 && he_gi == 0) { 280 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 281 } else if (he_ltf == 1 && he_gi == 1) { 282 *fix_giltf = RTW89_GILTF_2XHE16; 283 } else if (he_ltf == 1 && he_gi == 0) { 284 *fix_giltf = RTW89_GILTF_2XHE08; 285 } else if (he_ltf == 0 && he_gi == 1) { 286 *fix_giltf = RTW89_GILTF_1XHE16; 287 } else if (he_ltf == 0 && he_gi == 0) { 288 *fix_giltf = RTW89_GILTF_1XHE08; 289 } else { 290 *fix_giltf_en = false; 291 return; 292 } 293 294 *fix_giltf_en = true; 295 } 296 297 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 298 struct ieee80211_sta *sta, bool csi) 299 { 300 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 301 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 302 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 303 struct rtw89_ra_info *ra = &rtwsta->ra; 304 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 305 rtwvif->sub_entity_idx); 306 struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); 307 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 308 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 309 u64 ra_mask = 0; 310 u64 ra_mask_bak; 311 u8 mode = 0; 312 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 313 u8 bw_mode = 0; 314 u8 stbc_en = 0; 315 u8 ldpc_en = 0; 316 u8 fix_giltf = 0; 317 u8 i; 318 bool sgi = false; 319 bool fix_giltf_en = false; 320 321 memset(ra, 0, sizeof(*ra)); 322 /* Set the ra mask from sta's capability */ 323 if (sta->deflink.eht_cap.has_eht) { 324 mode |= RTW89_RA_MODE_EHT; 325 ra_mask |= get_eht_ra_mask(sta); 326 high_rate_masks = rtw89_ra_mask_eht_rates; 327 } else if (sta->deflink.he_cap.has_he) { 328 mode |= RTW89_RA_MODE_HE; 329 csi_mode = RTW89_RA_RPT_MODE_HE; 330 ra_mask |= get_he_ra_mask(sta); 331 high_rate_masks = rtw89_ra_mask_he_rates; 332 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 333 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 334 stbc_en = 1; 335 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 336 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 337 ldpc_en = 1; 338 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, chan, &fix_giltf_en, &fix_giltf); 339 } else if (sta->deflink.vht_cap.vht_supported) { 340 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 341 342 mode |= RTW89_RA_MODE_VHT; 343 csi_mode = RTW89_RA_RPT_MODE_VHT; 344 /* MCS9, MCS8, MCS7 */ 345 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 346 high_rate_masks = rtw89_ra_mask_vht_rates; 347 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 348 stbc_en = 1; 349 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 350 ldpc_en = 1; 351 } else if (sta->deflink.ht_cap.ht_supported) { 352 mode |= RTW89_RA_MODE_HT; 353 csi_mode = RTW89_RA_RPT_MODE_HT; 354 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 355 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 356 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 357 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 358 high_rate_masks = rtw89_ra_mask_ht_rates; 359 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 360 stbc_en = 1; 361 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 362 ldpc_en = 1; 363 } 364 365 switch (chan->band_type) { 366 case RTW89_BAND_2G: 367 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 368 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xf) 369 mode |= RTW89_RA_MODE_CCK; 370 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xff0) 371 mode |= RTW89_RA_MODE_OFDM; 372 break; 373 case RTW89_BAND_5G: 374 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 375 mode |= RTW89_RA_MODE_OFDM; 376 break; 377 case RTW89_BAND_6G: 378 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 379 mode |= RTW89_RA_MODE_OFDM; 380 break; 381 default: 382 rtw89_err(rtwdev, "Unknown band type\n"); 383 break; 384 } 385 386 ra_mask_bak = ra_mask; 387 388 if (mode >= RTW89_RA_MODE_HT) { 389 u64 mask = 0; 390 for (i = 0; i < rtwdev->hal.tx_nss; i++) 391 mask |= high_rate_masks[i]; 392 if (mode & RTW89_RA_MODE_OFDM) 393 mask |= RA_MASK_SUBOFDM_RATES; 394 if (mode & RTW89_RA_MODE_CCK) 395 mask |= RA_MASK_SUBCCK_RATES; 396 ra_mask &= mask; 397 } else if (mode & RTW89_RA_MODE_OFDM) { 398 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 399 } 400 401 if (mode != RTW89_RA_MODE_CCK) 402 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 403 404 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 405 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan); 406 407 switch (sta->deflink.bandwidth) { 408 case IEEE80211_STA_RX_BW_160: 409 bw_mode = RTW89_CHANNEL_WIDTH_160; 410 sgi = sta->deflink.vht_cap.vht_supported && 411 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 412 break; 413 case IEEE80211_STA_RX_BW_80: 414 bw_mode = RTW89_CHANNEL_WIDTH_80; 415 sgi = sta->deflink.vht_cap.vht_supported && 416 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 417 break; 418 case IEEE80211_STA_RX_BW_40: 419 bw_mode = RTW89_CHANNEL_WIDTH_40; 420 sgi = sta->deflink.ht_cap.ht_supported && 421 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 422 break; 423 default: 424 bw_mode = RTW89_CHANNEL_WIDTH_20; 425 sgi = sta->deflink.ht_cap.ht_supported && 426 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 427 break; 428 } 429 430 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 431 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 432 ra->dcm_cap = 1; 433 434 if (rate_pattern->enable && !vif->p2p) { 435 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan); 436 ra_mask &= rate_pattern->ra_mask; 437 mode = rate_pattern->ra_mode; 438 } 439 440 ra->bw_cap = bw_mode; 441 ra->er_cap = rtwsta->er_cap; 442 ra->mode_ctrl = mode; 443 ra->macid = rtwsta->mac_id; 444 ra->stbc_cap = stbc_en; 445 ra->ldpc_cap = ldpc_en; 446 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 447 ra->en_sgi = sgi; 448 ra->ra_mask = ra_mask; 449 ra->fix_giltf_en = fix_giltf_en; 450 ra->fix_giltf = fix_giltf; 451 452 if (!csi) 453 return; 454 455 ra->fixed_csi_rate_en = false; 456 ra->ra_csi_rate_en = true; 457 ra->cr_tbl_sel = false; 458 ra->band_num = rtwvif->phy_idx; 459 ra->csi_bw = bw_mode; 460 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 461 ra->csi_mcs_ss_idx = 5; 462 ra->csi_mode = csi_mode; 463 } 464 465 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 466 u32 changed) 467 { 468 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 469 struct rtw89_ra_info *ra = &rtwsta->ra; 470 471 rtw89_phy_ra_sta_update(rtwdev, sta, false); 472 473 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 474 ra->upd_mask = 1; 475 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 476 ra->upd_bw_nss_mask = 1; 477 478 rtw89_debug(rtwdev, RTW89_DBG_RA, 479 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 480 ra->macid, 481 ra->bw_cap, 482 ra->ss_num, 483 ra->en_sgi, 484 ra->giltf); 485 486 rtw89_fw_h2c_ra(rtwdev, ra, false); 487 } 488 489 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 490 u16 rate_base, u64 ra_mask, u8 ra_mode, 491 u32 rate_ctrl, u32 ctrl_skip, bool force) 492 { 493 u8 n, c; 494 495 if (rate_ctrl == ctrl_skip) 496 return true; 497 498 n = hweight32(rate_ctrl); 499 if (n == 0) 500 return true; 501 502 if (force && n != 1) 503 return false; 504 505 if (next->enable) 506 return false; 507 508 c = __fls(rate_ctrl); 509 next->rate = rate_base + c; 510 next->ra_mode = ra_mode; 511 next->ra_mask = ra_mask; 512 next->enable = true; 513 514 return true; 515 } 516 517 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \ 518 { \ 519 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \ 520 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \ 521 } 522 523 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 524 struct ieee80211_vif *vif, 525 const struct cfg80211_bitrate_mask *mask) 526 { 527 struct ieee80211_supported_band *sband; 528 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 529 struct rtw89_phy_rate_pattern next_pattern = {0}; 530 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 531 rtwvif->sub_entity_idx); 532 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = { 533 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0), 534 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0), 535 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0), 536 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0), 537 }; 538 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = { 539 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0), 540 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0), 541 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0), 542 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0), 543 }; 544 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = { 545 RTW89_HW_RATE_BY_CHIP_GEN(MCS0), 546 RTW89_HW_RATE_BY_CHIP_GEN(MCS8), 547 RTW89_HW_RATE_BY_CHIP_GEN(MCS16), 548 RTW89_HW_RATE_BY_CHIP_GEN(MCS24), 549 }; 550 u8 band = chan->band_type; 551 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 552 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 553 u8 tx_nss = rtwdev->hal.tx_nss; 554 u8 i; 555 556 for (i = 0; i < tx_nss; i++) 557 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen], 558 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 559 mask->control[nl_band].he_mcs[i], 560 0, true)) 561 goto out; 562 563 for (i = 0; i < tx_nss; i++) 564 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen], 565 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 566 mask->control[nl_band].vht_mcs[i], 567 0, true)) 568 goto out; 569 570 for (i = 0; i < tx_nss; i++) 571 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen], 572 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 573 mask->control[nl_band].ht_mcs[i], 574 0, true)) 575 goto out; 576 577 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 578 * require at least one basic rate for ieee80211_set_bitrate_mask, 579 * so the decision just depends on if all bitrates are set or not. 580 */ 581 sband = rtwdev->hw->wiphy->bands[nl_band]; 582 if (band == RTW89_BAND_2G) { 583 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 584 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 585 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 586 mask->control[nl_band].legacy, 587 BIT(sband->n_bitrates) - 1, false)) 588 goto out; 589 } else { 590 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 591 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 592 mask->control[nl_band].legacy, 593 BIT(sband->n_bitrates) - 1, false)) 594 goto out; 595 } 596 597 if (!next_pattern.enable) 598 goto out; 599 600 rtwvif->rate_pattern = next_pattern; 601 rtw89_debug(rtwdev, RTW89_DBG_RA, 602 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 603 next_pattern.rate, 604 next_pattern.ra_mask, 605 next_pattern.ra_mode); 606 return; 607 608 out: 609 rtwvif->rate_pattern.enable = false; 610 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 611 } 612 613 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 614 { 615 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 616 617 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 618 } 619 620 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 621 { 622 ieee80211_iterate_stations_atomic(rtwdev->hw, 623 rtw89_phy_ra_updata_sta_iter, 624 rtwdev); 625 } 626 627 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 628 { 629 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 630 struct rtw89_ra_info *ra = &rtwsta->ra; 631 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 632 bool csi = rtw89_sta_has_beamformer_cap(sta); 633 634 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 635 636 if (rssi > 40) 637 ra->init_rate_lv = 1; 638 else if (rssi > 20) 639 ra->init_rate_lv = 2; 640 else if (rssi > 1) 641 ra->init_rate_lv = 3; 642 else 643 ra->init_rate_lv = 0; 644 ra->upd_all = 1; 645 rtw89_debug(rtwdev, RTW89_DBG_RA, 646 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 647 ra->macid, 648 ra->mode_ctrl, 649 ra->bw_cap, 650 ra->ss_num, 651 ra->init_rate_lv); 652 rtw89_debug(rtwdev, RTW89_DBG_RA, 653 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 654 ra->dcm_cap, 655 ra->er_cap, 656 ra->ldpc_cap, 657 ra->stbc_cap, 658 ra->en_sgi, 659 ra->giltf); 660 661 rtw89_fw_h2c_ra(rtwdev, ra, csi); 662 } 663 664 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 665 const struct rtw89_chan *chan, 666 enum rtw89_bandwidth dbw) 667 { 668 enum rtw89_bandwidth cbw = chan->band_width; 669 u8 pri_ch = chan->primary_channel; 670 u8 central_ch = chan->channel; 671 u8 txsc_idx = 0; 672 u8 tmp = 0; 673 674 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 675 return txsc_idx; 676 677 switch (cbw) { 678 case RTW89_CHANNEL_WIDTH_40: 679 txsc_idx = pri_ch > central_ch ? 1 : 2; 680 break; 681 case RTW89_CHANNEL_WIDTH_80: 682 if (dbw == RTW89_CHANNEL_WIDTH_20) { 683 if (pri_ch > central_ch) 684 txsc_idx = (pri_ch - central_ch) >> 1; 685 else 686 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 687 } else { 688 txsc_idx = pri_ch > central_ch ? 9 : 10; 689 } 690 break; 691 case RTW89_CHANNEL_WIDTH_160: 692 if (pri_ch > central_ch) 693 tmp = (pri_ch - central_ch) >> 1; 694 else 695 tmp = ((central_ch - pri_ch) >> 1) + 1; 696 697 if (dbw == RTW89_CHANNEL_WIDTH_20) { 698 txsc_idx = tmp; 699 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 700 if (tmp == 1 || tmp == 3) 701 txsc_idx = 9; 702 else if (tmp == 5 || tmp == 7) 703 txsc_idx = 11; 704 else if (tmp == 2 || tmp == 4) 705 txsc_idx = 10; 706 else if (tmp == 6 || tmp == 8) 707 txsc_idx = 12; 708 else 709 return 0xff; 710 } else { 711 txsc_idx = pri_ch > central_ch ? 13 : 14; 712 } 713 break; 714 case RTW89_CHANNEL_WIDTH_80_80: 715 if (dbw == RTW89_CHANNEL_WIDTH_20) { 716 if (pri_ch > central_ch) 717 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 718 else 719 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 720 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 721 txsc_idx = pri_ch > central_ch ? 10 : 12; 722 } else { 723 txsc_idx = 14; 724 } 725 break; 726 default: 727 break; 728 } 729 730 return txsc_idx; 731 } 732 EXPORT_SYMBOL(rtw89_phy_get_txsc); 733 734 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 735 enum rtw89_bandwidth dbw) 736 { 737 enum rtw89_bandwidth cbw = chan->band_width; 738 u8 pri_ch = chan->primary_channel; 739 u8 central_ch = chan->channel; 740 u8 txsb_idx = 0; 741 742 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 743 return txsb_idx; 744 745 switch (cbw) { 746 case RTW89_CHANNEL_WIDTH_40: 747 txsb_idx = pri_ch > central_ch ? 1 : 0; 748 break; 749 case RTW89_CHANNEL_WIDTH_80: 750 if (dbw == RTW89_CHANNEL_WIDTH_20) 751 txsb_idx = (pri_ch - central_ch + 6) / 4; 752 else 753 txsb_idx = pri_ch > central_ch ? 1 : 0; 754 break; 755 case RTW89_CHANNEL_WIDTH_160: 756 if (dbw == RTW89_CHANNEL_WIDTH_20) 757 txsb_idx = (pri_ch - central_ch + 14) / 4; 758 else if (dbw == RTW89_CHANNEL_WIDTH_40) 759 txsb_idx = (pri_ch - central_ch + 12) / 8; 760 else 761 txsb_idx = pri_ch > central_ch ? 1 : 0; 762 break; 763 case RTW89_CHANNEL_WIDTH_320: 764 if (dbw == RTW89_CHANNEL_WIDTH_20) 765 txsb_idx = (pri_ch - central_ch + 30) / 4; 766 else if (dbw == RTW89_CHANNEL_WIDTH_40) 767 txsb_idx = (pri_ch - central_ch + 28) / 8; 768 else if (dbw == RTW89_CHANNEL_WIDTH_80) 769 txsb_idx = (pri_ch - central_ch + 24) / 16; 770 else 771 txsb_idx = pri_ch > central_ch ? 1 : 0; 772 break; 773 default: 774 break; 775 } 776 777 return txsb_idx; 778 } 779 EXPORT_SYMBOL(rtw89_phy_get_txsb); 780 781 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 782 { 783 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 784 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 785 } 786 787 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 788 u32 addr, u32 mask) 789 { 790 const struct rtw89_chip_info *chip = rtwdev->chip; 791 const u32 *base_addr = chip->rf_base_addr; 792 u32 val, direct_addr; 793 794 if (rf_path >= rtwdev->chip->rf_path_num) { 795 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 796 return INV_RF_DATA; 797 } 798 799 addr &= 0xff; 800 direct_addr = base_addr[rf_path] + (addr << 2); 801 mask &= RFREG_MASK; 802 803 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 804 805 return val; 806 } 807 EXPORT_SYMBOL(rtw89_phy_read_rf); 808 809 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 810 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 811 { 812 bool busy; 813 bool done; 814 u32 val; 815 int ret; 816 817 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 818 1, 30, false, rtwdev); 819 if (ret) { 820 rtw89_err(rtwdev, "read rf busy swsi\n"); 821 return INV_RF_DATA; 822 } 823 824 mask &= RFREG_MASK; 825 826 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 827 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 828 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 829 udelay(2); 830 831 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 832 30, false, rtwdev, R_SWSI_V1, 833 B_SWSI_R_DATA_DONE_V1); 834 if (ret) { 835 rtw89_err(rtwdev, "read swsi busy\n"); 836 return INV_RF_DATA; 837 } 838 839 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 840 } 841 842 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 843 u32 addr, u32 mask) 844 { 845 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 846 847 if (rf_path >= rtwdev->chip->rf_path_num) { 848 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 849 return INV_RF_DATA; 850 } 851 852 if (ad_sel) 853 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 854 else 855 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 856 } 857 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 858 859 static u32 rtw89_phy_read_full_rf_v2_a(struct rtw89_dev *rtwdev, 860 enum rtw89_rf_path rf_path, u32 addr) 861 { 862 static const u16 r_addr_ofst[2] = {0x2C24, 0x2D24}; 863 static const u16 addr_ofst[2] = {0x2ADC, 0x2BDC}; 864 bool busy, done; 865 int ret; 866 u32 val; 867 868 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_CTL_MASK, 0x1); 869 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, 870 1, 3800, false, 871 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_BUSY); 872 if (ret) { 873 rtw89_warn(rtwdev, "poll HWSI is busy\n"); 874 return INV_RF_DATA; 875 } 876 877 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_MASK, addr); 878 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_RD, 0x1); 879 udelay(2); 880 881 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 882 1, 3800, false, 883 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_RDONE); 884 if (ret) { 885 rtw89_warn(rtwdev, "read HWSI is busy\n"); 886 val = INV_RF_DATA; 887 goto out; 888 } 889 890 val = rtw89_phy_read32_mask(rtwdev, r_addr_ofst[rf_path], RFREG_MASK); 891 out: 892 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_POLL_MASK, 0); 893 894 return val; 895 } 896 897 static u32 rtw89_phy_read_rf_v2_a(struct rtw89_dev *rtwdev, 898 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 899 { 900 u32 val; 901 902 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr); 903 904 return (val & mask) >> __ffs(mask); 905 } 906 907 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 908 u32 addr, u32 mask) 909 { 910 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); 911 912 if (rf_path >= rtwdev->chip->rf_path_num) { 913 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 914 return INV_RF_DATA; 915 } 916 917 if (ad_sel) 918 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 919 else 920 return rtw89_phy_read_rf_v2_a(rtwdev, rf_path, addr, mask); 921 } 922 EXPORT_SYMBOL(rtw89_phy_read_rf_v2); 923 924 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 925 u32 addr, u32 mask, u32 data) 926 { 927 const struct rtw89_chip_info *chip = rtwdev->chip; 928 const u32 *base_addr = chip->rf_base_addr; 929 u32 direct_addr; 930 931 if (rf_path >= rtwdev->chip->rf_path_num) { 932 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 933 return false; 934 } 935 936 addr &= 0xff; 937 direct_addr = base_addr[rf_path] + (addr << 2); 938 mask &= RFREG_MASK; 939 940 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 941 942 /* delay to ensure writing properly */ 943 udelay(1); 944 945 return true; 946 } 947 EXPORT_SYMBOL(rtw89_phy_write_rf); 948 949 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 950 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 951 u32 data) 952 { 953 u8 bit_shift; 954 u32 val; 955 bool busy, b_msk_en = false; 956 int ret; 957 958 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 959 1, 30, false, rtwdev); 960 if (ret) { 961 rtw89_err(rtwdev, "write rf busy swsi\n"); 962 return false; 963 } 964 965 data &= RFREG_MASK; 966 mask &= RFREG_MASK; 967 968 if (mask != RFREG_MASK) { 969 b_msk_en = true; 970 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 971 mask); 972 bit_shift = __ffs(mask); 973 data = (data << bit_shift) & RFREG_MASK; 974 } 975 976 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 977 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 978 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 979 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 980 981 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 982 983 return true; 984 } 985 986 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 987 u32 addr, u32 mask, u32 data) 988 { 989 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 990 991 if (rf_path >= rtwdev->chip->rf_path_num) { 992 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 993 return false; 994 } 995 996 if (ad_sel) 997 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 998 else 999 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 1000 } 1001 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 1002 1003 static 1004 bool rtw89_phy_write_full_rf_v2_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1005 u32 addr, u32 data) 1006 { 1007 static const u32 addr_is_idle[2] = {0x2C24, 0x2D24}; 1008 static const u32 addr_ofst[2] = {0x2AE0, 0x2BE0}; 1009 bool busy; 1010 u32 val; 1011 int ret; 1012 1013 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, 1014 1, 3800, false, 1015 rtwdev, addr_is_idle[rf_path], BIT(29)); 1016 if (ret) { 1017 rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__); 1018 return false; 1019 } 1020 1021 val = u32_encode_bits(addr, B_HWSI_DATA_ADDR) | 1022 u32_encode_bits(data, B_HWSI_DATA_VAL); 1023 1024 rtw89_phy_write32(rtwdev, addr_ofst[rf_path], val); 1025 1026 return true; 1027 } 1028 1029 static 1030 bool rtw89_phy_write_rf_a_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1031 u32 addr, u32 mask, u32 data) 1032 { 1033 u32 val; 1034 1035 if (mask == RFREG_MASK) { 1036 val = data; 1037 } else { 1038 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr); 1039 val &= ~mask; 1040 val |= (data << __ffs(mask)) & mask; 1041 } 1042 1043 return rtw89_phy_write_full_rf_v2_a(rtwdev, rf_path, addr, val); 1044 } 1045 1046 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1047 u32 addr, u32 mask, u32 data) 1048 { 1049 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); 1050 1051 if (rf_path >= rtwdev->chip->rf_path_num) { 1052 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 1053 return INV_RF_DATA; 1054 } 1055 1056 if (ad_sel) 1057 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 1058 else 1059 return rtw89_phy_write_rf_a_v2(rtwdev, rf_path, addr, mask, data); 1060 } 1061 EXPORT_SYMBOL(rtw89_phy_write_rf_v2); 1062 1063 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 1064 { 1065 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; 1066 } 1067 1068 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 1069 enum rtw89_phy_idx phy_idx) 1070 { 1071 const struct rtw89_chip_info *chip = rtwdev->chip; 1072 1073 chip->ops->bb_reset(rtwdev, phy_idx); 1074 } 1075 1076 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 1077 const struct rtw89_reg2_def *reg, 1078 enum rtw89_rf_path rf_path, 1079 void *extra_data) 1080 { 1081 u32 addr; 1082 1083 if (reg->addr == 0xfe) { 1084 mdelay(50); 1085 } else if (reg->addr == 0xfd) { 1086 mdelay(5); 1087 } else if (reg->addr == 0xfc) { 1088 mdelay(1); 1089 } else if (reg->addr == 0xfb) { 1090 udelay(50); 1091 } else if (reg->addr == 0xfa) { 1092 udelay(5); 1093 } else if (reg->addr == 0xf9) { 1094 udelay(1); 1095 } else if (reg->data == BYPASS_CR_DATA) { 1096 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr); 1097 } else { 1098 addr = reg->addr; 1099 1100 if ((uintptr_t)extra_data == RTW89_PHY_1) 1101 addr += rtw89_phy0_phy1_offset(rtwdev, reg->addr); 1102 1103 rtw89_phy_write32(rtwdev, addr, reg->data); 1104 } 1105 } 1106 1107 union rtw89_phy_bb_gain_arg { 1108 u32 addr; 1109 struct { 1110 union { 1111 u8 type; 1112 struct { 1113 u8 rxsc_start:4; 1114 u8 bw:4; 1115 }; 1116 }; 1117 u8 path; 1118 u8 gain_band; 1119 u8 cfg_type; 1120 }; 1121 } __packed; 1122 1123 static void 1124 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 1125 union rtw89_phy_bb_gain_arg arg, u32 data) 1126 { 1127 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1128 u8 type = arg.type; 1129 u8 path = arg.path; 1130 u8 gband = arg.gain_band; 1131 int i; 1132 1133 switch (type) { 1134 case 0: 1135 for (i = 0; i < 4; i++, data >>= 8) 1136 gain->lna_gain[gband][path][i] = data & 0xff; 1137 break; 1138 case 1: 1139 for (i = 4; i < 7; i++, data >>= 8) 1140 gain->lna_gain[gband][path][i] = data & 0xff; 1141 break; 1142 case 2: 1143 for (i = 0; i < 2; i++, data >>= 8) 1144 gain->tia_gain[gband][path][i] = data & 0xff; 1145 break; 1146 default: 1147 rtw89_warn(rtwdev, 1148 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 1149 arg.addr, data, type); 1150 break; 1151 } 1152 } 1153 1154 enum rtw89_phy_bb_rxsc_start_idx { 1155 RTW89_BB_RXSC_START_IDX_FULL = 0, 1156 RTW89_BB_RXSC_START_IDX_20 = 1, 1157 RTW89_BB_RXSC_START_IDX_20_1 = 5, 1158 RTW89_BB_RXSC_START_IDX_40 = 9, 1159 RTW89_BB_RXSC_START_IDX_80 = 13, 1160 }; 1161 1162 static void 1163 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 1164 union rtw89_phy_bb_gain_arg arg, u32 data) 1165 { 1166 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1167 u8 rxsc_start = arg.rxsc_start; 1168 u8 bw = arg.bw; 1169 u8 path = arg.path; 1170 u8 gband = arg.gain_band; 1171 u8 rxsc; 1172 s8 ofst; 1173 int i; 1174 1175 switch (bw) { 1176 case RTW89_CHANNEL_WIDTH_20: 1177 gain->rpl_ofst_20[gband][path] = (s8)data; 1178 break; 1179 case RTW89_CHANNEL_WIDTH_40: 1180 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1181 gain->rpl_ofst_40[gband][path][0] = (s8)data; 1182 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1183 for (i = 0; i < 2; i++, data >>= 8) { 1184 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1185 ofst = (s8)(data & 0xff); 1186 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 1187 } 1188 } 1189 break; 1190 case RTW89_CHANNEL_WIDTH_80: 1191 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1192 gain->rpl_ofst_80[gband][path][0] = (s8)data; 1193 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1194 for (i = 0; i < 4; i++, data >>= 8) { 1195 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1196 ofst = (s8)(data & 0xff); 1197 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 1198 } 1199 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 1200 for (i = 0; i < 2; i++, data >>= 8) { 1201 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 1202 ofst = (s8)(data & 0xff); 1203 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 1204 } 1205 } 1206 break; 1207 case RTW89_CHANNEL_WIDTH_160: 1208 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1209 gain->rpl_ofst_160[gband][path][0] = (s8)data; 1210 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1211 for (i = 0; i < 4; i++, data >>= 8) { 1212 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1213 ofst = (s8)(data & 0xff); 1214 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1215 } 1216 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 1217 for (i = 0; i < 4; i++, data >>= 8) { 1218 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 1219 ofst = (s8)(data & 0xff); 1220 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1221 } 1222 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 1223 for (i = 0; i < 4; i++, data >>= 8) { 1224 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 1225 ofst = (s8)(data & 0xff); 1226 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1227 } 1228 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 1229 for (i = 0; i < 2; i++, data >>= 8) { 1230 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 1231 ofst = (s8)(data & 0xff); 1232 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1233 } 1234 } 1235 break; 1236 default: 1237 rtw89_warn(rtwdev, 1238 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 1239 arg.addr, data, bw); 1240 break; 1241 } 1242 } 1243 1244 static void 1245 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 1246 union rtw89_phy_bb_gain_arg arg, u32 data) 1247 { 1248 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1249 u8 type = arg.type; 1250 u8 path = arg.path; 1251 u8 gband = arg.gain_band; 1252 int i; 1253 1254 switch (type) { 1255 case 0: 1256 for (i = 0; i < 4; i++, data >>= 8) 1257 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1258 break; 1259 case 1: 1260 for (i = 4; i < 7; i++, data >>= 8) 1261 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1262 break; 1263 default: 1264 rtw89_warn(rtwdev, 1265 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 1266 arg.addr, data, type); 1267 break; 1268 } 1269 } 1270 1271 static void 1272 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 1273 union rtw89_phy_bb_gain_arg arg, u32 data) 1274 { 1275 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1276 u8 type = arg.type; 1277 u8 path = arg.path; 1278 u8 gband = arg.gain_band; 1279 int i; 1280 1281 switch (type) { 1282 case 0: 1283 for (i = 0; i < 4; i++, data >>= 8) 1284 gain->lna_op1db[gband][path][i] = data & 0xff; 1285 break; 1286 case 1: 1287 for (i = 4; i < 7; i++, data >>= 8) 1288 gain->lna_op1db[gband][path][i] = data & 0xff; 1289 break; 1290 case 2: 1291 for (i = 0; i < 4; i++, data >>= 8) 1292 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1293 break; 1294 case 3: 1295 for (i = 4; i < 8; i++, data >>= 8) 1296 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1297 break; 1298 default: 1299 rtw89_warn(rtwdev, 1300 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1301 arg.addr, data, type); 1302 break; 1303 } 1304 } 1305 1306 static void rtw89_phy_config_bb_gain_ax(struct rtw89_dev *rtwdev, 1307 const struct rtw89_reg2_def *reg, 1308 enum rtw89_rf_path rf_path, 1309 void *extra_data) 1310 { 1311 const struct rtw89_chip_info *chip = rtwdev->chip; 1312 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1313 struct rtw89_efuse *efuse = &rtwdev->efuse; 1314 1315 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1316 return; 1317 1318 if (arg.path >= chip->rf_path_num) 1319 return; 1320 1321 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1322 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1323 return; 1324 } 1325 1326 switch (arg.cfg_type) { 1327 case 0: 1328 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1329 break; 1330 case 1: 1331 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1332 break; 1333 case 2: 1334 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1335 break; 1336 case 3: 1337 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1338 break; 1339 case 4: 1340 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 1341 if (efuse->rfe_type < 50) 1342 break; 1343 fallthrough; 1344 default: 1345 rtw89_warn(rtwdev, 1346 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1347 arg.addr, reg->data, arg.cfg_type); 1348 break; 1349 } 1350 } 1351 1352 static void 1353 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1354 const struct rtw89_reg2_def *reg, 1355 enum rtw89_rf_path rf_path, 1356 struct rtw89_fw_h2c_rf_reg_info *info) 1357 { 1358 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1359 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1360 1361 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1362 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1363 rf_path, info->curr_idx); 1364 return; 1365 } 1366 1367 info->rtw89_phy_config_rf_h2c[page][idx] = 1368 cpu_to_le32((reg->addr << 20) | reg->data); 1369 info->curr_idx++; 1370 } 1371 1372 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1373 struct rtw89_fw_h2c_rf_reg_info *info) 1374 { 1375 u16 remain = info->curr_idx; 1376 u16 len = 0; 1377 u8 i; 1378 int ret = 0; 1379 1380 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1381 rtw89_warn(rtwdev, 1382 "rf reg h2c total len %d larger than %d\n", 1383 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1384 ret = -EINVAL; 1385 goto out; 1386 } 1387 1388 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1389 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1390 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1391 if (ret) 1392 goto out; 1393 } 1394 out: 1395 info->curr_idx = 0; 1396 1397 return ret; 1398 } 1399 1400 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev, 1401 const struct rtw89_reg2_def *reg, 1402 enum rtw89_rf_path rf_path, 1403 void *extra_data) 1404 { 1405 u32 addr = reg->addr; 1406 1407 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || 1408 addr == 0xfa || addr == 0xf9) 1409 return; 1410 1411 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100) 1412 return; 1413 1414 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1415 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1416 } 1417 1418 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1419 const struct rtw89_reg2_def *reg, 1420 enum rtw89_rf_path rf_path, 1421 void *extra_data) 1422 { 1423 if (reg->addr == 0xfe) { 1424 mdelay(50); 1425 } else if (reg->addr == 0xfd) { 1426 mdelay(5); 1427 } else if (reg->addr == 0xfc) { 1428 mdelay(1); 1429 } else if (reg->addr == 0xfb) { 1430 udelay(50); 1431 } else if (reg->addr == 0xfa) { 1432 udelay(5); 1433 } else if (reg->addr == 0xf9) { 1434 udelay(1); 1435 } else { 1436 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1437 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1438 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1439 } 1440 } 1441 1442 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1443 const struct rtw89_reg2_def *reg, 1444 enum rtw89_rf_path rf_path, 1445 void *extra_data) 1446 { 1447 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1448 1449 if (reg->addr < 0x100) 1450 return; 1451 1452 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1453 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1454 } 1455 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1456 1457 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1458 const struct rtw89_phy_table *table, 1459 u32 *headline_size, u32 *headline_idx, 1460 u8 rfe, u8 cv) 1461 { 1462 const struct rtw89_reg2_def *reg; 1463 u32 headline; 1464 u32 compare, target; 1465 u8 rfe_para, cv_para; 1466 u8 cv_max = 0; 1467 bool case_matched = false; 1468 u32 i; 1469 1470 for (i = 0; i < table->n_regs; i++) { 1471 reg = &table->regs[i]; 1472 headline = get_phy_headline(reg->addr); 1473 if (headline != PHY_HEADLINE_VALID) 1474 break; 1475 } 1476 *headline_size = i; 1477 if (*headline_size == 0) 1478 return 0; 1479 1480 /* case 1: RFE match, CV match */ 1481 compare = get_phy_compare(rfe, cv); 1482 for (i = 0; i < *headline_size; i++) { 1483 reg = &table->regs[i]; 1484 target = get_phy_target(reg->addr); 1485 if (target == compare) { 1486 *headline_idx = i; 1487 return 0; 1488 } 1489 } 1490 1491 /* case 2: RFE match, CV don't care */ 1492 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1493 for (i = 0; i < *headline_size; i++) { 1494 reg = &table->regs[i]; 1495 target = get_phy_target(reg->addr); 1496 if (target == compare) { 1497 *headline_idx = i; 1498 return 0; 1499 } 1500 } 1501 1502 /* case 3: RFE match, CV max in table */ 1503 for (i = 0; i < *headline_size; i++) { 1504 reg = &table->regs[i]; 1505 rfe_para = get_phy_cond_rfe(reg->addr); 1506 cv_para = get_phy_cond_cv(reg->addr); 1507 if (rfe_para == rfe) { 1508 if (cv_para >= cv_max) { 1509 cv_max = cv_para; 1510 *headline_idx = i; 1511 case_matched = true; 1512 } 1513 } 1514 } 1515 1516 if (case_matched) 1517 return 0; 1518 1519 /* case 4: RFE don't care, CV max in table */ 1520 for (i = 0; i < *headline_size; i++) { 1521 reg = &table->regs[i]; 1522 rfe_para = get_phy_cond_rfe(reg->addr); 1523 cv_para = get_phy_cond_cv(reg->addr); 1524 if (rfe_para == PHY_COND_DONT_CARE) { 1525 if (cv_para >= cv_max) { 1526 cv_max = cv_para; 1527 *headline_idx = i; 1528 case_matched = true; 1529 } 1530 } 1531 } 1532 1533 if (case_matched) 1534 return 0; 1535 1536 return -EINVAL; 1537 } 1538 1539 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1540 const struct rtw89_phy_table *table, 1541 void (*config)(struct rtw89_dev *rtwdev, 1542 const struct rtw89_reg2_def *reg, 1543 enum rtw89_rf_path rf_path, 1544 void *data), 1545 void *extra_data) 1546 { 1547 const struct rtw89_reg2_def *reg; 1548 enum rtw89_rf_path rf_path = table->rf_path; 1549 u8 rfe = rtwdev->efuse.rfe_type; 1550 u8 cv = rtwdev->hal.cv; 1551 u32 i; 1552 u32 headline_size = 0, headline_idx = 0; 1553 u32 target = 0, cfg_target; 1554 u8 cond; 1555 bool is_matched = true; 1556 bool target_found = false; 1557 int ret; 1558 1559 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1560 &headline_idx, rfe, cv); 1561 if (ret) { 1562 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1563 return; 1564 } 1565 1566 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1567 for (i = headline_size; i < table->n_regs; i++) { 1568 reg = &table->regs[i]; 1569 cond = get_phy_cond(reg->addr); 1570 switch (cond) { 1571 case PHY_COND_BRANCH_IF: 1572 case PHY_COND_BRANCH_ELIF: 1573 target = get_phy_target(reg->addr); 1574 break; 1575 case PHY_COND_BRANCH_ELSE: 1576 is_matched = false; 1577 if (!target_found) { 1578 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1579 reg->addr, reg->data); 1580 return; 1581 } 1582 break; 1583 case PHY_COND_BRANCH_END: 1584 is_matched = true; 1585 target_found = false; 1586 break; 1587 case PHY_COND_CHECK: 1588 if (target_found) { 1589 is_matched = false; 1590 break; 1591 } 1592 1593 if (target == cfg_target) { 1594 is_matched = true; 1595 target_found = true; 1596 } else { 1597 is_matched = false; 1598 target_found = false; 1599 } 1600 break; 1601 default: 1602 if (is_matched) 1603 config(rtwdev, reg, rf_path, extra_data); 1604 break; 1605 } 1606 } 1607 } 1608 1609 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1610 { 1611 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1612 const struct rtw89_chip_info *chip = rtwdev->chip; 1613 const struct rtw89_phy_table *bb_table; 1614 const struct rtw89_phy_table *bb_gain_table; 1615 1616 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table; 1617 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1618 if (rtwdev->dbcc_en) 1619 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, 1620 (void *)RTW89_PHY_1); 1621 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1622 1623 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table; 1624 if (bb_gain_table) 1625 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1626 chip->phy_def->config_bb_gain, NULL); 1627 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1628 } 1629 1630 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1631 { 1632 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1633 udelay(1); 1634 return rtw89_phy_read32(rtwdev, 0x8080); 1635 } 1636 1637 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio) 1638 { 1639 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1640 enum rtw89_rf_path rf_path, void *data); 1641 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1642 const struct rtw89_chip_info *chip = rtwdev->chip; 1643 const struct rtw89_phy_table *rf_table; 1644 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1645 u8 path; 1646 1647 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1648 if (!rf_reg_info) 1649 return; 1650 1651 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1652 rf_table = elm_info->rf_radio[path] ? 1653 elm_info->rf_radio[path] : chip->rf_table[path]; 1654 rf_reg_info->rf_path = rf_table->rf_path; 1655 if (noio) 1656 config = rtw89_phy_config_rf_reg_noio; 1657 else 1658 config = rf_table->config ? rf_table->config : 1659 rtw89_phy_config_rf_reg; 1660 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1661 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1662 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1663 rf_reg_info->rf_path); 1664 } 1665 kfree(rf_reg_info); 1666 } 1667 1668 static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev) 1669 { 1670 const struct rtw89_chip_info *chip = rtwdev->chip; 1671 u32 val; 1672 int ret; 1673 1674 /* IQK/DPK clock & reset */ 1675 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3); 1676 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1); 1677 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000); 1678 if (chip->chip_id != RTL8851B) 1679 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000); 1680 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8852BT) 1681 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2); 1682 1683 /* check 0x8080 */ 1684 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8); 1685 1686 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1687 1000, false, rtwdev); 1688 if (ret) 1689 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1690 } 1691 1692 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1693 { 1694 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1695 const struct rtw89_chip_info *chip = rtwdev->chip; 1696 const struct rtw89_phy_table *nctl_table; 1697 1698 rtw89_phy_preinit_rf_nctl(rtwdev); 1699 1700 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table; 1701 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1702 1703 if (chip->nctl_post_table) 1704 rtw89_rfk_parser(rtwdev, chip->nctl_post_table); 1705 } 1706 1707 static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr) 1708 { 1709 u32 phy_page = addr >> 8; 1710 u32 ofst = 0; 1711 1712 switch (phy_page) { 1713 case 0x6: 1714 case 0x7: 1715 case 0x8: 1716 case 0x9: 1717 case 0xa: 1718 case 0xb: 1719 case 0xc: 1720 case 0xd: 1721 case 0x19: 1722 case 0x1a: 1723 case 0x1b: 1724 ofst = 0x2000; 1725 break; 1726 default: 1727 /* warning case */ 1728 ofst = 0; 1729 break; 1730 } 1731 1732 if (phy_page >= 0x40 && phy_page <= 0x4f) 1733 ofst = 0x2000; 1734 1735 return ofst; 1736 } 1737 1738 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1739 u32 data, enum rtw89_phy_idx phy_idx) 1740 { 1741 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1742 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1743 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1744 } 1745 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1746 1747 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1748 enum rtw89_phy_idx phy_idx) 1749 { 1750 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1751 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1752 return rtw89_phy_read32_mask(rtwdev, addr, mask); 1753 } 1754 EXPORT_SYMBOL(rtw89_phy_read32_idx); 1755 1756 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1757 u32 val) 1758 { 1759 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1760 1761 if (!rtwdev->dbcc_en) 1762 return; 1763 1764 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1765 } 1766 EXPORT_SYMBOL(rtw89_phy_set_phy_regs); 1767 1768 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1769 const struct rtw89_phy_reg3_tbl *tbl) 1770 { 1771 const struct rtw89_reg3_def *reg3; 1772 int i; 1773 1774 for (i = 0; i < tbl->size; i++) { 1775 reg3 = &tbl->reg3[i]; 1776 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1777 } 1778 } 1779 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1780 1781 static const u8 rtw89_rs_idx_num_ax[] = { 1782 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM, 1783 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM, 1784 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX, 1785 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM, 1786 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX, 1787 }; 1788 1789 static const u8 rtw89_rs_nss_num_ax[] = { 1790 [RTW89_RS_CCK] = 1, 1791 [RTW89_RS_OFDM] = 1, 1792 [RTW89_RS_MCS] = RTW89_NSS_NUM, 1793 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM, 1794 [RTW89_RS_OFFSET] = 1, 1795 }; 1796 1797 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, 1798 struct rtw89_txpwr_byrate *head, 1799 const struct rtw89_rate_desc *desc) 1800 { 1801 switch (desc->rs) { 1802 case RTW89_RS_CCK: 1803 return &head->cck[desc->idx]; 1804 case RTW89_RS_OFDM: 1805 return &head->ofdm[desc->idx]; 1806 case RTW89_RS_MCS: 1807 return &head->mcs[desc->ofdma][desc->nss][desc->idx]; 1808 case RTW89_RS_HEDCM: 1809 return &head->hedcm[desc->ofdma][desc->nss][desc->idx]; 1810 case RTW89_RS_OFFSET: 1811 return &head->offset[desc->idx]; 1812 default: 1813 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs); 1814 return &head->trap; 1815 } 1816 } 1817 1818 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1819 const struct rtw89_txpwr_table *tbl) 1820 { 1821 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1822 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1823 struct rtw89_txpwr_byrate *byr_head; 1824 struct rtw89_rate_desc desc = {}; 1825 s8 *byr; 1826 u32 data; 1827 u8 i; 1828 1829 for (; cfg < end; cfg++) { 1830 byr_head = &rtwdev->byr[cfg->band][0]; 1831 desc.rs = cfg->rs; 1832 desc.nss = cfg->nss; 1833 data = cfg->data; 1834 1835 for (i = 0; i < cfg->len; i++, data >>= 8) { 1836 desc.idx = cfg->shf + i; 1837 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc); 1838 *byr = data & 0xff; 1839 } 1840 } 1841 } 1842 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1843 1844 static s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf) 1845 { 1846 const struct rtw89_chip_info *chip = rtwdev->chip; 1847 1848 return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac); 1849 } 1850 1851 static s8 rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev *rtwdev, s8 dbm) 1852 { 1853 const struct rtw89_chip_info *chip = rtwdev->chip; 1854 1855 return clamp_t(s16, dbm << chip->txpwr_factor_mac, -64, 63); 1856 } 1857 1858 static s8 rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm) 1859 { 1860 const u8 tssi_deviation_point = 0; 1861 const u8 tssi_max_deviation = 2; 1862 1863 if (dbm <= tssi_deviation_point) 1864 dbm -= tssi_max_deviation; 1865 1866 return dbm; 1867 } 1868 1869 static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band) 1870 { 1871 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1872 const struct rtw89_reg_6ghz_tpe *tpe = ®ulatory->reg_6ghz_tpe; 1873 s8 cstr = S8_MAX; 1874 1875 if (band == RTW89_BAND_6G && tpe->valid) 1876 cstr = rtw89_phy_txpwr_dbm_without_tolerance(tpe->constraint); 1877 1878 return rtw89_phy_txpwr_dbm_to_mac(rtwdev, cstr); 1879 } 1880 1881 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, 1882 const struct rtw89_rate_desc *rate_desc) 1883 { 1884 struct rtw89_txpwr_byrate *byr_head; 1885 s8 *byr; 1886 1887 if (rate_desc->rs == RTW89_RS_CCK) 1888 band = RTW89_BAND_2G; 1889 1890 byr_head = &rtwdev->byr[band][bw]; 1891 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc); 1892 1893 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr); 1894 } 1895 1896 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1897 { 1898 switch (channel_6g) { 1899 case 1 ... 29: 1900 return (channel_6g - 1) / 2; 1901 case 33 ... 61: 1902 return (channel_6g - 3) / 2; 1903 case 65 ... 93: 1904 return (channel_6g - 5) / 2; 1905 case 97 ... 125: 1906 return (channel_6g - 7) / 2; 1907 case 129 ... 157: 1908 return (channel_6g - 9) / 2; 1909 case 161 ... 189: 1910 return (channel_6g - 11) / 2; 1911 case 193 ... 221: 1912 return (channel_6g - 13) / 2; 1913 case 225 ... 253: 1914 return (channel_6g - 15) / 2; 1915 default: 1916 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1917 return 0; 1918 } 1919 } 1920 1921 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1922 { 1923 if (band == RTW89_BAND_6G) 1924 return rtw89_channel_6g_to_idx(rtwdev, channel); 1925 1926 switch (channel) { 1927 case 1 ... 14: 1928 return channel - 1; 1929 case 36 ... 64: 1930 return (channel - 36) / 2; 1931 case 100 ... 144: 1932 return ((channel - 100) / 2) + 15; 1933 case 149 ... 177: 1934 return ((channel - 149) / 2) + 38; 1935 default: 1936 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1937 return 0; 1938 } 1939 } 1940 1941 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1942 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1943 { 1944 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1945 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 1946 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 1947 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 1948 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1949 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 1950 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 1951 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1952 u8 regd = rtw89_regd_get(rtwdev, band); 1953 u8 reg6 = regulatory->reg_6ghz_power; 1954 s8 lmt = 0, sar; 1955 s8 cstr; 1956 1957 switch (band) { 1958 case RTW89_BAND_2G: 1959 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1960 if (lmt) 1961 break; 1962 1963 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1964 break; 1965 case RTW89_BAND_5G: 1966 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1967 if (lmt) 1968 break; 1969 1970 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1971 break; 1972 case RTW89_BAND_6G: 1973 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx]; 1974 if (lmt) 1975 break; 1976 1977 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW] 1978 [RTW89_REG_6GHZ_POWER_DFLT] 1979 [ch_idx]; 1980 break; 1981 default: 1982 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1983 return 0; 1984 } 1985 1986 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt); 1987 sar = rtw89_query_sar(rtwdev, freq); 1988 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band); 1989 1990 return min3(lmt, sar, cstr); 1991 } 1992 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1993 1994 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 1995 do { \ 1996 u8 __i; \ 1997 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1998 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1999 band, \ 2000 bw, ntx, \ 2001 rs, __i, \ 2002 (ch)); \ 2003 } while (0) 2004 2005 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev, 2006 struct rtw89_txpwr_limit_ax *lmt, 2007 u8 band, u8 ntx, u8 ch) 2008 { 2009 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 2010 ntx, RTW89_RS_CCK, ch); 2011 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 2012 ntx, RTW89_RS_CCK, ch); 2013 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2014 ntx, RTW89_RS_OFDM, ch); 2015 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2016 RTW89_CHANNEL_WIDTH_20, 2017 ntx, RTW89_RS_MCS, ch); 2018 } 2019 2020 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev, 2021 struct rtw89_txpwr_limit_ax *lmt, 2022 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2023 { 2024 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 2025 ntx, RTW89_RS_CCK, ch - 2); 2026 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 2027 ntx, RTW89_RS_CCK, ch); 2028 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2029 ntx, RTW89_RS_OFDM, pri_ch); 2030 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2031 RTW89_CHANNEL_WIDTH_20, 2032 ntx, RTW89_RS_MCS, ch - 2); 2033 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2034 RTW89_CHANNEL_WIDTH_20, 2035 ntx, RTW89_RS_MCS, ch + 2); 2036 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2037 RTW89_CHANNEL_WIDTH_40, 2038 ntx, RTW89_RS_MCS, ch); 2039 } 2040 2041 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev, 2042 struct rtw89_txpwr_limit_ax *lmt, 2043 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2044 { 2045 s8 val_0p5_n[RTW89_BF_NUM]; 2046 s8 val_0p5_p[RTW89_BF_NUM]; 2047 u8 i; 2048 2049 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2050 ntx, RTW89_RS_OFDM, pri_ch); 2051 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2052 RTW89_CHANNEL_WIDTH_20, 2053 ntx, RTW89_RS_MCS, ch - 6); 2054 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2055 RTW89_CHANNEL_WIDTH_20, 2056 ntx, RTW89_RS_MCS, ch - 2); 2057 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 2058 RTW89_CHANNEL_WIDTH_20, 2059 ntx, RTW89_RS_MCS, ch + 2); 2060 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 2061 RTW89_CHANNEL_WIDTH_20, 2062 ntx, RTW89_RS_MCS, ch + 6); 2063 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2064 RTW89_CHANNEL_WIDTH_40, 2065 ntx, RTW89_RS_MCS, ch - 4); 2066 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 2067 RTW89_CHANNEL_WIDTH_40, 2068 ntx, RTW89_RS_MCS, ch + 4); 2069 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 2070 RTW89_CHANNEL_WIDTH_80, 2071 ntx, RTW89_RS_MCS, ch); 2072 2073 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 2074 ntx, RTW89_RS_MCS, ch - 4); 2075 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 2076 ntx, RTW89_RS_MCS, ch + 4); 2077 2078 for (i = 0; i < RTW89_BF_NUM; i++) 2079 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 2080 } 2081 2082 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev, 2083 struct rtw89_txpwr_limit_ax *lmt, 2084 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2085 { 2086 s8 val_0p5_n[RTW89_BF_NUM]; 2087 s8 val_0p5_p[RTW89_BF_NUM]; 2088 s8 val_2p5_n[RTW89_BF_NUM]; 2089 s8 val_2p5_p[RTW89_BF_NUM]; 2090 u8 i; 2091 2092 /* fill ofdm section */ 2093 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2094 ntx, RTW89_RS_OFDM, pri_ch); 2095 2096 /* fill mcs 20m section */ 2097 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2098 RTW89_CHANNEL_WIDTH_20, 2099 ntx, RTW89_RS_MCS, ch - 14); 2100 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2101 RTW89_CHANNEL_WIDTH_20, 2102 ntx, RTW89_RS_MCS, ch - 10); 2103 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 2104 RTW89_CHANNEL_WIDTH_20, 2105 ntx, RTW89_RS_MCS, ch - 6); 2106 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 2107 RTW89_CHANNEL_WIDTH_20, 2108 ntx, RTW89_RS_MCS, ch - 2); 2109 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 2110 RTW89_CHANNEL_WIDTH_20, 2111 ntx, RTW89_RS_MCS, ch + 2); 2112 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 2113 RTW89_CHANNEL_WIDTH_20, 2114 ntx, RTW89_RS_MCS, ch + 6); 2115 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 2116 RTW89_CHANNEL_WIDTH_20, 2117 ntx, RTW89_RS_MCS, ch + 10); 2118 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 2119 RTW89_CHANNEL_WIDTH_20, 2120 ntx, RTW89_RS_MCS, ch + 14); 2121 2122 /* fill mcs 40m section */ 2123 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2124 RTW89_CHANNEL_WIDTH_40, 2125 ntx, RTW89_RS_MCS, ch - 12); 2126 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 2127 RTW89_CHANNEL_WIDTH_40, 2128 ntx, RTW89_RS_MCS, ch - 4); 2129 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 2130 RTW89_CHANNEL_WIDTH_40, 2131 ntx, RTW89_RS_MCS, ch + 4); 2132 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 2133 RTW89_CHANNEL_WIDTH_40, 2134 ntx, RTW89_RS_MCS, ch + 12); 2135 2136 /* fill mcs 80m section */ 2137 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 2138 RTW89_CHANNEL_WIDTH_80, 2139 ntx, RTW89_RS_MCS, ch - 8); 2140 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 2141 RTW89_CHANNEL_WIDTH_80, 2142 ntx, RTW89_RS_MCS, ch + 8); 2143 2144 /* fill mcs 160m section */ 2145 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 2146 RTW89_CHANNEL_WIDTH_160, 2147 ntx, RTW89_RS_MCS, ch); 2148 2149 /* fill mcs 40m 0p5 section */ 2150 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 2151 ntx, RTW89_RS_MCS, ch - 4); 2152 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 2153 ntx, RTW89_RS_MCS, ch + 4); 2154 2155 for (i = 0; i < RTW89_BF_NUM; i++) 2156 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 2157 2158 /* fill mcs 40m 2p5 section */ 2159 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 2160 ntx, RTW89_RS_MCS, ch - 8); 2161 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 2162 ntx, RTW89_RS_MCS, ch + 8); 2163 2164 for (i = 0; i < RTW89_BF_NUM; i++) 2165 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 2166 } 2167 2168 static 2169 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev, 2170 const struct rtw89_chan *chan, 2171 struct rtw89_txpwr_limit_ax *lmt, 2172 u8 ntx) 2173 { 2174 u8 band = chan->band_type; 2175 u8 pri_ch = chan->primary_channel; 2176 u8 ch = chan->channel; 2177 u8 bw = chan->band_width; 2178 2179 memset(lmt, 0, sizeof(*lmt)); 2180 2181 switch (bw) { 2182 case RTW89_CHANNEL_WIDTH_20: 2183 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch); 2184 break; 2185 case RTW89_CHANNEL_WIDTH_40: 2186 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch, 2187 pri_ch); 2188 break; 2189 case RTW89_CHANNEL_WIDTH_80: 2190 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch, 2191 pri_ch); 2192 break; 2193 case RTW89_CHANNEL_WIDTH_160: 2194 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch, 2195 pri_ch); 2196 break; 2197 } 2198 } 2199 2200 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 2201 u8 ru, u8 ntx, u8 ch) 2202 { 2203 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 2204 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 2205 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 2206 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 2207 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 2208 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 2209 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 2210 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 2211 u8 regd = rtw89_regd_get(rtwdev, band); 2212 u8 reg6 = regulatory->reg_6ghz_power; 2213 s8 lmt_ru = 0, sar; 2214 s8 cstr; 2215 2216 switch (band) { 2217 case RTW89_BAND_2G: 2218 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 2219 if (lmt_ru) 2220 break; 2221 2222 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 2223 break; 2224 case RTW89_BAND_5G: 2225 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 2226 if (lmt_ru) 2227 break; 2228 2229 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 2230 break; 2231 case RTW89_BAND_6G: 2232 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx]; 2233 if (lmt_ru) 2234 break; 2235 2236 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW] 2237 [RTW89_REG_6GHZ_POWER_DFLT] 2238 [ch_idx]; 2239 break; 2240 default: 2241 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 2242 return 0; 2243 } 2244 2245 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 2246 sar = rtw89_query_sar(rtwdev, freq); 2247 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band); 2248 2249 return min3(lmt_ru, sar, cstr); 2250 } 2251 2252 static void 2253 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev, 2254 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2255 u8 band, u8 ntx, u8 ch) 2256 { 2257 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2258 RTW89_RU26, 2259 ntx, ch); 2260 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2261 RTW89_RU52, 2262 ntx, ch); 2263 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2264 RTW89_RU106, 2265 ntx, ch); 2266 } 2267 2268 static void 2269 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev, 2270 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2271 u8 band, u8 ntx, u8 ch) 2272 { 2273 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2274 RTW89_RU26, 2275 ntx, ch - 2); 2276 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2277 RTW89_RU26, 2278 ntx, ch + 2); 2279 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2280 RTW89_RU52, 2281 ntx, ch - 2); 2282 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2283 RTW89_RU52, 2284 ntx, ch + 2); 2285 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2286 RTW89_RU106, 2287 ntx, ch - 2); 2288 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2289 RTW89_RU106, 2290 ntx, ch + 2); 2291 } 2292 2293 static void 2294 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev, 2295 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2296 u8 band, u8 ntx, u8 ch) 2297 { 2298 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2299 RTW89_RU26, 2300 ntx, ch - 6); 2301 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2302 RTW89_RU26, 2303 ntx, ch - 2); 2304 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2305 RTW89_RU26, 2306 ntx, ch + 2); 2307 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2308 RTW89_RU26, 2309 ntx, ch + 6); 2310 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2311 RTW89_RU52, 2312 ntx, ch - 6); 2313 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2314 RTW89_RU52, 2315 ntx, ch - 2); 2316 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2317 RTW89_RU52, 2318 ntx, ch + 2); 2319 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2320 RTW89_RU52, 2321 ntx, ch + 6); 2322 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2323 RTW89_RU106, 2324 ntx, ch - 6); 2325 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2326 RTW89_RU106, 2327 ntx, ch - 2); 2328 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2329 RTW89_RU106, 2330 ntx, ch + 2); 2331 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2332 RTW89_RU106, 2333 ntx, ch + 6); 2334 } 2335 2336 static void 2337 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev, 2338 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2339 u8 band, u8 ntx, u8 ch) 2340 { 2341 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 2342 int i; 2343 2344 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX); 2345 for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) { 2346 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2347 RTW89_RU26, 2348 ntx, 2349 ch + ofst[i]); 2350 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2351 RTW89_RU52, 2352 ntx, 2353 ch + ofst[i]); 2354 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2355 RTW89_RU106, 2356 ntx, 2357 ch + ofst[i]); 2358 } 2359 } 2360 2361 static 2362 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2363 const struct rtw89_chan *chan, 2364 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2365 u8 ntx) 2366 { 2367 u8 band = chan->band_type; 2368 u8 ch = chan->channel; 2369 u8 bw = chan->band_width; 2370 2371 memset(lmt_ru, 0, sizeof(*lmt_ru)); 2372 2373 switch (bw) { 2374 case RTW89_CHANNEL_WIDTH_20: 2375 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx, 2376 ch); 2377 break; 2378 case RTW89_CHANNEL_WIDTH_40: 2379 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx, 2380 ch); 2381 break; 2382 case RTW89_CHANNEL_WIDTH_80: 2383 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx, 2384 ch); 2385 break; 2386 case RTW89_CHANNEL_WIDTH_160: 2387 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx, 2388 ch); 2389 break; 2390 } 2391 } 2392 2393 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev, 2394 const struct rtw89_chan *chan, 2395 enum rtw89_phy_idx phy_idx) 2396 { 2397 u8 max_nss_num = rtwdev->chip->rf_path_num; 2398 static const u8 rs[] = { 2399 RTW89_RS_CCK, 2400 RTW89_RS_OFDM, 2401 RTW89_RS_MCS, 2402 RTW89_RS_HEDCM, 2403 }; 2404 struct rtw89_rate_desc cur = {}; 2405 u8 band = chan->band_type; 2406 u8 ch = chan->channel; 2407 u32 addr, val; 2408 s8 v[4] = {}; 2409 u8 i; 2410 2411 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2412 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 2413 2414 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4); 2415 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4); 2416 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4); 2417 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4); 2418 2419 addr = R_AX_PWR_BY_RATE; 2420 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) { 2421 for (i = 0; i < ARRAY_SIZE(rs); i++) { 2422 if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]]) 2423 continue; 2424 2425 cur.rs = rs[i]; 2426 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]]; 2427 cur.idx++) { 2428 v[cur.idx % 4] = 2429 rtw89_phy_read_txpwr_byrate(rtwdev, 2430 band, 0, 2431 &cur); 2432 2433 if ((cur.idx + 1) % 4) 2434 continue; 2435 2436 val = FIELD_PREP(GENMASK(7, 0), v[0]) | 2437 FIELD_PREP(GENMASK(15, 8), v[1]) | 2438 FIELD_PREP(GENMASK(23, 16), v[2]) | 2439 FIELD_PREP(GENMASK(31, 24), v[3]); 2440 2441 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 2442 val); 2443 addr += 4; 2444 } 2445 } 2446 } 2447 } 2448 2449 static 2450 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev, 2451 const struct rtw89_chan *chan, 2452 enum rtw89_phy_idx phy_idx) 2453 { 2454 struct rtw89_rate_desc desc = { 2455 .nss = RTW89_NSS_1, 2456 .rs = RTW89_RS_OFFSET, 2457 }; 2458 u8 band = chan->band_type; 2459 s8 v[RTW89_RATE_OFFSET_NUM_AX] = {}; 2460 u32 val; 2461 2462 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 2463 2464 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_AX; desc.idx++) 2465 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc); 2466 2467 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM_AX != 5); 2468 val = FIELD_PREP(GENMASK(3, 0), v[0]) | 2469 FIELD_PREP(GENMASK(7, 4), v[1]) | 2470 FIELD_PREP(GENMASK(11, 8), v[2]) | 2471 FIELD_PREP(GENMASK(15, 12), v[3]) | 2472 FIELD_PREP(GENMASK(19, 16), v[4]); 2473 2474 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 2475 GENMASK(19, 0), val); 2476 } 2477 2478 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev, 2479 const struct rtw89_chan *chan, 2480 enum rtw89_phy_idx phy_idx) 2481 { 2482 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2483 struct rtw89_txpwr_limit_ax lmt; 2484 u8 ch = chan->channel; 2485 u8 bw = chan->band_width; 2486 const s8 *ptr; 2487 u32 addr, val; 2488 u8 i, j; 2489 2490 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2491 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 2492 2493 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ax) != 2494 RTW89_TXPWR_LMT_PAGE_SIZE_AX); 2495 2496 addr = R_AX_PWR_LMT; 2497 for (i = 0; i < max_ntx_num; i++) { 2498 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i); 2499 2500 ptr = (s8 *)&lmt; 2501 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_AX; 2502 j += 4, addr += 4, ptr += 4) { 2503 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2504 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2505 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2506 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2507 2508 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2509 } 2510 } 2511 } 2512 2513 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2514 const struct rtw89_chan *chan, 2515 enum rtw89_phy_idx phy_idx) 2516 { 2517 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2518 struct rtw89_txpwr_limit_ru_ax lmt_ru; 2519 u8 ch = chan->channel; 2520 u8 bw = chan->band_width; 2521 const s8 *ptr; 2522 u32 addr, val; 2523 u8 i, j; 2524 2525 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2526 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 2527 2528 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) != 2529 RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX); 2530 2531 addr = R_AX_PWR_RU_LMT; 2532 for (i = 0; i < max_ntx_num; i++) { 2533 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i); 2534 2535 ptr = (s8 *)&lmt_ru; 2536 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX; 2537 j += 4, addr += 4, ptr += 4) { 2538 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2539 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2540 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2541 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2542 2543 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2544 } 2545 } 2546 } 2547 2548 struct rtw89_phy_iter_ra_data { 2549 struct rtw89_dev *rtwdev; 2550 struct sk_buff *c2h; 2551 }; 2552 2553 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 2554 { 2555 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 2556 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2557 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2558 const struct rtw89_c2h_ra_rpt *c2h = 2559 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data; 2560 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 2561 const struct rtw89_chip_info *chip = rtwdev->chip; 2562 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE; 2563 u8 mode, rate, bw, giltf, mac_id; 2564 u16 legacy_bitrate; 2565 bool valid; 2566 u8 mcs = 0; 2567 u8 t; 2568 2569 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID); 2570 if (mac_id != rtwsta->mac_id) 2571 return; 2572 2573 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS); 2574 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW); 2575 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF); 2576 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL); 2577 2578 if (format_v1) { 2579 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7); 2580 rate |= u8_encode_bits(t, BIT(7)); 2581 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2); 2582 bw |= u8_encode_bits(t, BIT(2)); 2583 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2); 2584 mode |= u8_encode_bits(t, BIT(2)); 2585 } 2586 2587 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2588 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2589 if (!valid) 2590 return; 2591 } 2592 2593 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2594 2595 switch (mode) { 2596 case RTW89_RA_RPT_MODE_LEGACY: 2597 ra_report->txrate.legacy = legacy_bitrate; 2598 break; 2599 case RTW89_RA_RPT_MODE_HT: 2600 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2601 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2602 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2603 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2604 else 2605 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2606 ra_report->txrate.mcs = rate; 2607 if (giltf) 2608 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2609 mcs = ra_report->txrate.mcs & 0x07; 2610 break; 2611 case RTW89_RA_RPT_MODE_VHT: 2612 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2613 ra_report->txrate.mcs = format_v1 ? 2614 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2615 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2616 ra_report->txrate.nss = format_v1 ? 2617 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2618 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2619 if (giltf) 2620 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2621 mcs = ra_report->txrate.mcs; 2622 break; 2623 case RTW89_RA_RPT_MODE_HE: 2624 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2625 ra_report->txrate.mcs = format_v1 ? 2626 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2627 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2628 ra_report->txrate.nss = format_v1 ? 2629 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2630 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2631 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2632 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2633 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2634 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2635 else 2636 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2637 mcs = ra_report->txrate.mcs; 2638 break; 2639 case RTW89_RA_RPT_MODE_EHT: 2640 ra_report->txrate.flags |= RATE_INFO_FLAGS_EHT_MCS; 2641 ra_report->txrate.mcs = u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1); 2642 ra_report->txrate.nss = u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1; 2643 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2644 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_0_8; 2645 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2646 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_1_6; 2647 else 2648 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_3_2; 2649 mcs = ra_report->txrate.mcs; 2650 break; 2651 } 2652 2653 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2654 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2655 ra_report->hw_rate = format_v1 ? 2656 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) | 2657 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) : 2658 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) | 2659 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL); 2660 ra_report->might_fallback_legacy = mcs <= 2; 2661 sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2662 rtwsta->max_agg_wait = sta->deflink.agg.max_rc_amsdu_len / 1500 - 1; 2663 } 2664 2665 static void 2666 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2667 { 2668 struct rtw89_phy_iter_ra_data ra_data; 2669 2670 ra_data.rtwdev = rtwdev; 2671 ra_data.c2h = c2h; 2672 ieee80211_iterate_stations_atomic(rtwdev->hw, 2673 rtw89_phy_c2h_ra_rpt_iter, 2674 &ra_data); 2675 } 2676 2677 static 2678 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2679 struct sk_buff *c2h, u32 len) = { 2680 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2681 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2682 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2683 }; 2684 2685 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, 2686 enum rtw89_phy_c2h_rfk_log_func func, 2687 void *content, u16 len) 2688 { 2689 struct rtw89_c2h_rf_txgapk_rpt_log *txgapk; 2690 struct rtw89_c2h_rf_rxdck_rpt_log *rxdck; 2691 struct rtw89_c2h_rf_dack_rpt_log *dack; 2692 struct rtw89_c2h_rf_dpk_rpt_log *dpk; 2693 2694 switch (func) { 2695 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: 2696 if (len != sizeof(*dpk)) 2697 goto out; 2698 2699 dpk = content; 2700 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2701 "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n", 2702 dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok); 2703 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2704 "DPK txagc:%2ph ther:%2ph gs:%2ph dc_i:%4ph dc_q:%4ph\n", 2705 dpk->txagc, dpk->ther, dpk->gs, dpk->dc_i, dpk->dc_q); 2706 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2707 "DPK corr_v:%2ph corr_i:%2ph to:%2ph ov:%2ph\n", 2708 dpk->corr_val, dpk->corr_idx, dpk->is_timeout, dpk->rxbb_ov); 2709 return; 2710 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK: 2711 if (len != sizeof(*dack)) 2712 goto out; 2713 2714 dack = content; 2715 2716 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ver=0x%x 0x%x\n", 2717 dack->fwdack_ver, dack->fwdack_rpt_ver); 2718 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK ic = [0x%x, 0x%x]\n", 2719 dack->cdack_d[0][0][0], dack->cdack_d[0][0][1]); 2720 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK qc = [0x%x, 0x%x]\n", 2721 dack->cdack_d[0][1][0], dack->cdack_d[0][1][1]); 2722 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK ic = [0x%x, 0x%x]\n", 2723 dack->cdack_d[1][0][0], dack->cdack_d[1][0][1]); 2724 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK qc = [0x%x, 0x%x]\n", 2725 dack->cdack_d[1][1][0], dack->cdack_d[1][1][1]); 2726 2727 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = [0x%x, 0x%x]\n", 2728 dack->addck2_d[0][0][0], dack->addck2_d[0][0][1]); 2729 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK qc = [0x%x, 0x%x]\n", 2730 dack->addck2_d[0][1][0], dack->addck2_d[0][1][1]); 2731 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK ic = [0x%x, 0x%x]\n", 2732 dack->addck2_d[1][0][0], dack->addck2_d[1][0][1]); 2733 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK qc = [0x%x, 0x%x]\n", 2734 dack->addck2_d[1][1][0], dack->addck2_d[1][1][1]); 2735 2736 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_GAINK ic = 0x%x, qc = 0x%x\n", 2737 dack->adgaink_d[0][0], dack->adgaink_d[0][1]); 2738 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_GAINK ic = 0x%x, qc = 0x%x\n", 2739 dack->adgaink_d[1][0], dack->adgaink_d[1][1]); 2740 2741 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n", 2742 dack->dadck_d[0][0], dack->dadck_d[0][1]); 2743 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n", 2744 dack->dadck_d[1][0], dack->dadck_d[1][1]); 2745 2746 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask iqc = 0x%x\n", 2747 dack->biask_d[0][0]); 2748 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 biask iqc = 0x%x\n", 2749 dack->biask_d[1][0]); 2750 2751 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic: %*ph\n", 2752 (int)sizeof(dack->msbk_d[0][0]), dack->msbk_d[0][0]); 2753 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc: %*ph\n", 2754 (int)sizeof(dack->msbk_d[0][1]), dack->msbk_d[0][1]); 2755 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic: %*ph\n", 2756 (int)sizeof(dack->msbk_d[1][0]), dack->msbk_d[1][0]); 2757 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc: %*ph\n", 2758 (int)sizeof(dack->msbk_d[1][1]), dack->msbk_d[1][1]); 2759 return; 2760 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: 2761 if (len != sizeof(*rxdck)) 2762 goto out; 2763 2764 rxdck = content; 2765 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2766 "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n", 2767 rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch, 2768 rxdck->timeout); 2769 return; 2770 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: 2771 if (len != sizeof(*txgapk)) 2772 goto out; 2773 2774 txgapk = content; 2775 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2776 "[TXGAPK]rpt r0x8010[0]=0x%x, r0x8010[1]=0x%x\n", 2777 le32_to_cpu(txgapk->r0x8010[0]), 2778 le32_to_cpu(txgapk->r0x8010[1])); 2779 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_id = %d\n", 2780 txgapk->chk_id); 2781 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_cnt = %d\n", 2782 le32_to_cpu(txgapk->chk_cnt)); 2783 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n", 2784 txgapk->ver); 2785 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n", 2786 txgapk->rsv1); 2787 2788 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n", 2789 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]); 2790 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[0] = %*ph\n", 2791 (int)sizeof(txgapk->power_d[0]), txgapk->power_d[0]); 2792 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[1] = %*ph\n", 2793 (int)sizeof(txgapk->track_d[1]), txgapk->track_d[1]); 2794 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n", 2795 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]); 2796 return; 2797 default: 2798 break; 2799 } 2800 2801 out: 2802 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2803 "unexpected RFK func %d report log with length %d\n", func, len); 2804 } 2805 2806 static bool rtw89_phy_c2h_rfk_run_log(struct rtw89_dev *rtwdev, 2807 enum rtw89_phy_c2h_rfk_log_func func, 2808 void *content, u16 len) 2809 { 2810 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 2811 const struct rtw89_c2h_rf_run_log *log = content; 2812 const struct rtw89_fw_element_hdr *elm; 2813 u32 fmt_idx; 2814 u16 offset; 2815 2816 if (sizeof(*log) != len) 2817 return false; 2818 2819 if (!elm_info->rfk_log_fmt) 2820 return false; 2821 2822 elm = elm_info->rfk_log_fmt->elm[func]; 2823 fmt_idx = le32_to_cpu(log->fmt_idx); 2824 if (!elm || fmt_idx >= elm->u.rfk_log_fmt.nr) 2825 return false; 2826 2827 offset = le16_to_cpu(elm->u.rfk_log_fmt.offset[fmt_idx]); 2828 if (offset == 0) 2829 return false; 2830 2831 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset], 2832 le32_to_cpu(log->arg[0]), le32_to_cpu(log->arg[1]), 2833 le32_to_cpu(log->arg[2]), le32_to_cpu(log->arg[3])); 2834 2835 return true; 2836 } 2837 2838 static void rtw89_phy_c2h_rfk_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 2839 u32 len, enum rtw89_phy_c2h_rfk_log_func func, 2840 const char *rfk_name) 2841 { 2842 struct rtw89_c2h_hdr *c2h_hdr = (struct rtw89_c2h_hdr *)c2h->data; 2843 struct rtw89_c2h_rf_log_hdr *log_hdr; 2844 void *log_ptr = c2h_hdr; 2845 u16 content_len; 2846 u16 chunk_len; 2847 bool handled; 2848 2849 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK)) 2850 return; 2851 2852 log_ptr += sizeof(*c2h_hdr); 2853 len -= sizeof(*c2h_hdr); 2854 2855 while (len > sizeof(*log_hdr)) { 2856 log_hdr = log_ptr; 2857 content_len = le16_to_cpu(log_hdr->len); 2858 chunk_len = content_len + sizeof(*log_hdr); 2859 2860 if (chunk_len > len) 2861 break; 2862 2863 switch (log_hdr->type) { 2864 case RTW89_RF_RUN_LOG: 2865 handled = rtw89_phy_c2h_rfk_run_log(rtwdev, func, 2866 log_hdr->content, content_len); 2867 if (handled) 2868 break; 2869 2870 rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s run: %*ph\n", 2871 rfk_name, content_len, log_hdr->content); 2872 break; 2873 case RTW89_RF_RPT_LOG: 2874 rtw89_phy_c2h_rfk_rpt_log(rtwdev, func, 2875 log_hdr->content, content_len); 2876 break; 2877 default: 2878 return; 2879 } 2880 2881 log_ptr += chunk_len; 2882 len -= chunk_len; 2883 } 2884 } 2885 2886 static void 2887 rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2888 { 2889 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2890 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK, "IQK"); 2891 } 2892 2893 static void 2894 rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2895 { 2896 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2897 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK, "DPK"); 2898 } 2899 2900 static void 2901 rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2902 { 2903 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2904 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK, "DACK"); 2905 } 2906 2907 static void 2908 rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2909 { 2910 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2911 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK, "RX_DCK"); 2912 } 2913 2914 static void 2915 rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2916 { 2917 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2918 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI, "TSSI"); 2919 } 2920 2921 static void 2922 rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2923 { 2924 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2925 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK, "TXGAPK"); 2926 } 2927 2928 static 2929 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev, 2930 struct sk_buff *c2h, u32 len) = { 2931 [RTW89_PHY_C2H_RFK_LOG_FUNC_IQK] = rtw89_phy_c2h_rfk_log_iqk, 2932 [RTW89_PHY_C2H_RFK_LOG_FUNC_DPK] = rtw89_phy_c2h_rfk_log_dpk, 2933 [RTW89_PHY_C2H_RFK_LOG_FUNC_DACK] = rtw89_phy_c2h_rfk_log_dack, 2934 [RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK] = rtw89_phy_c2h_rfk_log_rxdck, 2935 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi, 2936 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk, 2937 }; 2938 2939 static 2940 void rtw89_phy_rfk_report_prep(struct rtw89_dev *rtwdev) 2941 { 2942 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 2943 2944 wait->state = RTW89_RFK_STATE_START; 2945 wait->start_time = ktime_get(); 2946 reinit_completion(&wait->completion); 2947 } 2948 2949 static 2950 int rtw89_phy_rfk_report_wait(struct rtw89_dev *rtwdev, const char *rfk_name, 2951 unsigned int ms) 2952 { 2953 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 2954 unsigned long time_left; 2955 2956 /* Since we can't receive C2H event during SER, use a fixed delay. */ 2957 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) { 2958 fsleep(1000 * ms / 2); 2959 goto out; 2960 } 2961 2962 time_left = wait_for_completion_timeout(&wait->completion, 2963 msecs_to_jiffies(ms)); 2964 if (time_left == 0) { 2965 rtw89_warn(rtwdev, "failed to wait RF %s\n", rfk_name); 2966 return -ETIMEDOUT; 2967 } else if (wait->state != RTW89_RFK_STATE_OK) { 2968 rtw89_warn(rtwdev, "failed to do RF %s result from state %d\n", 2969 rfk_name, wait->state); 2970 return -EFAULT; 2971 } 2972 2973 out: 2974 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %lld ms to complete\n", 2975 rfk_name, ktime_ms_delta(ktime_get(), wait->start_time)); 2976 2977 return 0; 2978 } 2979 2980 static void 2981 rtw89_phy_c2h_rfk_report_state(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2982 { 2983 const struct rtw89_c2h_rfk_report *report = 2984 (const struct rtw89_c2h_rfk_report *)c2h->data; 2985 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 2986 2987 wait->state = report->state; 2988 wait->version = report->version; 2989 2990 complete(&wait->completion); 2991 2992 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2993 "RFK report state %d with version %d (%*ph)\n", 2994 wait->state, wait->version, 2995 (int)(len - sizeof(report->hdr)), &report->state); 2996 } 2997 2998 static 2999 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev, 3000 struct sk_buff *c2h, u32 len) = { 3001 [RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE] = rtw89_phy_c2h_rfk_report_state, 3002 }; 3003 3004 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 3005 { 3006 switch (class) { 3007 case RTW89_PHY_C2H_RFK_LOG: 3008 switch (func) { 3009 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK: 3010 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: 3011 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK: 3012 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: 3013 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI: 3014 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: 3015 return true; 3016 default: 3017 return false; 3018 } 3019 case RTW89_PHY_C2H_RFK_REPORT: 3020 switch (func) { 3021 case RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE: 3022 return true; 3023 default: 3024 return false; 3025 } 3026 default: 3027 return false; 3028 } 3029 } 3030 3031 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3032 u32 len, u8 class, u8 func) 3033 { 3034 void (*handler)(struct rtw89_dev *rtwdev, 3035 struct sk_buff *c2h, u32 len) = NULL; 3036 3037 switch (class) { 3038 case RTW89_PHY_C2H_CLASS_RA: 3039 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 3040 handler = rtw89_phy_c2h_ra_handler[func]; 3041 break; 3042 case RTW89_PHY_C2H_RFK_LOG: 3043 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_log_handler)) 3044 handler = rtw89_phy_c2h_rfk_log_handler[func]; 3045 break; 3046 case RTW89_PHY_C2H_RFK_REPORT: 3047 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_report_handler)) 3048 handler = rtw89_phy_c2h_rfk_report_handler[func]; 3049 break; 3050 case RTW89_PHY_C2H_CLASS_DM: 3051 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY) 3052 return; 3053 fallthrough; 3054 default: 3055 rtw89_info(rtwdev, "c2h class %d not support\n", class); 3056 return; 3057 } 3058 if (!handler) { 3059 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 3060 func); 3061 return; 3062 } 3063 handler(rtwdev, skb, len); 3064 } 3065 3066 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev, 3067 enum rtw89_phy_idx phy_idx, 3068 unsigned int ms) 3069 { 3070 int ret; 3071 3072 rtw89_phy_rfk_report_prep(rtwdev); 3073 3074 ret = rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx); 3075 if (ret) 3076 return ret; 3077 3078 return rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms); 3079 } 3080 EXPORT_SYMBOL(rtw89_phy_rfk_pre_ntfy_and_wait); 3081 3082 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev, 3083 enum rtw89_phy_idx phy_idx, 3084 enum rtw89_tssi_mode tssi_mode, 3085 unsigned int ms) 3086 { 3087 int ret; 3088 3089 rtw89_phy_rfk_report_prep(rtwdev); 3090 3091 ret = rtw89_fw_h2c_rf_tssi(rtwdev, phy_idx, tssi_mode); 3092 if (ret) 3093 return ret; 3094 3095 return rtw89_phy_rfk_report_wait(rtwdev, "TSSI", ms); 3096 } 3097 EXPORT_SYMBOL(rtw89_phy_rfk_tssi_and_wait); 3098 3099 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev, 3100 enum rtw89_phy_idx phy_idx, 3101 unsigned int ms) 3102 { 3103 int ret; 3104 3105 rtw89_phy_rfk_report_prep(rtwdev); 3106 3107 ret = rtw89_fw_h2c_rf_iqk(rtwdev, phy_idx); 3108 if (ret) 3109 return ret; 3110 3111 return rtw89_phy_rfk_report_wait(rtwdev, "IQK", ms); 3112 } 3113 EXPORT_SYMBOL(rtw89_phy_rfk_iqk_and_wait); 3114 3115 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev, 3116 enum rtw89_phy_idx phy_idx, 3117 unsigned int ms) 3118 { 3119 int ret; 3120 3121 rtw89_phy_rfk_report_prep(rtwdev); 3122 3123 ret = rtw89_fw_h2c_rf_dpk(rtwdev, phy_idx); 3124 if (ret) 3125 return ret; 3126 3127 return rtw89_phy_rfk_report_wait(rtwdev, "DPK", ms); 3128 } 3129 EXPORT_SYMBOL(rtw89_phy_rfk_dpk_and_wait); 3130 3131 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev, 3132 enum rtw89_phy_idx phy_idx, 3133 unsigned int ms) 3134 { 3135 int ret; 3136 3137 rtw89_phy_rfk_report_prep(rtwdev); 3138 3139 ret = rtw89_fw_h2c_rf_txgapk(rtwdev, phy_idx); 3140 if (ret) 3141 return ret; 3142 3143 return rtw89_phy_rfk_report_wait(rtwdev, "TXGAPK", ms); 3144 } 3145 EXPORT_SYMBOL(rtw89_phy_rfk_txgapk_and_wait); 3146 3147 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev, 3148 enum rtw89_phy_idx phy_idx, 3149 unsigned int ms) 3150 { 3151 int ret; 3152 3153 rtw89_phy_rfk_report_prep(rtwdev); 3154 3155 ret = rtw89_fw_h2c_rf_dack(rtwdev, phy_idx); 3156 if (ret) 3157 return ret; 3158 3159 return rtw89_phy_rfk_report_wait(rtwdev, "DACK", ms); 3160 } 3161 EXPORT_SYMBOL(rtw89_phy_rfk_dack_and_wait); 3162 3163 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev, 3164 enum rtw89_phy_idx phy_idx, 3165 unsigned int ms) 3166 { 3167 int ret; 3168 3169 rtw89_phy_rfk_report_prep(rtwdev); 3170 3171 ret = rtw89_fw_h2c_rf_rxdck(rtwdev, phy_idx); 3172 if (ret) 3173 return ret; 3174 3175 return rtw89_phy_rfk_report_wait(rtwdev, "RX_DCK", ms); 3176 } 3177 EXPORT_SYMBOL(rtw89_phy_rfk_rxdck_and_wait); 3178 3179 static u32 phy_tssi_get_cck_group(u8 ch) 3180 { 3181 switch (ch) { 3182 case 1 ... 2: 3183 return 0; 3184 case 3 ... 5: 3185 return 1; 3186 case 6 ... 8: 3187 return 2; 3188 case 9 ... 11: 3189 return 3; 3190 case 12 ... 13: 3191 return 4; 3192 case 14: 3193 return 5; 3194 } 3195 3196 return 0; 3197 } 3198 3199 #define PHY_TSSI_EXTRA_GROUP_BIT BIT(31) 3200 #define PHY_TSSI_EXTRA_GROUP(idx) (PHY_TSSI_EXTRA_GROUP_BIT | (idx)) 3201 #define PHY_IS_TSSI_EXTRA_GROUP(group) ((group) & PHY_TSSI_EXTRA_GROUP_BIT) 3202 #define PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) \ 3203 ((group) & ~PHY_TSSI_EXTRA_GROUP_BIT) 3204 #define PHY_TSSI_EXTRA_GET_GROUP_IDX2(group) \ 3205 (PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) + 1) 3206 3207 static u32 phy_tssi_get_ofdm_group(u8 ch) 3208 { 3209 switch (ch) { 3210 case 1 ... 2: 3211 return 0; 3212 case 3 ... 5: 3213 return 1; 3214 case 6 ... 8: 3215 return 2; 3216 case 9 ... 11: 3217 return 3; 3218 case 12 ... 14: 3219 return 4; 3220 case 36 ... 40: 3221 return 5; 3222 case 41 ... 43: 3223 return PHY_TSSI_EXTRA_GROUP(5); 3224 case 44 ... 48: 3225 return 6; 3226 case 49 ... 51: 3227 return PHY_TSSI_EXTRA_GROUP(6); 3228 case 52 ... 56: 3229 return 7; 3230 case 57 ... 59: 3231 return PHY_TSSI_EXTRA_GROUP(7); 3232 case 60 ... 64: 3233 return 8; 3234 case 100 ... 104: 3235 return 9; 3236 case 105 ... 107: 3237 return PHY_TSSI_EXTRA_GROUP(9); 3238 case 108 ... 112: 3239 return 10; 3240 case 113 ... 115: 3241 return PHY_TSSI_EXTRA_GROUP(10); 3242 case 116 ... 120: 3243 return 11; 3244 case 121 ... 123: 3245 return PHY_TSSI_EXTRA_GROUP(11); 3246 case 124 ... 128: 3247 return 12; 3248 case 129 ... 131: 3249 return PHY_TSSI_EXTRA_GROUP(12); 3250 case 132 ... 136: 3251 return 13; 3252 case 137 ... 139: 3253 return PHY_TSSI_EXTRA_GROUP(13); 3254 case 140 ... 144: 3255 return 14; 3256 case 149 ... 153: 3257 return 15; 3258 case 154 ... 156: 3259 return PHY_TSSI_EXTRA_GROUP(15); 3260 case 157 ... 161: 3261 return 16; 3262 case 162 ... 164: 3263 return PHY_TSSI_EXTRA_GROUP(16); 3264 case 165 ... 169: 3265 return 17; 3266 case 170 ... 172: 3267 return PHY_TSSI_EXTRA_GROUP(17); 3268 case 173 ... 177: 3269 return 18; 3270 } 3271 3272 return 0; 3273 } 3274 3275 static u32 phy_tssi_get_6g_ofdm_group(u8 ch) 3276 { 3277 switch (ch) { 3278 case 1 ... 5: 3279 return 0; 3280 case 6 ... 8: 3281 return PHY_TSSI_EXTRA_GROUP(0); 3282 case 9 ... 13: 3283 return 1; 3284 case 14 ... 16: 3285 return PHY_TSSI_EXTRA_GROUP(1); 3286 case 17 ... 21: 3287 return 2; 3288 case 22 ... 24: 3289 return PHY_TSSI_EXTRA_GROUP(2); 3290 case 25 ... 29: 3291 return 3; 3292 case 33 ... 37: 3293 return 4; 3294 case 38 ... 40: 3295 return PHY_TSSI_EXTRA_GROUP(4); 3296 case 41 ... 45: 3297 return 5; 3298 case 46 ... 48: 3299 return PHY_TSSI_EXTRA_GROUP(5); 3300 case 49 ... 53: 3301 return 6; 3302 case 54 ... 56: 3303 return PHY_TSSI_EXTRA_GROUP(6); 3304 case 57 ... 61: 3305 return 7; 3306 case 65 ... 69: 3307 return 8; 3308 case 70 ... 72: 3309 return PHY_TSSI_EXTRA_GROUP(8); 3310 case 73 ... 77: 3311 return 9; 3312 case 78 ... 80: 3313 return PHY_TSSI_EXTRA_GROUP(9); 3314 case 81 ... 85: 3315 return 10; 3316 case 86 ... 88: 3317 return PHY_TSSI_EXTRA_GROUP(10); 3318 case 89 ... 93: 3319 return 11; 3320 case 97 ... 101: 3321 return 12; 3322 case 102 ... 104: 3323 return PHY_TSSI_EXTRA_GROUP(12); 3324 case 105 ... 109: 3325 return 13; 3326 case 110 ... 112: 3327 return PHY_TSSI_EXTRA_GROUP(13); 3328 case 113 ... 117: 3329 return 14; 3330 case 118 ... 120: 3331 return PHY_TSSI_EXTRA_GROUP(14); 3332 case 121 ... 125: 3333 return 15; 3334 case 129 ... 133: 3335 return 16; 3336 case 134 ... 136: 3337 return PHY_TSSI_EXTRA_GROUP(16); 3338 case 137 ... 141: 3339 return 17; 3340 case 142 ... 144: 3341 return PHY_TSSI_EXTRA_GROUP(17); 3342 case 145 ... 149: 3343 return 18; 3344 case 150 ... 152: 3345 return PHY_TSSI_EXTRA_GROUP(18); 3346 case 153 ... 157: 3347 return 19; 3348 case 161 ... 165: 3349 return 20; 3350 case 166 ... 168: 3351 return PHY_TSSI_EXTRA_GROUP(20); 3352 case 169 ... 173: 3353 return 21; 3354 case 174 ... 176: 3355 return PHY_TSSI_EXTRA_GROUP(21); 3356 case 177 ... 181: 3357 return 22; 3358 case 182 ... 184: 3359 return PHY_TSSI_EXTRA_GROUP(22); 3360 case 185 ... 189: 3361 return 23; 3362 case 193 ... 197: 3363 return 24; 3364 case 198 ... 200: 3365 return PHY_TSSI_EXTRA_GROUP(24); 3366 case 201 ... 205: 3367 return 25; 3368 case 206 ... 208: 3369 return PHY_TSSI_EXTRA_GROUP(25); 3370 case 209 ... 213: 3371 return 26; 3372 case 214 ... 216: 3373 return PHY_TSSI_EXTRA_GROUP(26); 3374 case 217 ... 221: 3375 return 27; 3376 case 225 ... 229: 3377 return 28; 3378 case 230 ... 232: 3379 return PHY_TSSI_EXTRA_GROUP(28); 3380 case 233 ... 237: 3381 return 29; 3382 case 238 ... 240: 3383 return PHY_TSSI_EXTRA_GROUP(29); 3384 case 241 ... 245: 3385 return 30; 3386 case 246 ... 248: 3387 return PHY_TSSI_EXTRA_GROUP(30); 3388 case 249 ... 253: 3389 return 31; 3390 } 3391 3392 return 0; 3393 } 3394 3395 static u32 phy_tssi_get_trim_group(u8 ch) 3396 { 3397 switch (ch) { 3398 case 1 ... 8: 3399 return 0; 3400 case 9 ... 14: 3401 return 1; 3402 case 36 ... 48: 3403 return 2; 3404 case 49 ... 51: 3405 return PHY_TSSI_EXTRA_GROUP(2); 3406 case 52 ... 64: 3407 return 3; 3408 case 100 ... 112: 3409 return 4; 3410 case 113 ... 115: 3411 return PHY_TSSI_EXTRA_GROUP(4); 3412 case 116 ... 128: 3413 return 5; 3414 case 132 ... 144: 3415 return 6; 3416 case 149 ... 177: 3417 return 7; 3418 } 3419 3420 return 0; 3421 } 3422 3423 static u32 phy_tssi_get_6g_trim_group(u8 ch) 3424 { 3425 switch (ch) { 3426 case 1 ... 13: 3427 return 0; 3428 case 14 ... 16: 3429 return PHY_TSSI_EXTRA_GROUP(0); 3430 case 17 ... 29: 3431 return 1; 3432 case 33 ... 45: 3433 return 2; 3434 case 46 ... 48: 3435 return PHY_TSSI_EXTRA_GROUP(2); 3436 case 49 ... 61: 3437 return 3; 3438 case 65 ... 77: 3439 return 4; 3440 case 78 ... 80: 3441 return PHY_TSSI_EXTRA_GROUP(4); 3442 case 81 ... 93: 3443 return 5; 3444 case 97 ... 109: 3445 return 6; 3446 case 110 ... 112: 3447 return PHY_TSSI_EXTRA_GROUP(6); 3448 case 113 ... 125: 3449 return 7; 3450 case 129 ... 141: 3451 return 8; 3452 case 142 ... 144: 3453 return PHY_TSSI_EXTRA_GROUP(8); 3454 case 145 ... 157: 3455 return 9; 3456 case 161 ... 173: 3457 return 10; 3458 case 174 ... 176: 3459 return PHY_TSSI_EXTRA_GROUP(10); 3460 case 177 ... 189: 3461 return 11; 3462 case 193 ... 205: 3463 return 12; 3464 case 206 ... 208: 3465 return PHY_TSSI_EXTRA_GROUP(12); 3466 case 209 ... 221: 3467 return 13; 3468 case 225 ... 237: 3469 return 14; 3470 case 238 ... 240: 3471 return PHY_TSSI_EXTRA_GROUP(14); 3472 case 241 ... 253: 3473 return 15; 3474 } 3475 3476 return 0; 3477 } 3478 3479 static s8 phy_tssi_get_ofdm_de(struct rtw89_dev *rtwdev, 3480 enum rtw89_phy_idx phy, 3481 const struct rtw89_chan *chan, 3482 enum rtw89_rf_path path) 3483 { 3484 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3485 enum rtw89_band band = chan->band_type; 3486 u8 ch = chan->channel; 3487 u32 gidx_1st; 3488 u32 gidx_2nd; 3489 s8 de_1st; 3490 s8 de_2nd; 3491 u32 gidx; 3492 s8 val; 3493 3494 if (band == RTW89_BAND_6G) 3495 goto calc_6g; 3496 3497 gidx = phy_tssi_get_ofdm_group(ch); 3498 3499 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3500 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", 3501 path, gidx); 3502 3503 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) { 3504 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx); 3505 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx); 3506 de_1st = tssi_info->tssi_mcs[path][gidx_1st]; 3507 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd]; 3508 val = (de_1st + de_2nd) / 2; 3509 3510 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3511 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", 3512 path, val, de_1st, de_2nd); 3513 } else { 3514 val = tssi_info->tssi_mcs[path][gidx]; 3515 3516 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3517 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); 3518 } 3519 3520 return val; 3521 3522 calc_6g: 3523 gidx = phy_tssi_get_6g_ofdm_group(ch); 3524 3525 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3526 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", 3527 path, gidx); 3528 3529 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) { 3530 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx); 3531 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx); 3532 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st]; 3533 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd]; 3534 val = (de_1st + de_2nd) / 2; 3535 3536 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3537 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", 3538 path, val, de_1st, de_2nd); 3539 } else { 3540 val = tssi_info->tssi_6g_mcs[path][gidx]; 3541 3542 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3543 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); 3544 } 3545 3546 return val; 3547 } 3548 3549 static s8 phy_tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev, 3550 enum rtw89_phy_idx phy, 3551 const struct rtw89_chan *chan, 3552 enum rtw89_rf_path path) 3553 { 3554 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3555 enum rtw89_band band = chan->band_type; 3556 u8 ch = chan->channel; 3557 u32 tgidx_1st; 3558 u32 tgidx_2nd; 3559 s8 tde_1st; 3560 s8 tde_2nd; 3561 u32 tgidx; 3562 s8 val; 3563 3564 if (band == RTW89_BAND_6G) 3565 goto calc_6g; 3566 3567 tgidx = phy_tssi_get_trim_group(ch); 3568 3569 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3570 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", 3571 path, tgidx); 3572 3573 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) { 3574 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx); 3575 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx); 3576 tde_1st = tssi_info->tssi_trim[path][tgidx_1st]; 3577 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd]; 3578 val = (tde_1st + tde_2nd) / 2; 3579 3580 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3581 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", 3582 path, val, tde_1st, tde_2nd); 3583 } else { 3584 val = tssi_info->tssi_trim[path][tgidx]; 3585 3586 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3587 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", 3588 path, val); 3589 } 3590 3591 return val; 3592 3593 calc_6g: 3594 tgidx = phy_tssi_get_6g_trim_group(ch); 3595 3596 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3597 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", 3598 path, tgidx); 3599 3600 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) { 3601 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx); 3602 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx); 3603 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st]; 3604 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd]; 3605 val = (tde_1st + tde_2nd) / 2; 3606 3607 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3608 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", 3609 path, val, tde_1st, tde_2nd); 3610 } else { 3611 val = tssi_info->tssi_trim_6g[path][tgidx]; 3612 3613 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3614 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", 3615 path, val); 3616 } 3617 3618 return val; 3619 } 3620 3621 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, 3622 enum rtw89_phy_idx phy, 3623 const struct rtw89_chan *chan, 3624 struct rtw89_h2c_rf_tssi *h2c) 3625 { 3626 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3627 u8 ch = chan->channel; 3628 s8 trim_de; 3629 s8 ofdm_de; 3630 s8 cck_de; 3631 u8 gidx; 3632 s8 val; 3633 int i; 3634 3635 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n", 3636 phy, ch); 3637 3638 for (i = RF_PATH_A; i <= RF_PATH_B; i++) { 3639 trim_de = phy_tssi_get_ofdm_trim_de(rtwdev, phy, chan, i); 3640 h2c->curr_tssi_trim_de[i] = trim_de; 3641 3642 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3643 "[TSSI][TRIM]: path=%d trim_de=0x%x\n", i, trim_de); 3644 3645 gidx = phy_tssi_get_cck_group(ch); 3646 cck_de = tssi_info->tssi_cck[i][gidx]; 3647 val = u32_get_bits(cck_de + trim_de, 0xff); 3648 3649 h2c->curr_tssi_cck_de[i] = 0x0; 3650 h2c->curr_tssi_cck_de_20m[i] = val; 3651 h2c->curr_tssi_cck_de_40m[i] = val; 3652 h2c->curr_tssi_efuse_cck_de[i] = cck_de; 3653 3654 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3655 "[TSSI][TRIM]: path=%d cck_de=0x%x\n", i, cck_de); 3656 3657 ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i); 3658 val = u32_get_bits(ofdm_de + trim_de, 0xff); 3659 3660 h2c->curr_tssi_ofdm_de[i] = 0x0; 3661 h2c->curr_tssi_ofdm_de_20m[i] = val; 3662 h2c->curr_tssi_ofdm_de_40m[i] = val; 3663 h2c->curr_tssi_ofdm_de_80m[i] = val; 3664 h2c->curr_tssi_ofdm_de_160m[i] = val; 3665 h2c->curr_tssi_ofdm_de_320m[i] = val; 3666 h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de; 3667 3668 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3669 "[TSSI][TRIM]: path=%d ofdm_de=0x%x\n", i, ofdm_de); 3670 } 3671 } 3672 3673 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev, 3674 enum rtw89_phy_idx phy, 3675 const struct rtw89_chan *chan, 3676 struct rtw89_h2c_rf_tssi *h2c) 3677 { 3678 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk; 3679 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3680 const s8 *thm_up[RF_PATH_B + 1] = {}; 3681 const s8 *thm_down[RF_PATH_B + 1] = {}; 3682 u8 subband = chan->subband_type; 3683 s8 thm_ofst[128] = {0}; 3684 u8 thermal; 3685 u8 path; 3686 u8 i, j; 3687 3688 switch (subband) { 3689 default: 3690 case RTW89_CH_2G: 3691 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0]; 3692 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0]; 3693 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0]; 3694 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0]; 3695 break; 3696 case RTW89_CH_5G_BAND_1: 3697 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0]; 3698 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0]; 3699 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0]; 3700 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0]; 3701 break; 3702 case RTW89_CH_5G_BAND_3: 3703 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1]; 3704 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1]; 3705 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1]; 3706 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1]; 3707 break; 3708 case RTW89_CH_5G_BAND_4: 3709 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2]; 3710 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2]; 3711 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2]; 3712 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2]; 3713 break; 3714 case RTW89_CH_6G_BAND_IDX0: 3715 case RTW89_CH_6G_BAND_IDX1: 3716 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0]; 3717 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0]; 3718 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0]; 3719 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0]; 3720 break; 3721 case RTW89_CH_6G_BAND_IDX2: 3722 case RTW89_CH_6G_BAND_IDX3: 3723 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1]; 3724 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1]; 3725 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1]; 3726 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1]; 3727 break; 3728 case RTW89_CH_6G_BAND_IDX4: 3729 case RTW89_CH_6G_BAND_IDX5: 3730 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2]; 3731 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2]; 3732 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2]; 3733 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2]; 3734 break; 3735 case RTW89_CH_6G_BAND_IDX6: 3736 case RTW89_CH_6G_BAND_IDX7: 3737 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3]; 3738 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3]; 3739 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3]; 3740 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3]; 3741 break; 3742 } 3743 3744 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3745 "[TSSI] tmeter tbl on subband: %u\n", subband); 3746 3747 for (path = RF_PATH_A; path <= RF_PATH_B; path++) { 3748 thermal = tssi_info->thermal[path]; 3749 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3750 "path: %u, pg thermal: 0x%x\n", path, thermal); 3751 3752 if (thermal == 0xff) { 3753 h2c->pg_thermal[path] = 0x38; 3754 memset(h2c->ftable[path], 0, sizeof(h2c->ftable[path])); 3755 continue; 3756 } 3757 3758 h2c->pg_thermal[path] = thermal; 3759 3760 i = 0; 3761 for (j = 0; j < 64; j++) 3762 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 3763 thm_up[path][i++] : 3764 thm_up[path][DELTA_SWINGIDX_SIZE - 1]; 3765 3766 i = 1; 3767 for (j = 127; j >= 64; j--) 3768 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 3769 -thm_down[path][i++] : 3770 -thm_down[path][DELTA_SWINGIDX_SIZE - 1]; 3771 3772 for (i = 0; i < 128; i += 4) { 3773 h2c->ftable[path][i + 0] = thm_ofst[i + 3]; 3774 h2c->ftable[path][i + 1] = thm_ofst[i + 2]; 3775 h2c->ftable[path][i + 2] = thm_ofst[i + 1]; 3776 h2c->ftable[path][i + 3] = thm_ofst[i + 0]; 3777 3778 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3779 "thm ofst [%x]: %02x %02x %02x %02x\n", 3780 i, thm_ofst[i], thm_ofst[i + 1], 3781 thm_ofst[i + 2], thm_ofst[i + 3]); 3782 } 3783 } 3784 } 3785 3786 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 3787 { 3788 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 3789 u32 reg_mask; 3790 3791 if (sc_xo) 3792 reg_mask = xtal->sc_xo_mask; 3793 else 3794 reg_mask = xtal->sc_xi_mask; 3795 3796 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask); 3797 } 3798 3799 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 3800 u8 val) 3801 { 3802 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 3803 u32 reg_mask; 3804 3805 if (sc_xo) 3806 reg_mask = xtal->sc_xo_mask; 3807 else 3808 reg_mask = xtal->sc_xi_mask; 3809 3810 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val); 3811 } 3812 3813 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 3814 u8 crystal_cap, bool force) 3815 { 3816 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3817 const struct rtw89_chip_info *chip = rtwdev->chip; 3818 u8 sc_xi_val, sc_xo_val; 3819 3820 if (!force && cfo->crystal_cap == crystal_cap) 3821 return; 3822 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 3823 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) { 3824 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 3825 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 3826 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 3827 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 3828 } else { 3829 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 3830 crystal_cap, XTAL_SC_XO_MASK); 3831 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 3832 crystal_cap, XTAL_SC_XI_MASK); 3833 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 3834 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 3835 } 3836 cfo->crystal_cap = sc_xi_val; 3837 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 3838 3839 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 3840 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 3841 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 3842 cfo->x_cap_ofst); 3843 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 3844 } 3845 3846 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 3847 { 3848 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3849 u8 cap; 3850 3851 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 3852 cfo->is_adjust = false; 3853 if (cfo->crystal_cap == cfo->def_x_cap) 3854 return; 3855 cap = cfo->crystal_cap; 3856 cap += (cap > cfo->def_x_cap ? -1 : 1); 3857 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 3858 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3859 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 3860 cfo->def_x_cap); 3861 } 3862 3863 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 3864 { 3865 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 3866 bool is_linked = rtwdev->total_sta_assoc > 0; 3867 s32 cfo_avg_312; 3868 s32 dcfo_comp_val; 3869 int sign; 3870 3871 if (rtwdev->chip->chip_id == RTL8922A) 3872 return; 3873 3874 if (!is_linked) { 3875 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 3876 is_linked); 3877 return; 3878 } 3879 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 3880 if (curr_cfo == 0) 3881 return; 3882 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 3883 sign = curr_cfo > 0 ? 1 : -1; 3884 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val; 3885 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312); 3886 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 3887 cfo_avg_312 = -cfo_avg_312; 3888 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 3889 cfo_avg_312); 3890 } 3891 3892 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 3893 { 3894 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3895 const struct rtw89_chip_info *chip = rtwdev->chip; 3896 const struct rtw89_cfo_regs *cfo = phy->cfo; 3897 3898 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1); 3899 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8); 3900 3901 if (chip->chip_gen == RTW89_CHIP_AX) { 3902 if (chip->cfo_hw_comp) { 3903 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2, 3904 B_AX_PWR_UL_CFO_MASK, 0x6); 3905 } else { 3906 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 3907 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, 3908 B_AX_PWR_UL_CFO_MASK); 3909 } 3910 } 3911 } 3912 3913 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 3914 { 3915 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3916 struct rtw89_efuse *efuse = &rtwdev->efuse; 3917 3918 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 3919 cfo->crystal_cap = cfo->crystal_cap_default; 3920 cfo->def_x_cap = cfo->crystal_cap; 3921 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 3922 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 3923 cfo->is_adjust = false; 3924 cfo->divergence_lock_en = false; 3925 cfo->x_cap_ofst = 0; 3926 cfo->lock_cnt = 0; 3927 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 3928 cfo->apply_compensation = false; 3929 cfo->residual_cfo_acc = 0; 3930 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 3931 cfo->crystal_cap_default); 3932 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 3933 rtw89_dcfo_comp_init(rtwdev); 3934 cfo->cfo_timer_ms = 2000; 3935 cfo->cfo_trig_by_timer_en = false; 3936 cfo->phy_cfo_trk_cnt = 0; 3937 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 3938 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 3939 } 3940 3941 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 3942 s32 curr_cfo) 3943 { 3944 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3945 s8 crystal_cap = cfo->crystal_cap; 3946 s32 cfo_abs = abs(curr_cfo); 3947 int sign; 3948 3949 if (curr_cfo == 0) { 3950 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 3951 return; 3952 } 3953 if (!cfo->is_adjust) { 3954 if (cfo_abs > CFO_TRK_ENABLE_TH) 3955 cfo->is_adjust = true; 3956 } else { 3957 if (cfo_abs <= CFO_TRK_STOP_TH) 3958 cfo->is_adjust = false; 3959 } 3960 if (!cfo->is_adjust) { 3961 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 3962 return; 3963 } 3964 sign = curr_cfo > 0 ? 1 : -1; 3965 if (cfo_abs > CFO_TRK_STOP_TH_4) 3966 crystal_cap += 7 * sign; 3967 else if (cfo_abs > CFO_TRK_STOP_TH_3) 3968 crystal_cap += 5 * sign; 3969 else if (cfo_abs > CFO_TRK_STOP_TH_2) 3970 crystal_cap += 3 * sign; 3971 else if (cfo_abs > CFO_TRK_STOP_TH_1) 3972 crystal_cap += 1 * sign; 3973 else 3974 return; 3975 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 3976 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3977 "X_cap{Curr,Default}={0x%x,0x%x}\n", 3978 cfo->crystal_cap, cfo->def_x_cap); 3979 } 3980 3981 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 3982 { 3983 const struct rtw89_chip_info *chip = rtwdev->chip; 3984 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3985 s32 cfo_khz_all = 0; 3986 s32 cfo_cnt_all = 0; 3987 s32 cfo_all_avg = 0; 3988 u8 i; 3989 3990 if (rtwdev->total_sta_assoc != 1) 3991 return 0; 3992 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 3993 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 3994 if (cfo->cfo_cnt[i] == 0) 3995 continue; 3996 cfo_khz_all += cfo->cfo_tail[i]; 3997 cfo_cnt_all += cfo->cfo_cnt[i]; 3998 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 3999 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 4000 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft, 4001 cfo_cnt_all); 4002 } 4003 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4004 "CFO track for macid = %d\n", i); 4005 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4006 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 4007 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 4008 return cfo_all_avg; 4009 } 4010 4011 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 4012 { 4013 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4014 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4015 s32 target_cfo = 0; 4016 s32 cfo_khz_all = 0; 4017 s32 cfo_khz_all_tp_wgt = 0; 4018 s32 cfo_avg = 0; 4019 s32 max_cfo_lb = BIT(31); 4020 s32 min_cfo_ub = GENMASK(30, 0); 4021 u16 cfo_cnt_all = 0; 4022 u8 active_entry_cnt = 0; 4023 u8 sta_cnt = 0; 4024 u32 tp_all = 0; 4025 u8 i; 4026 u8 cfo_tol = 0; 4027 4028 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 4029 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 4030 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 4031 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4032 if (cfo->cfo_cnt[i] == 0) 4033 continue; 4034 cfo_khz_all += cfo->cfo_tail[i]; 4035 cfo_cnt_all += cfo->cfo_cnt[i]; 4036 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 4037 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4038 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 4039 cfo_khz_all, cfo_cnt_all, cfo_avg); 4040 target_cfo = cfo_avg; 4041 } 4042 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 4043 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 4044 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4045 if (cfo->cfo_cnt[i] == 0) 4046 continue; 4047 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 4048 (s32)cfo->cfo_cnt[i]); 4049 cfo_khz_all += cfo->cfo_avg[i]; 4050 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4051 "Macid=%d, cfo_avg=%d\n", i, 4052 cfo->cfo_avg[i]); 4053 } 4054 sta_cnt = rtwdev->total_sta_assoc; 4055 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 4056 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4057 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 4058 cfo_khz_all, sta_cnt, cfo_avg); 4059 target_cfo = cfo_avg; 4060 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 4061 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 4062 cfo_tol = cfo->sta_cfo_tolerance; 4063 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4064 sta_cnt++; 4065 if (cfo->cfo_cnt[i] != 0) { 4066 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 4067 (s32)cfo->cfo_cnt[i]); 4068 active_entry_cnt++; 4069 } else { 4070 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 4071 } 4072 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 4073 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 4074 cfo_khz_all += cfo->cfo_avg[i]; 4075 /* need tp for each entry */ 4076 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4077 "[%d] cfo_avg=%d, tp=tbd\n", 4078 i, cfo->cfo_avg[i]); 4079 if (sta_cnt >= rtwdev->total_sta_assoc) 4080 break; 4081 } 4082 tp_all = stats->rx_throughput; /* need tp for each entry */ 4083 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 4084 4085 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 4086 sta_cnt); 4087 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 4088 active_entry_cnt); 4089 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4090 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 4091 cfo_khz_all_tp_wgt, cfo_avg); 4092 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 4093 max_cfo_lb, min_cfo_ub); 4094 if (max_cfo_lb <= min_cfo_ub) { 4095 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4096 "cfo win_size=%d\n", 4097 min_cfo_ub - max_cfo_lb); 4098 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 4099 } else { 4100 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4101 "No intersection of cfo tolerance windows\n"); 4102 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 4103 } 4104 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 4105 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 4106 } 4107 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 4108 return target_cfo; 4109 } 4110 4111 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 4112 { 4113 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4114 4115 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 4116 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 4117 cfo->packet_count = 0; 4118 cfo->packet_count_pre = 0; 4119 cfo->cfo_avg_pre = 0; 4120 } 4121 4122 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 4123 { 4124 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4125 s32 new_cfo = 0; 4126 bool x_cap_update = false; 4127 u8 pre_x_cap = cfo->crystal_cap; 4128 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 4129 4130 cfo->dcfo_avg = 0; 4131 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 4132 rtwdev->total_sta_assoc); 4133 if (rtwdev->total_sta_assoc == 0) { 4134 rtw89_phy_cfo_reset(rtwdev); 4135 return; 4136 } 4137 if (cfo->packet_count == 0) { 4138 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 4139 return; 4140 } 4141 if (cfo->packet_count == cfo->packet_count_pre) { 4142 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 4143 return; 4144 } 4145 if (rtwdev->total_sta_assoc == 1) 4146 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 4147 else 4148 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 4149 if (cfo->divergence_lock_en) { 4150 cfo->lock_cnt++; 4151 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 4152 cfo->divergence_lock_en = false; 4153 cfo->lock_cnt = 0; 4154 } else { 4155 rtw89_phy_cfo_reset(rtwdev); 4156 } 4157 return; 4158 } 4159 if (cfo->crystal_cap >= cfo->x_cap_ub || 4160 cfo->crystal_cap <= cfo->x_cap_lb) { 4161 cfo->divergence_lock_en = true; 4162 rtw89_phy_cfo_reset(rtwdev); 4163 return; 4164 } 4165 4166 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 4167 cfo->cfo_avg_pre = new_cfo; 4168 cfo->dcfo_avg_pre = cfo->dcfo_avg; 4169 x_cap_update = cfo->crystal_cap != pre_x_cap; 4170 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 4171 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 4172 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 4173 cfo->x_cap_ofst); 4174 if (x_cap_update) { 4175 if (cfo->dcfo_avg > 0) 4176 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 4177 else 4178 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 4179 } 4180 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg); 4181 rtw89_phy_cfo_statistics_reset(rtwdev); 4182 } 4183 4184 void rtw89_phy_cfo_track_work(struct work_struct *work) 4185 { 4186 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4187 cfo_track_work.work); 4188 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4189 4190 mutex_lock(&rtwdev->mutex); 4191 if (!cfo->cfo_trig_by_timer_en) 4192 goto out; 4193 rtw89_leave_ps_mode(rtwdev); 4194 rtw89_phy_cfo_dm(rtwdev); 4195 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 4196 msecs_to_jiffies(cfo->cfo_timer_ms)); 4197 out: 4198 mutex_unlock(&rtwdev->mutex); 4199 } 4200 4201 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 4202 { 4203 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4204 4205 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 4206 msecs_to_jiffies(cfo->cfo_timer_ms)); 4207 } 4208 4209 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 4210 { 4211 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4212 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4213 bool is_ul_ofdma = false, ofdma_acc_en = false; 4214 4215 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 4216 is_ul_ofdma = true; 4217 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 4218 is_ul_ofdma) 4219 ofdma_acc_en = true; 4220 4221 switch (cfo->phy_cfo_status) { 4222 case RTW89_PHY_DCFO_STATE_NORMAL: 4223 if (stats->tx_throughput >= CFO_TP_UPPER) { 4224 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 4225 cfo->cfo_trig_by_timer_en = true; 4226 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 4227 rtw89_phy_cfo_start_work(rtwdev); 4228 } 4229 break; 4230 case RTW89_PHY_DCFO_STATE_ENHANCE: 4231 if (stats->tx_throughput <= CFO_TP_LOWER) 4232 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4233 else if (ofdma_acc_en && 4234 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 4235 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 4236 else 4237 cfo->phy_cfo_trk_cnt++; 4238 4239 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 4240 cfo->phy_cfo_trk_cnt = 0; 4241 cfo->cfo_trig_by_timer_en = false; 4242 } 4243 break; 4244 case RTW89_PHY_DCFO_STATE_HOLD: 4245 if (stats->tx_throughput <= CFO_TP_LOWER) { 4246 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4247 cfo->phy_cfo_trk_cnt = 0; 4248 cfo->cfo_trig_by_timer_en = false; 4249 } else { 4250 cfo->phy_cfo_trk_cnt++; 4251 } 4252 break; 4253 default: 4254 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4255 cfo->phy_cfo_trk_cnt = 0; 4256 break; 4257 } 4258 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4259 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 4260 stats->tx_throughput, cfo->phy_cfo_status, 4261 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 4262 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 4263 if (cfo->cfo_trig_by_timer_en) 4264 return; 4265 rtw89_phy_cfo_dm(rtwdev); 4266 } 4267 4268 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 4269 struct rtw89_rx_phy_ppdu *phy_ppdu) 4270 { 4271 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4272 u8 macid = phy_ppdu->mac_id; 4273 4274 if (macid >= CFO_TRACK_MAX_USER) { 4275 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 4276 return; 4277 } 4278 4279 cfo->cfo_tail[macid] += cfo_val; 4280 cfo->cfo_cnt[macid]++; 4281 cfo->packet_count++; 4282 } 4283 4284 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4285 { 4286 const struct rtw89_chip_info *chip = rtwdev->chip; 4287 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4288 rtwvif->sub_entity_idx); 4289 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4290 4291 if (!chip->ul_tb_waveform_ctrl) 4292 return; 4293 4294 rtwvif->def_tri_idx = 4295 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG); 4296 4297 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV) 4298 rtwvif->dyn_tb_bedge_en = false; 4299 else if (chan->band_type >= RTW89_BAND_5G && 4300 chan->band_width >= RTW89_CHANNEL_WIDTH_40) 4301 rtwvif->dyn_tb_bedge_en = true; 4302 else 4303 rtwvif->dyn_tb_bedge_en = false; 4304 4305 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4306 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n", 4307 ul_tb_info->def_if_bandedge, rtwvif->def_tri_idx); 4308 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4309 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n", 4310 rtwvif->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en); 4311 } 4312 4313 struct rtw89_phy_ul_tb_check_data { 4314 bool valid; 4315 bool high_tf_client; 4316 bool low_tf_client; 4317 bool dyn_tb_bedge_en; 4318 u8 def_tri_idx; 4319 }; 4320 4321 struct rtw89_phy_power_diff { 4322 u32 q_00; 4323 u32 q_11; 4324 u32 q_matrix_en; 4325 u32 ultb_1t_norm_160; 4326 u32 ultb_2t_norm_160; 4327 u32 com1_norm_1sts; 4328 u32 com2_resp_1sts_path; 4329 }; 4330 4331 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev, 4332 struct rtw89_vif *rtwvif) 4333 { 4334 static const struct rtw89_phy_power_diff table[2] = { 4335 {0x0, 0x0, 0x0, 0x0, 0xf4, 0x3, 0x3}, 4336 {0xb50, 0xb50, 0x1, 0xc, 0x0, 0x1, 0x1}, 4337 }; 4338 const struct rtw89_phy_power_diff *param; 4339 u32 reg; 4340 4341 if (!rtwdev->chip->ul_tb_pwr_diff) 4342 return; 4343 4344 if (rtwvif->pwr_diff_en == rtwvif->pre_pwr_diff_en) { 4345 rtwvif->pwr_diff_en = false; 4346 return; 4347 } 4348 4349 rtwvif->pre_pwr_diff_en = rtwvif->pwr_diff_en; 4350 param = &table[rtwvif->pwr_diff_en]; 4351 4352 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL, 4353 param->q_00); 4354 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL, 4355 param->q_11); 4356 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX, 4357 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en); 4358 4359 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif->mac_idx); 4360 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160, 4361 param->ultb_1t_norm_160); 4362 4363 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif->mac_idx); 4364 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160, 4365 param->ultb_2t_norm_160); 4366 4367 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif->mac_idx); 4368 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS, 4369 param->com1_norm_1sts); 4370 4371 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif->mac_idx); 4372 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH, 4373 param->com2_resp_1sts_path); 4374 } 4375 4376 static 4377 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev, 4378 struct rtw89_vif *rtwvif, 4379 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 4380 { 4381 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4382 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4383 4384 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4385 return; 4386 4387 if (!vif->cfg.assoc) 4388 return; 4389 4390 if (rtwdev->chip->ul_tb_waveform_ctrl) { 4391 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH) 4392 ul_tb_data->high_tf_client = true; 4393 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH) 4394 ul_tb_data->low_tf_client = true; 4395 4396 ul_tb_data->valid = true; 4397 ul_tb_data->def_tri_idx = rtwvif->def_tri_idx; 4398 ul_tb_data->dyn_tb_bedge_en = rtwvif->dyn_tb_bedge_en; 4399 } 4400 4401 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif); 4402 } 4403 4404 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev, 4405 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 4406 { 4407 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4408 4409 if (!rtwdev->chip->ul_tb_waveform_ctrl) 4410 return; 4411 4412 if (ul_tb_data->dyn_tb_bedge_en) { 4413 if (ul_tb_data->high_tf_client) { 4414 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0); 4415 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4416 "[ULTB] Turn off if_bandedge\n"); 4417 } else if (ul_tb_data->low_tf_client) { 4418 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 4419 ul_tb_info->def_if_bandedge); 4420 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4421 "[ULTB] Set to default if_bandedge = %d\n", 4422 ul_tb_info->def_if_bandedge); 4423 } 4424 } 4425 4426 if (ul_tb_info->dyn_tb_tri_en) { 4427 if (ul_tb_data->high_tf_client) { 4428 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 4429 B_TXSHAPE_TRIANGULAR_CFG, 0); 4430 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4431 "[ULTB] Turn off Tx triangle\n"); 4432 } else if (ul_tb_data->low_tf_client) { 4433 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 4434 B_TXSHAPE_TRIANGULAR_CFG, 4435 ul_tb_data->def_tri_idx); 4436 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4437 "[ULTB] Set to default tx_shap_idx = %d\n", 4438 ul_tb_data->def_tri_idx); 4439 } 4440 } 4441 } 4442 4443 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev) 4444 { 4445 const struct rtw89_chip_info *chip = rtwdev->chip; 4446 struct rtw89_phy_ul_tb_check_data ul_tb_data = {}; 4447 struct rtw89_vif *rtwvif; 4448 4449 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff) 4450 return; 4451 4452 if (rtwdev->total_sta_assoc != 1) 4453 return; 4454 4455 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4456 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data); 4457 4458 if (!ul_tb_data.valid) 4459 return; 4460 4461 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data); 4462 } 4463 4464 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev) 4465 { 4466 const struct rtw89_chip_info *chip = rtwdev->chip; 4467 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4468 4469 if (!chip->ul_tb_waveform_ctrl) 4470 return; 4471 4472 ul_tb_info->dyn_tb_tri_en = true; 4473 ul_tb_info->def_if_bandedge = 4474 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN); 4475 } 4476 4477 static 4478 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts) 4479 { 4480 ewma_rssi_init(&antdiv_sts->cck_rssi_avg); 4481 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg); 4482 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg); 4483 antdiv_sts->pkt_cnt_cck = 0; 4484 antdiv_sts->pkt_cnt_ofdm = 0; 4485 antdiv_sts->pkt_cnt_non_legacy = 0; 4486 antdiv_sts->evm = 0; 4487 } 4488 4489 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev, 4490 struct rtw89_rx_phy_ppdu *phy_ppdu, 4491 struct rtw89_antdiv_stats *stats) 4492 { 4493 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) { 4494 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) { 4495 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg); 4496 stats->pkt_cnt_cck++; 4497 } else { 4498 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg); 4499 stats->pkt_cnt_ofdm++; 4500 stats->evm += phy_ppdu->ofdm.evm_min; 4501 } 4502 } else { 4503 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg); 4504 stats->pkt_cnt_non_legacy++; 4505 stats->evm += phy_ppdu->ofdm.evm_min; 4506 } 4507 } 4508 4509 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats) 4510 { 4511 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck && 4512 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm) 4513 return ewma_rssi_read(&stats->non_legacy_rssi_avg); 4514 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck && 4515 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy) 4516 return ewma_rssi_read(&stats->ofdm_rssi_avg); 4517 else 4518 return ewma_rssi_read(&stats->cck_rssi_avg); 4519 } 4520 4521 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats) 4522 { 4523 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm); 4524 } 4525 4526 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 4527 struct rtw89_rx_phy_ppdu *phy_ppdu) 4528 { 4529 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4530 struct rtw89_hal *hal = &rtwdev->hal; 4531 4532 if (!hal->ant_diversity || hal->ant_diversity_fixed) 4533 return; 4534 4535 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats); 4536 4537 if (!antdiv->get_stats) 4538 return; 4539 4540 if (hal->antenna_rx == RF_A) 4541 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats); 4542 else if (hal->antenna_rx == RF_B) 4543 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats); 4544 } 4545 4546 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev) 4547 { 4548 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN, 4549 0x0, RTW89_PHY_0); 4550 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL, 4551 0x0, RTW89_PHY_0); 4552 4553 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND, 4554 0x0, RTW89_PHY_0); 4555 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT, 4556 0x0, RTW89_PHY_0); 4557 4558 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN, 4559 0x0, RTW89_PHY_0); 4560 4561 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING, 4562 0x0100, RTW89_PHY_0); 4563 4564 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX, 4565 0x1, RTW89_PHY_0); 4566 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL, 4567 0x0, RTW89_PHY_0); 4568 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G, 4569 0x0, RTW89_PHY_0); 4570 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G, 4571 0x0, RTW89_PHY_0); 4572 } 4573 4574 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev) 4575 { 4576 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4577 4578 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 4579 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats); 4580 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats); 4581 } 4582 4583 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev) 4584 { 4585 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4586 struct rtw89_hal *hal = &rtwdev->hal; 4587 4588 if (!hal->ant_diversity) 4589 return; 4590 4591 antdiv->get_stats = false; 4592 antdiv->rssi_pre = 0; 4593 rtw89_phy_antdiv_sts_reset(rtwdev); 4594 rtw89_phy_antdiv_reg_init(rtwdev); 4595 } 4596 4597 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 4598 { 4599 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 4600 int i; 4601 u8 th; 4602 4603 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 4604 th = rtw89_chip_get_thermal(rtwdev, i); 4605 if (th) 4606 ewma_thermal_add(&phystat->avg_thermal[i], th); 4607 4608 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 4609 "path(%d) thermal cur=%u avg=%ld", i, th, 4610 ewma_thermal_read(&phystat->avg_thermal[i])); 4611 } 4612 } 4613 4614 struct rtw89_phy_iter_rssi_data { 4615 struct rtw89_dev *rtwdev; 4616 struct rtw89_phy_ch_info *ch_info; 4617 bool rssi_changed; 4618 }; 4619 4620 static void rtw89_phy_stat_rssi_update_iter(void *data, 4621 struct ieee80211_sta *sta) 4622 { 4623 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 4624 struct rtw89_phy_iter_rssi_data *rssi_data = 4625 (struct rtw89_phy_iter_rssi_data *)data; 4626 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 4627 unsigned long rssi_curr; 4628 4629 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 4630 4631 if (rssi_curr < ch_info->rssi_min) { 4632 ch_info->rssi_min = rssi_curr; 4633 ch_info->rssi_min_macid = rtwsta->mac_id; 4634 } 4635 4636 if (rtwsta->prev_rssi == 0) { 4637 rtwsta->prev_rssi = rssi_curr; 4638 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 4639 rtwsta->prev_rssi = rssi_curr; 4640 rssi_data->rssi_changed = true; 4641 } 4642 } 4643 4644 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 4645 { 4646 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 4647 4648 rssi_data.rtwdev = rtwdev; 4649 rssi_data.ch_info = &rtwdev->ch_info; 4650 rssi_data.ch_info->rssi_min = U8_MAX; 4651 ieee80211_iterate_stations_atomic(rtwdev->hw, 4652 rtw89_phy_stat_rssi_update_iter, 4653 &rssi_data); 4654 if (rssi_data.rssi_changed) 4655 rtw89_btc_ntfy_wl_sta(rtwdev); 4656 } 4657 4658 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 4659 { 4660 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 4661 int i; 4662 4663 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 4664 ewma_thermal_init(&phystat->avg_thermal[i]); 4665 4666 rtw89_phy_stat_thermal_update(rtwdev); 4667 4668 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 4669 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 4670 } 4671 4672 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 4673 { 4674 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 4675 4676 rtw89_phy_stat_thermal_update(rtwdev); 4677 rtw89_phy_stat_rssi_update(rtwdev); 4678 4679 phystat->last_pkt_stat = phystat->cur_pkt_stat; 4680 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 4681 } 4682 4683 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 4684 { 4685 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4686 4687 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 4688 } 4689 4690 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 4691 { 4692 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4693 4694 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 4695 } 4696 4697 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 4698 { 4699 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4700 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4701 const struct rtw89_ccx_regs *ccx = phy->ccx; 4702 4703 env->ccx_manual_ctrl = false; 4704 env->ccx_ongoing = false; 4705 env->ccx_rac_lv = RTW89_RAC_RELEASE; 4706 env->ccx_period = 0; 4707 env->ccx_unit_idx = RTW89_CCX_32_US; 4708 4709 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->en_mask, 1); 4710 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1); 4711 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1); 4712 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask, 4713 RTW89_CCX_EDCCA_BW20_0); 4714 } 4715 4716 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 4717 u16 score) 4718 { 4719 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4720 u32 numer = 0; 4721 u16 ret = 0; 4722 4723 numer = report * score + (env->ccx_period >> 1); 4724 if (env->ccx_period) 4725 ret = numer / env->ccx_period; 4726 4727 return ret >= score ? score - 1 : ret; 4728 } 4729 4730 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 4731 u16 time_ms, u32 *period, 4732 u32 *unit_idx) 4733 { 4734 u32 idx; 4735 u8 quotient; 4736 4737 if (time_ms >= CCX_MAX_PERIOD) 4738 time_ms = CCX_MAX_PERIOD; 4739 4740 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 4741 4742 if (quotient < 4) 4743 idx = RTW89_CCX_4_US; 4744 else if (quotient < 8) 4745 idx = RTW89_CCX_8_US; 4746 else if (quotient < 16) 4747 idx = RTW89_CCX_16_US; 4748 else 4749 idx = RTW89_CCX_32_US; 4750 4751 *unit_idx = idx; 4752 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 4753 4754 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4755 "[Trigger Time] period:%d, unit_idx:%d\n", 4756 *period, *unit_idx); 4757 } 4758 4759 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 4760 { 4761 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4762 4763 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4764 "lv:(%d)->(0)\n", env->ccx_rac_lv); 4765 4766 env->ccx_ongoing = false; 4767 env->ccx_rac_lv = RTW89_RAC_RELEASE; 4768 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 4769 } 4770 4771 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 4772 struct rtw89_ccx_para_info *para) 4773 { 4774 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4775 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 4776 u8 i = 0; 4777 u16 *ifs_th_l = env->ifs_clm_th_l; 4778 u16 *ifs_th_h = env->ifs_clm_th_h; 4779 u32 ifs_th0_us = 0, ifs_th_times = 0; 4780 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 4781 4782 if (!is_update) 4783 goto ifs_update_finished; 4784 4785 switch (para->ifs_clm_app) { 4786 case RTW89_IFS_CLM_INIT: 4787 case RTW89_IFS_CLM_BACKGROUND: 4788 case RTW89_IFS_CLM_ACS: 4789 case RTW89_IFS_CLM_DBG: 4790 case RTW89_IFS_CLM_DIG: 4791 case RTW89_IFS_CLM_TDMA_DIG: 4792 ifs_th0_us = IFS_CLM_TH0_UPPER; 4793 ifs_th_times = IFS_CLM_TH_MUL; 4794 break; 4795 case RTW89_IFS_CLM_DBG_MANUAL: 4796 ifs_th0_us = para->ifs_clm_manual_th0; 4797 ifs_th_times = para->ifs_clm_manual_th_times; 4798 break; 4799 default: 4800 break; 4801 } 4802 4803 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 4804 * low[i] = high[i-1] + 1 4805 * high[i] = high[i-1] * ifs_th_times 4806 */ 4807 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 4808 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 4809 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 4810 ifs_th0_us); 4811 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 4812 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 4813 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 4814 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 4815 } 4816 4817 ifs_update_finished: 4818 if (!is_update) 4819 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4820 "No need to update IFS_TH\n"); 4821 4822 return is_update; 4823 } 4824 4825 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 4826 { 4827 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4828 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4829 const struct rtw89_ccx_regs *ccx = phy->ccx; 4830 u8 i = 0; 4831 4832 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask, 4833 env->ifs_clm_th_l[0]); 4834 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask, 4835 env->ifs_clm_th_l[1]); 4836 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask, 4837 env->ifs_clm_th_l[2]); 4838 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask, 4839 env->ifs_clm_th_l[3]); 4840 4841 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask, 4842 env->ifs_clm_th_h[0]); 4843 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask, 4844 env->ifs_clm_th_h[1]); 4845 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask, 4846 env->ifs_clm_th_h[2]); 4847 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask, 4848 env->ifs_clm_th_h[3]); 4849 4850 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 4851 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4852 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 4853 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 4854 } 4855 4856 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 4857 { 4858 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4859 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4860 const struct rtw89_ccx_regs *ccx = phy->ccx; 4861 struct rtw89_ccx_para_info para = {0}; 4862 4863 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 4864 env->ifs_clm_mntr_time = 0; 4865 4866 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 4867 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 4868 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 4869 4870 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true); 4871 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true); 4872 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true); 4873 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true); 4874 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true); 4875 } 4876 4877 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 4878 enum rtw89_env_racing_lv level) 4879 { 4880 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4881 int ret = 0; 4882 4883 if (level >= RTW89_RAC_MAX_NUM) { 4884 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4885 "[WARNING] Wrong LV=%d\n", level); 4886 return -EINVAL; 4887 } 4888 4889 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4890 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 4891 env->ccx_rac_lv, level); 4892 4893 if (env->ccx_ongoing) { 4894 if (level <= env->ccx_rac_lv) 4895 ret = -EINVAL; 4896 else 4897 env->ccx_ongoing = false; 4898 } 4899 4900 if (ret == 0) 4901 env->ccx_rac_lv = level; 4902 4903 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 4904 !ret); 4905 4906 return ret; 4907 } 4908 4909 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 4910 { 4911 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4912 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4913 const struct rtw89_ccx_regs *ccx = phy->ccx; 4914 4915 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0); 4916 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0); 4917 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1); 4918 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1); 4919 4920 env->ccx_ongoing = true; 4921 } 4922 4923 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 4924 { 4925 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4926 u8 i = 0; 4927 u32 res = 0; 4928 4929 env->ifs_clm_tx_ratio = 4930 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 4931 env->ifs_clm_edcca_excl_cca_ratio = 4932 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 4933 PERCENT); 4934 env->ifs_clm_cck_fa_ratio = 4935 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 4936 env->ifs_clm_ofdm_fa_ratio = 4937 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 4938 env->ifs_clm_cck_cca_excl_fa_ratio = 4939 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 4940 PERCENT); 4941 env->ifs_clm_ofdm_cca_excl_fa_ratio = 4942 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 4943 PERCENT); 4944 env->ifs_clm_cck_fa_permil = 4945 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 4946 env->ifs_clm_ofdm_fa_permil = 4947 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 4948 4949 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 4950 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 4951 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 4952 } else { 4953 env->ifs_clm_ifs_avg[i] = 4954 rtw89_phy_ccx_idx_to_us(rtwdev, 4955 env->ifs_clm_avg[i]); 4956 } 4957 4958 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 4959 res += env->ifs_clm_his[i] >> 1; 4960 if (env->ifs_clm_his[i]) 4961 res /= env->ifs_clm_his[i]; 4962 else 4963 res = 0; 4964 env->ifs_clm_cca_avg[i] = res; 4965 } 4966 4967 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4968 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 4969 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 4970 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4971 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 4972 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 4973 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4974 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 4975 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 4976 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4977 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 4978 env->ifs_clm_cck_cca_excl_fa_ratio, 4979 env->ifs_clm_ofdm_cca_excl_fa_ratio); 4980 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4981 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 4982 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 4983 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 4984 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 4985 env->ifs_clm_cca_avg[i]); 4986 } 4987 4988 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 4989 { 4990 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4991 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4992 const struct rtw89_ccx_regs *ccx = phy->ccx; 4993 u8 i = 0; 4994 4995 if (rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr, 4996 ccx->ifs_cnt_done_mask) == 0) { 4997 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4998 "Get IFS_CLM report Fail\n"); 4999 return false; 5000 } 5001 5002 env->ifs_clm_tx = 5003 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr, 5004 ccx->ifs_clm_tx_cnt_msk); 5005 env->ifs_clm_edcca_excl_cca = 5006 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr, 5007 ccx->ifs_clm_edcca_excl_cca_fa_mask); 5008 env->ifs_clm_cckcca_excl_fa = 5009 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr, 5010 ccx->ifs_clm_cckcca_excl_fa_mask); 5011 env->ifs_clm_ofdmcca_excl_fa = 5012 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr, 5013 ccx->ifs_clm_ofdmcca_excl_fa_mask); 5014 env->ifs_clm_cckfa = 5015 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr, 5016 ccx->ifs_clm_cck_fa_mask); 5017 env->ifs_clm_ofdmfa = 5018 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr, 5019 ccx->ifs_clm_ofdm_fa_mask); 5020 5021 env->ifs_clm_his[0] = 5022 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 5023 ccx->ifs_t1_his_mask); 5024 env->ifs_clm_his[1] = 5025 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 5026 ccx->ifs_t2_his_mask); 5027 env->ifs_clm_his[2] = 5028 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 5029 ccx->ifs_t3_his_mask); 5030 env->ifs_clm_his[3] = 5031 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 5032 ccx->ifs_t4_his_mask); 5033 5034 env->ifs_clm_avg[0] = 5035 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr, 5036 ccx->ifs_t1_avg_mask); 5037 env->ifs_clm_avg[1] = 5038 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr, 5039 ccx->ifs_t2_avg_mask); 5040 env->ifs_clm_avg[2] = 5041 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr, 5042 ccx->ifs_t3_avg_mask); 5043 env->ifs_clm_avg[3] = 5044 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr, 5045 ccx->ifs_t4_avg_mask); 5046 5047 env->ifs_clm_cca[0] = 5048 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr, 5049 ccx->ifs_t1_cca_mask); 5050 env->ifs_clm_cca[1] = 5051 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr, 5052 ccx->ifs_t2_cca_mask); 5053 env->ifs_clm_cca[2] = 5054 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr, 5055 ccx->ifs_t3_cca_mask); 5056 env->ifs_clm_cca[3] = 5057 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr, 5058 ccx->ifs_t4_cca_mask); 5059 5060 env->ifs_clm_total_ifs = 5061 rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr, 5062 ccx->ifs_total_mask); 5063 5064 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 5065 env->ifs_clm_total_ifs); 5066 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5067 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 5068 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 5069 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5070 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 5071 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 5072 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5073 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 5074 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 5075 5076 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 5077 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 5078 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5079 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 5080 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 5081 5082 rtw89_phy_ifs_clm_get_utility(rtwdev); 5083 5084 return true; 5085 } 5086 5087 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 5088 struct rtw89_ccx_para_info *para) 5089 { 5090 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5091 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 5092 const struct rtw89_ccx_regs *ccx = phy->ccx; 5093 u32 period = 0; 5094 u32 unit_idx = 0; 5095 5096 if (para->mntr_time == 0) { 5097 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5098 "[WARN] MNTR_TIME is 0\n"); 5099 return -EINVAL; 5100 } 5101 5102 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 5103 return -EINVAL; 5104 5105 if (para->mntr_time != env->ifs_clm_mntr_time) { 5106 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 5107 &period, &unit_idx); 5108 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, 5109 ccx->ifs_clm_period_mask, period); 5110 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, 5111 ccx->ifs_clm_cnt_unit_mask, 5112 unit_idx); 5113 5114 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5115 "Update IFS-CLM time ((%d)) -> ((%d))\n", 5116 env->ifs_clm_mntr_time, para->mntr_time); 5117 5118 env->ifs_clm_mntr_time = para->mntr_time; 5119 env->ccx_period = (u16)period; 5120 env->ccx_unit_idx = (u8)unit_idx; 5121 } 5122 5123 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 5124 env->ifs_clm_app = para->ifs_clm_app; 5125 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 5126 } 5127 5128 return 0; 5129 } 5130 5131 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 5132 { 5133 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 5134 struct rtw89_ccx_para_info para = {0}; 5135 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 5136 5137 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 5138 if (env->ccx_manual_ctrl) { 5139 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5140 "CCX in manual ctrl\n"); 5141 return; 5142 } 5143 5144 /* only ifs_clm for now */ 5145 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 5146 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 5147 5148 rtw89_phy_ccx_racing_release(rtwdev); 5149 para.mntr_time = 1900; 5150 para.rac_lv = RTW89_RAC_LV_1; 5151 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 5152 5153 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 5154 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 5155 if (chk_result) 5156 rtw89_phy_ccx_trigger(rtwdev); 5157 5158 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5159 "get_result=0x%x, chk_result:0x%x\n", 5160 env->ccx_watchdog_result, chk_result); 5161 } 5162 5163 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 5164 { 5165 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM || 5166 *ie_page == RTW89_RSVD_9) 5167 return false; 5168 else if (*ie_page > RTW89_RSVD_9) 5169 *ie_page -= 1; 5170 5171 return true; 5172 } 5173 5174 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 5175 { 5176 static const u8 ie_page_shift = 2; 5177 5178 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 5179 } 5180 5181 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 5182 enum rtw89_phy_status_bitmap ie_page) 5183 { 5184 u32 addr; 5185 5186 if (!rtw89_physts_ie_page_valid(&ie_page)) 5187 return 0; 5188 5189 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 5190 5191 return rtw89_phy_read32(rtwdev, addr); 5192 } 5193 5194 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 5195 enum rtw89_phy_status_bitmap ie_page, 5196 u32 val) 5197 { 5198 const struct rtw89_chip_info *chip = rtwdev->chip; 5199 u32 addr; 5200 5201 if (!rtw89_physts_ie_page_valid(&ie_page)) 5202 return; 5203 5204 if (chip->chip_id == RTL8852A) 5205 val &= B_PHY_STS_BITMAP_MSK_52A; 5206 5207 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 5208 rtw89_phy_write32(rtwdev, addr, val); 5209 } 5210 5211 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 5212 enum rtw89_phy_status_bitmap bitmap, 5213 enum rtw89_phy_status_ie_type ie, 5214 bool enable) 5215 { 5216 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 5217 5218 if (enable) 5219 val |= BIT(ie); 5220 else 5221 val &= ~BIT(ie); 5222 5223 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 5224 } 5225 5226 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 5227 bool enable, 5228 enum rtw89_phy_idx phy_idx) 5229 { 5230 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5231 const struct rtw89_physts_regs *physts = phy->physts; 5232 5233 if (enable) { 5234 rtw89_phy_write32_clr(rtwdev, physts->setting_addr, 5235 physts->dis_trigger_fail_mask); 5236 rtw89_phy_write32_clr(rtwdev, physts->setting_addr, 5237 physts->dis_trigger_brk_mask); 5238 } else { 5239 rtw89_phy_write32_set(rtwdev, physts->setting_addr, 5240 physts->dis_trigger_fail_mask); 5241 rtw89_phy_write32_set(rtwdev, physts->setting_addr, 5242 physts->dis_trigger_brk_mask); 5243 } 5244 } 5245 5246 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 5247 { 5248 u8 i; 5249 5250 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 5251 5252 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 5253 if (i >= RTW89_CCK_PKT) 5254 rtw89_physts_enable_ie_bitmap(rtwdev, i, 5255 RTW89_PHYSTS_IE09_FTR_0, 5256 true); 5257 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 5258 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 5259 continue; 5260 rtw89_physts_enable_ie_bitmap(rtwdev, i, 5261 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 5262 true); 5263 } 5264 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 5265 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 5266 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 5267 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 5268 5269 /* force IE01 for channel index, only channel field is valid */ 5270 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 5271 RTW89_PHYSTS_IE01_CMN_OFDM, true); 5272 } 5273 5274 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 5275 { 5276 const struct rtw89_chip_info *chip = rtwdev->chip; 5277 struct rtw89_dig_info *dig = &rtwdev->dig; 5278 const struct rtw89_phy_dig_gain_cfg *cfg; 5279 const char *msg; 5280 u8 i; 5281 s8 gain_base; 5282 s8 *gain_arr; 5283 u32 tmp; 5284 5285 switch (type) { 5286 case RTW89_DIG_GAIN_LNA_G: 5287 gain_arr = dig->lna_gain_g; 5288 gain_base = LNA0_GAIN; 5289 cfg = chip->dig_table->cfg_lna_g; 5290 msg = "lna_gain_g"; 5291 break; 5292 case RTW89_DIG_GAIN_TIA_G: 5293 gain_arr = dig->tia_gain_g; 5294 gain_base = TIA0_GAIN_G; 5295 cfg = chip->dig_table->cfg_tia_g; 5296 msg = "tia_gain_g"; 5297 break; 5298 case RTW89_DIG_GAIN_LNA_A: 5299 gain_arr = dig->lna_gain_a; 5300 gain_base = LNA0_GAIN; 5301 cfg = chip->dig_table->cfg_lna_a; 5302 msg = "lna_gain_a"; 5303 break; 5304 case RTW89_DIG_GAIN_TIA_A: 5305 gain_arr = dig->tia_gain_a; 5306 gain_base = TIA0_GAIN_A; 5307 cfg = chip->dig_table->cfg_tia_a; 5308 msg = "tia_gain_a"; 5309 break; 5310 default: 5311 return; 5312 } 5313 5314 for (i = 0; i < cfg->size; i++) { 5315 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 5316 cfg->table[i].mask); 5317 tmp >>= DIG_GAIN_SHIFT; 5318 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 5319 gain_base += DIG_GAIN; 5320 5321 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 5322 msg, i, gain_arr[i]); 5323 } 5324 } 5325 5326 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 5327 { 5328 struct rtw89_dig_info *dig = &rtwdev->dig; 5329 u32 tmp; 5330 u8 i; 5331 5332 if (!rtwdev->hal.support_igi) 5333 return; 5334 5335 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 5336 B_PATH0_IB_PKPW_MSK); 5337 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 5338 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 5339 B_PATH0_IB_PBK_MSK); 5340 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 5341 dig->ib_pkpwr, dig->ib_pbk); 5342 5343 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 5344 rtw89_phy_dig_read_gain_table(rtwdev, i); 5345 } 5346 5347 static const u8 rssi_nolink = 22; 5348 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 5349 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 5350 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 5351 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 5352 5353 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 5354 { 5355 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 5356 struct rtw89_dig_info *dig = &rtwdev->dig; 5357 bool is_linked = rtwdev->total_sta_assoc > 0; 5358 5359 if (is_linked) { 5360 dig->igi_rssi = ch_info->rssi_min >> 1; 5361 } else { 5362 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 5363 dig->igi_rssi = rssi_nolink; 5364 } 5365 } 5366 5367 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 5368 { 5369 struct rtw89_dig_info *dig = &rtwdev->dig; 5370 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 5371 bool is_linked = rtwdev->total_sta_assoc > 0; 5372 const u16 *fa_th_src = NULL; 5373 5374 switch (chan->band_type) { 5375 case RTW89_BAND_2G: 5376 dig->lna_gain = dig->lna_gain_g; 5377 dig->tia_gain = dig->tia_gain_g; 5378 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 5379 dig->force_gaincode_idx_en = false; 5380 dig->dyn_pd_th_en = true; 5381 break; 5382 case RTW89_BAND_5G: 5383 default: 5384 dig->lna_gain = dig->lna_gain_a; 5385 dig->tia_gain = dig->tia_gain_a; 5386 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 5387 dig->force_gaincode_idx_en = true; 5388 dig->dyn_pd_th_en = true; 5389 break; 5390 } 5391 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 5392 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 5393 } 5394 5395 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 5396 static const u8 igi_max_performance_mode = 0x5a; 5397 static const u8 dynamic_pd_threshold_max; 5398 5399 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 5400 { 5401 struct rtw89_dig_info *dig = &rtwdev->dig; 5402 5403 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 5404 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 5405 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 5406 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 5407 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 5408 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 5409 5410 dig->dyn_igi_max = igi_max_performance_mode; 5411 dig->dyn_igi_min = dynamic_igi_min; 5412 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 5413 dig->pd_low_th_ofst = pd_low_th_offset; 5414 dig->is_linked_pre = false; 5415 } 5416 5417 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 5418 { 5419 rtw89_phy_dig_update_gain_para(rtwdev); 5420 rtw89_phy_dig_reset(rtwdev); 5421 } 5422 5423 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 5424 { 5425 struct rtw89_dig_info *dig = &rtwdev->dig; 5426 u8 lna_idx; 5427 5428 if (rssi < dig->igi_rssi_th[0]) 5429 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 5430 else if (rssi < dig->igi_rssi_th[1]) 5431 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 5432 else if (rssi < dig->igi_rssi_th[2]) 5433 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 5434 else if (rssi < dig->igi_rssi_th[3]) 5435 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 5436 else if (rssi < dig->igi_rssi_th[4]) 5437 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 5438 else 5439 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 5440 5441 return lna_idx; 5442 } 5443 5444 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 5445 { 5446 struct rtw89_dig_info *dig = &rtwdev->dig; 5447 u8 tia_idx; 5448 5449 if (rssi < dig->igi_rssi_th[0]) 5450 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 5451 else 5452 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 5453 5454 return tia_idx; 5455 } 5456 5457 #define IB_PBK_BASE 110 5458 #define WB_RSSI_BASE 10 5459 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 5460 struct rtw89_agc_gaincode_set *set) 5461 { 5462 struct rtw89_dig_info *dig = &rtwdev->dig; 5463 s8 lna_gain = dig->lna_gain[set->lna_idx]; 5464 s8 tia_gain = dig->tia_gain[set->tia_idx]; 5465 s32 wb_rssi = rssi + lna_gain + tia_gain; 5466 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 5467 u8 rxb_idx; 5468 5469 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 5470 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 5471 5472 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 5473 wb_rssi, rxb_idx_tmp); 5474 5475 return rxb_idx; 5476 } 5477 5478 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 5479 struct rtw89_agc_gaincode_set *set) 5480 { 5481 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 5482 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 5483 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 5484 5485 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5486 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 5487 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 5488 } 5489 5490 #define IGI_OFFSET_MAX 25 5491 #define IGI_OFFSET_MUL 2 5492 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 5493 { 5494 struct rtw89_dig_info *dig = &rtwdev->dig; 5495 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 5496 enum rtw89_dig_noisy_level noisy_lv; 5497 u8 igi_offset = dig->fa_rssi_ofst; 5498 u16 fa_ratio = 0; 5499 5500 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 5501 5502 if (fa_ratio < dig->fa_th[0]) 5503 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 5504 else if (fa_ratio < dig->fa_th[1]) 5505 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 5506 else if (fa_ratio < dig->fa_th[2]) 5507 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 5508 else if (fa_ratio < dig->fa_th[3]) 5509 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 5510 else 5511 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 5512 5513 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 5514 igi_offset = 0; 5515 else 5516 igi_offset += noisy_lv * IGI_OFFSET_MUL; 5517 5518 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 5519 dig->fa_rssi_ofst = igi_offset; 5520 5521 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5522 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 5523 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 5524 5525 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5526 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 5527 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 5528 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 5529 noisy_lv, igi_offset); 5530 } 5531 5532 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 5533 { 5534 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5535 5536 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr, 5537 dig_regs->p0_lna_init.mask, lna_idx); 5538 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr, 5539 dig_regs->p1_lna_init.mask, lna_idx); 5540 } 5541 5542 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 5543 { 5544 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5545 5546 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr, 5547 dig_regs->p0_tia_init.mask, tia_idx); 5548 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr, 5549 dig_regs->p1_tia_init.mask, tia_idx); 5550 } 5551 5552 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 5553 { 5554 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5555 5556 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr, 5557 dig_regs->p0_rxb_init.mask, rxb_idx); 5558 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr, 5559 dig_regs->p1_rxb_init.mask, rxb_idx); 5560 } 5561 5562 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 5563 const struct rtw89_agc_gaincode_set set) 5564 { 5565 if (!rtwdev->hal.support_igi) 5566 return; 5567 5568 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 5569 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 5570 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 5571 5572 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 5573 set.lna_idx, set.tia_idx, set.rxb_idx); 5574 } 5575 5576 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 5577 bool enable) 5578 { 5579 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5580 5581 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 5582 dig_regs->p0_p20_pagcugc_en.mask, enable); 5583 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 5584 dig_regs->p0_s20_pagcugc_en.mask, enable); 5585 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 5586 dig_regs->p1_p20_pagcugc_en.mask, enable); 5587 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 5588 dig_regs->p1_s20_pagcugc_en.mask, enable); 5589 5590 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 5591 } 5592 5593 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 5594 { 5595 struct rtw89_dig_info *dig = &rtwdev->dig; 5596 5597 if (!rtwdev->hal.support_igi) 5598 return; 5599 5600 if (dig->force_gaincode_idx_en) { 5601 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 5602 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5603 "Force gaincode index enabled.\n"); 5604 } else { 5605 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 5606 &dig->cur_gaincode); 5607 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 5608 } 5609 } 5610 5611 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 5612 bool enable) 5613 { 5614 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 5615 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5616 enum rtw89_bandwidth cbw = chan->band_width; 5617 struct rtw89_dig_info *dig = &rtwdev->dig; 5618 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 5619 u8 ofdm_cca_th; 5620 s8 cck_cca_th; 5621 u32 pd_val = 0; 5622 5623 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX) 5624 under_region += PD_TH_SB_FLTR_CMP_VAL; 5625 5626 switch (cbw) { 5627 case RTW89_CHANNEL_WIDTH_40: 5628 under_region += PD_TH_BW40_CMP_VAL; 5629 break; 5630 case RTW89_CHANNEL_WIDTH_80: 5631 under_region += PD_TH_BW80_CMP_VAL; 5632 break; 5633 case RTW89_CHANNEL_WIDTH_160: 5634 under_region += PD_TH_BW160_CMP_VAL; 5635 break; 5636 case RTW89_CHANNEL_WIDTH_20: 5637 fallthrough; 5638 default: 5639 under_region += PD_TH_BW20_CMP_VAL; 5640 break; 5641 } 5642 5643 dig->dyn_pd_th_max = dig->igi_rssi; 5644 5645 final_rssi = min_t(u8, rssi, dig->igi_rssi); 5646 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 5647 PD_TH_MAX_RSSI + under_region); 5648 5649 if (enable) { 5650 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 5651 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5652 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 5653 final_rssi, ofdm_cca_th, under_region, pd_val); 5654 } else { 5655 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5656 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 5657 } 5658 5659 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 5660 dig_regs->pd_lower_bound_mask, pd_val); 5661 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 5662 dig_regs->pd_spatial_reuse_en, enable); 5663 5664 if (!rtwdev->hal.support_cckpd) 5665 return; 5666 5667 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 5668 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 5669 5670 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5671 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 5672 final_rssi, cck_cca_th, under_region, pd_val); 5673 5674 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_reg, 5675 dig_regs->bmode_cca_rssi_limit_en, enable); 5676 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_lower_bound_reg, 5677 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val); 5678 } 5679 5680 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 5681 { 5682 struct rtw89_dig_info *dig = &rtwdev->dig; 5683 5684 dig->bypass_dig = false; 5685 rtw89_phy_dig_para_reset(rtwdev); 5686 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 5687 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 5688 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 5689 rtw89_phy_dig_update_para(rtwdev); 5690 } 5691 5692 #define IGI_RSSI_MIN 10 5693 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 5694 { 5695 struct rtw89_dig_info *dig = &rtwdev->dig; 5696 bool is_linked = rtwdev->total_sta_assoc > 0; 5697 5698 if (unlikely(dig->bypass_dig)) { 5699 dig->bypass_dig = false; 5700 return; 5701 } 5702 5703 if (!dig->is_linked_pre && is_linked) { 5704 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 5705 rtw89_phy_dig_update_para(rtwdev); 5706 } else if (dig->is_linked_pre && !is_linked) { 5707 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 5708 rtw89_phy_dig_update_para(rtwdev); 5709 } 5710 dig->is_linked_pre = is_linked; 5711 5712 rtw89_phy_dig_igi_offset_by_env(rtwdev); 5713 rtw89_phy_dig_update_rssi_info(rtwdev); 5714 5715 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 5716 dig->igi_rssi - IGI_RSSI_MIN : 0; 5717 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 5718 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 5719 5720 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 5721 dig->dyn_igi_max); 5722 5723 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5724 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 5725 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 5726 dig->igi_fa_rssi); 5727 5728 rtw89_phy_dig_config_igi(rtwdev); 5729 5730 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 5731 5732 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 5733 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 5734 else 5735 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 5736 } 5737 5738 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 5739 { 5740 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 5741 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 5742 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5743 struct rtw89_hal *hal = &rtwdev->hal; 5744 bool *done = data; 5745 u8 rssi_a, rssi_b; 5746 u32 candidate; 5747 5748 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || sta->tdls) 5749 return; 5750 5751 if (*done) 5752 return; 5753 5754 *done = true; 5755 5756 rssi_a = ewma_rssi_read(&rtwsta->rssi[RF_PATH_A]); 5757 rssi_b = ewma_rssi_read(&rtwsta->rssi[RF_PATH_B]); 5758 5759 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 5760 candidate = RF_A; 5761 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 5762 candidate = RF_B; 5763 else 5764 return; 5765 5766 if (hal->antenna_tx == candidate) 5767 return; 5768 5769 hal->antenna_tx = candidate; 5770 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta); 5771 5772 if (hal->antenna_tx == RF_A) { 5773 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 5774 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 5775 } else if (hal->antenna_tx == RF_B) { 5776 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 5777 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 5778 } 5779 } 5780 5781 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 5782 { 5783 struct rtw89_hal *hal = &rtwdev->hal; 5784 bool done = false; 5785 5786 if (!hal->tx_path_diversity) 5787 return; 5788 5789 ieee80211_iterate_stations_atomic(rtwdev->hw, 5790 rtw89_phy_tx_path_div_sta_iter, 5791 &done); 5792 } 5793 5794 #define ANTDIV_MAIN 0 5795 #define ANTDIV_AUX 1 5796 5797 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev) 5798 { 5799 struct rtw89_hal *hal = &rtwdev->hal; 5800 u8 default_ant, optional_ant; 5801 5802 if (!hal->ant_diversity || hal->antenna_tx == 0) 5803 return; 5804 5805 if (hal->antenna_tx == RF_B) { 5806 default_ant = ANTDIV_AUX; 5807 optional_ant = ANTDIV_MAIN; 5808 } else { 5809 default_ant = ANTDIV_MAIN; 5810 optional_ant = ANTDIV_AUX; 5811 } 5812 5813 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL, 5814 default_ant, RTW89_PHY_0); 5815 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI, 5816 default_ant, RTW89_PHY_0); 5817 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT, 5818 optional_ant, RTW89_PHY_0); 5819 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI, 5820 default_ant, RTW89_PHY_0); 5821 } 5822 5823 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev) 5824 { 5825 struct rtw89_hal *hal = &rtwdev->hal; 5826 5827 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A; 5828 hal->antenna_tx = hal->antenna_rx; 5829 } 5830 5831 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev) 5832 { 5833 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5834 struct rtw89_hal *hal = &rtwdev->hal; 5835 bool no_change = false; 5836 u8 main_rssi, aux_rssi; 5837 u8 main_evm, aux_evm; 5838 u32 candidate; 5839 5840 antdiv->get_stats = false; 5841 antdiv->training_count = 0; 5842 5843 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats); 5844 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats); 5845 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats); 5846 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats); 5847 5848 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH) 5849 candidate = RF_A; 5850 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH) 5851 candidate = RF_B; 5852 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 5853 candidate = RF_A; 5854 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 5855 candidate = RF_B; 5856 else 5857 no_change = true; 5858 5859 if (no_change) { 5860 /* swap back from training antenna to original */ 5861 rtw89_phy_swap_hal_antenna(rtwdev); 5862 return; 5863 } 5864 5865 hal->antenna_tx = candidate; 5866 hal->antenna_rx = candidate; 5867 } 5868 5869 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev) 5870 { 5871 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5872 u64 state_period; 5873 5874 if (antdiv->training_count % 2 == 0) { 5875 if (antdiv->training_count == 0) 5876 rtw89_phy_antdiv_sts_reset(rtwdev); 5877 5878 antdiv->get_stats = true; 5879 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL); 5880 } else { 5881 antdiv->get_stats = false; 5882 state_period = msecs_to_jiffies(ANTDIV_DELAY); 5883 5884 rtw89_phy_swap_hal_antenna(rtwdev); 5885 rtw89_phy_antdiv_set_ant(rtwdev); 5886 } 5887 5888 antdiv->training_count++; 5889 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 5890 state_period); 5891 } 5892 5893 void rtw89_phy_antdiv_work(struct work_struct *work) 5894 { 5895 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 5896 antdiv_work.work); 5897 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5898 5899 mutex_lock(&rtwdev->mutex); 5900 5901 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) { 5902 rtw89_phy_antdiv_training_state(rtwdev); 5903 } else { 5904 rtw89_phy_antdiv_decision_state(rtwdev); 5905 rtw89_phy_antdiv_set_ant(rtwdev); 5906 } 5907 5908 mutex_unlock(&rtwdev->mutex); 5909 } 5910 5911 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev) 5912 { 5913 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5914 struct rtw89_hal *hal = &rtwdev->hal; 5915 u8 rssi, rssi_pre; 5916 5917 if (!hal->ant_diversity || hal->ant_diversity_fixed) 5918 return; 5919 5920 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats); 5921 rssi_pre = antdiv->rssi_pre; 5922 antdiv->rssi_pre = rssi; 5923 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 5924 5925 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH) 5926 return; 5927 5928 antdiv->training_count = 0; 5929 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 0); 5930 } 5931 5932 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 5933 { 5934 rtw89_phy_ccx_top_setting_init(rtwdev); 5935 rtw89_phy_ifs_clm_setting_init(rtwdev); 5936 } 5937 5938 static void rtw89_phy_edcca_init(struct rtw89_dev *rtwdev) 5939 { 5940 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 5941 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak; 5942 5943 memset(edcca_bak, 0, sizeof(*edcca_bak)); 5944 5945 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) { 5946 rtw89_phy_set_phy_regs(rtwdev, R_TXGATING, B_TXGATING_EN, 0); 5947 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_VAL, 2); 5948 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_ON, 1); 5949 rtw89_phy_set_phy_regs(rtwdev, R_SPOOF_CG, B_SPOOF_CG_EN, 0); 5950 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_CG_EN, 0); 5951 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 0); 5952 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 0); 5953 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 1); 5954 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 1); 5955 } 5956 5957 rtw89_phy_write32_mask(rtwdev, edcca_regs->tx_collision_t2r_st, 5958 edcca_regs->tx_collision_t2r_st_mask, 0x29); 5959 } 5960 5961 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 5962 { 5963 rtw89_phy_stat_init(rtwdev); 5964 5965 rtw89_chip_bb_sethw(rtwdev); 5966 5967 rtw89_phy_env_monitor_init(rtwdev); 5968 rtw89_physts_parsing_init(rtwdev); 5969 rtw89_phy_dig_init(rtwdev); 5970 rtw89_phy_cfo_init(rtwdev); 5971 rtw89_phy_bb_wrap_init(rtwdev); 5972 rtw89_phy_edcca_init(rtwdev); 5973 rtw89_phy_ch_info_init(rtwdev); 5974 rtw89_phy_ul_tb_info_init(rtwdev); 5975 rtw89_phy_antdiv_init(rtwdev); 5976 rtw89_chip_rfe_gpio(rtwdev); 5977 rtw89_phy_antdiv_set_ant(rtwdev); 5978 5979 rtw89_chip_rfk_hw_init(rtwdev); 5980 rtw89_phy_init_rf_nctl(rtwdev); 5981 rtw89_chip_rfk_init(rtwdev); 5982 rtw89_chip_set_txpwr_ctrl(rtwdev); 5983 rtw89_chip_power_trim(rtwdev); 5984 rtw89_chip_cfg_txrx_path(rtwdev); 5985 } 5986 5987 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 5988 { 5989 const struct rtw89_chip_info *chip = rtwdev->chip; 5990 const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld; 5991 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 5992 u8 bss_color; 5993 5994 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 5995 return; 5996 5997 bss_color = vif->bss_conf.he_bss_color.color; 5998 5999 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1, 6000 phy_idx); 6001 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT, 6002 bss_color, phy_idx); 6003 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID, 6004 vif->cfg.aid, phy_idx); 6005 } 6006 6007 static bool rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc *desc) 6008 { 6009 return desc->ch != 0; 6010 } 6011 6012 static bool rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc *desc, 6013 const struct rtw89_chan *chan) 6014 { 6015 if (!rfk_chan_validate_desc(desc)) 6016 return false; 6017 6018 if (desc->ch != chan->channel) 6019 return false; 6020 6021 if (desc->has_band && desc->band != chan->band_type) 6022 return false; 6023 6024 if (desc->has_bw && desc->bw != chan->band_width) 6025 return false; 6026 6027 return true; 6028 } 6029 6030 struct rfk_chan_iter_data { 6031 const struct rtw89_rfk_chan_desc desc; 6032 unsigned int found; 6033 }; 6034 6035 static int rfk_chan_iter_search(const struct rtw89_chan *chan, void *data) 6036 { 6037 struct rfk_chan_iter_data *iter_data = data; 6038 6039 if (rfk_chan_is_equivalent(&iter_data->desc, chan)) 6040 iter_data->found++; 6041 6042 return 0; 6043 } 6044 6045 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev, 6046 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr, 6047 const struct rtw89_chan *target_chan) 6048 { 6049 int sel = -1; 6050 u8 i; 6051 6052 for (i = 0; i < desc_nr; i++) { 6053 struct rfk_chan_iter_data iter_data = { 6054 .desc = desc[i], 6055 }; 6056 6057 if (rfk_chan_is_equivalent(&desc[i], target_chan)) 6058 return i; 6059 6060 rtw89_iterate_entity_chan(rtwdev, rfk_chan_iter_search, &iter_data); 6061 if (!iter_data.found && sel == -1) 6062 sel = i; 6063 } 6064 6065 if (sel == -1) { 6066 rtw89_debug(rtwdev, RTW89_DBG_RFK, 6067 "no idle rfk entry; force replace the first\n"); 6068 sel = 0; 6069 } 6070 6071 return sel; 6072 } 6073 EXPORT_SYMBOL(rtw89_rfk_chan_lookup); 6074 6075 static void 6076 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6077 { 6078 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 6079 } 6080 6081 static void 6082 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6083 { 6084 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 6085 } 6086 6087 static void 6088 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6089 { 6090 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 6091 } 6092 6093 static void 6094 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6095 { 6096 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 6097 } 6098 6099 static void 6100 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6101 { 6102 udelay(def->data); 6103 } 6104 6105 static void 6106 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 6107 [RTW89_RFK_F_WRF] = _rfk_write_rf, 6108 [RTW89_RFK_F_WM] = _rfk_write32_mask, 6109 [RTW89_RFK_F_WS] = _rfk_write32_set, 6110 [RTW89_RFK_F_WC] = _rfk_write32_clr, 6111 [RTW89_RFK_F_DELAY] = _rfk_delay, 6112 }; 6113 6114 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 6115 6116 void 6117 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 6118 { 6119 const struct rtw89_reg5_def *p = tbl->defs; 6120 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 6121 6122 for (; p < end; p++) 6123 _rfk_handler[p->flag](rtwdev, p); 6124 } 6125 EXPORT_SYMBOL(rtw89_rfk_parser); 6126 6127 #define RTW89_TSSI_FAST_MODE_NUM 4 6128 6129 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 6130 {0xD934, 0xff0000}, 6131 {0xD934, 0xff000000}, 6132 {0xD938, 0xff}, 6133 {0xD934, 0xff00}, 6134 }; 6135 6136 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 6137 {0xD930, 0xff0000}, 6138 {0xD930, 0xff000000}, 6139 {0xD934, 0xff}, 6140 {0xD930, 0xff00}, 6141 }; 6142 6143 static 6144 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 6145 enum rtw89_mac_idx mac_idx, 6146 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 6147 u32 val) 6148 { 6149 const struct rtw89_reg_def *regs; 6150 u32 reg; 6151 int i; 6152 6153 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 6154 regs = rtw89_tssi_fastmode_regs_flat; 6155 else 6156 regs = rtw89_tssi_fastmode_regs_level; 6157 6158 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 6159 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 6160 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 6161 } 6162 } 6163 6164 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 6165 {0xD91C, 0xff000000}, 6166 {0xD920, 0xff}, 6167 {0xD920, 0xff00}, 6168 {0xD920, 0xff0000}, 6169 {0xD920, 0xff000000}, 6170 {0xD924, 0xff}, 6171 {0xD924, 0xff00}, 6172 {0xD914, 0xff000000}, 6173 {0xD918, 0xff}, 6174 {0xD918, 0xff00}, 6175 {0xD918, 0xff0000}, 6176 {0xD918, 0xff000000}, 6177 {0xD91C, 0xff}, 6178 {0xD91C, 0xff00}, 6179 {0xD91C, 0xff0000}, 6180 }; 6181 6182 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 6183 {0xD910, 0xff}, 6184 {0xD910, 0xff00}, 6185 {0xD910, 0xff0000}, 6186 {0xD910, 0xff000000}, 6187 {0xD914, 0xff}, 6188 {0xD914, 0xff00}, 6189 {0xD914, 0xff0000}, 6190 {0xD908, 0xff}, 6191 {0xD908, 0xff00}, 6192 {0xD908, 0xff0000}, 6193 {0xD908, 0xff000000}, 6194 {0xD90C, 0xff}, 6195 {0xD90C, 0xff00}, 6196 {0xD90C, 0xff0000}, 6197 {0xD90C, 0xff000000}, 6198 }; 6199 6200 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 6201 enum rtw89_mac_idx mac_idx, 6202 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 6203 { 6204 const struct rtw89_chip_info *chip = rtwdev->chip; 6205 const struct rtw89_reg_def *regs; 6206 const u32 *data; 6207 u32 reg; 6208 int i; 6209 6210 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 6211 return; 6212 6213 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 6214 regs = rtw89_tssi_bandedge_regs_flat; 6215 else 6216 regs = rtw89_tssi_bandedge_regs_level; 6217 6218 data = chip->tssi_dbw_table->data[bandedge_cfg]; 6219 6220 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 6221 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 6222 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 6223 } 6224 6225 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx); 6226 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 6227 6228 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 6229 data[RTW89_TSSI_SBW20]); 6230 } 6231 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 6232 6233 static 6234 const u8 rtw89_ch_base_table[16] = {1, 0xff, 6235 36, 100, 132, 149, 0xff, 6236 1, 33, 65, 97, 129, 161, 193, 225, 0xff}; 6237 #define RTW89_CH_BASE_IDX_2G 0 6238 #define RTW89_CH_BASE_IDX_5G_FIRST 2 6239 #define RTW89_CH_BASE_IDX_5G_LAST 5 6240 #define RTW89_CH_BASE_IDX_6G_FIRST 7 6241 #define RTW89_CH_BASE_IDX_6G_LAST 14 6242 6243 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4) 6244 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0) 6245 6246 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band) 6247 { 6248 u8 chan_idx; 6249 u8 last, first; 6250 u8 idx; 6251 6252 switch (band) { 6253 case RTW89_BAND_2G: 6254 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) | 6255 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch); 6256 return chan_idx; 6257 case RTW89_BAND_5G: 6258 first = RTW89_CH_BASE_IDX_5G_FIRST; 6259 last = RTW89_CH_BASE_IDX_5G_LAST; 6260 break; 6261 case RTW89_BAND_6G: 6262 first = RTW89_CH_BASE_IDX_6G_FIRST; 6263 last = RTW89_CH_BASE_IDX_6G_LAST; 6264 break; 6265 default: 6266 rtw89_warn(rtwdev, "Unsupported band %d\n", band); 6267 return 0; 6268 } 6269 6270 for (idx = last; idx >= first; idx--) 6271 if (central_ch >= rtw89_ch_base_table[idx]) 6272 break; 6273 6274 if (idx < first) { 6275 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch); 6276 return 0; 6277 } 6278 6279 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) | 6280 FIELD_PREP(RTW89_CH_OFFSET_MASK, 6281 (central_ch - rtw89_ch_base_table[idx]) >> 1); 6282 return chan_idx; 6283 } 6284 EXPORT_SYMBOL(rtw89_encode_chan_idx); 6285 6286 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 6287 u8 *ch, enum nl80211_band *band) 6288 { 6289 u8 idx, offset; 6290 6291 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx); 6292 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx); 6293 6294 if (idx == RTW89_CH_BASE_IDX_2G) { 6295 *band = NL80211_BAND_2GHZ; 6296 *ch = offset; 6297 return; 6298 } 6299 6300 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ; 6301 *ch = rtw89_ch_base_table[idx] + (offset << 1); 6302 } 6303 EXPORT_SYMBOL(rtw89_decode_chan_idx); 6304 6305 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan) 6306 { 6307 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 6308 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak; 6309 6310 if (scan) { 6311 edcca_bak->a = 6312 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level, 6313 edcca_regs->edcca_mask); 6314 edcca_bak->p = 6315 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level, 6316 edcca_regs->edcca_p_mask); 6317 edcca_bak->ppdu = 6318 rtw89_phy_read32_mask(rtwdev, edcca_regs->ppdu_level, 6319 edcca_regs->ppdu_mask); 6320 6321 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6322 edcca_regs->edcca_mask, EDCCA_MAX); 6323 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6324 edcca_regs->edcca_p_mask, EDCCA_MAX); 6325 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level, 6326 edcca_regs->ppdu_mask, EDCCA_MAX); 6327 } else { 6328 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6329 edcca_regs->edcca_mask, 6330 edcca_bak->a); 6331 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6332 edcca_regs->edcca_p_mask, 6333 edcca_bak->p); 6334 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level, 6335 edcca_regs->ppdu_mask, 6336 edcca_bak->ppdu); 6337 } 6338 } 6339 6340 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev) 6341 { 6342 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 6343 bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80; 6344 s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80; 6345 u8 path, per20_bitmap; 6346 u8 pwdb[8]; 6347 u32 tmp; 6348 6349 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA)) 6350 return; 6351 6352 if (rtwdev->chip->chip_id == RTL8922A) 6353 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 6354 edcca_regs->rpt_sel_be_mask, 0); 6355 6356 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6357 edcca_regs->rpt_sel_mask, 0); 6358 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 6359 path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK); 6360 flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80); 6361 flag_s40 = u32_get_bits(tmp, B_EDCCA_RPT_B_S40); 6362 flag_s20 = u32_get_bits(tmp, B_EDCCA_RPT_B_S20); 6363 flag_p20 = u32_get_bits(tmp, B_EDCCA_RPT_B_P20); 6364 flag_fb = u32_get_bits(tmp, B_EDCCA_RPT_B_FB); 6365 pwdb_s20 = u32_get_bits(tmp, MASKBYTE1); 6366 pwdb_p20 = u32_get_bits(tmp, MASKBYTE2); 6367 pwdb_fb = u32_get_bits(tmp, MASKBYTE3); 6368 6369 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6370 edcca_regs->rpt_sel_mask, 4); 6371 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 6372 pwdb_s80 = u32_get_bits(tmp, MASKBYTE1); 6373 pwdb_s40 = u32_get_bits(tmp, MASKBYTE2); 6374 6375 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_regs->rpt_a, 6376 MASKBYTE0); 6377 6378 if (rtwdev->chip->chip_id == RTL8922A) { 6379 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 6380 edcca_regs->rpt_sel_be_mask, 4); 6381 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 6382 pwdb[0] = u32_get_bits(tmp, MASKBYTE3); 6383 pwdb[1] = u32_get_bits(tmp, MASKBYTE2); 6384 pwdb[2] = u32_get_bits(tmp, MASKBYTE1); 6385 pwdb[3] = u32_get_bits(tmp, MASKBYTE0); 6386 6387 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 6388 edcca_regs->rpt_sel_be_mask, 5); 6389 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 6390 pwdb[4] = u32_get_bits(tmp, MASKBYTE3); 6391 pwdb[5] = u32_get_bits(tmp, MASKBYTE2); 6392 pwdb[6] = u32_get_bits(tmp, MASKBYTE1); 6393 pwdb[7] = u32_get_bits(tmp, MASKBYTE0); 6394 } else { 6395 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6396 edcca_regs->rpt_sel_mask, 0); 6397 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 6398 pwdb[0] = u32_get_bits(tmp, MASKBYTE3); 6399 pwdb[1] = u32_get_bits(tmp, MASKBYTE2); 6400 6401 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6402 edcca_regs->rpt_sel_mask, 1); 6403 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 6404 pwdb[2] = u32_get_bits(tmp, MASKBYTE3); 6405 pwdb[3] = u32_get_bits(tmp, MASKBYTE2); 6406 6407 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6408 edcca_regs->rpt_sel_mask, 2); 6409 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 6410 pwdb[4] = u32_get_bits(tmp, MASKBYTE3); 6411 pwdb[5] = u32_get_bits(tmp, MASKBYTE2); 6412 6413 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6414 edcca_regs->rpt_sel_mask, 3); 6415 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 6416 pwdb[6] = u32_get_bits(tmp, MASKBYTE3); 6417 pwdb[7] = u32_get_bits(tmp, MASKBYTE2); 6418 } 6419 6420 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6421 "[EDCCA]: edcca_bitmap = %04x\n", per20_bitmap); 6422 6423 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6424 "[EDCCA]: pwdb per20{0,1,2,3,4,5,6,7} = {%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n", 6425 pwdb[0], pwdb[1], pwdb[2], pwdb[3], pwdb[4], pwdb[5], 6426 pwdb[6], pwdb[7]); 6427 6428 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6429 "[EDCCA]: path=%d, flag {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}\n", 6430 path, flag_fb, flag_p20, flag_s20, flag_s40, flag_s80); 6431 6432 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6433 "[EDCCA]: pwdb {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}(dBm)\n", 6434 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80); 6435 } 6436 6437 static u8 rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev *rtwdev) 6438 { 6439 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 6440 bool is_linked = rtwdev->total_sta_assoc > 0; 6441 u8 rssi_min = ch_info->rssi_min >> 1; 6442 u8 edcca_thre; 6443 6444 if (!is_linked) { 6445 edcca_thre = EDCCA_MAX; 6446 } else { 6447 edcca_thre = rssi_min - RSSI_UNIT_CONVER + EDCCA_UNIT_CONVER - 6448 EDCCA_TH_REF; 6449 edcca_thre = max_t(u8, edcca_thre, EDCCA_TH_L2H_LB); 6450 } 6451 6452 return edcca_thre; 6453 } 6454 6455 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev) 6456 { 6457 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 6458 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak; 6459 u8 th; 6460 6461 th = rtw89_phy_edcca_get_thre_by_rssi(rtwdev); 6462 if (th == edcca_bak->th_old) 6463 return; 6464 6465 edcca_bak->th_old = th; 6466 6467 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6468 "[EDCCA]: Normal Mode, EDCCA_th = %d\n", th); 6469 6470 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6471 edcca_regs->edcca_mask, th); 6472 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6473 edcca_regs->edcca_p_mask, th); 6474 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level, 6475 edcca_regs->ppdu_mask, th); 6476 } 6477 6478 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev) 6479 { 6480 struct rtw89_hal *hal = &rtwdev->hal; 6481 6482 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DYNAMIC_EDCCA)) 6483 return; 6484 6485 rtw89_phy_edcca_thre_calc(rtwdev); 6486 rtw89_phy_edcca_log(rtwdev); 6487 } 6488 6489 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev, 6490 enum rtw89_phy_idx phy_idx) 6491 { 6492 rtw89_debug(rtwdev, RTW89_DBG_RFK, 6493 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n", 6494 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx); 6495 6496 switch (rtwdev->mlo_dbcc_mode) { 6497 case MLO_1_PLUS_1_1RF: 6498 if (phy_idx == RTW89_PHY_0) 6499 return RF_A; 6500 else 6501 return RF_B; 6502 case MLO_1_PLUS_1_2RF: 6503 if (phy_idx == RTW89_PHY_0) 6504 return RF_A; 6505 else 6506 return RF_D; 6507 case MLO_0_PLUS_2_1RF: 6508 case MLO_2_PLUS_0_1RF: 6509 /* for both PHY 0/1 */ 6510 return RF_AB; 6511 case MLO_0_PLUS_2_2RF: 6512 case MLO_2_PLUS_0_2RF: 6513 case MLO_2_PLUS_2_2RF: 6514 default: 6515 if (phy_idx == RTW89_PHY_0) 6516 return RF_AB; 6517 else 6518 return RF_CD; 6519 } 6520 } 6521 EXPORT_SYMBOL(rtw89_phy_get_kpath); 6522 6523 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev, 6524 enum rtw89_phy_idx phy_idx) 6525 { 6526 rtw89_debug(rtwdev, RTW89_DBG_RFK, 6527 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n", 6528 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx); 6529 6530 switch (rtwdev->mlo_dbcc_mode) { 6531 case MLO_1_PLUS_1_1RF: 6532 if (phy_idx == RTW89_PHY_0) 6533 return RF_PATH_A; 6534 else 6535 return RF_PATH_B; 6536 case MLO_1_PLUS_1_2RF: 6537 if (phy_idx == RTW89_PHY_0) 6538 return RF_PATH_A; 6539 else 6540 return RF_PATH_D; 6541 case MLO_0_PLUS_2_1RF: 6542 case MLO_2_PLUS_0_1RF: 6543 if (phy_idx == RTW89_PHY_0) 6544 return RF_PATH_A; 6545 else 6546 return RF_PATH_B; 6547 case MLO_0_PLUS_2_2RF: 6548 case MLO_2_PLUS_0_2RF: 6549 case MLO_2_PLUS_2_2RF: 6550 default: 6551 if (phy_idx == RTW89_PHY_0) 6552 return RF_PATH_A; 6553 else 6554 return RF_PATH_C; 6555 } 6556 } 6557 EXPORT_SYMBOL(rtw89_phy_get_syn_sel); 6558 6559 static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = { 6560 .setting_addr = R_CCX, 6561 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK, 6562 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, 6563 .trig_opt_mask = B_CCX_TRIG_OPT_MSK, 6564 .en_mask = B_CCX_EN_MSK, 6565 .ifs_cnt_addr = R_IFS_COUNTER, 6566 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, 6567 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, 6568 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, 6569 .ifs_collect_en_mask = B_IFS_COLLECT_EN, 6570 .ifs_t1_addr = R_IFS_T1, 6571 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, 6572 .ifs_t1_en_mask = B_IFS_T1_EN_MSK, 6573 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, 6574 .ifs_t2_addr = R_IFS_T2, 6575 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, 6576 .ifs_t2_en_mask = B_IFS_T2_EN_MSK, 6577 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, 6578 .ifs_t3_addr = R_IFS_T3, 6579 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, 6580 .ifs_t3_en_mask = B_IFS_T3_EN_MSK, 6581 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, 6582 .ifs_t4_addr = R_IFS_T4, 6583 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, 6584 .ifs_t4_en_mask = B_IFS_T4_EN_MSK, 6585 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, 6586 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT, 6587 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, 6588 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, 6589 .ifs_clm_cca_addr = R_IFS_CLM_CCA, 6590 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, 6591 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, 6592 .ifs_clm_fa_addr = R_IFS_CLM_FA, 6593 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, 6594 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, 6595 .ifs_his_addr = R_IFS_HIS, 6596 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, 6597 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, 6598 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, 6599 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK, 6600 .ifs_avg_l_addr = R_IFS_AVG_L, 6601 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK, 6602 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK, 6603 .ifs_avg_h_addr = R_IFS_AVG_H, 6604 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK, 6605 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK, 6606 .ifs_cca_l_addr = R_IFS_CCA_L, 6607 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK, 6608 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK, 6609 .ifs_cca_h_addr = R_IFS_CCA_H, 6610 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK, 6611 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK, 6612 .ifs_total_addr = R_IFSCNT, 6613 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK, 6614 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK, 6615 }; 6616 6617 static const struct rtw89_physts_regs rtw89_physts_regs_ax = { 6618 .setting_addr = R_PLCP_HISTOGRAM, 6619 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, 6620 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, 6621 }; 6622 6623 static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = { 6624 .comp = R_DCFO_WEIGHT, 6625 .weighting_mask = B_DCFO_WEIGHT_MSK, 6626 .comp_seg0 = R_DCFO_OPT, 6627 .valid_0_mask = B_DCFO_OPT_EN, 6628 }; 6629 6630 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = { 6631 .cr_base = 0x10000, 6632 .ccx = &rtw89_ccx_regs_ax, 6633 .physts = &rtw89_physts_regs_ax, 6634 .cfo = &rtw89_cfo_regs_ax, 6635 .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax, 6636 .config_bb_gain = rtw89_phy_config_bb_gain_ax, 6637 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax, 6638 .bb_wrap_init = NULL, 6639 .ch_info_init = NULL, 6640 6641 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax, 6642 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax, 6643 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax, 6644 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax, 6645 }; 6646 EXPORT_SYMBOL(rtw89_phy_gen_ax); 6647