1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "acpi.h" 6 #include "chan.h" 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "phy.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "sar.h" 15 #include "txrx.h" 16 #include "util.h" 17 18 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 19 { 20 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 21 22 return phy->phy0_phy1_offset(rtwdev, addr); 23 } 24 25 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 26 const struct rtw89_ra_report *report) 27 { 28 u32 bit_rate = report->bit_rate; 29 30 /* lower than ofdm, do not aggregate */ 31 if (bit_rate < 550) 32 return 1; 33 34 /* avoid AMSDU for legacy rate */ 35 if (report->might_fallback_legacy) 36 return 1; 37 38 /* lower than 20M vht 2ss mcs8, make it small */ 39 if (bit_rate < 1800) 40 return 1200; 41 42 /* lower than 40M vht 2ss mcs9, make it medium */ 43 if (bit_rate < 4000) 44 return 2600; 45 46 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 47 if (bit_rate < 7000) 48 return 3500; 49 50 return rtwdev->chip->max_amsdu_limit; 51 } 52 53 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 54 { 55 u64 ra_mask = 0; 56 u8 mcs_cap; 57 int i, nss; 58 59 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 60 mcs_cap = mcs_map & 0x3; 61 switch (mcs_cap) { 62 case 2: 63 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 64 break; 65 case 1: 66 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 67 break; 68 case 0: 69 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 70 break; 71 default: 72 break; 73 } 74 } 75 76 return ra_mask; 77 } 78 79 static u64 get_he_ra_mask(struct ieee80211_link_sta *link_sta) 80 { 81 struct ieee80211_sta_he_cap cap = link_sta->he_cap; 82 u16 mcs_map; 83 84 switch (link_sta->bandwidth) { 85 case IEEE80211_STA_RX_BW_160: 86 if (cap.he_cap_elem.phy_cap_info[0] & 87 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 88 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 89 else 90 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 91 break; 92 default: 93 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 94 } 95 96 /* MCS11, MCS9, MCS7 */ 97 return get_mcs_ra_mask(mcs_map, 11, 2); 98 } 99 100 static u64 get_eht_mcs_ra_mask(u8 *max_nss, u8 start_mcs, u8 n_nss) 101 { 102 u64 nss_mcs_shift; 103 u64 nss_mcs_val; 104 u64 mask = 0; 105 int i, j; 106 u8 nss; 107 108 for (i = 0; i < n_nss; i++) { 109 nss = u8_get_bits(max_nss[i], IEEE80211_EHT_MCS_NSS_RX); 110 if (!nss) 111 continue; 112 113 nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0); 114 115 for (j = 0, nss_mcs_shift = 12; j < nss; j++, nss_mcs_shift += 16) 116 mask |= nss_mcs_val << nss_mcs_shift; 117 } 118 119 return mask; 120 } 121 122 static u64 get_eht_ra_mask(struct ieee80211_link_sta *link_sta) 123 { 124 struct ieee80211_sta_eht_cap *eht_cap = &link_sta->eht_cap; 125 struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs_nss_20mhz; 126 struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss; 127 u8 *he_phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; 128 129 switch (link_sta->bandwidth) { 130 case IEEE80211_STA_RX_BW_320: 131 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320; 132 /* MCS 9, 11, 13 */ 133 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 134 case IEEE80211_STA_RX_BW_160: 135 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160; 136 /* MCS 9, 11, 13 */ 137 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 138 case IEEE80211_STA_RX_BW_20: 139 if (!(he_phy_cap[0] & 140 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) { 141 mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz; 142 /* MCS 7, 9, 11, 13 */ 143 return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4); 144 } 145 fallthrough; 146 case IEEE80211_STA_RX_BW_80: 147 default: 148 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80; 149 /* MCS 9, 11, 13 */ 150 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 151 } 152 } 153 154 #define RA_FLOOR_TABLE_SIZE 7 155 #define RA_FLOOR_UP_GAP 3 156 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 157 u8 ratr_state) 158 { 159 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 160 u8 rssi_lv = 0; 161 u8 i; 162 163 rssi >>= 1; 164 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 165 if (i >= ratr_state) 166 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 167 if (rssi < rssi_lv_t[i]) { 168 rssi_lv = i; 169 break; 170 } 171 } 172 if (rssi_lv == 0) 173 return 0xffffffffffffffffULL; 174 else if (rssi_lv == 1) 175 return 0xfffffffffffffff0ULL; 176 else if (rssi_lv == 2) 177 return 0xffffffffffffefe0ULL; 178 else if (rssi_lv == 3) 179 return 0xffffffffffffcfc0ULL; 180 else if (rssi_lv == 4) 181 return 0xffffffffffff8f80ULL; 182 else if (rssi_lv >= 5) 183 return 0xffffffffffff0f00ULL; 184 185 return 0xffffffffffffffffULL; 186 } 187 188 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 189 { 190 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 191 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 192 193 if (ra_mask == 0) 194 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 195 196 return ra_mask; 197 } 198 199 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, 200 struct rtw89_sta_link *rtwsta_link, 201 struct ieee80211_link_sta *link_sta, 202 const struct rtw89_chan *chan) 203 { 204 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask; 205 enum nl80211_band band; 206 u64 cfg_mask; 207 208 if (!rtwsta_link->use_cfg_mask) 209 return -1; 210 211 switch (chan->band_type) { 212 case RTW89_BAND_2G: 213 band = NL80211_BAND_2GHZ; 214 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 215 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 216 break; 217 case RTW89_BAND_5G: 218 band = NL80211_BAND_5GHZ; 219 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 220 RA_MASK_OFDM_RATES); 221 break; 222 case RTW89_BAND_6G: 223 band = NL80211_BAND_6GHZ; 224 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 225 RA_MASK_OFDM_RATES); 226 break; 227 default: 228 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 229 return -1; 230 } 231 232 if (link_sta->he_cap.has_he) { 233 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 234 RA_MASK_HE_1SS_RATES); 235 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 236 RA_MASK_HE_2SS_RATES); 237 } else if (link_sta->vht_cap.vht_supported) { 238 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 239 RA_MASK_VHT_1SS_RATES); 240 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 241 RA_MASK_VHT_2SS_RATES); 242 } else if (link_sta->ht_cap.ht_supported) { 243 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 244 RA_MASK_HT_1SS_RATES); 245 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 246 RA_MASK_HT_2SS_RATES); 247 } 248 249 return cfg_mask; 250 } 251 252 static const u64 253 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 254 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 255 static const u64 256 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 257 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 258 static const u64 259 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 260 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 261 static const u64 262 rtw89_ra_mask_eht_rates[4] = {RA_MASK_EHT_1SS_RATES, RA_MASK_EHT_2SS_RATES, 263 RA_MASK_EHT_3SS_RATES, RA_MASK_EHT_4SS_RATES}; 264 static const u64 265 rtw89_ra_mask_eht_mcs0_11[4] = {RA_MASK_EHT_1SS_MCS0_11, RA_MASK_EHT_2SS_MCS0_11, 266 RA_MASK_EHT_3SS_MCS0_11, RA_MASK_EHT_4SS_MCS0_11}; 267 268 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 269 struct rtw89_sta_link *rtwsta_link, 270 struct ieee80211_link_sta *link_sta, 271 const struct rtw89_chan *chan, 272 bool *fix_giltf_en, u8 *fix_giltf) 273 { 274 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask; 275 u8 band = chan->band_type; 276 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 277 u8 he_ltf = mask->control[nl_band].he_ltf; 278 u8 he_gi = mask->control[nl_band].he_gi; 279 280 *fix_giltf_en = true; 281 282 if (rtwdev->chip->chip_id == RTL8852C && 283 chan->band_width == RTW89_CHANNEL_WIDTH_160 && 284 rtw89_sta_link_has_su_mu_4xhe08(link_sta)) 285 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 286 else 287 *fix_giltf = RTW89_GILTF_2XHE08; 288 289 if (!(rtwsta_link->use_cfg_mask && link_sta->he_cap.has_he)) 290 return; 291 292 if (he_ltf == 2 && he_gi == 2) { 293 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 294 } else if (he_ltf == 2 && he_gi == 0) { 295 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 296 } else if (he_ltf == 1 && he_gi == 1) { 297 *fix_giltf = RTW89_GILTF_2XHE16; 298 } else if (he_ltf == 1 && he_gi == 0) { 299 *fix_giltf = RTW89_GILTF_2XHE08; 300 } else if (he_ltf == 0 && he_gi == 1) { 301 *fix_giltf = RTW89_GILTF_1XHE16; 302 } else if (he_ltf == 0 && he_gi == 0) { 303 *fix_giltf = RTW89_GILTF_1XHE08; 304 } 305 } 306 307 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 308 struct rtw89_vif_link *rtwvif_link, 309 struct rtw89_sta_link *rtwsta_link, 310 struct ieee80211_link_sta *link_sta, 311 bool p2p, bool csi) 312 { 313 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern; 314 struct rtw89_ra_info *ra = &rtwsta_link->ra; 315 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 316 rtwvif_link->chanctx_idx); 317 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 318 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi); 319 u64 ra_mask = 0; 320 u64 ra_mask_bak; 321 u8 mode = 0; 322 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 323 u8 bw_mode = 0; 324 u8 stbc_en = 0; 325 u8 ldpc_en = 0; 326 u8 fix_giltf = 0; 327 u8 i; 328 bool sgi = false; 329 bool fix_giltf_en = false; 330 331 memset(ra, 0, sizeof(*ra)); 332 /* Set the ra mask from sta's capability */ 333 if (link_sta->eht_cap.has_eht) { 334 mode |= RTW89_RA_MODE_EHT; 335 ra_mask |= get_eht_ra_mask(link_sta); 336 337 if (rtwdev->hal.no_mcs_12_13) 338 high_rate_masks = rtw89_ra_mask_eht_mcs0_11; 339 else 340 high_rate_masks = rtw89_ra_mask_eht_rates; 341 342 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta, 343 chan, &fix_giltf_en, &fix_giltf); 344 } else if (link_sta->he_cap.has_he) { 345 mode |= RTW89_RA_MODE_HE; 346 csi_mode = RTW89_RA_RPT_MODE_HE; 347 ra_mask |= get_he_ra_mask(link_sta); 348 high_rate_masks = rtw89_ra_mask_he_rates; 349 if (link_sta->he_cap.he_cap_elem.phy_cap_info[2] & 350 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 351 stbc_en = 1; 352 if (link_sta->he_cap.he_cap_elem.phy_cap_info[1] & 353 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 354 ldpc_en = 1; 355 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta, 356 chan, &fix_giltf_en, &fix_giltf); 357 } else if (link_sta->vht_cap.vht_supported) { 358 u16 mcs_map = le16_to_cpu(link_sta->vht_cap.vht_mcs.rx_mcs_map); 359 360 mode |= RTW89_RA_MODE_VHT; 361 csi_mode = RTW89_RA_RPT_MODE_VHT; 362 /* MCS9 (non-20MHz), MCS8, MCS7 */ 363 if (link_sta->bandwidth == IEEE80211_STA_RX_BW_20) 364 ra_mask |= get_mcs_ra_mask(mcs_map, 8, 1); 365 else 366 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 367 high_rate_masks = rtw89_ra_mask_vht_rates; 368 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 369 stbc_en = 1; 370 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 371 ldpc_en = 1; 372 } else if (link_sta->ht_cap.ht_supported) { 373 mode |= RTW89_RA_MODE_HT; 374 csi_mode = RTW89_RA_RPT_MODE_HT; 375 ra_mask |= ((u64)link_sta->ht_cap.mcs.rx_mask[3] << 48) | 376 ((u64)link_sta->ht_cap.mcs.rx_mask[2] << 36) | 377 ((u64)link_sta->ht_cap.mcs.rx_mask[1] << 24) | 378 ((u64)link_sta->ht_cap.mcs.rx_mask[0] << 12); 379 high_rate_masks = rtw89_ra_mask_ht_rates; 380 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 381 stbc_en = 1; 382 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 383 ldpc_en = 1; 384 } 385 386 switch (chan->band_type) { 387 case RTW89_BAND_2G: 388 ra_mask |= link_sta->supp_rates[NL80211_BAND_2GHZ]; 389 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xf) 390 mode |= RTW89_RA_MODE_CCK; 391 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xff0) 392 mode |= RTW89_RA_MODE_OFDM; 393 break; 394 case RTW89_BAND_5G: 395 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_5GHZ] << 4; 396 mode |= RTW89_RA_MODE_OFDM; 397 break; 398 case RTW89_BAND_6G: 399 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_6GHZ] << 4; 400 mode |= RTW89_RA_MODE_OFDM; 401 break; 402 default: 403 rtw89_err(rtwdev, "Unknown band type\n"); 404 break; 405 } 406 407 ra_mask_bak = ra_mask; 408 409 if (mode >= RTW89_RA_MODE_HT) { 410 u64 mask = 0; 411 for (i = 0; i < rtwdev->hal.tx_nss; i++) 412 mask |= high_rate_masks[i]; 413 if (mode & RTW89_RA_MODE_OFDM) 414 mask |= RA_MASK_SUBOFDM_RATES; 415 if (mode & RTW89_RA_MODE_CCK) 416 mask |= RA_MASK_SUBCCK_RATES; 417 ra_mask &= mask; 418 } else if (mode & RTW89_RA_MODE_OFDM) { 419 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 420 } 421 422 if (mode != RTW89_RA_MODE_CCK) 423 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 424 425 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 426 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan); 427 428 switch (link_sta->bandwidth) { 429 case IEEE80211_STA_RX_BW_160: 430 bw_mode = RTW89_CHANNEL_WIDTH_160; 431 sgi = link_sta->vht_cap.vht_supported && 432 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 433 break; 434 case IEEE80211_STA_RX_BW_80: 435 bw_mode = RTW89_CHANNEL_WIDTH_80; 436 sgi = link_sta->vht_cap.vht_supported && 437 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 438 break; 439 case IEEE80211_STA_RX_BW_40: 440 bw_mode = RTW89_CHANNEL_WIDTH_40; 441 sgi = link_sta->ht_cap.ht_supported && 442 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 443 break; 444 default: 445 bw_mode = RTW89_CHANNEL_WIDTH_20; 446 sgi = link_sta->ht_cap.ht_supported && 447 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 448 break; 449 } 450 451 if (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 452 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 453 ra->dcm_cap = 1; 454 455 if (rate_pattern->enable && !p2p) { 456 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan); 457 ra_mask &= rate_pattern->ra_mask; 458 mode = rate_pattern->ra_mode; 459 } 460 461 ra->bw_cap = bw_mode; 462 ra->er_cap = rtwsta_link->er_cap; 463 ra->mode_ctrl = mode; 464 ra->macid = rtwsta_link->mac_id; 465 ra->stbc_cap = stbc_en; 466 ra->ldpc_cap = ldpc_en; 467 ra->ss_num = min(link_sta->rx_nss, rtwdev->hal.tx_nss) - 1; 468 ra->en_sgi = sgi; 469 ra->ra_mask = ra_mask; 470 ra->fix_giltf_en = fix_giltf_en; 471 ra->fix_giltf = fix_giltf; 472 473 if (!csi) 474 return; 475 476 ra->fixed_csi_rate_en = false; 477 ra->ra_csi_rate_en = true; 478 ra->cr_tbl_sel = false; 479 ra->band_num = rtwvif_link->phy_idx; 480 ra->csi_bw = bw_mode; 481 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 482 ra->csi_mcs_ss_idx = 5; 483 ra->csi_mode = csi_mode; 484 } 485 486 void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev, 487 struct rtw89_sta_link *rtwsta_link, 488 u32 changed) 489 { 490 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link; 491 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 492 struct rtw89_ra_info *ra = &rtwsta_link->ra; 493 struct ieee80211_link_sta *link_sta; 494 495 rcu_read_lock(); 496 497 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 498 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link, 499 link_sta, vif->p2p, false); 500 501 rcu_read_unlock(); 502 503 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 504 ra->upd_mask = 1; 505 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 506 ra->upd_bw_nss_mask = 1; 507 508 rtw89_debug(rtwdev, RTW89_DBG_RA, 509 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 510 ra->macid, 511 ra->bw_cap, 512 ra->ss_num, 513 ra->en_sgi, 514 ra->giltf); 515 516 rtw89_fw_h2c_ra(rtwdev, ra, false); 517 } 518 519 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 520 u32 changed) 521 { 522 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 523 struct rtw89_sta_link *rtwsta_link; 524 unsigned int link_id; 525 526 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 527 rtw89_phy_ra_update_sta_link(rtwdev, rtwsta_link, changed); 528 } 529 530 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 531 u16 rate_base, u64 ra_mask, u8 ra_mode, 532 u32 rate_ctrl, u32 ctrl_skip, bool force) 533 { 534 u8 n, c; 535 536 if (rate_ctrl == ctrl_skip) 537 return true; 538 539 n = hweight32(rate_ctrl); 540 if (n == 0) 541 return true; 542 543 if (force && n != 1) 544 return false; 545 546 if (next->enable) 547 return false; 548 549 c = __fls(rate_ctrl); 550 next->rate = rate_base + c; 551 next->ra_mode = ra_mode; 552 next->ra_mask = ra_mask; 553 next->enable = true; 554 555 return true; 556 } 557 558 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \ 559 { \ 560 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \ 561 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \ 562 } 563 564 static 565 void __rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 566 struct rtw89_vif_link *rtwvif_link, 567 const struct cfg80211_bitrate_mask *mask) 568 { 569 struct ieee80211_supported_band *sband; 570 struct rtw89_phy_rate_pattern next_pattern = {0}; 571 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 572 rtwvif_link->chanctx_idx); 573 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = { 574 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0), 575 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0), 576 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0), 577 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0), 578 }; 579 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = { 580 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0), 581 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0), 582 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0), 583 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0), 584 }; 585 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = { 586 RTW89_HW_RATE_BY_CHIP_GEN(MCS0), 587 RTW89_HW_RATE_BY_CHIP_GEN(MCS8), 588 RTW89_HW_RATE_BY_CHIP_GEN(MCS16), 589 RTW89_HW_RATE_BY_CHIP_GEN(MCS24), 590 }; 591 u8 band = chan->band_type; 592 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 593 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 594 u8 tx_nss = rtwdev->hal.tx_nss; 595 u8 i; 596 597 for (i = 0; i < tx_nss; i++) 598 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen], 599 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 600 mask->control[nl_band].he_mcs[i], 601 0, true)) 602 goto out; 603 604 for (i = 0; i < tx_nss; i++) 605 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen], 606 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 607 mask->control[nl_band].vht_mcs[i], 608 0, true)) 609 goto out; 610 611 for (i = 0; i < tx_nss; i++) 612 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen], 613 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 614 mask->control[nl_band].ht_mcs[i], 615 0, true)) 616 goto out; 617 618 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 619 * require at least one basic rate for ieee80211_set_bitrate_mask, 620 * so the decision just depends on if all bitrates are set or not. 621 */ 622 sband = rtwdev->hw->wiphy->bands[nl_band]; 623 if (band == RTW89_BAND_2G) { 624 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 625 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 626 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 627 mask->control[nl_band].legacy, 628 BIT(sband->n_bitrates) - 1, false)) 629 goto out; 630 } else { 631 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 632 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 633 mask->control[nl_band].legacy, 634 BIT(sband->n_bitrates) - 1, false)) 635 goto out; 636 } 637 638 if (!next_pattern.enable) 639 goto out; 640 641 rtwvif_link->rate_pattern = next_pattern; 642 rtw89_debug(rtwdev, RTW89_DBG_RA, 643 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 644 next_pattern.rate, 645 next_pattern.ra_mask, 646 next_pattern.ra_mode); 647 return; 648 649 out: 650 rtwvif_link->rate_pattern.enable = false; 651 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 652 } 653 654 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 655 struct ieee80211_vif *vif, 656 const struct cfg80211_bitrate_mask *mask) 657 { 658 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 659 struct rtw89_vif_link *rtwvif_link; 660 unsigned int link_id; 661 662 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 663 __rtw89_phy_rate_pattern_vif(rtwdev, rtwvif_link, mask); 664 } 665 666 static void rtw89_phy_ra_update_sta_iter(void *data, struct ieee80211_sta *sta) 667 { 668 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 669 670 rtw89_phy_ra_update_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 671 } 672 673 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 674 { 675 ieee80211_iterate_stations_atomic(rtwdev->hw, 676 rtw89_phy_ra_update_sta_iter, 677 rtwdev); 678 } 679 680 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link) 681 { 682 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link; 683 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 684 struct rtw89_ra_info *ra = &rtwsta_link->ra; 685 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi) >> RSSI_FACTOR; 686 struct ieee80211_link_sta *link_sta; 687 bool csi; 688 689 rcu_read_lock(); 690 691 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 692 csi = rtw89_sta_has_beamformer_cap(link_sta); 693 694 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link, 695 link_sta, vif->p2p, csi); 696 697 rcu_read_unlock(); 698 699 if (rssi > 40) 700 ra->init_rate_lv = 1; 701 else if (rssi > 20) 702 ra->init_rate_lv = 2; 703 else if (rssi > 1) 704 ra->init_rate_lv = 3; 705 else 706 ra->init_rate_lv = 0; 707 ra->upd_all = 1; 708 rtw89_debug(rtwdev, RTW89_DBG_RA, 709 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 710 ra->macid, 711 ra->mode_ctrl, 712 ra->bw_cap, 713 ra->ss_num, 714 ra->init_rate_lv); 715 rtw89_debug(rtwdev, RTW89_DBG_RA, 716 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 717 ra->dcm_cap, 718 ra->er_cap, 719 ra->ldpc_cap, 720 ra->stbc_cap, 721 ra->en_sgi, 722 ra->giltf); 723 724 rtw89_fw_h2c_ra(rtwdev, ra, csi); 725 } 726 727 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 728 const struct rtw89_chan *chan, 729 enum rtw89_bandwidth dbw) 730 { 731 enum rtw89_bandwidth cbw = chan->band_width; 732 u8 pri_ch = chan->primary_channel; 733 u8 central_ch = chan->channel; 734 u8 txsc_idx = 0; 735 u8 tmp = 0; 736 737 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 738 return txsc_idx; 739 740 switch (cbw) { 741 case RTW89_CHANNEL_WIDTH_40: 742 txsc_idx = pri_ch > central_ch ? 1 : 2; 743 break; 744 case RTW89_CHANNEL_WIDTH_80: 745 if (dbw == RTW89_CHANNEL_WIDTH_20) { 746 if (pri_ch > central_ch) 747 txsc_idx = (pri_ch - central_ch) >> 1; 748 else 749 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 750 } else { 751 txsc_idx = pri_ch > central_ch ? 9 : 10; 752 } 753 break; 754 case RTW89_CHANNEL_WIDTH_160: 755 if (pri_ch > central_ch) 756 tmp = (pri_ch - central_ch) >> 1; 757 else 758 tmp = ((central_ch - pri_ch) >> 1) + 1; 759 760 if (dbw == RTW89_CHANNEL_WIDTH_20) { 761 txsc_idx = tmp; 762 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 763 if (tmp == 1 || tmp == 3) 764 txsc_idx = 9; 765 else if (tmp == 5 || tmp == 7) 766 txsc_idx = 11; 767 else if (tmp == 2 || tmp == 4) 768 txsc_idx = 10; 769 else if (tmp == 6 || tmp == 8) 770 txsc_idx = 12; 771 else 772 return 0xff; 773 } else { 774 txsc_idx = pri_ch > central_ch ? 13 : 14; 775 } 776 break; 777 case RTW89_CHANNEL_WIDTH_80_80: 778 if (dbw == RTW89_CHANNEL_WIDTH_20) { 779 if (pri_ch > central_ch) 780 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 781 else 782 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 783 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 784 txsc_idx = pri_ch > central_ch ? 10 : 12; 785 } else { 786 txsc_idx = 14; 787 } 788 break; 789 default: 790 break; 791 } 792 793 return txsc_idx; 794 } 795 EXPORT_SYMBOL(rtw89_phy_get_txsc); 796 797 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 798 enum rtw89_bandwidth dbw) 799 { 800 enum rtw89_bandwidth cbw = chan->band_width; 801 u8 pri_ch = chan->primary_channel; 802 u8 central_ch = chan->channel; 803 u8 txsb_idx = 0; 804 805 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 806 return txsb_idx; 807 808 switch (cbw) { 809 case RTW89_CHANNEL_WIDTH_40: 810 txsb_idx = pri_ch > central_ch ? 1 : 0; 811 break; 812 case RTW89_CHANNEL_WIDTH_80: 813 if (dbw == RTW89_CHANNEL_WIDTH_20) 814 txsb_idx = (pri_ch - central_ch + 6) / 4; 815 else 816 txsb_idx = pri_ch > central_ch ? 1 : 0; 817 break; 818 case RTW89_CHANNEL_WIDTH_160: 819 if (dbw == RTW89_CHANNEL_WIDTH_20) 820 txsb_idx = (pri_ch - central_ch + 14) / 4; 821 else if (dbw == RTW89_CHANNEL_WIDTH_40) 822 txsb_idx = (pri_ch - central_ch + 12) / 8; 823 else 824 txsb_idx = pri_ch > central_ch ? 1 : 0; 825 break; 826 case RTW89_CHANNEL_WIDTH_320: 827 if (dbw == RTW89_CHANNEL_WIDTH_20) 828 txsb_idx = (pri_ch - central_ch + 30) / 4; 829 else if (dbw == RTW89_CHANNEL_WIDTH_40) 830 txsb_idx = (pri_ch - central_ch + 28) / 8; 831 else if (dbw == RTW89_CHANNEL_WIDTH_80) 832 txsb_idx = (pri_ch - central_ch + 24) / 16; 833 else 834 txsb_idx = pri_ch > central_ch ? 1 : 0; 835 break; 836 default: 837 break; 838 } 839 840 return txsb_idx; 841 } 842 EXPORT_SYMBOL(rtw89_phy_get_txsb); 843 844 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 845 { 846 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 847 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 848 } 849 850 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 851 u32 addr, u32 mask) 852 { 853 const struct rtw89_chip_info *chip = rtwdev->chip; 854 const u32 *base_addr = chip->rf_base_addr; 855 u32 val, direct_addr; 856 857 if (rf_path >= rtwdev->chip->rf_path_num) { 858 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 859 return INV_RF_DATA; 860 } 861 862 addr &= 0xff; 863 direct_addr = base_addr[rf_path] + (addr << 2); 864 mask &= RFREG_MASK; 865 866 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 867 868 return val; 869 } 870 EXPORT_SYMBOL(rtw89_phy_read_rf); 871 872 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 873 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 874 { 875 bool busy; 876 bool done; 877 u32 val; 878 int ret; 879 880 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 881 1, 30, false, rtwdev); 882 if (ret) { 883 rtw89_err(rtwdev, "read rf busy swsi\n"); 884 return INV_RF_DATA; 885 } 886 887 mask &= RFREG_MASK; 888 889 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 890 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 891 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 892 udelay(2); 893 894 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 895 30, false, rtwdev, R_SWSI_V1, 896 B_SWSI_R_DATA_DONE_V1); 897 if (ret) { 898 rtw89_err(rtwdev, "read swsi busy\n"); 899 return INV_RF_DATA; 900 } 901 902 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 903 } 904 905 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 906 u32 addr, u32 mask) 907 { 908 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 909 910 if (rf_path >= rtwdev->chip->rf_path_num) { 911 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 912 return INV_RF_DATA; 913 } 914 915 if (ad_sel) 916 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 917 else 918 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 919 } 920 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 921 922 static u32 rtw89_phy_read_full_rf_v2_a(struct rtw89_dev *rtwdev, 923 enum rtw89_rf_path rf_path, u32 addr) 924 { 925 static const u16 r_addr_ofst[2] = {0x2C24, 0x2D24}; 926 static const u16 addr_ofst[2] = {0x2ADC, 0x2BDC}; 927 bool busy, done; 928 int ret; 929 u32 val; 930 931 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_CTL_MASK, 0x1); 932 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, 933 1, 3800, false, 934 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_BUSY); 935 if (ret) { 936 rtw89_warn(rtwdev, "poll HWSI is busy\n"); 937 return INV_RF_DATA; 938 } 939 940 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_MASK, addr); 941 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_RD, 0x1); 942 udelay(2); 943 944 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 945 1, 3800, false, 946 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_RDONE); 947 if (ret) { 948 rtw89_warn(rtwdev, "read HWSI is busy\n"); 949 val = INV_RF_DATA; 950 goto out; 951 } 952 953 val = rtw89_phy_read32_mask(rtwdev, r_addr_ofst[rf_path], RFREG_MASK); 954 out: 955 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_POLL_MASK, 0); 956 957 return val; 958 } 959 960 static u32 rtw89_phy_read_rf_v2_a(struct rtw89_dev *rtwdev, 961 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 962 { 963 u32 val; 964 965 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr); 966 967 return (val & mask) >> __ffs(mask); 968 } 969 970 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 971 u32 addr, u32 mask) 972 { 973 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); 974 975 if (rf_path >= rtwdev->chip->rf_path_num) { 976 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 977 return INV_RF_DATA; 978 } 979 980 if (ad_sel) 981 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 982 else 983 return rtw89_phy_read_rf_v2_a(rtwdev, rf_path, addr, mask); 984 } 985 EXPORT_SYMBOL(rtw89_phy_read_rf_v2); 986 987 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 988 u32 addr, u32 mask, u32 data) 989 { 990 const struct rtw89_chip_info *chip = rtwdev->chip; 991 const u32 *base_addr = chip->rf_base_addr; 992 u32 direct_addr; 993 994 if (rf_path >= rtwdev->chip->rf_path_num) { 995 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 996 return false; 997 } 998 999 addr &= 0xff; 1000 direct_addr = base_addr[rf_path] + (addr << 2); 1001 mask &= RFREG_MASK; 1002 1003 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 1004 1005 /* delay to ensure writing properly */ 1006 udelay(1); 1007 1008 return true; 1009 } 1010 EXPORT_SYMBOL(rtw89_phy_write_rf); 1011 1012 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 1013 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 1014 u32 data) 1015 { 1016 u8 bit_shift; 1017 u32 val; 1018 bool busy, b_msk_en = false; 1019 int ret; 1020 1021 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 1022 1, 30, false, rtwdev); 1023 if (ret) { 1024 rtw89_err(rtwdev, "write rf busy swsi\n"); 1025 return false; 1026 } 1027 1028 data &= RFREG_MASK; 1029 mask &= RFREG_MASK; 1030 1031 if (mask != RFREG_MASK) { 1032 b_msk_en = true; 1033 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 1034 mask); 1035 bit_shift = __ffs(mask); 1036 data = (data << bit_shift) & RFREG_MASK; 1037 } 1038 1039 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 1040 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 1041 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 1042 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 1043 1044 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 1045 1046 return true; 1047 } 1048 1049 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1050 u32 addr, u32 mask, u32 data) 1051 { 1052 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 1053 1054 if (rf_path >= rtwdev->chip->rf_path_num) { 1055 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 1056 return false; 1057 } 1058 1059 if (ad_sel) 1060 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 1061 else 1062 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 1063 } 1064 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 1065 1066 static 1067 bool rtw89_phy_write_full_rf_v2_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1068 u32 addr, u32 data) 1069 { 1070 static const u32 addr_is_idle[2] = {0x2C24, 0x2D24}; 1071 static const u32 addr_ofst[2] = {0x2AE0, 0x2BE0}; 1072 bool busy; 1073 u32 val; 1074 int ret; 1075 1076 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, 1077 1, 3800, false, 1078 rtwdev, addr_is_idle[rf_path], BIT(29)); 1079 if (ret) { 1080 rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__); 1081 return false; 1082 } 1083 1084 val = u32_encode_bits(addr, B_HWSI_DATA_ADDR) | 1085 u32_encode_bits(data, B_HWSI_DATA_VAL); 1086 1087 rtw89_phy_write32(rtwdev, addr_ofst[rf_path], val); 1088 1089 return true; 1090 } 1091 1092 static 1093 bool rtw89_phy_write_rf_a_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1094 u32 addr, u32 mask, u32 data) 1095 { 1096 u32 val; 1097 1098 if (mask == RFREG_MASK) { 1099 val = data; 1100 } else { 1101 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr); 1102 val &= ~mask; 1103 val |= (data << __ffs(mask)) & mask; 1104 } 1105 1106 return rtw89_phy_write_full_rf_v2_a(rtwdev, rf_path, addr, val); 1107 } 1108 1109 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1110 u32 addr, u32 mask, u32 data) 1111 { 1112 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); 1113 1114 if (rf_path >= rtwdev->chip->rf_path_num) { 1115 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 1116 return INV_RF_DATA; 1117 } 1118 1119 if (ad_sel) 1120 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 1121 else 1122 return rtw89_phy_write_rf_a_v2(rtwdev, rf_path, addr, mask, data); 1123 } 1124 EXPORT_SYMBOL(rtw89_phy_write_rf_v2); 1125 1126 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 1127 { 1128 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; 1129 } 1130 1131 static void __rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 1132 enum rtw89_phy_idx phy_idx) 1133 { 1134 const struct rtw89_chip_info *chip = rtwdev->chip; 1135 1136 chip->ops->bb_reset(rtwdev, phy_idx); 1137 } 1138 1139 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev) 1140 { 1141 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1142 if (rtwdev->dbcc_en) 1143 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_1); 1144 } 1145 1146 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 1147 const struct rtw89_reg2_def *reg, 1148 enum rtw89_rf_path rf_path, 1149 void *extra_data) 1150 { 1151 u32 addr; 1152 1153 if (reg->addr == 0xfe) { 1154 mdelay(50); 1155 } else if (reg->addr == 0xfd) { 1156 mdelay(5); 1157 } else if (reg->addr == 0xfc) { 1158 mdelay(1); 1159 } else if (reg->addr == 0xfb) { 1160 udelay(50); 1161 } else if (reg->addr == 0xfa) { 1162 udelay(5); 1163 } else if (reg->addr == 0xf9) { 1164 udelay(1); 1165 } else if (reg->data == BYPASS_CR_DATA) { 1166 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr); 1167 } else { 1168 addr = reg->addr; 1169 1170 if ((uintptr_t)extra_data == RTW89_PHY_1) 1171 addr += rtw89_phy0_phy1_offset(rtwdev, reg->addr); 1172 1173 rtw89_phy_write32(rtwdev, addr, reg->data); 1174 } 1175 } 1176 1177 union rtw89_phy_bb_gain_arg { 1178 u32 addr; 1179 struct { 1180 union { 1181 u8 type; 1182 struct { 1183 u8 rxsc_start:4; 1184 u8 bw:4; 1185 }; 1186 }; 1187 u8 path; 1188 u8 gain_band; 1189 u8 cfg_type; 1190 }; 1191 } __packed; 1192 1193 static void 1194 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 1195 union rtw89_phy_bb_gain_arg arg, u32 data) 1196 { 1197 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1198 u8 type = arg.type; 1199 u8 path = arg.path; 1200 u8 gband = arg.gain_band; 1201 int i; 1202 1203 switch (type) { 1204 case 0: 1205 for (i = 0; i < 4; i++, data >>= 8) 1206 gain->lna_gain[gband][path][i] = data & 0xff; 1207 break; 1208 case 1: 1209 for (i = 4; i < 7; i++, data >>= 8) 1210 gain->lna_gain[gband][path][i] = data & 0xff; 1211 break; 1212 case 2: 1213 for (i = 0; i < 2; i++, data >>= 8) 1214 gain->tia_gain[gband][path][i] = data & 0xff; 1215 break; 1216 default: 1217 rtw89_warn(rtwdev, 1218 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 1219 arg.addr, data, type); 1220 break; 1221 } 1222 } 1223 1224 enum rtw89_phy_bb_rxsc_start_idx { 1225 RTW89_BB_RXSC_START_IDX_FULL = 0, 1226 RTW89_BB_RXSC_START_IDX_20 = 1, 1227 RTW89_BB_RXSC_START_IDX_20_1 = 5, 1228 RTW89_BB_RXSC_START_IDX_40 = 9, 1229 RTW89_BB_RXSC_START_IDX_80 = 13, 1230 }; 1231 1232 static void 1233 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 1234 union rtw89_phy_bb_gain_arg arg, u32 data) 1235 { 1236 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1237 u8 rxsc_start = arg.rxsc_start; 1238 u8 bw = arg.bw; 1239 u8 path = arg.path; 1240 u8 gband = arg.gain_band; 1241 u8 rxsc; 1242 s8 ofst; 1243 int i; 1244 1245 switch (bw) { 1246 case RTW89_CHANNEL_WIDTH_20: 1247 gain->rpl_ofst_20[gband][path] = (s8)data; 1248 break; 1249 case RTW89_CHANNEL_WIDTH_40: 1250 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1251 gain->rpl_ofst_40[gband][path][0] = (s8)data; 1252 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1253 for (i = 0; i < 2; i++, data >>= 8) { 1254 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1255 ofst = (s8)(data & 0xff); 1256 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 1257 } 1258 } 1259 break; 1260 case RTW89_CHANNEL_WIDTH_80: 1261 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1262 gain->rpl_ofst_80[gband][path][0] = (s8)data; 1263 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1264 for (i = 0; i < 4; i++, data >>= 8) { 1265 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1266 ofst = (s8)(data & 0xff); 1267 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 1268 } 1269 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 1270 for (i = 0; i < 2; i++, data >>= 8) { 1271 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 1272 ofst = (s8)(data & 0xff); 1273 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 1274 } 1275 } 1276 break; 1277 case RTW89_CHANNEL_WIDTH_160: 1278 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1279 gain->rpl_ofst_160[gband][path][0] = (s8)data; 1280 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1281 for (i = 0; i < 4; i++, data >>= 8) { 1282 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1283 ofst = (s8)(data & 0xff); 1284 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1285 } 1286 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 1287 for (i = 0; i < 4; i++, data >>= 8) { 1288 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 1289 ofst = (s8)(data & 0xff); 1290 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1291 } 1292 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 1293 for (i = 0; i < 4; i++, data >>= 8) { 1294 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 1295 ofst = (s8)(data & 0xff); 1296 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1297 } 1298 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 1299 for (i = 0; i < 2; i++, data >>= 8) { 1300 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 1301 ofst = (s8)(data & 0xff); 1302 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1303 } 1304 } 1305 break; 1306 default: 1307 rtw89_warn(rtwdev, 1308 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 1309 arg.addr, data, bw); 1310 break; 1311 } 1312 } 1313 1314 static void 1315 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 1316 union rtw89_phy_bb_gain_arg arg, u32 data) 1317 { 1318 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1319 u8 type = arg.type; 1320 u8 path = arg.path; 1321 u8 gband = arg.gain_band; 1322 int i; 1323 1324 switch (type) { 1325 case 0: 1326 for (i = 0; i < 4; i++, data >>= 8) 1327 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1328 break; 1329 case 1: 1330 for (i = 4; i < 7; i++, data >>= 8) 1331 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1332 break; 1333 default: 1334 rtw89_warn(rtwdev, 1335 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 1336 arg.addr, data, type); 1337 break; 1338 } 1339 } 1340 1341 static void 1342 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 1343 union rtw89_phy_bb_gain_arg arg, u32 data) 1344 { 1345 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1346 u8 type = arg.type; 1347 u8 path = arg.path; 1348 u8 gband = arg.gain_band; 1349 int i; 1350 1351 switch (type) { 1352 case 0: 1353 for (i = 0; i < 4; i++, data >>= 8) 1354 gain->lna_op1db[gband][path][i] = data & 0xff; 1355 break; 1356 case 1: 1357 for (i = 4; i < 7; i++, data >>= 8) 1358 gain->lna_op1db[gband][path][i] = data & 0xff; 1359 break; 1360 case 2: 1361 for (i = 0; i < 4; i++, data >>= 8) 1362 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1363 break; 1364 case 3: 1365 for (i = 4; i < 8; i++, data >>= 8) 1366 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1367 break; 1368 default: 1369 rtw89_warn(rtwdev, 1370 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1371 arg.addr, data, type); 1372 break; 1373 } 1374 } 1375 1376 static void rtw89_phy_config_bb_gain_ax(struct rtw89_dev *rtwdev, 1377 const struct rtw89_reg2_def *reg, 1378 enum rtw89_rf_path rf_path, 1379 void *extra_data) 1380 { 1381 const struct rtw89_chip_info *chip = rtwdev->chip; 1382 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1383 struct rtw89_efuse *efuse = &rtwdev->efuse; 1384 1385 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1386 return; 1387 1388 if (arg.path >= chip->rf_path_num) 1389 return; 1390 1391 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1392 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1393 return; 1394 } 1395 1396 switch (arg.cfg_type) { 1397 case 0: 1398 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1399 break; 1400 case 1: 1401 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1402 break; 1403 case 2: 1404 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1405 break; 1406 case 3: 1407 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1408 break; 1409 case 4: 1410 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 1411 if (efuse->rfe_type < 50) 1412 break; 1413 fallthrough; 1414 default: 1415 rtw89_warn(rtwdev, 1416 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1417 arg.addr, reg->data, arg.cfg_type); 1418 break; 1419 } 1420 } 1421 1422 static void 1423 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1424 const struct rtw89_reg2_def *reg, 1425 enum rtw89_rf_path rf_path, 1426 struct rtw89_fw_h2c_rf_reg_info *info) 1427 { 1428 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1429 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1430 1431 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1432 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1433 rf_path, info->curr_idx); 1434 return; 1435 } 1436 1437 info->rtw89_phy_config_rf_h2c[page][idx] = 1438 cpu_to_le32((reg->addr << 20) | reg->data); 1439 info->curr_idx++; 1440 } 1441 1442 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1443 struct rtw89_fw_h2c_rf_reg_info *info) 1444 { 1445 u16 remain = info->curr_idx; 1446 u16 len = 0; 1447 u8 i; 1448 int ret = 0; 1449 1450 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1451 rtw89_warn(rtwdev, 1452 "rf reg h2c total len %d larger than %d\n", 1453 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1454 ret = -EINVAL; 1455 goto out; 1456 } 1457 1458 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1459 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1460 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1461 if (ret) 1462 goto out; 1463 } 1464 out: 1465 info->curr_idx = 0; 1466 1467 return ret; 1468 } 1469 1470 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev, 1471 const struct rtw89_reg2_def *reg, 1472 enum rtw89_rf_path rf_path, 1473 void *extra_data) 1474 { 1475 u32 addr = reg->addr; 1476 1477 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || 1478 addr == 0xfa || addr == 0xf9) 1479 return; 1480 1481 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100) 1482 return; 1483 1484 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1485 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1486 } 1487 1488 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1489 const struct rtw89_reg2_def *reg, 1490 enum rtw89_rf_path rf_path, 1491 void *extra_data) 1492 { 1493 if (reg->addr == 0xfe) { 1494 mdelay(50); 1495 } else if (reg->addr == 0xfd) { 1496 mdelay(5); 1497 } else if (reg->addr == 0xfc) { 1498 mdelay(1); 1499 } else if (reg->addr == 0xfb) { 1500 udelay(50); 1501 } else if (reg->addr == 0xfa) { 1502 udelay(5); 1503 } else if (reg->addr == 0xf9) { 1504 udelay(1); 1505 } else { 1506 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1507 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1508 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1509 } 1510 } 1511 1512 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1513 const struct rtw89_reg2_def *reg, 1514 enum rtw89_rf_path rf_path, 1515 void *extra_data) 1516 { 1517 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1518 1519 if (reg->addr < 0x100) 1520 return; 1521 1522 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1523 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1524 } 1525 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1526 1527 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1528 const struct rtw89_phy_table *table, 1529 u32 *headline_size, u32 *headline_idx, 1530 u8 rfe, u8 cv) 1531 { 1532 const struct rtw89_reg2_def *reg; 1533 u32 headline; 1534 u32 compare, target; 1535 u8 rfe_para, cv_para; 1536 u8 cv_max = 0; 1537 bool case_matched = false; 1538 u32 i; 1539 1540 for (i = 0; i < table->n_regs; i++) { 1541 reg = &table->regs[i]; 1542 headline = get_phy_headline(reg->addr); 1543 if (headline != PHY_HEADLINE_VALID) 1544 break; 1545 } 1546 *headline_size = i; 1547 if (*headline_size == 0) 1548 return 0; 1549 1550 /* case 1: RFE match, CV match */ 1551 compare = get_phy_compare(rfe, cv); 1552 for (i = 0; i < *headline_size; i++) { 1553 reg = &table->regs[i]; 1554 target = get_phy_target(reg->addr); 1555 if (target == compare) { 1556 *headline_idx = i; 1557 return 0; 1558 } 1559 } 1560 1561 /* case 2: RFE match, CV don't care */ 1562 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1563 for (i = 0; i < *headline_size; i++) { 1564 reg = &table->regs[i]; 1565 target = get_phy_target(reg->addr); 1566 if (target == compare) { 1567 *headline_idx = i; 1568 return 0; 1569 } 1570 } 1571 1572 /* case 3: RFE match, CV max in table */ 1573 for (i = 0; i < *headline_size; i++) { 1574 reg = &table->regs[i]; 1575 rfe_para = get_phy_cond_rfe(reg->addr); 1576 cv_para = get_phy_cond_cv(reg->addr); 1577 if (rfe_para == rfe) { 1578 if (cv_para >= cv_max) { 1579 cv_max = cv_para; 1580 *headline_idx = i; 1581 case_matched = true; 1582 } 1583 } 1584 } 1585 1586 if (case_matched) 1587 return 0; 1588 1589 /* case 4: RFE don't care, CV max in table */ 1590 for (i = 0; i < *headline_size; i++) { 1591 reg = &table->regs[i]; 1592 rfe_para = get_phy_cond_rfe(reg->addr); 1593 cv_para = get_phy_cond_cv(reg->addr); 1594 if (rfe_para == PHY_COND_DONT_CARE) { 1595 if (cv_para >= cv_max) { 1596 cv_max = cv_para; 1597 *headline_idx = i; 1598 case_matched = true; 1599 } 1600 } 1601 } 1602 1603 if (case_matched) 1604 return 0; 1605 1606 return -EINVAL; 1607 } 1608 1609 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1610 const struct rtw89_phy_table *table, 1611 void (*config)(struct rtw89_dev *rtwdev, 1612 const struct rtw89_reg2_def *reg, 1613 enum rtw89_rf_path rf_path, 1614 void *data), 1615 void *extra_data) 1616 { 1617 const struct rtw89_reg2_def *reg; 1618 enum rtw89_rf_path rf_path = table->rf_path; 1619 u8 rfe = rtwdev->efuse.rfe_type; 1620 u8 cv = rtwdev->hal.cv; 1621 u32 i; 1622 u32 headline_size = 0, headline_idx = 0; 1623 u32 target = 0, cfg_target; 1624 u8 cond; 1625 bool is_matched = true; 1626 bool target_found = false; 1627 int ret; 1628 1629 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1630 &headline_idx, rfe, cv); 1631 if (ret) { 1632 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1633 return; 1634 } 1635 1636 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1637 for (i = headline_size; i < table->n_regs; i++) { 1638 reg = &table->regs[i]; 1639 cond = get_phy_cond(reg->addr); 1640 switch (cond) { 1641 case PHY_COND_BRANCH_IF: 1642 case PHY_COND_BRANCH_ELIF: 1643 target = get_phy_target(reg->addr); 1644 break; 1645 case PHY_COND_BRANCH_ELSE: 1646 is_matched = false; 1647 if (!target_found) { 1648 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1649 reg->addr, reg->data); 1650 return; 1651 } 1652 break; 1653 case PHY_COND_BRANCH_END: 1654 is_matched = true; 1655 target_found = false; 1656 break; 1657 case PHY_COND_CHECK: 1658 if (target_found) { 1659 is_matched = false; 1660 break; 1661 } 1662 1663 if (target == cfg_target) { 1664 is_matched = true; 1665 target_found = true; 1666 } else { 1667 is_matched = false; 1668 target_found = false; 1669 } 1670 break; 1671 default: 1672 if (is_matched) 1673 config(rtwdev, reg, rf_path, extra_data); 1674 break; 1675 } 1676 } 1677 } 1678 1679 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1680 { 1681 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1682 const struct rtw89_chip_info *chip = rtwdev->chip; 1683 const struct rtw89_phy_table *bb_table; 1684 const struct rtw89_phy_table *bb_gain_table; 1685 1686 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table; 1687 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1688 if (rtwdev->dbcc_en) 1689 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, 1690 (void *)RTW89_PHY_1); 1691 1692 rtw89_chip_init_txpwr_unit(rtwdev); 1693 1694 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table; 1695 if (bb_gain_table) 1696 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1697 chip->phy_def->config_bb_gain, NULL); 1698 1699 rtw89_phy_bb_reset(rtwdev); 1700 } 1701 1702 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1703 { 1704 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1705 udelay(1); 1706 return rtw89_phy_read32(rtwdev, 0x8080); 1707 } 1708 1709 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio) 1710 { 1711 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1712 enum rtw89_rf_path rf_path, void *data); 1713 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1714 const struct rtw89_chip_info *chip = rtwdev->chip; 1715 const struct rtw89_phy_table *rf_table; 1716 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1717 u8 path; 1718 1719 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1720 if (!rf_reg_info) 1721 return; 1722 1723 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1724 rf_table = elm_info->rf_radio[path] ? 1725 elm_info->rf_radio[path] : chip->rf_table[path]; 1726 rf_reg_info->rf_path = rf_table->rf_path; 1727 if (noio) 1728 config = rtw89_phy_config_rf_reg_noio; 1729 else 1730 config = rf_table->config ? rf_table->config : 1731 rtw89_phy_config_rf_reg; 1732 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1733 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1734 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1735 rf_reg_info->rf_path); 1736 } 1737 kfree(rf_reg_info); 1738 } 1739 1740 static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev) 1741 { 1742 const struct rtw89_chip_info *chip = rtwdev->chip; 1743 u32 val; 1744 int ret; 1745 1746 /* IQK/DPK clock & reset */ 1747 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3); 1748 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1); 1749 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000); 1750 if (chip->chip_id != RTL8851B) 1751 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000); 1752 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8852BT) 1753 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2); 1754 1755 /* check 0x8080 */ 1756 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8); 1757 1758 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1759 1000, false, rtwdev); 1760 if (ret) 1761 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1762 } 1763 1764 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1765 { 1766 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1767 const struct rtw89_chip_info *chip = rtwdev->chip; 1768 const struct rtw89_phy_table *nctl_table; 1769 1770 rtw89_phy_preinit_rf_nctl(rtwdev); 1771 1772 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table; 1773 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1774 1775 if (chip->nctl_post_table) 1776 rtw89_rfk_parser(rtwdev, chip->nctl_post_table); 1777 } 1778 1779 static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr) 1780 { 1781 u32 phy_page = addr >> 8; 1782 u32 ofst = 0; 1783 1784 switch (phy_page) { 1785 case 0x6: 1786 case 0x7: 1787 case 0x8: 1788 case 0x9: 1789 case 0xa: 1790 case 0xb: 1791 case 0xc: 1792 case 0xd: 1793 case 0x19: 1794 case 0x1a: 1795 case 0x1b: 1796 ofst = 0x2000; 1797 break; 1798 default: 1799 /* warning case */ 1800 ofst = 0; 1801 break; 1802 } 1803 1804 if (phy_page >= 0x40 && phy_page <= 0x4f) 1805 ofst = 0x2000; 1806 1807 return ofst; 1808 } 1809 1810 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1811 u32 data, enum rtw89_phy_idx phy_idx) 1812 { 1813 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1814 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1815 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1816 } 1817 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1818 1819 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits, 1820 enum rtw89_phy_idx phy_idx) 1821 { 1822 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1823 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1824 rtw89_phy_write32_set(rtwdev, addr, bits); 1825 } 1826 EXPORT_SYMBOL(rtw89_phy_write32_idx_set); 1827 1828 void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits, 1829 enum rtw89_phy_idx phy_idx) 1830 { 1831 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1832 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1833 rtw89_phy_write32_clr(rtwdev, addr, bits); 1834 } 1835 EXPORT_SYMBOL(rtw89_phy_write32_idx_clr); 1836 1837 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1838 enum rtw89_phy_idx phy_idx) 1839 { 1840 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1841 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1842 return rtw89_phy_read32_mask(rtwdev, addr, mask); 1843 } 1844 EXPORT_SYMBOL(rtw89_phy_read32_idx); 1845 1846 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1847 u32 val) 1848 { 1849 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1850 1851 if (!rtwdev->dbcc_en) 1852 return; 1853 1854 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1855 } 1856 EXPORT_SYMBOL(rtw89_phy_set_phy_regs); 1857 1858 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1859 const struct rtw89_phy_reg3_tbl *tbl) 1860 { 1861 const struct rtw89_reg3_def *reg3; 1862 int i; 1863 1864 for (i = 0; i < tbl->size; i++) { 1865 reg3 = &tbl->reg3[i]; 1866 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1867 } 1868 } 1869 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1870 1871 static u8 rtw89_phy_ant_gain_domain_to_regd(struct rtw89_dev *rtwdev, u8 ant_gain_regd) 1872 { 1873 switch (ant_gain_regd) { 1874 case RTW89_ANT_GAIN_ETSI: 1875 return RTW89_ETSI; 1876 default: 1877 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1878 "unknown antenna gain domain: %d\n", 1879 ant_gain_regd); 1880 return RTW89_REGD_NUM; 1881 } 1882 } 1883 1884 /* antenna gain in unit of 0.25 dbm */ 1885 #define RTW89_ANT_GAIN_2GHZ_MIN -8 1886 #define RTW89_ANT_GAIN_2GHZ_MAX 14 1887 #define RTW89_ANT_GAIN_5GHZ_MIN -8 1888 #define RTW89_ANT_GAIN_5GHZ_MAX 20 1889 #define RTW89_ANT_GAIN_6GHZ_MIN -8 1890 #define RTW89_ANT_GAIN_6GHZ_MAX 20 1891 1892 #define RTW89_ANT_GAIN_REF_2GHZ 14 1893 #define RTW89_ANT_GAIN_REF_5GHZ 20 1894 #define RTW89_ANT_GAIN_REF_6GHZ 20 1895 1896 void rtw89_phy_ant_gain_init(struct rtw89_dev *rtwdev) 1897 { 1898 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain; 1899 const struct rtw89_chip_info *chip = rtwdev->chip; 1900 struct rtw89_acpi_rtag_result res = {}; 1901 u32 domain; 1902 int ret; 1903 u8 i, j; 1904 u8 regd; 1905 u8 val; 1906 1907 if (!chip->support_ant_gain) 1908 return; 1909 1910 ret = rtw89_acpi_evaluate_rtag(rtwdev, &res); 1911 if (ret) { 1912 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1913 "acpi: cannot eval rtag: %d\n", ret); 1914 return; 1915 } 1916 1917 if (res.revision != 0) { 1918 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1919 "unknown rtag revision: %d\n", res.revision); 1920 return; 1921 } 1922 1923 domain = get_unaligned_le32(&res.domain); 1924 1925 for (i = 0; i < RTW89_ANT_GAIN_DOMAIN_NUM; i++) { 1926 if (!(domain & BIT(i))) 1927 continue; 1928 1929 regd = rtw89_phy_ant_gain_domain_to_regd(rtwdev, i); 1930 if (regd >= RTW89_REGD_NUM) 1931 continue; 1932 ant_gain->regd_enabled |= BIT(regd); 1933 } 1934 1935 for (i = 0; i < RTW89_ANT_GAIN_CHAIN_NUM; i++) { 1936 for (j = 0; j < RTW89_ANT_GAIN_SUBBAND_NR; j++) { 1937 val = res.ant_gain_table[i][j]; 1938 switch (j) { 1939 default: 1940 case RTW89_ANT_GAIN_2GHZ_SUBBAND: 1941 val = RTW89_ANT_GAIN_REF_2GHZ - 1942 clamp_t(s8, val, 1943 RTW89_ANT_GAIN_2GHZ_MIN, 1944 RTW89_ANT_GAIN_2GHZ_MAX); 1945 break; 1946 case RTW89_ANT_GAIN_5GHZ_SUBBAND_1: 1947 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2: 1948 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2E: 1949 case RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4: 1950 val = RTW89_ANT_GAIN_REF_5GHZ - 1951 clamp_t(s8, val, 1952 RTW89_ANT_GAIN_5GHZ_MIN, 1953 RTW89_ANT_GAIN_5GHZ_MAX); 1954 break; 1955 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L: 1956 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H: 1957 case RTW89_ANT_GAIN_6GHZ_SUBBAND_6: 1958 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L: 1959 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H: 1960 case RTW89_ANT_GAIN_6GHZ_SUBBAND_8: 1961 val = RTW89_ANT_GAIN_REF_6GHZ - 1962 clamp_t(s8, val, 1963 RTW89_ANT_GAIN_6GHZ_MIN, 1964 RTW89_ANT_GAIN_6GHZ_MAX); 1965 } 1966 ant_gain->offset[i][j] = val; 1967 } 1968 } 1969 } 1970 1971 static 1972 enum rtw89_ant_gain_subband rtw89_phy_ant_gain_get_subband(struct rtw89_dev *rtwdev, 1973 u32 center_freq) 1974 { 1975 switch (center_freq) { 1976 default: 1977 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1978 "center freq: %u to antenna gain subband is unhandled\n", 1979 center_freq); 1980 fallthrough; 1981 case 2412 ... 2484: 1982 return RTW89_ANT_GAIN_2GHZ_SUBBAND; 1983 case 5180 ... 5240: 1984 return RTW89_ANT_GAIN_5GHZ_SUBBAND_1; 1985 case 5250 ... 5320: 1986 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2; 1987 case 5500 ... 5720: 1988 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2E; 1989 case 5745 ... 5885: 1990 return RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4; 1991 case 5955 ... 6155: 1992 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L; 1993 case 6175 ... 6415: 1994 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H; 1995 case 6435 ... 6515: 1996 return RTW89_ANT_GAIN_6GHZ_SUBBAND_6; 1997 case 6535 ... 6695: 1998 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L; 1999 case 6715 ... 6855: 2000 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H; 2001 2002 /* freq 6875 (ch 185, 20MHz) spans RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H 2003 * and RTW89_ANT_GAIN_6GHZ_SUBBAND_8, so directly describe it with 2004 * struct rtw89_6ghz_span. 2005 */ 2006 2007 case 6895 ... 7115: 2008 return RTW89_ANT_GAIN_6GHZ_SUBBAND_8; 2009 } 2010 } 2011 2012 static s8 rtw89_phy_ant_gain_query(struct rtw89_dev *rtwdev, 2013 enum rtw89_rf_path path, u32 center_freq) 2014 { 2015 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain; 2016 enum rtw89_ant_gain_subband subband_l, subband_h; 2017 const struct rtw89_6ghz_span *span; 2018 2019 span = rtw89_get_6ghz_span(rtwdev, center_freq); 2020 2021 if (span && RTW89_ANT_GAIN_SPAN_VALID(span)) { 2022 subband_l = span->ant_gain_subband_low; 2023 subband_h = span->ant_gain_subband_high; 2024 } else { 2025 subband_l = rtw89_phy_ant_gain_get_subband(rtwdev, center_freq); 2026 subband_h = subband_l; 2027 } 2028 2029 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2030 "center_freq %u: antenna gain subband {%u, %u}\n", 2031 center_freq, subband_l, subband_h); 2032 2033 return min(ant_gain->offset[path][subband_l], 2034 ant_gain->offset[path][subband_h]); 2035 } 2036 2037 static s8 rtw89_phy_ant_gain_offset(struct rtw89_dev *rtwdev, u8 band, u32 center_freq) 2038 { 2039 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain; 2040 const struct rtw89_chip_info *chip = rtwdev->chip; 2041 u8 regd = rtw89_regd_get(rtwdev, band); 2042 s8 offset_patha, offset_pathb; 2043 2044 if (!chip->support_ant_gain) 2045 return 0; 2046 2047 if (!(ant_gain->regd_enabled & BIT(regd))) 2048 return 0; 2049 2050 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, center_freq); 2051 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, center_freq); 2052 2053 return max(offset_patha, offset_pathb); 2054 } 2055 2056 s16 rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev *rtwdev, 2057 const struct rtw89_chan *chan) 2058 { 2059 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain; 2060 u8 regd = rtw89_regd_get(rtwdev, chan->band_type); 2061 s8 offset_patha, offset_pathb; 2062 2063 if (!(ant_gain->regd_enabled & BIT(regd))) 2064 return 0; 2065 2066 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq); 2067 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq); 2068 2069 return rtw89_phy_txpwr_rf_to_bb(rtwdev, offset_patha - offset_pathb); 2070 } 2071 EXPORT_SYMBOL(rtw89_phy_ant_gain_pwr_offset); 2072 2073 int rtw89_print_ant_gain(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 2074 const struct rtw89_chan *chan) 2075 { 2076 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain; 2077 const struct rtw89_chip_info *chip = rtwdev->chip; 2078 u8 regd = rtw89_regd_get(rtwdev, chan->band_type); 2079 char *p = buf, *end = buf + bufsz; 2080 s8 offset_patha, offset_pathb; 2081 2082 if (!chip->support_ant_gain || !(ant_gain->regd_enabled & BIT(regd))) { 2083 p += scnprintf(p, end - p, "no DAG is applied\n"); 2084 goto out; 2085 } 2086 2087 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq); 2088 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq); 2089 2090 p += scnprintf(p, end - p, "ChainA offset: %d dBm\n", offset_patha); 2091 p += scnprintf(p, end - p, "ChainB offset: %d dBm\n", offset_pathb); 2092 2093 out: 2094 return p - buf; 2095 } 2096 2097 static const u8 rtw89_rs_idx_num_ax[] = { 2098 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM, 2099 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM, 2100 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX, 2101 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM, 2102 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX, 2103 }; 2104 2105 static const u8 rtw89_rs_nss_num_ax[] = { 2106 [RTW89_RS_CCK] = 1, 2107 [RTW89_RS_OFDM] = 1, 2108 [RTW89_RS_MCS] = RTW89_NSS_NUM, 2109 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM, 2110 [RTW89_RS_OFFSET] = 1, 2111 }; 2112 2113 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, 2114 struct rtw89_txpwr_byrate *head, 2115 const struct rtw89_rate_desc *desc) 2116 { 2117 switch (desc->rs) { 2118 case RTW89_RS_CCK: 2119 return &head->cck[desc->idx]; 2120 case RTW89_RS_OFDM: 2121 return &head->ofdm[desc->idx]; 2122 case RTW89_RS_MCS: 2123 return &head->mcs[desc->ofdma][desc->nss][desc->idx]; 2124 case RTW89_RS_HEDCM: 2125 return &head->hedcm[desc->ofdma][desc->nss][desc->idx]; 2126 case RTW89_RS_OFFSET: 2127 return &head->offset[desc->idx]; 2128 default: 2129 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs); 2130 return &head->trap; 2131 } 2132 } 2133 2134 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 2135 const struct rtw89_txpwr_table *tbl) 2136 { 2137 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 2138 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 2139 struct rtw89_txpwr_byrate *byr_head; 2140 struct rtw89_rate_desc desc = {}; 2141 s8 *byr; 2142 u32 data; 2143 u8 i; 2144 2145 for (; cfg < end; cfg++) { 2146 byr_head = &rtwdev->byr[cfg->band][0]; 2147 desc.rs = cfg->rs; 2148 desc.nss = cfg->nss; 2149 data = cfg->data; 2150 2151 for (i = 0; i < cfg->len; i++, data >>= 8) { 2152 desc.idx = cfg->shf + i; 2153 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc); 2154 *byr = data & 0xff; 2155 } 2156 } 2157 } 2158 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 2159 2160 static s8 rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm) 2161 { 2162 const u8 tssi_deviation_point = 0; 2163 const u8 tssi_max_deviation = 2; 2164 2165 if (dbm <= tssi_deviation_point) 2166 dbm -= tssi_max_deviation; 2167 2168 return dbm; 2169 } 2170 2171 static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band) 2172 { 2173 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 2174 const struct rtw89_reg_6ghz_tpe *tpe = ®ulatory->reg_6ghz_tpe; 2175 s8 cstr = S8_MAX; 2176 2177 if (band == RTW89_BAND_6G && tpe->valid) 2178 cstr = rtw89_phy_txpwr_dbm_without_tolerance(tpe->constraint); 2179 2180 return rtw89_phy_txpwr_dbm_to_mac(rtwdev, cstr); 2181 } 2182 2183 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, 2184 const struct rtw89_rate_desc *rate_desc) 2185 { 2186 struct rtw89_txpwr_byrate *byr_head; 2187 s8 *byr; 2188 2189 if (rate_desc->rs == RTW89_RS_CCK) 2190 band = RTW89_BAND_2G; 2191 2192 byr_head = &rtwdev->byr[band][bw]; 2193 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc); 2194 2195 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr); 2196 } 2197 2198 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 2199 { 2200 switch (channel_6g) { 2201 case 1 ... 29: 2202 return (channel_6g - 1) / 2; 2203 case 33 ... 61: 2204 return (channel_6g - 3) / 2; 2205 case 65 ... 93: 2206 return (channel_6g - 5) / 2; 2207 case 97 ... 125: 2208 return (channel_6g - 7) / 2; 2209 case 129 ... 157: 2210 return (channel_6g - 9) / 2; 2211 case 161 ... 189: 2212 return (channel_6g - 11) / 2; 2213 case 193 ... 221: 2214 return (channel_6g - 13) / 2; 2215 case 225 ... 253: 2216 return (channel_6g - 15) / 2; 2217 default: 2218 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 2219 return 0; 2220 } 2221 } 2222 2223 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 2224 { 2225 if (band == RTW89_BAND_6G) 2226 return rtw89_channel_6g_to_idx(rtwdev, channel); 2227 2228 switch (channel) { 2229 case 1 ... 14: 2230 return channel - 1; 2231 case 36 ... 64: 2232 return (channel - 36) / 2; 2233 case 100 ... 144: 2234 return ((channel - 100) / 2) + 15; 2235 case 149 ... 177: 2236 return ((channel - 149) / 2) + 38; 2237 default: 2238 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 2239 return 0; 2240 } 2241 } 2242 2243 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 2244 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 2245 { 2246 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 2247 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 2248 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 2249 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 2250 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 2251 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 2252 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 2253 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 2254 u8 regd = rtw89_regd_get(rtwdev, band); 2255 u8 reg6 = regulatory->reg_6ghz_power; 2256 s8 lmt = 0, sar, offset; 2257 s8 cstr; 2258 2259 switch (band) { 2260 case RTW89_BAND_2G: 2261 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 2262 if (lmt) 2263 break; 2264 2265 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 2266 break; 2267 case RTW89_BAND_5G: 2268 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 2269 if (lmt) 2270 break; 2271 2272 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 2273 break; 2274 case RTW89_BAND_6G: 2275 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx]; 2276 if (lmt) 2277 break; 2278 2279 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW] 2280 [RTW89_REG_6GHZ_POWER_DFLT] 2281 [ch_idx]; 2282 break; 2283 default: 2284 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 2285 return 0; 2286 } 2287 2288 offset = rtw89_phy_ant_gain_offset(rtwdev, band, freq); 2289 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt + offset); 2290 sar = rtw89_query_sar(rtwdev, freq); 2291 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band); 2292 2293 return min3(lmt, sar, cstr); 2294 } 2295 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 2296 2297 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 2298 do { \ 2299 u8 __i; \ 2300 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 2301 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 2302 band, \ 2303 bw, ntx, \ 2304 rs, __i, \ 2305 (ch)); \ 2306 } while (0) 2307 2308 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev, 2309 struct rtw89_txpwr_limit_ax *lmt, 2310 u8 band, u8 ntx, u8 ch) 2311 { 2312 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 2313 ntx, RTW89_RS_CCK, ch); 2314 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 2315 ntx, RTW89_RS_CCK, ch); 2316 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2317 ntx, RTW89_RS_OFDM, ch); 2318 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2319 RTW89_CHANNEL_WIDTH_20, 2320 ntx, RTW89_RS_MCS, ch); 2321 } 2322 2323 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev, 2324 struct rtw89_txpwr_limit_ax *lmt, 2325 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2326 { 2327 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 2328 ntx, RTW89_RS_CCK, ch - 2); 2329 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 2330 ntx, RTW89_RS_CCK, ch); 2331 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2332 ntx, RTW89_RS_OFDM, pri_ch); 2333 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2334 RTW89_CHANNEL_WIDTH_20, 2335 ntx, RTW89_RS_MCS, ch - 2); 2336 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2337 RTW89_CHANNEL_WIDTH_20, 2338 ntx, RTW89_RS_MCS, ch + 2); 2339 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2340 RTW89_CHANNEL_WIDTH_40, 2341 ntx, RTW89_RS_MCS, ch); 2342 } 2343 2344 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev, 2345 struct rtw89_txpwr_limit_ax *lmt, 2346 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2347 { 2348 s8 val_0p5_n[RTW89_BF_NUM]; 2349 s8 val_0p5_p[RTW89_BF_NUM]; 2350 u8 i; 2351 2352 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2353 ntx, RTW89_RS_OFDM, pri_ch); 2354 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2355 RTW89_CHANNEL_WIDTH_20, 2356 ntx, RTW89_RS_MCS, ch - 6); 2357 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2358 RTW89_CHANNEL_WIDTH_20, 2359 ntx, RTW89_RS_MCS, ch - 2); 2360 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 2361 RTW89_CHANNEL_WIDTH_20, 2362 ntx, RTW89_RS_MCS, ch + 2); 2363 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 2364 RTW89_CHANNEL_WIDTH_20, 2365 ntx, RTW89_RS_MCS, ch + 6); 2366 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2367 RTW89_CHANNEL_WIDTH_40, 2368 ntx, RTW89_RS_MCS, ch - 4); 2369 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 2370 RTW89_CHANNEL_WIDTH_40, 2371 ntx, RTW89_RS_MCS, ch + 4); 2372 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 2373 RTW89_CHANNEL_WIDTH_80, 2374 ntx, RTW89_RS_MCS, ch); 2375 2376 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 2377 ntx, RTW89_RS_MCS, ch - 4); 2378 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 2379 ntx, RTW89_RS_MCS, ch + 4); 2380 2381 for (i = 0; i < RTW89_BF_NUM; i++) 2382 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 2383 } 2384 2385 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev, 2386 struct rtw89_txpwr_limit_ax *lmt, 2387 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2388 { 2389 s8 val_0p5_n[RTW89_BF_NUM]; 2390 s8 val_0p5_p[RTW89_BF_NUM]; 2391 s8 val_2p5_n[RTW89_BF_NUM]; 2392 s8 val_2p5_p[RTW89_BF_NUM]; 2393 u8 i; 2394 2395 /* fill ofdm section */ 2396 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2397 ntx, RTW89_RS_OFDM, pri_ch); 2398 2399 /* fill mcs 20m section */ 2400 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2401 RTW89_CHANNEL_WIDTH_20, 2402 ntx, RTW89_RS_MCS, ch - 14); 2403 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2404 RTW89_CHANNEL_WIDTH_20, 2405 ntx, RTW89_RS_MCS, ch - 10); 2406 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 2407 RTW89_CHANNEL_WIDTH_20, 2408 ntx, RTW89_RS_MCS, ch - 6); 2409 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 2410 RTW89_CHANNEL_WIDTH_20, 2411 ntx, RTW89_RS_MCS, ch - 2); 2412 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 2413 RTW89_CHANNEL_WIDTH_20, 2414 ntx, RTW89_RS_MCS, ch + 2); 2415 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 2416 RTW89_CHANNEL_WIDTH_20, 2417 ntx, RTW89_RS_MCS, ch + 6); 2418 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 2419 RTW89_CHANNEL_WIDTH_20, 2420 ntx, RTW89_RS_MCS, ch + 10); 2421 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 2422 RTW89_CHANNEL_WIDTH_20, 2423 ntx, RTW89_RS_MCS, ch + 14); 2424 2425 /* fill mcs 40m section */ 2426 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2427 RTW89_CHANNEL_WIDTH_40, 2428 ntx, RTW89_RS_MCS, ch - 12); 2429 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 2430 RTW89_CHANNEL_WIDTH_40, 2431 ntx, RTW89_RS_MCS, ch - 4); 2432 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 2433 RTW89_CHANNEL_WIDTH_40, 2434 ntx, RTW89_RS_MCS, ch + 4); 2435 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 2436 RTW89_CHANNEL_WIDTH_40, 2437 ntx, RTW89_RS_MCS, ch + 12); 2438 2439 /* fill mcs 80m section */ 2440 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 2441 RTW89_CHANNEL_WIDTH_80, 2442 ntx, RTW89_RS_MCS, ch - 8); 2443 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 2444 RTW89_CHANNEL_WIDTH_80, 2445 ntx, RTW89_RS_MCS, ch + 8); 2446 2447 /* fill mcs 160m section */ 2448 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 2449 RTW89_CHANNEL_WIDTH_160, 2450 ntx, RTW89_RS_MCS, ch); 2451 2452 /* fill mcs 40m 0p5 section */ 2453 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 2454 ntx, RTW89_RS_MCS, ch - 4); 2455 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 2456 ntx, RTW89_RS_MCS, ch + 4); 2457 2458 for (i = 0; i < RTW89_BF_NUM; i++) 2459 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 2460 2461 /* fill mcs 40m 2p5 section */ 2462 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 2463 ntx, RTW89_RS_MCS, ch - 8); 2464 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 2465 ntx, RTW89_RS_MCS, ch + 8); 2466 2467 for (i = 0; i < RTW89_BF_NUM; i++) 2468 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 2469 } 2470 2471 static 2472 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev, 2473 const struct rtw89_chan *chan, 2474 struct rtw89_txpwr_limit_ax *lmt, 2475 u8 ntx) 2476 { 2477 u8 band = chan->band_type; 2478 u8 pri_ch = chan->primary_channel; 2479 u8 ch = chan->channel; 2480 u8 bw = chan->band_width; 2481 2482 memset(lmt, 0, sizeof(*lmt)); 2483 2484 switch (bw) { 2485 case RTW89_CHANNEL_WIDTH_20: 2486 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch); 2487 break; 2488 case RTW89_CHANNEL_WIDTH_40: 2489 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch, 2490 pri_ch); 2491 break; 2492 case RTW89_CHANNEL_WIDTH_80: 2493 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch, 2494 pri_ch); 2495 break; 2496 case RTW89_CHANNEL_WIDTH_160: 2497 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch, 2498 pri_ch); 2499 break; 2500 } 2501 } 2502 2503 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 2504 u8 ru, u8 ntx, u8 ch) 2505 { 2506 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 2507 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 2508 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 2509 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 2510 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 2511 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 2512 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 2513 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 2514 u8 regd = rtw89_regd_get(rtwdev, band); 2515 u8 reg6 = regulatory->reg_6ghz_power; 2516 s8 lmt_ru = 0, sar, offset; 2517 s8 cstr; 2518 2519 switch (band) { 2520 case RTW89_BAND_2G: 2521 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 2522 if (lmt_ru) 2523 break; 2524 2525 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 2526 break; 2527 case RTW89_BAND_5G: 2528 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 2529 if (lmt_ru) 2530 break; 2531 2532 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 2533 break; 2534 case RTW89_BAND_6G: 2535 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx]; 2536 if (lmt_ru) 2537 break; 2538 2539 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW] 2540 [RTW89_REG_6GHZ_POWER_DFLT] 2541 [ch_idx]; 2542 break; 2543 default: 2544 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 2545 return 0; 2546 } 2547 2548 offset = rtw89_phy_ant_gain_offset(rtwdev, band, freq); 2549 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt_ru + offset); 2550 sar = rtw89_query_sar(rtwdev, freq); 2551 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band); 2552 2553 return min3(lmt_ru, sar, cstr); 2554 } 2555 2556 static void 2557 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev, 2558 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2559 u8 band, u8 ntx, u8 ch) 2560 { 2561 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2562 RTW89_RU26, 2563 ntx, ch); 2564 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2565 RTW89_RU52, 2566 ntx, ch); 2567 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2568 RTW89_RU106, 2569 ntx, ch); 2570 } 2571 2572 static void 2573 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev, 2574 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2575 u8 band, u8 ntx, u8 ch) 2576 { 2577 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2578 RTW89_RU26, 2579 ntx, ch - 2); 2580 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2581 RTW89_RU26, 2582 ntx, ch + 2); 2583 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2584 RTW89_RU52, 2585 ntx, ch - 2); 2586 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2587 RTW89_RU52, 2588 ntx, ch + 2); 2589 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2590 RTW89_RU106, 2591 ntx, ch - 2); 2592 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2593 RTW89_RU106, 2594 ntx, ch + 2); 2595 } 2596 2597 static void 2598 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev, 2599 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2600 u8 band, u8 ntx, u8 ch) 2601 { 2602 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2603 RTW89_RU26, 2604 ntx, ch - 6); 2605 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2606 RTW89_RU26, 2607 ntx, ch - 2); 2608 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2609 RTW89_RU26, 2610 ntx, ch + 2); 2611 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2612 RTW89_RU26, 2613 ntx, ch + 6); 2614 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2615 RTW89_RU52, 2616 ntx, ch - 6); 2617 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2618 RTW89_RU52, 2619 ntx, ch - 2); 2620 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2621 RTW89_RU52, 2622 ntx, ch + 2); 2623 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2624 RTW89_RU52, 2625 ntx, ch + 6); 2626 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2627 RTW89_RU106, 2628 ntx, ch - 6); 2629 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2630 RTW89_RU106, 2631 ntx, ch - 2); 2632 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2633 RTW89_RU106, 2634 ntx, ch + 2); 2635 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2636 RTW89_RU106, 2637 ntx, ch + 6); 2638 } 2639 2640 static void 2641 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev, 2642 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2643 u8 band, u8 ntx, u8 ch) 2644 { 2645 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 2646 int i; 2647 2648 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX); 2649 for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) { 2650 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2651 RTW89_RU26, 2652 ntx, 2653 ch + ofst[i]); 2654 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2655 RTW89_RU52, 2656 ntx, 2657 ch + ofst[i]); 2658 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2659 RTW89_RU106, 2660 ntx, 2661 ch + ofst[i]); 2662 } 2663 } 2664 2665 static 2666 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2667 const struct rtw89_chan *chan, 2668 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2669 u8 ntx) 2670 { 2671 u8 band = chan->band_type; 2672 u8 ch = chan->channel; 2673 u8 bw = chan->band_width; 2674 2675 memset(lmt_ru, 0, sizeof(*lmt_ru)); 2676 2677 switch (bw) { 2678 case RTW89_CHANNEL_WIDTH_20: 2679 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx, 2680 ch); 2681 break; 2682 case RTW89_CHANNEL_WIDTH_40: 2683 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx, 2684 ch); 2685 break; 2686 case RTW89_CHANNEL_WIDTH_80: 2687 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx, 2688 ch); 2689 break; 2690 case RTW89_CHANNEL_WIDTH_160: 2691 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx, 2692 ch); 2693 break; 2694 } 2695 } 2696 2697 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev, 2698 const struct rtw89_chan *chan, 2699 enum rtw89_phy_idx phy_idx) 2700 { 2701 u8 max_nss_num = rtwdev->chip->rf_path_num; 2702 static const u8 rs[] = { 2703 RTW89_RS_CCK, 2704 RTW89_RS_OFDM, 2705 RTW89_RS_MCS, 2706 RTW89_RS_HEDCM, 2707 }; 2708 struct rtw89_rate_desc cur = {}; 2709 u8 band = chan->band_type; 2710 u8 ch = chan->channel; 2711 u32 addr, val; 2712 s8 v[4] = {}; 2713 u8 i; 2714 2715 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2716 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 2717 2718 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4); 2719 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4); 2720 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4); 2721 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4); 2722 2723 addr = R_AX_PWR_BY_RATE; 2724 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) { 2725 for (i = 0; i < ARRAY_SIZE(rs); i++) { 2726 if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]]) 2727 continue; 2728 2729 cur.rs = rs[i]; 2730 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]]; 2731 cur.idx++) { 2732 v[cur.idx % 4] = 2733 rtw89_phy_read_txpwr_byrate(rtwdev, 2734 band, 0, 2735 &cur); 2736 2737 if ((cur.idx + 1) % 4) 2738 continue; 2739 2740 val = FIELD_PREP(GENMASK(7, 0), v[0]) | 2741 FIELD_PREP(GENMASK(15, 8), v[1]) | 2742 FIELD_PREP(GENMASK(23, 16), v[2]) | 2743 FIELD_PREP(GENMASK(31, 24), v[3]); 2744 2745 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 2746 val); 2747 addr += 4; 2748 } 2749 } 2750 } 2751 } 2752 2753 static 2754 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev, 2755 const struct rtw89_chan *chan, 2756 enum rtw89_phy_idx phy_idx) 2757 { 2758 struct rtw89_rate_desc desc = { 2759 .nss = RTW89_NSS_1, 2760 .rs = RTW89_RS_OFFSET, 2761 }; 2762 u8 band = chan->band_type; 2763 s8 v[RTW89_RATE_OFFSET_NUM_AX] = {}; 2764 u32 val; 2765 2766 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 2767 2768 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_AX; desc.idx++) 2769 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc); 2770 2771 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM_AX != 5); 2772 val = FIELD_PREP(GENMASK(3, 0), v[0]) | 2773 FIELD_PREP(GENMASK(7, 4), v[1]) | 2774 FIELD_PREP(GENMASK(11, 8), v[2]) | 2775 FIELD_PREP(GENMASK(15, 12), v[3]) | 2776 FIELD_PREP(GENMASK(19, 16), v[4]); 2777 2778 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 2779 GENMASK(19, 0), val); 2780 } 2781 2782 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev, 2783 const struct rtw89_chan *chan, 2784 enum rtw89_phy_idx phy_idx) 2785 { 2786 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2787 struct rtw89_txpwr_limit_ax lmt; 2788 u8 ch = chan->channel; 2789 u8 bw = chan->band_width; 2790 const s8 *ptr; 2791 u32 addr, val; 2792 u8 i, j; 2793 2794 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2795 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 2796 2797 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ax) != 2798 RTW89_TXPWR_LMT_PAGE_SIZE_AX); 2799 2800 addr = R_AX_PWR_LMT; 2801 for (i = 0; i < max_ntx_num; i++) { 2802 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i); 2803 2804 ptr = (s8 *)&lmt; 2805 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_AX; 2806 j += 4, addr += 4, ptr += 4) { 2807 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2808 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2809 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2810 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2811 2812 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2813 } 2814 } 2815 } 2816 2817 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2818 const struct rtw89_chan *chan, 2819 enum rtw89_phy_idx phy_idx) 2820 { 2821 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2822 struct rtw89_txpwr_limit_ru_ax lmt_ru; 2823 u8 ch = chan->channel; 2824 u8 bw = chan->band_width; 2825 const s8 *ptr; 2826 u32 addr, val; 2827 u8 i, j; 2828 2829 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2830 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 2831 2832 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) != 2833 RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX); 2834 2835 addr = R_AX_PWR_RU_LMT; 2836 for (i = 0; i < max_ntx_num; i++) { 2837 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i); 2838 2839 ptr = (s8 *)&lmt_ru; 2840 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX; 2841 j += 4, addr += 4, ptr += 4) { 2842 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2843 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2844 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2845 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2846 2847 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2848 } 2849 } 2850 } 2851 2852 struct rtw89_phy_iter_ra_data { 2853 struct rtw89_dev *rtwdev; 2854 struct sk_buff *c2h; 2855 }; 2856 2857 static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link, 2858 struct ieee80211_link_sta *link_sta, 2859 struct rtw89_phy_iter_ra_data *ra_data) 2860 { 2861 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2862 const struct rtw89_c2h_ra_rpt *c2h = 2863 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data; 2864 struct rtw89_ra_report *ra_report = &rtwsta_link->ra_report; 2865 const struct rtw89_chip_info *chip = rtwdev->chip; 2866 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE; 2867 u8 mode, rate, bw, giltf, mac_id; 2868 u16 legacy_bitrate; 2869 bool valid; 2870 u8 mcs = 0; 2871 u8 t; 2872 2873 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID); 2874 if (mac_id != rtwsta_link->mac_id) 2875 return; 2876 2877 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS); 2878 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW); 2879 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF); 2880 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL); 2881 2882 if (format_v1) { 2883 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7); 2884 rate |= u8_encode_bits(t, BIT(7)); 2885 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2); 2886 bw |= u8_encode_bits(t, BIT(2)); 2887 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2); 2888 mode |= u8_encode_bits(t, BIT(2)); 2889 } 2890 2891 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2892 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2893 if (!valid) 2894 return; 2895 } 2896 2897 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2898 2899 switch (mode) { 2900 case RTW89_RA_RPT_MODE_LEGACY: 2901 ra_report->txrate.legacy = legacy_bitrate; 2902 break; 2903 case RTW89_RA_RPT_MODE_HT: 2904 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2905 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2906 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2907 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2908 else 2909 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2910 ra_report->txrate.mcs = rate; 2911 if (giltf) 2912 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2913 mcs = ra_report->txrate.mcs & 0x07; 2914 break; 2915 case RTW89_RA_RPT_MODE_VHT: 2916 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2917 ra_report->txrate.mcs = format_v1 ? 2918 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2919 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2920 ra_report->txrate.nss = format_v1 ? 2921 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2922 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2923 if (giltf) 2924 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2925 mcs = ra_report->txrate.mcs; 2926 break; 2927 case RTW89_RA_RPT_MODE_HE: 2928 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2929 ra_report->txrate.mcs = format_v1 ? 2930 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2931 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2932 ra_report->txrate.nss = format_v1 ? 2933 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2934 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2935 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2936 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2937 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2938 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2939 else 2940 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2941 mcs = ra_report->txrate.mcs; 2942 break; 2943 case RTW89_RA_RPT_MODE_EHT: 2944 ra_report->txrate.flags |= RATE_INFO_FLAGS_EHT_MCS; 2945 ra_report->txrate.mcs = u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1); 2946 ra_report->txrate.nss = u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1; 2947 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2948 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_0_8; 2949 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2950 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_1_6; 2951 else 2952 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_3_2; 2953 mcs = ra_report->txrate.mcs; 2954 break; 2955 } 2956 2957 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2958 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2959 ra_report->hw_rate = format_v1 ? 2960 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) | 2961 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) : 2962 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) | 2963 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL); 2964 ra_report->might_fallback_legacy = mcs <= 2; 2965 link_sta->agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2966 rtwsta_link->max_agg_wait = link_sta->agg.max_rc_amsdu_len / 1500 - 1; 2967 } 2968 2969 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 2970 { 2971 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 2972 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 2973 struct rtw89_sta_link *rtwsta_link; 2974 struct ieee80211_link_sta *link_sta; 2975 unsigned int link_id; 2976 2977 rcu_read_lock(); 2978 2979 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 2980 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 2981 __rtw89_phy_c2h_ra_rpt_iter(rtwsta_link, link_sta, ra_data); 2982 } 2983 2984 rcu_read_unlock(); 2985 } 2986 2987 static void 2988 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2989 { 2990 struct rtw89_phy_iter_ra_data ra_data; 2991 2992 ra_data.rtwdev = rtwdev; 2993 ra_data.c2h = c2h; 2994 ieee80211_iterate_stations_atomic(rtwdev->hw, 2995 rtw89_phy_c2h_ra_rpt_iter, 2996 &ra_data); 2997 } 2998 2999 static 3000 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 3001 struct sk_buff *c2h, u32 len) = { 3002 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 3003 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 3004 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 3005 }; 3006 3007 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, 3008 enum rtw89_phy_c2h_rfk_log_func func, 3009 void *content, u16 len) 3010 { 3011 struct rtw89_c2h_rf_txgapk_rpt_log *txgapk; 3012 struct rtw89_c2h_rf_rxdck_rpt_log *rxdck; 3013 struct rtw89_c2h_rf_dack_rpt_log *dack; 3014 struct rtw89_c2h_rf_tssi_rpt_log *tssi; 3015 struct rtw89_c2h_rf_dpk_rpt_log *dpk; 3016 struct rtw89_c2h_rf_iqk_rpt_log *iqk; 3017 int i, j, k; 3018 3019 switch (func) { 3020 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK: 3021 if (len != sizeof(*iqk)) 3022 goto out; 3023 3024 iqk = content; 3025 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3026 "[IQK] iqk->is_iqk_init = %x\n", iqk->is_iqk_init); 3027 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3028 "[IQK] iqk->is_reload = %x\n", iqk->is_reload); 3029 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3030 "[IQK] iqk->is_nbiqk = %x\n", iqk->is_nbiqk); 3031 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3032 "[IQK] iqk->txiqk_en = %x\n", iqk->txiqk_en); 3033 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3034 "[IQK] iqk->rxiqk_en = %x\n", iqk->rxiqk_en); 3035 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3036 "[IQK] iqk->lok_en = %x\n", iqk->lok_en); 3037 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3038 "[IQK] iqk->iqk_xym_en = %x\n", iqk->iqk_xym_en); 3039 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3040 "[IQK] iqk->iqk_sram_en = %x\n", iqk->iqk_sram_en); 3041 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3042 "[IQK] iqk->iqk_fft_en = %x\n", iqk->iqk_fft_en); 3043 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3044 "[IQK] iqk->is_fw_iqk = %x\n", iqk->is_fw_iqk); 3045 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3046 "[IQK] iqk->is_iqk_enable = %x\n", iqk->is_iqk_enable); 3047 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3048 "[IQK] iqk->iqk_cfir_en = %x\n", iqk->iqk_cfir_en); 3049 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3050 "[IQK] iqk->thermal_rek_en = %x\n", iqk->thermal_rek_en); 3051 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3052 "[IQK] iqk->version = %x\n", iqk->version); 3053 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3054 "[IQK] iqk->phy = %x\n", iqk->phy); 3055 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3056 "[IQK] iqk->fwk_status = %x\n", iqk->fwk_status); 3057 3058 for (i = 0; i < 2; i++) { 3059 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3060 "[IQK] ======== Path %x ========\n", i); 3061 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_band[%d] = %x\n", 3062 i, iqk->iqk_band[i]); 3063 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_ch[%d] = %x\n", 3064 i, iqk->iqk_ch[i]); 3065 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_bw[%d] = %x\n", 3066 i, iqk->iqk_bw[i]); 3067 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_idac[%d] = %x\n", 3068 i, le32_to_cpu(iqk->lok_idac[i])); 3069 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_vbuf[%d] = %x\n", 3070 i, le32_to_cpu(iqk->lok_vbuf[i])); 3071 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_tx_fail[%d] = %x\n", 3072 i, iqk->iqk_tx_fail[i]); 3073 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_rx_fail[%d] = %x\n", 3074 i, iqk->iqk_rx_fail[i]); 3075 for (j = 0; j < 4; j++) 3076 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3077 "[IQK] iqk->rftxgain[%d][%d] = %x\n", 3078 i, j, le32_to_cpu(iqk->rftxgain[i][j])); 3079 for (j = 0; j < 4; j++) 3080 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3081 "[IQK] iqk->tx_xym[%d][%d] = %x\n", 3082 i, j, le32_to_cpu(iqk->tx_xym[i][j])); 3083 for (j = 0; j < 4; j++) 3084 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3085 "[IQK] iqk->rfrxgain[%d][%d] = %x\n", 3086 i, j, le32_to_cpu(iqk->rfrxgain[i][j])); 3087 for (j = 0; j < 4; j++) 3088 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3089 "[IQK] iqk->rx_xym[%d][%d] = %x\n", 3090 i, j, le32_to_cpu(iqk->rx_xym[i][j])); 3091 } 3092 return; 3093 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: 3094 if (len != sizeof(*dpk)) 3095 goto out; 3096 3097 dpk = content; 3098 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3099 "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n", 3100 dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok); 3101 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3102 "DPK txagc:%2ph ther:%2ph gs:%2ph dc_i:%4ph dc_q:%4ph\n", 3103 dpk->txagc, dpk->ther, dpk->gs, dpk->dc_i, dpk->dc_q); 3104 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3105 "DPK corr_v:%2ph corr_i:%2ph to:%2ph ov:%2ph\n", 3106 dpk->corr_val, dpk->corr_idx, dpk->is_timeout, dpk->rxbb_ov); 3107 return; 3108 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK: 3109 if (len != sizeof(*dack)) 3110 goto out; 3111 3112 dack = content; 3113 3114 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]FWDACK SUMMARY!!!!!\n"); 3115 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3116 "[DACK]FWDACK ver = 0x%x, FWDACK rpt_ver = 0x%x, driver rpt_ver = 0x%x\n", 3117 dack->fwdack_ver, dack->fwdack_info_ver, 0x2); 3118 3119 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3120 "[DACK]timeout code = [0x%x 0x%x 0x%x 0x%x 0x%x]\n", 3121 dack->addck_timeout, dack->cdack_timeout, dack->dadck_timeout, 3122 dack->adgaink_timeout, dack->msbk_timeout); 3123 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3124 "[DACK]DACK fail = 0x%x\n", dack->dack_fail); 3125 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3126 "[DACK]S0 WBADCK = [0x%x]\n", dack->wbdck_d[0]); 3127 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3128 "[DACK]S1 WBADCK = [0x%x]\n", dack->wbdck_d[1]); 3129 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3130 "[DACK]DRCK = [0x%x]\n", dack->rck_d); 3131 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK ic = [0x%x, 0x%x]\n", 3132 dack->cdack_d[0][0][0], dack->cdack_d[0][0][1]); 3133 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK qc = [0x%x, 0x%x]\n", 3134 dack->cdack_d[0][1][0], dack->cdack_d[0][1][1]); 3135 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK ic = [0x%x, 0x%x]\n", 3136 dack->cdack_d[1][0][0], dack->cdack_d[1][0][1]); 3137 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK qc = [0x%x, 0x%x]\n", 3138 dack->cdack_d[1][1][0], dack->cdack_d[1][1][1]); 3139 3140 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = [0x%x, 0x%x]\n", 3141 ((u32)dack->addck2_hd[0][0][0] << 8) | dack->addck2_ld[0][0][0], 3142 ((u32)dack->addck2_hd[0][0][1] << 8) | dack->addck2_ld[0][0][1]); 3143 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK qc = [0x%x, 0x%x]\n", 3144 ((u32)dack->addck2_hd[0][1][0] << 8) | dack->addck2_ld[0][1][0], 3145 ((u32)dack->addck2_hd[0][1][1] << 8) | dack->addck2_ld[0][1][1]); 3146 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK ic = [0x%x, 0x%x]\n", 3147 ((u32)dack->addck2_hd[1][0][0] << 8) | dack->addck2_ld[1][0][0], 3148 ((u32)dack->addck2_hd[1][0][1] << 8) | dack->addck2_ld[1][0][1]); 3149 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK qc = [0x%x, 0x%x]\n", 3150 ((u32)dack->addck2_hd[1][1][0] << 8) | dack->addck2_ld[1][1][0], 3151 ((u32)dack->addck2_hd[1][1][1] << 8) | dack->addck2_ld[1][1][1]); 3152 3153 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_GAINK ic = 0x%x, qc = 0x%x\n", 3154 dack->adgaink_d[0][0], dack->adgaink_d[0][1]); 3155 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_GAINK ic = 0x%x, qc = 0x%x\n", 3156 dack->adgaink_d[1][0], dack->adgaink_d[1][1]); 3157 3158 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n", 3159 dack->dadck_d[0][0], dack->dadck_d[0][1]); 3160 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n", 3161 dack->dadck_d[1][0], dack->dadck_d[1][1]); 3162 3163 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask iqc = 0x%x\n", 3164 ((u32)dack->biask_hd[0][0] << 8) | dack->biask_ld[0][0]); 3165 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 biask iqc = 0x%x\n", 3166 ((u32)dack->biask_hd[1][0] << 8) | dack->biask_ld[1][0]); 3167 3168 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n"); 3169 for (i = 0; i < 0x10; i++) 3170 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", 3171 dack->msbk_d[0][0][i]); 3172 3173 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n"); 3174 for (i = 0; i < 0x10; i++) 3175 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", 3176 dack->msbk_d[0][1][i]); 3177 3178 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n"); 3179 for (i = 0; i < 0x10; i++) 3180 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", 3181 dack->msbk_d[1][0][i]); 3182 3183 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n"); 3184 for (i = 0; i < 0x10; i++) 3185 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", 3186 dack->msbk_d[1][1][i]); 3187 return; 3188 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: 3189 if (len != sizeof(*rxdck)) 3190 goto out; 3191 3192 rxdck = content; 3193 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3194 "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n", 3195 rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch, 3196 rxdck->timeout); 3197 return; 3198 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI: 3199 if (len != sizeof(*tssi)) 3200 goto out; 3201 3202 tssi = content; 3203 for (i = 0; i < 2; i++) { 3204 for (j = 0; j < 2; j++) { 3205 for (k = 0; k < 4; k++) { 3206 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3207 "[TSSI] alignment_power_cw_h[%d][%d][%d]=%d\n", 3208 i, j, k, tssi->alignment_power_cw_h[i][j][k]); 3209 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3210 "[TSSI] alignment_power_cw_l[%d][%d][%d]=%d\n", 3211 i, j, k, tssi->alignment_power_cw_l[i][j][k]); 3212 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3213 "[TSSI] alignment_power[%d][%d][%d]=%d\n", 3214 i, j, k, tssi->alignment_power[i][j][k]); 3215 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3216 "[TSSI] alignment_power_cw[%d][%d][%d]=%d\n", 3217 i, j, k, 3218 (tssi->alignment_power_cw_h[i][j][k] << 8) + 3219 tssi->alignment_power_cw_l[i][j][k]); 3220 } 3221 3222 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3223 "[TSSI] tssi_alimk_state[%d][%d]=%d\n", 3224 i, j, tssi->tssi_alimk_state[i][j]); 3225 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3226 "[TSSI] default_txagc_offset[%d]=%d\n", 3227 j, tssi->default_txagc_offset[0][j]); 3228 } 3229 } 3230 return; 3231 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: 3232 if (len != sizeof(*txgapk)) 3233 goto out; 3234 3235 txgapk = content; 3236 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3237 "[TXGAPK]rpt r0x8010[0]=0x%x, r0x8010[1]=0x%x\n", 3238 le32_to_cpu(txgapk->r0x8010[0]), 3239 le32_to_cpu(txgapk->r0x8010[1])); 3240 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_id = %d\n", 3241 txgapk->chk_id); 3242 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_cnt = %d\n", 3243 le32_to_cpu(txgapk->chk_cnt)); 3244 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n", 3245 txgapk->ver); 3246 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n", 3247 txgapk->rsv1); 3248 3249 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n", 3250 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]); 3251 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[0] = %*ph\n", 3252 (int)sizeof(txgapk->power_d[0]), txgapk->power_d[0]); 3253 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[1] = %*ph\n", 3254 (int)sizeof(txgapk->track_d[1]), txgapk->track_d[1]); 3255 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n", 3256 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]); 3257 return; 3258 default: 3259 break; 3260 } 3261 3262 out: 3263 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3264 "unexpected RFK func %d report log with length %d\n", func, len); 3265 } 3266 3267 static bool rtw89_phy_c2h_rfk_run_log(struct rtw89_dev *rtwdev, 3268 enum rtw89_phy_c2h_rfk_log_func func, 3269 void *content, u16 len) 3270 { 3271 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 3272 const struct rtw89_c2h_rf_run_log *log = content; 3273 const struct rtw89_fw_element_hdr *elm; 3274 u32 fmt_idx; 3275 u16 offset; 3276 3277 if (sizeof(*log) != len) 3278 return false; 3279 3280 if (!elm_info->rfk_log_fmt) 3281 return false; 3282 3283 elm = elm_info->rfk_log_fmt->elm[func]; 3284 fmt_idx = le32_to_cpu(log->fmt_idx); 3285 if (!elm || fmt_idx >= elm->u.rfk_log_fmt.nr) 3286 return false; 3287 3288 offset = le16_to_cpu(elm->u.rfk_log_fmt.offset[fmt_idx]); 3289 if (offset == 0) 3290 return false; 3291 3292 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset], 3293 le32_to_cpu(log->arg[0]), le32_to_cpu(log->arg[1]), 3294 le32_to_cpu(log->arg[2]), le32_to_cpu(log->arg[3])); 3295 3296 return true; 3297 } 3298 3299 static void rtw89_phy_c2h_rfk_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 3300 u32 len, enum rtw89_phy_c2h_rfk_log_func func, 3301 const char *rfk_name) 3302 { 3303 struct rtw89_c2h_hdr *c2h_hdr = (struct rtw89_c2h_hdr *)c2h->data; 3304 struct rtw89_c2h_rf_log_hdr *log_hdr; 3305 void *log_ptr = c2h_hdr; 3306 u16 content_len; 3307 u16 chunk_len; 3308 bool handled; 3309 3310 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK)) 3311 return; 3312 3313 log_ptr += sizeof(*c2h_hdr); 3314 len -= sizeof(*c2h_hdr); 3315 3316 while (len > sizeof(*log_hdr)) { 3317 log_hdr = log_ptr; 3318 content_len = le16_to_cpu(log_hdr->len); 3319 chunk_len = content_len + sizeof(*log_hdr); 3320 3321 if (chunk_len > len) 3322 break; 3323 3324 switch (log_hdr->type) { 3325 case RTW89_RF_RUN_LOG: 3326 handled = rtw89_phy_c2h_rfk_run_log(rtwdev, func, 3327 log_hdr->content, content_len); 3328 if (handled) 3329 break; 3330 3331 rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s run: %*ph\n", 3332 rfk_name, content_len, log_hdr->content); 3333 break; 3334 case RTW89_RF_RPT_LOG: 3335 rtw89_phy_c2h_rfk_rpt_log(rtwdev, func, 3336 log_hdr->content, content_len); 3337 break; 3338 default: 3339 return; 3340 } 3341 3342 log_ptr += chunk_len; 3343 len -= chunk_len; 3344 } 3345 } 3346 3347 static void 3348 rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3349 { 3350 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3351 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK, "IQK"); 3352 } 3353 3354 static void 3355 rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3356 { 3357 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3358 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK, "DPK"); 3359 } 3360 3361 static void 3362 rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3363 { 3364 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3365 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK, "DACK"); 3366 } 3367 3368 static void 3369 rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3370 { 3371 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3372 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK, "RX_DCK"); 3373 } 3374 3375 static void 3376 rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3377 { 3378 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3379 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI, "TSSI"); 3380 } 3381 3382 static void 3383 rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3384 { 3385 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3386 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK, "TXGAPK"); 3387 } 3388 3389 static 3390 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev, 3391 struct sk_buff *c2h, u32 len) = { 3392 [RTW89_PHY_C2H_RFK_LOG_FUNC_IQK] = rtw89_phy_c2h_rfk_log_iqk, 3393 [RTW89_PHY_C2H_RFK_LOG_FUNC_DPK] = rtw89_phy_c2h_rfk_log_dpk, 3394 [RTW89_PHY_C2H_RFK_LOG_FUNC_DACK] = rtw89_phy_c2h_rfk_log_dack, 3395 [RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK] = rtw89_phy_c2h_rfk_log_rxdck, 3396 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi, 3397 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk, 3398 }; 3399 3400 static 3401 void rtw89_phy_rfk_report_prep(struct rtw89_dev *rtwdev) 3402 { 3403 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 3404 3405 wait->state = RTW89_RFK_STATE_START; 3406 wait->start_time = ktime_get(); 3407 reinit_completion(&wait->completion); 3408 } 3409 3410 static 3411 int rtw89_phy_rfk_report_wait(struct rtw89_dev *rtwdev, const char *rfk_name, 3412 unsigned int ms) 3413 { 3414 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 3415 unsigned long time_left; 3416 3417 /* Since we can't receive C2H event during SER, use a fixed delay. */ 3418 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) { 3419 fsleep(1000 * ms / 2); 3420 goto out; 3421 } 3422 3423 time_left = wait_for_completion_timeout(&wait->completion, 3424 msecs_to_jiffies(ms)); 3425 if (time_left == 0) { 3426 rtw89_warn(rtwdev, "failed to wait RF %s\n", rfk_name); 3427 return -ETIMEDOUT; 3428 } else if (wait->state != RTW89_RFK_STATE_OK) { 3429 rtw89_warn(rtwdev, "failed to do RF %s result from state %d\n", 3430 rfk_name, wait->state); 3431 return -EFAULT; 3432 } 3433 3434 out: 3435 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %lld ms to complete\n", 3436 rfk_name, ktime_ms_delta(ktime_get(), wait->start_time)); 3437 3438 return 0; 3439 } 3440 3441 static void 3442 rtw89_phy_c2h_rfk_report_state(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3443 { 3444 const struct rtw89_c2h_rfk_report *report = 3445 (const struct rtw89_c2h_rfk_report *)c2h->data; 3446 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 3447 3448 wait->state = report->state; 3449 wait->version = report->version; 3450 3451 complete(&wait->completion); 3452 3453 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3454 "RFK report state %d with version %d (%*ph)\n", 3455 wait->state, wait->version, 3456 (int)(len - sizeof(report->hdr)), &report->state); 3457 } 3458 3459 static void 3460 rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3461 { 3462 } 3463 3464 static 3465 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev, 3466 struct sk_buff *c2h, u32 len) = { 3467 [RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE] = rtw89_phy_c2h_rfk_report_state, 3468 [RTW89_PHY_C2H_RFK_LOG_TAS_PWR] = rtw89_phy_c2h_rfk_log_tas_pwr, 3469 }; 3470 3471 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 3472 { 3473 switch (class) { 3474 case RTW89_PHY_C2H_RFK_LOG: 3475 switch (func) { 3476 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK: 3477 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: 3478 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK: 3479 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: 3480 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI: 3481 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: 3482 return true; 3483 default: 3484 return false; 3485 } 3486 case RTW89_PHY_C2H_RFK_REPORT: 3487 switch (func) { 3488 case RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE: 3489 return true; 3490 default: 3491 return false; 3492 } 3493 default: 3494 return false; 3495 } 3496 } 3497 3498 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3499 u32 len, u8 class, u8 func) 3500 { 3501 void (*handler)(struct rtw89_dev *rtwdev, 3502 struct sk_buff *c2h, u32 len) = NULL; 3503 3504 switch (class) { 3505 case RTW89_PHY_C2H_CLASS_RA: 3506 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 3507 handler = rtw89_phy_c2h_ra_handler[func]; 3508 break; 3509 case RTW89_PHY_C2H_RFK_LOG: 3510 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_log_handler)) 3511 handler = rtw89_phy_c2h_rfk_log_handler[func]; 3512 break; 3513 case RTW89_PHY_C2H_RFK_REPORT: 3514 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_report_handler)) 3515 handler = rtw89_phy_c2h_rfk_report_handler[func]; 3516 break; 3517 case RTW89_PHY_C2H_CLASS_DM: 3518 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY) 3519 return; 3520 fallthrough; 3521 default: 3522 rtw89_info(rtwdev, "PHY c2h class %d not support\n", class); 3523 return; 3524 } 3525 if (!handler) { 3526 rtw89_info(rtwdev, "PHY c2h class %d func %d not support\n", class, 3527 func); 3528 return; 3529 } 3530 handler(rtwdev, skb, len); 3531 } 3532 3533 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev, 3534 enum rtw89_phy_idx phy_idx, 3535 unsigned int ms) 3536 { 3537 int ret; 3538 3539 rtw89_phy_rfk_report_prep(rtwdev); 3540 3541 ret = rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx); 3542 if (ret) 3543 return ret; 3544 3545 return rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms); 3546 } 3547 EXPORT_SYMBOL(rtw89_phy_rfk_pre_ntfy_and_wait); 3548 3549 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev, 3550 enum rtw89_phy_idx phy_idx, 3551 const struct rtw89_chan *chan, 3552 enum rtw89_tssi_mode tssi_mode, 3553 unsigned int ms) 3554 { 3555 int ret; 3556 3557 rtw89_phy_rfk_report_prep(rtwdev); 3558 3559 ret = rtw89_fw_h2c_rf_tssi(rtwdev, phy_idx, chan, tssi_mode); 3560 if (ret) 3561 return ret; 3562 3563 return rtw89_phy_rfk_report_wait(rtwdev, "TSSI", ms); 3564 } 3565 EXPORT_SYMBOL(rtw89_phy_rfk_tssi_and_wait); 3566 3567 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev, 3568 enum rtw89_phy_idx phy_idx, 3569 const struct rtw89_chan *chan, 3570 unsigned int ms) 3571 { 3572 int ret; 3573 3574 rtw89_phy_rfk_report_prep(rtwdev); 3575 3576 ret = rtw89_fw_h2c_rf_iqk(rtwdev, phy_idx, chan); 3577 if (ret) 3578 return ret; 3579 3580 return rtw89_phy_rfk_report_wait(rtwdev, "IQK", ms); 3581 } 3582 EXPORT_SYMBOL(rtw89_phy_rfk_iqk_and_wait); 3583 3584 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev, 3585 enum rtw89_phy_idx phy_idx, 3586 const struct rtw89_chan *chan, 3587 unsigned int ms) 3588 { 3589 int ret; 3590 3591 rtw89_phy_rfk_report_prep(rtwdev); 3592 3593 ret = rtw89_fw_h2c_rf_dpk(rtwdev, phy_idx, chan); 3594 if (ret) 3595 return ret; 3596 3597 return rtw89_phy_rfk_report_wait(rtwdev, "DPK", ms); 3598 } 3599 EXPORT_SYMBOL(rtw89_phy_rfk_dpk_and_wait); 3600 3601 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev, 3602 enum rtw89_phy_idx phy_idx, 3603 const struct rtw89_chan *chan, 3604 unsigned int ms) 3605 { 3606 int ret; 3607 3608 rtw89_phy_rfk_report_prep(rtwdev); 3609 3610 ret = rtw89_fw_h2c_rf_txgapk(rtwdev, phy_idx, chan); 3611 if (ret) 3612 return ret; 3613 3614 return rtw89_phy_rfk_report_wait(rtwdev, "TXGAPK", ms); 3615 } 3616 EXPORT_SYMBOL(rtw89_phy_rfk_txgapk_and_wait); 3617 3618 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev, 3619 enum rtw89_phy_idx phy_idx, 3620 const struct rtw89_chan *chan, 3621 unsigned int ms) 3622 { 3623 int ret; 3624 3625 rtw89_phy_rfk_report_prep(rtwdev); 3626 3627 ret = rtw89_fw_h2c_rf_dack(rtwdev, phy_idx, chan); 3628 if (ret) 3629 return ret; 3630 3631 return rtw89_phy_rfk_report_wait(rtwdev, "DACK", ms); 3632 } 3633 EXPORT_SYMBOL(rtw89_phy_rfk_dack_and_wait); 3634 3635 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev, 3636 enum rtw89_phy_idx phy_idx, 3637 const struct rtw89_chan *chan, 3638 bool is_chl_k, unsigned int ms) 3639 { 3640 int ret; 3641 3642 rtw89_phy_rfk_report_prep(rtwdev); 3643 3644 ret = rtw89_fw_h2c_rf_rxdck(rtwdev, phy_idx, chan, is_chl_k); 3645 if (ret) 3646 return ret; 3647 3648 return rtw89_phy_rfk_report_wait(rtwdev, "RX_DCK", ms); 3649 } 3650 EXPORT_SYMBOL(rtw89_phy_rfk_rxdck_and_wait); 3651 3652 static u32 phy_tssi_get_cck_group(u8 ch) 3653 { 3654 switch (ch) { 3655 case 1 ... 2: 3656 return 0; 3657 case 3 ... 5: 3658 return 1; 3659 case 6 ... 8: 3660 return 2; 3661 case 9 ... 11: 3662 return 3; 3663 case 12 ... 13: 3664 return 4; 3665 case 14: 3666 return 5; 3667 } 3668 3669 return 0; 3670 } 3671 3672 #define PHY_TSSI_EXTRA_GROUP_BIT BIT(31) 3673 #define PHY_TSSI_EXTRA_GROUP(idx) (PHY_TSSI_EXTRA_GROUP_BIT | (idx)) 3674 #define PHY_IS_TSSI_EXTRA_GROUP(group) ((group) & PHY_TSSI_EXTRA_GROUP_BIT) 3675 #define PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) \ 3676 ((group) & ~PHY_TSSI_EXTRA_GROUP_BIT) 3677 #define PHY_TSSI_EXTRA_GET_GROUP_IDX2(group) \ 3678 (PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) + 1) 3679 3680 static u32 phy_tssi_get_ofdm_group(u8 ch) 3681 { 3682 switch (ch) { 3683 case 1 ... 2: 3684 return 0; 3685 case 3 ... 5: 3686 return 1; 3687 case 6 ... 8: 3688 return 2; 3689 case 9 ... 11: 3690 return 3; 3691 case 12 ... 14: 3692 return 4; 3693 case 36 ... 40: 3694 return 5; 3695 case 41 ... 43: 3696 return PHY_TSSI_EXTRA_GROUP(5); 3697 case 44 ... 48: 3698 return 6; 3699 case 49 ... 51: 3700 return PHY_TSSI_EXTRA_GROUP(6); 3701 case 52 ... 56: 3702 return 7; 3703 case 57 ... 59: 3704 return PHY_TSSI_EXTRA_GROUP(7); 3705 case 60 ... 64: 3706 return 8; 3707 case 100 ... 104: 3708 return 9; 3709 case 105 ... 107: 3710 return PHY_TSSI_EXTRA_GROUP(9); 3711 case 108 ... 112: 3712 return 10; 3713 case 113 ... 115: 3714 return PHY_TSSI_EXTRA_GROUP(10); 3715 case 116 ... 120: 3716 return 11; 3717 case 121 ... 123: 3718 return PHY_TSSI_EXTRA_GROUP(11); 3719 case 124 ... 128: 3720 return 12; 3721 case 129 ... 131: 3722 return PHY_TSSI_EXTRA_GROUP(12); 3723 case 132 ... 136: 3724 return 13; 3725 case 137 ... 139: 3726 return PHY_TSSI_EXTRA_GROUP(13); 3727 case 140 ... 144: 3728 return 14; 3729 case 149 ... 153: 3730 return 15; 3731 case 154 ... 156: 3732 return PHY_TSSI_EXTRA_GROUP(15); 3733 case 157 ... 161: 3734 return 16; 3735 case 162 ... 164: 3736 return PHY_TSSI_EXTRA_GROUP(16); 3737 case 165 ... 169: 3738 return 17; 3739 case 170 ... 172: 3740 return PHY_TSSI_EXTRA_GROUP(17); 3741 case 173 ... 177: 3742 return 18; 3743 } 3744 3745 return 0; 3746 } 3747 3748 static u32 phy_tssi_get_6g_ofdm_group(u8 ch) 3749 { 3750 switch (ch) { 3751 case 1 ... 5: 3752 return 0; 3753 case 6 ... 8: 3754 return PHY_TSSI_EXTRA_GROUP(0); 3755 case 9 ... 13: 3756 return 1; 3757 case 14 ... 16: 3758 return PHY_TSSI_EXTRA_GROUP(1); 3759 case 17 ... 21: 3760 return 2; 3761 case 22 ... 24: 3762 return PHY_TSSI_EXTRA_GROUP(2); 3763 case 25 ... 29: 3764 return 3; 3765 case 33 ... 37: 3766 return 4; 3767 case 38 ... 40: 3768 return PHY_TSSI_EXTRA_GROUP(4); 3769 case 41 ... 45: 3770 return 5; 3771 case 46 ... 48: 3772 return PHY_TSSI_EXTRA_GROUP(5); 3773 case 49 ... 53: 3774 return 6; 3775 case 54 ... 56: 3776 return PHY_TSSI_EXTRA_GROUP(6); 3777 case 57 ... 61: 3778 return 7; 3779 case 65 ... 69: 3780 return 8; 3781 case 70 ... 72: 3782 return PHY_TSSI_EXTRA_GROUP(8); 3783 case 73 ... 77: 3784 return 9; 3785 case 78 ... 80: 3786 return PHY_TSSI_EXTRA_GROUP(9); 3787 case 81 ... 85: 3788 return 10; 3789 case 86 ... 88: 3790 return PHY_TSSI_EXTRA_GROUP(10); 3791 case 89 ... 93: 3792 return 11; 3793 case 97 ... 101: 3794 return 12; 3795 case 102 ... 104: 3796 return PHY_TSSI_EXTRA_GROUP(12); 3797 case 105 ... 109: 3798 return 13; 3799 case 110 ... 112: 3800 return PHY_TSSI_EXTRA_GROUP(13); 3801 case 113 ... 117: 3802 return 14; 3803 case 118 ... 120: 3804 return PHY_TSSI_EXTRA_GROUP(14); 3805 case 121 ... 125: 3806 return 15; 3807 case 129 ... 133: 3808 return 16; 3809 case 134 ... 136: 3810 return PHY_TSSI_EXTRA_GROUP(16); 3811 case 137 ... 141: 3812 return 17; 3813 case 142 ... 144: 3814 return PHY_TSSI_EXTRA_GROUP(17); 3815 case 145 ... 149: 3816 return 18; 3817 case 150 ... 152: 3818 return PHY_TSSI_EXTRA_GROUP(18); 3819 case 153 ... 157: 3820 return 19; 3821 case 161 ... 165: 3822 return 20; 3823 case 166 ... 168: 3824 return PHY_TSSI_EXTRA_GROUP(20); 3825 case 169 ... 173: 3826 return 21; 3827 case 174 ... 176: 3828 return PHY_TSSI_EXTRA_GROUP(21); 3829 case 177 ... 181: 3830 return 22; 3831 case 182 ... 184: 3832 return PHY_TSSI_EXTRA_GROUP(22); 3833 case 185 ... 189: 3834 return 23; 3835 case 193 ... 197: 3836 return 24; 3837 case 198 ... 200: 3838 return PHY_TSSI_EXTRA_GROUP(24); 3839 case 201 ... 205: 3840 return 25; 3841 case 206 ... 208: 3842 return PHY_TSSI_EXTRA_GROUP(25); 3843 case 209 ... 213: 3844 return 26; 3845 case 214 ... 216: 3846 return PHY_TSSI_EXTRA_GROUP(26); 3847 case 217 ... 221: 3848 return 27; 3849 case 225 ... 229: 3850 return 28; 3851 case 230 ... 232: 3852 return PHY_TSSI_EXTRA_GROUP(28); 3853 case 233 ... 237: 3854 return 29; 3855 case 238 ... 240: 3856 return PHY_TSSI_EXTRA_GROUP(29); 3857 case 241 ... 245: 3858 return 30; 3859 case 246 ... 248: 3860 return PHY_TSSI_EXTRA_GROUP(30); 3861 case 249 ... 253: 3862 return 31; 3863 } 3864 3865 return 0; 3866 } 3867 3868 static u32 phy_tssi_get_trim_group(u8 ch) 3869 { 3870 switch (ch) { 3871 case 1 ... 8: 3872 return 0; 3873 case 9 ... 14: 3874 return 1; 3875 case 36 ... 48: 3876 return 2; 3877 case 49 ... 51: 3878 return PHY_TSSI_EXTRA_GROUP(2); 3879 case 52 ... 64: 3880 return 3; 3881 case 100 ... 112: 3882 return 4; 3883 case 113 ... 115: 3884 return PHY_TSSI_EXTRA_GROUP(4); 3885 case 116 ... 128: 3886 return 5; 3887 case 132 ... 144: 3888 return 6; 3889 case 149 ... 177: 3890 return 7; 3891 } 3892 3893 return 0; 3894 } 3895 3896 static u32 phy_tssi_get_6g_trim_group(u8 ch) 3897 { 3898 switch (ch) { 3899 case 1 ... 13: 3900 return 0; 3901 case 14 ... 16: 3902 return PHY_TSSI_EXTRA_GROUP(0); 3903 case 17 ... 29: 3904 return 1; 3905 case 33 ... 45: 3906 return 2; 3907 case 46 ... 48: 3908 return PHY_TSSI_EXTRA_GROUP(2); 3909 case 49 ... 61: 3910 return 3; 3911 case 65 ... 77: 3912 return 4; 3913 case 78 ... 80: 3914 return PHY_TSSI_EXTRA_GROUP(4); 3915 case 81 ... 93: 3916 return 5; 3917 case 97 ... 109: 3918 return 6; 3919 case 110 ... 112: 3920 return PHY_TSSI_EXTRA_GROUP(6); 3921 case 113 ... 125: 3922 return 7; 3923 case 129 ... 141: 3924 return 8; 3925 case 142 ... 144: 3926 return PHY_TSSI_EXTRA_GROUP(8); 3927 case 145 ... 157: 3928 return 9; 3929 case 161 ... 173: 3930 return 10; 3931 case 174 ... 176: 3932 return PHY_TSSI_EXTRA_GROUP(10); 3933 case 177 ... 189: 3934 return 11; 3935 case 193 ... 205: 3936 return 12; 3937 case 206 ... 208: 3938 return PHY_TSSI_EXTRA_GROUP(12); 3939 case 209 ... 221: 3940 return 13; 3941 case 225 ... 237: 3942 return 14; 3943 case 238 ... 240: 3944 return PHY_TSSI_EXTRA_GROUP(14); 3945 case 241 ... 253: 3946 return 15; 3947 } 3948 3949 return 0; 3950 } 3951 3952 static s8 phy_tssi_get_ofdm_de(struct rtw89_dev *rtwdev, 3953 enum rtw89_phy_idx phy, 3954 const struct rtw89_chan *chan, 3955 enum rtw89_rf_path path) 3956 { 3957 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3958 enum rtw89_band band = chan->band_type; 3959 u8 ch = chan->channel; 3960 u32 gidx_1st; 3961 u32 gidx_2nd; 3962 s8 de_1st; 3963 s8 de_2nd; 3964 u32 gidx; 3965 s8 val; 3966 3967 if (band == RTW89_BAND_6G) 3968 goto calc_6g; 3969 3970 gidx = phy_tssi_get_ofdm_group(ch); 3971 3972 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3973 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", 3974 path, gidx); 3975 3976 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) { 3977 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx); 3978 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx); 3979 de_1st = tssi_info->tssi_mcs[path][gidx_1st]; 3980 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd]; 3981 val = (de_1st + de_2nd) / 2; 3982 3983 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3984 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", 3985 path, val, de_1st, de_2nd); 3986 } else { 3987 val = tssi_info->tssi_mcs[path][gidx]; 3988 3989 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3990 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); 3991 } 3992 3993 return val; 3994 3995 calc_6g: 3996 gidx = phy_tssi_get_6g_ofdm_group(ch); 3997 3998 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3999 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", 4000 path, gidx); 4001 4002 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) { 4003 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx); 4004 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx); 4005 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st]; 4006 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd]; 4007 val = (de_1st + de_2nd) / 2; 4008 4009 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4010 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", 4011 path, val, de_1st, de_2nd); 4012 } else { 4013 val = tssi_info->tssi_6g_mcs[path][gidx]; 4014 4015 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4016 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); 4017 } 4018 4019 return val; 4020 } 4021 4022 static s8 phy_tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev, 4023 enum rtw89_phy_idx phy, 4024 const struct rtw89_chan *chan, 4025 enum rtw89_rf_path path) 4026 { 4027 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 4028 enum rtw89_band band = chan->band_type; 4029 u8 ch = chan->channel; 4030 u32 tgidx_1st; 4031 u32 tgidx_2nd; 4032 s8 tde_1st; 4033 s8 tde_2nd; 4034 u32 tgidx; 4035 s8 val; 4036 4037 if (band == RTW89_BAND_6G) 4038 goto calc_6g; 4039 4040 tgidx = phy_tssi_get_trim_group(ch); 4041 4042 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4043 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", 4044 path, tgidx); 4045 4046 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) { 4047 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx); 4048 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx); 4049 tde_1st = tssi_info->tssi_trim[path][tgidx_1st]; 4050 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd]; 4051 val = (tde_1st + tde_2nd) / 2; 4052 4053 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4054 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", 4055 path, val, tde_1st, tde_2nd); 4056 } else { 4057 val = tssi_info->tssi_trim[path][tgidx]; 4058 4059 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4060 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", 4061 path, val); 4062 } 4063 4064 return val; 4065 4066 calc_6g: 4067 tgidx = phy_tssi_get_6g_trim_group(ch); 4068 4069 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4070 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", 4071 path, tgidx); 4072 4073 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) { 4074 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx); 4075 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx); 4076 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st]; 4077 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd]; 4078 val = (tde_1st + tde_2nd) / 2; 4079 4080 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4081 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", 4082 path, val, tde_1st, tde_2nd); 4083 } else { 4084 val = tssi_info->tssi_trim_6g[path][tgidx]; 4085 4086 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4087 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", 4088 path, val); 4089 } 4090 4091 return val; 4092 } 4093 4094 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, 4095 enum rtw89_phy_idx phy, 4096 const struct rtw89_chan *chan, 4097 struct rtw89_h2c_rf_tssi *h2c) 4098 { 4099 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 4100 u8 ch = chan->channel; 4101 s8 trim_de; 4102 s8 ofdm_de; 4103 s8 cck_de; 4104 u8 gidx; 4105 s8 val; 4106 int i; 4107 4108 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n", 4109 phy, ch); 4110 4111 for (i = RF_PATH_A; i <= RF_PATH_B; i++) { 4112 trim_de = phy_tssi_get_ofdm_trim_de(rtwdev, phy, chan, i); 4113 h2c->curr_tssi_trim_de[i] = trim_de; 4114 4115 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4116 "[TSSI][TRIM]: path=%d trim_de=0x%x\n", i, trim_de); 4117 4118 gidx = phy_tssi_get_cck_group(ch); 4119 cck_de = tssi_info->tssi_cck[i][gidx]; 4120 val = u32_get_bits(cck_de + trim_de, 0xff); 4121 4122 h2c->curr_tssi_cck_de[i] = 0x0; 4123 h2c->curr_tssi_cck_de_20m[i] = val; 4124 h2c->curr_tssi_cck_de_40m[i] = val; 4125 h2c->curr_tssi_efuse_cck_de[i] = cck_de; 4126 4127 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4128 "[TSSI][TRIM]: path=%d cck_de=0x%x\n", i, cck_de); 4129 4130 ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i); 4131 val = u32_get_bits(ofdm_de + trim_de, 0xff); 4132 4133 h2c->curr_tssi_ofdm_de[i] = 0x0; 4134 h2c->curr_tssi_ofdm_de_20m[i] = val; 4135 h2c->curr_tssi_ofdm_de_40m[i] = val; 4136 h2c->curr_tssi_ofdm_de_80m[i] = val; 4137 h2c->curr_tssi_ofdm_de_160m[i] = val; 4138 h2c->curr_tssi_ofdm_de_320m[i] = val; 4139 h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de; 4140 4141 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4142 "[TSSI][TRIM]: path=%d ofdm_de=0x%x\n", i, ofdm_de); 4143 } 4144 } 4145 4146 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev, 4147 enum rtw89_phy_idx phy, 4148 const struct rtw89_chan *chan, 4149 struct rtw89_h2c_rf_tssi *h2c) 4150 { 4151 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk; 4152 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 4153 const s8 *thm_up[RF_PATH_B + 1] = {}; 4154 const s8 *thm_down[RF_PATH_B + 1] = {}; 4155 u8 subband = chan->subband_type; 4156 s8 thm_ofst[128] = {0}; 4157 u8 thermal; 4158 u8 path; 4159 u8 i, j; 4160 4161 switch (subband) { 4162 default: 4163 case RTW89_CH_2G: 4164 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0]; 4165 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0]; 4166 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0]; 4167 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0]; 4168 break; 4169 case RTW89_CH_5G_BAND_1: 4170 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0]; 4171 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0]; 4172 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0]; 4173 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0]; 4174 break; 4175 case RTW89_CH_5G_BAND_3: 4176 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1]; 4177 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1]; 4178 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1]; 4179 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1]; 4180 break; 4181 case RTW89_CH_5G_BAND_4: 4182 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2]; 4183 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2]; 4184 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2]; 4185 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2]; 4186 break; 4187 case RTW89_CH_6G_BAND_IDX0: 4188 case RTW89_CH_6G_BAND_IDX1: 4189 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0]; 4190 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0]; 4191 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0]; 4192 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0]; 4193 break; 4194 case RTW89_CH_6G_BAND_IDX2: 4195 case RTW89_CH_6G_BAND_IDX3: 4196 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1]; 4197 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1]; 4198 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1]; 4199 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1]; 4200 break; 4201 case RTW89_CH_6G_BAND_IDX4: 4202 case RTW89_CH_6G_BAND_IDX5: 4203 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2]; 4204 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2]; 4205 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2]; 4206 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2]; 4207 break; 4208 case RTW89_CH_6G_BAND_IDX6: 4209 case RTW89_CH_6G_BAND_IDX7: 4210 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3]; 4211 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3]; 4212 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3]; 4213 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3]; 4214 break; 4215 } 4216 4217 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4218 "[TSSI] tmeter tbl on subband: %u\n", subband); 4219 4220 for (path = RF_PATH_A; path <= RF_PATH_B; path++) { 4221 thermal = tssi_info->thermal[path]; 4222 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4223 "path: %u, pg thermal: 0x%x\n", path, thermal); 4224 4225 if (thermal == 0xff) { 4226 h2c->pg_thermal[path] = 0x38; 4227 memset(h2c->ftable[path], 0, sizeof(h2c->ftable[path])); 4228 continue; 4229 } 4230 4231 h2c->pg_thermal[path] = thermal; 4232 4233 i = 0; 4234 for (j = 0; j < 64; j++) 4235 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 4236 thm_up[path][i++] : 4237 thm_up[path][DELTA_SWINGIDX_SIZE - 1]; 4238 4239 i = 1; 4240 for (j = 127; j >= 64; j--) 4241 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 4242 -thm_down[path][i++] : 4243 -thm_down[path][DELTA_SWINGIDX_SIZE - 1]; 4244 4245 for (i = 0; i < 128; i += 4) { 4246 h2c->ftable[path][i + 0] = thm_ofst[i + 3]; 4247 h2c->ftable[path][i + 1] = thm_ofst[i + 2]; 4248 h2c->ftable[path][i + 2] = thm_ofst[i + 1]; 4249 h2c->ftable[path][i + 3] = thm_ofst[i + 0]; 4250 4251 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 4252 "thm ofst [%x]: %02x %02x %02x %02x\n", 4253 i, thm_ofst[i], thm_ofst[i + 1], 4254 thm_ofst[i + 2], thm_ofst[i + 3]); 4255 } 4256 } 4257 } 4258 4259 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 4260 { 4261 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 4262 u32 reg_mask; 4263 4264 if (sc_xo) 4265 reg_mask = xtal->sc_xo_mask; 4266 else 4267 reg_mask = xtal->sc_xi_mask; 4268 4269 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask); 4270 } 4271 4272 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 4273 u8 val) 4274 { 4275 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 4276 u32 reg_mask; 4277 4278 if (sc_xo) 4279 reg_mask = xtal->sc_xo_mask; 4280 else 4281 reg_mask = xtal->sc_xi_mask; 4282 4283 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val); 4284 } 4285 4286 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 4287 u8 crystal_cap, bool force) 4288 { 4289 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4290 const struct rtw89_chip_info *chip = rtwdev->chip; 4291 u8 sc_xi_val, sc_xo_val; 4292 4293 if (!force && cfo->crystal_cap == crystal_cap) 4294 return; 4295 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) { 4296 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 4297 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 4298 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 4299 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 4300 } else { 4301 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 4302 crystal_cap, XTAL_SC_XO_MASK); 4303 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 4304 crystal_cap, XTAL_SC_XI_MASK); 4305 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 4306 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 4307 } 4308 cfo->crystal_cap = sc_xi_val; 4309 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 4310 4311 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 4312 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 4313 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 4314 cfo->x_cap_ofst); 4315 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 4316 } 4317 4318 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 4319 { 4320 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4321 u8 cap; 4322 4323 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 4324 cfo->is_adjust = false; 4325 if (cfo->crystal_cap == cfo->def_x_cap) 4326 return; 4327 cap = cfo->crystal_cap; 4328 cap += (cap > cfo->def_x_cap ? -1 : 1); 4329 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 4330 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4331 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 4332 cfo->def_x_cap); 4333 } 4334 4335 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 4336 { 4337 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 4338 bool is_linked = rtwdev->total_sta_assoc > 0; 4339 s32 cfo_avg_312; 4340 s32 dcfo_comp_val; 4341 int sign; 4342 4343 if (rtwdev->chip->chip_id == RTL8922A) 4344 return; 4345 4346 if (!is_linked) { 4347 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 4348 is_linked); 4349 return; 4350 } 4351 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 4352 if (curr_cfo == 0) 4353 return; 4354 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 4355 sign = curr_cfo > 0 ? 1 : -1; 4356 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val; 4357 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312); 4358 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 4359 cfo_avg_312 = -cfo_avg_312; 4360 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 4361 cfo_avg_312); 4362 } 4363 4364 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 4365 { 4366 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4367 const struct rtw89_chip_info *chip = rtwdev->chip; 4368 const struct rtw89_cfo_regs *cfo = phy->cfo; 4369 4370 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1); 4371 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8); 4372 4373 if (chip->chip_gen == RTW89_CHIP_AX) { 4374 if (chip->cfo_hw_comp) { 4375 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2, 4376 B_AX_PWR_UL_CFO_MASK, 0x6); 4377 } else { 4378 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 4379 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, 4380 B_AX_PWR_UL_CFO_MASK); 4381 } 4382 } 4383 } 4384 4385 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 4386 { 4387 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4388 struct rtw89_efuse *efuse = &rtwdev->efuse; 4389 4390 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 4391 cfo->crystal_cap = cfo->crystal_cap_default; 4392 cfo->def_x_cap = cfo->crystal_cap; 4393 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 4394 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 4395 cfo->is_adjust = false; 4396 cfo->divergence_lock_en = false; 4397 cfo->x_cap_ofst = 0; 4398 cfo->lock_cnt = 0; 4399 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 4400 cfo->apply_compensation = false; 4401 cfo->residual_cfo_acc = 0; 4402 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 4403 cfo->crystal_cap_default); 4404 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 4405 rtw89_dcfo_comp_init(rtwdev); 4406 cfo->cfo_timer_ms = 2000; 4407 cfo->cfo_trig_by_timer_en = false; 4408 cfo->phy_cfo_trk_cnt = 0; 4409 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4410 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 4411 } 4412 4413 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 4414 s32 curr_cfo) 4415 { 4416 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4417 int crystal_cap = cfo->crystal_cap; 4418 s32 cfo_abs = abs(curr_cfo); 4419 int sign; 4420 4421 if (curr_cfo == 0) { 4422 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 4423 return; 4424 } 4425 if (!cfo->is_adjust) { 4426 if (cfo_abs > CFO_TRK_ENABLE_TH) 4427 cfo->is_adjust = true; 4428 } else { 4429 if (cfo_abs <= CFO_TRK_STOP_TH) 4430 cfo->is_adjust = false; 4431 } 4432 if (!cfo->is_adjust) { 4433 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 4434 return; 4435 } 4436 sign = curr_cfo > 0 ? 1 : -1; 4437 if (cfo_abs > CFO_TRK_STOP_TH_4) 4438 crystal_cap += 3 * sign; 4439 else if (cfo_abs > CFO_TRK_STOP_TH_3) 4440 crystal_cap += 3 * sign; 4441 else if (cfo_abs > CFO_TRK_STOP_TH_2) 4442 crystal_cap += 1 * sign; 4443 else if (cfo_abs > CFO_TRK_STOP_TH_1) 4444 crystal_cap += 1 * sign; 4445 else 4446 return; 4447 4448 crystal_cap = clamp(crystal_cap, 0, 127); 4449 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 4450 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4451 "X_cap{Curr,Default}={0x%x,0x%x}\n", 4452 cfo->crystal_cap, cfo->def_x_cap); 4453 } 4454 4455 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 4456 { 4457 const struct rtw89_chip_info *chip = rtwdev->chip; 4458 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4459 s32 cfo_khz_all = 0; 4460 s32 cfo_cnt_all = 0; 4461 s32 cfo_all_avg = 0; 4462 u8 i; 4463 4464 if (rtwdev->total_sta_assoc != 1) 4465 return 0; 4466 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 4467 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4468 if (cfo->cfo_cnt[i] == 0) 4469 continue; 4470 cfo_khz_all += cfo->cfo_tail[i]; 4471 cfo_cnt_all += cfo->cfo_cnt[i]; 4472 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 4473 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 4474 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft, 4475 cfo_cnt_all); 4476 } 4477 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4478 "CFO track for macid = %d\n", i); 4479 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4480 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 4481 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 4482 return cfo_all_avg; 4483 } 4484 4485 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 4486 { 4487 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4488 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4489 s32 target_cfo = 0; 4490 s32 cfo_khz_all = 0; 4491 s32 cfo_khz_all_tp_wgt = 0; 4492 s32 cfo_avg = 0; 4493 s32 max_cfo_lb = BIT(31); 4494 s32 min_cfo_ub = GENMASK(30, 0); 4495 u16 cfo_cnt_all = 0; 4496 u8 active_entry_cnt = 0; 4497 u8 sta_cnt = 0; 4498 u32 tp_all = 0; 4499 u8 i; 4500 u8 cfo_tol = 0; 4501 4502 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 4503 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 4504 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 4505 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4506 if (cfo->cfo_cnt[i] == 0) 4507 continue; 4508 cfo_khz_all += cfo->cfo_tail[i]; 4509 cfo_cnt_all += cfo->cfo_cnt[i]; 4510 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 4511 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4512 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 4513 cfo_khz_all, cfo_cnt_all, cfo_avg); 4514 target_cfo = cfo_avg; 4515 } 4516 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 4517 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 4518 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4519 if (cfo->cfo_cnt[i] == 0) 4520 continue; 4521 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 4522 (s32)cfo->cfo_cnt[i]); 4523 cfo_khz_all += cfo->cfo_avg[i]; 4524 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4525 "Macid=%d, cfo_avg=%d\n", i, 4526 cfo->cfo_avg[i]); 4527 } 4528 sta_cnt = rtwdev->total_sta_assoc; 4529 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 4530 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4531 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 4532 cfo_khz_all, sta_cnt, cfo_avg); 4533 target_cfo = cfo_avg; 4534 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 4535 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 4536 cfo_tol = cfo->sta_cfo_tolerance; 4537 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4538 sta_cnt++; 4539 if (cfo->cfo_cnt[i] != 0) { 4540 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 4541 (s32)cfo->cfo_cnt[i]); 4542 active_entry_cnt++; 4543 } else { 4544 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 4545 } 4546 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 4547 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 4548 cfo_khz_all += cfo->cfo_avg[i]; 4549 /* need tp for each entry */ 4550 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4551 "[%d] cfo_avg=%d, tp=tbd\n", 4552 i, cfo->cfo_avg[i]); 4553 if (sta_cnt >= rtwdev->total_sta_assoc) 4554 break; 4555 } 4556 tp_all = stats->rx_throughput; /* need tp for each entry */ 4557 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 4558 4559 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 4560 sta_cnt); 4561 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 4562 active_entry_cnt); 4563 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4564 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 4565 cfo_khz_all_tp_wgt, cfo_avg); 4566 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 4567 max_cfo_lb, min_cfo_ub); 4568 if (max_cfo_lb <= min_cfo_ub) { 4569 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4570 "cfo win_size=%d\n", 4571 min_cfo_ub - max_cfo_lb); 4572 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 4573 } else { 4574 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4575 "No intersection of cfo tolerance windows\n"); 4576 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 4577 } 4578 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 4579 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 4580 } 4581 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 4582 return target_cfo; 4583 } 4584 4585 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 4586 { 4587 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4588 4589 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 4590 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 4591 cfo->packet_count = 0; 4592 cfo->packet_count_pre = 0; 4593 cfo->cfo_avg_pre = 0; 4594 } 4595 4596 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 4597 { 4598 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4599 s32 new_cfo = 0; 4600 bool x_cap_update = false; 4601 u8 pre_x_cap = cfo->crystal_cap; 4602 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 4603 4604 cfo->dcfo_avg = 0; 4605 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 4606 rtwdev->total_sta_assoc); 4607 if (rtwdev->total_sta_assoc == 0 || rtw89_is_mlo_1_1(rtwdev)) { 4608 rtw89_phy_cfo_reset(rtwdev); 4609 return; 4610 } 4611 if (cfo->packet_count == 0) { 4612 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 4613 return; 4614 } 4615 if (cfo->packet_count == cfo->packet_count_pre) { 4616 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 4617 return; 4618 } 4619 if (rtwdev->total_sta_assoc == 1) 4620 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 4621 else 4622 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 4623 if (cfo->divergence_lock_en) { 4624 cfo->lock_cnt++; 4625 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 4626 cfo->divergence_lock_en = false; 4627 cfo->lock_cnt = 0; 4628 } else { 4629 rtw89_phy_cfo_reset(rtwdev); 4630 } 4631 return; 4632 } 4633 if (cfo->crystal_cap >= cfo->x_cap_ub || 4634 cfo->crystal_cap <= cfo->x_cap_lb) { 4635 cfo->divergence_lock_en = true; 4636 rtw89_phy_cfo_reset(rtwdev); 4637 return; 4638 } 4639 4640 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 4641 cfo->cfo_avg_pre = new_cfo; 4642 cfo->dcfo_avg_pre = cfo->dcfo_avg; 4643 x_cap_update = cfo->crystal_cap != pre_x_cap; 4644 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 4645 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 4646 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 4647 cfo->x_cap_ofst); 4648 if (x_cap_update) { 4649 if (cfo->dcfo_avg > 0) 4650 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 4651 else 4652 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 4653 } 4654 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg); 4655 rtw89_phy_cfo_statistics_reset(rtwdev); 4656 } 4657 4658 void rtw89_phy_cfo_track_work(struct wiphy *wiphy, struct wiphy_work *work) 4659 { 4660 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4661 cfo_track_work.work); 4662 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4663 4664 lockdep_assert_wiphy(wiphy); 4665 4666 if (!cfo->cfo_trig_by_timer_en) 4667 return; 4668 rtw89_leave_ps_mode(rtwdev); 4669 rtw89_phy_cfo_dm(rtwdev); 4670 wiphy_delayed_work_queue(wiphy, &rtwdev->cfo_track_work, 4671 msecs_to_jiffies(cfo->cfo_timer_ms)); 4672 } 4673 4674 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 4675 { 4676 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4677 4678 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->cfo_track_work, 4679 msecs_to_jiffies(cfo->cfo_timer_ms)); 4680 } 4681 4682 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 4683 { 4684 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4685 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4686 bool is_ul_ofdma = false, ofdma_acc_en = false; 4687 4688 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 4689 is_ul_ofdma = true; 4690 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 4691 is_ul_ofdma) 4692 ofdma_acc_en = true; 4693 4694 switch (cfo->phy_cfo_status) { 4695 case RTW89_PHY_DCFO_STATE_NORMAL: 4696 if (stats->tx_throughput >= CFO_TP_UPPER) { 4697 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 4698 cfo->cfo_trig_by_timer_en = true; 4699 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 4700 rtw89_phy_cfo_start_work(rtwdev); 4701 } 4702 break; 4703 case RTW89_PHY_DCFO_STATE_ENHANCE: 4704 if (stats->tx_throughput <= CFO_TP_LOWER) 4705 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4706 else if (ofdma_acc_en && 4707 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 4708 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 4709 else 4710 cfo->phy_cfo_trk_cnt++; 4711 4712 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 4713 cfo->phy_cfo_trk_cnt = 0; 4714 cfo->cfo_trig_by_timer_en = false; 4715 } 4716 break; 4717 case RTW89_PHY_DCFO_STATE_HOLD: 4718 if (stats->tx_throughput <= CFO_TP_LOWER) { 4719 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4720 cfo->phy_cfo_trk_cnt = 0; 4721 cfo->cfo_trig_by_timer_en = false; 4722 } else { 4723 cfo->phy_cfo_trk_cnt++; 4724 } 4725 break; 4726 default: 4727 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4728 cfo->phy_cfo_trk_cnt = 0; 4729 break; 4730 } 4731 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4732 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 4733 stats->tx_throughput, cfo->phy_cfo_status, 4734 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 4735 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 4736 if (cfo->cfo_trig_by_timer_en) 4737 return; 4738 rtw89_phy_cfo_dm(rtwdev); 4739 } 4740 4741 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 4742 struct rtw89_rx_phy_ppdu *phy_ppdu) 4743 { 4744 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4745 u8 macid = phy_ppdu->mac_id; 4746 4747 if (macid >= CFO_TRACK_MAX_USER) { 4748 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 4749 return; 4750 } 4751 4752 cfo->cfo_tail[macid] += cfo_val; 4753 cfo->cfo_cnt[macid]++; 4754 cfo->packet_count++; 4755 } 4756 4757 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4758 { 4759 const struct rtw89_chip_info *chip = rtwdev->chip; 4760 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4761 rtwvif_link->chanctx_idx); 4762 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4763 4764 if (!chip->ul_tb_waveform_ctrl) 4765 return; 4766 4767 rtwvif_link->def_tri_idx = 4768 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG); 4769 4770 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV) 4771 rtwvif_link->dyn_tb_bedge_en = false; 4772 else if (chan->band_type >= RTW89_BAND_5G && 4773 chan->band_width >= RTW89_CHANNEL_WIDTH_40) 4774 rtwvif_link->dyn_tb_bedge_en = true; 4775 else 4776 rtwvif_link->dyn_tb_bedge_en = false; 4777 4778 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4779 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n", 4780 ul_tb_info->def_if_bandedge, rtwvif_link->def_tri_idx); 4781 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4782 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n", 4783 rtwvif_link->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en); 4784 } 4785 4786 struct rtw89_phy_ul_tb_check_data { 4787 bool valid; 4788 bool high_tf_client; 4789 bool low_tf_client; 4790 bool dyn_tb_bedge_en; 4791 u8 def_tri_idx; 4792 }; 4793 4794 struct rtw89_phy_power_diff { 4795 u32 q_00; 4796 u32 q_11; 4797 u32 q_matrix_en; 4798 u32 ultb_1t_norm_160; 4799 u32 ultb_2t_norm_160; 4800 u32 com1_norm_1sts; 4801 u32 com2_resp_1sts_path; 4802 }; 4803 4804 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev, 4805 struct rtw89_vif_link *rtwvif_link) 4806 { 4807 static const struct rtw89_phy_power_diff table[2] = { 4808 {0x0, 0x0, 0x0, 0x0, 0xf4, 0x3, 0x3}, 4809 {0xb50, 0xb50, 0x1, 0xc, 0x0, 0x1, 0x1}, 4810 }; 4811 const struct rtw89_phy_power_diff *param; 4812 u32 reg; 4813 4814 if (!rtwdev->chip->ul_tb_pwr_diff) 4815 return; 4816 4817 if (rtwvif_link->pwr_diff_en == rtwvif_link->pre_pwr_diff_en) { 4818 rtwvif_link->pwr_diff_en = false; 4819 return; 4820 } 4821 4822 rtwvif_link->pre_pwr_diff_en = rtwvif_link->pwr_diff_en; 4823 param = &table[rtwvif_link->pwr_diff_en]; 4824 4825 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL, 4826 param->q_00); 4827 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL, 4828 param->q_11); 4829 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX, 4830 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en); 4831 4832 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif_link->mac_idx); 4833 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160, 4834 param->ultb_1t_norm_160); 4835 4836 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif_link->mac_idx); 4837 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160, 4838 param->ultb_2t_norm_160); 4839 4840 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif_link->mac_idx); 4841 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS, 4842 param->com1_norm_1sts); 4843 4844 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif_link->mac_idx); 4845 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH, 4846 param->com2_resp_1sts_path); 4847 } 4848 4849 static 4850 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev, 4851 struct rtw89_vif_link *rtwvif_link, 4852 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 4853 { 4854 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4855 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4856 4857 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION) 4858 return; 4859 4860 if (!vif->cfg.assoc) 4861 return; 4862 4863 if (rtwdev->chip->ul_tb_waveform_ctrl) { 4864 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH) 4865 ul_tb_data->high_tf_client = true; 4866 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH) 4867 ul_tb_data->low_tf_client = true; 4868 4869 ul_tb_data->valid = true; 4870 ul_tb_data->def_tri_idx = rtwvif_link->def_tri_idx; 4871 ul_tb_data->dyn_tb_bedge_en = rtwvif_link->dyn_tb_bedge_en; 4872 } 4873 4874 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif_link); 4875 } 4876 4877 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev, 4878 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 4879 { 4880 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4881 4882 if (!rtwdev->chip->ul_tb_waveform_ctrl) 4883 return; 4884 4885 if (ul_tb_data->dyn_tb_bedge_en) { 4886 if (ul_tb_data->high_tf_client) { 4887 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0); 4888 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4889 "[ULTB] Turn off if_bandedge\n"); 4890 } else if (ul_tb_data->low_tf_client) { 4891 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 4892 ul_tb_info->def_if_bandedge); 4893 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4894 "[ULTB] Set to default if_bandedge = %d\n", 4895 ul_tb_info->def_if_bandedge); 4896 } 4897 } 4898 4899 if (ul_tb_info->dyn_tb_tri_en) { 4900 if (ul_tb_data->high_tf_client) { 4901 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 4902 B_TXSHAPE_TRIANGULAR_CFG, 0); 4903 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4904 "[ULTB] Turn off Tx triangle\n"); 4905 } else if (ul_tb_data->low_tf_client) { 4906 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 4907 B_TXSHAPE_TRIANGULAR_CFG, 4908 ul_tb_data->def_tri_idx); 4909 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4910 "[ULTB] Set to default tx_shap_idx = %d\n", 4911 ul_tb_data->def_tri_idx); 4912 } 4913 } 4914 } 4915 4916 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev) 4917 { 4918 const struct rtw89_chip_info *chip = rtwdev->chip; 4919 struct rtw89_phy_ul_tb_check_data ul_tb_data = {}; 4920 struct rtw89_vif_link *rtwvif_link; 4921 struct rtw89_vif *rtwvif; 4922 unsigned int link_id; 4923 4924 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff) 4925 return; 4926 4927 if (rtwdev->total_sta_assoc != 1) 4928 return; 4929 4930 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4931 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4932 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif_link, &ul_tb_data); 4933 4934 if (!ul_tb_data.valid) 4935 return; 4936 4937 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data); 4938 } 4939 4940 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev) 4941 { 4942 const struct rtw89_chip_info *chip = rtwdev->chip; 4943 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4944 4945 if (!chip->ul_tb_waveform_ctrl) 4946 return; 4947 4948 ul_tb_info->dyn_tb_tri_en = true; 4949 ul_tb_info->def_if_bandedge = 4950 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN); 4951 } 4952 4953 static 4954 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts) 4955 { 4956 ewma_rssi_init(&antdiv_sts->cck_rssi_avg); 4957 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg); 4958 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg); 4959 antdiv_sts->pkt_cnt_cck = 0; 4960 antdiv_sts->pkt_cnt_ofdm = 0; 4961 antdiv_sts->pkt_cnt_non_legacy = 0; 4962 antdiv_sts->evm = 0; 4963 } 4964 4965 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev, 4966 struct rtw89_rx_phy_ppdu *phy_ppdu, 4967 struct rtw89_antdiv_stats *stats) 4968 { 4969 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) { 4970 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) { 4971 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg); 4972 stats->pkt_cnt_cck++; 4973 } else { 4974 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg); 4975 stats->pkt_cnt_ofdm++; 4976 stats->evm += phy_ppdu->ofdm.evm_min; 4977 } 4978 } else { 4979 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg); 4980 stats->pkt_cnt_non_legacy++; 4981 stats->evm += phy_ppdu->ofdm.evm_min; 4982 } 4983 } 4984 4985 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats) 4986 { 4987 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck && 4988 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm) 4989 return ewma_rssi_read(&stats->non_legacy_rssi_avg); 4990 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck && 4991 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy) 4992 return ewma_rssi_read(&stats->ofdm_rssi_avg); 4993 else 4994 return ewma_rssi_read(&stats->cck_rssi_avg); 4995 } 4996 4997 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats) 4998 { 4999 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm); 5000 } 5001 5002 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 5003 struct rtw89_rx_phy_ppdu *phy_ppdu) 5004 { 5005 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5006 struct rtw89_hal *hal = &rtwdev->hal; 5007 5008 if (!hal->ant_diversity || hal->ant_diversity_fixed) 5009 return; 5010 5011 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats); 5012 5013 if (!antdiv->get_stats) 5014 return; 5015 5016 if (hal->antenna_rx == RF_A) 5017 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats); 5018 else if (hal->antenna_rx == RF_B) 5019 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats); 5020 } 5021 5022 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev) 5023 { 5024 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN, 5025 0x0, RTW89_PHY_0); 5026 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL, 5027 0x0, RTW89_PHY_0); 5028 5029 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND, 5030 0x0, RTW89_PHY_0); 5031 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT, 5032 0x0, RTW89_PHY_0); 5033 5034 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN, 5035 0x0, RTW89_PHY_0); 5036 5037 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING, 5038 0x0100, RTW89_PHY_0); 5039 5040 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX, 5041 0x1, RTW89_PHY_0); 5042 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL, 5043 0x0, RTW89_PHY_0); 5044 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G, 5045 0x0, RTW89_PHY_0); 5046 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G, 5047 0x0, RTW89_PHY_0); 5048 } 5049 5050 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev) 5051 { 5052 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5053 5054 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 5055 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats); 5056 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats); 5057 } 5058 5059 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev) 5060 { 5061 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5062 struct rtw89_hal *hal = &rtwdev->hal; 5063 5064 if (!hal->ant_diversity) 5065 return; 5066 5067 antdiv->get_stats = false; 5068 antdiv->rssi_pre = 0; 5069 rtw89_phy_antdiv_sts_reset(rtwdev); 5070 rtw89_phy_antdiv_reg_init(rtwdev); 5071 } 5072 5073 static void rtw89_phy_thermal_protect(struct rtw89_dev *rtwdev) 5074 { 5075 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 5076 struct rtw89_hal *hal = &rtwdev->hal; 5077 u8 th_max = phystat->last_thermal_max; 5078 u8 lv = hal->thermal_prot_lv; 5079 5080 if (!hal->thermal_prot_th || 5081 (hal->disabled_dm_bitmap & BIT(RTW89_DM_THERMAL_PROTECT))) 5082 return; 5083 5084 if (th_max > hal->thermal_prot_th && lv < RTW89_THERMAL_PROT_LV_MAX) 5085 lv++; 5086 else if (th_max < hal->thermal_prot_th - 2 && lv > 0) 5087 lv--; 5088 else 5089 return; 5090 5091 hal->thermal_prot_lv = lv; 5092 5093 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "thermal protection lv=%d\n", lv); 5094 5095 rtw89_fw_h2c_tx_duty(rtwdev, hal->thermal_prot_lv); 5096 } 5097 5098 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 5099 { 5100 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 5101 u8 th, th_max = 0; 5102 int i; 5103 5104 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 5105 th = rtw89_chip_get_thermal(rtwdev, i); 5106 if (th) 5107 ewma_thermal_add(&phystat->avg_thermal[i], th); 5108 5109 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 5110 "path(%d) thermal cur=%u avg=%ld", i, th, 5111 ewma_thermal_read(&phystat->avg_thermal[i])); 5112 5113 th_max = max(th_max, th); 5114 } 5115 5116 phystat->last_thermal_max = th_max; 5117 } 5118 5119 struct rtw89_phy_iter_rssi_data { 5120 struct rtw89_dev *rtwdev; 5121 bool rssi_changed; 5122 }; 5123 5124 static 5125 void __rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link *rtwsta_link, 5126 struct rtw89_phy_iter_rssi_data *rssi_data) 5127 { 5128 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link; 5129 struct rtw89_dev *rtwdev = rssi_data->rtwdev; 5130 struct rtw89_phy_ch_info *ch_info; 5131 struct rtw89_bb_ctx *bb; 5132 unsigned long rssi_curr; 5133 5134 rssi_curr = ewma_rssi_read(&rtwsta_link->avg_rssi); 5135 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 5136 ch_info = &bb->ch_info; 5137 5138 if (rssi_curr < ch_info->rssi_min) { 5139 ch_info->rssi_min = rssi_curr; 5140 ch_info->rssi_min_macid = rtwsta_link->mac_id; 5141 } 5142 5143 if (rtwsta_link->prev_rssi == 0) { 5144 rtwsta_link->prev_rssi = rssi_curr; 5145 } else if (abs((int)rtwsta_link->prev_rssi - (int)rssi_curr) > 5146 (3 << RSSI_FACTOR)) { 5147 rtwsta_link->prev_rssi = rssi_curr; 5148 rssi_data->rssi_changed = true; 5149 } 5150 } 5151 5152 static void rtw89_phy_stat_rssi_update_iter(void *data, 5153 struct ieee80211_sta *sta) 5154 { 5155 struct rtw89_phy_iter_rssi_data *rssi_data = 5156 (struct rtw89_phy_iter_rssi_data *)data; 5157 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 5158 struct rtw89_sta_link *rtwsta_link; 5159 unsigned int link_id; 5160 5161 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 5162 __rtw89_phy_stat_rssi_update_iter(rtwsta_link, rssi_data); 5163 } 5164 5165 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 5166 { 5167 struct rtw89_phy_iter_rssi_data rssi_data = {}; 5168 struct rtw89_bb_ctx *bb; 5169 5170 rssi_data.rtwdev = rtwdev; 5171 rtw89_for_each_active_bb(rtwdev, bb) 5172 bb->ch_info.rssi_min = U8_MAX; 5173 5174 ieee80211_iterate_stations_atomic(rtwdev->hw, 5175 rtw89_phy_stat_rssi_update_iter, 5176 &rssi_data); 5177 if (rssi_data.rssi_changed) 5178 rtw89_btc_ntfy_wl_sta(rtwdev); 5179 } 5180 5181 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 5182 { 5183 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 5184 int i; 5185 5186 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 5187 ewma_thermal_init(&phystat->avg_thermal[i]); 5188 5189 rtw89_phy_stat_thermal_update(rtwdev); 5190 5191 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 5192 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 5193 5194 ewma_rssi_init(&phystat->bcn_rssi); 5195 5196 rtwdev->hal.thermal_prot_lv = 0; 5197 } 5198 5199 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 5200 { 5201 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 5202 5203 rtw89_phy_stat_thermal_update(rtwdev); 5204 rtw89_phy_thermal_protect(rtwdev); 5205 rtw89_phy_stat_rssi_update(rtwdev); 5206 5207 phystat->last_pkt_stat = phystat->cur_pkt_stat; 5208 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 5209 } 5210 5211 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, 5212 struct rtw89_bb_ctx *bb, u32 time_us) 5213 { 5214 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5215 5216 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 5217 } 5218 5219 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, 5220 struct rtw89_bb_ctx *bb, u16 idx) 5221 { 5222 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5223 5224 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 5225 } 5226 5227 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev, 5228 struct rtw89_bb_ctx *bb) 5229 { 5230 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5231 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5232 const struct rtw89_ccx_regs *ccx = phy->ccx; 5233 5234 env->ccx_manual_ctrl = false; 5235 env->ccx_ongoing = false; 5236 env->ccx_rac_lv = RTW89_RAC_RELEASE; 5237 env->ccx_period = 0; 5238 env->ccx_unit_idx = RTW89_CCX_32_US; 5239 5240 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->en_mask, 1, bb->phy_idx); 5241 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1, 5242 bb->phy_idx); 5243 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1, 5244 bb->phy_idx); 5245 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask, 5246 RTW89_CCX_EDCCA_BW20_0, bb->phy_idx); 5247 } 5248 5249 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, 5250 struct rtw89_bb_ctx *bb, 5251 u16 report, u16 score) 5252 { 5253 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5254 u32 numer = 0; 5255 u16 ret = 0; 5256 5257 numer = report * score + (env->ccx_period >> 1); 5258 if (env->ccx_period) 5259 ret = numer / env->ccx_period; 5260 5261 return ret >= score ? score - 1 : ret; 5262 } 5263 5264 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 5265 u16 time_ms, u32 *period, 5266 u32 *unit_idx) 5267 { 5268 u32 idx; 5269 u8 quotient; 5270 5271 if (time_ms >= CCX_MAX_PERIOD) 5272 time_ms = CCX_MAX_PERIOD; 5273 5274 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 5275 5276 if (quotient < 4) 5277 idx = RTW89_CCX_4_US; 5278 else if (quotient < 8) 5279 idx = RTW89_CCX_8_US; 5280 else if (quotient < 16) 5281 idx = RTW89_CCX_16_US; 5282 else 5283 idx = RTW89_CCX_32_US; 5284 5285 *unit_idx = idx; 5286 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 5287 5288 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5289 "[Trigger Time] period:%d, unit_idx:%d\n", 5290 *period, *unit_idx); 5291 } 5292 5293 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev, 5294 struct rtw89_bb_ctx *bb) 5295 { 5296 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5297 5298 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5299 "lv:(%d)->(0)\n", env->ccx_rac_lv); 5300 5301 env->ccx_ongoing = false; 5302 env->ccx_rac_lv = RTW89_RAC_RELEASE; 5303 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 5304 } 5305 5306 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 5307 struct rtw89_bb_ctx *bb, 5308 struct rtw89_ccx_para_info *para) 5309 { 5310 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5311 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 5312 u8 i = 0; 5313 u16 *ifs_th_l = env->ifs_clm_th_l; 5314 u16 *ifs_th_h = env->ifs_clm_th_h; 5315 u32 ifs_th0_us = 0, ifs_th_times = 0; 5316 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 5317 5318 if (!is_update) 5319 goto ifs_update_finished; 5320 5321 switch (para->ifs_clm_app) { 5322 case RTW89_IFS_CLM_INIT: 5323 case RTW89_IFS_CLM_BACKGROUND: 5324 case RTW89_IFS_CLM_ACS: 5325 case RTW89_IFS_CLM_DBG: 5326 case RTW89_IFS_CLM_DIG: 5327 case RTW89_IFS_CLM_TDMA_DIG: 5328 ifs_th0_us = IFS_CLM_TH0_UPPER; 5329 ifs_th_times = IFS_CLM_TH_MUL; 5330 break; 5331 case RTW89_IFS_CLM_DBG_MANUAL: 5332 ifs_th0_us = para->ifs_clm_manual_th0; 5333 ifs_th_times = para->ifs_clm_manual_th_times; 5334 break; 5335 default: 5336 break; 5337 } 5338 5339 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 5340 * low[i] = high[i-1] + 1 5341 * high[i] = high[i-1] * ifs_th_times 5342 */ 5343 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 5344 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 5345 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, bb, 5346 ifs_th0_us); 5347 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 5348 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 5349 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 5350 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, bb, ifs_th_h_us[i]); 5351 } 5352 5353 ifs_update_finished: 5354 if (!is_update) 5355 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5356 "No need to update IFS_TH\n"); 5357 5358 return is_update; 5359 } 5360 5361 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev, 5362 struct rtw89_bb_ctx *bb) 5363 { 5364 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5365 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5366 const struct rtw89_ccx_regs *ccx = phy->ccx; 5367 u8 i = 0; 5368 5369 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask, 5370 env->ifs_clm_th_l[0], bb->phy_idx); 5371 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask, 5372 env->ifs_clm_th_l[1], bb->phy_idx); 5373 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask, 5374 env->ifs_clm_th_l[2], bb->phy_idx); 5375 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask, 5376 env->ifs_clm_th_l[3], bb->phy_idx); 5377 5378 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask, 5379 env->ifs_clm_th_h[0], bb->phy_idx); 5380 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask, 5381 env->ifs_clm_th_h[1], bb->phy_idx); 5382 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask, 5383 env->ifs_clm_th_h[2], bb->phy_idx); 5384 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask, 5385 env->ifs_clm_th_h[3], bb->phy_idx); 5386 5387 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 5388 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5389 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 5390 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 5391 } 5392 5393 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev, 5394 struct rtw89_bb_ctx *bb) 5395 { 5396 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5397 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5398 const struct rtw89_ccx_regs *ccx = phy->ccx; 5399 struct rtw89_ccx_para_info para = {}; 5400 5401 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 5402 env->ifs_clm_mntr_time = 0; 5403 5404 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 5405 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, bb, ¶)) 5406 rtw89_phy_ifs_clm_set_th_reg(rtwdev, bb); 5407 5408 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true, 5409 bb->phy_idx); 5410 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true, 5411 bb->phy_idx); 5412 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true, 5413 bb->phy_idx); 5414 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true, 5415 bb->phy_idx); 5416 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true, 5417 bb->phy_idx); 5418 } 5419 5420 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 5421 struct rtw89_bb_ctx *bb, 5422 enum rtw89_env_racing_lv level) 5423 { 5424 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5425 int ret = 0; 5426 5427 if (level >= RTW89_RAC_MAX_NUM) { 5428 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5429 "[WARNING] Wrong LV=%d\n", level); 5430 return -EINVAL; 5431 } 5432 5433 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5434 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 5435 env->ccx_rac_lv, level); 5436 5437 if (env->ccx_ongoing) { 5438 if (level <= env->ccx_rac_lv) 5439 ret = -EINVAL; 5440 else 5441 env->ccx_ongoing = false; 5442 } 5443 5444 if (ret == 0) 5445 env->ccx_rac_lv = level; 5446 5447 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 5448 !ret); 5449 5450 return ret; 5451 } 5452 5453 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev, 5454 struct rtw89_bb_ctx *bb) 5455 { 5456 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5457 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5458 const struct rtw89_ccx_regs *ccx = phy->ccx; 5459 5460 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0, 5461 bb->phy_idx); 5462 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0, 5463 bb->phy_idx); 5464 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1, 5465 bb->phy_idx); 5466 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1, 5467 bb->phy_idx); 5468 5469 env->ccx_ongoing = true; 5470 } 5471 5472 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev, 5473 struct rtw89_bb_ctx *bb) 5474 { 5475 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5476 u8 i = 0; 5477 u32 res = 0; 5478 5479 env->ifs_clm_tx_ratio = 5480 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_tx, PERCENT); 5481 env->ifs_clm_edcca_excl_cca_ratio = 5482 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_edcca_excl_cca, 5483 PERCENT); 5484 env->ifs_clm_cck_fa_ratio = 5485 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckfa, PERCENT); 5486 env->ifs_clm_ofdm_fa_ratio = 5487 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmfa, PERCENT); 5488 env->ifs_clm_cck_cca_excl_fa_ratio = 5489 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckcca_excl_fa, 5490 PERCENT); 5491 env->ifs_clm_ofdm_cca_excl_fa_ratio = 5492 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmcca_excl_fa, 5493 PERCENT); 5494 env->ifs_clm_cck_fa_permil = 5495 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckfa, PERMIL); 5496 env->ifs_clm_ofdm_fa_permil = 5497 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmfa, PERMIL); 5498 5499 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 5500 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 5501 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 5502 } else { 5503 env->ifs_clm_ifs_avg[i] = 5504 rtw89_phy_ccx_idx_to_us(rtwdev, bb, 5505 env->ifs_clm_avg[i]); 5506 } 5507 5508 res = rtw89_phy_ccx_idx_to_us(rtwdev, bb, env->ifs_clm_cca[i]); 5509 res += env->ifs_clm_his[i] >> 1; 5510 if (env->ifs_clm_his[i]) 5511 res /= env->ifs_clm_his[i]; 5512 else 5513 res = 0; 5514 env->ifs_clm_cca_avg[i] = res; 5515 } 5516 5517 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5518 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 5519 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 5520 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5521 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 5522 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 5523 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5524 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 5525 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 5526 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5527 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 5528 env->ifs_clm_cck_cca_excl_fa_ratio, 5529 env->ifs_clm_ofdm_cca_excl_fa_ratio); 5530 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5531 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 5532 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 5533 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 5534 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 5535 env->ifs_clm_cca_avg[i]); 5536 } 5537 5538 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev, 5539 struct rtw89_bb_ctx *bb) 5540 { 5541 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5542 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5543 const struct rtw89_ccx_regs *ccx = phy->ccx; 5544 u8 i = 0; 5545 5546 if (rtw89_phy_read32_idx(rtwdev, ccx->ifs_total_addr, 5547 ccx->ifs_cnt_done_mask, bb->phy_idx) == 0) { 5548 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5549 "Get IFS_CLM report Fail\n"); 5550 return false; 5551 } 5552 5553 env->ifs_clm_tx = 5554 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_tx_cnt_addr, 5555 ccx->ifs_clm_tx_cnt_msk, bb->phy_idx); 5556 env->ifs_clm_edcca_excl_cca = 5557 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_tx_cnt_addr, 5558 ccx->ifs_clm_edcca_excl_cca_fa_mask, bb->phy_idx); 5559 env->ifs_clm_cckcca_excl_fa = 5560 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_cca_addr, 5561 ccx->ifs_clm_cckcca_excl_fa_mask, bb->phy_idx); 5562 env->ifs_clm_ofdmcca_excl_fa = 5563 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_cca_addr, 5564 ccx->ifs_clm_ofdmcca_excl_fa_mask, bb->phy_idx); 5565 env->ifs_clm_cckfa = 5566 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_fa_addr, 5567 ccx->ifs_clm_cck_fa_mask, bb->phy_idx); 5568 env->ifs_clm_ofdmfa = 5569 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_fa_addr, 5570 ccx->ifs_clm_ofdm_fa_mask, bb->phy_idx); 5571 5572 env->ifs_clm_his[0] = 5573 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, 5574 ccx->ifs_t1_his_mask, bb->phy_idx); 5575 env->ifs_clm_his[1] = 5576 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, 5577 ccx->ifs_t2_his_mask, bb->phy_idx); 5578 env->ifs_clm_his[2] = 5579 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, 5580 ccx->ifs_t3_his_mask, bb->phy_idx); 5581 env->ifs_clm_his[3] = 5582 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr, 5583 ccx->ifs_t4_his_mask, bb->phy_idx); 5584 5585 env->ifs_clm_avg[0] = 5586 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_l_addr, 5587 ccx->ifs_t1_avg_mask, bb->phy_idx); 5588 env->ifs_clm_avg[1] = 5589 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_l_addr, 5590 ccx->ifs_t2_avg_mask, bb->phy_idx); 5591 env->ifs_clm_avg[2] = 5592 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_h_addr, 5593 ccx->ifs_t3_avg_mask, bb->phy_idx); 5594 env->ifs_clm_avg[3] = 5595 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_h_addr, 5596 ccx->ifs_t4_avg_mask, bb->phy_idx); 5597 5598 env->ifs_clm_cca[0] = 5599 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_l_addr, 5600 ccx->ifs_t1_cca_mask, bb->phy_idx); 5601 env->ifs_clm_cca[1] = 5602 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_l_addr, 5603 ccx->ifs_t2_cca_mask, bb->phy_idx); 5604 env->ifs_clm_cca[2] = 5605 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_h_addr, 5606 ccx->ifs_t3_cca_mask, bb->phy_idx); 5607 env->ifs_clm_cca[3] = 5608 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_h_addr, 5609 ccx->ifs_t4_cca_mask, bb->phy_idx); 5610 5611 env->ifs_clm_total_ifs = 5612 rtw89_phy_read32_idx(rtwdev, ccx->ifs_total_addr, 5613 ccx->ifs_total_mask, bb->phy_idx); 5614 5615 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 5616 env->ifs_clm_total_ifs); 5617 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5618 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 5619 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 5620 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5621 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 5622 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 5623 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5624 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 5625 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 5626 5627 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 5628 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 5629 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5630 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 5631 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 5632 5633 rtw89_phy_ifs_clm_get_utility(rtwdev, bb); 5634 5635 return true; 5636 } 5637 5638 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 5639 struct rtw89_bb_ctx *bb, 5640 struct rtw89_ccx_para_info *para) 5641 { 5642 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5643 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5644 const struct rtw89_ccx_regs *ccx = phy->ccx; 5645 u32 period = 0; 5646 u32 unit_idx = 0; 5647 5648 if (para->mntr_time == 0) { 5649 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5650 "[WARN] MNTR_TIME is 0\n"); 5651 return -EINVAL; 5652 } 5653 5654 if (rtw89_phy_ccx_racing_ctrl(rtwdev, bb, para->rac_lv)) 5655 return -EINVAL; 5656 5657 if (para->mntr_time != env->ifs_clm_mntr_time) { 5658 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 5659 &period, &unit_idx); 5660 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, 5661 ccx->ifs_clm_period_mask, period, bb->phy_idx); 5662 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, 5663 ccx->ifs_clm_cnt_unit_mask, 5664 unit_idx, bb->phy_idx); 5665 5666 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5667 "Update IFS-CLM time ((%d)) -> ((%d))\n", 5668 env->ifs_clm_mntr_time, para->mntr_time); 5669 5670 env->ifs_clm_mntr_time = para->mntr_time; 5671 env->ccx_period = (u16)period; 5672 env->ccx_unit_idx = (u8)unit_idx; 5673 } 5674 5675 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, bb, para)) { 5676 env->ifs_clm_app = para->ifs_clm_app; 5677 rtw89_phy_ifs_clm_set_th_reg(rtwdev, bb); 5678 } 5679 5680 return 0; 5681 } 5682 5683 static void __rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev, 5684 struct rtw89_bb_ctx *bb) 5685 { 5686 struct rtw89_env_monitor_info *env = &bb->env_monitor; 5687 struct rtw89_ccx_para_info para = {}; 5688 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 5689 5690 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 5691 if (env->ccx_manual_ctrl) { 5692 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5693 "CCX in manual ctrl\n"); 5694 return; 5695 } 5696 5697 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5698 "BB-%d env_monitor track\n", bb->phy_idx); 5699 5700 /* only ifs_clm for now */ 5701 if (rtw89_phy_ifs_clm_get_result(rtwdev, bb)) 5702 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 5703 5704 rtw89_phy_ccx_racing_release(rtwdev, bb); 5705 para.mntr_time = 1900; 5706 para.rac_lv = RTW89_RAC_LV_1; 5707 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 5708 5709 if (rtw89_phy_ifs_clm_set(rtwdev, bb, ¶) == 0) 5710 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 5711 if (chk_result) 5712 rtw89_phy_ccx_trigger(rtwdev, bb); 5713 5714 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5715 "get_result=0x%x, chk_result:0x%x\n", 5716 env->ccx_watchdog_result, chk_result); 5717 } 5718 5719 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 5720 { 5721 struct rtw89_bb_ctx *bb; 5722 5723 rtw89_for_each_active_bb(rtwdev, bb) 5724 __rtw89_phy_env_monitor_track(rtwdev, bb); 5725 } 5726 5727 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 5728 { 5729 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM || 5730 *ie_page == RTW89_RSVD_9) 5731 return false; 5732 else if (*ie_page > RTW89_RSVD_9) 5733 *ie_page -= 1; 5734 5735 return true; 5736 } 5737 5738 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 5739 { 5740 static const u8 ie_page_shift = 2; 5741 5742 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 5743 } 5744 5745 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 5746 enum rtw89_phy_status_bitmap ie_page, 5747 enum rtw89_phy_idx phy_idx) 5748 { 5749 u32 addr; 5750 5751 if (!rtw89_physts_ie_page_valid(&ie_page)) 5752 return 0; 5753 5754 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 5755 5756 return rtw89_phy_read32_idx(rtwdev, addr, MASKDWORD, phy_idx); 5757 } 5758 5759 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 5760 enum rtw89_phy_status_bitmap ie_page, 5761 u32 val, enum rtw89_phy_idx phy_idx) 5762 { 5763 const struct rtw89_chip_info *chip = rtwdev->chip; 5764 u32 addr; 5765 5766 if (!rtw89_physts_ie_page_valid(&ie_page)) 5767 return; 5768 5769 if (chip->chip_id == RTL8852A) 5770 val &= B_PHY_STS_BITMAP_MSK_52A; 5771 5772 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 5773 rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx); 5774 } 5775 5776 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 5777 enum rtw89_phy_status_bitmap bitmap, 5778 enum rtw89_phy_status_ie_type ie, 5779 bool enable, enum rtw89_phy_idx phy_idx) 5780 { 5781 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap, phy_idx); 5782 5783 if (enable) 5784 val |= BIT(ie); 5785 else 5786 val &= ~BIT(ie); 5787 5788 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val, phy_idx); 5789 } 5790 5791 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 5792 bool enable, 5793 enum rtw89_phy_idx phy_idx) 5794 { 5795 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5796 const struct rtw89_physts_regs *physts = phy->physts; 5797 5798 if (enable) { 5799 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr, 5800 physts->dis_trigger_fail_mask, phy_idx); 5801 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr, 5802 physts->dis_trigger_brk_mask, phy_idx); 5803 } else { 5804 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr, 5805 physts->dis_trigger_fail_mask, phy_idx); 5806 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr, 5807 physts->dis_trigger_brk_mask, phy_idx); 5808 } 5809 } 5810 5811 static void __rtw89_physts_parsing_init(struct rtw89_dev *rtwdev, 5812 enum rtw89_phy_idx phy_idx) 5813 { 5814 u8 i; 5815 5816 rtw89_physts_enable_fail_report(rtwdev, false, phy_idx); 5817 5818 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 5819 if (i >= RTW89_CCK_PKT) 5820 rtw89_physts_enable_ie_bitmap(rtwdev, i, 5821 RTW89_PHYSTS_IE09_FTR_0, 5822 true, phy_idx); 5823 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 5824 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 5825 continue; 5826 rtw89_physts_enable_ie_bitmap(rtwdev, i, 5827 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 5828 true, phy_idx); 5829 } 5830 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 5831 RTW89_PHYSTS_IE13_DL_MU_DEF, true, phy_idx); 5832 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 5833 RTW89_PHYSTS_IE13_DL_MU_DEF, true, phy_idx); 5834 5835 /* force IE01 for channel index, only channel field is valid */ 5836 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 5837 RTW89_PHYSTS_IE01_CMN_OFDM, true, phy_idx); 5838 } 5839 5840 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 5841 { 5842 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_0); 5843 if (rtwdev->dbcc_en) 5844 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_1); 5845 } 5846 5847 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, 5848 struct rtw89_bb_ctx *bb, int type) 5849 { 5850 const struct rtw89_chip_info *chip = rtwdev->chip; 5851 const struct rtw89_phy_dig_gain_cfg *cfg; 5852 struct rtw89_dig_info *dig = &bb->dig; 5853 const char *msg; 5854 u8 i; 5855 s8 gain_base; 5856 s8 *gain_arr; 5857 u32 tmp; 5858 5859 switch (type) { 5860 case RTW89_DIG_GAIN_LNA_G: 5861 gain_arr = dig->lna_gain_g; 5862 gain_base = LNA0_GAIN; 5863 cfg = chip->dig_table->cfg_lna_g; 5864 msg = "lna_gain_g"; 5865 break; 5866 case RTW89_DIG_GAIN_TIA_G: 5867 gain_arr = dig->tia_gain_g; 5868 gain_base = TIA0_GAIN_G; 5869 cfg = chip->dig_table->cfg_tia_g; 5870 msg = "tia_gain_g"; 5871 break; 5872 case RTW89_DIG_GAIN_LNA_A: 5873 gain_arr = dig->lna_gain_a; 5874 gain_base = LNA0_GAIN; 5875 cfg = chip->dig_table->cfg_lna_a; 5876 msg = "lna_gain_a"; 5877 break; 5878 case RTW89_DIG_GAIN_TIA_A: 5879 gain_arr = dig->tia_gain_a; 5880 gain_base = TIA0_GAIN_A; 5881 cfg = chip->dig_table->cfg_tia_a; 5882 msg = "tia_gain_a"; 5883 break; 5884 default: 5885 return; 5886 } 5887 5888 for (i = 0; i < cfg->size; i++) { 5889 tmp = rtw89_phy_read32_idx(rtwdev, cfg->table[i].addr, 5890 cfg->table[i].mask, bb->phy_idx); 5891 tmp >>= DIG_GAIN_SHIFT; 5892 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 5893 gain_base += DIG_GAIN; 5894 5895 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 5896 msg, i, gain_arr[i]); 5897 } 5898 } 5899 5900 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev, 5901 struct rtw89_bb_ctx *bb) 5902 { 5903 struct rtw89_dig_info *dig = &bb->dig; 5904 u32 tmp; 5905 u8 i; 5906 5907 if (!rtwdev->hal.support_igi) 5908 return; 5909 5910 tmp = rtw89_phy_read32_idx(rtwdev, R_PATH0_IB_PKPW, 5911 B_PATH0_IB_PKPW_MSK, bb->phy_idx); 5912 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 5913 dig->ib_pbk = rtw89_phy_read32_idx(rtwdev, R_PATH0_IB_PBK, 5914 B_PATH0_IB_PBK_MSK, bb->phy_idx); 5915 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 5916 dig->ib_pkpwr, dig->ib_pbk); 5917 5918 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 5919 rtw89_phy_dig_read_gain_table(rtwdev, bb, i); 5920 } 5921 5922 static const u8 rssi_nolink = 22; 5923 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 5924 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 5925 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 5926 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 5927 5928 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev, 5929 struct rtw89_bb_ctx *bb) 5930 { 5931 struct rtw89_phy_ch_info *ch_info = &bb->ch_info; 5932 struct rtw89_dig_info *dig = &bb->dig; 5933 bool is_linked = rtwdev->total_sta_assoc > 0; 5934 5935 if (is_linked) { 5936 dig->igi_rssi = ch_info->rssi_min >> 1; 5937 } else { 5938 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 5939 dig->igi_rssi = rssi_nolink; 5940 } 5941 } 5942 5943 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev, 5944 struct rtw89_bb_ctx *bb) 5945 { 5946 const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx); 5947 struct rtw89_dig_info *dig = &bb->dig; 5948 bool is_linked = rtwdev->total_sta_assoc > 0; 5949 const u16 *fa_th_src = NULL; 5950 5951 switch (chan->band_type) { 5952 case RTW89_BAND_2G: 5953 dig->lna_gain = dig->lna_gain_g; 5954 dig->tia_gain = dig->tia_gain_g; 5955 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 5956 dig->force_gaincode_idx_en = false; 5957 dig->dyn_pd_th_en = true; 5958 break; 5959 case RTW89_BAND_5G: 5960 default: 5961 dig->lna_gain = dig->lna_gain_a; 5962 dig->tia_gain = dig->tia_gain_a; 5963 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 5964 dig->force_gaincode_idx_en = true; 5965 dig->dyn_pd_th_en = true; 5966 break; 5967 } 5968 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 5969 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 5970 } 5971 5972 static const u8 pd_low_th_offset = 16, dynamic_igi_min = 0x20; 5973 static const u8 igi_max_performance_mode = 0x5a; 5974 static const u8 dynamic_pd_threshold_max; 5975 5976 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev, 5977 struct rtw89_bb_ctx *bb) 5978 { 5979 struct rtw89_dig_info *dig = &bb->dig; 5980 5981 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 5982 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 5983 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 5984 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 5985 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 5986 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 5987 5988 dig->dyn_igi_max = igi_max_performance_mode; 5989 dig->dyn_igi_min = dynamic_igi_min; 5990 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 5991 dig->pd_low_th_ofst = pd_low_th_offset; 5992 dig->is_linked_pre = false; 5993 } 5994 5995 static void __rtw89_phy_dig_init(struct rtw89_dev *rtwdev, 5996 struct rtw89_bb_ctx *bb) 5997 { 5998 rtw89_debug(rtwdev, RTW89_DBG_DIG, "BB-%d dig_init\n", bb->phy_idx); 5999 6000 rtw89_phy_dig_update_gain_para(rtwdev, bb); 6001 rtw89_phy_dig_reset(rtwdev, bb); 6002 } 6003 6004 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 6005 { 6006 struct rtw89_bb_ctx *bb; 6007 6008 rtw89_for_each_capab_bb(rtwdev, bb) 6009 __rtw89_phy_dig_init(rtwdev, bb); 6010 } 6011 6012 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, 6013 struct rtw89_bb_ctx *bb, u8 rssi) 6014 { 6015 struct rtw89_dig_info *dig = &bb->dig; 6016 u8 lna_idx; 6017 6018 if (rssi < dig->igi_rssi_th[0]) 6019 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 6020 else if (rssi < dig->igi_rssi_th[1]) 6021 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 6022 else if (rssi < dig->igi_rssi_th[2]) 6023 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 6024 else if (rssi < dig->igi_rssi_th[3]) 6025 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 6026 else if (rssi < dig->igi_rssi_th[4]) 6027 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 6028 else 6029 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 6030 6031 return lna_idx; 6032 } 6033 6034 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, 6035 struct rtw89_bb_ctx *bb, u8 rssi) 6036 { 6037 struct rtw89_dig_info *dig = &bb->dig; 6038 u8 tia_idx; 6039 6040 if (rssi < dig->igi_rssi_th[0]) 6041 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 6042 else 6043 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 6044 6045 return tia_idx; 6046 } 6047 6048 #define IB_PBK_BASE 110 6049 #define WB_RSSI_BASE 10 6050 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, 6051 struct rtw89_bb_ctx *bb, u8 rssi, 6052 struct rtw89_agc_gaincode_set *set) 6053 { 6054 struct rtw89_dig_info *dig = &bb->dig; 6055 s8 lna_gain = dig->lna_gain[set->lna_idx]; 6056 s8 tia_gain = dig->tia_gain[set->tia_idx]; 6057 s32 wb_rssi = rssi + lna_gain + tia_gain; 6058 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 6059 u8 rxb_idx; 6060 6061 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 6062 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 6063 6064 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 6065 wb_rssi, rxb_idx_tmp); 6066 6067 return rxb_idx; 6068 } 6069 6070 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, 6071 struct rtw89_bb_ctx *bb, u8 rssi, 6072 struct rtw89_agc_gaincode_set *set) 6073 { 6074 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, bb, rssi); 6075 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, bb, rssi); 6076 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, bb, rssi, set); 6077 6078 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6079 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 6080 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 6081 } 6082 6083 #define IGI_OFFSET_MAX 25 6084 #define IGI_OFFSET_MUL 2 6085 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev, 6086 struct rtw89_bb_ctx *bb) 6087 { 6088 struct rtw89_dig_info *dig = &bb->dig; 6089 struct rtw89_env_monitor_info *env = &bb->env_monitor; 6090 enum rtw89_dig_noisy_level noisy_lv; 6091 u8 igi_offset = dig->fa_rssi_ofst; 6092 u16 fa_ratio = 0; 6093 6094 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 6095 6096 if (fa_ratio < dig->fa_th[0]) 6097 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 6098 else if (fa_ratio < dig->fa_th[1]) 6099 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 6100 else if (fa_ratio < dig->fa_th[2]) 6101 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 6102 else if (fa_ratio < dig->fa_th[3]) 6103 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 6104 else 6105 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 6106 6107 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 6108 igi_offset = 0; 6109 else 6110 igi_offset += noisy_lv * IGI_OFFSET_MUL; 6111 6112 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 6113 dig->fa_rssi_ofst = igi_offset; 6114 6115 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6116 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 6117 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 6118 6119 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6120 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 6121 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 6122 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 6123 noisy_lv, igi_offset); 6124 } 6125 6126 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, 6127 struct rtw89_bb_ctx *bb, u8 lna_idx) 6128 { 6129 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 6130 6131 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_lna_init.addr, 6132 dig_regs->p0_lna_init.mask, lna_idx, bb->phy_idx); 6133 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_lna_init.addr, 6134 dig_regs->p1_lna_init.mask, lna_idx, bb->phy_idx); 6135 } 6136 6137 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, 6138 struct rtw89_bb_ctx *bb, u8 tia_idx) 6139 { 6140 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 6141 6142 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_tia_init.addr, 6143 dig_regs->p0_tia_init.mask, tia_idx, bb->phy_idx); 6144 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_tia_init.addr, 6145 dig_regs->p1_tia_init.mask, tia_idx, bb->phy_idx); 6146 } 6147 6148 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, 6149 struct rtw89_bb_ctx *bb, u8 rxb_idx) 6150 { 6151 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 6152 6153 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_rxb_init.addr, 6154 dig_regs->p0_rxb_init.mask, rxb_idx, bb->phy_idx); 6155 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_rxb_init.addr, 6156 dig_regs->p1_rxb_init.mask, rxb_idx, bb->phy_idx); 6157 } 6158 6159 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 6160 struct rtw89_bb_ctx *bb, 6161 const struct rtw89_agc_gaincode_set set) 6162 { 6163 if (!rtwdev->hal.support_igi) 6164 return; 6165 6166 rtw89_phy_dig_set_lna_idx(rtwdev, bb, set.lna_idx); 6167 rtw89_phy_dig_set_tia_idx(rtwdev, bb, set.tia_idx); 6168 rtw89_phy_dig_set_rxb_idx(rtwdev, bb, set.rxb_idx); 6169 6170 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 6171 set.lna_idx, set.tia_idx, set.rxb_idx); 6172 } 6173 6174 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 6175 struct rtw89_bb_ctx *bb, 6176 bool enable) 6177 { 6178 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 6179 6180 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 6181 dig_regs->p0_p20_pagcugc_en.mask, enable, bb->phy_idx); 6182 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 6183 dig_regs->p0_s20_pagcugc_en.mask, enable, bb->phy_idx); 6184 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 6185 dig_regs->p1_p20_pagcugc_en.mask, enable, bb->phy_idx); 6186 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 6187 dig_regs->p1_s20_pagcugc_en.mask, enable, bb->phy_idx); 6188 6189 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 6190 } 6191 6192 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev, 6193 struct rtw89_bb_ctx *bb) 6194 { 6195 struct rtw89_dig_info *dig = &bb->dig; 6196 6197 if (!rtwdev->hal.support_igi) 6198 return; 6199 6200 if (dig->force_gaincode_idx_en) { 6201 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->force_gaincode); 6202 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6203 "Force gaincode index enabled.\n"); 6204 } else { 6205 rtw89_phy_dig_gaincode_by_rssi(rtwdev, bb, dig->igi_fa_rssi, 6206 &dig->cur_gaincode); 6207 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->cur_gaincode); 6208 } 6209 } 6210 6211 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, 6212 struct rtw89_bb_ctx *bb, 6213 u8 rssi, bool enable) 6214 { 6215 const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx); 6216 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 6217 enum rtw89_bandwidth cbw = chan->band_width; 6218 struct rtw89_dig_info *dig = &bb->dig; 6219 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 6220 u8 ofdm_cca_th; 6221 s8 cck_cca_th; 6222 u32 pd_val = 0; 6223 6224 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX) 6225 under_region += PD_TH_SB_FLTR_CMP_VAL; 6226 6227 switch (cbw) { 6228 case RTW89_CHANNEL_WIDTH_40: 6229 under_region += PD_TH_BW40_CMP_VAL; 6230 break; 6231 case RTW89_CHANNEL_WIDTH_80: 6232 under_region += PD_TH_BW80_CMP_VAL; 6233 break; 6234 case RTW89_CHANNEL_WIDTH_160: 6235 under_region += PD_TH_BW160_CMP_VAL; 6236 break; 6237 case RTW89_CHANNEL_WIDTH_20: 6238 fallthrough; 6239 default: 6240 under_region += PD_TH_BW20_CMP_VAL; 6241 break; 6242 } 6243 6244 dig->dyn_pd_th_max = dig->igi_rssi; 6245 6246 final_rssi = min_t(u8, rssi, dig->igi_rssi); 6247 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 6248 PD_TH_MAX_RSSI + under_region); 6249 6250 if (enable) { 6251 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 6252 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6253 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 6254 final_rssi, ofdm_cca_th, under_region, pd_val); 6255 } else { 6256 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6257 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 6258 } 6259 6260 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg, 6261 dig_regs->pd_lower_bound_mask, pd_val, bb->phy_idx); 6262 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg, 6263 dig_regs->pd_spatial_reuse_en, enable, bb->phy_idx); 6264 6265 if (!rtwdev->hal.support_cckpd) 6266 return; 6267 6268 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 6269 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 6270 6271 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6272 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 6273 final_rssi, cck_cca_th, under_region, pd_val); 6274 6275 rtw89_phy_write32_idx(rtwdev, dig_regs->bmode_pd_reg, 6276 dig_regs->bmode_cca_rssi_limit_en, enable, bb->phy_idx); 6277 rtw89_phy_write32_idx(rtwdev, dig_regs->bmode_pd_lower_bound_reg, 6278 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val, bb->phy_idx); 6279 } 6280 6281 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb) 6282 { 6283 struct rtw89_dig_info *dig = &bb->dig; 6284 6285 dig->bypass_dig = false; 6286 rtw89_phy_dig_para_reset(rtwdev, bb); 6287 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->force_gaincode); 6288 rtw89_phy_dig_dyn_pd_th(rtwdev, bb, rssi_nolink, false); 6289 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, false); 6290 rtw89_phy_dig_update_para(rtwdev, bb); 6291 } 6292 6293 #define IGI_RSSI_MIN 10 6294 #define ABS_IGI_MIN 0xc 6295 static void __rtw89_phy_dig(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb) 6296 { 6297 struct rtw89_dig_info *dig = &bb->dig; 6298 bool is_linked = rtwdev->total_sta_assoc > 0; 6299 u8 igi_min; 6300 6301 if (unlikely(dig->bypass_dig)) { 6302 dig->bypass_dig = false; 6303 return; 6304 } 6305 6306 rtw89_debug(rtwdev, RTW89_DBG_DIG, "BB-%d dig track\n", bb->phy_idx); 6307 6308 rtw89_phy_dig_update_rssi_info(rtwdev, bb); 6309 6310 if (!dig->is_linked_pre && is_linked) { 6311 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 6312 rtw89_phy_dig_update_para(rtwdev, bb); 6313 dig->igi_fa_rssi = dig->igi_rssi; 6314 } else if (dig->is_linked_pre && !is_linked) { 6315 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 6316 rtw89_phy_dig_update_para(rtwdev, bb); 6317 dig->igi_fa_rssi = dig->igi_rssi; 6318 } 6319 dig->is_linked_pre = is_linked; 6320 6321 rtw89_phy_dig_igi_offset_by_env(rtwdev, bb); 6322 6323 igi_min = max_t(int, dig->igi_rssi - IGI_RSSI_MIN, 0); 6324 dig->dyn_igi_max = min(igi_min + IGI_OFFSET_MAX, igi_max_performance_mode); 6325 dig->dyn_igi_min = max(igi_min, ABS_IGI_MIN); 6326 6327 if (dig->dyn_igi_max >= dig->dyn_igi_min) { 6328 dig->igi_fa_rssi += dig->fa_rssi_ofst; 6329 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 6330 dig->dyn_igi_max); 6331 } else { 6332 dig->igi_fa_rssi = dig->dyn_igi_max; 6333 } 6334 6335 rtw89_debug(rtwdev, RTW89_DBG_DIG, 6336 "rssi=%03d, dyn_joint(max,min)=(%d,%d), final_rssi=%d\n", 6337 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 6338 dig->igi_fa_rssi); 6339 6340 rtw89_phy_dig_config_igi(rtwdev, bb); 6341 6342 rtw89_phy_dig_dyn_pd_th(rtwdev, bb, dig->igi_fa_rssi, dig->dyn_pd_th_en); 6343 6344 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 6345 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, true); 6346 else 6347 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, false); 6348 } 6349 6350 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 6351 { 6352 struct rtw89_bb_ctx *bb; 6353 6354 rtw89_for_each_active_bb(rtwdev, bb) 6355 __rtw89_phy_dig(rtwdev, bb); 6356 } 6357 6358 static void __rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev *rtwdev, 6359 struct rtw89_sta_link *rtwsta_link) 6360 { 6361 struct rtw89_hal *hal = &rtwdev->hal; 6362 u8 rssi_a, rssi_b; 6363 u32 candidate; 6364 6365 rssi_a = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_A]); 6366 rssi_b = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_B]); 6367 6368 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 6369 candidate = RF_A; 6370 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 6371 candidate = RF_B; 6372 else 6373 return; 6374 6375 if (hal->antenna_tx == candidate) 6376 return; 6377 6378 hal->antenna_tx = candidate; 6379 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta_link); 6380 6381 if (hal->antenna_tx == RF_A) { 6382 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 6383 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 6384 } else if (hal->antenna_tx == RF_B) { 6385 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 6386 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 6387 } 6388 } 6389 6390 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 6391 { 6392 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6393 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6394 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6395 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 6396 struct rtw89_vif_link *rtwvif_link; 6397 struct rtw89_sta_link *rtwsta_link; 6398 unsigned int link_id; 6399 bool *done = data; 6400 6401 if (WARN(ieee80211_vif_is_mld(vif), "MLD mix path_div\n")) 6402 return; 6403 6404 if (sta->tdls) 6405 return; 6406 6407 if (*done) 6408 return; 6409 6410 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6411 rtwvif_link = rtwsta_link->rtwvif_link; 6412 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION) 6413 continue; 6414 6415 *done = true; 6416 __rtw89_phy_tx_path_div_sta_iter(rtwdev, rtwsta_link); 6417 return; 6418 } 6419 } 6420 6421 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 6422 { 6423 struct rtw89_hal *hal = &rtwdev->hal; 6424 bool done = false; 6425 6426 if (!hal->tx_path_diversity) 6427 return; 6428 6429 ieee80211_iterate_stations_atomic(rtwdev->hw, 6430 rtw89_phy_tx_path_div_sta_iter, 6431 &done); 6432 } 6433 6434 #define ANTDIV_MAIN 0 6435 #define ANTDIV_AUX 1 6436 6437 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev) 6438 { 6439 struct rtw89_hal *hal = &rtwdev->hal; 6440 u8 default_ant, optional_ant; 6441 6442 if (!hal->ant_diversity || hal->antenna_tx == 0) 6443 return; 6444 6445 if (hal->antenna_tx == RF_B) { 6446 default_ant = ANTDIV_AUX; 6447 optional_ant = ANTDIV_MAIN; 6448 } else { 6449 default_ant = ANTDIV_MAIN; 6450 optional_ant = ANTDIV_AUX; 6451 } 6452 6453 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL, 6454 default_ant, RTW89_PHY_0); 6455 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI, 6456 default_ant, RTW89_PHY_0); 6457 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT, 6458 optional_ant, RTW89_PHY_0); 6459 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI, 6460 default_ant, RTW89_PHY_0); 6461 } 6462 6463 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev) 6464 { 6465 struct rtw89_hal *hal = &rtwdev->hal; 6466 6467 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A; 6468 hal->antenna_tx = hal->antenna_rx; 6469 } 6470 6471 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev) 6472 { 6473 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 6474 struct rtw89_hal *hal = &rtwdev->hal; 6475 bool no_change = false; 6476 u8 main_rssi, aux_rssi; 6477 u8 main_evm, aux_evm; 6478 u32 candidate; 6479 6480 antdiv->get_stats = false; 6481 antdiv->training_count = 0; 6482 6483 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats); 6484 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats); 6485 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats); 6486 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats); 6487 6488 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH) 6489 candidate = RF_A; 6490 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH) 6491 candidate = RF_B; 6492 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 6493 candidate = RF_A; 6494 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 6495 candidate = RF_B; 6496 else 6497 no_change = true; 6498 6499 if (no_change) { 6500 /* swap back from training antenna to original */ 6501 rtw89_phy_swap_hal_antenna(rtwdev); 6502 return; 6503 } 6504 6505 hal->antenna_tx = candidate; 6506 hal->antenna_rx = candidate; 6507 } 6508 6509 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev) 6510 { 6511 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 6512 u64 state_period; 6513 6514 if (antdiv->training_count % 2 == 0) { 6515 if (antdiv->training_count == 0) 6516 rtw89_phy_antdiv_sts_reset(rtwdev); 6517 6518 antdiv->get_stats = true; 6519 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL); 6520 } else { 6521 antdiv->get_stats = false; 6522 state_period = msecs_to_jiffies(ANTDIV_DELAY); 6523 6524 rtw89_phy_swap_hal_antenna(rtwdev); 6525 rtw89_phy_antdiv_set_ant(rtwdev); 6526 } 6527 6528 antdiv->training_count++; 6529 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->antdiv_work, 6530 state_period); 6531 } 6532 6533 void rtw89_phy_antdiv_work(struct wiphy *wiphy, struct wiphy_work *work) 6534 { 6535 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 6536 antdiv_work.work); 6537 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 6538 6539 lockdep_assert_wiphy(wiphy); 6540 6541 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) { 6542 rtw89_phy_antdiv_training_state(rtwdev); 6543 } else { 6544 rtw89_phy_antdiv_decision_state(rtwdev); 6545 rtw89_phy_antdiv_set_ant(rtwdev); 6546 } 6547 } 6548 6549 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev) 6550 { 6551 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 6552 struct rtw89_hal *hal = &rtwdev->hal; 6553 u8 rssi, rssi_pre; 6554 6555 if (!hal->ant_diversity || hal->ant_diversity_fixed) 6556 return; 6557 6558 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats); 6559 rssi_pre = antdiv->rssi_pre; 6560 antdiv->rssi_pre = rssi; 6561 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 6562 6563 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH) 6564 return; 6565 6566 antdiv->training_count = 0; 6567 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->antdiv_work, 0); 6568 } 6569 6570 static void __rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev, 6571 struct rtw89_bb_ctx *bb) 6572 { 6573 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 6574 "BB-%d env_monitor init\n", bb->phy_idx); 6575 6576 rtw89_phy_ccx_top_setting_init(rtwdev, bb); 6577 rtw89_phy_ifs_clm_setting_init(rtwdev, bb); 6578 } 6579 6580 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 6581 { 6582 struct rtw89_bb_ctx *bb; 6583 6584 rtw89_for_each_capab_bb(rtwdev, bb) 6585 __rtw89_phy_env_monitor_init(rtwdev, bb); 6586 } 6587 6588 static void __rtw89_phy_edcca_init(struct rtw89_dev *rtwdev, 6589 struct rtw89_bb_ctx *bb) 6590 { 6591 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 6592 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak; 6593 6594 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, "BB-%d edcca init\n", bb->phy_idx); 6595 6596 memset(edcca_bak, 0, sizeof(*edcca_bak)); 6597 6598 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) { 6599 rtw89_phy_set_phy_regs(rtwdev, R_TXGATING, B_TXGATING_EN, 0); 6600 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_VAL, 2); 6601 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_ON, 1); 6602 rtw89_phy_set_phy_regs(rtwdev, R_SPOOF_CG, B_SPOOF_CG_EN, 0); 6603 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_CG_EN, 0); 6604 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 0); 6605 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 0); 6606 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 1); 6607 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 1); 6608 } 6609 6610 rtw89_phy_write32_idx(rtwdev, edcca_regs->tx_collision_t2r_st, 6611 edcca_regs->tx_collision_t2r_st_mask, 0x29, bb->phy_idx); 6612 } 6613 6614 static void rtw89_phy_edcca_init(struct rtw89_dev *rtwdev) 6615 { 6616 struct rtw89_bb_ctx *bb; 6617 6618 rtw89_for_each_capab_bb(rtwdev, bb) 6619 __rtw89_phy_edcca_init(rtwdev, bb); 6620 } 6621 6622 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 6623 { 6624 rtw89_phy_stat_init(rtwdev); 6625 6626 rtw89_chip_bb_sethw(rtwdev); 6627 6628 rtw89_phy_env_monitor_init(rtwdev); 6629 rtw89_physts_parsing_init(rtwdev); 6630 rtw89_phy_dig_init(rtwdev); 6631 rtw89_phy_cfo_init(rtwdev); 6632 rtw89_phy_bb_wrap_init(rtwdev); 6633 rtw89_phy_edcca_init(rtwdev); 6634 rtw89_phy_ch_info_init(rtwdev); 6635 rtw89_phy_ul_tb_info_init(rtwdev); 6636 rtw89_phy_antdiv_init(rtwdev); 6637 rtw89_chip_rfe_gpio(rtwdev); 6638 rtw89_phy_antdiv_set_ant(rtwdev); 6639 6640 rtw89_chip_rfk_hw_init(rtwdev); 6641 rtw89_phy_init_rf_nctl(rtwdev); 6642 rtw89_chip_rfk_init(rtwdev); 6643 rtw89_chip_set_txpwr_ctrl(rtwdev); 6644 rtw89_chip_power_trim(rtwdev); 6645 rtw89_chip_cfg_txrx_path(rtwdev); 6646 } 6647 6648 void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev) 6649 { 6650 rtw89_phy_env_monitor_init(rtwdev); 6651 rtw89_physts_parsing_init(rtwdev); 6652 } 6653 6654 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, 6655 struct rtw89_vif_link *rtwvif_link) 6656 { 6657 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6658 const struct rtw89_chip_info *chip = rtwdev->chip; 6659 const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld; 6660 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx; 6661 struct ieee80211_bss_conf *bss_conf; 6662 u8 bss_color; 6663 6664 rcu_read_lock(); 6665 6666 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 6667 if (!bss_conf->he_support || !vif->cfg.assoc) { 6668 rcu_read_unlock(); 6669 return; 6670 } 6671 6672 bss_color = bss_conf->he_bss_color.color; 6673 6674 rcu_read_unlock(); 6675 6676 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1, 6677 phy_idx); 6678 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT, 6679 bss_color, phy_idx); 6680 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID, 6681 vif->cfg.aid, phy_idx); 6682 } 6683 6684 static bool rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc *desc) 6685 { 6686 return desc->ch != 0; 6687 } 6688 6689 static bool rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc *desc, 6690 const struct rtw89_chan *chan) 6691 { 6692 if (!rfk_chan_validate_desc(desc)) 6693 return false; 6694 6695 if (desc->ch != chan->channel) 6696 return false; 6697 6698 if (desc->has_band && desc->band != chan->band_type) 6699 return false; 6700 6701 if (desc->has_bw && desc->bw != chan->band_width) 6702 return false; 6703 6704 return true; 6705 } 6706 6707 struct rfk_chan_iter_data { 6708 const struct rtw89_rfk_chan_desc desc; 6709 unsigned int found; 6710 }; 6711 6712 static int rfk_chan_iter_search(const struct rtw89_chan *chan, void *data) 6713 { 6714 struct rfk_chan_iter_data *iter_data = data; 6715 6716 if (rfk_chan_is_equivalent(&iter_data->desc, chan)) 6717 iter_data->found++; 6718 6719 return 0; 6720 } 6721 6722 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev, 6723 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr, 6724 const struct rtw89_chan *target_chan) 6725 { 6726 int sel = -1; 6727 u8 i; 6728 6729 for (i = 0; i < desc_nr; i++) { 6730 struct rfk_chan_iter_data iter_data = { 6731 .desc = desc[i], 6732 }; 6733 6734 if (rfk_chan_is_equivalent(&desc[i], target_chan)) 6735 return i; 6736 6737 rtw89_iterate_entity_chan(rtwdev, rfk_chan_iter_search, &iter_data); 6738 if (!iter_data.found && sel == -1) 6739 sel = i; 6740 } 6741 6742 if (sel == -1) { 6743 rtw89_debug(rtwdev, RTW89_DBG_RFK, 6744 "no idle rfk entry; force replace the first\n"); 6745 sel = 0; 6746 } 6747 6748 return sel; 6749 } 6750 EXPORT_SYMBOL(rtw89_rfk_chan_lookup); 6751 6752 static void 6753 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6754 { 6755 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 6756 } 6757 6758 static void 6759 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6760 { 6761 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 6762 } 6763 6764 static void 6765 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6766 { 6767 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 6768 } 6769 6770 static void 6771 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6772 { 6773 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 6774 } 6775 6776 static void 6777 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6778 { 6779 udelay(def->data); 6780 } 6781 6782 static void 6783 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 6784 [RTW89_RFK_F_WRF] = _rfk_write_rf, 6785 [RTW89_RFK_F_WM] = _rfk_write32_mask, 6786 [RTW89_RFK_F_WS] = _rfk_write32_set, 6787 [RTW89_RFK_F_WC] = _rfk_write32_clr, 6788 [RTW89_RFK_F_DELAY] = _rfk_delay, 6789 }; 6790 6791 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 6792 6793 void 6794 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 6795 { 6796 const struct rtw89_reg5_def *p = tbl->defs; 6797 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 6798 6799 for (; p < end; p++) 6800 _rfk_handler[p->flag](rtwdev, p); 6801 } 6802 EXPORT_SYMBOL(rtw89_rfk_parser); 6803 6804 #define RTW89_TSSI_FAST_MODE_NUM 4 6805 6806 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 6807 {0xD934, 0xff0000}, 6808 {0xD934, 0xff000000}, 6809 {0xD938, 0xff}, 6810 {0xD934, 0xff00}, 6811 }; 6812 6813 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 6814 {0xD930, 0xff0000}, 6815 {0xD930, 0xff000000}, 6816 {0xD934, 0xff}, 6817 {0xD930, 0xff00}, 6818 }; 6819 6820 static 6821 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 6822 enum rtw89_mac_idx mac_idx, 6823 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 6824 u32 val) 6825 { 6826 const struct rtw89_reg_def *regs; 6827 u32 reg; 6828 int i; 6829 6830 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 6831 regs = rtw89_tssi_fastmode_regs_flat; 6832 else 6833 regs = rtw89_tssi_fastmode_regs_level; 6834 6835 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 6836 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 6837 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 6838 } 6839 } 6840 6841 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 6842 {0xD91C, 0xff000000}, 6843 {0xD920, 0xff}, 6844 {0xD920, 0xff00}, 6845 {0xD920, 0xff0000}, 6846 {0xD920, 0xff000000}, 6847 {0xD924, 0xff}, 6848 {0xD924, 0xff00}, 6849 {0xD914, 0xff000000}, 6850 {0xD918, 0xff}, 6851 {0xD918, 0xff00}, 6852 {0xD918, 0xff0000}, 6853 {0xD918, 0xff000000}, 6854 {0xD91C, 0xff}, 6855 {0xD91C, 0xff00}, 6856 {0xD91C, 0xff0000}, 6857 }; 6858 6859 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 6860 {0xD910, 0xff}, 6861 {0xD910, 0xff00}, 6862 {0xD910, 0xff0000}, 6863 {0xD910, 0xff000000}, 6864 {0xD914, 0xff}, 6865 {0xD914, 0xff00}, 6866 {0xD914, 0xff0000}, 6867 {0xD908, 0xff}, 6868 {0xD908, 0xff00}, 6869 {0xD908, 0xff0000}, 6870 {0xD908, 0xff000000}, 6871 {0xD90C, 0xff}, 6872 {0xD90C, 0xff00}, 6873 {0xD90C, 0xff0000}, 6874 {0xD90C, 0xff000000}, 6875 }; 6876 6877 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 6878 enum rtw89_mac_idx mac_idx, 6879 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 6880 { 6881 const struct rtw89_chip_info *chip = rtwdev->chip; 6882 const struct rtw89_reg_def *regs; 6883 const u32 *data; 6884 u32 reg; 6885 int i; 6886 6887 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 6888 return; 6889 6890 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 6891 regs = rtw89_tssi_bandedge_regs_flat; 6892 else 6893 regs = rtw89_tssi_bandedge_regs_level; 6894 6895 data = chip->tssi_dbw_table->data[bandedge_cfg]; 6896 6897 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 6898 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 6899 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 6900 } 6901 6902 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx); 6903 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 6904 6905 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 6906 data[RTW89_TSSI_SBW20]); 6907 } 6908 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 6909 6910 static 6911 const u8 rtw89_ch_base_table[16] = {1, 0xff, 6912 36, 100, 132, 149, 0xff, 6913 1, 33, 65, 97, 129, 161, 193, 225, 0xff}; 6914 #define RTW89_CH_BASE_IDX_2G 0 6915 #define RTW89_CH_BASE_IDX_5G_FIRST 2 6916 #define RTW89_CH_BASE_IDX_5G_LAST 5 6917 #define RTW89_CH_BASE_IDX_6G_FIRST 7 6918 #define RTW89_CH_BASE_IDX_6G_LAST 14 6919 6920 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4) 6921 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0) 6922 6923 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band) 6924 { 6925 u8 chan_idx; 6926 u8 last, first; 6927 u8 idx; 6928 6929 switch (band) { 6930 case RTW89_BAND_2G: 6931 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) | 6932 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch); 6933 return chan_idx; 6934 case RTW89_BAND_5G: 6935 first = RTW89_CH_BASE_IDX_5G_FIRST; 6936 last = RTW89_CH_BASE_IDX_5G_LAST; 6937 break; 6938 case RTW89_BAND_6G: 6939 first = RTW89_CH_BASE_IDX_6G_FIRST; 6940 last = RTW89_CH_BASE_IDX_6G_LAST; 6941 break; 6942 default: 6943 rtw89_warn(rtwdev, "Unsupported band %d\n", band); 6944 return 0; 6945 } 6946 6947 for (idx = last; idx >= first; idx--) 6948 if (central_ch >= rtw89_ch_base_table[idx]) 6949 break; 6950 6951 if (idx < first) { 6952 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch); 6953 return 0; 6954 } 6955 6956 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) | 6957 FIELD_PREP(RTW89_CH_OFFSET_MASK, 6958 (central_ch - rtw89_ch_base_table[idx]) >> 1); 6959 return chan_idx; 6960 } 6961 EXPORT_SYMBOL(rtw89_encode_chan_idx); 6962 6963 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 6964 u8 *ch, enum nl80211_band *band) 6965 { 6966 u8 idx, offset; 6967 6968 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx); 6969 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx); 6970 6971 if (idx == RTW89_CH_BASE_IDX_2G) { 6972 *band = NL80211_BAND_2GHZ; 6973 *ch = offset; 6974 return; 6975 } 6976 6977 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ; 6978 *ch = rtw89_ch_base_table[idx] + (offset << 1); 6979 } 6980 EXPORT_SYMBOL(rtw89_decode_chan_idx); 6981 6982 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, 6983 struct rtw89_bb_ctx *bb, bool scan) 6984 { 6985 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 6986 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak; 6987 6988 if (scan) { 6989 edcca_bak->a = 6990 rtw89_phy_read32_idx(rtwdev, edcca_regs->edcca_level, 6991 edcca_regs->edcca_mask, bb->phy_idx); 6992 edcca_bak->p = 6993 rtw89_phy_read32_idx(rtwdev, edcca_regs->edcca_level, 6994 edcca_regs->edcca_p_mask, bb->phy_idx); 6995 edcca_bak->ppdu = 6996 rtw89_phy_read32_idx(rtwdev, edcca_regs->ppdu_level, 6997 edcca_regs->ppdu_mask, bb->phy_idx); 6998 6999 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level, 7000 edcca_regs->edcca_mask, EDCCA_MAX, bb->phy_idx); 7001 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level, 7002 edcca_regs->edcca_p_mask, EDCCA_MAX, bb->phy_idx); 7003 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level, 7004 edcca_regs->ppdu_mask, EDCCA_MAX, bb->phy_idx); 7005 } else { 7006 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level, 7007 edcca_regs->edcca_mask, 7008 edcca_bak->a, bb->phy_idx); 7009 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level, 7010 edcca_regs->edcca_p_mask, 7011 edcca_bak->p, bb->phy_idx); 7012 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level, 7013 edcca_regs->ppdu_mask, 7014 edcca_bak->ppdu, bb->phy_idx); 7015 } 7016 } 7017 7018 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb) 7019 { 7020 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 7021 const struct rtw89_edcca_p_regs *edcca_p_regs; 7022 bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80; 7023 s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80; 7024 u8 path, per20_bitmap; 7025 u8 pwdb[8]; 7026 u32 tmp; 7027 7028 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA)) 7029 return; 7030 7031 if (bb->phy_idx == RTW89_PHY_1) 7032 edcca_p_regs = &edcca_regs->p[RTW89_PHY_1]; 7033 else 7034 edcca_p_regs = &edcca_regs->p[RTW89_PHY_0]; 7035 7036 if (rtwdev->chip->chip_id == RTL8922A) 7037 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 7038 edcca_regs->rpt_sel_be_mask, 0); 7039 7040 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 7041 edcca_p_regs->rpt_sel_mask, 0); 7042 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); 7043 path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK); 7044 flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80); 7045 flag_s40 = u32_get_bits(tmp, B_EDCCA_RPT_B_S40); 7046 flag_s20 = u32_get_bits(tmp, B_EDCCA_RPT_B_S20); 7047 flag_p20 = u32_get_bits(tmp, B_EDCCA_RPT_B_P20); 7048 flag_fb = u32_get_bits(tmp, B_EDCCA_RPT_B_FB); 7049 pwdb_s20 = u32_get_bits(tmp, MASKBYTE1); 7050 pwdb_p20 = u32_get_bits(tmp, MASKBYTE2); 7051 pwdb_fb = u32_get_bits(tmp, MASKBYTE3); 7052 7053 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 7054 edcca_p_regs->rpt_sel_mask, 4); 7055 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); 7056 pwdb_s80 = u32_get_bits(tmp, MASKBYTE1); 7057 pwdb_s40 = u32_get_bits(tmp, MASKBYTE2); 7058 7059 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_p_regs->rpt_a, 7060 MASKBYTE0); 7061 7062 if (rtwdev->chip->chip_id == RTL8922A) { 7063 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 7064 edcca_regs->rpt_sel_be_mask, 4); 7065 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); 7066 pwdb[0] = u32_get_bits(tmp, MASKBYTE3); 7067 pwdb[1] = u32_get_bits(tmp, MASKBYTE2); 7068 pwdb[2] = u32_get_bits(tmp, MASKBYTE1); 7069 pwdb[3] = u32_get_bits(tmp, MASKBYTE0); 7070 7071 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 7072 edcca_regs->rpt_sel_be_mask, 5); 7073 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b); 7074 pwdb[4] = u32_get_bits(tmp, MASKBYTE3); 7075 pwdb[5] = u32_get_bits(tmp, MASKBYTE2); 7076 pwdb[6] = u32_get_bits(tmp, MASKBYTE1); 7077 pwdb[7] = u32_get_bits(tmp, MASKBYTE0); 7078 } else { 7079 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 7080 edcca_p_regs->rpt_sel_mask, 0); 7081 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a); 7082 pwdb[0] = u32_get_bits(tmp, MASKBYTE3); 7083 pwdb[1] = u32_get_bits(tmp, MASKBYTE2); 7084 7085 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 7086 edcca_p_regs->rpt_sel_mask, 1); 7087 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a); 7088 pwdb[2] = u32_get_bits(tmp, MASKBYTE3); 7089 pwdb[3] = u32_get_bits(tmp, MASKBYTE2); 7090 7091 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 7092 edcca_p_regs->rpt_sel_mask, 2); 7093 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a); 7094 pwdb[4] = u32_get_bits(tmp, MASKBYTE3); 7095 pwdb[5] = u32_get_bits(tmp, MASKBYTE2); 7096 7097 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel, 7098 edcca_p_regs->rpt_sel_mask, 3); 7099 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a); 7100 pwdb[6] = u32_get_bits(tmp, MASKBYTE3); 7101 pwdb[7] = u32_get_bits(tmp, MASKBYTE2); 7102 } 7103 7104 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 7105 "[EDCCA]: edcca_bitmap = %04x\n", per20_bitmap); 7106 7107 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 7108 "[EDCCA]: pwdb per20{0,1,2,3,4,5,6,7} = {%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n", 7109 pwdb[0], pwdb[1], pwdb[2], pwdb[3], pwdb[4], pwdb[5], 7110 pwdb[6], pwdb[7]); 7111 7112 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 7113 "[EDCCA]: path=%d, flag {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}\n", 7114 path, flag_fb, flag_p20, flag_s20, flag_s40, flag_s80); 7115 7116 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 7117 "[EDCCA]: pwdb {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}(dBm)\n", 7118 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80); 7119 } 7120 7121 static u8 rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev *rtwdev, 7122 struct rtw89_bb_ctx *bb) 7123 { 7124 struct rtw89_phy_ch_info *ch_info = &bb->ch_info; 7125 bool is_linked = rtwdev->total_sta_assoc > 0; 7126 u8 rssi_min = ch_info->rssi_min >> 1; 7127 u8 edcca_thre; 7128 7129 if (!is_linked) { 7130 edcca_thre = EDCCA_MAX; 7131 } else { 7132 edcca_thre = rssi_min - RSSI_UNIT_CONVER + EDCCA_UNIT_CONVER - 7133 EDCCA_TH_REF; 7134 edcca_thre = max_t(u8, edcca_thre, EDCCA_TH_L2H_LB); 7135 } 7136 7137 return edcca_thre; 7138 } 7139 7140 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb) 7141 { 7142 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 7143 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak; 7144 u8 th; 7145 7146 th = rtw89_phy_edcca_get_thre_by_rssi(rtwdev, bb); 7147 if (th == edcca_bak->th_old) 7148 return; 7149 7150 edcca_bak->th_old = th; 7151 7152 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 7153 "[EDCCA]: Normal Mode, EDCCA_th = %d\n", th); 7154 7155 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level, 7156 edcca_regs->edcca_mask, th, bb->phy_idx); 7157 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level, 7158 edcca_regs->edcca_p_mask, th, bb->phy_idx); 7159 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level, 7160 edcca_regs->ppdu_mask, th, bb->phy_idx); 7161 } 7162 7163 static 7164 void __rtw89_phy_edcca_track(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb) 7165 { 7166 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, "BB-%d edcca track\n", bb->phy_idx); 7167 7168 rtw89_phy_edcca_thre_calc(rtwdev, bb); 7169 rtw89_phy_edcca_log(rtwdev, bb); 7170 } 7171 7172 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev) 7173 { 7174 struct rtw89_hal *hal = &rtwdev->hal; 7175 struct rtw89_bb_ctx *bb; 7176 7177 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DYNAMIC_EDCCA)) 7178 return; 7179 7180 rtw89_for_each_active_bb(rtwdev, bb) 7181 __rtw89_phy_edcca_track(rtwdev, bb); 7182 } 7183 7184 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev, 7185 enum rtw89_phy_idx phy_idx) 7186 { 7187 rtw89_debug(rtwdev, RTW89_DBG_RFK, 7188 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n", 7189 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx); 7190 7191 switch (rtwdev->mlo_dbcc_mode) { 7192 case MLO_1_PLUS_1_1RF: 7193 if (phy_idx == RTW89_PHY_0) 7194 return RF_A; 7195 else 7196 return RF_B; 7197 case MLO_1_PLUS_1_2RF: 7198 if (phy_idx == RTW89_PHY_0) 7199 return RF_A; 7200 else 7201 return RF_D; 7202 case MLO_0_PLUS_2_1RF: 7203 case MLO_2_PLUS_0_1RF: 7204 /* for both PHY 0/1 */ 7205 return RF_AB; 7206 case MLO_0_PLUS_2_2RF: 7207 case MLO_2_PLUS_0_2RF: 7208 case MLO_2_PLUS_2_2RF: 7209 default: 7210 if (phy_idx == RTW89_PHY_0) 7211 return RF_AB; 7212 else 7213 return RF_CD; 7214 } 7215 } 7216 EXPORT_SYMBOL(rtw89_phy_get_kpath); 7217 7218 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev, 7219 enum rtw89_phy_idx phy_idx) 7220 { 7221 rtw89_debug(rtwdev, RTW89_DBG_RFK, 7222 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n", 7223 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx); 7224 7225 switch (rtwdev->mlo_dbcc_mode) { 7226 case MLO_1_PLUS_1_1RF: 7227 if (phy_idx == RTW89_PHY_0) 7228 return RF_PATH_A; 7229 else 7230 return RF_PATH_B; 7231 case MLO_1_PLUS_1_2RF: 7232 if (phy_idx == RTW89_PHY_0) 7233 return RF_PATH_A; 7234 else 7235 return RF_PATH_D; 7236 case MLO_0_PLUS_2_1RF: 7237 case MLO_2_PLUS_0_1RF: 7238 if (phy_idx == RTW89_PHY_0) 7239 return RF_PATH_A; 7240 else 7241 return RF_PATH_B; 7242 case MLO_0_PLUS_2_2RF: 7243 case MLO_2_PLUS_0_2RF: 7244 case MLO_2_PLUS_2_2RF: 7245 default: 7246 if (phy_idx == RTW89_PHY_0) 7247 return RF_PATH_A; 7248 else 7249 return RF_PATH_C; 7250 } 7251 } 7252 EXPORT_SYMBOL(rtw89_phy_get_syn_sel); 7253 7254 static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = { 7255 .setting_addr = R_CCX, 7256 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK, 7257 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, 7258 .trig_opt_mask = B_CCX_TRIG_OPT_MSK, 7259 .en_mask = B_CCX_EN_MSK, 7260 .ifs_cnt_addr = R_IFS_COUNTER, 7261 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, 7262 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, 7263 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, 7264 .ifs_collect_en_mask = B_IFS_COLLECT_EN, 7265 .ifs_t1_addr = R_IFS_T1, 7266 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, 7267 .ifs_t1_en_mask = B_IFS_T1_EN_MSK, 7268 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, 7269 .ifs_t2_addr = R_IFS_T2, 7270 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, 7271 .ifs_t2_en_mask = B_IFS_T2_EN_MSK, 7272 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, 7273 .ifs_t3_addr = R_IFS_T3, 7274 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, 7275 .ifs_t3_en_mask = B_IFS_T3_EN_MSK, 7276 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, 7277 .ifs_t4_addr = R_IFS_T4, 7278 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, 7279 .ifs_t4_en_mask = B_IFS_T4_EN_MSK, 7280 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, 7281 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT, 7282 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, 7283 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, 7284 .ifs_clm_cca_addr = R_IFS_CLM_CCA, 7285 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, 7286 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, 7287 .ifs_clm_fa_addr = R_IFS_CLM_FA, 7288 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, 7289 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, 7290 .ifs_his_addr = R_IFS_HIS, 7291 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, 7292 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, 7293 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, 7294 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK, 7295 .ifs_avg_l_addr = R_IFS_AVG_L, 7296 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK, 7297 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK, 7298 .ifs_avg_h_addr = R_IFS_AVG_H, 7299 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK, 7300 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK, 7301 .ifs_cca_l_addr = R_IFS_CCA_L, 7302 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK, 7303 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK, 7304 .ifs_cca_h_addr = R_IFS_CCA_H, 7305 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK, 7306 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK, 7307 .ifs_total_addr = R_IFSCNT, 7308 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK, 7309 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK, 7310 }; 7311 7312 static const struct rtw89_physts_regs rtw89_physts_regs_ax = { 7313 .setting_addr = R_PLCP_HISTOGRAM, 7314 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, 7315 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, 7316 }; 7317 7318 static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = { 7319 .comp = R_DCFO_WEIGHT, 7320 .weighting_mask = B_DCFO_WEIGHT_MSK, 7321 .comp_seg0 = R_DCFO_OPT, 7322 .valid_0_mask = B_DCFO_OPT_EN, 7323 }; 7324 7325 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = { 7326 .cr_base = 0x10000, 7327 .ccx = &rtw89_ccx_regs_ax, 7328 .physts = &rtw89_physts_regs_ax, 7329 .cfo = &rtw89_cfo_regs_ax, 7330 .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax, 7331 .config_bb_gain = rtw89_phy_config_bb_gain_ax, 7332 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax, 7333 .bb_wrap_init = NULL, 7334 .ch_info_init = NULL, 7335 7336 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax, 7337 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax, 7338 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax, 7339 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax, 7340 }; 7341 EXPORT_SYMBOL(rtw89_phy_gen_ax); 7342