1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "chan.h" 6 #include "coex.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "phy.h" 11 #include "ps.h" 12 #include "reg.h" 13 #include "sar.h" 14 #include "txrx.h" 15 #include "util.h" 16 17 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 18 { 19 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 20 21 return phy->phy0_phy1_offset(rtwdev, addr); 22 } 23 24 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 25 const struct rtw89_ra_report *report) 26 { 27 u32 bit_rate = report->bit_rate; 28 29 /* lower than ofdm, do not aggregate */ 30 if (bit_rate < 550) 31 return 1; 32 33 /* avoid AMSDU for legacy rate */ 34 if (report->might_fallback_legacy) 35 return 1; 36 37 /* lower than 20M vht 2ss mcs8, make it small */ 38 if (bit_rate < 1800) 39 return 1200; 40 41 /* lower than 40M vht 2ss mcs9, make it medium */ 42 if (bit_rate < 4000) 43 return 2600; 44 45 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 46 if (bit_rate < 7000) 47 return 3500; 48 49 return rtwdev->chip->max_amsdu_limit; 50 } 51 52 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 53 { 54 u64 ra_mask = 0; 55 u8 mcs_cap; 56 int i, nss; 57 58 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 59 mcs_cap = mcs_map & 0x3; 60 switch (mcs_cap) { 61 case 2: 62 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 63 break; 64 case 1: 65 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 66 break; 67 case 0: 68 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 69 break; 70 default: 71 break; 72 } 73 } 74 75 return ra_mask; 76 } 77 78 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 79 { 80 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 81 u16 mcs_map; 82 83 switch (sta->deflink.bandwidth) { 84 case IEEE80211_STA_RX_BW_160: 85 if (cap.he_cap_elem.phy_cap_info[0] & 86 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 87 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 88 else 89 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 90 break; 91 default: 92 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 93 } 94 95 /* MCS11, MCS9, MCS7 */ 96 return get_mcs_ra_mask(mcs_map, 11, 2); 97 } 98 99 static u64 get_eht_mcs_ra_mask(u8 *max_nss, u8 start_mcs, u8 n_nss) 100 { 101 u64 nss_mcs_shift; 102 u64 nss_mcs_val; 103 u64 mask = 0; 104 int i, j; 105 u8 nss; 106 107 for (i = 0; i < n_nss; i++) { 108 nss = u8_get_bits(max_nss[i], IEEE80211_EHT_MCS_NSS_RX); 109 if (!nss) 110 continue; 111 112 nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0); 113 114 for (j = 0, nss_mcs_shift = 12; j < nss; j++, nss_mcs_shift += 16) 115 mask |= nss_mcs_val << nss_mcs_shift; 116 } 117 118 return mask; 119 } 120 121 static u64 get_eht_ra_mask(struct ieee80211_sta *sta) 122 { 123 struct ieee80211_sta_eht_cap *eht_cap = &sta->deflink.eht_cap; 124 struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs_nss_20mhz; 125 struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss; 126 u8 *he_phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 127 128 switch (sta->deflink.bandwidth) { 129 case IEEE80211_STA_RX_BW_320: 130 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320; 131 /* MCS 9, 11, 13 */ 132 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 133 case IEEE80211_STA_RX_BW_160: 134 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160; 135 /* MCS 9, 11, 13 */ 136 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 137 case IEEE80211_STA_RX_BW_20: 138 if (!(he_phy_cap[0] & 139 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) { 140 mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz; 141 /* MCS 7, 9, 11, 13 */ 142 return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4); 143 } 144 fallthrough; 145 case IEEE80211_STA_RX_BW_80: 146 default: 147 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80; 148 /* MCS 9, 11, 13 */ 149 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 150 } 151 } 152 153 #define RA_FLOOR_TABLE_SIZE 7 154 #define RA_FLOOR_UP_GAP 3 155 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 156 u8 ratr_state) 157 { 158 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 159 u8 rssi_lv = 0; 160 u8 i; 161 162 rssi >>= 1; 163 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 164 if (i >= ratr_state) 165 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 166 if (rssi < rssi_lv_t[i]) { 167 rssi_lv = i; 168 break; 169 } 170 } 171 if (rssi_lv == 0) 172 return 0xffffffffffffffffULL; 173 else if (rssi_lv == 1) 174 return 0xfffffffffffffff0ULL; 175 else if (rssi_lv == 2) 176 return 0xffffffffffffefe0ULL; 177 else if (rssi_lv == 3) 178 return 0xffffffffffffcfc0ULL; 179 else if (rssi_lv == 4) 180 return 0xffffffffffff8f80ULL; 181 else if (rssi_lv >= 5) 182 return 0xffffffffffff0f00ULL; 183 184 return 0xffffffffffffffffULL; 185 } 186 187 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 188 { 189 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 190 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 191 192 if (ra_mask == 0) 193 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 194 195 return ra_mask; 196 } 197 198 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 199 const struct rtw89_chan *chan) 200 { 201 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 202 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 203 enum nl80211_band band; 204 u64 cfg_mask; 205 206 if (!rtwsta->use_cfg_mask) 207 return -1; 208 209 switch (chan->band_type) { 210 case RTW89_BAND_2G: 211 band = NL80211_BAND_2GHZ; 212 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 213 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 214 break; 215 case RTW89_BAND_5G: 216 band = NL80211_BAND_5GHZ; 217 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 218 RA_MASK_OFDM_RATES); 219 break; 220 case RTW89_BAND_6G: 221 band = NL80211_BAND_6GHZ; 222 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 223 RA_MASK_OFDM_RATES); 224 break; 225 default: 226 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 227 return -1; 228 } 229 230 if (sta->deflink.he_cap.has_he) { 231 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 232 RA_MASK_HE_1SS_RATES); 233 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 234 RA_MASK_HE_2SS_RATES); 235 } else if (sta->deflink.vht_cap.vht_supported) { 236 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 237 RA_MASK_VHT_1SS_RATES); 238 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 239 RA_MASK_VHT_2SS_RATES); 240 } else if (sta->deflink.ht_cap.ht_supported) { 241 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 242 RA_MASK_HT_1SS_RATES); 243 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 244 RA_MASK_HT_2SS_RATES); 245 } 246 247 return cfg_mask; 248 } 249 250 static const u64 251 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 252 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 253 static const u64 254 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 255 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 256 static const u64 257 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 258 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 259 static const u64 260 rtw89_ra_mask_eht_rates[4] = {RA_MASK_EHT_1SS_RATES, RA_MASK_EHT_2SS_RATES, 261 RA_MASK_EHT_3SS_RATES, RA_MASK_EHT_4SS_RATES}; 262 263 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 264 struct rtw89_sta *rtwsta, 265 const struct rtw89_chan *chan, 266 bool *fix_giltf_en, u8 *fix_giltf) 267 { 268 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 269 u8 band = chan->band_type; 270 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 271 u8 he_gi = mask->control[nl_band].he_gi; 272 u8 he_ltf = mask->control[nl_band].he_ltf; 273 274 if (!rtwsta->use_cfg_mask) 275 return; 276 277 if (he_ltf == 2 && he_gi == 2) { 278 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 279 } else if (he_ltf == 2 && he_gi == 0) { 280 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 281 } else if (he_ltf == 1 && he_gi == 1) { 282 *fix_giltf = RTW89_GILTF_2XHE16; 283 } else if (he_ltf == 1 && he_gi == 0) { 284 *fix_giltf = RTW89_GILTF_2XHE08; 285 } else if (he_ltf == 0 && he_gi == 1) { 286 *fix_giltf = RTW89_GILTF_1XHE16; 287 } else if (he_ltf == 0 && he_gi == 0) { 288 *fix_giltf = RTW89_GILTF_1XHE08; 289 } else { 290 *fix_giltf_en = false; 291 return; 292 } 293 294 *fix_giltf_en = true; 295 } 296 297 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 298 struct ieee80211_sta *sta, bool csi) 299 { 300 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 301 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 302 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 303 struct rtw89_ra_info *ra = &rtwsta->ra; 304 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 305 rtwvif->chanctx_idx); 306 struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); 307 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 308 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 309 u64 ra_mask = 0; 310 u64 ra_mask_bak; 311 u8 mode = 0; 312 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 313 u8 bw_mode = 0; 314 u8 stbc_en = 0; 315 u8 ldpc_en = 0; 316 u8 fix_giltf = 0; 317 u8 i; 318 bool sgi = false; 319 bool fix_giltf_en = false; 320 321 memset(ra, 0, sizeof(*ra)); 322 /* Set the ra mask from sta's capability */ 323 if (sta->deflink.eht_cap.has_eht) { 324 mode |= RTW89_RA_MODE_EHT; 325 ra_mask |= get_eht_ra_mask(sta); 326 high_rate_masks = rtw89_ra_mask_eht_rates; 327 } else if (sta->deflink.he_cap.has_he) { 328 mode |= RTW89_RA_MODE_HE; 329 csi_mode = RTW89_RA_RPT_MODE_HE; 330 ra_mask |= get_he_ra_mask(sta); 331 high_rate_masks = rtw89_ra_mask_he_rates; 332 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 333 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 334 stbc_en = 1; 335 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 336 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 337 ldpc_en = 1; 338 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, chan, &fix_giltf_en, &fix_giltf); 339 } else if (sta->deflink.vht_cap.vht_supported) { 340 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 341 342 mode |= RTW89_RA_MODE_VHT; 343 csi_mode = RTW89_RA_RPT_MODE_VHT; 344 /* MCS9 (non-20MHz), MCS8, MCS7 */ 345 if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_20) 346 ra_mask |= get_mcs_ra_mask(mcs_map, 8, 1); 347 else 348 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 349 high_rate_masks = rtw89_ra_mask_vht_rates; 350 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 351 stbc_en = 1; 352 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 353 ldpc_en = 1; 354 } else if (sta->deflink.ht_cap.ht_supported) { 355 mode |= RTW89_RA_MODE_HT; 356 csi_mode = RTW89_RA_RPT_MODE_HT; 357 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 358 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 359 ((u64)sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 360 ((u64)sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 361 high_rate_masks = rtw89_ra_mask_ht_rates; 362 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 363 stbc_en = 1; 364 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 365 ldpc_en = 1; 366 } 367 368 switch (chan->band_type) { 369 case RTW89_BAND_2G: 370 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 371 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xf) 372 mode |= RTW89_RA_MODE_CCK; 373 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xff0) 374 mode |= RTW89_RA_MODE_OFDM; 375 break; 376 case RTW89_BAND_5G: 377 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 378 mode |= RTW89_RA_MODE_OFDM; 379 break; 380 case RTW89_BAND_6G: 381 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 382 mode |= RTW89_RA_MODE_OFDM; 383 break; 384 default: 385 rtw89_err(rtwdev, "Unknown band type\n"); 386 break; 387 } 388 389 ra_mask_bak = ra_mask; 390 391 if (mode >= RTW89_RA_MODE_HT) { 392 u64 mask = 0; 393 for (i = 0; i < rtwdev->hal.tx_nss; i++) 394 mask |= high_rate_masks[i]; 395 if (mode & RTW89_RA_MODE_OFDM) 396 mask |= RA_MASK_SUBOFDM_RATES; 397 if (mode & RTW89_RA_MODE_CCK) 398 mask |= RA_MASK_SUBCCK_RATES; 399 ra_mask &= mask; 400 } else if (mode & RTW89_RA_MODE_OFDM) { 401 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 402 } 403 404 if (mode != RTW89_RA_MODE_CCK) 405 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 406 407 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 408 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan); 409 410 switch (sta->deflink.bandwidth) { 411 case IEEE80211_STA_RX_BW_160: 412 bw_mode = RTW89_CHANNEL_WIDTH_160; 413 sgi = sta->deflink.vht_cap.vht_supported && 414 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 415 break; 416 case IEEE80211_STA_RX_BW_80: 417 bw_mode = RTW89_CHANNEL_WIDTH_80; 418 sgi = sta->deflink.vht_cap.vht_supported && 419 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 420 break; 421 case IEEE80211_STA_RX_BW_40: 422 bw_mode = RTW89_CHANNEL_WIDTH_40; 423 sgi = sta->deflink.ht_cap.ht_supported && 424 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 425 break; 426 default: 427 bw_mode = RTW89_CHANNEL_WIDTH_20; 428 sgi = sta->deflink.ht_cap.ht_supported && 429 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 430 break; 431 } 432 433 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 434 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 435 ra->dcm_cap = 1; 436 437 if (rate_pattern->enable && !vif->p2p) { 438 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan); 439 ra_mask &= rate_pattern->ra_mask; 440 mode = rate_pattern->ra_mode; 441 } 442 443 ra->bw_cap = bw_mode; 444 ra->er_cap = rtwsta->er_cap; 445 ra->mode_ctrl = mode; 446 ra->macid = rtwsta->mac_id; 447 ra->stbc_cap = stbc_en; 448 ra->ldpc_cap = ldpc_en; 449 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 450 ra->en_sgi = sgi; 451 ra->ra_mask = ra_mask; 452 ra->fix_giltf_en = fix_giltf_en; 453 ra->fix_giltf = fix_giltf; 454 455 if (!csi) 456 return; 457 458 ra->fixed_csi_rate_en = false; 459 ra->ra_csi_rate_en = true; 460 ra->cr_tbl_sel = false; 461 ra->band_num = rtwvif->phy_idx; 462 ra->csi_bw = bw_mode; 463 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 464 ra->csi_mcs_ss_idx = 5; 465 ra->csi_mode = csi_mode; 466 } 467 468 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 469 u32 changed) 470 { 471 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 472 struct rtw89_ra_info *ra = &rtwsta->ra; 473 474 rtw89_phy_ra_sta_update(rtwdev, sta, false); 475 476 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 477 ra->upd_mask = 1; 478 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 479 ra->upd_bw_nss_mask = 1; 480 481 rtw89_debug(rtwdev, RTW89_DBG_RA, 482 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 483 ra->macid, 484 ra->bw_cap, 485 ra->ss_num, 486 ra->en_sgi, 487 ra->giltf); 488 489 rtw89_fw_h2c_ra(rtwdev, ra, false); 490 } 491 492 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 493 u16 rate_base, u64 ra_mask, u8 ra_mode, 494 u32 rate_ctrl, u32 ctrl_skip, bool force) 495 { 496 u8 n, c; 497 498 if (rate_ctrl == ctrl_skip) 499 return true; 500 501 n = hweight32(rate_ctrl); 502 if (n == 0) 503 return true; 504 505 if (force && n != 1) 506 return false; 507 508 if (next->enable) 509 return false; 510 511 c = __fls(rate_ctrl); 512 next->rate = rate_base + c; 513 next->ra_mode = ra_mode; 514 next->ra_mask = ra_mask; 515 next->enable = true; 516 517 return true; 518 } 519 520 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \ 521 { \ 522 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \ 523 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \ 524 } 525 526 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 527 struct ieee80211_vif *vif, 528 const struct cfg80211_bitrate_mask *mask) 529 { 530 struct ieee80211_supported_band *sband; 531 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 532 struct rtw89_phy_rate_pattern next_pattern = {0}; 533 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 534 rtwvif->chanctx_idx); 535 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = { 536 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0), 537 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0), 538 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0), 539 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0), 540 }; 541 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = { 542 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0), 543 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0), 544 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0), 545 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0), 546 }; 547 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = { 548 RTW89_HW_RATE_BY_CHIP_GEN(MCS0), 549 RTW89_HW_RATE_BY_CHIP_GEN(MCS8), 550 RTW89_HW_RATE_BY_CHIP_GEN(MCS16), 551 RTW89_HW_RATE_BY_CHIP_GEN(MCS24), 552 }; 553 u8 band = chan->band_type; 554 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 555 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 556 u8 tx_nss = rtwdev->hal.tx_nss; 557 u8 i; 558 559 for (i = 0; i < tx_nss; i++) 560 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen], 561 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 562 mask->control[nl_band].he_mcs[i], 563 0, true)) 564 goto out; 565 566 for (i = 0; i < tx_nss; i++) 567 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen], 568 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 569 mask->control[nl_band].vht_mcs[i], 570 0, true)) 571 goto out; 572 573 for (i = 0; i < tx_nss; i++) 574 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen], 575 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 576 mask->control[nl_band].ht_mcs[i], 577 0, true)) 578 goto out; 579 580 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 581 * require at least one basic rate for ieee80211_set_bitrate_mask, 582 * so the decision just depends on if all bitrates are set or not. 583 */ 584 sband = rtwdev->hw->wiphy->bands[nl_band]; 585 if (band == RTW89_BAND_2G) { 586 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 587 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 588 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 589 mask->control[nl_band].legacy, 590 BIT(sband->n_bitrates) - 1, false)) 591 goto out; 592 } else { 593 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 594 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 595 mask->control[nl_band].legacy, 596 BIT(sband->n_bitrates) - 1, false)) 597 goto out; 598 } 599 600 if (!next_pattern.enable) 601 goto out; 602 603 rtwvif->rate_pattern = next_pattern; 604 rtw89_debug(rtwdev, RTW89_DBG_RA, 605 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 606 next_pattern.rate, 607 next_pattern.ra_mask, 608 next_pattern.ra_mode); 609 return; 610 611 out: 612 rtwvif->rate_pattern.enable = false; 613 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 614 } 615 616 static void rtw89_phy_ra_update_sta_iter(void *data, struct ieee80211_sta *sta) 617 { 618 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 619 620 rtw89_phy_ra_update_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 621 } 622 623 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 624 { 625 ieee80211_iterate_stations_atomic(rtwdev->hw, 626 rtw89_phy_ra_update_sta_iter, 627 rtwdev); 628 } 629 630 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 631 { 632 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 633 struct rtw89_ra_info *ra = &rtwsta->ra; 634 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 635 bool csi = rtw89_sta_has_beamformer_cap(sta); 636 637 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 638 639 if (rssi > 40) 640 ra->init_rate_lv = 1; 641 else if (rssi > 20) 642 ra->init_rate_lv = 2; 643 else if (rssi > 1) 644 ra->init_rate_lv = 3; 645 else 646 ra->init_rate_lv = 0; 647 ra->upd_all = 1; 648 rtw89_debug(rtwdev, RTW89_DBG_RA, 649 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 650 ra->macid, 651 ra->mode_ctrl, 652 ra->bw_cap, 653 ra->ss_num, 654 ra->init_rate_lv); 655 rtw89_debug(rtwdev, RTW89_DBG_RA, 656 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 657 ra->dcm_cap, 658 ra->er_cap, 659 ra->ldpc_cap, 660 ra->stbc_cap, 661 ra->en_sgi, 662 ra->giltf); 663 664 rtw89_fw_h2c_ra(rtwdev, ra, csi); 665 } 666 667 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 668 const struct rtw89_chan *chan, 669 enum rtw89_bandwidth dbw) 670 { 671 enum rtw89_bandwidth cbw = chan->band_width; 672 u8 pri_ch = chan->primary_channel; 673 u8 central_ch = chan->channel; 674 u8 txsc_idx = 0; 675 u8 tmp = 0; 676 677 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 678 return txsc_idx; 679 680 switch (cbw) { 681 case RTW89_CHANNEL_WIDTH_40: 682 txsc_idx = pri_ch > central_ch ? 1 : 2; 683 break; 684 case RTW89_CHANNEL_WIDTH_80: 685 if (dbw == RTW89_CHANNEL_WIDTH_20) { 686 if (pri_ch > central_ch) 687 txsc_idx = (pri_ch - central_ch) >> 1; 688 else 689 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 690 } else { 691 txsc_idx = pri_ch > central_ch ? 9 : 10; 692 } 693 break; 694 case RTW89_CHANNEL_WIDTH_160: 695 if (pri_ch > central_ch) 696 tmp = (pri_ch - central_ch) >> 1; 697 else 698 tmp = ((central_ch - pri_ch) >> 1) + 1; 699 700 if (dbw == RTW89_CHANNEL_WIDTH_20) { 701 txsc_idx = tmp; 702 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 703 if (tmp == 1 || tmp == 3) 704 txsc_idx = 9; 705 else if (tmp == 5 || tmp == 7) 706 txsc_idx = 11; 707 else if (tmp == 2 || tmp == 4) 708 txsc_idx = 10; 709 else if (tmp == 6 || tmp == 8) 710 txsc_idx = 12; 711 else 712 return 0xff; 713 } else { 714 txsc_idx = pri_ch > central_ch ? 13 : 14; 715 } 716 break; 717 case RTW89_CHANNEL_WIDTH_80_80: 718 if (dbw == RTW89_CHANNEL_WIDTH_20) { 719 if (pri_ch > central_ch) 720 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 721 else 722 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 723 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 724 txsc_idx = pri_ch > central_ch ? 10 : 12; 725 } else { 726 txsc_idx = 14; 727 } 728 break; 729 default: 730 break; 731 } 732 733 return txsc_idx; 734 } 735 EXPORT_SYMBOL(rtw89_phy_get_txsc); 736 737 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 738 enum rtw89_bandwidth dbw) 739 { 740 enum rtw89_bandwidth cbw = chan->band_width; 741 u8 pri_ch = chan->primary_channel; 742 u8 central_ch = chan->channel; 743 u8 txsb_idx = 0; 744 745 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 746 return txsb_idx; 747 748 switch (cbw) { 749 case RTW89_CHANNEL_WIDTH_40: 750 txsb_idx = pri_ch > central_ch ? 1 : 0; 751 break; 752 case RTW89_CHANNEL_WIDTH_80: 753 if (dbw == RTW89_CHANNEL_WIDTH_20) 754 txsb_idx = (pri_ch - central_ch + 6) / 4; 755 else 756 txsb_idx = pri_ch > central_ch ? 1 : 0; 757 break; 758 case RTW89_CHANNEL_WIDTH_160: 759 if (dbw == RTW89_CHANNEL_WIDTH_20) 760 txsb_idx = (pri_ch - central_ch + 14) / 4; 761 else if (dbw == RTW89_CHANNEL_WIDTH_40) 762 txsb_idx = (pri_ch - central_ch + 12) / 8; 763 else 764 txsb_idx = pri_ch > central_ch ? 1 : 0; 765 break; 766 case RTW89_CHANNEL_WIDTH_320: 767 if (dbw == RTW89_CHANNEL_WIDTH_20) 768 txsb_idx = (pri_ch - central_ch + 30) / 4; 769 else if (dbw == RTW89_CHANNEL_WIDTH_40) 770 txsb_idx = (pri_ch - central_ch + 28) / 8; 771 else if (dbw == RTW89_CHANNEL_WIDTH_80) 772 txsb_idx = (pri_ch - central_ch + 24) / 16; 773 else 774 txsb_idx = pri_ch > central_ch ? 1 : 0; 775 break; 776 default: 777 break; 778 } 779 780 return txsb_idx; 781 } 782 EXPORT_SYMBOL(rtw89_phy_get_txsb); 783 784 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 785 { 786 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 787 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 788 } 789 790 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 791 u32 addr, u32 mask) 792 { 793 const struct rtw89_chip_info *chip = rtwdev->chip; 794 const u32 *base_addr = chip->rf_base_addr; 795 u32 val, direct_addr; 796 797 if (rf_path >= rtwdev->chip->rf_path_num) { 798 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 799 return INV_RF_DATA; 800 } 801 802 addr &= 0xff; 803 direct_addr = base_addr[rf_path] + (addr << 2); 804 mask &= RFREG_MASK; 805 806 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 807 808 return val; 809 } 810 EXPORT_SYMBOL(rtw89_phy_read_rf); 811 812 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 813 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 814 { 815 bool busy; 816 bool done; 817 u32 val; 818 int ret; 819 820 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 821 1, 30, false, rtwdev); 822 if (ret) { 823 rtw89_err(rtwdev, "read rf busy swsi\n"); 824 return INV_RF_DATA; 825 } 826 827 mask &= RFREG_MASK; 828 829 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 830 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 831 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 832 udelay(2); 833 834 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 835 30, false, rtwdev, R_SWSI_V1, 836 B_SWSI_R_DATA_DONE_V1); 837 if (ret) { 838 rtw89_err(rtwdev, "read swsi busy\n"); 839 return INV_RF_DATA; 840 } 841 842 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 843 } 844 845 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 846 u32 addr, u32 mask) 847 { 848 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 849 850 if (rf_path >= rtwdev->chip->rf_path_num) { 851 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 852 return INV_RF_DATA; 853 } 854 855 if (ad_sel) 856 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 857 else 858 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 859 } 860 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 861 862 static u32 rtw89_phy_read_full_rf_v2_a(struct rtw89_dev *rtwdev, 863 enum rtw89_rf_path rf_path, u32 addr) 864 { 865 static const u16 r_addr_ofst[2] = {0x2C24, 0x2D24}; 866 static const u16 addr_ofst[2] = {0x2ADC, 0x2BDC}; 867 bool busy, done; 868 int ret; 869 u32 val; 870 871 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_CTL_MASK, 0x1); 872 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, 873 1, 3800, false, 874 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_BUSY); 875 if (ret) { 876 rtw89_warn(rtwdev, "poll HWSI is busy\n"); 877 return INV_RF_DATA; 878 } 879 880 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_MASK, addr); 881 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_RD, 0x1); 882 udelay(2); 883 884 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 885 1, 3800, false, 886 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_RDONE); 887 if (ret) { 888 rtw89_warn(rtwdev, "read HWSI is busy\n"); 889 val = INV_RF_DATA; 890 goto out; 891 } 892 893 val = rtw89_phy_read32_mask(rtwdev, r_addr_ofst[rf_path], RFREG_MASK); 894 out: 895 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_POLL_MASK, 0); 896 897 return val; 898 } 899 900 static u32 rtw89_phy_read_rf_v2_a(struct rtw89_dev *rtwdev, 901 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 902 { 903 u32 val; 904 905 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr); 906 907 return (val & mask) >> __ffs(mask); 908 } 909 910 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 911 u32 addr, u32 mask) 912 { 913 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); 914 915 if (rf_path >= rtwdev->chip->rf_path_num) { 916 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 917 return INV_RF_DATA; 918 } 919 920 if (ad_sel) 921 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 922 else 923 return rtw89_phy_read_rf_v2_a(rtwdev, rf_path, addr, mask); 924 } 925 EXPORT_SYMBOL(rtw89_phy_read_rf_v2); 926 927 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 928 u32 addr, u32 mask, u32 data) 929 { 930 const struct rtw89_chip_info *chip = rtwdev->chip; 931 const u32 *base_addr = chip->rf_base_addr; 932 u32 direct_addr; 933 934 if (rf_path >= rtwdev->chip->rf_path_num) { 935 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 936 return false; 937 } 938 939 addr &= 0xff; 940 direct_addr = base_addr[rf_path] + (addr << 2); 941 mask &= RFREG_MASK; 942 943 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 944 945 /* delay to ensure writing properly */ 946 udelay(1); 947 948 return true; 949 } 950 EXPORT_SYMBOL(rtw89_phy_write_rf); 951 952 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 953 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 954 u32 data) 955 { 956 u8 bit_shift; 957 u32 val; 958 bool busy, b_msk_en = false; 959 int ret; 960 961 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 962 1, 30, false, rtwdev); 963 if (ret) { 964 rtw89_err(rtwdev, "write rf busy swsi\n"); 965 return false; 966 } 967 968 data &= RFREG_MASK; 969 mask &= RFREG_MASK; 970 971 if (mask != RFREG_MASK) { 972 b_msk_en = true; 973 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 974 mask); 975 bit_shift = __ffs(mask); 976 data = (data << bit_shift) & RFREG_MASK; 977 } 978 979 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 980 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 981 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 982 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 983 984 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 985 986 return true; 987 } 988 989 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 990 u32 addr, u32 mask, u32 data) 991 { 992 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 993 994 if (rf_path >= rtwdev->chip->rf_path_num) { 995 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 996 return false; 997 } 998 999 if (ad_sel) 1000 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 1001 else 1002 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 1003 } 1004 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 1005 1006 static 1007 bool rtw89_phy_write_full_rf_v2_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1008 u32 addr, u32 data) 1009 { 1010 static const u32 addr_is_idle[2] = {0x2C24, 0x2D24}; 1011 static const u32 addr_ofst[2] = {0x2AE0, 0x2BE0}; 1012 bool busy; 1013 u32 val; 1014 int ret; 1015 1016 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, 1017 1, 3800, false, 1018 rtwdev, addr_is_idle[rf_path], BIT(29)); 1019 if (ret) { 1020 rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__); 1021 return false; 1022 } 1023 1024 val = u32_encode_bits(addr, B_HWSI_DATA_ADDR) | 1025 u32_encode_bits(data, B_HWSI_DATA_VAL); 1026 1027 rtw89_phy_write32(rtwdev, addr_ofst[rf_path], val); 1028 1029 return true; 1030 } 1031 1032 static 1033 bool rtw89_phy_write_rf_a_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1034 u32 addr, u32 mask, u32 data) 1035 { 1036 u32 val; 1037 1038 if (mask == RFREG_MASK) { 1039 val = data; 1040 } else { 1041 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr); 1042 val &= ~mask; 1043 val |= (data << __ffs(mask)) & mask; 1044 } 1045 1046 return rtw89_phy_write_full_rf_v2_a(rtwdev, rf_path, addr, val); 1047 } 1048 1049 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1050 u32 addr, u32 mask, u32 data) 1051 { 1052 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); 1053 1054 if (rf_path >= rtwdev->chip->rf_path_num) { 1055 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 1056 return INV_RF_DATA; 1057 } 1058 1059 if (ad_sel) 1060 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 1061 else 1062 return rtw89_phy_write_rf_a_v2(rtwdev, rf_path, addr, mask, data); 1063 } 1064 EXPORT_SYMBOL(rtw89_phy_write_rf_v2); 1065 1066 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 1067 { 1068 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; 1069 } 1070 1071 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 1072 enum rtw89_phy_idx phy_idx) 1073 { 1074 const struct rtw89_chip_info *chip = rtwdev->chip; 1075 1076 chip->ops->bb_reset(rtwdev, phy_idx); 1077 } 1078 1079 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 1080 const struct rtw89_reg2_def *reg, 1081 enum rtw89_rf_path rf_path, 1082 void *extra_data) 1083 { 1084 u32 addr; 1085 1086 if (reg->addr == 0xfe) { 1087 mdelay(50); 1088 } else if (reg->addr == 0xfd) { 1089 mdelay(5); 1090 } else if (reg->addr == 0xfc) { 1091 mdelay(1); 1092 } else if (reg->addr == 0xfb) { 1093 udelay(50); 1094 } else if (reg->addr == 0xfa) { 1095 udelay(5); 1096 } else if (reg->addr == 0xf9) { 1097 udelay(1); 1098 } else if (reg->data == BYPASS_CR_DATA) { 1099 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr); 1100 } else { 1101 addr = reg->addr; 1102 1103 if ((uintptr_t)extra_data == RTW89_PHY_1) 1104 addr += rtw89_phy0_phy1_offset(rtwdev, reg->addr); 1105 1106 rtw89_phy_write32(rtwdev, addr, reg->data); 1107 } 1108 } 1109 1110 union rtw89_phy_bb_gain_arg { 1111 u32 addr; 1112 struct { 1113 union { 1114 u8 type; 1115 struct { 1116 u8 rxsc_start:4; 1117 u8 bw:4; 1118 }; 1119 }; 1120 u8 path; 1121 u8 gain_band; 1122 u8 cfg_type; 1123 }; 1124 } __packed; 1125 1126 static void 1127 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 1128 union rtw89_phy_bb_gain_arg arg, u32 data) 1129 { 1130 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1131 u8 type = arg.type; 1132 u8 path = arg.path; 1133 u8 gband = arg.gain_band; 1134 int i; 1135 1136 switch (type) { 1137 case 0: 1138 for (i = 0; i < 4; i++, data >>= 8) 1139 gain->lna_gain[gband][path][i] = data & 0xff; 1140 break; 1141 case 1: 1142 for (i = 4; i < 7; i++, data >>= 8) 1143 gain->lna_gain[gband][path][i] = data & 0xff; 1144 break; 1145 case 2: 1146 for (i = 0; i < 2; i++, data >>= 8) 1147 gain->tia_gain[gband][path][i] = data & 0xff; 1148 break; 1149 default: 1150 rtw89_warn(rtwdev, 1151 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 1152 arg.addr, data, type); 1153 break; 1154 } 1155 } 1156 1157 enum rtw89_phy_bb_rxsc_start_idx { 1158 RTW89_BB_RXSC_START_IDX_FULL = 0, 1159 RTW89_BB_RXSC_START_IDX_20 = 1, 1160 RTW89_BB_RXSC_START_IDX_20_1 = 5, 1161 RTW89_BB_RXSC_START_IDX_40 = 9, 1162 RTW89_BB_RXSC_START_IDX_80 = 13, 1163 }; 1164 1165 static void 1166 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 1167 union rtw89_phy_bb_gain_arg arg, u32 data) 1168 { 1169 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1170 u8 rxsc_start = arg.rxsc_start; 1171 u8 bw = arg.bw; 1172 u8 path = arg.path; 1173 u8 gband = arg.gain_band; 1174 u8 rxsc; 1175 s8 ofst; 1176 int i; 1177 1178 switch (bw) { 1179 case RTW89_CHANNEL_WIDTH_20: 1180 gain->rpl_ofst_20[gband][path] = (s8)data; 1181 break; 1182 case RTW89_CHANNEL_WIDTH_40: 1183 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1184 gain->rpl_ofst_40[gband][path][0] = (s8)data; 1185 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1186 for (i = 0; i < 2; i++, data >>= 8) { 1187 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1188 ofst = (s8)(data & 0xff); 1189 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 1190 } 1191 } 1192 break; 1193 case RTW89_CHANNEL_WIDTH_80: 1194 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1195 gain->rpl_ofst_80[gband][path][0] = (s8)data; 1196 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1197 for (i = 0; i < 4; i++, data >>= 8) { 1198 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1199 ofst = (s8)(data & 0xff); 1200 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 1201 } 1202 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 1203 for (i = 0; i < 2; i++, data >>= 8) { 1204 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 1205 ofst = (s8)(data & 0xff); 1206 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 1207 } 1208 } 1209 break; 1210 case RTW89_CHANNEL_WIDTH_160: 1211 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1212 gain->rpl_ofst_160[gband][path][0] = (s8)data; 1213 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1214 for (i = 0; i < 4; i++, data >>= 8) { 1215 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1216 ofst = (s8)(data & 0xff); 1217 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1218 } 1219 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 1220 for (i = 0; i < 4; i++, data >>= 8) { 1221 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 1222 ofst = (s8)(data & 0xff); 1223 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1224 } 1225 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 1226 for (i = 0; i < 4; i++, data >>= 8) { 1227 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 1228 ofst = (s8)(data & 0xff); 1229 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1230 } 1231 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 1232 for (i = 0; i < 2; i++, data >>= 8) { 1233 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 1234 ofst = (s8)(data & 0xff); 1235 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1236 } 1237 } 1238 break; 1239 default: 1240 rtw89_warn(rtwdev, 1241 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 1242 arg.addr, data, bw); 1243 break; 1244 } 1245 } 1246 1247 static void 1248 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 1249 union rtw89_phy_bb_gain_arg arg, u32 data) 1250 { 1251 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1252 u8 type = arg.type; 1253 u8 path = arg.path; 1254 u8 gband = arg.gain_band; 1255 int i; 1256 1257 switch (type) { 1258 case 0: 1259 for (i = 0; i < 4; i++, data >>= 8) 1260 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1261 break; 1262 case 1: 1263 for (i = 4; i < 7; i++, data >>= 8) 1264 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1265 break; 1266 default: 1267 rtw89_warn(rtwdev, 1268 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 1269 arg.addr, data, type); 1270 break; 1271 } 1272 } 1273 1274 static void 1275 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 1276 union rtw89_phy_bb_gain_arg arg, u32 data) 1277 { 1278 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1279 u8 type = arg.type; 1280 u8 path = arg.path; 1281 u8 gband = arg.gain_band; 1282 int i; 1283 1284 switch (type) { 1285 case 0: 1286 for (i = 0; i < 4; i++, data >>= 8) 1287 gain->lna_op1db[gband][path][i] = data & 0xff; 1288 break; 1289 case 1: 1290 for (i = 4; i < 7; i++, data >>= 8) 1291 gain->lna_op1db[gband][path][i] = data & 0xff; 1292 break; 1293 case 2: 1294 for (i = 0; i < 4; i++, data >>= 8) 1295 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1296 break; 1297 case 3: 1298 for (i = 4; i < 8; i++, data >>= 8) 1299 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1300 break; 1301 default: 1302 rtw89_warn(rtwdev, 1303 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1304 arg.addr, data, type); 1305 break; 1306 } 1307 } 1308 1309 static void rtw89_phy_config_bb_gain_ax(struct rtw89_dev *rtwdev, 1310 const struct rtw89_reg2_def *reg, 1311 enum rtw89_rf_path rf_path, 1312 void *extra_data) 1313 { 1314 const struct rtw89_chip_info *chip = rtwdev->chip; 1315 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1316 struct rtw89_efuse *efuse = &rtwdev->efuse; 1317 1318 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1319 return; 1320 1321 if (arg.path >= chip->rf_path_num) 1322 return; 1323 1324 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1325 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1326 return; 1327 } 1328 1329 switch (arg.cfg_type) { 1330 case 0: 1331 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1332 break; 1333 case 1: 1334 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1335 break; 1336 case 2: 1337 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1338 break; 1339 case 3: 1340 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1341 break; 1342 case 4: 1343 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 1344 if (efuse->rfe_type < 50) 1345 break; 1346 fallthrough; 1347 default: 1348 rtw89_warn(rtwdev, 1349 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1350 arg.addr, reg->data, arg.cfg_type); 1351 break; 1352 } 1353 } 1354 1355 static void 1356 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1357 const struct rtw89_reg2_def *reg, 1358 enum rtw89_rf_path rf_path, 1359 struct rtw89_fw_h2c_rf_reg_info *info) 1360 { 1361 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1362 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1363 1364 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1365 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1366 rf_path, info->curr_idx); 1367 return; 1368 } 1369 1370 info->rtw89_phy_config_rf_h2c[page][idx] = 1371 cpu_to_le32((reg->addr << 20) | reg->data); 1372 info->curr_idx++; 1373 } 1374 1375 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1376 struct rtw89_fw_h2c_rf_reg_info *info) 1377 { 1378 u16 remain = info->curr_idx; 1379 u16 len = 0; 1380 u8 i; 1381 int ret = 0; 1382 1383 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1384 rtw89_warn(rtwdev, 1385 "rf reg h2c total len %d larger than %d\n", 1386 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1387 ret = -EINVAL; 1388 goto out; 1389 } 1390 1391 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1392 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1393 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1394 if (ret) 1395 goto out; 1396 } 1397 out: 1398 info->curr_idx = 0; 1399 1400 return ret; 1401 } 1402 1403 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev, 1404 const struct rtw89_reg2_def *reg, 1405 enum rtw89_rf_path rf_path, 1406 void *extra_data) 1407 { 1408 u32 addr = reg->addr; 1409 1410 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || 1411 addr == 0xfa || addr == 0xf9) 1412 return; 1413 1414 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100) 1415 return; 1416 1417 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1418 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1419 } 1420 1421 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1422 const struct rtw89_reg2_def *reg, 1423 enum rtw89_rf_path rf_path, 1424 void *extra_data) 1425 { 1426 if (reg->addr == 0xfe) { 1427 mdelay(50); 1428 } else if (reg->addr == 0xfd) { 1429 mdelay(5); 1430 } else if (reg->addr == 0xfc) { 1431 mdelay(1); 1432 } else if (reg->addr == 0xfb) { 1433 udelay(50); 1434 } else if (reg->addr == 0xfa) { 1435 udelay(5); 1436 } else if (reg->addr == 0xf9) { 1437 udelay(1); 1438 } else { 1439 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1440 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1441 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1442 } 1443 } 1444 1445 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1446 const struct rtw89_reg2_def *reg, 1447 enum rtw89_rf_path rf_path, 1448 void *extra_data) 1449 { 1450 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1451 1452 if (reg->addr < 0x100) 1453 return; 1454 1455 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1456 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1457 } 1458 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1459 1460 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1461 const struct rtw89_phy_table *table, 1462 u32 *headline_size, u32 *headline_idx, 1463 u8 rfe, u8 cv) 1464 { 1465 const struct rtw89_reg2_def *reg; 1466 u32 headline; 1467 u32 compare, target; 1468 u8 rfe_para, cv_para; 1469 u8 cv_max = 0; 1470 bool case_matched = false; 1471 u32 i; 1472 1473 for (i = 0; i < table->n_regs; i++) { 1474 reg = &table->regs[i]; 1475 headline = get_phy_headline(reg->addr); 1476 if (headline != PHY_HEADLINE_VALID) 1477 break; 1478 } 1479 *headline_size = i; 1480 if (*headline_size == 0) 1481 return 0; 1482 1483 /* case 1: RFE match, CV match */ 1484 compare = get_phy_compare(rfe, cv); 1485 for (i = 0; i < *headline_size; i++) { 1486 reg = &table->regs[i]; 1487 target = get_phy_target(reg->addr); 1488 if (target == compare) { 1489 *headline_idx = i; 1490 return 0; 1491 } 1492 } 1493 1494 /* case 2: RFE match, CV don't care */ 1495 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1496 for (i = 0; i < *headline_size; i++) { 1497 reg = &table->regs[i]; 1498 target = get_phy_target(reg->addr); 1499 if (target == compare) { 1500 *headline_idx = i; 1501 return 0; 1502 } 1503 } 1504 1505 /* case 3: RFE match, CV max in table */ 1506 for (i = 0; i < *headline_size; i++) { 1507 reg = &table->regs[i]; 1508 rfe_para = get_phy_cond_rfe(reg->addr); 1509 cv_para = get_phy_cond_cv(reg->addr); 1510 if (rfe_para == rfe) { 1511 if (cv_para >= cv_max) { 1512 cv_max = cv_para; 1513 *headline_idx = i; 1514 case_matched = true; 1515 } 1516 } 1517 } 1518 1519 if (case_matched) 1520 return 0; 1521 1522 /* case 4: RFE don't care, CV max in table */ 1523 for (i = 0; i < *headline_size; i++) { 1524 reg = &table->regs[i]; 1525 rfe_para = get_phy_cond_rfe(reg->addr); 1526 cv_para = get_phy_cond_cv(reg->addr); 1527 if (rfe_para == PHY_COND_DONT_CARE) { 1528 if (cv_para >= cv_max) { 1529 cv_max = cv_para; 1530 *headline_idx = i; 1531 case_matched = true; 1532 } 1533 } 1534 } 1535 1536 if (case_matched) 1537 return 0; 1538 1539 return -EINVAL; 1540 } 1541 1542 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1543 const struct rtw89_phy_table *table, 1544 void (*config)(struct rtw89_dev *rtwdev, 1545 const struct rtw89_reg2_def *reg, 1546 enum rtw89_rf_path rf_path, 1547 void *data), 1548 void *extra_data) 1549 { 1550 const struct rtw89_reg2_def *reg; 1551 enum rtw89_rf_path rf_path = table->rf_path; 1552 u8 rfe = rtwdev->efuse.rfe_type; 1553 u8 cv = rtwdev->hal.cv; 1554 u32 i; 1555 u32 headline_size = 0, headline_idx = 0; 1556 u32 target = 0, cfg_target; 1557 u8 cond; 1558 bool is_matched = true; 1559 bool target_found = false; 1560 int ret; 1561 1562 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1563 &headline_idx, rfe, cv); 1564 if (ret) { 1565 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1566 return; 1567 } 1568 1569 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1570 for (i = headline_size; i < table->n_regs; i++) { 1571 reg = &table->regs[i]; 1572 cond = get_phy_cond(reg->addr); 1573 switch (cond) { 1574 case PHY_COND_BRANCH_IF: 1575 case PHY_COND_BRANCH_ELIF: 1576 target = get_phy_target(reg->addr); 1577 break; 1578 case PHY_COND_BRANCH_ELSE: 1579 is_matched = false; 1580 if (!target_found) { 1581 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1582 reg->addr, reg->data); 1583 return; 1584 } 1585 break; 1586 case PHY_COND_BRANCH_END: 1587 is_matched = true; 1588 target_found = false; 1589 break; 1590 case PHY_COND_CHECK: 1591 if (target_found) { 1592 is_matched = false; 1593 break; 1594 } 1595 1596 if (target == cfg_target) { 1597 is_matched = true; 1598 target_found = true; 1599 } else { 1600 is_matched = false; 1601 target_found = false; 1602 } 1603 break; 1604 default: 1605 if (is_matched) 1606 config(rtwdev, reg, rf_path, extra_data); 1607 break; 1608 } 1609 } 1610 } 1611 1612 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1613 { 1614 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1615 const struct rtw89_chip_info *chip = rtwdev->chip; 1616 const struct rtw89_phy_table *bb_table; 1617 const struct rtw89_phy_table *bb_gain_table; 1618 1619 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table; 1620 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1621 if (rtwdev->dbcc_en) 1622 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, 1623 (void *)RTW89_PHY_1); 1624 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1625 1626 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table; 1627 if (bb_gain_table) 1628 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1629 chip->phy_def->config_bb_gain, NULL); 1630 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1631 } 1632 1633 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1634 { 1635 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1636 udelay(1); 1637 return rtw89_phy_read32(rtwdev, 0x8080); 1638 } 1639 1640 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio) 1641 { 1642 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1643 enum rtw89_rf_path rf_path, void *data); 1644 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1645 const struct rtw89_chip_info *chip = rtwdev->chip; 1646 const struct rtw89_phy_table *rf_table; 1647 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1648 u8 path; 1649 1650 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1651 if (!rf_reg_info) 1652 return; 1653 1654 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1655 rf_table = elm_info->rf_radio[path] ? 1656 elm_info->rf_radio[path] : chip->rf_table[path]; 1657 rf_reg_info->rf_path = rf_table->rf_path; 1658 if (noio) 1659 config = rtw89_phy_config_rf_reg_noio; 1660 else 1661 config = rf_table->config ? rf_table->config : 1662 rtw89_phy_config_rf_reg; 1663 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1664 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1665 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1666 rf_reg_info->rf_path); 1667 } 1668 kfree(rf_reg_info); 1669 } 1670 1671 static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev) 1672 { 1673 const struct rtw89_chip_info *chip = rtwdev->chip; 1674 u32 val; 1675 int ret; 1676 1677 /* IQK/DPK clock & reset */ 1678 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3); 1679 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1); 1680 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000); 1681 if (chip->chip_id != RTL8851B) 1682 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000); 1683 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8852BT) 1684 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2); 1685 1686 /* check 0x8080 */ 1687 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8); 1688 1689 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1690 1000, false, rtwdev); 1691 if (ret) 1692 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1693 } 1694 1695 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1696 { 1697 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1698 const struct rtw89_chip_info *chip = rtwdev->chip; 1699 const struct rtw89_phy_table *nctl_table; 1700 1701 rtw89_phy_preinit_rf_nctl(rtwdev); 1702 1703 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table; 1704 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1705 1706 if (chip->nctl_post_table) 1707 rtw89_rfk_parser(rtwdev, chip->nctl_post_table); 1708 } 1709 1710 static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr) 1711 { 1712 u32 phy_page = addr >> 8; 1713 u32 ofst = 0; 1714 1715 switch (phy_page) { 1716 case 0x6: 1717 case 0x7: 1718 case 0x8: 1719 case 0x9: 1720 case 0xa: 1721 case 0xb: 1722 case 0xc: 1723 case 0xd: 1724 case 0x19: 1725 case 0x1a: 1726 case 0x1b: 1727 ofst = 0x2000; 1728 break; 1729 default: 1730 /* warning case */ 1731 ofst = 0; 1732 break; 1733 } 1734 1735 if (phy_page >= 0x40 && phy_page <= 0x4f) 1736 ofst = 0x2000; 1737 1738 return ofst; 1739 } 1740 1741 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1742 u32 data, enum rtw89_phy_idx phy_idx) 1743 { 1744 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1745 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1746 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1747 } 1748 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1749 1750 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1751 enum rtw89_phy_idx phy_idx) 1752 { 1753 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1754 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1755 return rtw89_phy_read32_mask(rtwdev, addr, mask); 1756 } 1757 EXPORT_SYMBOL(rtw89_phy_read32_idx); 1758 1759 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1760 u32 val) 1761 { 1762 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1763 1764 if (!rtwdev->dbcc_en) 1765 return; 1766 1767 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1768 } 1769 EXPORT_SYMBOL(rtw89_phy_set_phy_regs); 1770 1771 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1772 const struct rtw89_phy_reg3_tbl *tbl) 1773 { 1774 const struct rtw89_reg3_def *reg3; 1775 int i; 1776 1777 for (i = 0; i < tbl->size; i++) { 1778 reg3 = &tbl->reg3[i]; 1779 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1780 } 1781 } 1782 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1783 1784 static const u8 rtw89_rs_idx_num_ax[] = { 1785 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM, 1786 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM, 1787 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX, 1788 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM, 1789 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX, 1790 }; 1791 1792 static const u8 rtw89_rs_nss_num_ax[] = { 1793 [RTW89_RS_CCK] = 1, 1794 [RTW89_RS_OFDM] = 1, 1795 [RTW89_RS_MCS] = RTW89_NSS_NUM, 1796 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM, 1797 [RTW89_RS_OFFSET] = 1, 1798 }; 1799 1800 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, 1801 struct rtw89_txpwr_byrate *head, 1802 const struct rtw89_rate_desc *desc) 1803 { 1804 switch (desc->rs) { 1805 case RTW89_RS_CCK: 1806 return &head->cck[desc->idx]; 1807 case RTW89_RS_OFDM: 1808 return &head->ofdm[desc->idx]; 1809 case RTW89_RS_MCS: 1810 return &head->mcs[desc->ofdma][desc->nss][desc->idx]; 1811 case RTW89_RS_HEDCM: 1812 return &head->hedcm[desc->ofdma][desc->nss][desc->idx]; 1813 case RTW89_RS_OFFSET: 1814 return &head->offset[desc->idx]; 1815 default: 1816 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs); 1817 return &head->trap; 1818 } 1819 } 1820 1821 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1822 const struct rtw89_txpwr_table *tbl) 1823 { 1824 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1825 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1826 struct rtw89_txpwr_byrate *byr_head; 1827 struct rtw89_rate_desc desc = {}; 1828 s8 *byr; 1829 u32 data; 1830 u8 i; 1831 1832 for (; cfg < end; cfg++) { 1833 byr_head = &rtwdev->byr[cfg->band][0]; 1834 desc.rs = cfg->rs; 1835 desc.nss = cfg->nss; 1836 data = cfg->data; 1837 1838 for (i = 0; i < cfg->len; i++, data >>= 8) { 1839 desc.idx = cfg->shf + i; 1840 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc); 1841 *byr = data & 0xff; 1842 } 1843 } 1844 } 1845 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1846 1847 static s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf) 1848 { 1849 const struct rtw89_chip_info *chip = rtwdev->chip; 1850 1851 return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac); 1852 } 1853 1854 static s8 rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev *rtwdev, s8 dbm) 1855 { 1856 const struct rtw89_chip_info *chip = rtwdev->chip; 1857 1858 return clamp_t(s16, dbm << chip->txpwr_factor_mac, -64, 63); 1859 } 1860 1861 static s8 rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm) 1862 { 1863 const u8 tssi_deviation_point = 0; 1864 const u8 tssi_max_deviation = 2; 1865 1866 if (dbm <= tssi_deviation_point) 1867 dbm -= tssi_max_deviation; 1868 1869 return dbm; 1870 } 1871 1872 static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band) 1873 { 1874 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1875 const struct rtw89_reg_6ghz_tpe *tpe = ®ulatory->reg_6ghz_tpe; 1876 s8 cstr = S8_MAX; 1877 1878 if (band == RTW89_BAND_6G && tpe->valid) 1879 cstr = rtw89_phy_txpwr_dbm_without_tolerance(tpe->constraint); 1880 1881 return rtw89_phy_txpwr_dbm_to_mac(rtwdev, cstr); 1882 } 1883 1884 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, 1885 const struct rtw89_rate_desc *rate_desc) 1886 { 1887 struct rtw89_txpwr_byrate *byr_head; 1888 s8 *byr; 1889 1890 if (rate_desc->rs == RTW89_RS_CCK) 1891 band = RTW89_BAND_2G; 1892 1893 byr_head = &rtwdev->byr[band][bw]; 1894 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc); 1895 1896 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr); 1897 } 1898 1899 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1900 { 1901 switch (channel_6g) { 1902 case 1 ... 29: 1903 return (channel_6g - 1) / 2; 1904 case 33 ... 61: 1905 return (channel_6g - 3) / 2; 1906 case 65 ... 93: 1907 return (channel_6g - 5) / 2; 1908 case 97 ... 125: 1909 return (channel_6g - 7) / 2; 1910 case 129 ... 157: 1911 return (channel_6g - 9) / 2; 1912 case 161 ... 189: 1913 return (channel_6g - 11) / 2; 1914 case 193 ... 221: 1915 return (channel_6g - 13) / 2; 1916 case 225 ... 253: 1917 return (channel_6g - 15) / 2; 1918 default: 1919 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1920 return 0; 1921 } 1922 } 1923 1924 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1925 { 1926 if (band == RTW89_BAND_6G) 1927 return rtw89_channel_6g_to_idx(rtwdev, channel); 1928 1929 switch (channel) { 1930 case 1 ... 14: 1931 return channel - 1; 1932 case 36 ... 64: 1933 return (channel - 36) / 2; 1934 case 100 ... 144: 1935 return ((channel - 100) / 2) + 15; 1936 case 149 ... 177: 1937 return ((channel - 149) / 2) + 38; 1938 default: 1939 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1940 return 0; 1941 } 1942 } 1943 1944 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1945 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1946 { 1947 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1948 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 1949 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 1950 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 1951 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1952 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 1953 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 1954 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1955 u8 regd = rtw89_regd_get(rtwdev, band); 1956 u8 reg6 = regulatory->reg_6ghz_power; 1957 s8 lmt = 0, sar; 1958 s8 cstr; 1959 1960 switch (band) { 1961 case RTW89_BAND_2G: 1962 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1963 if (lmt) 1964 break; 1965 1966 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1967 break; 1968 case RTW89_BAND_5G: 1969 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1970 if (lmt) 1971 break; 1972 1973 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1974 break; 1975 case RTW89_BAND_6G: 1976 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx]; 1977 if (lmt) 1978 break; 1979 1980 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW] 1981 [RTW89_REG_6GHZ_POWER_DFLT] 1982 [ch_idx]; 1983 break; 1984 default: 1985 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1986 return 0; 1987 } 1988 1989 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt); 1990 sar = rtw89_query_sar(rtwdev, freq); 1991 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band); 1992 1993 return min3(lmt, sar, cstr); 1994 } 1995 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1996 1997 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 1998 do { \ 1999 u8 __i; \ 2000 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 2001 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 2002 band, \ 2003 bw, ntx, \ 2004 rs, __i, \ 2005 (ch)); \ 2006 } while (0) 2007 2008 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev, 2009 struct rtw89_txpwr_limit_ax *lmt, 2010 u8 band, u8 ntx, u8 ch) 2011 { 2012 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 2013 ntx, RTW89_RS_CCK, ch); 2014 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 2015 ntx, RTW89_RS_CCK, ch); 2016 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2017 ntx, RTW89_RS_OFDM, ch); 2018 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2019 RTW89_CHANNEL_WIDTH_20, 2020 ntx, RTW89_RS_MCS, ch); 2021 } 2022 2023 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev, 2024 struct rtw89_txpwr_limit_ax *lmt, 2025 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2026 { 2027 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 2028 ntx, RTW89_RS_CCK, ch - 2); 2029 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 2030 ntx, RTW89_RS_CCK, ch); 2031 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2032 ntx, RTW89_RS_OFDM, pri_ch); 2033 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2034 RTW89_CHANNEL_WIDTH_20, 2035 ntx, RTW89_RS_MCS, ch - 2); 2036 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2037 RTW89_CHANNEL_WIDTH_20, 2038 ntx, RTW89_RS_MCS, ch + 2); 2039 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2040 RTW89_CHANNEL_WIDTH_40, 2041 ntx, RTW89_RS_MCS, ch); 2042 } 2043 2044 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev, 2045 struct rtw89_txpwr_limit_ax *lmt, 2046 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2047 { 2048 s8 val_0p5_n[RTW89_BF_NUM]; 2049 s8 val_0p5_p[RTW89_BF_NUM]; 2050 u8 i; 2051 2052 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2053 ntx, RTW89_RS_OFDM, pri_ch); 2054 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2055 RTW89_CHANNEL_WIDTH_20, 2056 ntx, RTW89_RS_MCS, ch - 6); 2057 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2058 RTW89_CHANNEL_WIDTH_20, 2059 ntx, RTW89_RS_MCS, ch - 2); 2060 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 2061 RTW89_CHANNEL_WIDTH_20, 2062 ntx, RTW89_RS_MCS, ch + 2); 2063 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 2064 RTW89_CHANNEL_WIDTH_20, 2065 ntx, RTW89_RS_MCS, ch + 6); 2066 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2067 RTW89_CHANNEL_WIDTH_40, 2068 ntx, RTW89_RS_MCS, ch - 4); 2069 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 2070 RTW89_CHANNEL_WIDTH_40, 2071 ntx, RTW89_RS_MCS, ch + 4); 2072 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 2073 RTW89_CHANNEL_WIDTH_80, 2074 ntx, RTW89_RS_MCS, ch); 2075 2076 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 2077 ntx, RTW89_RS_MCS, ch - 4); 2078 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 2079 ntx, RTW89_RS_MCS, ch + 4); 2080 2081 for (i = 0; i < RTW89_BF_NUM; i++) 2082 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 2083 } 2084 2085 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev, 2086 struct rtw89_txpwr_limit_ax *lmt, 2087 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2088 { 2089 s8 val_0p5_n[RTW89_BF_NUM]; 2090 s8 val_0p5_p[RTW89_BF_NUM]; 2091 s8 val_2p5_n[RTW89_BF_NUM]; 2092 s8 val_2p5_p[RTW89_BF_NUM]; 2093 u8 i; 2094 2095 /* fill ofdm section */ 2096 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2097 ntx, RTW89_RS_OFDM, pri_ch); 2098 2099 /* fill mcs 20m section */ 2100 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2101 RTW89_CHANNEL_WIDTH_20, 2102 ntx, RTW89_RS_MCS, ch - 14); 2103 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2104 RTW89_CHANNEL_WIDTH_20, 2105 ntx, RTW89_RS_MCS, ch - 10); 2106 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 2107 RTW89_CHANNEL_WIDTH_20, 2108 ntx, RTW89_RS_MCS, ch - 6); 2109 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 2110 RTW89_CHANNEL_WIDTH_20, 2111 ntx, RTW89_RS_MCS, ch - 2); 2112 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 2113 RTW89_CHANNEL_WIDTH_20, 2114 ntx, RTW89_RS_MCS, ch + 2); 2115 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 2116 RTW89_CHANNEL_WIDTH_20, 2117 ntx, RTW89_RS_MCS, ch + 6); 2118 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 2119 RTW89_CHANNEL_WIDTH_20, 2120 ntx, RTW89_RS_MCS, ch + 10); 2121 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 2122 RTW89_CHANNEL_WIDTH_20, 2123 ntx, RTW89_RS_MCS, ch + 14); 2124 2125 /* fill mcs 40m section */ 2126 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2127 RTW89_CHANNEL_WIDTH_40, 2128 ntx, RTW89_RS_MCS, ch - 12); 2129 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 2130 RTW89_CHANNEL_WIDTH_40, 2131 ntx, RTW89_RS_MCS, ch - 4); 2132 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 2133 RTW89_CHANNEL_WIDTH_40, 2134 ntx, RTW89_RS_MCS, ch + 4); 2135 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 2136 RTW89_CHANNEL_WIDTH_40, 2137 ntx, RTW89_RS_MCS, ch + 12); 2138 2139 /* fill mcs 80m section */ 2140 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 2141 RTW89_CHANNEL_WIDTH_80, 2142 ntx, RTW89_RS_MCS, ch - 8); 2143 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 2144 RTW89_CHANNEL_WIDTH_80, 2145 ntx, RTW89_RS_MCS, ch + 8); 2146 2147 /* fill mcs 160m section */ 2148 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 2149 RTW89_CHANNEL_WIDTH_160, 2150 ntx, RTW89_RS_MCS, ch); 2151 2152 /* fill mcs 40m 0p5 section */ 2153 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 2154 ntx, RTW89_RS_MCS, ch - 4); 2155 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 2156 ntx, RTW89_RS_MCS, ch + 4); 2157 2158 for (i = 0; i < RTW89_BF_NUM; i++) 2159 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 2160 2161 /* fill mcs 40m 2p5 section */ 2162 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 2163 ntx, RTW89_RS_MCS, ch - 8); 2164 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 2165 ntx, RTW89_RS_MCS, ch + 8); 2166 2167 for (i = 0; i < RTW89_BF_NUM; i++) 2168 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 2169 } 2170 2171 static 2172 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev, 2173 const struct rtw89_chan *chan, 2174 struct rtw89_txpwr_limit_ax *lmt, 2175 u8 ntx) 2176 { 2177 u8 band = chan->band_type; 2178 u8 pri_ch = chan->primary_channel; 2179 u8 ch = chan->channel; 2180 u8 bw = chan->band_width; 2181 2182 memset(lmt, 0, sizeof(*lmt)); 2183 2184 switch (bw) { 2185 case RTW89_CHANNEL_WIDTH_20: 2186 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch); 2187 break; 2188 case RTW89_CHANNEL_WIDTH_40: 2189 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch, 2190 pri_ch); 2191 break; 2192 case RTW89_CHANNEL_WIDTH_80: 2193 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch, 2194 pri_ch); 2195 break; 2196 case RTW89_CHANNEL_WIDTH_160: 2197 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch, 2198 pri_ch); 2199 break; 2200 } 2201 } 2202 2203 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 2204 u8 ru, u8 ntx, u8 ch) 2205 { 2206 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 2207 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 2208 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 2209 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 2210 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 2211 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 2212 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 2213 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 2214 u8 regd = rtw89_regd_get(rtwdev, band); 2215 u8 reg6 = regulatory->reg_6ghz_power; 2216 s8 lmt_ru = 0, sar; 2217 s8 cstr; 2218 2219 switch (band) { 2220 case RTW89_BAND_2G: 2221 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 2222 if (lmt_ru) 2223 break; 2224 2225 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 2226 break; 2227 case RTW89_BAND_5G: 2228 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 2229 if (lmt_ru) 2230 break; 2231 2232 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 2233 break; 2234 case RTW89_BAND_6G: 2235 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx]; 2236 if (lmt_ru) 2237 break; 2238 2239 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW] 2240 [RTW89_REG_6GHZ_POWER_DFLT] 2241 [ch_idx]; 2242 break; 2243 default: 2244 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 2245 return 0; 2246 } 2247 2248 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 2249 sar = rtw89_query_sar(rtwdev, freq); 2250 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band); 2251 2252 return min3(lmt_ru, sar, cstr); 2253 } 2254 2255 static void 2256 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev, 2257 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2258 u8 band, u8 ntx, u8 ch) 2259 { 2260 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2261 RTW89_RU26, 2262 ntx, ch); 2263 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2264 RTW89_RU52, 2265 ntx, ch); 2266 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2267 RTW89_RU106, 2268 ntx, ch); 2269 } 2270 2271 static void 2272 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev, 2273 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2274 u8 band, u8 ntx, u8 ch) 2275 { 2276 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2277 RTW89_RU26, 2278 ntx, ch - 2); 2279 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2280 RTW89_RU26, 2281 ntx, ch + 2); 2282 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2283 RTW89_RU52, 2284 ntx, ch - 2); 2285 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2286 RTW89_RU52, 2287 ntx, ch + 2); 2288 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2289 RTW89_RU106, 2290 ntx, ch - 2); 2291 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2292 RTW89_RU106, 2293 ntx, ch + 2); 2294 } 2295 2296 static void 2297 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev, 2298 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2299 u8 band, u8 ntx, u8 ch) 2300 { 2301 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2302 RTW89_RU26, 2303 ntx, ch - 6); 2304 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2305 RTW89_RU26, 2306 ntx, ch - 2); 2307 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2308 RTW89_RU26, 2309 ntx, ch + 2); 2310 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2311 RTW89_RU26, 2312 ntx, ch + 6); 2313 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2314 RTW89_RU52, 2315 ntx, ch - 6); 2316 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2317 RTW89_RU52, 2318 ntx, ch - 2); 2319 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2320 RTW89_RU52, 2321 ntx, ch + 2); 2322 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2323 RTW89_RU52, 2324 ntx, ch + 6); 2325 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2326 RTW89_RU106, 2327 ntx, ch - 6); 2328 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2329 RTW89_RU106, 2330 ntx, ch - 2); 2331 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2332 RTW89_RU106, 2333 ntx, ch + 2); 2334 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2335 RTW89_RU106, 2336 ntx, ch + 6); 2337 } 2338 2339 static void 2340 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev, 2341 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2342 u8 band, u8 ntx, u8 ch) 2343 { 2344 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 2345 int i; 2346 2347 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX); 2348 for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) { 2349 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2350 RTW89_RU26, 2351 ntx, 2352 ch + ofst[i]); 2353 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2354 RTW89_RU52, 2355 ntx, 2356 ch + ofst[i]); 2357 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2358 RTW89_RU106, 2359 ntx, 2360 ch + ofst[i]); 2361 } 2362 } 2363 2364 static 2365 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2366 const struct rtw89_chan *chan, 2367 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2368 u8 ntx) 2369 { 2370 u8 band = chan->band_type; 2371 u8 ch = chan->channel; 2372 u8 bw = chan->band_width; 2373 2374 memset(lmt_ru, 0, sizeof(*lmt_ru)); 2375 2376 switch (bw) { 2377 case RTW89_CHANNEL_WIDTH_20: 2378 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx, 2379 ch); 2380 break; 2381 case RTW89_CHANNEL_WIDTH_40: 2382 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx, 2383 ch); 2384 break; 2385 case RTW89_CHANNEL_WIDTH_80: 2386 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx, 2387 ch); 2388 break; 2389 case RTW89_CHANNEL_WIDTH_160: 2390 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx, 2391 ch); 2392 break; 2393 } 2394 } 2395 2396 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev, 2397 const struct rtw89_chan *chan, 2398 enum rtw89_phy_idx phy_idx) 2399 { 2400 u8 max_nss_num = rtwdev->chip->rf_path_num; 2401 static const u8 rs[] = { 2402 RTW89_RS_CCK, 2403 RTW89_RS_OFDM, 2404 RTW89_RS_MCS, 2405 RTW89_RS_HEDCM, 2406 }; 2407 struct rtw89_rate_desc cur = {}; 2408 u8 band = chan->band_type; 2409 u8 ch = chan->channel; 2410 u32 addr, val; 2411 s8 v[4] = {}; 2412 u8 i; 2413 2414 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2415 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 2416 2417 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4); 2418 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4); 2419 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4); 2420 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4); 2421 2422 addr = R_AX_PWR_BY_RATE; 2423 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) { 2424 for (i = 0; i < ARRAY_SIZE(rs); i++) { 2425 if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]]) 2426 continue; 2427 2428 cur.rs = rs[i]; 2429 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]]; 2430 cur.idx++) { 2431 v[cur.idx % 4] = 2432 rtw89_phy_read_txpwr_byrate(rtwdev, 2433 band, 0, 2434 &cur); 2435 2436 if ((cur.idx + 1) % 4) 2437 continue; 2438 2439 val = FIELD_PREP(GENMASK(7, 0), v[0]) | 2440 FIELD_PREP(GENMASK(15, 8), v[1]) | 2441 FIELD_PREP(GENMASK(23, 16), v[2]) | 2442 FIELD_PREP(GENMASK(31, 24), v[3]); 2443 2444 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 2445 val); 2446 addr += 4; 2447 } 2448 } 2449 } 2450 } 2451 2452 static 2453 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev, 2454 const struct rtw89_chan *chan, 2455 enum rtw89_phy_idx phy_idx) 2456 { 2457 struct rtw89_rate_desc desc = { 2458 .nss = RTW89_NSS_1, 2459 .rs = RTW89_RS_OFFSET, 2460 }; 2461 u8 band = chan->band_type; 2462 s8 v[RTW89_RATE_OFFSET_NUM_AX] = {}; 2463 u32 val; 2464 2465 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 2466 2467 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_AX; desc.idx++) 2468 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc); 2469 2470 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM_AX != 5); 2471 val = FIELD_PREP(GENMASK(3, 0), v[0]) | 2472 FIELD_PREP(GENMASK(7, 4), v[1]) | 2473 FIELD_PREP(GENMASK(11, 8), v[2]) | 2474 FIELD_PREP(GENMASK(15, 12), v[3]) | 2475 FIELD_PREP(GENMASK(19, 16), v[4]); 2476 2477 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 2478 GENMASK(19, 0), val); 2479 } 2480 2481 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev, 2482 const struct rtw89_chan *chan, 2483 enum rtw89_phy_idx phy_idx) 2484 { 2485 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2486 struct rtw89_txpwr_limit_ax lmt; 2487 u8 ch = chan->channel; 2488 u8 bw = chan->band_width; 2489 const s8 *ptr; 2490 u32 addr, val; 2491 u8 i, j; 2492 2493 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2494 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 2495 2496 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ax) != 2497 RTW89_TXPWR_LMT_PAGE_SIZE_AX); 2498 2499 addr = R_AX_PWR_LMT; 2500 for (i = 0; i < max_ntx_num; i++) { 2501 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i); 2502 2503 ptr = (s8 *)&lmt; 2504 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_AX; 2505 j += 4, addr += 4, ptr += 4) { 2506 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2507 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2508 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2509 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2510 2511 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2512 } 2513 } 2514 } 2515 2516 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2517 const struct rtw89_chan *chan, 2518 enum rtw89_phy_idx phy_idx) 2519 { 2520 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2521 struct rtw89_txpwr_limit_ru_ax lmt_ru; 2522 u8 ch = chan->channel; 2523 u8 bw = chan->band_width; 2524 const s8 *ptr; 2525 u32 addr, val; 2526 u8 i, j; 2527 2528 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2529 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 2530 2531 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) != 2532 RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX); 2533 2534 addr = R_AX_PWR_RU_LMT; 2535 for (i = 0; i < max_ntx_num; i++) { 2536 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i); 2537 2538 ptr = (s8 *)&lmt_ru; 2539 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX; 2540 j += 4, addr += 4, ptr += 4) { 2541 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2542 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2543 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2544 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2545 2546 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2547 } 2548 } 2549 } 2550 2551 struct rtw89_phy_iter_ra_data { 2552 struct rtw89_dev *rtwdev; 2553 struct sk_buff *c2h; 2554 }; 2555 2556 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 2557 { 2558 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 2559 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2560 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2561 const struct rtw89_c2h_ra_rpt *c2h = 2562 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data; 2563 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 2564 const struct rtw89_chip_info *chip = rtwdev->chip; 2565 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE; 2566 u8 mode, rate, bw, giltf, mac_id; 2567 u16 legacy_bitrate; 2568 bool valid; 2569 u8 mcs = 0; 2570 u8 t; 2571 2572 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID); 2573 if (mac_id != rtwsta->mac_id) 2574 return; 2575 2576 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS); 2577 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW); 2578 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF); 2579 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL); 2580 2581 if (format_v1) { 2582 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7); 2583 rate |= u8_encode_bits(t, BIT(7)); 2584 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2); 2585 bw |= u8_encode_bits(t, BIT(2)); 2586 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2); 2587 mode |= u8_encode_bits(t, BIT(2)); 2588 } 2589 2590 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2591 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2592 if (!valid) 2593 return; 2594 } 2595 2596 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2597 2598 switch (mode) { 2599 case RTW89_RA_RPT_MODE_LEGACY: 2600 ra_report->txrate.legacy = legacy_bitrate; 2601 break; 2602 case RTW89_RA_RPT_MODE_HT: 2603 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2604 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2605 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2606 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2607 else 2608 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2609 ra_report->txrate.mcs = rate; 2610 if (giltf) 2611 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2612 mcs = ra_report->txrate.mcs & 0x07; 2613 break; 2614 case RTW89_RA_RPT_MODE_VHT: 2615 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2616 ra_report->txrate.mcs = format_v1 ? 2617 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2618 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2619 ra_report->txrate.nss = format_v1 ? 2620 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2621 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2622 if (giltf) 2623 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2624 mcs = ra_report->txrate.mcs; 2625 break; 2626 case RTW89_RA_RPT_MODE_HE: 2627 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2628 ra_report->txrate.mcs = format_v1 ? 2629 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2630 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2631 ra_report->txrate.nss = format_v1 ? 2632 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2633 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2634 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2635 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2636 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2637 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2638 else 2639 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2640 mcs = ra_report->txrate.mcs; 2641 break; 2642 case RTW89_RA_RPT_MODE_EHT: 2643 ra_report->txrate.flags |= RATE_INFO_FLAGS_EHT_MCS; 2644 ra_report->txrate.mcs = u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1); 2645 ra_report->txrate.nss = u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1; 2646 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2647 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_0_8; 2648 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2649 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_1_6; 2650 else 2651 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_3_2; 2652 mcs = ra_report->txrate.mcs; 2653 break; 2654 } 2655 2656 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2657 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2658 ra_report->hw_rate = format_v1 ? 2659 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) | 2660 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) : 2661 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) | 2662 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL); 2663 ra_report->might_fallback_legacy = mcs <= 2; 2664 sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2665 rtwsta->max_agg_wait = sta->deflink.agg.max_rc_amsdu_len / 1500 - 1; 2666 } 2667 2668 static void 2669 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2670 { 2671 struct rtw89_phy_iter_ra_data ra_data; 2672 2673 ra_data.rtwdev = rtwdev; 2674 ra_data.c2h = c2h; 2675 ieee80211_iterate_stations_atomic(rtwdev->hw, 2676 rtw89_phy_c2h_ra_rpt_iter, 2677 &ra_data); 2678 } 2679 2680 static 2681 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2682 struct sk_buff *c2h, u32 len) = { 2683 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2684 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2685 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2686 }; 2687 2688 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, 2689 enum rtw89_phy_c2h_rfk_log_func func, 2690 void *content, u16 len) 2691 { 2692 struct rtw89_c2h_rf_txgapk_rpt_log *txgapk; 2693 struct rtw89_c2h_rf_rxdck_rpt_log *rxdck; 2694 struct rtw89_c2h_rf_dack_rpt_log *dack; 2695 struct rtw89_c2h_rf_dpk_rpt_log *dpk; 2696 2697 switch (func) { 2698 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: 2699 if (len != sizeof(*dpk)) 2700 goto out; 2701 2702 dpk = content; 2703 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2704 "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n", 2705 dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok); 2706 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2707 "DPK txagc:%2ph ther:%2ph gs:%2ph dc_i:%4ph dc_q:%4ph\n", 2708 dpk->txagc, dpk->ther, dpk->gs, dpk->dc_i, dpk->dc_q); 2709 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2710 "DPK corr_v:%2ph corr_i:%2ph to:%2ph ov:%2ph\n", 2711 dpk->corr_val, dpk->corr_idx, dpk->is_timeout, dpk->rxbb_ov); 2712 return; 2713 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK: 2714 if (len != sizeof(*dack)) 2715 goto out; 2716 2717 dack = content; 2718 2719 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ver=0x%x 0x%x\n", 2720 dack->fwdack_ver, dack->fwdack_rpt_ver); 2721 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK ic = [0x%x, 0x%x]\n", 2722 dack->cdack_d[0][0][0], dack->cdack_d[0][0][1]); 2723 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK qc = [0x%x, 0x%x]\n", 2724 dack->cdack_d[0][1][0], dack->cdack_d[0][1][1]); 2725 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK ic = [0x%x, 0x%x]\n", 2726 dack->cdack_d[1][0][0], dack->cdack_d[1][0][1]); 2727 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK qc = [0x%x, 0x%x]\n", 2728 dack->cdack_d[1][1][0], dack->cdack_d[1][1][1]); 2729 2730 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = [0x%x, 0x%x]\n", 2731 dack->addck2_d[0][0][0], dack->addck2_d[0][0][1]); 2732 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK qc = [0x%x, 0x%x]\n", 2733 dack->addck2_d[0][1][0], dack->addck2_d[0][1][1]); 2734 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK ic = [0x%x, 0x%x]\n", 2735 dack->addck2_d[1][0][0], dack->addck2_d[1][0][1]); 2736 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK qc = [0x%x, 0x%x]\n", 2737 dack->addck2_d[1][1][0], dack->addck2_d[1][1][1]); 2738 2739 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_GAINK ic = 0x%x, qc = 0x%x\n", 2740 dack->adgaink_d[0][0], dack->adgaink_d[0][1]); 2741 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_GAINK ic = 0x%x, qc = 0x%x\n", 2742 dack->adgaink_d[1][0], dack->adgaink_d[1][1]); 2743 2744 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n", 2745 dack->dadck_d[0][0], dack->dadck_d[0][1]); 2746 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n", 2747 dack->dadck_d[1][0], dack->dadck_d[1][1]); 2748 2749 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask iqc = 0x%x\n", 2750 dack->biask_d[0][0]); 2751 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 biask iqc = 0x%x\n", 2752 dack->biask_d[1][0]); 2753 2754 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic: %*ph\n", 2755 (int)sizeof(dack->msbk_d[0][0]), dack->msbk_d[0][0]); 2756 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc: %*ph\n", 2757 (int)sizeof(dack->msbk_d[0][1]), dack->msbk_d[0][1]); 2758 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic: %*ph\n", 2759 (int)sizeof(dack->msbk_d[1][0]), dack->msbk_d[1][0]); 2760 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc: %*ph\n", 2761 (int)sizeof(dack->msbk_d[1][1]), dack->msbk_d[1][1]); 2762 return; 2763 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: 2764 if (len != sizeof(*rxdck)) 2765 goto out; 2766 2767 rxdck = content; 2768 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2769 "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n", 2770 rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch, 2771 rxdck->timeout); 2772 return; 2773 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: 2774 if (len != sizeof(*txgapk)) 2775 goto out; 2776 2777 txgapk = content; 2778 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2779 "[TXGAPK]rpt r0x8010[0]=0x%x, r0x8010[1]=0x%x\n", 2780 le32_to_cpu(txgapk->r0x8010[0]), 2781 le32_to_cpu(txgapk->r0x8010[1])); 2782 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_id = %d\n", 2783 txgapk->chk_id); 2784 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_cnt = %d\n", 2785 le32_to_cpu(txgapk->chk_cnt)); 2786 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n", 2787 txgapk->ver); 2788 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n", 2789 txgapk->rsv1); 2790 2791 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n", 2792 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]); 2793 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[0] = %*ph\n", 2794 (int)sizeof(txgapk->power_d[0]), txgapk->power_d[0]); 2795 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[1] = %*ph\n", 2796 (int)sizeof(txgapk->track_d[1]), txgapk->track_d[1]); 2797 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n", 2798 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]); 2799 return; 2800 default: 2801 break; 2802 } 2803 2804 out: 2805 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2806 "unexpected RFK func %d report log with length %d\n", func, len); 2807 } 2808 2809 static bool rtw89_phy_c2h_rfk_run_log(struct rtw89_dev *rtwdev, 2810 enum rtw89_phy_c2h_rfk_log_func func, 2811 void *content, u16 len) 2812 { 2813 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 2814 const struct rtw89_c2h_rf_run_log *log = content; 2815 const struct rtw89_fw_element_hdr *elm; 2816 u32 fmt_idx; 2817 u16 offset; 2818 2819 if (sizeof(*log) != len) 2820 return false; 2821 2822 if (!elm_info->rfk_log_fmt) 2823 return false; 2824 2825 elm = elm_info->rfk_log_fmt->elm[func]; 2826 fmt_idx = le32_to_cpu(log->fmt_idx); 2827 if (!elm || fmt_idx >= elm->u.rfk_log_fmt.nr) 2828 return false; 2829 2830 offset = le16_to_cpu(elm->u.rfk_log_fmt.offset[fmt_idx]); 2831 if (offset == 0) 2832 return false; 2833 2834 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset], 2835 le32_to_cpu(log->arg[0]), le32_to_cpu(log->arg[1]), 2836 le32_to_cpu(log->arg[2]), le32_to_cpu(log->arg[3])); 2837 2838 return true; 2839 } 2840 2841 static void rtw89_phy_c2h_rfk_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 2842 u32 len, enum rtw89_phy_c2h_rfk_log_func func, 2843 const char *rfk_name) 2844 { 2845 struct rtw89_c2h_hdr *c2h_hdr = (struct rtw89_c2h_hdr *)c2h->data; 2846 struct rtw89_c2h_rf_log_hdr *log_hdr; 2847 void *log_ptr = c2h_hdr; 2848 u16 content_len; 2849 u16 chunk_len; 2850 bool handled; 2851 2852 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK)) 2853 return; 2854 2855 log_ptr += sizeof(*c2h_hdr); 2856 len -= sizeof(*c2h_hdr); 2857 2858 while (len > sizeof(*log_hdr)) { 2859 log_hdr = log_ptr; 2860 content_len = le16_to_cpu(log_hdr->len); 2861 chunk_len = content_len + sizeof(*log_hdr); 2862 2863 if (chunk_len > len) 2864 break; 2865 2866 switch (log_hdr->type) { 2867 case RTW89_RF_RUN_LOG: 2868 handled = rtw89_phy_c2h_rfk_run_log(rtwdev, func, 2869 log_hdr->content, content_len); 2870 if (handled) 2871 break; 2872 2873 rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s run: %*ph\n", 2874 rfk_name, content_len, log_hdr->content); 2875 break; 2876 case RTW89_RF_RPT_LOG: 2877 rtw89_phy_c2h_rfk_rpt_log(rtwdev, func, 2878 log_hdr->content, content_len); 2879 break; 2880 default: 2881 return; 2882 } 2883 2884 log_ptr += chunk_len; 2885 len -= chunk_len; 2886 } 2887 } 2888 2889 static void 2890 rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2891 { 2892 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2893 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK, "IQK"); 2894 } 2895 2896 static void 2897 rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2898 { 2899 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2900 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK, "DPK"); 2901 } 2902 2903 static void 2904 rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2905 { 2906 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2907 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK, "DACK"); 2908 } 2909 2910 static void 2911 rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2912 { 2913 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2914 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK, "RX_DCK"); 2915 } 2916 2917 static void 2918 rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2919 { 2920 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2921 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI, "TSSI"); 2922 } 2923 2924 static void 2925 rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2926 { 2927 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2928 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK, "TXGAPK"); 2929 } 2930 2931 static 2932 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev, 2933 struct sk_buff *c2h, u32 len) = { 2934 [RTW89_PHY_C2H_RFK_LOG_FUNC_IQK] = rtw89_phy_c2h_rfk_log_iqk, 2935 [RTW89_PHY_C2H_RFK_LOG_FUNC_DPK] = rtw89_phy_c2h_rfk_log_dpk, 2936 [RTW89_PHY_C2H_RFK_LOG_FUNC_DACK] = rtw89_phy_c2h_rfk_log_dack, 2937 [RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK] = rtw89_phy_c2h_rfk_log_rxdck, 2938 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi, 2939 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk, 2940 }; 2941 2942 static 2943 void rtw89_phy_rfk_report_prep(struct rtw89_dev *rtwdev) 2944 { 2945 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 2946 2947 wait->state = RTW89_RFK_STATE_START; 2948 wait->start_time = ktime_get(); 2949 reinit_completion(&wait->completion); 2950 } 2951 2952 static 2953 int rtw89_phy_rfk_report_wait(struct rtw89_dev *rtwdev, const char *rfk_name, 2954 unsigned int ms) 2955 { 2956 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 2957 unsigned long time_left; 2958 2959 /* Since we can't receive C2H event during SER, use a fixed delay. */ 2960 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) { 2961 fsleep(1000 * ms / 2); 2962 goto out; 2963 } 2964 2965 time_left = wait_for_completion_timeout(&wait->completion, 2966 msecs_to_jiffies(ms)); 2967 if (time_left == 0) { 2968 rtw89_warn(rtwdev, "failed to wait RF %s\n", rfk_name); 2969 return -ETIMEDOUT; 2970 } else if (wait->state != RTW89_RFK_STATE_OK) { 2971 rtw89_warn(rtwdev, "failed to do RF %s result from state %d\n", 2972 rfk_name, wait->state); 2973 return -EFAULT; 2974 } 2975 2976 out: 2977 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %lld ms to complete\n", 2978 rfk_name, ktime_ms_delta(ktime_get(), wait->start_time)); 2979 2980 return 0; 2981 } 2982 2983 static void 2984 rtw89_phy_c2h_rfk_report_state(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2985 { 2986 const struct rtw89_c2h_rfk_report *report = 2987 (const struct rtw89_c2h_rfk_report *)c2h->data; 2988 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 2989 2990 wait->state = report->state; 2991 wait->version = report->version; 2992 2993 complete(&wait->completion); 2994 2995 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2996 "RFK report state %d with version %d (%*ph)\n", 2997 wait->state, wait->version, 2998 (int)(len - sizeof(report->hdr)), &report->state); 2999 } 3000 3001 static 3002 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev, 3003 struct sk_buff *c2h, u32 len) = { 3004 [RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE] = rtw89_phy_c2h_rfk_report_state, 3005 }; 3006 3007 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 3008 { 3009 switch (class) { 3010 case RTW89_PHY_C2H_RFK_LOG: 3011 switch (func) { 3012 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK: 3013 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: 3014 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK: 3015 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: 3016 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI: 3017 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: 3018 return true; 3019 default: 3020 return false; 3021 } 3022 case RTW89_PHY_C2H_RFK_REPORT: 3023 switch (func) { 3024 case RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE: 3025 return true; 3026 default: 3027 return false; 3028 } 3029 default: 3030 return false; 3031 } 3032 } 3033 3034 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3035 u32 len, u8 class, u8 func) 3036 { 3037 void (*handler)(struct rtw89_dev *rtwdev, 3038 struct sk_buff *c2h, u32 len) = NULL; 3039 3040 switch (class) { 3041 case RTW89_PHY_C2H_CLASS_RA: 3042 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 3043 handler = rtw89_phy_c2h_ra_handler[func]; 3044 break; 3045 case RTW89_PHY_C2H_RFK_LOG: 3046 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_log_handler)) 3047 handler = rtw89_phy_c2h_rfk_log_handler[func]; 3048 break; 3049 case RTW89_PHY_C2H_RFK_REPORT: 3050 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_report_handler)) 3051 handler = rtw89_phy_c2h_rfk_report_handler[func]; 3052 break; 3053 case RTW89_PHY_C2H_CLASS_DM: 3054 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY) 3055 return; 3056 fallthrough; 3057 default: 3058 rtw89_info(rtwdev, "c2h class %d not support\n", class); 3059 return; 3060 } 3061 if (!handler) { 3062 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 3063 func); 3064 return; 3065 } 3066 handler(rtwdev, skb, len); 3067 } 3068 3069 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev, 3070 enum rtw89_phy_idx phy_idx, 3071 unsigned int ms) 3072 { 3073 int ret; 3074 3075 rtw89_phy_rfk_report_prep(rtwdev); 3076 3077 ret = rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx); 3078 if (ret) 3079 return ret; 3080 3081 return rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms); 3082 } 3083 EXPORT_SYMBOL(rtw89_phy_rfk_pre_ntfy_and_wait); 3084 3085 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev, 3086 enum rtw89_phy_idx phy_idx, 3087 const struct rtw89_chan *chan, 3088 enum rtw89_tssi_mode tssi_mode, 3089 unsigned int ms) 3090 { 3091 int ret; 3092 3093 rtw89_phy_rfk_report_prep(rtwdev); 3094 3095 ret = rtw89_fw_h2c_rf_tssi(rtwdev, phy_idx, chan, tssi_mode); 3096 if (ret) 3097 return ret; 3098 3099 return rtw89_phy_rfk_report_wait(rtwdev, "TSSI", ms); 3100 } 3101 EXPORT_SYMBOL(rtw89_phy_rfk_tssi_and_wait); 3102 3103 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev, 3104 enum rtw89_phy_idx phy_idx, 3105 const struct rtw89_chan *chan, 3106 unsigned int ms) 3107 { 3108 int ret; 3109 3110 rtw89_phy_rfk_report_prep(rtwdev); 3111 3112 ret = rtw89_fw_h2c_rf_iqk(rtwdev, phy_idx, chan); 3113 if (ret) 3114 return ret; 3115 3116 return rtw89_phy_rfk_report_wait(rtwdev, "IQK", ms); 3117 } 3118 EXPORT_SYMBOL(rtw89_phy_rfk_iqk_and_wait); 3119 3120 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev, 3121 enum rtw89_phy_idx phy_idx, 3122 const struct rtw89_chan *chan, 3123 unsigned int ms) 3124 { 3125 int ret; 3126 3127 rtw89_phy_rfk_report_prep(rtwdev); 3128 3129 ret = rtw89_fw_h2c_rf_dpk(rtwdev, phy_idx, chan); 3130 if (ret) 3131 return ret; 3132 3133 return rtw89_phy_rfk_report_wait(rtwdev, "DPK", ms); 3134 } 3135 EXPORT_SYMBOL(rtw89_phy_rfk_dpk_and_wait); 3136 3137 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev, 3138 enum rtw89_phy_idx phy_idx, 3139 const struct rtw89_chan *chan, 3140 unsigned int ms) 3141 { 3142 int ret; 3143 3144 rtw89_phy_rfk_report_prep(rtwdev); 3145 3146 ret = rtw89_fw_h2c_rf_txgapk(rtwdev, phy_idx, chan); 3147 if (ret) 3148 return ret; 3149 3150 return rtw89_phy_rfk_report_wait(rtwdev, "TXGAPK", ms); 3151 } 3152 EXPORT_SYMBOL(rtw89_phy_rfk_txgapk_and_wait); 3153 3154 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev, 3155 enum rtw89_phy_idx phy_idx, 3156 const struct rtw89_chan *chan, 3157 unsigned int ms) 3158 { 3159 int ret; 3160 3161 rtw89_phy_rfk_report_prep(rtwdev); 3162 3163 ret = rtw89_fw_h2c_rf_dack(rtwdev, phy_idx, chan); 3164 if (ret) 3165 return ret; 3166 3167 return rtw89_phy_rfk_report_wait(rtwdev, "DACK", ms); 3168 } 3169 EXPORT_SYMBOL(rtw89_phy_rfk_dack_and_wait); 3170 3171 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev, 3172 enum rtw89_phy_idx phy_idx, 3173 const struct rtw89_chan *chan, 3174 unsigned int ms) 3175 { 3176 int ret; 3177 3178 rtw89_phy_rfk_report_prep(rtwdev); 3179 3180 ret = rtw89_fw_h2c_rf_rxdck(rtwdev, phy_idx, chan); 3181 if (ret) 3182 return ret; 3183 3184 return rtw89_phy_rfk_report_wait(rtwdev, "RX_DCK", ms); 3185 } 3186 EXPORT_SYMBOL(rtw89_phy_rfk_rxdck_and_wait); 3187 3188 static u32 phy_tssi_get_cck_group(u8 ch) 3189 { 3190 switch (ch) { 3191 case 1 ... 2: 3192 return 0; 3193 case 3 ... 5: 3194 return 1; 3195 case 6 ... 8: 3196 return 2; 3197 case 9 ... 11: 3198 return 3; 3199 case 12 ... 13: 3200 return 4; 3201 case 14: 3202 return 5; 3203 } 3204 3205 return 0; 3206 } 3207 3208 #define PHY_TSSI_EXTRA_GROUP_BIT BIT(31) 3209 #define PHY_TSSI_EXTRA_GROUP(idx) (PHY_TSSI_EXTRA_GROUP_BIT | (idx)) 3210 #define PHY_IS_TSSI_EXTRA_GROUP(group) ((group) & PHY_TSSI_EXTRA_GROUP_BIT) 3211 #define PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) \ 3212 ((group) & ~PHY_TSSI_EXTRA_GROUP_BIT) 3213 #define PHY_TSSI_EXTRA_GET_GROUP_IDX2(group) \ 3214 (PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) + 1) 3215 3216 static u32 phy_tssi_get_ofdm_group(u8 ch) 3217 { 3218 switch (ch) { 3219 case 1 ... 2: 3220 return 0; 3221 case 3 ... 5: 3222 return 1; 3223 case 6 ... 8: 3224 return 2; 3225 case 9 ... 11: 3226 return 3; 3227 case 12 ... 14: 3228 return 4; 3229 case 36 ... 40: 3230 return 5; 3231 case 41 ... 43: 3232 return PHY_TSSI_EXTRA_GROUP(5); 3233 case 44 ... 48: 3234 return 6; 3235 case 49 ... 51: 3236 return PHY_TSSI_EXTRA_GROUP(6); 3237 case 52 ... 56: 3238 return 7; 3239 case 57 ... 59: 3240 return PHY_TSSI_EXTRA_GROUP(7); 3241 case 60 ... 64: 3242 return 8; 3243 case 100 ... 104: 3244 return 9; 3245 case 105 ... 107: 3246 return PHY_TSSI_EXTRA_GROUP(9); 3247 case 108 ... 112: 3248 return 10; 3249 case 113 ... 115: 3250 return PHY_TSSI_EXTRA_GROUP(10); 3251 case 116 ... 120: 3252 return 11; 3253 case 121 ... 123: 3254 return PHY_TSSI_EXTRA_GROUP(11); 3255 case 124 ... 128: 3256 return 12; 3257 case 129 ... 131: 3258 return PHY_TSSI_EXTRA_GROUP(12); 3259 case 132 ... 136: 3260 return 13; 3261 case 137 ... 139: 3262 return PHY_TSSI_EXTRA_GROUP(13); 3263 case 140 ... 144: 3264 return 14; 3265 case 149 ... 153: 3266 return 15; 3267 case 154 ... 156: 3268 return PHY_TSSI_EXTRA_GROUP(15); 3269 case 157 ... 161: 3270 return 16; 3271 case 162 ... 164: 3272 return PHY_TSSI_EXTRA_GROUP(16); 3273 case 165 ... 169: 3274 return 17; 3275 case 170 ... 172: 3276 return PHY_TSSI_EXTRA_GROUP(17); 3277 case 173 ... 177: 3278 return 18; 3279 } 3280 3281 return 0; 3282 } 3283 3284 static u32 phy_tssi_get_6g_ofdm_group(u8 ch) 3285 { 3286 switch (ch) { 3287 case 1 ... 5: 3288 return 0; 3289 case 6 ... 8: 3290 return PHY_TSSI_EXTRA_GROUP(0); 3291 case 9 ... 13: 3292 return 1; 3293 case 14 ... 16: 3294 return PHY_TSSI_EXTRA_GROUP(1); 3295 case 17 ... 21: 3296 return 2; 3297 case 22 ... 24: 3298 return PHY_TSSI_EXTRA_GROUP(2); 3299 case 25 ... 29: 3300 return 3; 3301 case 33 ... 37: 3302 return 4; 3303 case 38 ... 40: 3304 return PHY_TSSI_EXTRA_GROUP(4); 3305 case 41 ... 45: 3306 return 5; 3307 case 46 ... 48: 3308 return PHY_TSSI_EXTRA_GROUP(5); 3309 case 49 ... 53: 3310 return 6; 3311 case 54 ... 56: 3312 return PHY_TSSI_EXTRA_GROUP(6); 3313 case 57 ... 61: 3314 return 7; 3315 case 65 ... 69: 3316 return 8; 3317 case 70 ... 72: 3318 return PHY_TSSI_EXTRA_GROUP(8); 3319 case 73 ... 77: 3320 return 9; 3321 case 78 ... 80: 3322 return PHY_TSSI_EXTRA_GROUP(9); 3323 case 81 ... 85: 3324 return 10; 3325 case 86 ... 88: 3326 return PHY_TSSI_EXTRA_GROUP(10); 3327 case 89 ... 93: 3328 return 11; 3329 case 97 ... 101: 3330 return 12; 3331 case 102 ... 104: 3332 return PHY_TSSI_EXTRA_GROUP(12); 3333 case 105 ... 109: 3334 return 13; 3335 case 110 ... 112: 3336 return PHY_TSSI_EXTRA_GROUP(13); 3337 case 113 ... 117: 3338 return 14; 3339 case 118 ... 120: 3340 return PHY_TSSI_EXTRA_GROUP(14); 3341 case 121 ... 125: 3342 return 15; 3343 case 129 ... 133: 3344 return 16; 3345 case 134 ... 136: 3346 return PHY_TSSI_EXTRA_GROUP(16); 3347 case 137 ... 141: 3348 return 17; 3349 case 142 ... 144: 3350 return PHY_TSSI_EXTRA_GROUP(17); 3351 case 145 ... 149: 3352 return 18; 3353 case 150 ... 152: 3354 return PHY_TSSI_EXTRA_GROUP(18); 3355 case 153 ... 157: 3356 return 19; 3357 case 161 ... 165: 3358 return 20; 3359 case 166 ... 168: 3360 return PHY_TSSI_EXTRA_GROUP(20); 3361 case 169 ... 173: 3362 return 21; 3363 case 174 ... 176: 3364 return PHY_TSSI_EXTRA_GROUP(21); 3365 case 177 ... 181: 3366 return 22; 3367 case 182 ... 184: 3368 return PHY_TSSI_EXTRA_GROUP(22); 3369 case 185 ... 189: 3370 return 23; 3371 case 193 ... 197: 3372 return 24; 3373 case 198 ... 200: 3374 return PHY_TSSI_EXTRA_GROUP(24); 3375 case 201 ... 205: 3376 return 25; 3377 case 206 ... 208: 3378 return PHY_TSSI_EXTRA_GROUP(25); 3379 case 209 ... 213: 3380 return 26; 3381 case 214 ... 216: 3382 return PHY_TSSI_EXTRA_GROUP(26); 3383 case 217 ... 221: 3384 return 27; 3385 case 225 ... 229: 3386 return 28; 3387 case 230 ... 232: 3388 return PHY_TSSI_EXTRA_GROUP(28); 3389 case 233 ... 237: 3390 return 29; 3391 case 238 ... 240: 3392 return PHY_TSSI_EXTRA_GROUP(29); 3393 case 241 ... 245: 3394 return 30; 3395 case 246 ... 248: 3396 return PHY_TSSI_EXTRA_GROUP(30); 3397 case 249 ... 253: 3398 return 31; 3399 } 3400 3401 return 0; 3402 } 3403 3404 static u32 phy_tssi_get_trim_group(u8 ch) 3405 { 3406 switch (ch) { 3407 case 1 ... 8: 3408 return 0; 3409 case 9 ... 14: 3410 return 1; 3411 case 36 ... 48: 3412 return 2; 3413 case 49 ... 51: 3414 return PHY_TSSI_EXTRA_GROUP(2); 3415 case 52 ... 64: 3416 return 3; 3417 case 100 ... 112: 3418 return 4; 3419 case 113 ... 115: 3420 return PHY_TSSI_EXTRA_GROUP(4); 3421 case 116 ... 128: 3422 return 5; 3423 case 132 ... 144: 3424 return 6; 3425 case 149 ... 177: 3426 return 7; 3427 } 3428 3429 return 0; 3430 } 3431 3432 static u32 phy_tssi_get_6g_trim_group(u8 ch) 3433 { 3434 switch (ch) { 3435 case 1 ... 13: 3436 return 0; 3437 case 14 ... 16: 3438 return PHY_TSSI_EXTRA_GROUP(0); 3439 case 17 ... 29: 3440 return 1; 3441 case 33 ... 45: 3442 return 2; 3443 case 46 ... 48: 3444 return PHY_TSSI_EXTRA_GROUP(2); 3445 case 49 ... 61: 3446 return 3; 3447 case 65 ... 77: 3448 return 4; 3449 case 78 ... 80: 3450 return PHY_TSSI_EXTRA_GROUP(4); 3451 case 81 ... 93: 3452 return 5; 3453 case 97 ... 109: 3454 return 6; 3455 case 110 ... 112: 3456 return PHY_TSSI_EXTRA_GROUP(6); 3457 case 113 ... 125: 3458 return 7; 3459 case 129 ... 141: 3460 return 8; 3461 case 142 ... 144: 3462 return PHY_TSSI_EXTRA_GROUP(8); 3463 case 145 ... 157: 3464 return 9; 3465 case 161 ... 173: 3466 return 10; 3467 case 174 ... 176: 3468 return PHY_TSSI_EXTRA_GROUP(10); 3469 case 177 ... 189: 3470 return 11; 3471 case 193 ... 205: 3472 return 12; 3473 case 206 ... 208: 3474 return PHY_TSSI_EXTRA_GROUP(12); 3475 case 209 ... 221: 3476 return 13; 3477 case 225 ... 237: 3478 return 14; 3479 case 238 ... 240: 3480 return PHY_TSSI_EXTRA_GROUP(14); 3481 case 241 ... 253: 3482 return 15; 3483 } 3484 3485 return 0; 3486 } 3487 3488 static s8 phy_tssi_get_ofdm_de(struct rtw89_dev *rtwdev, 3489 enum rtw89_phy_idx phy, 3490 const struct rtw89_chan *chan, 3491 enum rtw89_rf_path path) 3492 { 3493 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3494 enum rtw89_band band = chan->band_type; 3495 u8 ch = chan->channel; 3496 u32 gidx_1st; 3497 u32 gidx_2nd; 3498 s8 de_1st; 3499 s8 de_2nd; 3500 u32 gidx; 3501 s8 val; 3502 3503 if (band == RTW89_BAND_6G) 3504 goto calc_6g; 3505 3506 gidx = phy_tssi_get_ofdm_group(ch); 3507 3508 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3509 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", 3510 path, gidx); 3511 3512 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) { 3513 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx); 3514 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx); 3515 de_1st = tssi_info->tssi_mcs[path][gidx_1st]; 3516 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd]; 3517 val = (de_1st + de_2nd) / 2; 3518 3519 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3520 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", 3521 path, val, de_1st, de_2nd); 3522 } else { 3523 val = tssi_info->tssi_mcs[path][gidx]; 3524 3525 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3526 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); 3527 } 3528 3529 return val; 3530 3531 calc_6g: 3532 gidx = phy_tssi_get_6g_ofdm_group(ch); 3533 3534 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3535 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", 3536 path, gidx); 3537 3538 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) { 3539 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx); 3540 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx); 3541 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st]; 3542 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd]; 3543 val = (de_1st + de_2nd) / 2; 3544 3545 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3546 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", 3547 path, val, de_1st, de_2nd); 3548 } else { 3549 val = tssi_info->tssi_6g_mcs[path][gidx]; 3550 3551 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3552 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); 3553 } 3554 3555 return val; 3556 } 3557 3558 static s8 phy_tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev, 3559 enum rtw89_phy_idx phy, 3560 const struct rtw89_chan *chan, 3561 enum rtw89_rf_path path) 3562 { 3563 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3564 enum rtw89_band band = chan->band_type; 3565 u8 ch = chan->channel; 3566 u32 tgidx_1st; 3567 u32 tgidx_2nd; 3568 s8 tde_1st; 3569 s8 tde_2nd; 3570 u32 tgidx; 3571 s8 val; 3572 3573 if (band == RTW89_BAND_6G) 3574 goto calc_6g; 3575 3576 tgidx = phy_tssi_get_trim_group(ch); 3577 3578 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3579 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", 3580 path, tgidx); 3581 3582 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) { 3583 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx); 3584 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx); 3585 tde_1st = tssi_info->tssi_trim[path][tgidx_1st]; 3586 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd]; 3587 val = (tde_1st + tde_2nd) / 2; 3588 3589 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3590 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", 3591 path, val, tde_1st, tde_2nd); 3592 } else { 3593 val = tssi_info->tssi_trim[path][tgidx]; 3594 3595 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3596 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", 3597 path, val); 3598 } 3599 3600 return val; 3601 3602 calc_6g: 3603 tgidx = phy_tssi_get_6g_trim_group(ch); 3604 3605 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3606 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", 3607 path, tgidx); 3608 3609 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) { 3610 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx); 3611 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx); 3612 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st]; 3613 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd]; 3614 val = (tde_1st + tde_2nd) / 2; 3615 3616 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3617 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", 3618 path, val, tde_1st, tde_2nd); 3619 } else { 3620 val = tssi_info->tssi_trim_6g[path][tgidx]; 3621 3622 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3623 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", 3624 path, val); 3625 } 3626 3627 return val; 3628 } 3629 3630 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, 3631 enum rtw89_phy_idx phy, 3632 const struct rtw89_chan *chan, 3633 struct rtw89_h2c_rf_tssi *h2c) 3634 { 3635 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3636 u8 ch = chan->channel; 3637 s8 trim_de; 3638 s8 ofdm_de; 3639 s8 cck_de; 3640 u8 gidx; 3641 s8 val; 3642 int i; 3643 3644 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n", 3645 phy, ch); 3646 3647 for (i = RF_PATH_A; i <= RF_PATH_B; i++) { 3648 trim_de = phy_tssi_get_ofdm_trim_de(rtwdev, phy, chan, i); 3649 h2c->curr_tssi_trim_de[i] = trim_de; 3650 3651 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3652 "[TSSI][TRIM]: path=%d trim_de=0x%x\n", i, trim_de); 3653 3654 gidx = phy_tssi_get_cck_group(ch); 3655 cck_de = tssi_info->tssi_cck[i][gidx]; 3656 val = u32_get_bits(cck_de + trim_de, 0xff); 3657 3658 h2c->curr_tssi_cck_de[i] = 0x0; 3659 h2c->curr_tssi_cck_de_20m[i] = val; 3660 h2c->curr_tssi_cck_de_40m[i] = val; 3661 h2c->curr_tssi_efuse_cck_de[i] = cck_de; 3662 3663 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3664 "[TSSI][TRIM]: path=%d cck_de=0x%x\n", i, cck_de); 3665 3666 ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i); 3667 val = u32_get_bits(ofdm_de + trim_de, 0xff); 3668 3669 h2c->curr_tssi_ofdm_de[i] = 0x0; 3670 h2c->curr_tssi_ofdm_de_20m[i] = val; 3671 h2c->curr_tssi_ofdm_de_40m[i] = val; 3672 h2c->curr_tssi_ofdm_de_80m[i] = val; 3673 h2c->curr_tssi_ofdm_de_160m[i] = val; 3674 h2c->curr_tssi_ofdm_de_320m[i] = val; 3675 h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de; 3676 3677 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3678 "[TSSI][TRIM]: path=%d ofdm_de=0x%x\n", i, ofdm_de); 3679 } 3680 } 3681 3682 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev, 3683 enum rtw89_phy_idx phy, 3684 const struct rtw89_chan *chan, 3685 struct rtw89_h2c_rf_tssi *h2c) 3686 { 3687 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk; 3688 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3689 const s8 *thm_up[RF_PATH_B + 1] = {}; 3690 const s8 *thm_down[RF_PATH_B + 1] = {}; 3691 u8 subband = chan->subband_type; 3692 s8 thm_ofst[128] = {0}; 3693 u8 thermal; 3694 u8 path; 3695 u8 i, j; 3696 3697 switch (subband) { 3698 default: 3699 case RTW89_CH_2G: 3700 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0]; 3701 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0]; 3702 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0]; 3703 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0]; 3704 break; 3705 case RTW89_CH_5G_BAND_1: 3706 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0]; 3707 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0]; 3708 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0]; 3709 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0]; 3710 break; 3711 case RTW89_CH_5G_BAND_3: 3712 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1]; 3713 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1]; 3714 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1]; 3715 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1]; 3716 break; 3717 case RTW89_CH_5G_BAND_4: 3718 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2]; 3719 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2]; 3720 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2]; 3721 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2]; 3722 break; 3723 case RTW89_CH_6G_BAND_IDX0: 3724 case RTW89_CH_6G_BAND_IDX1: 3725 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0]; 3726 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0]; 3727 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0]; 3728 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0]; 3729 break; 3730 case RTW89_CH_6G_BAND_IDX2: 3731 case RTW89_CH_6G_BAND_IDX3: 3732 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1]; 3733 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1]; 3734 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1]; 3735 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1]; 3736 break; 3737 case RTW89_CH_6G_BAND_IDX4: 3738 case RTW89_CH_6G_BAND_IDX5: 3739 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2]; 3740 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2]; 3741 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2]; 3742 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2]; 3743 break; 3744 case RTW89_CH_6G_BAND_IDX6: 3745 case RTW89_CH_6G_BAND_IDX7: 3746 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3]; 3747 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3]; 3748 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3]; 3749 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3]; 3750 break; 3751 } 3752 3753 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3754 "[TSSI] tmeter tbl on subband: %u\n", subband); 3755 3756 for (path = RF_PATH_A; path <= RF_PATH_B; path++) { 3757 thermal = tssi_info->thermal[path]; 3758 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3759 "path: %u, pg thermal: 0x%x\n", path, thermal); 3760 3761 if (thermal == 0xff) { 3762 h2c->pg_thermal[path] = 0x38; 3763 memset(h2c->ftable[path], 0, sizeof(h2c->ftable[path])); 3764 continue; 3765 } 3766 3767 h2c->pg_thermal[path] = thermal; 3768 3769 i = 0; 3770 for (j = 0; j < 64; j++) 3771 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 3772 thm_up[path][i++] : 3773 thm_up[path][DELTA_SWINGIDX_SIZE - 1]; 3774 3775 i = 1; 3776 for (j = 127; j >= 64; j--) 3777 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 3778 -thm_down[path][i++] : 3779 -thm_down[path][DELTA_SWINGIDX_SIZE - 1]; 3780 3781 for (i = 0; i < 128; i += 4) { 3782 h2c->ftable[path][i + 0] = thm_ofst[i + 3]; 3783 h2c->ftable[path][i + 1] = thm_ofst[i + 2]; 3784 h2c->ftable[path][i + 2] = thm_ofst[i + 1]; 3785 h2c->ftable[path][i + 3] = thm_ofst[i + 0]; 3786 3787 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3788 "thm ofst [%x]: %02x %02x %02x %02x\n", 3789 i, thm_ofst[i], thm_ofst[i + 1], 3790 thm_ofst[i + 2], thm_ofst[i + 3]); 3791 } 3792 } 3793 } 3794 3795 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 3796 { 3797 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 3798 u32 reg_mask; 3799 3800 if (sc_xo) 3801 reg_mask = xtal->sc_xo_mask; 3802 else 3803 reg_mask = xtal->sc_xi_mask; 3804 3805 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask); 3806 } 3807 3808 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 3809 u8 val) 3810 { 3811 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 3812 u32 reg_mask; 3813 3814 if (sc_xo) 3815 reg_mask = xtal->sc_xo_mask; 3816 else 3817 reg_mask = xtal->sc_xi_mask; 3818 3819 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val); 3820 } 3821 3822 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 3823 u8 crystal_cap, bool force) 3824 { 3825 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3826 const struct rtw89_chip_info *chip = rtwdev->chip; 3827 u8 sc_xi_val, sc_xo_val; 3828 3829 if (!force && cfo->crystal_cap == crystal_cap) 3830 return; 3831 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 3832 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) { 3833 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 3834 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 3835 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 3836 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 3837 } else { 3838 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 3839 crystal_cap, XTAL_SC_XO_MASK); 3840 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 3841 crystal_cap, XTAL_SC_XI_MASK); 3842 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 3843 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 3844 } 3845 cfo->crystal_cap = sc_xi_val; 3846 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 3847 3848 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 3849 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 3850 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 3851 cfo->x_cap_ofst); 3852 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 3853 } 3854 3855 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 3856 { 3857 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3858 u8 cap; 3859 3860 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 3861 cfo->is_adjust = false; 3862 if (cfo->crystal_cap == cfo->def_x_cap) 3863 return; 3864 cap = cfo->crystal_cap; 3865 cap += (cap > cfo->def_x_cap ? -1 : 1); 3866 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 3867 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3868 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 3869 cfo->def_x_cap); 3870 } 3871 3872 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 3873 { 3874 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 3875 bool is_linked = rtwdev->total_sta_assoc > 0; 3876 s32 cfo_avg_312; 3877 s32 dcfo_comp_val; 3878 int sign; 3879 3880 if (rtwdev->chip->chip_id == RTL8922A) 3881 return; 3882 3883 if (!is_linked) { 3884 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 3885 is_linked); 3886 return; 3887 } 3888 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 3889 if (curr_cfo == 0) 3890 return; 3891 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 3892 sign = curr_cfo > 0 ? 1 : -1; 3893 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val; 3894 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312); 3895 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 3896 cfo_avg_312 = -cfo_avg_312; 3897 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 3898 cfo_avg_312); 3899 } 3900 3901 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 3902 { 3903 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3904 const struct rtw89_chip_info *chip = rtwdev->chip; 3905 const struct rtw89_cfo_regs *cfo = phy->cfo; 3906 3907 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1); 3908 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8); 3909 3910 if (chip->chip_gen == RTW89_CHIP_AX) { 3911 if (chip->cfo_hw_comp) { 3912 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2, 3913 B_AX_PWR_UL_CFO_MASK, 0x6); 3914 } else { 3915 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 3916 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, 3917 B_AX_PWR_UL_CFO_MASK); 3918 } 3919 } 3920 } 3921 3922 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 3923 { 3924 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3925 struct rtw89_efuse *efuse = &rtwdev->efuse; 3926 3927 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 3928 cfo->crystal_cap = cfo->crystal_cap_default; 3929 cfo->def_x_cap = cfo->crystal_cap; 3930 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 3931 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 3932 cfo->is_adjust = false; 3933 cfo->divergence_lock_en = false; 3934 cfo->x_cap_ofst = 0; 3935 cfo->lock_cnt = 0; 3936 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 3937 cfo->apply_compensation = false; 3938 cfo->residual_cfo_acc = 0; 3939 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 3940 cfo->crystal_cap_default); 3941 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 3942 rtw89_dcfo_comp_init(rtwdev); 3943 cfo->cfo_timer_ms = 2000; 3944 cfo->cfo_trig_by_timer_en = false; 3945 cfo->phy_cfo_trk_cnt = 0; 3946 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 3947 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 3948 } 3949 3950 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 3951 s32 curr_cfo) 3952 { 3953 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3954 s8 crystal_cap = cfo->crystal_cap; 3955 s32 cfo_abs = abs(curr_cfo); 3956 int sign; 3957 3958 if (curr_cfo == 0) { 3959 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 3960 return; 3961 } 3962 if (!cfo->is_adjust) { 3963 if (cfo_abs > CFO_TRK_ENABLE_TH) 3964 cfo->is_adjust = true; 3965 } else { 3966 if (cfo_abs <= CFO_TRK_STOP_TH) 3967 cfo->is_adjust = false; 3968 } 3969 if (!cfo->is_adjust) { 3970 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 3971 return; 3972 } 3973 sign = curr_cfo > 0 ? 1 : -1; 3974 if (cfo_abs > CFO_TRK_STOP_TH_4) 3975 crystal_cap += 7 * sign; 3976 else if (cfo_abs > CFO_TRK_STOP_TH_3) 3977 crystal_cap += 5 * sign; 3978 else if (cfo_abs > CFO_TRK_STOP_TH_2) 3979 crystal_cap += 3 * sign; 3980 else if (cfo_abs > CFO_TRK_STOP_TH_1) 3981 crystal_cap += 1 * sign; 3982 else 3983 return; 3984 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 3985 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3986 "X_cap{Curr,Default}={0x%x,0x%x}\n", 3987 cfo->crystal_cap, cfo->def_x_cap); 3988 } 3989 3990 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 3991 { 3992 const struct rtw89_chip_info *chip = rtwdev->chip; 3993 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3994 s32 cfo_khz_all = 0; 3995 s32 cfo_cnt_all = 0; 3996 s32 cfo_all_avg = 0; 3997 u8 i; 3998 3999 if (rtwdev->total_sta_assoc != 1) 4000 return 0; 4001 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 4002 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4003 if (cfo->cfo_cnt[i] == 0) 4004 continue; 4005 cfo_khz_all += cfo->cfo_tail[i]; 4006 cfo_cnt_all += cfo->cfo_cnt[i]; 4007 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 4008 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 4009 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft, 4010 cfo_cnt_all); 4011 } 4012 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4013 "CFO track for macid = %d\n", i); 4014 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4015 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 4016 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 4017 return cfo_all_avg; 4018 } 4019 4020 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 4021 { 4022 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4023 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4024 s32 target_cfo = 0; 4025 s32 cfo_khz_all = 0; 4026 s32 cfo_khz_all_tp_wgt = 0; 4027 s32 cfo_avg = 0; 4028 s32 max_cfo_lb = BIT(31); 4029 s32 min_cfo_ub = GENMASK(30, 0); 4030 u16 cfo_cnt_all = 0; 4031 u8 active_entry_cnt = 0; 4032 u8 sta_cnt = 0; 4033 u32 tp_all = 0; 4034 u8 i; 4035 u8 cfo_tol = 0; 4036 4037 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 4038 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 4039 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 4040 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4041 if (cfo->cfo_cnt[i] == 0) 4042 continue; 4043 cfo_khz_all += cfo->cfo_tail[i]; 4044 cfo_cnt_all += cfo->cfo_cnt[i]; 4045 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 4046 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4047 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 4048 cfo_khz_all, cfo_cnt_all, cfo_avg); 4049 target_cfo = cfo_avg; 4050 } 4051 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 4052 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 4053 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4054 if (cfo->cfo_cnt[i] == 0) 4055 continue; 4056 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 4057 (s32)cfo->cfo_cnt[i]); 4058 cfo_khz_all += cfo->cfo_avg[i]; 4059 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4060 "Macid=%d, cfo_avg=%d\n", i, 4061 cfo->cfo_avg[i]); 4062 } 4063 sta_cnt = rtwdev->total_sta_assoc; 4064 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 4065 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4066 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 4067 cfo_khz_all, sta_cnt, cfo_avg); 4068 target_cfo = cfo_avg; 4069 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 4070 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 4071 cfo_tol = cfo->sta_cfo_tolerance; 4072 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4073 sta_cnt++; 4074 if (cfo->cfo_cnt[i] != 0) { 4075 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 4076 (s32)cfo->cfo_cnt[i]); 4077 active_entry_cnt++; 4078 } else { 4079 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 4080 } 4081 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 4082 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 4083 cfo_khz_all += cfo->cfo_avg[i]; 4084 /* need tp for each entry */ 4085 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4086 "[%d] cfo_avg=%d, tp=tbd\n", 4087 i, cfo->cfo_avg[i]); 4088 if (sta_cnt >= rtwdev->total_sta_assoc) 4089 break; 4090 } 4091 tp_all = stats->rx_throughput; /* need tp for each entry */ 4092 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 4093 4094 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 4095 sta_cnt); 4096 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 4097 active_entry_cnt); 4098 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4099 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 4100 cfo_khz_all_tp_wgt, cfo_avg); 4101 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 4102 max_cfo_lb, min_cfo_ub); 4103 if (max_cfo_lb <= min_cfo_ub) { 4104 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4105 "cfo win_size=%d\n", 4106 min_cfo_ub - max_cfo_lb); 4107 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 4108 } else { 4109 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4110 "No intersection of cfo tolerance windows\n"); 4111 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 4112 } 4113 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 4114 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 4115 } 4116 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 4117 return target_cfo; 4118 } 4119 4120 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 4121 { 4122 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4123 4124 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 4125 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 4126 cfo->packet_count = 0; 4127 cfo->packet_count_pre = 0; 4128 cfo->cfo_avg_pre = 0; 4129 } 4130 4131 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 4132 { 4133 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4134 s32 new_cfo = 0; 4135 bool x_cap_update = false; 4136 u8 pre_x_cap = cfo->crystal_cap; 4137 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 4138 4139 cfo->dcfo_avg = 0; 4140 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 4141 rtwdev->total_sta_assoc); 4142 if (rtwdev->total_sta_assoc == 0) { 4143 rtw89_phy_cfo_reset(rtwdev); 4144 return; 4145 } 4146 if (cfo->packet_count == 0) { 4147 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 4148 return; 4149 } 4150 if (cfo->packet_count == cfo->packet_count_pre) { 4151 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 4152 return; 4153 } 4154 if (rtwdev->total_sta_assoc == 1) 4155 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 4156 else 4157 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 4158 if (cfo->divergence_lock_en) { 4159 cfo->lock_cnt++; 4160 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 4161 cfo->divergence_lock_en = false; 4162 cfo->lock_cnt = 0; 4163 } else { 4164 rtw89_phy_cfo_reset(rtwdev); 4165 } 4166 return; 4167 } 4168 if (cfo->crystal_cap >= cfo->x_cap_ub || 4169 cfo->crystal_cap <= cfo->x_cap_lb) { 4170 cfo->divergence_lock_en = true; 4171 rtw89_phy_cfo_reset(rtwdev); 4172 return; 4173 } 4174 4175 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 4176 cfo->cfo_avg_pre = new_cfo; 4177 cfo->dcfo_avg_pre = cfo->dcfo_avg; 4178 x_cap_update = cfo->crystal_cap != pre_x_cap; 4179 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 4180 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 4181 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 4182 cfo->x_cap_ofst); 4183 if (x_cap_update) { 4184 if (cfo->dcfo_avg > 0) 4185 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 4186 else 4187 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 4188 } 4189 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg); 4190 rtw89_phy_cfo_statistics_reset(rtwdev); 4191 } 4192 4193 void rtw89_phy_cfo_track_work(struct work_struct *work) 4194 { 4195 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4196 cfo_track_work.work); 4197 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4198 4199 mutex_lock(&rtwdev->mutex); 4200 if (!cfo->cfo_trig_by_timer_en) 4201 goto out; 4202 rtw89_leave_ps_mode(rtwdev); 4203 rtw89_phy_cfo_dm(rtwdev); 4204 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 4205 msecs_to_jiffies(cfo->cfo_timer_ms)); 4206 out: 4207 mutex_unlock(&rtwdev->mutex); 4208 } 4209 4210 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 4211 { 4212 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4213 4214 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 4215 msecs_to_jiffies(cfo->cfo_timer_ms)); 4216 } 4217 4218 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 4219 { 4220 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4221 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4222 bool is_ul_ofdma = false, ofdma_acc_en = false; 4223 4224 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 4225 is_ul_ofdma = true; 4226 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 4227 is_ul_ofdma) 4228 ofdma_acc_en = true; 4229 4230 switch (cfo->phy_cfo_status) { 4231 case RTW89_PHY_DCFO_STATE_NORMAL: 4232 if (stats->tx_throughput >= CFO_TP_UPPER) { 4233 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 4234 cfo->cfo_trig_by_timer_en = true; 4235 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 4236 rtw89_phy_cfo_start_work(rtwdev); 4237 } 4238 break; 4239 case RTW89_PHY_DCFO_STATE_ENHANCE: 4240 if (stats->tx_throughput <= CFO_TP_LOWER) 4241 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4242 else if (ofdma_acc_en && 4243 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 4244 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 4245 else 4246 cfo->phy_cfo_trk_cnt++; 4247 4248 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 4249 cfo->phy_cfo_trk_cnt = 0; 4250 cfo->cfo_trig_by_timer_en = false; 4251 } 4252 break; 4253 case RTW89_PHY_DCFO_STATE_HOLD: 4254 if (stats->tx_throughput <= CFO_TP_LOWER) { 4255 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4256 cfo->phy_cfo_trk_cnt = 0; 4257 cfo->cfo_trig_by_timer_en = false; 4258 } else { 4259 cfo->phy_cfo_trk_cnt++; 4260 } 4261 break; 4262 default: 4263 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4264 cfo->phy_cfo_trk_cnt = 0; 4265 break; 4266 } 4267 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4268 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 4269 stats->tx_throughput, cfo->phy_cfo_status, 4270 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 4271 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 4272 if (cfo->cfo_trig_by_timer_en) 4273 return; 4274 rtw89_phy_cfo_dm(rtwdev); 4275 } 4276 4277 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 4278 struct rtw89_rx_phy_ppdu *phy_ppdu) 4279 { 4280 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4281 u8 macid = phy_ppdu->mac_id; 4282 4283 if (macid >= CFO_TRACK_MAX_USER) { 4284 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 4285 return; 4286 } 4287 4288 cfo->cfo_tail[macid] += cfo_val; 4289 cfo->cfo_cnt[macid]++; 4290 cfo->packet_count++; 4291 } 4292 4293 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4294 { 4295 const struct rtw89_chip_info *chip = rtwdev->chip; 4296 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4297 rtwvif->chanctx_idx); 4298 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4299 4300 if (!chip->ul_tb_waveform_ctrl) 4301 return; 4302 4303 rtwvif->def_tri_idx = 4304 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG); 4305 4306 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV) 4307 rtwvif->dyn_tb_bedge_en = false; 4308 else if (chan->band_type >= RTW89_BAND_5G && 4309 chan->band_width >= RTW89_CHANNEL_WIDTH_40) 4310 rtwvif->dyn_tb_bedge_en = true; 4311 else 4312 rtwvif->dyn_tb_bedge_en = false; 4313 4314 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4315 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n", 4316 ul_tb_info->def_if_bandedge, rtwvif->def_tri_idx); 4317 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4318 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n", 4319 rtwvif->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en); 4320 } 4321 4322 struct rtw89_phy_ul_tb_check_data { 4323 bool valid; 4324 bool high_tf_client; 4325 bool low_tf_client; 4326 bool dyn_tb_bedge_en; 4327 u8 def_tri_idx; 4328 }; 4329 4330 struct rtw89_phy_power_diff { 4331 u32 q_00; 4332 u32 q_11; 4333 u32 q_matrix_en; 4334 u32 ultb_1t_norm_160; 4335 u32 ultb_2t_norm_160; 4336 u32 com1_norm_1sts; 4337 u32 com2_resp_1sts_path; 4338 }; 4339 4340 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev, 4341 struct rtw89_vif *rtwvif) 4342 { 4343 static const struct rtw89_phy_power_diff table[2] = { 4344 {0x0, 0x0, 0x0, 0x0, 0xf4, 0x3, 0x3}, 4345 {0xb50, 0xb50, 0x1, 0xc, 0x0, 0x1, 0x1}, 4346 }; 4347 const struct rtw89_phy_power_diff *param; 4348 u32 reg; 4349 4350 if (!rtwdev->chip->ul_tb_pwr_diff) 4351 return; 4352 4353 if (rtwvif->pwr_diff_en == rtwvif->pre_pwr_diff_en) { 4354 rtwvif->pwr_diff_en = false; 4355 return; 4356 } 4357 4358 rtwvif->pre_pwr_diff_en = rtwvif->pwr_diff_en; 4359 param = &table[rtwvif->pwr_diff_en]; 4360 4361 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL, 4362 param->q_00); 4363 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL, 4364 param->q_11); 4365 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX, 4366 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en); 4367 4368 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif->mac_idx); 4369 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160, 4370 param->ultb_1t_norm_160); 4371 4372 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif->mac_idx); 4373 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160, 4374 param->ultb_2t_norm_160); 4375 4376 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif->mac_idx); 4377 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS, 4378 param->com1_norm_1sts); 4379 4380 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif->mac_idx); 4381 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH, 4382 param->com2_resp_1sts_path); 4383 } 4384 4385 static 4386 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev, 4387 struct rtw89_vif *rtwvif, 4388 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 4389 { 4390 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4391 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4392 4393 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4394 return; 4395 4396 if (!vif->cfg.assoc) 4397 return; 4398 4399 if (rtwdev->chip->ul_tb_waveform_ctrl) { 4400 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH) 4401 ul_tb_data->high_tf_client = true; 4402 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH) 4403 ul_tb_data->low_tf_client = true; 4404 4405 ul_tb_data->valid = true; 4406 ul_tb_data->def_tri_idx = rtwvif->def_tri_idx; 4407 ul_tb_data->dyn_tb_bedge_en = rtwvif->dyn_tb_bedge_en; 4408 } 4409 4410 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif); 4411 } 4412 4413 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev, 4414 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 4415 { 4416 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4417 4418 if (!rtwdev->chip->ul_tb_waveform_ctrl) 4419 return; 4420 4421 if (ul_tb_data->dyn_tb_bedge_en) { 4422 if (ul_tb_data->high_tf_client) { 4423 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0); 4424 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4425 "[ULTB] Turn off if_bandedge\n"); 4426 } else if (ul_tb_data->low_tf_client) { 4427 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 4428 ul_tb_info->def_if_bandedge); 4429 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4430 "[ULTB] Set to default if_bandedge = %d\n", 4431 ul_tb_info->def_if_bandedge); 4432 } 4433 } 4434 4435 if (ul_tb_info->dyn_tb_tri_en) { 4436 if (ul_tb_data->high_tf_client) { 4437 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 4438 B_TXSHAPE_TRIANGULAR_CFG, 0); 4439 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4440 "[ULTB] Turn off Tx triangle\n"); 4441 } else if (ul_tb_data->low_tf_client) { 4442 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 4443 B_TXSHAPE_TRIANGULAR_CFG, 4444 ul_tb_data->def_tri_idx); 4445 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4446 "[ULTB] Set to default tx_shap_idx = %d\n", 4447 ul_tb_data->def_tri_idx); 4448 } 4449 } 4450 } 4451 4452 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev) 4453 { 4454 const struct rtw89_chip_info *chip = rtwdev->chip; 4455 struct rtw89_phy_ul_tb_check_data ul_tb_data = {}; 4456 struct rtw89_vif *rtwvif; 4457 4458 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff) 4459 return; 4460 4461 if (rtwdev->total_sta_assoc != 1) 4462 return; 4463 4464 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4465 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data); 4466 4467 if (!ul_tb_data.valid) 4468 return; 4469 4470 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data); 4471 } 4472 4473 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev) 4474 { 4475 const struct rtw89_chip_info *chip = rtwdev->chip; 4476 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4477 4478 if (!chip->ul_tb_waveform_ctrl) 4479 return; 4480 4481 ul_tb_info->dyn_tb_tri_en = true; 4482 ul_tb_info->def_if_bandedge = 4483 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN); 4484 } 4485 4486 static 4487 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts) 4488 { 4489 ewma_rssi_init(&antdiv_sts->cck_rssi_avg); 4490 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg); 4491 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg); 4492 antdiv_sts->pkt_cnt_cck = 0; 4493 antdiv_sts->pkt_cnt_ofdm = 0; 4494 antdiv_sts->pkt_cnt_non_legacy = 0; 4495 antdiv_sts->evm = 0; 4496 } 4497 4498 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev, 4499 struct rtw89_rx_phy_ppdu *phy_ppdu, 4500 struct rtw89_antdiv_stats *stats) 4501 { 4502 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) { 4503 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) { 4504 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg); 4505 stats->pkt_cnt_cck++; 4506 } else { 4507 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg); 4508 stats->pkt_cnt_ofdm++; 4509 stats->evm += phy_ppdu->ofdm.evm_min; 4510 } 4511 } else { 4512 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg); 4513 stats->pkt_cnt_non_legacy++; 4514 stats->evm += phy_ppdu->ofdm.evm_min; 4515 } 4516 } 4517 4518 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats) 4519 { 4520 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck && 4521 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm) 4522 return ewma_rssi_read(&stats->non_legacy_rssi_avg); 4523 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck && 4524 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy) 4525 return ewma_rssi_read(&stats->ofdm_rssi_avg); 4526 else 4527 return ewma_rssi_read(&stats->cck_rssi_avg); 4528 } 4529 4530 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats) 4531 { 4532 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm); 4533 } 4534 4535 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 4536 struct rtw89_rx_phy_ppdu *phy_ppdu) 4537 { 4538 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4539 struct rtw89_hal *hal = &rtwdev->hal; 4540 4541 if (!hal->ant_diversity || hal->ant_diversity_fixed) 4542 return; 4543 4544 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats); 4545 4546 if (!antdiv->get_stats) 4547 return; 4548 4549 if (hal->antenna_rx == RF_A) 4550 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats); 4551 else if (hal->antenna_rx == RF_B) 4552 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats); 4553 } 4554 4555 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev) 4556 { 4557 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN, 4558 0x0, RTW89_PHY_0); 4559 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL, 4560 0x0, RTW89_PHY_0); 4561 4562 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND, 4563 0x0, RTW89_PHY_0); 4564 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT, 4565 0x0, RTW89_PHY_0); 4566 4567 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN, 4568 0x0, RTW89_PHY_0); 4569 4570 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING, 4571 0x0100, RTW89_PHY_0); 4572 4573 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX, 4574 0x1, RTW89_PHY_0); 4575 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL, 4576 0x0, RTW89_PHY_0); 4577 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G, 4578 0x0, RTW89_PHY_0); 4579 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G, 4580 0x0, RTW89_PHY_0); 4581 } 4582 4583 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev) 4584 { 4585 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4586 4587 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 4588 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats); 4589 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats); 4590 } 4591 4592 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev) 4593 { 4594 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4595 struct rtw89_hal *hal = &rtwdev->hal; 4596 4597 if (!hal->ant_diversity) 4598 return; 4599 4600 antdiv->get_stats = false; 4601 antdiv->rssi_pre = 0; 4602 rtw89_phy_antdiv_sts_reset(rtwdev); 4603 rtw89_phy_antdiv_reg_init(rtwdev); 4604 } 4605 4606 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 4607 { 4608 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 4609 int i; 4610 u8 th; 4611 4612 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 4613 th = rtw89_chip_get_thermal(rtwdev, i); 4614 if (th) 4615 ewma_thermal_add(&phystat->avg_thermal[i], th); 4616 4617 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 4618 "path(%d) thermal cur=%u avg=%ld", i, th, 4619 ewma_thermal_read(&phystat->avg_thermal[i])); 4620 } 4621 } 4622 4623 struct rtw89_phy_iter_rssi_data { 4624 struct rtw89_dev *rtwdev; 4625 struct rtw89_phy_ch_info *ch_info; 4626 bool rssi_changed; 4627 }; 4628 4629 static void rtw89_phy_stat_rssi_update_iter(void *data, 4630 struct ieee80211_sta *sta) 4631 { 4632 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 4633 struct rtw89_phy_iter_rssi_data *rssi_data = 4634 (struct rtw89_phy_iter_rssi_data *)data; 4635 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 4636 unsigned long rssi_curr; 4637 4638 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 4639 4640 if (rssi_curr < ch_info->rssi_min) { 4641 ch_info->rssi_min = rssi_curr; 4642 ch_info->rssi_min_macid = rtwsta->mac_id; 4643 } 4644 4645 if (rtwsta->prev_rssi == 0) { 4646 rtwsta->prev_rssi = rssi_curr; 4647 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 4648 rtwsta->prev_rssi = rssi_curr; 4649 rssi_data->rssi_changed = true; 4650 } 4651 } 4652 4653 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 4654 { 4655 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 4656 4657 rssi_data.rtwdev = rtwdev; 4658 rssi_data.ch_info = &rtwdev->ch_info; 4659 rssi_data.ch_info->rssi_min = U8_MAX; 4660 ieee80211_iterate_stations_atomic(rtwdev->hw, 4661 rtw89_phy_stat_rssi_update_iter, 4662 &rssi_data); 4663 if (rssi_data.rssi_changed) 4664 rtw89_btc_ntfy_wl_sta(rtwdev); 4665 } 4666 4667 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 4668 { 4669 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 4670 int i; 4671 4672 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 4673 ewma_thermal_init(&phystat->avg_thermal[i]); 4674 4675 rtw89_phy_stat_thermal_update(rtwdev); 4676 4677 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 4678 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 4679 } 4680 4681 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 4682 { 4683 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 4684 4685 rtw89_phy_stat_thermal_update(rtwdev); 4686 rtw89_phy_stat_rssi_update(rtwdev); 4687 4688 phystat->last_pkt_stat = phystat->cur_pkt_stat; 4689 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 4690 } 4691 4692 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 4693 { 4694 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4695 4696 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 4697 } 4698 4699 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 4700 { 4701 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4702 4703 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 4704 } 4705 4706 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 4707 { 4708 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4709 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4710 const struct rtw89_ccx_regs *ccx = phy->ccx; 4711 4712 env->ccx_manual_ctrl = false; 4713 env->ccx_ongoing = false; 4714 env->ccx_rac_lv = RTW89_RAC_RELEASE; 4715 env->ccx_period = 0; 4716 env->ccx_unit_idx = RTW89_CCX_32_US; 4717 4718 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->en_mask, 1); 4719 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1); 4720 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1); 4721 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask, 4722 RTW89_CCX_EDCCA_BW20_0); 4723 } 4724 4725 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 4726 u16 score) 4727 { 4728 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4729 u32 numer = 0; 4730 u16 ret = 0; 4731 4732 numer = report * score + (env->ccx_period >> 1); 4733 if (env->ccx_period) 4734 ret = numer / env->ccx_period; 4735 4736 return ret >= score ? score - 1 : ret; 4737 } 4738 4739 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 4740 u16 time_ms, u32 *period, 4741 u32 *unit_idx) 4742 { 4743 u32 idx; 4744 u8 quotient; 4745 4746 if (time_ms >= CCX_MAX_PERIOD) 4747 time_ms = CCX_MAX_PERIOD; 4748 4749 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 4750 4751 if (quotient < 4) 4752 idx = RTW89_CCX_4_US; 4753 else if (quotient < 8) 4754 idx = RTW89_CCX_8_US; 4755 else if (quotient < 16) 4756 idx = RTW89_CCX_16_US; 4757 else 4758 idx = RTW89_CCX_32_US; 4759 4760 *unit_idx = idx; 4761 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 4762 4763 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4764 "[Trigger Time] period:%d, unit_idx:%d\n", 4765 *period, *unit_idx); 4766 } 4767 4768 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 4769 { 4770 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4771 4772 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4773 "lv:(%d)->(0)\n", env->ccx_rac_lv); 4774 4775 env->ccx_ongoing = false; 4776 env->ccx_rac_lv = RTW89_RAC_RELEASE; 4777 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 4778 } 4779 4780 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 4781 struct rtw89_ccx_para_info *para) 4782 { 4783 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4784 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 4785 u8 i = 0; 4786 u16 *ifs_th_l = env->ifs_clm_th_l; 4787 u16 *ifs_th_h = env->ifs_clm_th_h; 4788 u32 ifs_th0_us = 0, ifs_th_times = 0; 4789 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 4790 4791 if (!is_update) 4792 goto ifs_update_finished; 4793 4794 switch (para->ifs_clm_app) { 4795 case RTW89_IFS_CLM_INIT: 4796 case RTW89_IFS_CLM_BACKGROUND: 4797 case RTW89_IFS_CLM_ACS: 4798 case RTW89_IFS_CLM_DBG: 4799 case RTW89_IFS_CLM_DIG: 4800 case RTW89_IFS_CLM_TDMA_DIG: 4801 ifs_th0_us = IFS_CLM_TH0_UPPER; 4802 ifs_th_times = IFS_CLM_TH_MUL; 4803 break; 4804 case RTW89_IFS_CLM_DBG_MANUAL: 4805 ifs_th0_us = para->ifs_clm_manual_th0; 4806 ifs_th_times = para->ifs_clm_manual_th_times; 4807 break; 4808 default: 4809 break; 4810 } 4811 4812 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 4813 * low[i] = high[i-1] + 1 4814 * high[i] = high[i-1] * ifs_th_times 4815 */ 4816 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 4817 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 4818 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 4819 ifs_th0_us); 4820 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 4821 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 4822 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 4823 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 4824 } 4825 4826 ifs_update_finished: 4827 if (!is_update) 4828 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4829 "No need to update IFS_TH\n"); 4830 4831 return is_update; 4832 } 4833 4834 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 4835 { 4836 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4837 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4838 const struct rtw89_ccx_regs *ccx = phy->ccx; 4839 u8 i = 0; 4840 4841 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask, 4842 env->ifs_clm_th_l[0]); 4843 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask, 4844 env->ifs_clm_th_l[1]); 4845 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask, 4846 env->ifs_clm_th_l[2]); 4847 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask, 4848 env->ifs_clm_th_l[3]); 4849 4850 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask, 4851 env->ifs_clm_th_h[0]); 4852 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask, 4853 env->ifs_clm_th_h[1]); 4854 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask, 4855 env->ifs_clm_th_h[2]); 4856 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask, 4857 env->ifs_clm_th_h[3]); 4858 4859 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 4860 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4861 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 4862 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 4863 } 4864 4865 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 4866 { 4867 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4868 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4869 const struct rtw89_ccx_regs *ccx = phy->ccx; 4870 struct rtw89_ccx_para_info para = {0}; 4871 4872 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 4873 env->ifs_clm_mntr_time = 0; 4874 4875 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 4876 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 4877 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 4878 4879 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true); 4880 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true); 4881 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true); 4882 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true); 4883 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true); 4884 } 4885 4886 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 4887 enum rtw89_env_racing_lv level) 4888 { 4889 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4890 int ret = 0; 4891 4892 if (level >= RTW89_RAC_MAX_NUM) { 4893 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4894 "[WARNING] Wrong LV=%d\n", level); 4895 return -EINVAL; 4896 } 4897 4898 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4899 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 4900 env->ccx_rac_lv, level); 4901 4902 if (env->ccx_ongoing) { 4903 if (level <= env->ccx_rac_lv) 4904 ret = -EINVAL; 4905 else 4906 env->ccx_ongoing = false; 4907 } 4908 4909 if (ret == 0) 4910 env->ccx_rac_lv = level; 4911 4912 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 4913 !ret); 4914 4915 return ret; 4916 } 4917 4918 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 4919 { 4920 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4921 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4922 const struct rtw89_ccx_regs *ccx = phy->ccx; 4923 4924 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0); 4925 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0); 4926 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1); 4927 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1); 4928 4929 env->ccx_ongoing = true; 4930 } 4931 4932 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 4933 { 4934 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4935 u8 i = 0; 4936 u32 res = 0; 4937 4938 env->ifs_clm_tx_ratio = 4939 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 4940 env->ifs_clm_edcca_excl_cca_ratio = 4941 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 4942 PERCENT); 4943 env->ifs_clm_cck_fa_ratio = 4944 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 4945 env->ifs_clm_ofdm_fa_ratio = 4946 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 4947 env->ifs_clm_cck_cca_excl_fa_ratio = 4948 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 4949 PERCENT); 4950 env->ifs_clm_ofdm_cca_excl_fa_ratio = 4951 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 4952 PERCENT); 4953 env->ifs_clm_cck_fa_permil = 4954 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 4955 env->ifs_clm_ofdm_fa_permil = 4956 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 4957 4958 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 4959 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 4960 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 4961 } else { 4962 env->ifs_clm_ifs_avg[i] = 4963 rtw89_phy_ccx_idx_to_us(rtwdev, 4964 env->ifs_clm_avg[i]); 4965 } 4966 4967 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 4968 res += env->ifs_clm_his[i] >> 1; 4969 if (env->ifs_clm_his[i]) 4970 res /= env->ifs_clm_his[i]; 4971 else 4972 res = 0; 4973 env->ifs_clm_cca_avg[i] = res; 4974 } 4975 4976 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4977 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 4978 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 4979 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4980 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 4981 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 4982 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4983 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 4984 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 4985 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4986 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 4987 env->ifs_clm_cck_cca_excl_fa_ratio, 4988 env->ifs_clm_ofdm_cca_excl_fa_ratio); 4989 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4990 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 4991 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 4992 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 4993 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 4994 env->ifs_clm_cca_avg[i]); 4995 } 4996 4997 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 4998 { 4999 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5000 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 5001 const struct rtw89_ccx_regs *ccx = phy->ccx; 5002 u8 i = 0; 5003 5004 if (rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr, 5005 ccx->ifs_cnt_done_mask) == 0) { 5006 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5007 "Get IFS_CLM report Fail\n"); 5008 return false; 5009 } 5010 5011 env->ifs_clm_tx = 5012 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr, 5013 ccx->ifs_clm_tx_cnt_msk); 5014 env->ifs_clm_edcca_excl_cca = 5015 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr, 5016 ccx->ifs_clm_edcca_excl_cca_fa_mask); 5017 env->ifs_clm_cckcca_excl_fa = 5018 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr, 5019 ccx->ifs_clm_cckcca_excl_fa_mask); 5020 env->ifs_clm_ofdmcca_excl_fa = 5021 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr, 5022 ccx->ifs_clm_ofdmcca_excl_fa_mask); 5023 env->ifs_clm_cckfa = 5024 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr, 5025 ccx->ifs_clm_cck_fa_mask); 5026 env->ifs_clm_ofdmfa = 5027 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr, 5028 ccx->ifs_clm_ofdm_fa_mask); 5029 5030 env->ifs_clm_his[0] = 5031 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 5032 ccx->ifs_t1_his_mask); 5033 env->ifs_clm_his[1] = 5034 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 5035 ccx->ifs_t2_his_mask); 5036 env->ifs_clm_his[2] = 5037 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 5038 ccx->ifs_t3_his_mask); 5039 env->ifs_clm_his[3] = 5040 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 5041 ccx->ifs_t4_his_mask); 5042 5043 env->ifs_clm_avg[0] = 5044 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr, 5045 ccx->ifs_t1_avg_mask); 5046 env->ifs_clm_avg[1] = 5047 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr, 5048 ccx->ifs_t2_avg_mask); 5049 env->ifs_clm_avg[2] = 5050 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr, 5051 ccx->ifs_t3_avg_mask); 5052 env->ifs_clm_avg[3] = 5053 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr, 5054 ccx->ifs_t4_avg_mask); 5055 5056 env->ifs_clm_cca[0] = 5057 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr, 5058 ccx->ifs_t1_cca_mask); 5059 env->ifs_clm_cca[1] = 5060 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr, 5061 ccx->ifs_t2_cca_mask); 5062 env->ifs_clm_cca[2] = 5063 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr, 5064 ccx->ifs_t3_cca_mask); 5065 env->ifs_clm_cca[3] = 5066 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr, 5067 ccx->ifs_t4_cca_mask); 5068 5069 env->ifs_clm_total_ifs = 5070 rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr, 5071 ccx->ifs_total_mask); 5072 5073 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 5074 env->ifs_clm_total_ifs); 5075 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5076 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 5077 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 5078 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5079 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 5080 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 5081 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5082 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 5083 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 5084 5085 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 5086 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 5087 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5088 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 5089 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 5090 5091 rtw89_phy_ifs_clm_get_utility(rtwdev); 5092 5093 return true; 5094 } 5095 5096 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 5097 struct rtw89_ccx_para_info *para) 5098 { 5099 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5100 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 5101 const struct rtw89_ccx_regs *ccx = phy->ccx; 5102 u32 period = 0; 5103 u32 unit_idx = 0; 5104 5105 if (para->mntr_time == 0) { 5106 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5107 "[WARN] MNTR_TIME is 0\n"); 5108 return -EINVAL; 5109 } 5110 5111 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 5112 return -EINVAL; 5113 5114 if (para->mntr_time != env->ifs_clm_mntr_time) { 5115 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 5116 &period, &unit_idx); 5117 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, 5118 ccx->ifs_clm_period_mask, period); 5119 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, 5120 ccx->ifs_clm_cnt_unit_mask, 5121 unit_idx); 5122 5123 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5124 "Update IFS-CLM time ((%d)) -> ((%d))\n", 5125 env->ifs_clm_mntr_time, para->mntr_time); 5126 5127 env->ifs_clm_mntr_time = para->mntr_time; 5128 env->ccx_period = (u16)period; 5129 env->ccx_unit_idx = (u8)unit_idx; 5130 } 5131 5132 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 5133 env->ifs_clm_app = para->ifs_clm_app; 5134 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 5135 } 5136 5137 return 0; 5138 } 5139 5140 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 5141 { 5142 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 5143 struct rtw89_ccx_para_info para = {0}; 5144 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 5145 5146 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 5147 if (env->ccx_manual_ctrl) { 5148 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5149 "CCX in manual ctrl\n"); 5150 return; 5151 } 5152 5153 /* only ifs_clm for now */ 5154 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 5155 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 5156 5157 rtw89_phy_ccx_racing_release(rtwdev); 5158 para.mntr_time = 1900; 5159 para.rac_lv = RTW89_RAC_LV_1; 5160 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 5161 5162 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 5163 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 5164 if (chk_result) 5165 rtw89_phy_ccx_trigger(rtwdev); 5166 5167 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5168 "get_result=0x%x, chk_result:0x%x\n", 5169 env->ccx_watchdog_result, chk_result); 5170 } 5171 5172 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 5173 { 5174 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM || 5175 *ie_page == RTW89_RSVD_9) 5176 return false; 5177 else if (*ie_page > RTW89_RSVD_9) 5178 *ie_page -= 1; 5179 5180 return true; 5181 } 5182 5183 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 5184 { 5185 static const u8 ie_page_shift = 2; 5186 5187 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 5188 } 5189 5190 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 5191 enum rtw89_phy_status_bitmap ie_page) 5192 { 5193 u32 addr; 5194 5195 if (!rtw89_physts_ie_page_valid(&ie_page)) 5196 return 0; 5197 5198 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 5199 5200 return rtw89_phy_read32(rtwdev, addr); 5201 } 5202 5203 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 5204 enum rtw89_phy_status_bitmap ie_page, 5205 u32 val) 5206 { 5207 const struct rtw89_chip_info *chip = rtwdev->chip; 5208 u32 addr; 5209 5210 if (!rtw89_physts_ie_page_valid(&ie_page)) 5211 return; 5212 5213 if (chip->chip_id == RTL8852A) 5214 val &= B_PHY_STS_BITMAP_MSK_52A; 5215 5216 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 5217 rtw89_phy_write32(rtwdev, addr, val); 5218 } 5219 5220 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 5221 enum rtw89_phy_status_bitmap bitmap, 5222 enum rtw89_phy_status_ie_type ie, 5223 bool enable) 5224 { 5225 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 5226 5227 if (enable) 5228 val |= BIT(ie); 5229 else 5230 val &= ~BIT(ie); 5231 5232 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 5233 } 5234 5235 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 5236 bool enable, 5237 enum rtw89_phy_idx phy_idx) 5238 { 5239 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5240 const struct rtw89_physts_regs *physts = phy->physts; 5241 5242 if (enable) { 5243 rtw89_phy_write32_clr(rtwdev, physts->setting_addr, 5244 physts->dis_trigger_fail_mask); 5245 rtw89_phy_write32_clr(rtwdev, physts->setting_addr, 5246 physts->dis_trigger_brk_mask); 5247 } else { 5248 rtw89_phy_write32_set(rtwdev, physts->setting_addr, 5249 physts->dis_trigger_fail_mask); 5250 rtw89_phy_write32_set(rtwdev, physts->setting_addr, 5251 physts->dis_trigger_brk_mask); 5252 } 5253 } 5254 5255 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 5256 { 5257 u8 i; 5258 5259 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 5260 5261 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 5262 if (i >= RTW89_CCK_PKT) 5263 rtw89_physts_enable_ie_bitmap(rtwdev, i, 5264 RTW89_PHYSTS_IE09_FTR_0, 5265 true); 5266 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 5267 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 5268 continue; 5269 rtw89_physts_enable_ie_bitmap(rtwdev, i, 5270 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 5271 true); 5272 } 5273 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 5274 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 5275 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 5276 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 5277 5278 /* force IE01 for channel index, only channel field is valid */ 5279 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 5280 RTW89_PHYSTS_IE01_CMN_OFDM, true); 5281 } 5282 5283 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 5284 { 5285 const struct rtw89_chip_info *chip = rtwdev->chip; 5286 struct rtw89_dig_info *dig = &rtwdev->dig; 5287 const struct rtw89_phy_dig_gain_cfg *cfg; 5288 const char *msg; 5289 u8 i; 5290 s8 gain_base; 5291 s8 *gain_arr; 5292 u32 tmp; 5293 5294 switch (type) { 5295 case RTW89_DIG_GAIN_LNA_G: 5296 gain_arr = dig->lna_gain_g; 5297 gain_base = LNA0_GAIN; 5298 cfg = chip->dig_table->cfg_lna_g; 5299 msg = "lna_gain_g"; 5300 break; 5301 case RTW89_DIG_GAIN_TIA_G: 5302 gain_arr = dig->tia_gain_g; 5303 gain_base = TIA0_GAIN_G; 5304 cfg = chip->dig_table->cfg_tia_g; 5305 msg = "tia_gain_g"; 5306 break; 5307 case RTW89_DIG_GAIN_LNA_A: 5308 gain_arr = dig->lna_gain_a; 5309 gain_base = LNA0_GAIN; 5310 cfg = chip->dig_table->cfg_lna_a; 5311 msg = "lna_gain_a"; 5312 break; 5313 case RTW89_DIG_GAIN_TIA_A: 5314 gain_arr = dig->tia_gain_a; 5315 gain_base = TIA0_GAIN_A; 5316 cfg = chip->dig_table->cfg_tia_a; 5317 msg = "tia_gain_a"; 5318 break; 5319 default: 5320 return; 5321 } 5322 5323 for (i = 0; i < cfg->size; i++) { 5324 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 5325 cfg->table[i].mask); 5326 tmp >>= DIG_GAIN_SHIFT; 5327 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 5328 gain_base += DIG_GAIN; 5329 5330 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 5331 msg, i, gain_arr[i]); 5332 } 5333 } 5334 5335 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 5336 { 5337 struct rtw89_dig_info *dig = &rtwdev->dig; 5338 u32 tmp; 5339 u8 i; 5340 5341 if (!rtwdev->hal.support_igi) 5342 return; 5343 5344 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 5345 B_PATH0_IB_PKPW_MSK); 5346 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 5347 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 5348 B_PATH0_IB_PBK_MSK); 5349 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 5350 dig->ib_pkpwr, dig->ib_pbk); 5351 5352 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 5353 rtw89_phy_dig_read_gain_table(rtwdev, i); 5354 } 5355 5356 static const u8 rssi_nolink = 22; 5357 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 5358 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 5359 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 5360 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 5361 5362 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 5363 { 5364 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 5365 struct rtw89_dig_info *dig = &rtwdev->dig; 5366 bool is_linked = rtwdev->total_sta_assoc > 0; 5367 5368 if (is_linked) { 5369 dig->igi_rssi = ch_info->rssi_min >> 1; 5370 } else { 5371 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 5372 dig->igi_rssi = rssi_nolink; 5373 } 5374 } 5375 5376 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 5377 { 5378 struct rtw89_dig_info *dig = &rtwdev->dig; 5379 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 5380 bool is_linked = rtwdev->total_sta_assoc > 0; 5381 const u16 *fa_th_src = NULL; 5382 5383 switch (chan->band_type) { 5384 case RTW89_BAND_2G: 5385 dig->lna_gain = dig->lna_gain_g; 5386 dig->tia_gain = dig->tia_gain_g; 5387 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 5388 dig->force_gaincode_idx_en = false; 5389 dig->dyn_pd_th_en = true; 5390 break; 5391 case RTW89_BAND_5G: 5392 default: 5393 dig->lna_gain = dig->lna_gain_a; 5394 dig->tia_gain = dig->tia_gain_a; 5395 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 5396 dig->force_gaincode_idx_en = true; 5397 dig->dyn_pd_th_en = true; 5398 break; 5399 } 5400 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 5401 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 5402 } 5403 5404 static const u8 pd_low_th_offset = 16, dynamic_igi_min = 0x20; 5405 static const u8 igi_max_performance_mode = 0x5a; 5406 static const u8 dynamic_pd_threshold_max; 5407 5408 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 5409 { 5410 struct rtw89_dig_info *dig = &rtwdev->dig; 5411 5412 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 5413 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 5414 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 5415 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 5416 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 5417 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 5418 5419 dig->dyn_igi_max = igi_max_performance_mode; 5420 dig->dyn_igi_min = dynamic_igi_min; 5421 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 5422 dig->pd_low_th_ofst = pd_low_th_offset; 5423 dig->is_linked_pre = false; 5424 } 5425 5426 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 5427 { 5428 rtw89_phy_dig_update_gain_para(rtwdev); 5429 rtw89_phy_dig_reset(rtwdev); 5430 } 5431 5432 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 5433 { 5434 struct rtw89_dig_info *dig = &rtwdev->dig; 5435 u8 lna_idx; 5436 5437 if (rssi < dig->igi_rssi_th[0]) 5438 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 5439 else if (rssi < dig->igi_rssi_th[1]) 5440 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 5441 else if (rssi < dig->igi_rssi_th[2]) 5442 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 5443 else if (rssi < dig->igi_rssi_th[3]) 5444 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 5445 else if (rssi < dig->igi_rssi_th[4]) 5446 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 5447 else 5448 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 5449 5450 return lna_idx; 5451 } 5452 5453 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 5454 { 5455 struct rtw89_dig_info *dig = &rtwdev->dig; 5456 u8 tia_idx; 5457 5458 if (rssi < dig->igi_rssi_th[0]) 5459 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 5460 else 5461 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 5462 5463 return tia_idx; 5464 } 5465 5466 #define IB_PBK_BASE 110 5467 #define WB_RSSI_BASE 10 5468 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 5469 struct rtw89_agc_gaincode_set *set) 5470 { 5471 struct rtw89_dig_info *dig = &rtwdev->dig; 5472 s8 lna_gain = dig->lna_gain[set->lna_idx]; 5473 s8 tia_gain = dig->tia_gain[set->tia_idx]; 5474 s32 wb_rssi = rssi + lna_gain + tia_gain; 5475 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 5476 u8 rxb_idx; 5477 5478 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 5479 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 5480 5481 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 5482 wb_rssi, rxb_idx_tmp); 5483 5484 return rxb_idx; 5485 } 5486 5487 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 5488 struct rtw89_agc_gaincode_set *set) 5489 { 5490 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 5491 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 5492 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 5493 5494 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5495 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 5496 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 5497 } 5498 5499 #define IGI_OFFSET_MAX 25 5500 #define IGI_OFFSET_MUL 2 5501 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 5502 { 5503 struct rtw89_dig_info *dig = &rtwdev->dig; 5504 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 5505 enum rtw89_dig_noisy_level noisy_lv; 5506 u8 igi_offset = dig->fa_rssi_ofst; 5507 u16 fa_ratio = 0; 5508 5509 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 5510 5511 if (fa_ratio < dig->fa_th[0]) 5512 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 5513 else if (fa_ratio < dig->fa_th[1]) 5514 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 5515 else if (fa_ratio < dig->fa_th[2]) 5516 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 5517 else if (fa_ratio < dig->fa_th[3]) 5518 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 5519 else 5520 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 5521 5522 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 5523 igi_offset = 0; 5524 else 5525 igi_offset += noisy_lv * IGI_OFFSET_MUL; 5526 5527 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 5528 dig->fa_rssi_ofst = igi_offset; 5529 5530 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5531 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 5532 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 5533 5534 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5535 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 5536 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 5537 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 5538 noisy_lv, igi_offset); 5539 } 5540 5541 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 5542 { 5543 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5544 5545 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr, 5546 dig_regs->p0_lna_init.mask, lna_idx); 5547 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr, 5548 dig_regs->p1_lna_init.mask, lna_idx); 5549 } 5550 5551 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 5552 { 5553 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5554 5555 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr, 5556 dig_regs->p0_tia_init.mask, tia_idx); 5557 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr, 5558 dig_regs->p1_tia_init.mask, tia_idx); 5559 } 5560 5561 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 5562 { 5563 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5564 5565 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr, 5566 dig_regs->p0_rxb_init.mask, rxb_idx); 5567 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr, 5568 dig_regs->p1_rxb_init.mask, rxb_idx); 5569 } 5570 5571 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 5572 const struct rtw89_agc_gaincode_set set) 5573 { 5574 if (!rtwdev->hal.support_igi) 5575 return; 5576 5577 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 5578 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 5579 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 5580 5581 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 5582 set.lna_idx, set.tia_idx, set.rxb_idx); 5583 } 5584 5585 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 5586 bool enable) 5587 { 5588 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5589 5590 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 5591 dig_regs->p0_p20_pagcugc_en.mask, enable); 5592 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 5593 dig_regs->p0_s20_pagcugc_en.mask, enable); 5594 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 5595 dig_regs->p1_p20_pagcugc_en.mask, enable); 5596 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 5597 dig_regs->p1_s20_pagcugc_en.mask, enable); 5598 5599 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 5600 } 5601 5602 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 5603 { 5604 struct rtw89_dig_info *dig = &rtwdev->dig; 5605 5606 if (!rtwdev->hal.support_igi) 5607 return; 5608 5609 if (dig->force_gaincode_idx_en) { 5610 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 5611 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5612 "Force gaincode index enabled.\n"); 5613 } else { 5614 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 5615 &dig->cur_gaincode); 5616 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 5617 } 5618 } 5619 5620 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 5621 bool enable) 5622 { 5623 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 5624 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5625 enum rtw89_bandwidth cbw = chan->band_width; 5626 struct rtw89_dig_info *dig = &rtwdev->dig; 5627 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 5628 u8 ofdm_cca_th; 5629 s8 cck_cca_th; 5630 u32 pd_val = 0; 5631 5632 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX) 5633 under_region += PD_TH_SB_FLTR_CMP_VAL; 5634 5635 switch (cbw) { 5636 case RTW89_CHANNEL_WIDTH_40: 5637 under_region += PD_TH_BW40_CMP_VAL; 5638 break; 5639 case RTW89_CHANNEL_WIDTH_80: 5640 under_region += PD_TH_BW80_CMP_VAL; 5641 break; 5642 case RTW89_CHANNEL_WIDTH_160: 5643 under_region += PD_TH_BW160_CMP_VAL; 5644 break; 5645 case RTW89_CHANNEL_WIDTH_20: 5646 fallthrough; 5647 default: 5648 under_region += PD_TH_BW20_CMP_VAL; 5649 break; 5650 } 5651 5652 dig->dyn_pd_th_max = dig->igi_rssi; 5653 5654 final_rssi = min_t(u8, rssi, dig->igi_rssi); 5655 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 5656 PD_TH_MAX_RSSI + under_region); 5657 5658 if (enable) { 5659 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 5660 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5661 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 5662 final_rssi, ofdm_cca_th, under_region, pd_val); 5663 } else { 5664 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5665 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 5666 } 5667 5668 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 5669 dig_regs->pd_lower_bound_mask, pd_val); 5670 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 5671 dig_regs->pd_spatial_reuse_en, enable); 5672 5673 if (!rtwdev->hal.support_cckpd) 5674 return; 5675 5676 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 5677 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 5678 5679 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5680 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 5681 final_rssi, cck_cca_th, under_region, pd_val); 5682 5683 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_reg, 5684 dig_regs->bmode_cca_rssi_limit_en, enable); 5685 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_lower_bound_reg, 5686 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val); 5687 } 5688 5689 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 5690 { 5691 struct rtw89_dig_info *dig = &rtwdev->dig; 5692 5693 dig->bypass_dig = false; 5694 rtw89_phy_dig_para_reset(rtwdev); 5695 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 5696 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 5697 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 5698 rtw89_phy_dig_update_para(rtwdev); 5699 } 5700 5701 #define IGI_RSSI_MIN 10 5702 #define ABS_IGI_MIN 0xc 5703 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 5704 { 5705 struct rtw89_dig_info *dig = &rtwdev->dig; 5706 bool is_linked = rtwdev->total_sta_assoc > 0; 5707 u8 igi_min; 5708 5709 if (unlikely(dig->bypass_dig)) { 5710 dig->bypass_dig = false; 5711 return; 5712 } 5713 5714 rtw89_phy_dig_update_rssi_info(rtwdev); 5715 5716 if (!dig->is_linked_pre && is_linked) { 5717 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 5718 rtw89_phy_dig_update_para(rtwdev); 5719 dig->igi_fa_rssi = dig->igi_rssi; 5720 } else if (dig->is_linked_pre && !is_linked) { 5721 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 5722 rtw89_phy_dig_update_para(rtwdev); 5723 dig->igi_fa_rssi = dig->igi_rssi; 5724 } 5725 dig->is_linked_pre = is_linked; 5726 5727 rtw89_phy_dig_igi_offset_by_env(rtwdev); 5728 5729 igi_min = max_t(int, dig->igi_rssi - IGI_RSSI_MIN, 0); 5730 dig->dyn_igi_max = min(igi_min + IGI_OFFSET_MAX, igi_max_performance_mode); 5731 dig->dyn_igi_min = max(igi_min, ABS_IGI_MIN); 5732 5733 if (dig->dyn_igi_max >= dig->dyn_igi_min) { 5734 dig->igi_fa_rssi += dig->fa_rssi_ofst; 5735 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 5736 dig->dyn_igi_max); 5737 } else { 5738 dig->igi_fa_rssi = dig->dyn_igi_max; 5739 } 5740 5741 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5742 "rssi=%03d, dyn_joint(max,min)=(%d,%d), final_rssi=%d\n", 5743 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 5744 dig->igi_fa_rssi); 5745 5746 rtw89_phy_dig_config_igi(rtwdev); 5747 5748 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 5749 5750 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 5751 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 5752 else 5753 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 5754 } 5755 5756 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 5757 { 5758 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 5759 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 5760 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5761 struct rtw89_hal *hal = &rtwdev->hal; 5762 bool *done = data; 5763 u8 rssi_a, rssi_b; 5764 u32 candidate; 5765 5766 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || sta->tdls) 5767 return; 5768 5769 if (*done) 5770 return; 5771 5772 *done = true; 5773 5774 rssi_a = ewma_rssi_read(&rtwsta->rssi[RF_PATH_A]); 5775 rssi_b = ewma_rssi_read(&rtwsta->rssi[RF_PATH_B]); 5776 5777 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 5778 candidate = RF_A; 5779 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 5780 candidate = RF_B; 5781 else 5782 return; 5783 5784 if (hal->antenna_tx == candidate) 5785 return; 5786 5787 hal->antenna_tx = candidate; 5788 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta); 5789 5790 if (hal->antenna_tx == RF_A) { 5791 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 5792 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 5793 } else if (hal->antenna_tx == RF_B) { 5794 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 5795 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 5796 } 5797 } 5798 5799 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 5800 { 5801 struct rtw89_hal *hal = &rtwdev->hal; 5802 bool done = false; 5803 5804 if (!hal->tx_path_diversity) 5805 return; 5806 5807 ieee80211_iterate_stations_atomic(rtwdev->hw, 5808 rtw89_phy_tx_path_div_sta_iter, 5809 &done); 5810 } 5811 5812 #define ANTDIV_MAIN 0 5813 #define ANTDIV_AUX 1 5814 5815 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev) 5816 { 5817 struct rtw89_hal *hal = &rtwdev->hal; 5818 u8 default_ant, optional_ant; 5819 5820 if (!hal->ant_diversity || hal->antenna_tx == 0) 5821 return; 5822 5823 if (hal->antenna_tx == RF_B) { 5824 default_ant = ANTDIV_AUX; 5825 optional_ant = ANTDIV_MAIN; 5826 } else { 5827 default_ant = ANTDIV_MAIN; 5828 optional_ant = ANTDIV_AUX; 5829 } 5830 5831 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL, 5832 default_ant, RTW89_PHY_0); 5833 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI, 5834 default_ant, RTW89_PHY_0); 5835 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT, 5836 optional_ant, RTW89_PHY_0); 5837 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI, 5838 default_ant, RTW89_PHY_0); 5839 } 5840 5841 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev) 5842 { 5843 struct rtw89_hal *hal = &rtwdev->hal; 5844 5845 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A; 5846 hal->antenna_tx = hal->antenna_rx; 5847 } 5848 5849 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev) 5850 { 5851 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5852 struct rtw89_hal *hal = &rtwdev->hal; 5853 bool no_change = false; 5854 u8 main_rssi, aux_rssi; 5855 u8 main_evm, aux_evm; 5856 u32 candidate; 5857 5858 antdiv->get_stats = false; 5859 antdiv->training_count = 0; 5860 5861 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats); 5862 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats); 5863 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats); 5864 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats); 5865 5866 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH) 5867 candidate = RF_A; 5868 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH) 5869 candidate = RF_B; 5870 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 5871 candidate = RF_A; 5872 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 5873 candidate = RF_B; 5874 else 5875 no_change = true; 5876 5877 if (no_change) { 5878 /* swap back from training antenna to original */ 5879 rtw89_phy_swap_hal_antenna(rtwdev); 5880 return; 5881 } 5882 5883 hal->antenna_tx = candidate; 5884 hal->antenna_rx = candidate; 5885 } 5886 5887 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev) 5888 { 5889 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5890 u64 state_period; 5891 5892 if (antdiv->training_count % 2 == 0) { 5893 if (antdiv->training_count == 0) 5894 rtw89_phy_antdiv_sts_reset(rtwdev); 5895 5896 antdiv->get_stats = true; 5897 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL); 5898 } else { 5899 antdiv->get_stats = false; 5900 state_period = msecs_to_jiffies(ANTDIV_DELAY); 5901 5902 rtw89_phy_swap_hal_antenna(rtwdev); 5903 rtw89_phy_antdiv_set_ant(rtwdev); 5904 } 5905 5906 antdiv->training_count++; 5907 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 5908 state_period); 5909 } 5910 5911 void rtw89_phy_antdiv_work(struct work_struct *work) 5912 { 5913 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 5914 antdiv_work.work); 5915 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5916 5917 mutex_lock(&rtwdev->mutex); 5918 5919 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) { 5920 rtw89_phy_antdiv_training_state(rtwdev); 5921 } else { 5922 rtw89_phy_antdiv_decision_state(rtwdev); 5923 rtw89_phy_antdiv_set_ant(rtwdev); 5924 } 5925 5926 mutex_unlock(&rtwdev->mutex); 5927 } 5928 5929 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev) 5930 { 5931 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5932 struct rtw89_hal *hal = &rtwdev->hal; 5933 u8 rssi, rssi_pre; 5934 5935 if (!hal->ant_diversity || hal->ant_diversity_fixed) 5936 return; 5937 5938 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats); 5939 rssi_pre = antdiv->rssi_pre; 5940 antdiv->rssi_pre = rssi; 5941 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 5942 5943 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH) 5944 return; 5945 5946 antdiv->training_count = 0; 5947 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 0); 5948 } 5949 5950 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 5951 { 5952 rtw89_phy_ccx_top_setting_init(rtwdev); 5953 rtw89_phy_ifs_clm_setting_init(rtwdev); 5954 } 5955 5956 static void rtw89_phy_edcca_init(struct rtw89_dev *rtwdev) 5957 { 5958 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 5959 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak; 5960 5961 memset(edcca_bak, 0, sizeof(*edcca_bak)); 5962 5963 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) { 5964 rtw89_phy_set_phy_regs(rtwdev, R_TXGATING, B_TXGATING_EN, 0); 5965 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_VAL, 2); 5966 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_ON, 1); 5967 rtw89_phy_set_phy_regs(rtwdev, R_SPOOF_CG, B_SPOOF_CG_EN, 0); 5968 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_CG_EN, 0); 5969 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 0); 5970 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 0); 5971 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 1); 5972 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 1); 5973 } 5974 5975 rtw89_phy_write32_mask(rtwdev, edcca_regs->tx_collision_t2r_st, 5976 edcca_regs->tx_collision_t2r_st_mask, 0x29); 5977 } 5978 5979 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 5980 { 5981 rtw89_phy_stat_init(rtwdev); 5982 5983 rtw89_chip_bb_sethw(rtwdev); 5984 5985 rtw89_phy_env_monitor_init(rtwdev); 5986 rtw89_physts_parsing_init(rtwdev); 5987 rtw89_phy_dig_init(rtwdev); 5988 rtw89_phy_cfo_init(rtwdev); 5989 rtw89_phy_bb_wrap_init(rtwdev); 5990 rtw89_phy_edcca_init(rtwdev); 5991 rtw89_phy_ch_info_init(rtwdev); 5992 rtw89_phy_ul_tb_info_init(rtwdev); 5993 rtw89_phy_antdiv_init(rtwdev); 5994 rtw89_chip_rfe_gpio(rtwdev); 5995 rtw89_phy_antdiv_set_ant(rtwdev); 5996 5997 rtw89_chip_rfk_hw_init(rtwdev); 5998 rtw89_phy_init_rf_nctl(rtwdev); 5999 rtw89_chip_rfk_init(rtwdev); 6000 rtw89_chip_set_txpwr_ctrl(rtwdev); 6001 rtw89_chip_power_trim(rtwdev); 6002 rtw89_chip_cfg_txrx_path(rtwdev); 6003 } 6004 6005 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 6006 { 6007 const struct rtw89_chip_info *chip = rtwdev->chip; 6008 const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld; 6009 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 6010 u8 bss_color; 6011 6012 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 6013 return; 6014 6015 bss_color = vif->bss_conf.he_bss_color.color; 6016 6017 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1, 6018 phy_idx); 6019 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT, 6020 bss_color, phy_idx); 6021 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID, 6022 vif->cfg.aid, phy_idx); 6023 } 6024 6025 static bool rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc *desc) 6026 { 6027 return desc->ch != 0; 6028 } 6029 6030 static bool rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc *desc, 6031 const struct rtw89_chan *chan) 6032 { 6033 if (!rfk_chan_validate_desc(desc)) 6034 return false; 6035 6036 if (desc->ch != chan->channel) 6037 return false; 6038 6039 if (desc->has_band && desc->band != chan->band_type) 6040 return false; 6041 6042 if (desc->has_bw && desc->bw != chan->band_width) 6043 return false; 6044 6045 return true; 6046 } 6047 6048 struct rfk_chan_iter_data { 6049 const struct rtw89_rfk_chan_desc desc; 6050 unsigned int found; 6051 }; 6052 6053 static int rfk_chan_iter_search(const struct rtw89_chan *chan, void *data) 6054 { 6055 struct rfk_chan_iter_data *iter_data = data; 6056 6057 if (rfk_chan_is_equivalent(&iter_data->desc, chan)) 6058 iter_data->found++; 6059 6060 return 0; 6061 } 6062 6063 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev, 6064 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr, 6065 const struct rtw89_chan *target_chan) 6066 { 6067 int sel = -1; 6068 u8 i; 6069 6070 for (i = 0; i < desc_nr; i++) { 6071 struct rfk_chan_iter_data iter_data = { 6072 .desc = desc[i], 6073 }; 6074 6075 if (rfk_chan_is_equivalent(&desc[i], target_chan)) 6076 return i; 6077 6078 rtw89_iterate_entity_chan(rtwdev, rfk_chan_iter_search, &iter_data); 6079 if (!iter_data.found && sel == -1) 6080 sel = i; 6081 } 6082 6083 if (sel == -1) { 6084 rtw89_debug(rtwdev, RTW89_DBG_RFK, 6085 "no idle rfk entry; force replace the first\n"); 6086 sel = 0; 6087 } 6088 6089 return sel; 6090 } 6091 EXPORT_SYMBOL(rtw89_rfk_chan_lookup); 6092 6093 static void 6094 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6095 { 6096 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 6097 } 6098 6099 static void 6100 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6101 { 6102 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 6103 } 6104 6105 static void 6106 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6107 { 6108 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 6109 } 6110 6111 static void 6112 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6113 { 6114 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 6115 } 6116 6117 static void 6118 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6119 { 6120 udelay(def->data); 6121 } 6122 6123 static void 6124 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 6125 [RTW89_RFK_F_WRF] = _rfk_write_rf, 6126 [RTW89_RFK_F_WM] = _rfk_write32_mask, 6127 [RTW89_RFK_F_WS] = _rfk_write32_set, 6128 [RTW89_RFK_F_WC] = _rfk_write32_clr, 6129 [RTW89_RFK_F_DELAY] = _rfk_delay, 6130 }; 6131 6132 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 6133 6134 void 6135 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 6136 { 6137 const struct rtw89_reg5_def *p = tbl->defs; 6138 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 6139 6140 for (; p < end; p++) 6141 _rfk_handler[p->flag](rtwdev, p); 6142 } 6143 EXPORT_SYMBOL(rtw89_rfk_parser); 6144 6145 #define RTW89_TSSI_FAST_MODE_NUM 4 6146 6147 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 6148 {0xD934, 0xff0000}, 6149 {0xD934, 0xff000000}, 6150 {0xD938, 0xff}, 6151 {0xD934, 0xff00}, 6152 }; 6153 6154 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 6155 {0xD930, 0xff0000}, 6156 {0xD930, 0xff000000}, 6157 {0xD934, 0xff}, 6158 {0xD930, 0xff00}, 6159 }; 6160 6161 static 6162 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 6163 enum rtw89_mac_idx mac_idx, 6164 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 6165 u32 val) 6166 { 6167 const struct rtw89_reg_def *regs; 6168 u32 reg; 6169 int i; 6170 6171 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 6172 regs = rtw89_tssi_fastmode_regs_flat; 6173 else 6174 regs = rtw89_tssi_fastmode_regs_level; 6175 6176 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 6177 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 6178 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 6179 } 6180 } 6181 6182 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 6183 {0xD91C, 0xff000000}, 6184 {0xD920, 0xff}, 6185 {0xD920, 0xff00}, 6186 {0xD920, 0xff0000}, 6187 {0xD920, 0xff000000}, 6188 {0xD924, 0xff}, 6189 {0xD924, 0xff00}, 6190 {0xD914, 0xff000000}, 6191 {0xD918, 0xff}, 6192 {0xD918, 0xff00}, 6193 {0xD918, 0xff0000}, 6194 {0xD918, 0xff000000}, 6195 {0xD91C, 0xff}, 6196 {0xD91C, 0xff00}, 6197 {0xD91C, 0xff0000}, 6198 }; 6199 6200 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 6201 {0xD910, 0xff}, 6202 {0xD910, 0xff00}, 6203 {0xD910, 0xff0000}, 6204 {0xD910, 0xff000000}, 6205 {0xD914, 0xff}, 6206 {0xD914, 0xff00}, 6207 {0xD914, 0xff0000}, 6208 {0xD908, 0xff}, 6209 {0xD908, 0xff00}, 6210 {0xD908, 0xff0000}, 6211 {0xD908, 0xff000000}, 6212 {0xD90C, 0xff}, 6213 {0xD90C, 0xff00}, 6214 {0xD90C, 0xff0000}, 6215 {0xD90C, 0xff000000}, 6216 }; 6217 6218 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 6219 enum rtw89_mac_idx mac_idx, 6220 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 6221 { 6222 const struct rtw89_chip_info *chip = rtwdev->chip; 6223 const struct rtw89_reg_def *regs; 6224 const u32 *data; 6225 u32 reg; 6226 int i; 6227 6228 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 6229 return; 6230 6231 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 6232 regs = rtw89_tssi_bandedge_regs_flat; 6233 else 6234 regs = rtw89_tssi_bandedge_regs_level; 6235 6236 data = chip->tssi_dbw_table->data[bandedge_cfg]; 6237 6238 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 6239 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 6240 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 6241 } 6242 6243 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx); 6244 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 6245 6246 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 6247 data[RTW89_TSSI_SBW20]); 6248 } 6249 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 6250 6251 static 6252 const u8 rtw89_ch_base_table[16] = {1, 0xff, 6253 36, 100, 132, 149, 0xff, 6254 1, 33, 65, 97, 129, 161, 193, 225, 0xff}; 6255 #define RTW89_CH_BASE_IDX_2G 0 6256 #define RTW89_CH_BASE_IDX_5G_FIRST 2 6257 #define RTW89_CH_BASE_IDX_5G_LAST 5 6258 #define RTW89_CH_BASE_IDX_6G_FIRST 7 6259 #define RTW89_CH_BASE_IDX_6G_LAST 14 6260 6261 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4) 6262 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0) 6263 6264 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band) 6265 { 6266 u8 chan_idx; 6267 u8 last, first; 6268 u8 idx; 6269 6270 switch (band) { 6271 case RTW89_BAND_2G: 6272 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) | 6273 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch); 6274 return chan_idx; 6275 case RTW89_BAND_5G: 6276 first = RTW89_CH_BASE_IDX_5G_FIRST; 6277 last = RTW89_CH_BASE_IDX_5G_LAST; 6278 break; 6279 case RTW89_BAND_6G: 6280 first = RTW89_CH_BASE_IDX_6G_FIRST; 6281 last = RTW89_CH_BASE_IDX_6G_LAST; 6282 break; 6283 default: 6284 rtw89_warn(rtwdev, "Unsupported band %d\n", band); 6285 return 0; 6286 } 6287 6288 for (idx = last; idx >= first; idx--) 6289 if (central_ch >= rtw89_ch_base_table[idx]) 6290 break; 6291 6292 if (idx < first) { 6293 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch); 6294 return 0; 6295 } 6296 6297 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) | 6298 FIELD_PREP(RTW89_CH_OFFSET_MASK, 6299 (central_ch - rtw89_ch_base_table[idx]) >> 1); 6300 return chan_idx; 6301 } 6302 EXPORT_SYMBOL(rtw89_encode_chan_idx); 6303 6304 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 6305 u8 *ch, enum nl80211_band *band) 6306 { 6307 u8 idx, offset; 6308 6309 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx); 6310 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx); 6311 6312 if (idx == RTW89_CH_BASE_IDX_2G) { 6313 *band = NL80211_BAND_2GHZ; 6314 *ch = offset; 6315 return; 6316 } 6317 6318 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ; 6319 *ch = rtw89_ch_base_table[idx] + (offset << 1); 6320 } 6321 EXPORT_SYMBOL(rtw89_decode_chan_idx); 6322 6323 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan) 6324 { 6325 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 6326 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak; 6327 6328 if (scan) { 6329 edcca_bak->a = 6330 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level, 6331 edcca_regs->edcca_mask); 6332 edcca_bak->p = 6333 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level, 6334 edcca_regs->edcca_p_mask); 6335 edcca_bak->ppdu = 6336 rtw89_phy_read32_mask(rtwdev, edcca_regs->ppdu_level, 6337 edcca_regs->ppdu_mask); 6338 6339 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6340 edcca_regs->edcca_mask, EDCCA_MAX); 6341 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6342 edcca_regs->edcca_p_mask, EDCCA_MAX); 6343 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level, 6344 edcca_regs->ppdu_mask, EDCCA_MAX); 6345 } else { 6346 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6347 edcca_regs->edcca_mask, 6348 edcca_bak->a); 6349 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6350 edcca_regs->edcca_p_mask, 6351 edcca_bak->p); 6352 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level, 6353 edcca_regs->ppdu_mask, 6354 edcca_bak->ppdu); 6355 } 6356 } 6357 6358 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev) 6359 { 6360 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 6361 bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80; 6362 s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80; 6363 u8 path, per20_bitmap; 6364 u8 pwdb[8]; 6365 u32 tmp; 6366 6367 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA)) 6368 return; 6369 6370 if (rtwdev->chip->chip_id == RTL8922A) 6371 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 6372 edcca_regs->rpt_sel_be_mask, 0); 6373 6374 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6375 edcca_regs->rpt_sel_mask, 0); 6376 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 6377 path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK); 6378 flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80); 6379 flag_s40 = u32_get_bits(tmp, B_EDCCA_RPT_B_S40); 6380 flag_s20 = u32_get_bits(tmp, B_EDCCA_RPT_B_S20); 6381 flag_p20 = u32_get_bits(tmp, B_EDCCA_RPT_B_P20); 6382 flag_fb = u32_get_bits(tmp, B_EDCCA_RPT_B_FB); 6383 pwdb_s20 = u32_get_bits(tmp, MASKBYTE1); 6384 pwdb_p20 = u32_get_bits(tmp, MASKBYTE2); 6385 pwdb_fb = u32_get_bits(tmp, MASKBYTE3); 6386 6387 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6388 edcca_regs->rpt_sel_mask, 4); 6389 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 6390 pwdb_s80 = u32_get_bits(tmp, MASKBYTE1); 6391 pwdb_s40 = u32_get_bits(tmp, MASKBYTE2); 6392 6393 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_regs->rpt_a, 6394 MASKBYTE0); 6395 6396 if (rtwdev->chip->chip_id == RTL8922A) { 6397 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 6398 edcca_regs->rpt_sel_be_mask, 4); 6399 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 6400 pwdb[0] = u32_get_bits(tmp, MASKBYTE3); 6401 pwdb[1] = u32_get_bits(tmp, MASKBYTE2); 6402 pwdb[2] = u32_get_bits(tmp, MASKBYTE1); 6403 pwdb[3] = u32_get_bits(tmp, MASKBYTE0); 6404 6405 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 6406 edcca_regs->rpt_sel_be_mask, 5); 6407 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 6408 pwdb[4] = u32_get_bits(tmp, MASKBYTE3); 6409 pwdb[5] = u32_get_bits(tmp, MASKBYTE2); 6410 pwdb[6] = u32_get_bits(tmp, MASKBYTE1); 6411 pwdb[7] = u32_get_bits(tmp, MASKBYTE0); 6412 } else { 6413 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6414 edcca_regs->rpt_sel_mask, 0); 6415 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 6416 pwdb[0] = u32_get_bits(tmp, MASKBYTE3); 6417 pwdb[1] = u32_get_bits(tmp, MASKBYTE2); 6418 6419 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6420 edcca_regs->rpt_sel_mask, 1); 6421 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 6422 pwdb[2] = u32_get_bits(tmp, MASKBYTE3); 6423 pwdb[3] = u32_get_bits(tmp, MASKBYTE2); 6424 6425 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6426 edcca_regs->rpt_sel_mask, 2); 6427 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 6428 pwdb[4] = u32_get_bits(tmp, MASKBYTE3); 6429 pwdb[5] = u32_get_bits(tmp, MASKBYTE2); 6430 6431 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6432 edcca_regs->rpt_sel_mask, 3); 6433 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 6434 pwdb[6] = u32_get_bits(tmp, MASKBYTE3); 6435 pwdb[7] = u32_get_bits(tmp, MASKBYTE2); 6436 } 6437 6438 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6439 "[EDCCA]: edcca_bitmap = %04x\n", per20_bitmap); 6440 6441 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6442 "[EDCCA]: pwdb per20{0,1,2,3,4,5,6,7} = {%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n", 6443 pwdb[0], pwdb[1], pwdb[2], pwdb[3], pwdb[4], pwdb[5], 6444 pwdb[6], pwdb[7]); 6445 6446 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6447 "[EDCCA]: path=%d, flag {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}\n", 6448 path, flag_fb, flag_p20, flag_s20, flag_s40, flag_s80); 6449 6450 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6451 "[EDCCA]: pwdb {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}(dBm)\n", 6452 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80); 6453 } 6454 6455 static u8 rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev *rtwdev) 6456 { 6457 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 6458 bool is_linked = rtwdev->total_sta_assoc > 0; 6459 u8 rssi_min = ch_info->rssi_min >> 1; 6460 u8 edcca_thre; 6461 6462 if (!is_linked) { 6463 edcca_thre = EDCCA_MAX; 6464 } else { 6465 edcca_thre = rssi_min - RSSI_UNIT_CONVER + EDCCA_UNIT_CONVER - 6466 EDCCA_TH_REF; 6467 edcca_thre = max_t(u8, edcca_thre, EDCCA_TH_L2H_LB); 6468 } 6469 6470 return edcca_thre; 6471 } 6472 6473 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev) 6474 { 6475 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 6476 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak; 6477 u8 th; 6478 6479 th = rtw89_phy_edcca_get_thre_by_rssi(rtwdev); 6480 if (th == edcca_bak->th_old) 6481 return; 6482 6483 edcca_bak->th_old = th; 6484 6485 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6486 "[EDCCA]: Normal Mode, EDCCA_th = %d\n", th); 6487 6488 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6489 edcca_regs->edcca_mask, th); 6490 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6491 edcca_regs->edcca_p_mask, th); 6492 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level, 6493 edcca_regs->ppdu_mask, th); 6494 } 6495 6496 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev) 6497 { 6498 struct rtw89_hal *hal = &rtwdev->hal; 6499 6500 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DYNAMIC_EDCCA)) 6501 return; 6502 6503 rtw89_phy_edcca_thre_calc(rtwdev); 6504 rtw89_phy_edcca_log(rtwdev); 6505 } 6506 6507 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev, 6508 enum rtw89_phy_idx phy_idx) 6509 { 6510 rtw89_debug(rtwdev, RTW89_DBG_RFK, 6511 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n", 6512 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx); 6513 6514 switch (rtwdev->mlo_dbcc_mode) { 6515 case MLO_1_PLUS_1_1RF: 6516 if (phy_idx == RTW89_PHY_0) 6517 return RF_A; 6518 else 6519 return RF_B; 6520 case MLO_1_PLUS_1_2RF: 6521 if (phy_idx == RTW89_PHY_0) 6522 return RF_A; 6523 else 6524 return RF_D; 6525 case MLO_0_PLUS_2_1RF: 6526 case MLO_2_PLUS_0_1RF: 6527 /* for both PHY 0/1 */ 6528 return RF_AB; 6529 case MLO_0_PLUS_2_2RF: 6530 case MLO_2_PLUS_0_2RF: 6531 case MLO_2_PLUS_2_2RF: 6532 default: 6533 if (phy_idx == RTW89_PHY_0) 6534 return RF_AB; 6535 else 6536 return RF_CD; 6537 } 6538 } 6539 EXPORT_SYMBOL(rtw89_phy_get_kpath); 6540 6541 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev, 6542 enum rtw89_phy_idx phy_idx) 6543 { 6544 rtw89_debug(rtwdev, RTW89_DBG_RFK, 6545 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n", 6546 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx); 6547 6548 switch (rtwdev->mlo_dbcc_mode) { 6549 case MLO_1_PLUS_1_1RF: 6550 if (phy_idx == RTW89_PHY_0) 6551 return RF_PATH_A; 6552 else 6553 return RF_PATH_B; 6554 case MLO_1_PLUS_1_2RF: 6555 if (phy_idx == RTW89_PHY_0) 6556 return RF_PATH_A; 6557 else 6558 return RF_PATH_D; 6559 case MLO_0_PLUS_2_1RF: 6560 case MLO_2_PLUS_0_1RF: 6561 if (phy_idx == RTW89_PHY_0) 6562 return RF_PATH_A; 6563 else 6564 return RF_PATH_B; 6565 case MLO_0_PLUS_2_2RF: 6566 case MLO_2_PLUS_0_2RF: 6567 case MLO_2_PLUS_2_2RF: 6568 default: 6569 if (phy_idx == RTW89_PHY_0) 6570 return RF_PATH_A; 6571 else 6572 return RF_PATH_C; 6573 } 6574 } 6575 EXPORT_SYMBOL(rtw89_phy_get_syn_sel); 6576 6577 static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = { 6578 .setting_addr = R_CCX, 6579 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK, 6580 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, 6581 .trig_opt_mask = B_CCX_TRIG_OPT_MSK, 6582 .en_mask = B_CCX_EN_MSK, 6583 .ifs_cnt_addr = R_IFS_COUNTER, 6584 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, 6585 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, 6586 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, 6587 .ifs_collect_en_mask = B_IFS_COLLECT_EN, 6588 .ifs_t1_addr = R_IFS_T1, 6589 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, 6590 .ifs_t1_en_mask = B_IFS_T1_EN_MSK, 6591 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, 6592 .ifs_t2_addr = R_IFS_T2, 6593 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, 6594 .ifs_t2_en_mask = B_IFS_T2_EN_MSK, 6595 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, 6596 .ifs_t3_addr = R_IFS_T3, 6597 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, 6598 .ifs_t3_en_mask = B_IFS_T3_EN_MSK, 6599 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, 6600 .ifs_t4_addr = R_IFS_T4, 6601 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, 6602 .ifs_t4_en_mask = B_IFS_T4_EN_MSK, 6603 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, 6604 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT, 6605 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, 6606 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, 6607 .ifs_clm_cca_addr = R_IFS_CLM_CCA, 6608 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, 6609 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, 6610 .ifs_clm_fa_addr = R_IFS_CLM_FA, 6611 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, 6612 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, 6613 .ifs_his_addr = R_IFS_HIS, 6614 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, 6615 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, 6616 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, 6617 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK, 6618 .ifs_avg_l_addr = R_IFS_AVG_L, 6619 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK, 6620 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK, 6621 .ifs_avg_h_addr = R_IFS_AVG_H, 6622 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK, 6623 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK, 6624 .ifs_cca_l_addr = R_IFS_CCA_L, 6625 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK, 6626 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK, 6627 .ifs_cca_h_addr = R_IFS_CCA_H, 6628 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK, 6629 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK, 6630 .ifs_total_addr = R_IFSCNT, 6631 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK, 6632 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK, 6633 }; 6634 6635 static const struct rtw89_physts_regs rtw89_physts_regs_ax = { 6636 .setting_addr = R_PLCP_HISTOGRAM, 6637 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, 6638 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, 6639 }; 6640 6641 static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = { 6642 .comp = R_DCFO_WEIGHT, 6643 .weighting_mask = B_DCFO_WEIGHT_MSK, 6644 .comp_seg0 = R_DCFO_OPT, 6645 .valid_0_mask = B_DCFO_OPT_EN, 6646 }; 6647 6648 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = { 6649 .cr_base = 0x10000, 6650 .ccx = &rtw89_ccx_regs_ax, 6651 .physts = &rtw89_physts_regs_ax, 6652 .cfo = &rtw89_cfo_regs_ax, 6653 .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax, 6654 .config_bb_gain = rtw89_phy_config_bb_gain_ax, 6655 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax, 6656 .bb_wrap_init = NULL, 6657 .ch_info_init = NULL, 6658 6659 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax, 6660 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax, 6661 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax, 6662 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax, 6663 }; 6664 EXPORT_SYMBOL(rtw89_phy_gen_ax); 6665