1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "ps.h" 11 #include "reg.h" 12 #include "sar.h" 13 #include "txrx.h" 14 #include "util.h" 15 16 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 17 const struct rtw89_ra_report *report) 18 { 19 u32 bit_rate = report->bit_rate; 20 21 /* lower than ofdm, do not aggregate */ 22 if (bit_rate < 550) 23 return 1; 24 25 /* avoid AMSDU for legacy rate */ 26 if (report->might_fallback_legacy) 27 return 1; 28 29 /* lower than 20M vht 2ss mcs8, make it small */ 30 if (bit_rate < 1800) 31 return 1200; 32 33 /* lower than 40M vht 2ss mcs9, make it medium */ 34 if (bit_rate < 4000) 35 return 2600; 36 37 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 38 if (bit_rate < 7000) 39 return 3500; 40 41 return rtwdev->chip->max_amsdu_limit; 42 } 43 44 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 45 { 46 u64 ra_mask = 0; 47 u8 mcs_cap; 48 int i, nss; 49 50 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 51 mcs_cap = mcs_map & 0x3; 52 switch (mcs_cap) { 53 case 2: 54 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 55 break; 56 case 1: 57 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 58 break; 59 case 0: 60 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 61 break; 62 default: 63 break; 64 } 65 } 66 67 return ra_mask; 68 } 69 70 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 71 { 72 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 73 u16 mcs_map; 74 75 switch (sta->deflink.bandwidth) { 76 case IEEE80211_STA_RX_BW_160: 77 if (cap.he_cap_elem.phy_cap_info[0] & 78 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 79 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 80 else 81 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 82 break; 83 default: 84 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 85 } 86 87 /* MCS11, MCS9, MCS7 */ 88 return get_mcs_ra_mask(mcs_map, 11, 2); 89 } 90 91 #define RA_FLOOR_TABLE_SIZE 7 92 #define RA_FLOOR_UP_GAP 3 93 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 94 u8 ratr_state) 95 { 96 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 97 u8 rssi_lv = 0; 98 u8 i; 99 100 rssi >>= 1; 101 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 102 if (i >= ratr_state) 103 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 104 if (rssi < rssi_lv_t[i]) { 105 rssi_lv = i; 106 break; 107 } 108 } 109 if (rssi_lv == 0) 110 return 0xffffffffffffffffULL; 111 else if (rssi_lv == 1) 112 return 0xfffffffffffffff0ULL; 113 else if (rssi_lv == 2) 114 return 0xffffffffffffefe0ULL; 115 else if (rssi_lv == 3) 116 return 0xffffffffffffcfc0ULL; 117 else if (rssi_lv == 4) 118 return 0xffffffffffff8f80ULL; 119 else if (rssi_lv >= 5) 120 return 0xffffffffffff0f00ULL; 121 122 return 0xffffffffffffffffULL; 123 } 124 125 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 126 { 127 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 128 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 129 130 if (ra_mask == 0) 131 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 132 133 return ra_mask; 134 } 135 136 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 137 const struct rtw89_chan *chan) 138 { 139 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 140 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 141 enum nl80211_band band; 142 u64 cfg_mask; 143 144 if (!rtwsta->use_cfg_mask) 145 return -1; 146 147 switch (chan->band_type) { 148 case RTW89_BAND_2G: 149 band = NL80211_BAND_2GHZ; 150 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 151 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 152 break; 153 case RTW89_BAND_5G: 154 band = NL80211_BAND_5GHZ; 155 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 156 RA_MASK_OFDM_RATES); 157 break; 158 case RTW89_BAND_6G: 159 band = NL80211_BAND_6GHZ; 160 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 161 RA_MASK_OFDM_RATES); 162 break; 163 default: 164 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 165 return -1; 166 } 167 168 if (sta->deflink.he_cap.has_he) { 169 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 170 RA_MASK_HE_1SS_RATES); 171 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 172 RA_MASK_HE_2SS_RATES); 173 } else if (sta->deflink.vht_cap.vht_supported) { 174 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 175 RA_MASK_VHT_1SS_RATES); 176 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 177 RA_MASK_VHT_2SS_RATES); 178 } else if (sta->deflink.ht_cap.ht_supported) { 179 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 180 RA_MASK_HT_1SS_RATES); 181 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 182 RA_MASK_HT_2SS_RATES); 183 } 184 185 return cfg_mask; 186 } 187 188 static const u64 189 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 190 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 191 static const u64 192 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 193 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 194 static const u64 195 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 196 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 197 198 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 199 struct rtw89_sta *rtwsta, 200 const struct rtw89_chan *chan, 201 bool *fix_giltf_en, u8 *fix_giltf) 202 { 203 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 204 u8 band = chan->band_type; 205 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 206 u8 he_gi = mask->control[nl_band].he_gi; 207 u8 he_ltf = mask->control[nl_band].he_ltf; 208 209 if (!rtwsta->use_cfg_mask) 210 return; 211 212 if (he_ltf == 2 && he_gi == 2) { 213 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 214 } else if (he_ltf == 2 && he_gi == 0) { 215 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 216 } else if (he_ltf == 1 && he_gi == 1) { 217 *fix_giltf = RTW89_GILTF_2XHE16; 218 } else if (he_ltf == 1 && he_gi == 0) { 219 *fix_giltf = RTW89_GILTF_2XHE08; 220 } else if (he_ltf == 0 && he_gi == 1) { 221 *fix_giltf = RTW89_GILTF_1XHE16; 222 } else if (he_ltf == 0 && he_gi == 0) { 223 *fix_giltf = RTW89_GILTF_1XHE08; 224 } else { 225 *fix_giltf_en = false; 226 return; 227 } 228 229 *fix_giltf_en = true; 230 } 231 232 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 233 struct ieee80211_sta *sta, bool csi) 234 { 235 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 236 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 237 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 238 struct rtw89_ra_info *ra = &rtwsta->ra; 239 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 240 rtwvif->sub_entity_idx); 241 struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); 242 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 243 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 244 u64 ra_mask = 0; 245 u64 ra_mask_bak; 246 u8 mode = 0; 247 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 248 u8 bw_mode = 0; 249 u8 stbc_en = 0; 250 u8 ldpc_en = 0; 251 u8 fix_giltf = 0; 252 u8 i; 253 bool sgi = false; 254 bool fix_giltf_en = false; 255 256 memset(ra, 0, sizeof(*ra)); 257 /* Set the ra mask from sta's capability */ 258 if (sta->deflink.he_cap.has_he) { 259 mode |= RTW89_RA_MODE_HE; 260 csi_mode = RTW89_RA_RPT_MODE_HE; 261 ra_mask |= get_he_ra_mask(sta); 262 high_rate_masks = rtw89_ra_mask_he_rates; 263 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 264 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 265 stbc_en = 1; 266 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 267 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 268 ldpc_en = 1; 269 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, chan, &fix_giltf_en, &fix_giltf); 270 } else if (sta->deflink.vht_cap.vht_supported) { 271 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 272 273 mode |= RTW89_RA_MODE_VHT; 274 csi_mode = RTW89_RA_RPT_MODE_VHT; 275 /* MCS9, MCS8, MCS7 */ 276 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 277 high_rate_masks = rtw89_ra_mask_vht_rates; 278 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 279 stbc_en = 1; 280 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 281 ldpc_en = 1; 282 } else if (sta->deflink.ht_cap.ht_supported) { 283 mode |= RTW89_RA_MODE_HT; 284 csi_mode = RTW89_RA_RPT_MODE_HT; 285 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 286 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 287 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 288 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 289 high_rate_masks = rtw89_ra_mask_ht_rates; 290 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 291 stbc_en = 1; 292 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 293 ldpc_en = 1; 294 } 295 296 switch (chan->band_type) { 297 case RTW89_BAND_2G: 298 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 299 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xf) 300 mode |= RTW89_RA_MODE_CCK; 301 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xff0) 302 mode |= RTW89_RA_MODE_OFDM; 303 break; 304 case RTW89_BAND_5G: 305 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 306 mode |= RTW89_RA_MODE_OFDM; 307 break; 308 case RTW89_BAND_6G: 309 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 310 mode |= RTW89_RA_MODE_OFDM; 311 break; 312 default: 313 rtw89_err(rtwdev, "Unknown band type\n"); 314 break; 315 } 316 317 ra_mask_bak = ra_mask; 318 319 if (mode >= RTW89_RA_MODE_HT) { 320 u64 mask = 0; 321 for (i = 0; i < rtwdev->hal.tx_nss; i++) 322 mask |= high_rate_masks[i]; 323 if (mode & RTW89_RA_MODE_OFDM) 324 mask |= RA_MASK_SUBOFDM_RATES; 325 if (mode & RTW89_RA_MODE_CCK) 326 mask |= RA_MASK_SUBCCK_RATES; 327 ra_mask &= mask; 328 } else if (mode & RTW89_RA_MODE_OFDM) { 329 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 330 } 331 332 if (mode != RTW89_RA_MODE_CCK) 333 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 334 335 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 336 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan); 337 338 switch (sta->deflink.bandwidth) { 339 case IEEE80211_STA_RX_BW_160: 340 bw_mode = RTW89_CHANNEL_WIDTH_160; 341 sgi = sta->deflink.vht_cap.vht_supported && 342 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 343 break; 344 case IEEE80211_STA_RX_BW_80: 345 bw_mode = RTW89_CHANNEL_WIDTH_80; 346 sgi = sta->deflink.vht_cap.vht_supported && 347 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 348 break; 349 case IEEE80211_STA_RX_BW_40: 350 bw_mode = RTW89_CHANNEL_WIDTH_40; 351 sgi = sta->deflink.ht_cap.ht_supported && 352 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 353 break; 354 default: 355 bw_mode = RTW89_CHANNEL_WIDTH_20; 356 sgi = sta->deflink.ht_cap.ht_supported && 357 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 358 break; 359 } 360 361 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 362 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 363 ra->dcm_cap = 1; 364 365 if (rate_pattern->enable && !vif->p2p) { 366 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan); 367 ra_mask &= rate_pattern->ra_mask; 368 mode = rate_pattern->ra_mode; 369 } 370 371 ra->bw_cap = bw_mode; 372 ra->er_cap = rtwsta->er_cap; 373 ra->mode_ctrl = mode; 374 ra->macid = rtwsta->mac_id; 375 ra->stbc_cap = stbc_en; 376 ra->ldpc_cap = ldpc_en; 377 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 378 ra->en_sgi = sgi; 379 ra->ra_mask = ra_mask; 380 ra->fix_giltf_en = fix_giltf_en; 381 ra->fix_giltf = fix_giltf; 382 383 if (!csi) 384 return; 385 386 ra->fixed_csi_rate_en = false; 387 ra->ra_csi_rate_en = true; 388 ra->cr_tbl_sel = false; 389 ra->band_num = rtwvif->phy_idx; 390 ra->csi_bw = bw_mode; 391 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 392 ra->csi_mcs_ss_idx = 5; 393 ra->csi_mode = csi_mode; 394 } 395 396 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 397 u32 changed) 398 { 399 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 400 struct rtw89_ra_info *ra = &rtwsta->ra; 401 402 rtw89_phy_ra_sta_update(rtwdev, sta, false); 403 404 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 405 ra->upd_mask = 1; 406 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 407 ra->upd_bw_nss_mask = 1; 408 409 rtw89_debug(rtwdev, RTW89_DBG_RA, 410 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 411 ra->macid, 412 ra->bw_cap, 413 ra->ss_num, 414 ra->en_sgi, 415 ra->giltf); 416 417 rtw89_fw_h2c_ra(rtwdev, ra, false); 418 } 419 420 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 421 u16 rate_base, u64 ra_mask, u8 ra_mode, 422 u32 rate_ctrl, u32 ctrl_skip, bool force) 423 { 424 u8 n, c; 425 426 if (rate_ctrl == ctrl_skip) 427 return true; 428 429 n = hweight32(rate_ctrl); 430 if (n == 0) 431 return true; 432 433 if (force && n != 1) 434 return false; 435 436 if (next->enable) 437 return false; 438 439 c = __fls(rate_ctrl); 440 next->rate = rate_base + c; 441 next->ra_mode = ra_mode; 442 next->ra_mask = ra_mask; 443 next->enable = true; 444 445 return true; 446 } 447 448 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \ 449 { \ 450 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \ 451 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \ 452 } 453 454 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 455 struct ieee80211_vif *vif, 456 const struct cfg80211_bitrate_mask *mask) 457 { 458 struct ieee80211_supported_band *sband; 459 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 460 struct rtw89_phy_rate_pattern next_pattern = {0}; 461 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 462 rtwvif->sub_entity_idx); 463 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = { 464 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0), 465 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0), 466 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0), 467 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0), 468 }; 469 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = { 470 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0), 471 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0), 472 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0), 473 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0), 474 }; 475 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = { 476 RTW89_HW_RATE_BY_CHIP_GEN(MCS0), 477 RTW89_HW_RATE_BY_CHIP_GEN(MCS8), 478 RTW89_HW_RATE_BY_CHIP_GEN(MCS16), 479 RTW89_HW_RATE_BY_CHIP_GEN(MCS24), 480 }; 481 u8 band = chan->band_type; 482 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 483 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 484 u8 tx_nss = rtwdev->hal.tx_nss; 485 u8 i; 486 487 for (i = 0; i < tx_nss; i++) 488 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen], 489 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 490 mask->control[nl_band].he_mcs[i], 491 0, true)) 492 goto out; 493 494 for (i = 0; i < tx_nss; i++) 495 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen], 496 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 497 mask->control[nl_band].vht_mcs[i], 498 0, true)) 499 goto out; 500 501 for (i = 0; i < tx_nss; i++) 502 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen], 503 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 504 mask->control[nl_band].ht_mcs[i], 505 0, true)) 506 goto out; 507 508 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 509 * require at least one basic rate for ieee80211_set_bitrate_mask, 510 * so the decision just depends on if all bitrates are set or not. 511 */ 512 sband = rtwdev->hw->wiphy->bands[nl_band]; 513 if (band == RTW89_BAND_2G) { 514 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 515 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 516 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 517 mask->control[nl_band].legacy, 518 BIT(sband->n_bitrates) - 1, false)) 519 goto out; 520 } else { 521 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 522 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 523 mask->control[nl_band].legacy, 524 BIT(sband->n_bitrates) - 1, false)) 525 goto out; 526 } 527 528 if (!next_pattern.enable) 529 goto out; 530 531 rtwvif->rate_pattern = next_pattern; 532 rtw89_debug(rtwdev, RTW89_DBG_RA, 533 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 534 next_pattern.rate, 535 next_pattern.ra_mask, 536 next_pattern.ra_mode); 537 return; 538 539 out: 540 rtwvif->rate_pattern.enable = false; 541 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 542 } 543 544 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 545 { 546 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 547 548 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 549 } 550 551 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 552 { 553 ieee80211_iterate_stations_atomic(rtwdev->hw, 554 rtw89_phy_ra_updata_sta_iter, 555 rtwdev); 556 } 557 558 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 559 { 560 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 561 struct rtw89_ra_info *ra = &rtwsta->ra; 562 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 563 bool csi = rtw89_sta_has_beamformer_cap(sta); 564 565 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 566 567 if (rssi > 40) 568 ra->init_rate_lv = 1; 569 else if (rssi > 20) 570 ra->init_rate_lv = 2; 571 else if (rssi > 1) 572 ra->init_rate_lv = 3; 573 else 574 ra->init_rate_lv = 0; 575 ra->upd_all = 1; 576 rtw89_debug(rtwdev, RTW89_DBG_RA, 577 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 578 ra->macid, 579 ra->mode_ctrl, 580 ra->bw_cap, 581 ra->ss_num, 582 ra->init_rate_lv); 583 rtw89_debug(rtwdev, RTW89_DBG_RA, 584 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 585 ra->dcm_cap, 586 ra->er_cap, 587 ra->ldpc_cap, 588 ra->stbc_cap, 589 ra->en_sgi, 590 ra->giltf); 591 592 rtw89_fw_h2c_ra(rtwdev, ra, csi); 593 } 594 595 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 596 const struct rtw89_chan *chan, 597 enum rtw89_bandwidth dbw) 598 { 599 enum rtw89_bandwidth cbw = chan->band_width; 600 u8 pri_ch = chan->primary_channel; 601 u8 central_ch = chan->channel; 602 u8 txsc_idx = 0; 603 u8 tmp = 0; 604 605 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 606 return txsc_idx; 607 608 switch (cbw) { 609 case RTW89_CHANNEL_WIDTH_40: 610 txsc_idx = pri_ch > central_ch ? 1 : 2; 611 break; 612 case RTW89_CHANNEL_WIDTH_80: 613 if (dbw == RTW89_CHANNEL_WIDTH_20) { 614 if (pri_ch > central_ch) 615 txsc_idx = (pri_ch - central_ch) >> 1; 616 else 617 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 618 } else { 619 txsc_idx = pri_ch > central_ch ? 9 : 10; 620 } 621 break; 622 case RTW89_CHANNEL_WIDTH_160: 623 if (pri_ch > central_ch) 624 tmp = (pri_ch - central_ch) >> 1; 625 else 626 tmp = ((central_ch - pri_ch) >> 1) + 1; 627 628 if (dbw == RTW89_CHANNEL_WIDTH_20) { 629 txsc_idx = tmp; 630 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 631 if (tmp == 1 || tmp == 3) 632 txsc_idx = 9; 633 else if (tmp == 5 || tmp == 7) 634 txsc_idx = 11; 635 else if (tmp == 2 || tmp == 4) 636 txsc_idx = 10; 637 else if (tmp == 6 || tmp == 8) 638 txsc_idx = 12; 639 else 640 return 0xff; 641 } else { 642 txsc_idx = pri_ch > central_ch ? 13 : 14; 643 } 644 break; 645 case RTW89_CHANNEL_WIDTH_80_80: 646 if (dbw == RTW89_CHANNEL_WIDTH_20) { 647 if (pri_ch > central_ch) 648 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 649 else 650 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 651 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 652 txsc_idx = pri_ch > central_ch ? 10 : 12; 653 } else { 654 txsc_idx = 14; 655 } 656 break; 657 default: 658 break; 659 } 660 661 return txsc_idx; 662 } 663 EXPORT_SYMBOL(rtw89_phy_get_txsc); 664 665 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 666 { 667 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 668 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 669 } 670 671 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 672 u32 addr, u32 mask) 673 { 674 const struct rtw89_chip_info *chip = rtwdev->chip; 675 const u32 *base_addr = chip->rf_base_addr; 676 u32 val, direct_addr; 677 678 if (rf_path >= rtwdev->chip->rf_path_num) { 679 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 680 return INV_RF_DATA; 681 } 682 683 addr &= 0xff; 684 direct_addr = base_addr[rf_path] + (addr << 2); 685 mask &= RFREG_MASK; 686 687 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 688 689 return val; 690 } 691 EXPORT_SYMBOL(rtw89_phy_read_rf); 692 693 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 694 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 695 { 696 bool busy; 697 bool done; 698 u32 val; 699 int ret; 700 701 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 702 1, 30, false, rtwdev); 703 if (ret) { 704 rtw89_err(rtwdev, "read rf busy swsi\n"); 705 return INV_RF_DATA; 706 } 707 708 mask &= RFREG_MASK; 709 710 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 711 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 712 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 713 udelay(2); 714 715 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 716 30, false, rtwdev, R_SWSI_V1, 717 B_SWSI_R_DATA_DONE_V1); 718 if (ret) { 719 rtw89_err(rtwdev, "read swsi busy\n"); 720 return INV_RF_DATA; 721 } 722 723 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 724 } 725 726 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 727 u32 addr, u32 mask) 728 { 729 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 730 731 if (rf_path >= rtwdev->chip->rf_path_num) { 732 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 733 return INV_RF_DATA; 734 } 735 736 if (ad_sel) 737 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 738 else 739 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 740 } 741 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 742 743 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 744 u32 addr, u32 mask, u32 data) 745 { 746 const struct rtw89_chip_info *chip = rtwdev->chip; 747 const u32 *base_addr = chip->rf_base_addr; 748 u32 direct_addr; 749 750 if (rf_path >= rtwdev->chip->rf_path_num) { 751 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 752 return false; 753 } 754 755 addr &= 0xff; 756 direct_addr = base_addr[rf_path] + (addr << 2); 757 mask &= RFREG_MASK; 758 759 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 760 761 /* delay to ensure writing properly */ 762 udelay(1); 763 764 return true; 765 } 766 EXPORT_SYMBOL(rtw89_phy_write_rf); 767 768 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 769 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 770 u32 data) 771 { 772 u8 bit_shift; 773 u32 val; 774 bool busy, b_msk_en = false; 775 int ret; 776 777 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 778 1, 30, false, rtwdev); 779 if (ret) { 780 rtw89_err(rtwdev, "write rf busy swsi\n"); 781 return false; 782 } 783 784 data &= RFREG_MASK; 785 mask &= RFREG_MASK; 786 787 if (mask != RFREG_MASK) { 788 b_msk_en = true; 789 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 790 mask); 791 bit_shift = __ffs(mask); 792 data = (data << bit_shift) & RFREG_MASK; 793 } 794 795 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 796 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 797 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 798 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 799 800 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 801 802 return true; 803 } 804 805 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 806 u32 addr, u32 mask, u32 data) 807 { 808 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 809 810 if (rf_path >= rtwdev->chip->rf_path_num) { 811 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 812 return false; 813 } 814 815 if (ad_sel) 816 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 817 else 818 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 819 } 820 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 821 822 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 823 { 824 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; 825 } 826 827 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 828 enum rtw89_phy_idx phy_idx) 829 { 830 const struct rtw89_chip_info *chip = rtwdev->chip; 831 832 chip->ops->bb_reset(rtwdev, phy_idx); 833 } 834 835 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 836 const struct rtw89_reg2_def *reg, 837 enum rtw89_rf_path rf_path, 838 void *extra_data) 839 { 840 if (reg->addr == 0xfe) 841 mdelay(50); 842 else if (reg->addr == 0xfd) 843 mdelay(5); 844 else if (reg->addr == 0xfc) 845 mdelay(1); 846 else if (reg->addr == 0xfb) 847 udelay(50); 848 else if (reg->addr == 0xfa) 849 udelay(5); 850 else if (reg->addr == 0xf9) 851 udelay(1); 852 else 853 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 854 } 855 856 union rtw89_phy_bb_gain_arg { 857 u32 addr; 858 struct { 859 union { 860 u8 type; 861 struct { 862 u8 rxsc_start:4; 863 u8 bw:4; 864 }; 865 }; 866 u8 path; 867 u8 gain_band; 868 u8 cfg_type; 869 }; 870 } __packed; 871 872 static void 873 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 874 union rtw89_phy_bb_gain_arg arg, u32 data) 875 { 876 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 877 u8 type = arg.type; 878 u8 path = arg.path; 879 u8 gband = arg.gain_band; 880 int i; 881 882 switch (type) { 883 case 0: 884 for (i = 0; i < 4; i++, data >>= 8) 885 gain->lna_gain[gband][path][i] = data & 0xff; 886 break; 887 case 1: 888 for (i = 4; i < 7; i++, data >>= 8) 889 gain->lna_gain[gband][path][i] = data & 0xff; 890 break; 891 case 2: 892 for (i = 0; i < 2; i++, data >>= 8) 893 gain->tia_gain[gband][path][i] = data & 0xff; 894 break; 895 default: 896 rtw89_warn(rtwdev, 897 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 898 arg.addr, data, type); 899 break; 900 } 901 } 902 903 enum rtw89_phy_bb_rxsc_start_idx { 904 RTW89_BB_RXSC_START_IDX_FULL = 0, 905 RTW89_BB_RXSC_START_IDX_20 = 1, 906 RTW89_BB_RXSC_START_IDX_20_1 = 5, 907 RTW89_BB_RXSC_START_IDX_40 = 9, 908 RTW89_BB_RXSC_START_IDX_80 = 13, 909 }; 910 911 static void 912 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 913 union rtw89_phy_bb_gain_arg arg, u32 data) 914 { 915 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 916 u8 rxsc_start = arg.rxsc_start; 917 u8 bw = arg.bw; 918 u8 path = arg.path; 919 u8 gband = arg.gain_band; 920 u8 rxsc; 921 s8 ofst; 922 int i; 923 924 switch (bw) { 925 case RTW89_CHANNEL_WIDTH_20: 926 gain->rpl_ofst_20[gband][path] = (s8)data; 927 break; 928 case RTW89_CHANNEL_WIDTH_40: 929 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 930 gain->rpl_ofst_40[gband][path][0] = (s8)data; 931 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 932 for (i = 0; i < 2; i++, data >>= 8) { 933 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 934 ofst = (s8)(data & 0xff); 935 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 936 } 937 } 938 break; 939 case RTW89_CHANNEL_WIDTH_80: 940 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 941 gain->rpl_ofst_80[gband][path][0] = (s8)data; 942 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 943 for (i = 0; i < 4; i++, data >>= 8) { 944 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 945 ofst = (s8)(data & 0xff); 946 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 947 } 948 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 949 for (i = 0; i < 2; i++, data >>= 8) { 950 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 951 ofst = (s8)(data & 0xff); 952 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 953 } 954 } 955 break; 956 case RTW89_CHANNEL_WIDTH_160: 957 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 958 gain->rpl_ofst_160[gband][path][0] = (s8)data; 959 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 960 for (i = 0; i < 4; i++, data >>= 8) { 961 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 962 ofst = (s8)(data & 0xff); 963 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 964 } 965 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 966 for (i = 0; i < 4; i++, data >>= 8) { 967 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 968 ofst = (s8)(data & 0xff); 969 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 970 } 971 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 972 for (i = 0; i < 4; i++, data >>= 8) { 973 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 974 ofst = (s8)(data & 0xff); 975 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 976 } 977 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 978 for (i = 0; i < 2; i++, data >>= 8) { 979 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 980 ofst = (s8)(data & 0xff); 981 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 982 } 983 } 984 break; 985 default: 986 rtw89_warn(rtwdev, 987 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 988 arg.addr, data, bw); 989 break; 990 } 991 } 992 993 static void 994 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 995 union rtw89_phy_bb_gain_arg arg, u32 data) 996 { 997 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 998 u8 type = arg.type; 999 u8 path = arg.path; 1000 u8 gband = arg.gain_band; 1001 int i; 1002 1003 switch (type) { 1004 case 0: 1005 for (i = 0; i < 4; i++, data >>= 8) 1006 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1007 break; 1008 case 1: 1009 for (i = 4; i < 7; i++, data >>= 8) 1010 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1011 break; 1012 default: 1013 rtw89_warn(rtwdev, 1014 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 1015 arg.addr, data, type); 1016 break; 1017 } 1018 } 1019 1020 static void 1021 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 1022 union rtw89_phy_bb_gain_arg arg, u32 data) 1023 { 1024 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 1025 u8 type = arg.type; 1026 u8 path = arg.path; 1027 u8 gband = arg.gain_band; 1028 int i; 1029 1030 switch (type) { 1031 case 0: 1032 for (i = 0; i < 4; i++, data >>= 8) 1033 gain->lna_op1db[gband][path][i] = data & 0xff; 1034 break; 1035 case 1: 1036 for (i = 4; i < 7; i++, data >>= 8) 1037 gain->lna_op1db[gband][path][i] = data & 0xff; 1038 break; 1039 case 2: 1040 for (i = 0; i < 4; i++, data >>= 8) 1041 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1042 break; 1043 case 3: 1044 for (i = 4; i < 8; i++, data >>= 8) 1045 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1046 break; 1047 default: 1048 rtw89_warn(rtwdev, 1049 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1050 arg.addr, data, type); 1051 break; 1052 } 1053 } 1054 1055 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev, 1056 const struct rtw89_reg2_def *reg, 1057 enum rtw89_rf_path rf_path, 1058 void *extra_data) 1059 { 1060 const struct rtw89_chip_info *chip = rtwdev->chip; 1061 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1062 struct rtw89_efuse *efuse = &rtwdev->efuse; 1063 1064 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1065 return; 1066 1067 if (arg.path >= chip->rf_path_num) 1068 return; 1069 1070 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1071 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1072 return; 1073 } 1074 1075 switch (arg.cfg_type) { 1076 case 0: 1077 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1078 break; 1079 case 1: 1080 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1081 break; 1082 case 2: 1083 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1084 break; 1085 case 3: 1086 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1087 break; 1088 case 4: 1089 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 1090 if (efuse->rfe_type < 50) 1091 break; 1092 fallthrough; 1093 default: 1094 rtw89_warn(rtwdev, 1095 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1096 arg.addr, reg->data, arg.cfg_type); 1097 break; 1098 } 1099 } 1100 1101 static void 1102 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1103 const struct rtw89_reg2_def *reg, 1104 enum rtw89_rf_path rf_path, 1105 struct rtw89_fw_h2c_rf_reg_info *info) 1106 { 1107 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1108 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1109 1110 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1111 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1112 rf_path, info->curr_idx); 1113 return; 1114 } 1115 1116 info->rtw89_phy_config_rf_h2c[page][idx] = 1117 cpu_to_le32((reg->addr << 20) | reg->data); 1118 info->curr_idx++; 1119 } 1120 1121 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1122 struct rtw89_fw_h2c_rf_reg_info *info) 1123 { 1124 u16 remain = info->curr_idx; 1125 u16 len = 0; 1126 u8 i; 1127 int ret = 0; 1128 1129 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1130 rtw89_warn(rtwdev, 1131 "rf reg h2c total len %d larger than %d\n", 1132 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1133 ret = -EINVAL; 1134 goto out; 1135 } 1136 1137 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1138 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1139 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1140 if (ret) 1141 goto out; 1142 } 1143 out: 1144 info->curr_idx = 0; 1145 1146 return ret; 1147 } 1148 1149 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev, 1150 const struct rtw89_reg2_def *reg, 1151 enum rtw89_rf_path rf_path, 1152 void *extra_data) 1153 { 1154 u32 addr = reg->addr; 1155 1156 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || 1157 addr == 0xfa || addr == 0xf9) 1158 return; 1159 1160 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100) 1161 return; 1162 1163 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1164 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1165 } 1166 1167 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1168 const struct rtw89_reg2_def *reg, 1169 enum rtw89_rf_path rf_path, 1170 void *extra_data) 1171 { 1172 if (reg->addr == 0xfe) { 1173 mdelay(50); 1174 } else if (reg->addr == 0xfd) { 1175 mdelay(5); 1176 } else if (reg->addr == 0xfc) { 1177 mdelay(1); 1178 } else if (reg->addr == 0xfb) { 1179 udelay(50); 1180 } else if (reg->addr == 0xfa) { 1181 udelay(5); 1182 } else if (reg->addr == 0xf9) { 1183 udelay(1); 1184 } else { 1185 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1186 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1187 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1188 } 1189 } 1190 1191 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1192 const struct rtw89_reg2_def *reg, 1193 enum rtw89_rf_path rf_path, 1194 void *extra_data) 1195 { 1196 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1197 1198 if (reg->addr < 0x100) 1199 return; 1200 1201 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1202 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1203 } 1204 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1205 1206 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1207 const struct rtw89_phy_table *table, 1208 u32 *headline_size, u32 *headline_idx, 1209 u8 rfe, u8 cv) 1210 { 1211 const struct rtw89_reg2_def *reg; 1212 u32 headline; 1213 u32 compare, target; 1214 u8 rfe_para, cv_para; 1215 u8 cv_max = 0; 1216 bool case_matched = false; 1217 u32 i; 1218 1219 for (i = 0; i < table->n_regs; i++) { 1220 reg = &table->regs[i]; 1221 headline = get_phy_headline(reg->addr); 1222 if (headline != PHY_HEADLINE_VALID) 1223 break; 1224 } 1225 *headline_size = i; 1226 if (*headline_size == 0) 1227 return 0; 1228 1229 /* case 1: RFE match, CV match */ 1230 compare = get_phy_compare(rfe, cv); 1231 for (i = 0; i < *headline_size; i++) { 1232 reg = &table->regs[i]; 1233 target = get_phy_target(reg->addr); 1234 if (target == compare) { 1235 *headline_idx = i; 1236 return 0; 1237 } 1238 } 1239 1240 /* case 2: RFE match, CV don't care */ 1241 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1242 for (i = 0; i < *headline_size; i++) { 1243 reg = &table->regs[i]; 1244 target = get_phy_target(reg->addr); 1245 if (target == compare) { 1246 *headline_idx = i; 1247 return 0; 1248 } 1249 } 1250 1251 /* case 3: RFE match, CV max in table */ 1252 for (i = 0; i < *headline_size; i++) { 1253 reg = &table->regs[i]; 1254 rfe_para = get_phy_cond_rfe(reg->addr); 1255 cv_para = get_phy_cond_cv(reg->addr); 1256 if (rfe_para == rfe) { 1257 if (cv_para >= cv_max) { 1258 cv_max = cv_para; 1259 *headline_idx = i; 1260 case_matched = true; 1261 } 1262 } 1263 } 1264 1265 if (case_matched) 1266 return 0; 1267 1268 /* case 4: RFE don't care, CV max in table */ 1269 for (i = 0; i < *headline_size; i++) { 1270 reg = &table->regs[i]; 1271 rfe_para = get_phy_cond_rfe(reg->addr); 1272 cv_para = get_phy_cond_cv(reg->addr); 1273 if (rfe_para == PHY_COND_DONT_CARE) { 1274 if (cv_para >= cv_max) { 1275 cv_max = cv_para; 1276 *headline_idx = i; 1277 case_matched = true; 1278 } 1279 } 1280 } 1281 1282 if (case_matched) 1283 return 0; 1284 1285 return -EINVAL; 1286 } 1287 1288 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1289 const struct rtw89_phy_table *table, 1290 void (*config)(struct rtw89_dev *rtwdev, 1291 const struct rtw89_reg2_def *reg, 1292 enum rtw89_rf_path rf_path, 1293 void *data), 1294 void *extra_data) 1295 { 1296 const struct rtw89_reg2_def *reg; 1297 enum rtw89_rf_path rf_path = table->rf_path; 1298 u8 rfe = rtwdev->efuse.rfe_type; 1299 u8 cv = rtwdev->hal.cv; 1300 u32 i; 1301 u32 headline_size = 0, headline_idx = 0; 1302 u32 target = 0, cfg_target; 1303 u8 cond; 1304 bool is_matched = true; 1305 bool target_found = false; 1306 int ret; 1307 1308 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1309 &headline_idx, rfe, cv); 1310 if (ret) { 1311 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1312 return; 1313 } 1314 1315 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1316 for (i = headline_size; i < table->n_regs; i++) { 1317 reg = &table->regs[i]; 1318 cond = get_phy_cond(reg->addr); 1319 switch (cond) { 1320 case PHY_COND_BRANCH_IF: 1321 case PHY_COND_BRANCH_ELIF: 1322 target = get_phy_target(reg->addr); 1323 break; 1324 case PHY_COND_BRANCH_ELSE: 1325 is_matched = false; 1326 if (!target_found) { 1327 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1328 reg->addr, reg->data); 1329 return; 1330 } 1331 break; 1332 case PHY_COND_BRANCH_END: 1333 is_matched = true; 1334 target_found = false; 1335 break; 1336 case PHY_COND_CHECK: 1337 if (target_found) { 1338 is_matched = false; 1339 break; 1340 } 1341 1342 if (target == cfg_target) { 1343 is_matched = true; 1344 target_found = true; 1345 } else { 1346 is_matched = false; 1347 target_found = false; 1348 } 1349 break; 1350 default: 1351 if (is_matched) 1352 config(rtwdev, reg, rf_path, extra_data); 1353 break; 1354 } 1355 } 1356 } 1357 1358 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1359 { 1360 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1361 const struct rtw89_chip_info *chip = rtwdev->chip; 1362 const struct rtw89_phy_table *bb_table; 1363 const struct rtw89_phy_table *bb_gain_table; 1364 1365 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table; 1366 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1367 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1368 1369 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table; 1370 if (bb_gain_table) 1371 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1372 rtw89_phy_config_bb_gain, NULL); 1373 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1374 } 1375 1376 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1377 { 1378 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1379 udelay(1); 1380 return rtw89_phy_read32(rtwdev, 0x8080); 1381 } 1382 1383 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio) 1384 { 1385 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1386 enum rtw89_rf_path rf_path, void *data); 1387 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1388 const struct rtw89_chip_info *chip = rtwdev->chip; 1389 const struct rtw89_phy_table *rf_table; 1390 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1391 u8 path; 1392 1393 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1394 if (!rf_reg_info) 1395 return; 1396 1397 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1398 rf_table = elm_info->rf_radio[path] ? 1399 elm_info->rf_radio[path] : chip->rf_table[path]; 1400 rf_reg_info->rf_path = rf_table->rf_path; 1401 if (noio) 1402 config = rtw89_phy_config_rf_reg_noio; 1403 else 1404 config = rf_table->config ? rf_table->config : 1405 rtw89_phy_config_rf_reg; 1406 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1407 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1408 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1409 rf_reg_info->rf_path); 1410 } 1411 kfree(rf_reg_info); 1412 } 1413 1414 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1415 { 1416 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1417 const struct rtw89_chip_info *chip = rtwdev->chip; 1418 const struct rtw89_phy_table *nctl_table; 1419 u32 val; 1420 int ret; 1421 1422 /* IQK/DPK clock & reset */ 1423 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3); 1424 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1); 1425 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000); 1426 if (chip->chip_id != RTL8851B) 1427 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000); 1428 if (chip->chip_id == RTL8852B) 1429 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2); 1430 1431 /* check 0x8080 */ 1432 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8); 1433 1434 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1435 1000, false, rtwdev); 1436 if (ret) 1437 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1438 1439 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table; 1440 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1441 1442 if (chip->nctl_post_table) 1443 rtw89_rfk_parser(rtwdev, chip->nctl_post_table); 1444 } 1445 1446 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1447 { 1448 u32 phy_page = addr >> 8; 1449 u32 ofst = 0; 1450 1451 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1452 return addr < 0x10000 ? 0x20000 : 0; 1453 1454 switch (phy_page) { 1455 case 0x6: 1456 case 0x7: 1457 case 0x8: 1458 case 0x9: 1459 case 0xa: 1460 case 0xb: 1461 case 0xc: 1462 case 0xd: 1463 case 0x19: 1464 case 0x1a: 1465 case 0x1b: 1466 ofst = 0x2000; 1467 break; 1468 default: 1469 /* warning case */ 1470 ofst = 0; 1471 break; 1472 } 1473 1474 if (phy_page >= 0x40 && phy_page <= 0x4f) 1475 ofst = 0x2000; 1476 1477 return ofst; 1478 } 1479 1480 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1481 u32 data, enum rtw89_phy_idx phy_idx) 1482 { 1483 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1484 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1485 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1486 } 1487 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1488 1489 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1490 enum rtw89_phy_idx phy_idx) 1491 { 1492 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1493 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1494 return rtw89_phy_read32_mask(rtwdev, addr, mask); 1495 } 1496 EXPORT_SYMBOL(rtw89_phy_read32_idx); 1497 1498 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1499 u32 val) 1500 { 1501 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1502 1503 if (!rtwdev->dbcc_en) 1504 return; 1505 1506 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1507 } 1508 1509 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1510 const struct rtw89_phy_reg3_tbl *tbl) 1511 { 1512 const struct rtw89_reg3_def *reg3; 1513 int i; 1514 1515 for (i = 0; i < tbl->size; i++) { 1516 reg3 = &tbl->reg3[i]; 1517 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1518 } 1519 } 1520 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1521 1522 static const u8 rtw89_rs_idx_num_ax[] = { 1523 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM, 1524 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM, 1525 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX, 1526 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM, 1527 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX, 1528 }; 1529 1530 static const u8 rtw89_rs_nss_num_ax[] = { 1531 [RTW89_RS_CCK] = 1, 1532 [RTW89_RS_OFDM] = 1, 1533 [RTW89_RS_MCS] = RTW89_NSS_NUM, 1534 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM, 1535 [RTW89_RS_OFFSET] = 1, 1536 }; 1537 1538 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, 1539 struct rtw89_txpwr_byrate *head, 1540 const struct rtw89_rate_desc *desc) 1541 { 1542 switch (desc->rs) { 1543 case RTW89_RS_CCK: 1544 return &head->cck[desc->idx]; 1545 case RTW89_RS_OFDM: 1546 return &head->ofdm[desc->idx]; 1547 case RTW89_RS_MCS: 1548 return &head->mcs[desc->ofdma][desc->nss][desc->idx]; 1549 case RTW89_RS_HEDCM: 1550 return &head->hedcm[desc->ofdma][desc->nss][desc->idx]; 1551 case RTW89_RS_OFFSET: 1552 return &head->offset[desc->idx]; 1553 default: 1554 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs); 1555 return &head->trap; 1556 } 1557 } 1558 1559 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1560 const struct rtw89_txpwr_table *tbl) 1561 { 1562 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1563 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1564 struct rtw89_txpwr_byrate *byr_head; 1565 struct rtw89_rate_desc desc = {}; 1566 s8 *byr; 1567 u32 data; 1568 u8 i; 1569 1570 for (; cfg < end; cfg++) { 1571 byr_head = &rtwdev->byr[cfg->band][0]; 1572 desc.rs = cfg->rs; 1573 desc.nss = cfg->nss; 1574 data = cfg->data; 1575 1576 for (i = 0; i < cfg->len; i++, data >>= 8) { 1577 desc.idx = cfg->shf + i; 1578 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc); 1579 *byr = data & 0xff; 1580 } 1581 } 1582 } 1583 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1584 1585 static s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf) 1586 { 1587 const struct rtw89_chip_info *chip = rtwdev->chip; 1588 1589 return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac); 1590 } 1591 1592 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, 1593 const struct rtw89_rate_desc *rate_desc) 1594 { 1595 struct rtw89_txpwr_byrate *byr_head; 1596 s8 *byr; 1597 1598 if (rate_desc->rs == RTW89_RS_CCK) 1599 band = RTW89_BAND_2G; 1600 1601 byr_head = &rtwdev->byr[band][bw]; 1602 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc); 1603 1604 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr); 1605 } 1606 1607 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1608 { 1609 switch (channel_6g) { 1610 case 1 ... 29: 1611 return (channel_6g - 1) / 2; 1612 case 33 ... 61: 1613 return (channel_6g - 3) / 2; 1614 case 65 ... 93: 1615 return (channel_6g - 5) / 2; 1616 case 97 ... 125: 1617 return (channel_6g - 7) / 2; 1618 case 129 ... 157: 1619 return (channel_6g - 9) / 2; 1620 case 161 ... 189: 1621 return (channel_6g - 11) / 2; 1622 case 193 ... 221: 1623 return (channel_6g - 13) / 2; 1624 case 225 ... 253: 1625 return (channel_6g - 15) / 2; 1626 default: 1627 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1628 return 0; 1629 } 1630 } 1631 1632 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1633 { 1634 if (band == RTW89_BAND_6G) 1635 return rtw89_channel_6g_to_idx(rtwdev, channel); 1636 1637 switch (channel) { 1638 case 1 ... 14: 1639 return channel - 1; 1640 case 36 ... 64: 1641 return (channel - 36) / 2; 1642 case 100 ... 144: 1643 return ((channel - 100) / 2) + 15; 1644 case 149 ... 177: 1645 return ((channel - 149) / 2) + 38; 1646 default: 1647 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1648 return 0; 1649 } 1650 } 1651 1652 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1653 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1654 { 1655 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1656 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 1657 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 1658 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 1659 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1660 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 1661 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 1662 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1663 u8 regd = rtw89_regd_get(rtwdev, band); 1664 u8 reg6 = regulatory->reg_6ghz_power; 1665 s8 lmt = 0, sar; 1666 1667 switch (band) { 1668 case RTW89_BAND_2G: 1669 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1670 if (lmt) 1671 break; 1672 1673 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1674 break; 1675 case RTW89_BAND_5G: 1676 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1677 if (lmt) 1678 break; 1679 1680 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1681 break; 1682 case RTW89_BAND_6G: 1683 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx]; 1684 if (lmt) 1685 break; 1686 1687 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW] 1688 [RTW89_REG_6GHZ_POWER_DFLT] 1689 [ch_idx]; 1690 break; 1691 default: 1692 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1693 return 0; 1694 } 1695 1696 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt); 1697 sar = rtw89_query_sar(rtwdev, freq); 1698 1699 return min(lmt, sar); 1700 } 1701 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1702 1703 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 1704 do { \ 1705 u8 __i; \ 1706 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1707 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1708 band, \ 1709 bw, ntx, \ 1710 rs, __i, \ 1711 (ch)); \ 1712 } while (0) 1713 1714 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev, 1715 struct rtw89_txpwr_limit_ax *lmt, 1716 u8 band, u8 ntx, u8 ch) 1717 { 1718 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1719 ntx, RTW89_RS_CCK, ch); 1720 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1721 ntx, RTW89_RS_CCK, ch); 1722 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1723 ntx, RTW89_RS_OFDM, ch); 1724 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1725 RTW89_CHANNEL_WIDTH_20, 1726 ntx, RTW89_RS_MCS, ch); 1727 } 1728 1729 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev, 1730 struct rtw89_txpwr_limit_ax *lmt, 1731 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1732 { 1733 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1734 ntx, RTW89_RS_CCK, ch - 2); 1735 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1736 ntx, RTW89_RS_CCK, ch); 1737 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1738 ntx, RTW89_RS_OFDM, pri_ch); 1739 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1740 RTW89_CHANNEL_WIDTH_20, 1741 ntx, RTW89_RS_MCS, ch - 2); 1742 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1743 RTW89_CHANNEL_WIDTH_20, 1744 ntx, RTW89_RS_MCS, ch + 2); 1745 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1746 RTW89_CHANNEL_WIDTH_40, 1747 ntx, RTW89_RS_MCS, ch); 1748 } 1749 1750 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev, 1751 struct rtw89_txpwr_limit_ax *lmt, 1752 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1753 { 1754 s8 val_0p5_n[RTW89_BF_NUM]; 1755 s8 val_0p5_p[RTW89_BF_NUM]; 1756 u8 i; 1757 1758 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1759 ntx, RTW89_RS_OFDM, pri_ch); 1760 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1761 RTW89_CHANNEL_WIDTH_20, 1762 ntx, RTW89_RS_MCS, ch - 6); 1763 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1764 RTW89_CHANNEL_WIDTH_20, 1765 ntx, RTW89_RS_MCS, ch - 2); 1766 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1767 RTW89_CHANNEL_WIDTH_20, 1768 ntx, RTW89_RS_MCS, ch + 2); 1769 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1770 RTW89_CHANNEL_WIDTH_20, 1771 ntx, RTW89_RS_MCS, ch + 6); 1772 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1773 RTW89_CHANNEL_WIDTH_40, 1774 ntx, RTW89_RS_MCS, ch - 4); 1775 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1776 RTW89_CHANNEL_WIDTH_40, 1777 ntx, RTW89_RS_MCS, ch + 4); 1778 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1779 RTW89_CHANNEL_WIDTH_80, 1780 ntx, RTW89_RS_MCS, ch); 1781 1782 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1783 ntx, RTW89_RS_MCS, ch - 4); 1784 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1785 ntx, RTW89_RS_MCS, ch + 4); 1786 1787 for (i = 0; i < RTW89_BF_NUM; i++) 1788 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1789 } 1790 1791 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev, 1792 struct rtw89_txpwr_limit_ax *lmt, 1793 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1794 { 1795 s8 val_0p5_n[RTW89_BF_NUM]; 1796 s8 val_0p5_p[RTW89_BF_NUM]; 1797 s8 val_2p5_n[RTW89_BF_NUM]; 1798 s8 val_2p5_p[RTW89_BF_NUM]; 1799 u8 i; 1800 1801 /* fill ofdm section */ 1802 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1803 ntx, RTW89_RS_OFDM, pri_ch); 1804 1805 /* fill mcs 20m section */ 1806 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1807 RTW89_CHANNEL_WIDTH_20, 1808 ntx, RTW89_RS_MCS, ch - 14); 1809 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1810 RTW89_CHANNEL_WIDTH_20, 1811 ntx, RTW89_RS_MCS, ch - 10); 1812 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1813 RTW89_CHANNEL_WIDTH_20, 1814 ntx, RTW89_RS_MCS, ch - 6); 1815 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1816 RTW89_CHANNEL_WIDTH_20, 1817 ntx, RTW89_RS_MCS, ch - 2); 1818 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 1819 RTW89_CHANNEL_WIDTH_20, 1820 ntx, RTW89_RS_MCS, ch + 2); 1821 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 1822 RTW89_CHANNEL_WIDTH_20, 1823 ntx, RTW89_RS_MCS, ch + 6); 1824 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 1825 RTW89_CHANNEL_WIDTH_20, 1826 ntx, RTW89_RS_MCS, ch + 10); 1827 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 1828 RTW89_CHANNEL_WIDTH_20, 1829 ntx, RTW89_RS_MCS, ch + 14); 1830 1831 /* fill mcs 40m section */ 1832 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1833 RTW89_CHANNEL_WIDTH_40, 1834 ntx, RTW89_RS_MCS, ch - 12); 1835 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1836 RTW89_CHANNEL_WIDTH_40, 1837 ntx, RTW89_RS_MCS, ch - 4); 1838 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 1839 RTW89_CHANNEL_WIDTH_40, 1840 ntx, RTW89_RS_MCS, ch + 4); 1841 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 1842 RTW89_CHANNEL_WIDTH_40, 1843 ntx, RTW89_RS_MCS, ch + 12); 1844 1845 /* fill mcs 80m section */ 1846 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1847 RTW89_CHANNEL_WIDTH_80, 1848 ntx, RTW89_RS_MCS, ch - 8); 1849 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 1850 RTW89_CHANNEL_WIDTH_80, 1851 ntx, RTW89_RS_MCS, ch + 8); 1852 1853 /* fill mcs 160m section */ 1854 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 1855 RTW89_CHANNEL_WIDTH_160, 1856 ntx, RTW89_RS_MCS, ch); 1857 1858 /* fill mcs 40m 0p5 section */ 1859 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1860 ntx, RTW89_RS_MCS, ch - 4); 1861 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1862 ntx, RTW89_RS_MCS, ch + 4); 1863 1864 for (i = 0; i < RTW89_BF_NUM; i++) 1865 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1866 1867 /* fill mcs 40m 2p5 section */ 1868 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 1869 ntx, RTW89_RS_MCS, ch - 8); 1870 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 1871 ntx, RTW89_RS_MCS, ch + 8); 1872 1873 for (i = 0; i < RTW89_BF_NUM; i++) 1874 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1875 } 1876 1877 static 1878 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev, 1879 const struct rtw89_chan *chan, 1880 struct rtw89_txpwr_limit_ax *lmt, 1881 u8 ntx) 1882 { 1883 u8 band = chan->band_type; 1884 u8 pri_ch = chan->primary_channel; 1885 u8 ch = chan->channel; 1886 u8 bw = chan->band_width; 1887 1888 memset(lmt, 0, sizeof(*lmt)); 1889 1890 switch (bw) { 1891 case RTW89_CHANNEL_WIDTH_20: 1892 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch); 1893 break; 1894 case RTW89_CHANNEL_WIDTH_40: 1895 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch, 1896 pri_ch); 1897 break; 1898 case RTW89_CHANNEL_WIDTH_80: 1899 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch, 1900 pri_ch); 1901 break; 1902 case RTW89_CHANNEL_WIDTH_160: 1903 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch, 1904 pri_ch); 1905 break; 1906 } 1907 } 1908 1909 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 1910 u8 ru, u8 ntx, u8 ch) 1911 { 1912 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1913 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 1914 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 1915 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 1916 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1917 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 1918 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 1919 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1920 u8 regd = rtw89_regd_get(rtwdev, band); 1921 u8 reg6 = regulatory->reg_6ghz_power; 1922 s8 lmt_ru = 0, sar; 1923 1924 switch (band) { 1925 case RTW89_BAND_2G: 1926 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 1927 if (lmt_ru) 1928 break; 1929 1930 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 1931 break; 1932 case RTW89_BAND_5G: 1933 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 1934 if (lmt_ru) 1935 break; 1936 1937 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 1938 break; 1939 case RTW89_BAND_6G: 1940 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx]; 1941 if (lmt_ru) 1942 break; 1943 1944 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW] 1945 [RTW89_REG_6GHZ_POWER_DFLT] 1946 [ch_idx]; 1947 break; 1948 default: 1949 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1950 return 0; 1951 } 1952 1953 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1954 sar = rtw89_query_sar(rtwdev, freq); 1955 1956 return min(lmt_ru, sar); 1957 } 1958 1959 static void 1960 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev, 1961 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 1962 u8 band, u8 ntx, u8 ch) 1963 { 1964 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1965 RTW89_RU26, 1966 ntx, ch); 1967 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1968 RTW89_RU52, 1969 ntx, ch); 1970 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1971 RTW89_RU106, 1972 ntx, ch); 1973 } 1974 1975 static void 1976 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev, 1977 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 1978 u8 band, u8 ntx, u8 ch) 1979 { 1980 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1981 RTW89_RU26, 1982 ntx, ch - 2); 1983 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1984 RTW89_RU26, 1985 ntx, ch + 2); 1986 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1987 RTW89_RU52, 1988 ntx, ch - 2); 1989 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1990 RTW89_RU52, 1991 ntx, ch + 2); 1992 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1993 RTW89_RU106, 1994 ntx, ch - 2); 1995 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1996 RTW89_RU106, 1997 ntx, ch + 2); 1998 } 1999 2000 static void 2001 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev, 2002 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2003 u8 band, u8 ntx, u8 ch) 2004 { 2005 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2006 RTW89_RU26, 2007 ntx, ch - 6); 2008 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2009 RTW89_RU26, 2010 ntx, ch - 2); 2011 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2012 RTW89_RU26, 2013 ntx, ch + 2); 2014 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2015 RTW89_RU26, 2016 ntx, ch + 6); 2017 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2018 RTW89_RU52, 2019 ntx, ch - 6); 2020 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2021 RTW89_RU52, 2022 ntx, ch - 2); 2023 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2024 RTW89_RU52, 2025 ntx, ch + 2); 2026 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2027 RTW89_RU52, 2028 ntx, ch + 6); 2029 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2030 RTW89_RU106, 2031 ntx, ch - 6); 2032 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2033 RTW89_RU106, 2034 ntx, ch - 2); 2035 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2036 RTW89_RU106, 2037 ntx, ch + 2); 2038 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2039 RTW89_RU106, 2040 ntx, ch + 6); 2041 } 2042 2043 static void 2044 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev, 2045 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2046 u8 band, u8 ntx, u8 ch) 2047 { 2048 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 2049 int i; 2050 2051 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX); 2052 for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) { 2053 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2054 RTW89_RU26, 2055 ntx, 2056 ch + ofst[i]); 2057 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2058 RTW89_RU52, 2059 ntx, 2060 ch + ofst[i]); 2061 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2062 RTW89_RU106, 2063 ntx, 2064 ch + ofst[i]); 2065 } 2066 } 2067 2068 static 2069 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2070 const struct rtw89_chan *chan, 2071 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2072 u8 ntx) 2073 { 2074 u8 band = chan->band_type; 2075 u8 ch = chan->channel; 2076 u8 bw = chan->band_width; 2077 2078 memset(lmt_ru, 0, sizeof(*lmt_ru)); 2079 2080 switch (bw) { 2081 case RTW89_CHANNEL_WIDTH_20: 2082 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx, 2083 ch); 2084 break; 2085 case RTW89_CHANNEL_WIDTH_40: 2086 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx, 2087 ch); 2088 break; 2089 case RTW89_CHANNEL_WIDTH_80: 2090 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx, 2091 ch); 2092 break; 2093 case RTW89_CHANNEL_WIDTH_160: 2094 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx, 2095 ch); 2096 break; 2097 } 2098 } 2099 2100 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev, 2101 const struct rtw89_chan *chan, 2102 enum rtw89_phy_idx phy_idx) 2103 { 2104 u8 max_nss_num = rtwdev->chip->rf_path_num; 2105 static const u8 rs[] = { 2106 RTW89_RS_CCK, 2107 RTW89_RS_OFDM, 2108 RTW89_RS_MCS, 2109 RTW89_RS_HEDCM, 2110 }; 2111 struct rtw89_rate_desc cur = {}; 2112 u8 band = chan->band_type; 2113 u8 ch = chan->channel; 2114 u32 addr, val; 2115 s8 v[4] = {}; 2116 u8 i; 2117 2118 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2119 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 2120 2121 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4); 2122 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4); 2123 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4); 2124 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4); 2125 2126 addr = R_AX_PWR_BY_RATE; 2127 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) { 2128 for (i = 0; i < ARRAY_SIZE(rs); i++) { 2129 if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]]) 2130 continue; 2131 2132 cur.rs = rs[i]; 2133 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]]; 2134 cur.idx++) { 2135 v[cur.idx % 4] = 2136 rtw89_phy_read_txpwr_byrate(rtwdev, 2137 band, 0, 2138 &cur); 2139 2140 if ((cur.idx + 1) % 4) 2141 continue; 2142 2143 val = FIELD_PREP(GENMASK(7, 0), v[0]) | 2144 FIELD_PREP(GENMASK(15, 8), v[1]) | 2145 FIELD_PREP(GENMASK(23, 16), v[2]) | 2146 FIELD_PREP(GENMASK(31, 24), v[3]); 2147 2148 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 2149 val); 2150 addr += 4; 2151 } 2152 } 2153 } 2154 } 2155 2156 static 2157 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev, 2158 const struct rtw89_chan *chan, 2159 enum rtw89_phy_idx phy_idx) 2160 { 2161 struct rtw89_rate_desc desc = { 2162 .nss = RTW89_NSS_1, 2163 .rs = RTW89_RS_OFFSET, 2164 }; 2165 u8 band = chan->band_type; 2166 s8 v[RTW89_RATE_OFFSET_NUM_AX] = {}; 2167 u32 val; 2168 2169 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 2170 2171 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_AX; desc.idx++) 2172 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc); 2173 2174 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM_AX != 5); 2175 val = FIELD_PREP(GENMASK(3, 0), v[0]) | 2176 FIELD_PREP(GENMASK(7, 4), v[1]) | 2177 FIELD_PREP(GENMASK(11, 8), v[2]) | 2178 FIELD_PREP(GENMASK(15, 12), v[3]) | 2179 FIELD_PREP(GENMASK(19, 16), v[4]); 2180 2181 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 2182 GENMASK(19, 0), val); 2183 } 2184 2185 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev, 2186 const struct rtw89_chan *chan, 2187 enum rtw89_phy_idx phy_idx) 2188 { 2189 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2190 struct rtw89_txpwr_limit_ax lmt; 2191 u8 ch = chan->channel; 2192 u8 bw = chan->band_width; 2193 const s8 *ptr; 2194 u32 addr, val; 2195 u8 i, j; 2196 2197 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2198 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 2199 2200 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ax) != 2201 RTW89_TXPWR_LMT_PAGE_SIZE_AX); 2202 2203 addr = R_AX_PWR_LMT; 2204 for (i = 0; i < max_ntx_num; i++) { 2205 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i); 2206 2207 ptr = (s8 *)&lmt; 2208 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_AX; 2209 j += 4, addr += 4, ptr += 4) { 2210 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2211 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2212 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2213 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2214 2215 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2216 } 2217 } 2218 } 2219 2220 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2221 const struct rtw89_chan *chan, 2222 enum rtw89_phy_idx phy_idx) 2223 { 2224 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2225 struct rtw89_txpwr_limit_ru_ax lmt_ru; 2226 u8 ch = chan->channel; 2227 u8 bw = chan->band_width; 2228 const s8 *ptr; 2229 u32 addr, val; 2230 u8 i, j; 2231 2232 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2233 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 2234 2235 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) != 2236 RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX); 2237 2238 addr = R_AX_PWR_RU_LMT; 2239 for (i = 0; i < max_ntx_num; i++) { 2240 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i); 2241 2242 ptr = (s8 *)&lmt_ru; 2243 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX; 2244 j += 4, addr += 4, ptr += 4) { 2245 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2246 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2247 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2248 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2249 2250 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2251 } 2252 } 2253 } 2254 2255 struct rtw89_phy_iter_ra_data { 2256 struct rtw89_dev *rtwdev; 2257 struct sk_buff *c2h; 2258 }; 2259 2260 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 2261 { 2262 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 2263 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2264 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2265 const struct rtw89_c2h_ra_rpt *c2h = 2266 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data; 2267 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 2268 const struct rtw89_chip_info *chip = rtwdev->chip; 2269 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE; 2270 u8 mode, rate, bw, giltf, mac_id; 2271 u16 legacy_bitrate; 2272 bool valid; 2273 u8 mcs = 0; 2274 u8 t; 2275 2276 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID); 2277 if (mac_id != rtwsta->mac_id) 2278 return; 2279 2280 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS); 2281 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW); 2282 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF); 2283 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL); 2284 2285 if (format_v1) { 2286 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7); 2287 rate |= u8_encode_bits(t, BIT(7)); 2288 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2); 2289 bw |= u8_encode_bits(t, BIT(2)); 2290 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2); 2291 mode |= u8_encode_bits(t, BIT(2)); 2292 } 2293 2294 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2295 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2296 if (!valid) 2297 return; 2298 } 2299 2300 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2301 2302 switch (mode) { 2303 case RTW89_RA_RPT_MODE_LEGACY: 2304 ra_report->txrate.legacy = legacy_bitrate; 2305 break; 2306 case RTW89_RA_RPT_MODE_HT: 2307 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2308 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2309 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2310 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2311 else 2312 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2313 ra_report->txrate.mcs = rate; 2314 if (giltf) 2315 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2316 mcs = ra_report->txrate.mcs & 0x07; 2317 break; 2318 case RTW89_RA_RPT_MODE_VHT: 2319 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2320 ra_report->txrate.mcs = format_v1 ? 2321 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2322 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2323 ra_report->txrate.nss = format_v1 ? 2324 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2325 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2326 if (giltf) 2327 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2328 mcs = ra_report->txrate.mcs; 2329 break; 2330 case RTW89_RA_RPT_MODE_HE: 2331 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2332 ra_report->txrate.mcs = format_v1 ? 2333 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2334 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2335 ra_report->txrate.nss = format_v1 ? 2336 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2337 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2338 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2339 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2340 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2341 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2342 else 2343 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2344 mcs = ra_report->txrate.mcs; 2345 break; 2346 } 2347 2348 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2349 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2350 ra_report->hw_rate = format_v1 ? 2351 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) | 2352 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) : 2353 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) | 2354 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL); 2355 ra_report->might_fallback_legacy = mcs <= 2; 2356 sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2357 rtwsta->max_agg_wait = sta->deflink.agg.max_rc_amsdu_len / 1500 - 1; 2358 } 2359 2360 static void 2361 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2362 { 2363 struct rtw89_phy_iter_ra_data ra_data; 2364 2365 ra_data.rtwdev = rtwdev; 2366 ra_data.c2h = c2h; 2367 ieee80211_iterate_stations_atomic(rtwdev->hw, 2368 rtw89_phy_c2h_ra_rpt_iter, 2369 &ra_data); 2370 } 2371 2372 static 2373 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2374 struct sk_buff *c2h, u32 len) = { 2375 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2376 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2377 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2378 }; 2379 2380 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2381 u32 len, u8 class, u8 func) 2382 { 2383 void (*handler)(struct rtw89_dev *rtwdev, 2384 struct sk_buff *c2h, u32 len) = NULL; 2385 2386 switch (class) { 2387 case RTW89_PHY_C2H_CLASS_RA: 2388 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 2389 handler = rtw89_phy_c2h_ra_handler[func]; 2390 break; 2391 case RTW89_PHY_C2H_CLASS_DM: 2392 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY) 2393 return; 2394 fallthrough; 2395 default: 2396 rtw89_info(rtwdev, "c2h class %d not support\n", class); 2397 return; 2398 } 2399 if (!handler) { 2400 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 2401 func); 2402 return; 2403 } 2404 handler(rtwdev, skb, len); 2405 } 2406 2407 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 2408 { 2409 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 2410 u32 reg_mask; 2411 2412 if (sc_xo) 2413 reg_mask = xtal->sc_xo_mask; 2414 else 2415 reg_mask = xtal->sc_xi_mask; 2416 2417 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask); 2418 } 2419 2420 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 2421 u8 val) 2422 { 2423 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 2424 u32 reg_mask; 2425 2426 if (sc_xo) 2427 reg_mask = xtal->sc_xo_mask; 2428 else 2429 reg_mask = xtal->sc_xi_mask; 2430 2431 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val); 2432 } 2433 2434 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 2435 u8 crystal_cap, bool force) 2436 { 2437 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2438 const struct rtw89_chip_info *chip = rtwdev->chip; 2439 u8 sc_xi_val, sc_xo_val; 2440 2441 if (!force && cfo->crystal_cap == crystal_cap) 2442 return; 2443 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 2444 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) { 2445 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 2446 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 2447 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 2448 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 2449 } else { 2450 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 2451 crystal_cap, XTAL_SC_XO_MASK); 2452 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 2453 crystal_cap, XTAL_SC_XI_MASK); 2454 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 2455 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 2456 } 2457 cfo->crystal_cap = sc_xi_val; 2458 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 2459 2460 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 2461 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 2462 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 2463 cfo->x_cap_ofst); 2464 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 2465 } 2466 2467 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 2468 { 2469 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2470 u8 cap; 2471 2472 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 2473 cfo->is_adjust = false; 2474 if (cfo->crystal_cap == cfo->def_x_cap) 2475 return; 2476 cap = cfo->crystal_cap; 2477 cap += (cap > cfo->def_x_cap ? -1 : 1); 2478 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 2479 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2480 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 2481 cfo->def_x_cap); 2482 } 2483 2484 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 2485 { 2486 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 2487 bool is_linked = rtwdev->total_sta_assoc > 0; 2488 s32 cfo_avg_312; 2489 s32 dcfo_comp_val; 2490 int sign; 2491 2492 if (!is_linked) { 2493 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 2494 is_linked); 2495 return; 2496 } 2497 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 2498 if (curr_cfo == 0) 2499 return; 2500 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 2501 sign = curr_cfo > 0 ? 1 : -1; 2502 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val; 2503 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312); 2504 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2505 cfo_avg_312 = -cfo_avg_312; 2506 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 2507 cfo_avg_312); 2508 } 2509 2510 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 2511 { 2512 const struct rtw89_chip_info *chip = rtwdev->chip; 2513 2514 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 2515 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 2516 2517 if (chip->cfo_hw_comp) 2518 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2, 2519 B_AX_PWR_UL_CFO_MASK, 0x6); 2520 else 2521 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 2522 } 2523 2524 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 2525 { 2526 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2527 struct rtw89_efuse *efuse = &rtwdev->efuse; 2528 2529 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 2530 cfo->crystal_cap = cfo->crystal_cap_default; 2531 cfo->def_x_cap = cfo->crystal_cap; 2532 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 2533 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 2534 cfo->is_adjust = false; 2535 cfo->divergence_lock_en = false; 2536 cfo->x_cap_ofst = 0; 2537 cfo->lock_cnt = 0; 2538 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 2539 cfo->apply_compensation = false; 2540 cfo->residual_cfo_acc = 0; 2541 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 2542 cfo->crystal_cap_default); 2543 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 2544 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 2545 rtw89_dcfo_comp_init(rtwdev); 2546 cfo->cfo_timer_ms = 2000; 2547 cfo->cfo_trig_by_timer_en = false; 2548 cfo->phy_cfo_trk_cnt = 0; 2549 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2550 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 2551 } 2552 2553 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 2554 s32 curr_cfo) 2555 { 2556 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2557 s8 crystal_cap = cfo->crystal_cap; 2558 s32 cfo_abs = abs(curr_cfo); 2559 int sign; 2560 2561 if (!cfo->is_adjust) { 2562 if (cfo_abs > CFO_TRK_ENABLE_TH) 2563 cfo->is_adjust = true; 2564 } else { 2565 if (cfo_abs < CFO_TRK_STOP_TH) 2566 cfo->is_adjust = false; 2567 } 2568 if (!cfo->is_adjust) { 2569 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 2570 return; 2571 } 2572 sign = curr_cfo > 0 ? 1 : -1; 2573 if (cfo_abs > CFO_TRK_STOP_TH_4) 2574 crystal_cap += 7 * sign; 2575 else if (cfo_abs > CFO_TRK_STOP_TH_3) 2576 crystal_cap += 5 * sign; 2577 else if (cfo_abs > CFO_TRK_STOP_TH_2) 2578 crystal_cap += 3 * sign; 2579 else if (cfo_abs > CFO_TRK_STOP_TH_1) 2580 crystal_cap += 1 * sign; 2581 else 2582 return; 2583 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 2584 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2585 "X_cap{Curr,Default}={0x%x,0x%x}\n", 2586 cfo->crystal_cap, cfo->def_x_cap); 2587 } 2588 2589 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 2590 { 2591 const struct rtw89_chip_info *chip = rtwdev->chip; 2592 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2593 s32 cfo_khz_all = 0; 2594 s32 cfo_cnt_all = 0; 2595 s32 cfo_all_avg = 0; 2596 u8 i; 2597 2598 if (rtwdev->total_sta_assoc != 1) 2599 return 0; 2600 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 2601 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2602 if (cfo->cfo_cnt[i] == 0) 2603 continue; 2604 cfo_khz_all += cfo->cfo_tail[i]; 2605 cfo_cnt_all += cfo->cfo_cnt[i]; 2606 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 2607 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2608 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft, 2609 cfo_cnt_all); 2610 } 2611 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2612 "CFO track for macid = %d\n", i); 2613 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2614 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 2615 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 2616 return cfo_all_avg; 2617 } 2618 2619 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 2620 { 2621 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2622 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2623 s32 target_cfo = 0; 2624 s32 cfo_khz_all = 0; 2625 s32 cfo_khz_all_tp_wgt = 0; 2626 s32 cfo_avg = 0; 2627 s32 max_cfo_lb = BIT(31); 2628 s32 min_cfo_ub = GENMASK(30, 0); 2629 u16 cfo_cnt_all = 0; 2630 u8 active_entry_cnt = 0; 2631 u8 sta_cnt = 0; 2632 u32 tp_all = 0; 2633 u8 i; 2634 u8 cfo_tol = 0; 2635 2636 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 2637 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 2638 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 2639 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2640 if (cfo->cfo_cnt[i] == 0) 2641 continue; 2642 cfo_khz_all += cfo->cfo_tail[i]; 2643 cfo_cnt_all += cfo->cfo_cnt[i]; 2644 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 2645 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2646 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 2647 cfo_khz_all, cfo_cnt_all, cfo_avg); 2648 target_cfo = cfo_avg; 2649 } 2650 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 2651 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 2652 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2653 if (cfo->cfo_cnt[i] == 0) 2654 continue; 2655 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2656 (s32)cfo->cfo_cnt[i]); 2657 cfo_khz_all += cfo->cfo_avg[i]; 2658 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2659 "Macid=%d, cfo_avg=%d\n", i, 2660 cfo->cfo_avg[i]); 2661 } 2662 sta_cnt = rtwdev->total_sta_assoc; 2663 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 2664 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2665 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 2666 cfo_khz_all, sta_cnt, cfo_avg); 2667 target_cfo = cfo_avg; 2668 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 2669 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 2670 cfo_tol = cfo->sta_cfo_tolerance; 2671 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2672 sta_cnt++; 2673 if (cfo->cfo_cnt[i] != 0) { 2674 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2675 (s32)cfo->cfo_cnt[i]); 2676 active_entry_cnt++; 2677 } else { 2678 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 2679 } 2680 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 2681 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 2682 cfo_khz_all += cfo->cfo_avg[i]; 2683 /* need tp for each entry */ 2684 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2685 "[%d] cfo_avg=%d, tp=tbd\n", 2686 i, cfo->cfo_avg[i]); 2687 if (sta_cnt >= rtwdev->total_sta_assoc) 2688 break; 2689 } 2690 tp_all = stats->rx_throughput; /* need tp for each entry */ 2691 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 2692 2693 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 2694 sta_cnt); 2695 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 2696 active_entry_cnt); 2697 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2698 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 2699 cfo_khz_all_tp_wgt, cfo_avg); 2700 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 2701 max_cfo_lb, min_cfo_ub); 2702 if (max_cfo_lb <= min_cfo_ub) { 2703 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2704 "cfo win_size=%d\n", 2705 min_cfo_ub - max_cfo_lb); 2706 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 2707 } else { 2708 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2709 "No intersection of cfo tolerance windows\n"); 2710 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 2711 } 2712 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 2713 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2714 } 2715 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 2716 return target_cfo; 2717 } 2718 2719 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 2720 { 2721 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2722 2723 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 2724 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 2725 cfo->packet_count = 0; 2726 cfo->packet_count_pre = 0; 2727 cfo->cfo_avg_pre = 0; 2728 } 2729 2730 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 2731 { 2732 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2733 s32 new_cfo = 0; 2734 bool x_cap_update = false; 2735 u8 pre_x_cap = cfo->crystal_cap; 2736 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 2737 2738 cfo->dcfo_avg = 0; 2739 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 2740 rtwdev->total_sta_assoc); 2741 if (rtwdev->total_sta_assoc == 0) { 2742 rtw89_phy_cfo_reset(rtwdev); 2743 return; 2744 } 2745 if (cfo->packet_count == 0) { 2746 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 2747 return; 2748 } 2749 if (cfo->packet_count == cfo->packet_count_pre) { 2750 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 2751 return; 2752 } 2753 if (rtwdev->total_sta_assoc == 1) 2754 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 2755 else 2756 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 2757 if (new_cfo == 0) { 2758 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2759 return; 2760 } 2761 if (cfo->divergence_lock_en) { 2762 cfo->lock_cnt++; 2763 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 2764 cfo->divergence_lock_en = false; 2765 cfo->lock_cnt = 0; 2766 } else { 2767 rtw89_phy_cfo_reset(rtwdev); 2768 } 2769 return; 2770 } 2771 if (cfo->crystal_cap >= cfo->x_cap_ub || 2772 cfo->crystal_cap <= cfo->x_cap_lb) { 2773 cfo->divergence_lock_en = true; 2774 rtw89_phy_cfo_reset(rtwdev); 2775 return; 2776 } 2777 2778 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 2779 cfo->cfo_avg_pre = new_cfo; 2780 cfo->dcfo_avg_pre = cfo->dcfo_avg; 2781 x_cap_update = cfo->crystal_cap != pre_x_cap; 2782 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 2783 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 2784 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 2785 cfo->x_cap_ofst); 2786 if (x_cap_update) { 2787 if (cfo->dcfo_avg > 0) 2788 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 2789 else 2790 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 2791 } 2792 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg); 2793 rtw89_phy_cfo_statistics_reset(rtwdev); 2794 } 2795 2796 void rtw89_phy_cfo_track_work(struct work_struct *work) 2797 { 2798 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2799 cfo_track_work.work); 2800 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2801 2802 mutex_lock(&rtwdev->mutex); 2803 if (!cfo->cfo_trig_by_timer_en) 2804 goto out; 2805 rtw89_leave_ps_mode(rtwdev); 2806 rtw89_phy_cfo_dm(rtwdev); 2807 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2808 msecs_to_jiffies(cfo->cfo_timer_ms)); 2809 out: 2810 mutex_unlock(&rtwdev->mutex); 2811 } 2812 2813 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 2814 { 2815 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2816 2817 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2818 msecs_to_jiffies(cfo->cfo_timer_ms)); 2819 } 2820 2821 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 2822 { 2823 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2824 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2825 bool is_ul_ofdma = false, ofdma_acc_en = false; 2826 2827 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 2828 is_ul_ofdma = true; 2829 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 2830 is_ul_ofdma) 2831 ofdma_acc_en = true; 2832 2833 switch (cfo->phy_cfo_status) { 2834 case RTW89_PHY_DCFO_STATE_NORMAL: 2835 if (stats->tx_throughput >= CFO_TP_UPPER) { 2836 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 2837 cfo->cfo_trig_by_timer_en = true; 2838 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 2839 rtw89_phy_cfo_start_work(rtwdev); 2840 } 2841 break; 2842 case RTW89_PHY_DCFO_STATE_ENHANCE: 2843 if (stats->tx_throughput <= CFO_TP_LOWER) 2844 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2845 else if (ofdma_acc_en && 2846 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 2847 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 2848 else 2849 cfo->phy_cfo_trk_cnt++; 2850 2851 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 2852 cfo->phy_cfo_trk_cnt = 0; 2853 cfo->cfo_trig_by_timer_en = false; 2854 } 2855 break; 2856 case RTW89_PHY_DCFO_STATE_HOLD: 2857 if (stats->tx_throughput <= CFO_TP_LOWER) { 2858 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2859 cfo->phy_cfo_trk_cnt = 0; 2860 cfo->cfo_trig_by_timer_en = false; 2861 } else { 2862 cfo->phy_cfo_trk_cnt++; 2863 } 2864 break; 2865 default: 2866 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2867 cfo->phy_cfo_trk_cnt = 0; 2868 break; 2869 } 2870 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2871 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 2872 stats->tx_throughput, cfo->phy_cfo_status, 2873 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 2874 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 2875 if (cfo->cfo_trig_by_timer_en) 2876 return; 2877 rtw89_phy_cfo_dm(rtwdev); 2878 } 2879 2880 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 2881 struct rtw89_rx_phy_ppdu *phy_ppdu) 2882 { 2883 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2884 u8 macid = phy_ppdu->mac_id; 2885 2886 if (macid >= CFO_TRACK_MAX_USER) { 2887 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 2888 return; 2889 } 2890 2891 cfo->cfo_tail[macid] += cfo_val; 2892 cfo->cfo_cnt[macid]++; 2893 cfo->packet_count++; 2894 } 2895 2896 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2897 { 2898 const struct rtw89_chip_info *chip = rtwdev->chip; 2899 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 2900 rtwvif->sub_entity_idx); 2901 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2902 2903 if (!chip->ul_tb_waveform_ctrl) 2904 return; 2905 2906 rtwvif->def_tri_idx = 2907 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG); 2908 2909 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV) 2910 rtwvif->dyn_tb_bedge_en = false; 2911 else if (chan->band_type >= RTW89_BAND_5G && 2912 chan->band_width >= RTW89_CHANNEL_WIDTH_40) 2913 rtwvif->dyn_tb_bedge_en = true; 2914 else 2915 rtwvif->dyn_tb_bedge_en = false; 2916 2917 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2918 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n", 2919 ul_tb_info->def_if_bandedge, rtwvif->def_tri_idx); 2920 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2921 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n", 2922 rtwvif->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en); 2923 } 2924 2925 struct rtw89_phy_ul_tb_check_data { 2926 bool valid; 2927 bool high_tf_client; 2928 bool low_tf_client; 2929 bool dyn_tb_bedge_en; 2930 u8 def_tri_idx; 2931 }; 2932 2933 struct rtw89_phy_power_diff { 2934 u32 q_00; 2935 u32 q_11; 2936 u32 q_matrix_en; 2937 u32 ultb_1t_norm_160; 2938 u32 ultb_2t_norm_160; 2939 u32 com1_norm_1sts; 2940 u32 com2_resp_1sts_path; 2941 }; 2942 2943 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev, 2944 struct rtw89_vif *rtwvif) 2945 { 2946 static const struct rtw89_phy_power_diff table[2] = { 2947 {0x0, 0x0, 0x0, 0x0, 0xf4, 0x3, 0x3}, 2948 {0xb50, 0xb50, 0x1, 0xc, 0x0, 0x1, 0x1}, 2949 }; 2950 const struct rtw89_phy_power_diff *param; 2951 u32 reg; 2952 2953 if (!rtwdev->chip->ul_tb_pwr_diff) 2954 return; 2955 2956 if (rtwvif->pwr_diff_en == rtwvif->pre_pwr_diff_en) { 2957 rtwvif->pwr_diff_en = false; 2958 return; 2959 } 2960 2961 rtwvif->pre_pwr_diff_en = rtwvif->pwr_diff_en; 2962 param = &table[rtwvif->pwr_diff_en]; 2963 2964 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL, 2965 param->q_00); 2966 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL, 2967 param->q_11); 2968 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX, 2969 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en); 2970 2971 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif->mac_idx); 2972 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160, 2973 param->ultb_1t_norm_160); 2974 2975 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif->mac_idx); 2976 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160, 2977 param->ultb_2t_norm_160); 2978 2979 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif->mac_idx); 2980 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS, 2981 param->com1_norm_1sts); 2982 2983 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif->mac_idx); 2984 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH, 2985 param->com2_resp_1sts_path); 2986 } 2987 2988 static 2989 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev, 2990 struct rtw89_vif *rtwvif, 2991 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 2992 { 2993 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2994 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2995 2996 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 2997 return; 2998 2999 if (!vif->cfg.assoc) 3000 return; 3001 3002 if (rtwdev->chip->ul_tb_waveform_ctrl) { 3003 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH) 3004 ul_tb_data->high_tf_client = true; 3005 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH) 3006 ul_tb_data->low_tf_client = true; 3007 3008 ul_tb_data->valid = true; 3009 ul_tb_data->def_tri_idx = rtwvif->def_tri_idx; 3010 ul_tb_data->dyn_tb_bedge_en = rtwvif->dyn_tb_bedge_en; 3011 } 3012 3013 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif); 3014 } 3015 3016 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev, 3017 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 3018 { 3019 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 3020 3021 if (!rtwdev->chip->ul_tb_waveform_ctrl) 3022 return; 3023 3024 if (ul_tb_data->dyn_tb_bedge_en) { 3025 if (ul_tb_data->high_tf_client) { 3026 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0); 3027 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 3028 "[ULTB] Turn off if_bandedge\n"); 3029 } else if (ul_tb_data->low_tf_client) { 3030 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 3031 ul_tb_info->def_if_bandedge); 3032 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 3033 "[ULTB] Set to default if_bandedge = %d\n", 3034 ul_tb_info->def_if_bandedge); 3035 } 3036 } 3037 3038 if (ul_tb_info->dyn_tb_tri_en) { 3039 if (ul_tb_data->high_tf_client) { 3040 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 3041 B_TXSHAPE_TRIANGULAR_CFG, 0); 3042 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 3043 "[ULTB] Turn off Tx triangle\n"); 3044 } else if (ul_tb_data->low_tf_client) { 3045 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 3046 B_TXSHAPE_TRIANGULAR_CFG, 3047 ul_tb_data->def_tri_idx); 3048 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 3049 "[ULTB] Set to default tx_shap_idx = %d\n", 3050 ul_tb_data->def_tri_idx); 3051 } 3052 } 3053 } 3054 3055 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev) 3056 { 3057 const struct rtw89_chip_info *chip = rtwdev->chip; 3058 struct rtw89_phy_ul_tb_check_data ul_tb_data = {}; 3059 struct rtw89_vif *rtwvif; 3060 3061 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff) 3062 return; 3063 3064 if (rtwdev->total_sta_assoc != 1) 3065 return; 3066 3067 rtw89_for_each_rtwvif(rtwdev, rtwvif) 3068 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data); 3069 3070 if (!ul_tb_data.valid) 3071 return; 3072 3073 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data); 3074 } 3075 3076 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev) 3077 { 3078 const struct rtw89_chip_info *chip = rtwdev->chip; 3079 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 3080 3081 if (!chip->ul_tb_waveform_ctrl) 3082 return; 3083 3084 ul_tb_info->dyn_tb_tri_en = true; 3085 ul_tb_info->def_if_bandedge = 3086 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN); 3087 } 3088 3089 static 3090 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts) 3091 { 3092 ewma_rssi_init(&antdiv_sts->cck_rssi_avg); 3093 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg); 3094 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg); 3095 antdiv_sts->pkt_cnt_cck = 0; 3096 antdiv_sts->pkt_cnt_ofdm = 0; 3097 antdiv_sts->pkt_cnt_non_legacy = 0; 3098 antdiv_sts->evm = 0; 3099 } 3100 3101 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev, 3102 struct rtw89_rx_phy_ppdu *phy_ppdu, 3103 struct rtw89_antdiv_stats *stats) 3104 { 3105 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) { 3106 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) { 3107 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg); 3108 stats->pkt_cnt_cck++; 3109 } else { 3110 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg); 3111 stats->pkt_cnt_ofdm++; 3112 stats->evm += phy_ppdu->ofdm.evm_min; 3113 } 3114 } else { 3115 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg); 3116 stats->pkt_cnt_non_legacy++; 3117 stats->evm += phy_ppdu->ofdm.evm_min; 3118 } 3119 } 3120 3121 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats) 3122 { 3123 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck && 3124 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm) 3125 return ewma_rssi_read(&stats->non_legacy_rssi_avg); 3126 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck && 3127 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy) 3128 return ewma_rssi_read(&stats->ofdm_rssi_avg); 3129 else 3130 return ewma_rssi_read(&stats->cck_rssi_avg); 3131 } 3132 3133 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats) 3134 { 3135 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm); 3136 } 3137 3138 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 3139 struct rtw89_rx_phy_ppdu *phy_ppdu) 3140 { 3141 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3142 struct rtw89_hal *hal = &rtwdev->hal; 3143 3144 if (!hal->ant_diversity || hal->ant_diversity_fixed) 3145 return; 3146 3147 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats); 3148 3149 if (!antdiv->get_stats) 3150 return; 3151 3152 if (hal->antenna_rx == RF_A) 3153 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats); 3154 else if (hal->antenna_rx == RF_B) 3155 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats); 3156 } 3157 3158 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev) 3159 { 3160 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN, 3161 0x0, RTW89_PHY_0); 3162 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL, 3163 0x0, RTW89_PHY_0); 3164 3165 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND, 3166 0x0, RTW89_PHY_0); 3167 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT, 3168 0x0, RTW89_PHY_0); 3169 3170 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN, 3171 0x0, RTW89_PHY_0); 3172 3173 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING, 3174 0x0100, RTW89_PHY_0); 3175 3176 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX, 3177 0x1, RTW89_PHY_0); 3178 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL, 3179 0x0, RTW89_PHY_0); 3180 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G, 3181 0x0, RTW89_PHY_0); 3182 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G, 3183 0x0, RTW89_PHY_0); 3184 } 3185 3186 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev) 3187 { 3188 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3189 3190 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 3191 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats); 3192 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats); 3193 } 3194 3195 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev) 3196 { 3197 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3198 struct rtw89_hal *hal = &rtwdev->hal; 3199 3200 if (!hal->ant_diversity) 3201 return; 3202 3203 antdiv->get_stats = false; 3204 antdiv->rssi_pre = 0; 3205 rtw89_phy_antdiv_sts_reset(rtwdev); 3206 rtw89_phy_antdiv_reg_init(rtwdev); 3207 } 3208 3209 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 3210 { 3211 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3212 int i; 3213 u8 th; 3214 3215 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 3216 th = rtw89_chip_get_thermal(rtwdev, i); 3217 if (th) 3218 ewma_thermal_add(&phystat->avg_thermal[i], th); 3219 3220 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 3221 "path(%d) thermal cur=%u avg=%ld", i, th, 3222 ewma_thermal_read(&phystat->avg_thermal[i])); 3223 } 3224 } 3225 3226 struct rtw89_phy_iter_rssi_data { 3227 struct rtw89_dev *rtwdev; 3228 struct rtw89_phy_ch_info *ch_info; 3229 bool rssi_changed; 3230 }; 3231 3232 static void rtw89_phy_stat_rssi_update_iter(void *data, 3233 struct ieee80211_sta *sta) 3234 { 3235 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3236 struct rtw89_phy_iter_rssi_data *rssi_data = 3237 (struct rtw89_phy_iter_rssi_data *)data; 3238 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 3239 unsigned long rssi_curr; 3240 3241 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 3242 3243 if (rssi_curr < ch_info->rssi_min) { 3244 ch_info->rssi_min = rssi_curr; 3245 ch_info->rssi_min_macid = rtwsta->mac_id; 3246 } 3247 3248 if (rtwsta->prev_rssi == 0) { 3249 rtwsta->prev_rssi = rssi_curr; 3250 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 3251 rtwsta->prev_rssi = rssi_curr; 3252 rssi_data->rssi_changed = true; 3253 } 3254 } 3255 3256 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 3257 { 3258 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 3259 3260 rssi_data.rtwdev = rtwdev; 3261 rssi_data.ch_info = &rtwdev->ch_info; 3262 rssi_data.ch_info->rssi_min = U8_MAX; 3263 ieee80211_iterate_stations_atomic(rtwdev->hw, 3264 rtw89_phy_stat_rssi_update_iter, 3265 &rssi_data); 3266 if (rssi_data.rssi_changed) 3267 rtw89_btc_ntfy_wl_sta(rtwdev); 3268 } 3269 3270 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 3271 { 3272 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3273 int i; 3274 3275 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 3276 ewma_thermal_init(&phystat->avg_thermal[i]); 3277 3278 rtw89_phy_stat_thermal_update(rtwdev); 3279 3280 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 3281 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 3282 } 3283 3284 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 3285 { 3286 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3287 3288 rtw89_phy_stat_thermal_update(rtwdev); 3289 rtw89_phy_stat_rssi_update(rtwdev); 3290 3291 phystat->last_pkt_stat = phystat->cur_pkt_stat; 3292 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 3293 } 3294 3295 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 3296 { 3297 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3298 3299 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3300 } 3301 3302 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 3303 { 3304 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3305 3306 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3307 } 3308 3309 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 3310 { 3311 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3312 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3313 const struct rtw89_ccx_regs *ccx = phy->ccx; 3314 3315 env->ccx_manual_ctrl = false; 3316 env->ccx_ongoing = false; 3317 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3318 env->ccx_period = 0; 3319 env->ccx_unit_idx = RTW89_CCX_32_US; 3320 3321 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->en_mask, 1); 3322 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1); 3323 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1); 3324 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask, 3325 RTW89_CCX_EDCCA_BW20_0); 3326 } 3327 3328 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 3329 u16 score) 3330 { 3331 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3332 u32 numer = 0; 3333 u16 ret = 0; 3334 3335 numer = report * score + (env->ccx_period >> 1); 3336 if (env->ccx_period) 3337 ret = numer / env->ccx_period; 3338 3339 return ret >= score ? score - 1 : ret; 3340 } 3341 3342 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 3343 u16 time_ms, u32 *period, 3344 u32 *unit_idx) 3345 { 3346 u32 idx; 3347 u8 quotient; 3348 3349 if (time_ms >= CCX_MAX_PERIOD) 3350 time_ms = CCX_MAX_PERIOD; 3351 3352 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 3353 3354 if (quotient < 4) 3355 idx = RTW89_CCX_4_US; 3356 else if (quotient < 8) 3357 idx = RTW89_CCX_8_US; 3358 else if (quotient < 16) 3359 idx = RTW89_CCX_16_US; 3360 else 3361 idx = RTW89_CCX_32_US; 3362 3363 *unit_idx = idx; 3364 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 3365 3366 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3367 "[Trigger Time] period:%d, unit_idx:%d\n", 3368 *period, *unit_idx); 3369 } 3370 3371 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 3372 { 3373 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3374 3375 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3376 "lv:(%d)->(0)\n", env->ccx_rac_lv); 3377 3378 env->ccx_ongoing = false; 3379 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3380 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3381 } 3382 3383 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 3384 struct rtw89_ccx_para_info *para) 3385 { 3386 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3387 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 3388 u8 i = 0; 3389 u16 *ifs_th_l = env->ifs_clm_th_l; 3390 u16 *ifs_th_h = env->ifs_clm_th_h; 3391 u32 ifs_th0_us = 0, ifs_th_times = 0; 3392 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 3393 3394 if (!is_update) 3395 goto ifs_update_finished; 3396 3397 switch (para->ifs_clm_app) { 3398 case RTW89_IFS_CLM_INIT: 3399 case RTW89_IFS_CLM_BACKGROUND: 3400 case RTW89_IFS_CLM_ACS: 3401 case RTW89_IFS_CLM_DBG: 3402 case RTW89_IFS_CLM_DIG: 3403 case RTW89_IFS_CLM_TDMA_DIG: 3404 ifs_th0_us = IFS_CLM_TH0_UPPER; 3405 ifs_th_times = IFS_CLM_TH_MUL; 3406 break; 3407 case RTW89_IFS_CLM_DBG_MANUAL: 3408 ifs_th0_us = para->ifs_clm_manual_th0; 3409 ifs_th_times = para->ifs_clm_manual_th_times; 3410 break; 3411 default: 3412 break; 3413 } 3414 3415 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 3416 * low[i] = high[i-1] + 1 3417 * high[i] = high[i-1] * ifs_th_times 3418 */ 3419 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 3420 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 3421 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 3422 ifs_th0_us); 3423 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 3424 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 3425 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 3426 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 3427 } 3428 3429 ifs_update_finished: 3430 if (!is_update) 3431 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3432 "No need to update IFS_TH\n"); 3433 3434 return is_update; 3435 } 3436 3437 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 3438 { 3439 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3440 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3441 const struct rtw89_ccx_regs *ccx = phy->ccx; 3442 u8 i = 0; 3443 3444 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask, 3445 env->ifs_clm_th_l[0]); 3446 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask, 3447 env->ifs_clm_th_l[1]); 3448 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask, 3449 env->ifs_clm_th_l[2]); 3450 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask, 3451 env->ifs_clm_th_l[3]); 3452 3453 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask, 3454 env->ifs_clm_th_h[0]); 3455 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask, 3456 env->ifs_clm_th_h[1]); 3457 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask, 3458 env->ifs_clm_th_h[2]); 3459 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask, 3460 env->ifs_clm_th_h[3]); 3461 3462 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3463 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3464 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 3465 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 3466 } 3467 3468 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 3469 { 3470 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3471 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3472 const struct rtw89_ccx_regs *ccx = phy->ccx; 3473 struct rtw89_ccx_para_info para = {0}; 3474 3475 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3476 env->ifs_clm_mntr_time = 0; 3477 3478 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 3479 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 3480 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3481 3482 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true); 3483 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true); 3484 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true); 3485 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true); 3486 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true); 3487 } 3488 3489 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 3490 enum rtw89_env_racing_lv level) 3491 { 3492 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3493 int ret = 0; 3494 3495 if (level >= RTW89_RAC_MAX_NUM) { 3496 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3497 "[WARNING] Wrong LV=%d\n", level); 3498 return -EINVAL; 3499 } 3500 3501 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3502 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 3503 env->ccx_rac_lv, level); 3504 3505 if (env->ccx_ongoing) { 3506 if (level <= env->ccx_rac_lv) 3507 ret = -EINVAL; 3508 else 3509 env->ccx_ongoing = false; 3510 } 3511 3512 if (ret == 0) 3513 env->ccx_rac_lv = level; 3514 3515 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 3516 !ret); 3517 3518 return ret; 3519 } 3520 3521 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 3522 { 3523 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3524 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3525 const struct rtw89_ccx_regs *ccx = phy->ccx; 3526 3527 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0); 3528 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0); 3529 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1); 3530 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1); 3531 3532 env->ccx_ongoing = true; 3533 } 3534 3535 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 3536 { 3537 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3538 u8 i = 0; 3539 u32 res = 0; 3540 3541 env->ifs_clm_tx_ratio = 3542 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 3543 env->ifs_clm_edcca_excl_cca_ratio = 3544 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 3545 PERCENT); 3546 env->ifs_clm_cck_fa_ratio = 3547 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 3548 env->ifs_clm_ofdm_fa_ratio = 3549 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 3550 env->ifs_clm_cck_cca_excl_fa_ratio = 3551 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 3552 PERCENT); 3553 env->ifs_clm_ofdm_cca_excl_fa_ratio = 3554 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 3555 PERCENT); 3556 env->ifs_clm_cck_fa_permil = 3557 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 3558 env->ifs_clm_ofdm_fa_permil = 3559 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 3560 3561 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 3562 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 3563 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 3564 } else { 3565 env->ifs_clm_ifs_avg[i] = 3566 rtw89_phy_ccx_idx_to_us(rtwdev, 3567 env->ifs_clm_avg[i]); 3568 } 3569 3570 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 3571 res += env->ifs_clm_his[i] >> 1; 3572 if (env->ifs_clm_his[i]) 3573 res /= env->ifs_clm_his[i]; 3574 else 3575 res = 0; 3576 env->ifs_clm_cca_avg[i] = res; 3577 } 3578 3579 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3580 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3581 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 3582 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3583 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 3584 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 3585 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3586 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 3587 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 3588 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3589 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 3590 env->ifs_clm_cck_cca_excl_fa_ratio, 3591 env->ifs_clm_ofdm_cca_excl_fa_ratio); 3592 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3593 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 3594 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3595 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 3596 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 3597 env->ifs_clm_cca_avg[i]); 3598 } 3599 3600 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 3601 { 3602 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3603 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3604 const struct rtw89_ccx_regs *ccx = phy->ccx; 3605 u8 i = 0; 3606 3607 if (rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr, 3608 ccx->ifs_cnt_done_mask) == 0) { 3609 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3610 "Get IFS_CLM report Fail\n"); 3611 return false; 3612 } 3613 3614 env->ifs_clm_tx = 3615 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr, 3616 ccx->ifs_clm_tx_cnt_msk); 3617 env->ifs_clm_edcca_excl_cca = 3618 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr, 3619 ccx->ifs_clm_edcca_excl_cca_fa_mask); 3620 env->ifs_clm_cckcca_excl_fa = 3621 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr, 3622 ccx->ifs_clm_cckcca_excl_fa_mask); 3623 env->ifs_clm_ofdmcca_excl_fa = 3624 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr, 3625 ccx->ifs_clm_ofdmcca_excl_fa_mask); 3626 env->ifs_clm_cckfa = 3627 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr, 3628 ccx->ifs_clm_cck_fa_mask); 3629 env->ifs_clm_ofdmfa = 3630 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr, 3631 ccx->ifs_clm_ofdm_fa_mask); 3632 3633 env->ifs_clm_his[0] = 3634 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 3635 ccx->ifs_t1_his_mask); 3636 env->ifs_clm_his[1] = 3637 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 3638 ccx->ifs_t2_his_mask); 3639 env->ifs_clm_his[2] = 3640 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 3641 ccx->ifs_t3_his_mask); 3642 env->ifs_clm_his[3] = 3643 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 3644 ccx->ifs_t4_his_mask); 3645 3646 env->ifs_clm_avg[0] = 3647 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr, 3648 ccx->ifs_t1_avg_mask); 3649 env->ifs_clm_avg[1] = 3650 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr, 3651 ccx->ifs_t2_avg_mask); 3652 env->ifs_clm_avg[2] = 3653 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr, 3654 ccx->ifs_t3_avg_mask); 3655 env->ifs_clm_avg[3] = 3656 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr, 3657 ccx->ifs_t4_avg_mask); 3658 3659 env->ifs_clm_cca[0] = 3660 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr, 3661 ccx->ifs_t1_cca_mask); 3662 env->ifs_clm_cca[1] = 3663 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr, 3664 ccx->ifs_t2_cca_mask); 3665 env->ifs_clm_cca[2] = 3666 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr, 3667 ccx->ifs_t3_cca_mask); 3668 env->ifs_clm_cca[3] = 3669 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr, 3670 ccx->ifs_t4_cca_mask); 3671 3672 env->ifs_clm_total_ifs = 3673 rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr, 3674 ccx->ifs_total_mask); 3675 3676 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 3677 env->ifs_clm_total_ifs); 3678 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3679 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3680 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 3681 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3682 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 3683 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 3684 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3685 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 3686 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 3687 3688 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 3689 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3690 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3691 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 3692 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 3693 3694 rtw89_phy_ifs_clm_get_utility(rtwdev); 3695 3696 return true; 3697 } 3698 3699 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 3700 struct rtw89_ccx_para_info *para) 3701 { 3702 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3703 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3704 const struct rtw89_ccx_regs *ccx = phy->ccx; 3705 u32 period = 0; 3706 u32 unit_idx = 0; 3707 3708 if (para->mntr_time == 0) { 3709 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3710 "[WARN] MNTR_TIME is 0\n"); 3711 return -EINVAL; 3712 } 3713 3714 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 3715 return -EINVAL; 3716 3717 if (para->mntr_time != env->ifs_clm_mntr_time) { 3718 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 3719 &period, &unit_idx); 3720 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, 3721 ccx->ifs_clm_period_mask, period); 3722 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, 3723 ccx->ifs_clm_cnt_unit_mask, 3724 unit_idx); 3725 3726 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3727 "Update IFS-CLM time ((%d)) -> ((%d))\n", 3728 env->ifs_clm_mntr_time, para->mntr_time); 3729 3730 env->ifs_clm_mntr_time = para->mntr_time; 3731 env->ccx_period = (u16)period; 3732 env->ccx_unit_idx = (u8)unit_idx; 3733 } 3734 3735 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 3736 env->ifs_clm_app = para->ifs_clm_app; 3737 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3738 } 3739 3740 return 0; 3741 } 3742 3743 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 3744 { 3745 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3746 struct rtw89_ccx_para_info para = {0}; 3747 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3748 3749 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3750 if (env->ccx_manual_ctrl) { 3751 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3752 "CCX in manual ctrl\n"); 3753 return; 3754 } 3755 3756 /* only ifs_clm for now */ 3757 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 3758 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3759 3760 rtw89_phy_ccx_racing_release(rtwdev); 3761 para.mntr_time = 1900; 3762 para.rac_lv = RTW89_RAC_LV_1; 3763 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3764 3765 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 3766 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3767 if (chk_result) 3768 rtw89_phy_ccx_trigger(rtwdev); 3769 3770 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3771 "get_result=0x%x, chk_result:0x%x\n", 3772 env->ccx_watchdog_result, chk_result); 3773 } 3774 3775 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 3776 { 3777 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM || 3778 *ie_page == RTW89_RSVD_9) 3779 return false; 3780 else if (*ie_page > RTW89_RSVD_9) 3781 *ie_page -= 1; 3782 3783 return true; 3784 } 3785 3786 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 3787 { 3788 static const u8 ie_page_shift = 2; 3789 3790 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 3791 } 3792 3793 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 3794 enum rtw89_phy_status_bitmap ie_page) 3795 { 3796 u32 addr; 3797 3798 if (!rtw89_physts_ie_page_valid(&ie_page)) 3799 return 0; 3800 3801 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3802 3803 return rtw89_phy_read32(rtwdev, addr); 3804 } 3805 3806 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 3807 enum rtw89_phy_status_bitmap ie_page, 3808 u32 val) 3809 { 3810 const struct rtw89_chip_info *chip = rtwdev->chip; 3811 u32 addr; 3812 3813 if (!rtw89_physts_ie_page_valid(&ie_page)) 3814 return; 3815 3816 if (chip->chip_id == RTL8852A) 3817 val &= B_PHY_STS_BITMAP_MSK_52A; 3818 3819 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3820 rtw89_phy_write32(rtwdev, addr, val); 3821 } 3822 3823 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 3824 enum rtw89_phy_status_bitmap bitmap, 3825 enum rtw89_phy_status_ie_type ie, 3826 bool enable) 3827 { 3828 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 3829 3830 if (enable) 3831 val |= BIT(ie); 3832 else 3833 val &= ~BIT(ie); 3834 3835 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 3836 } 3837 3838 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 3839 bool enable, 3840 enum rtw89_phy_idx phy_idx) 3841 { 3842 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3843 const struct rtw89_physts_regs *physts = phy->physts; 3844 3845 if (enable) { 3846 rtw89_phy_write32_clr(rtwdev, physts->setting_addr, 3847 physts->dis_trigger_fail_mask); 3848 rtw89_phy_write32_clr(rtwdev, physts->setting_addr, 3849 physts->dis_trigger_brk_mask); 3850 } else { 3851 rtw89_phy_write32_set(rtwdev, physts->setting_addr, 3852 physts->dis_trigger_fail_mask); 3853 rtw89_phy_write32_set(rtwdev, physts->setting_addr, 3854 physts->dis_trigger_brk_mask); 3855 } 3856 } 3857 3858 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 3859 { 3860 u8 i; 3861 3862 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 3863 3864 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 3865 if (i >= RTW89_CCK_PKT) 3866 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3867 RTW89_PHYSTS_IE09_FTR_0, 3868 true); 3869 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 3870 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 3871 continue; 3872 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3873 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 3874 true); 3875 } 3876 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 3877 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3878 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 3879 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3880 3881 /* force IE01 for channel index, only channel field is valid */ 3882 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 3883 RTW89_PHYSTS_IE01_CMN_OFDM, true); 3884 } 3885 3886 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 3887 { 3888 const struct rtw89_chip_info *chip = rtwdev->chip; 3889 struct rtw89_dig_info *dig = &rtwdev->dig; 3890 const struct rtw89_phy_dig_gain_cfg *cfg; 3891 const char *msg; 3892 u8 i; 3893 s8 gain_base; 3894 s8 *gain_arr; 3895 u32 tmp; 3896 3897 switch (type) { 3898 case RTW89_DIG_GAIN_LNA_G: 3899 gain_arr = dig->lna_gain_g; 3900 gain_base = LNA0_GAIN; 3901 cfg = chip->dig_table->cfg_lna_g; 3902 msg = "lna_gain_g"; 3903 break; 3904 case RTW89_DIG_GAIN_TIA_G: 3905 gain_arr = dig->tia_gain_g; 3906 gain_base = TIA0_GAIN_G; 3907 cfg = chip->dig_table->cfg_tia_g; 3908 msg = "tia_gain_g"; 3909 break; 3910 case RTW89_DIG_GAIN_LNA_A: 3911 gain_arr = dig->lna_gain_a; 3912 gain_base = LNA0_GAIN; 3913 cfg = chip->dig_table->cfg_lna_a; 3914 msg = "lna_gain_a"; 3915 break; 3916 case RTW89_DIG_GAIN_TIA_A: 3917 gain_arr = dig->tia_gain_a; 3918 gain_base = TIA0_GAIN_A; 3919 cfg = chip->dig_table->cfg_tia_a; 3920 msg = "tia_gain_a"; 3921 break; 3922 default: 3923 return; 3924 } 3925 3926 for (i = 0; i < cfg->size; i++) { 3927 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 3928 cfg->table[i].mask); 3929 tmp >>= DIG_GAIN_SHIFT; 3930 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 3931 gain_base += DIG_GAIN; 3932 3933 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 3934 msg, i, gain_arr[i]); 3935 } 3936 } 3937 3938 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 3939 { 3940 struct rtw89_dig_info *dig = &rtwdev->dig; 3941 u32 tmp; 3942 u8 i; 3943 3944 if (!rtwdev->hal.support_igi) 3945 return; 3946 3947 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 3948 B_PATH0_IB_PKPW_MSK); 3949 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 3950 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 3951 B_PATH0_IB_PBK_MSK); 3952 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 3953 dig->ib_pkpwr, dig->ib_pbk); 3954 3955 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 3956 rtw89_phy_dig_read_gain_table(rtwdev, i); 3957 } 3958 3959 static const u8 rssi_nolink = 22; 3960 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 3961 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 3962 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 3963 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 3964 3965 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 3966 { 3967 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 3968 struct rtw89_dig_info *dig = &rtwdev->dig; 3969 bool is_linked = rtwdev->total_sta_assoc > 0; 3970 3971 if (is_linked) { 3972 dig->igi_rssi = ch_info->rssi_min >> 1; 3973 } else { 3974 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 3975 dig->igi_rssi = rssi_nolink; 3976 } 3977 } 3978 3979 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 3980 { 3981 struct rtw89_dig_info *dig = &rtwdev->dig; 3982 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3983 bool is_linked = rtwdev->total_sta_assoc > 0; 3984 const u16 *fa_th_src = NULL; 3985 3986 switch (chan->band_type) { 3987 case RTW89_BAND_2G: 3988 dig->lna_gain = dig->lna_gain_g; 3989 dig->tia_gain = dig->tia_gain_g; 3990 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 3991 dig->force_gaincode_idx_en = false; 3992 dig->dyn_pd_th_en = true; 3993 break; 3994 case RTW89_BAND_5G: 3995 default: 3996 dig->lna_gain = dig->lna_gain_a; 3997 dig->tia_gain = dig->tia_gain_a; 3998 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 3999 dig->force_gaincode_idx_en = true; 4000 dig->dyn_pd_th_en = true; 4001 break; 4002 } 4003 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 4004 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 4005 } 4006 4007 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 4008 static const u8 igi_max_performance_mode = 0x5a; 4009 static const u8 dynamic_pd_threshold_max; 4010 4011 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 4012 { 4013 struct rtw89_dig_info *dig = &rtwdev->dig; 4014 4015 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 4016 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 4017 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 4018 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 4019 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 4020 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 4021 4022 dig->dyn_igi_max = igi_max_performance_mode; 4023 dig->dyn_igi_min = dynamic_igi_min; 4024 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 4025 dig->pd_low_th_ofst = pd_low_th_offset; 4026 dig->is_linked_pre = false; 4027 } 4028 4029 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 4030 { 4031 rtw89_phy_dig_update_gain_para(rtwdev); 4032 rtw89_phy_dig_reset(rtwdev); 4033 } 4034 4035 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 4036 { 4037 struct rtw89_dig_info *dig = &rtwdev->dig; 4038 u8 lna_idx; 4039 4040 if (rssi < dig->igi_rssi_th[0]) 4041 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 4042 else if (rssi < dig->igi_rssi_th[1]) 4043 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 4044 else if (rssi < dig->igi_rssi_th[2]) 4045 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 4046 else if (rssi < dig->igi_rssi_th[3]) 4047 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 4048 else if (rssi < dig->igi_rssi_th[4]) 4049 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 4050 else 4051 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 4052 4053 return lna_idx; 4054 } 4055 4056 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 4057 { 4058 struct rtw89_dig_info *dig = &rtwdev->dig; 4059 u8 tia_idx; 4060 4061 if (rssi < dig->igi_rssi_th[0]) 4062 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 4063 else 4064 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 4065 4066 return tia_idx; 4067 } 4068 4069 #define IB_PBK_BASE 110 4070 #define WB_RSSI_BASE 10 4071 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 4072 struct rtw89_agc_gaincode_set *set) 4073 { 4074 struct rtw89_dig_info *dig = &rtwdev->dig; 4075 s8 lna_gain = dig->lna_gain[set->lna_idx]; 4076 s8 tia_gain = dig->tia_gain[set->tia_idx]; 4077 s32 wb_rssi = rssi + lna_gain + tia_gain; 4078 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 4079 u8 rxb_idx; 4080 4081 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 4082 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 4083 4084 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 4085 wb_rssi, rxb_idx_tmp); 4086 4087 return rxb_idx; 4088 } 4089 4090 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 4091 struct rtw89_agc_gaincode_set *set) 4092 { 4093 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 4094 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 4095 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 4096 4097 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4098 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 4099 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 4100 } 4101 4102 #define IGI_OFFSET_MAX 25 4103 #define IGI_OFFSET_MUL 2 4104 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 4105 { 4106 struct rtw89_dig_info *dig = &rtwdev->dig; 4107 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4108 enum rtw89_dig_noisy_level noisy_lv; 4109 u8 igi_offset = dig->fa_rssi_ofst; 4110 u16 fa_ratio = 0; 4111 4112 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 4113 4114 if (fa_ratio < dig->fa_th[0]) 4115 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 4116 else if (fa_ratio < dig->fa_th[1]) 4117 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 4118 else if (fa_ratio < dig->fa_th[2]) 4119 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 4120 else if (fa_ratio < dig->fa_th[3]) 4121 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 4122 else 4123 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 4124 4125 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 4126 igi_offset = 0; 4127 else 4128 igi_offset += noisy_lv * IGI_OFFSET_MUL; 4129 4130 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 4131 dig->fa_rssi_ofst = igi_offset; 4132 4133 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4134 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 4135 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 4136 4137 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4138 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 4139 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 4140 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 4141 noisy_lv, igi_offset); 4142 } 4143 4144 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 4145 { 4146 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4147 4148 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr, 4149 dig_regs->p0_lna_init.mask, lna_idx); 4150 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr, 4151 dig_regs->p1_lna_init.mask, lna_idx); 4152 } 4153 4154 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 4155 { 4156 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4157 4158 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr, 4159 dig_regs->p0_tia_init.mask, tia_idx); 4160 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr, 4161 dig_regs->p1_tia_init.mask, tia_idx); 4162 } 4163 4164 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 4165 { 4166 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4167 4168 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr, 4169 dig_regs->p0_rxb_init.mask, rxb_idx); 4170 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr, 4171 dig_regs->p1_rxb_init.mask, rxb_idx); 4172 } 4173 4174 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 4175 const struct rtw89_agc_gaincode_set set) 4176 { 4177 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 4178 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 4179 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 4180 4181 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 4182 set.lna_idx, set.tia_idx, set.rxb_idx); 4183 } 4184 4185 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 4186 bool enable) 4187 { 4188 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4189 4190 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 4191 dig_regs->p0_p20_pagcugc_en.mask, enable); 4192 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 4193 dig_regs->p0_s20_pagcugc_en.mask, enable); 4194 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 4195 dig_regs->p1_p20_pagcugc_en.mask, enable); 4196 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 4197 dig_regs->p1_s20_pagcugc_en.mask, enable); 4198 4199 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 4200 } 4201 4202 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 4203 { 4204 struct rtw89_dig_info *dig = &rtwdev->dig; 4205 4206 if (!rtwdev->hal.support_igi) 4207 return; 4208 4209 if (dig->force_gaincode_idx_en) { 4210 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 4211 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4212 "Force gaincode index enabled.\n"); 4213 } else { 4214 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 4215 &dig->cur_gaincode); 4216 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 4217 } 4218 } 4219 4220 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 4221 bool enable) 4222 { 4223 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 4224 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4225 enum rtw89_bandwidth cbw = chan->band_width; 4226 struct rtw89_dig_info *dig = &rtwdev->dig; 4227 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 4228 u8 ofdm_cca_th; 4229 s8 cck_cca_th; 4230 u32 pd_val = 0; 4231 4232 under_region += PD_TH_SB_FLTR_CMP_VAL; 4233 4234 switch (cbw) { 4235 case RTW89_CHANNEL_WIDTH_40: 4236 under_region += PD_TH_BW40_CMP_VAL; 4237 break; 4238 case RTW89_CHANNEL_WIDTH_80: 4239 under_region += PD_TH_BW80_CMP_VAL; 4240 break; 4241 case RTW89_CHANNEL_WIDTH_160: 4242 under_region += PD_TH_BW160_CMP_VAL; 4243 break; 4244 case RTW89_CHANNEL_WIDTH_20: 4245 fallthrough; 4246 default: 4247 under_region += PD_TH_BW20_CMP_VAL; 4248 break; 4249 } 4250 4251 dig->dyn_pd_th_max = dig->igi_rssi; 4252 4253 final_rssi = min_t(u8, rssi, dig->igi_rssi); 4254 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 4255 PD_TH_MAX_RSSI + under_region); 4256 4257 if (enable) { 4258 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 4259 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4260 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 4261 final_rssi, ofdm_cca_th, under_region, pd_val); 4262 } else { 4263 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4264 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 4265 } 4266 4267 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 4268 dig_regs->pd_lower_bound_mask, pd_val); 4269 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 4270 dig_regs->pd_spatial_reuse_en, enable); 4271 4272 if (!rtwdev->hal.support_cckpd) 4273 return; 4274 4275 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 4276 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 4277 4278 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4279 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 4280 final_rssi, cck_cca_th, under_region, pd_val); 4281 4282 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_reg, 4283 dig_regs->bmode_cca_rssi_limit_en, enable); 4284 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_lower_bound_reg, 4285 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val); 4286 } 4287 4288 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 4289 { 4290 struct rtw89_dig_info *dig = &rtwdev->dig; 4291 4292 dig->bypass_dig = false; 4293 rtw89_phy_dig_para_reset(rtwdev); 4294 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 4295 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 4296 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 4297 rtw89_phy_dig_update_para(rtwdev); 4298 } 4299 4300 #define IGI_RSSI_MIN 10 4301 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 4302 { 4303 struct rtw89_dig_info *dig = &rtwdev->dig; 4304 bool is_linked = rtwdev->total_sta_assoc > 0; 4305 4306 if (unlikely(dig->bypass_dig)) { 4307 dig->bypass_dig = false; 4308 return; 4309 } 4310 4311 if (!dig->is_linked_pre && is_linked) { 4312 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 4313 rtw89_phy_dig_update_para(rtwdev); 4314 } else if (dig->is_linked_pre && !is_linked) { 4315 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 4316 rtw89_phy_dig_update_para(rtwdev); 4317 } 4318 dig->is_linked_pre = is_linked; 4319 4320 rtw89_phy_dig_igi_offset_by_env(rtwdev); 4321 rtw89_phy_dig_update_rssi_info(rtwdev); 4322 4323 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 4324 dig->igi_rssi - IGI_RSSI_MIN : 0; 4325 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 4326 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 4327 4328 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 4329 dig->dyn_igi_max); 4330 4331 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4332 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 4333 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 4334 dig->igi_fa_rssi); 4335 4336 rtw89_phy_dig_config_igi(rtwdev); 4337 4338 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 4339 4340 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 4341 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 4342 else 4343 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 4344 } 4345 4346 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 4347 { 4348 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 4349 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4350 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4351 struct rtw89_hal *hal = &rtwdev->hal; 4352 bool *done = data; 4353 u8 rssi_a, rssi_b; 4354 u32 candidate; 4355 4356 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || sta->tdls) 4357 return; 4358 4359 if (*done) 4360 return; 4361 4362 *done = true; 4363 4364 rssi_a = ewma_rssi_read(&rtwsta->rssi[RF_PATH_A]); 4365 rssi_b = ewma_rssi_read(&rtwsta->rssi[RF_PATH_B]); 4366 4367 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 4368 candidate = RF_A; 4369 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 4370 candidate = RF_B; 4371 else 4372 return; 4373 4374 if (hal->antenna_tx == candidate) 4375 return; 4376 4377 hal->antenna_tx = candidate; 4378 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta); 4379 4380 if (hal->antenna_tx == RF_A) { 4381 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 4382 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 4383 } else if (hal->antenna_tx == RF_B) { 4384 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 4385 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 4386 } 4387 } 4388 4389 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 4390 { 4391 struct rtw89_hal *hal = &rtwdev->hal; 4392 bool done = false; 4393 4394 if (!hal->tx_path_diversity) 4395 return; 4396 4397 ieee80211_iterate_stations_atomic(rtwdev->hw, 4398 rtw89_phy_tx_path_div_sta_iter, 4399 &done); 4400 } 4401 4402 #define ANTDIV_MAIN 0 4403 #define ANTDIV_AUX 1 4404 4405 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev) 4406 { 4407 struct rtw89_hal *hal = &rtwdev->hal; 4408 u8 default_ant, optional_ant; 4409 4410 if (!hal->ant_diversity || hal->antenna_tx == 0) 4411 return; 4412 4413 if (hal->antenna_tx == RF_B) { 4414 default_ant = ANTDIV_AUX; 4415 optional_ant = ANTDIV_MAIN; 4416 } else { 4417 default_ant = ANTDIV_MAIN; 4418 optional_ant = ANTDIV_AUX; 4419 } 4420 4421 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL, 4422 default_ant, RTW89_PHY_0); 4423 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI, 4424 default_ant, RTW89_PHY_0); 4425 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT, 4426 optional_ant, RTW89_PHY_0); 4427 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI, 4428 default_ant, RTW89_PHY_0); 4429 } 4430 4431 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev) 4432 { 4433 struct rtw89_hal *hal = &rtwdev->hal; 4434 4435 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A; 4436 hal->antenna_tx = hal->antenna_rx; 4437 } 4438 4439 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev) 4440 { 4441 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4442 struct rtw89_hal *hal = &rtwdev->hal; 4443 bool no_change = false; 4444 u8 main_rssi, aux_rssi; 4445 u8 main_evm, aux_evm; 4446 u32 candidate; 4447 4448 antdiv->get_stats = false; 4449 antdiv->training_count = 0; 4450 4451 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats); 4452 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats); 4453 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats); 4454 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats); 4455 4456 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH) 4457 candidate = RF_A; 4458 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH) 4459 candidate = RF_B; 4460 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 4461 candidate = RF_A; 4462 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 4463 candidate = RF_B; 4464 else 4465 no_change = true; 4466 4467 if (no_change) { 4468 /* swap back from training antenna to original */ 4469 rtw89_phy_swap_hal_antenna(rtwdev); 4470 return; 4471 } 4472 4473 hal->antenna_tx = candidate; 4474 hal->antenna_rx = candidate; 4475 } 4476 4477 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev) 4478 { 4479 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4480 u64 state_period; 4481 4482 if (antdiv->training_count % 2 == 0) { 4483 if (antdiv->training_count == 0) 4484 rtw89_phy_antdiv_sts_reset(rtwdev); 4485 4486 antdiv->get_stats = true; 4487 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL); 4488 } else { 4489 antdiv->get_stats = false; 4490 state_period = msecs_to_jiffies(ANTDIV_DELAY); 4491 4492 rtw89_phy_swap_hal_antenna(rtwdev); 4493 rtw89_phy_antdiv_set_ant(rtwdev); 4494 } 4495 4496 antdiv->training_count++; 4497 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 4498 state_period); 4499 } 4500 4501 void rtw89_phy_antdiv_work(struct work_struct *work) 4502 { 4503 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4504 antdiv_work.work); 4505 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4506 4507 mutex_lock(&rtwdev->mutex); 4508 4509 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) { 4510 rtw89_phy_antdiv_training_state(rtwdev); 4511 } else { 4512 rtw89_phy_antdiv_decision_state(rtwdev); 4513 rtw89_phy_antdiv_set_ant(rtwdev); 4514 } 4515 4516 mutex_unlock(&rtwdev->mutex); 4517 } 4518 4519 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev) 4520 { 4521 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4522 struct rtw89_hal *hal = &rtwdev->hal; 4523 u8 rssi, rssi_pre; 4524 4525 if (!hal->ant_diversity || hal->ant_diversity_fixed) 4526 return; 4527 4528 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats); 4529 rssi_pre = antdiv->rssi_pre; 4530 antdiv->rssi_pre = rssi; 4531 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 4532 4533 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH) 4534 return; 4535 4536 antdiv->training_count = 0; 4537 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 0); 4538 } 4539 4540 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 4541 { 4542 rtw89_phy_ccx_top_setting_init(rtwdev); 4543 rtw89_phy_ifs_clm_setting_init(rtwdev); 4544 } 4545 4546 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 4547 { 4548 rtw89_phy_stat_init(rtwdev); 4549 4550 rtw89_chip_bb_sethw(rtwdev); 4551 4552 rtw89_phy_env_monitor_init(rtwdev); 4553 rtw89_physts_parsing_init(rtwdev); 4554 rtw89_phy_dig_init(rtwdev); 4555 rtw89_phy_cfo_init(rtwdev); 4556 rtw89_phy_ul_tb_info_init(rtwdev); 4557 rtw89_phy_antdiv_init(rtwdev); 4558 rtw89_chip_rfe_gpio(rtwdev); 4559 rtw89_phy_antdiv_set_ant(rtwdev); 4560 4561 rtw89_phy_init_rf_nctl(rtwdev); 4562 rtw89_chip_rfk_init(rtwdev); 4563 rtw89_chip_set_txpwr_ctrl(rtwdev); 4564 rtw89_chip_power_trim(rtwdev); 4565 rtw89_chip_cfg_txrx_path(rtwdev); 4566 } 4567 4568 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 4569 { 4570 const struct rtw89_chip_info *chip = rtwdev->chip; 4571 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 4572 u8 bss_color; 4573 4574 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4575 return; 4576 4577 bss_color = vif->bss_conf.he_bss_color.color; 4578 4579 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_VLD0, 0x1, 4580 phy_idx); 4581 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT, 4582 bss_color, phy_idx); 4583 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID, 4584 vif->cfg.aid, phy_idx); 4585 } 4586 4587 static void 4588 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4589 { 4590 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 4591 } 4592 4593 static void 4594 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4595 { 4596 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 4597 } 4598 4599 static void 4600 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4601 { 4602 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 4603 } 4604 4605 static void 4606 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4607 { 4608 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 4609 } 4610 4611 static void 4612 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4613 { 4614 udelay(def->data); 4615 } 4616 4617 static void 4618 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 4619 [RTW89_RFK_F_WRF] = _rfk_write_rf, 4620 [RTW89_RFK_F_WM] = _rfk_write32_mask, 4621 [RTW89_RFK_F_WS] = _rfk_write32_set, 4622 [RTW89_RFK_F_WC] = _rfk_write32_clr, 4623 [RTW89_RFK_F_DELAY] = _rfk_delay, 4624 }; 4625 4626 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 4627 4628 void 4629 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 4630 { 4631 const struct rtw89_reg5_def *p = tbl->defs; 4632 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 4633 4634 for (; p < end; p++) 4635 _rfk_handler[p->flag](rtwdev, p); 4636 } 4637 EXPORT_SYMBOL(rtw89_rfk_parser); 4638 4639 #define RTW89_TSSI_FAST_MODE_NUM 4 4640 4641 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 4642 {0xD934, 0xff0000}, 4643 {0xD934, 0xff000000}, 4644 {0xD938, 0xff}, 4645 {0xD934, 0xff00}, 4646 }; 4647 4648 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 4649 {0xD930, 0xff0000}, 4650 {0xD930, 0xff000000}, 4651 {0xD934, 0xff}, 4652 {0xD930, 0xff00}, 4653 }; 4654 4655 static 4656 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 4657 enum rtw89_mac_idx mac_idx, 4658 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 4659 u32 val) 4660 { 4661 const struct rtw89_reg_def *regs; 4662 u32 reg; 4663 int i; 4664 4665 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4666 regs = rtw89_tssi_fastmode_regs_flat; 4667 else 4668 regs = rtw89_tssi_fastmode_regs_level; 4669 4670 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 4671 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 4672 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 4673 } 4674 } 4675 4676 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 4677 {0xD91C, 0xff000000}, 4678 {0xD920, 0xff}, 4679 {0xD920, 0xff00}, 4680 {0xD920, 0xff0000}, 4681 {0xD920, 0xff000000}, 4682 {0xD924, 0xff}, 4683 {0xD924, 0xff00}, 4684 {0xD914, 0xff000000}, 4685 {0xD918, 0xff}, 4686 {0xD918, 0xff00}, 4687 {0xD918, 0xff0000}, 4688 {0xD918, 0xff000000}, 4689 {0xD91C, 0xff}, 4690 {0xD91C, 0xff00}, 4691 {0xD91C, 0xff0000}, 4692 }; 4693 4694 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 4695 {0xD910, 0xff}, 4696 {0xD910, 0xff00}, 4697 {0xD910, 0xff0000}, 4698 {0xD910, 0xff000000}, 4699 {0xD914, 0xff}, 4700 {0xD914, 0xff00}, 4701 {0xD914, 0xff0000}, 4702 {0xD908, 0xff}, 4703 {0xD908, 0xff00}, 4704 {0xD908, 0xff0000}, 4705 {0xD908, 0xff000000}, 4706 {0xD90C, 0xff}, 4707 {0xD90C, 0xff00}, 4708 {0xD90C, 0xff0000}, 4709 {0xD90C, 0xff000000}, 4710 }; 4711 4712 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 4713 enum rtw89_mac_idx mac_idx, 4714 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 4715 { 4716 const struct rtw89_chip_info *chip = rtwdev->chip; 4717 const struct rtw89_reg_def *regs; 4718 const u32 *data; 4719 u32 reg; 4720 int i; 4721 4722 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 4723 return; 4724 4725 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4726 regs = rtw89_tssi_bandedge_regs_flat; 4727 else 4728 regs = rtw89_tssi_bandedge_regs_level; 4729 4730 data = chip->tssi_dbw_table->data[bandedge_cfg]; 4731 4732 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 4733 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 4734 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 4735 } 4736 4737 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx); 4738 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 4739 4740 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 4741 data[RTW89_TSSI_SBW20]); 4742 } 4743 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 4744 4745 static 4746 const u8 rtw89_ch_base_table[16] = {1, 0xff, 4747 36, 100, 132, 149, 0xff, 4748 1, 33, 65, 97, 129, 161, 193, 225, 0xff}; 4749 #define RTW89_CH_BASE_IDX_2G 0 4750 #define RTW89_CH_BASE_IDX_5G_FIRST 2 4751 #define RTW89_CH_BASE_IDX_5G_LAST 5 4752 #define RTW89_CH_BASE_IDX_6G_FIRST 7 4753 #define RTW89_CH_BASE_IDX_6G_LAST 14 4754 4755 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4) 4756 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0) 4757 4758 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band) 4759 { 4760 u8 chan_idx; 4761 u8 last, first; 4762 u8 idx; 4763 4764 switch (band) { 4765 case RTW89_BAND_2G: 4766 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) | 4767 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch); 4768 return chan_idx; 4769 case RTW89_BAND_5G: 4770 first = RTW89_CH_BASE_IDX_5G_FIRST; 4771 last = RTW89_CH_BASE_IDX_5G_LAST; 4772 break; 4773 case RTW89_BAND_6G: 4774 first = RTW89_CH_BASE_IDX_6G_FIRST; 4775 last = RTW89_CH_BASE_IDX_6G_LAST; 4776 break; 4777 default: 4778 rtw89_warn(rtwdev, "Unsupported band %d\n", band); 4779 return 0; 4780 } 4781 4782 for (idx = last; idx >= first; idx--) 4783 if (central_ch >= rtw89_ch_base_table[idx]) 4784 break; 4785 4786 if (idx < first) { 4787 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch); 4788 return 0; 4789 } 4790 4791 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) | 4792 FIELD_PREP(RTW89_CH_OFFSET_MASK, 4793 (central_ch - rtw89_ch_base_table[idx]) >> 1); 4794 return chan_idx; 4795 } 4796 EXPORT_SYMBOL(rtw89_encode_chan_idx); 4797 4798 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 4799 u8 *ch, enum nl80211_band *band) 4800 { 4801 u8 idx, offset; 4802 4803 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx); 4804 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx); 4805 4806 if (idx == RTW89_CH_BASE_IDX_2G) { 4807 *band = NL80211_BAND_2GHZ; 4808 *ch = offset; 4809 return; 4810 } 4811 4812 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ; 4813 *ch = rtw89_ch_base_table[idx] + (offset << 1); 4814 } 4815 EXPORT_SYMBOL(rtw89_decode_chan_idx); 4816 4817 #define EDCCA_DEFAULT 249 4818 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan) 4819 { 4820 u32 reg = rtwdev->chip->edcca_lvl_reg; 4821 struct rtw89_hal *hal = &rtwdev->hal; 4822 u32 val; 4823 4824 if (scan) { 4825 hal->edcca_bak = rtw89_phy_read32(rtwdev, reg); 4826 val = hal->edcca_bak; 4827 u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_EDCCA_LVL_A_MSK); 4828 u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_EDCCA_LVL_P_MSK); 4829 u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_PPDU_LVL_MSK); 4830 rtw89_phy_write32(rtwdev, reg, val); 4831 } else { 4832 rtw89_phy_write32(rtwdev, reg, hal->edcca_bak); 4833 } 4834 } 4835 4836 static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = { 4837 .setting_addr = R_CCX, 4838 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK, 4839 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, 4840 .trig_opt_mask = B_CCX_TRIG_OPT_MSK, 4841 .en_mask = B_CCX_EN_MSK, 4842 .ifs_cnt_addr = R_IFS_COUNTER, 4843 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, 4844 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, 4845 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, 4846 .ifs_collect_en_mask = B_IFS_COLLECT_EN, 4847 .ifs_t1_addr = R_IFS_T1, 4848 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, 4849 .ifs_t1_en_mask = B_IFS_T1_EN_MSK, 4850 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, 4851 .ifs_t2_addr = R_IFS_T2, 4852 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, 4853 .ifs_t2_en_mask = B_IFS_T2_EN_MSK, 4854 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, 4855 .ifs_t3_addr = R_IFS_T3, 4856 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, 4857 .ifs_t3_en_mask = B_IFS_T3_EN_MSK, 4858 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, 4859 .ifs_t4_addr = R_IFS_T4, 4860 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, 4861 .ifs_t4_en_mask = B_IFS_T4_EN_MSK, 4862 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, 4863 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT, 4864 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, 4865 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, 4866 .ifs_clm_cca_addr = R_IFS_CLM_CCA, 4867 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, 4868 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, 4869 .ifs_clm_fa_addr = R_IFS_CLM_FA, 4870 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, 4871 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, 4872 .ifs_his_addr = R_IFS_HIS, 4873 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, 4874 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, 4875 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, 4876 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK, 4877 .ifs_avg_l_addr = R_IFS_AVG_L, 4878 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK, 4879 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK, 4880 .ifs_avg_h_addr = R_IFS_AVG_H, 4881 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK, 4882 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK, 4883 .ifs_cca_l_addr = R_IFS_CCA_L, 4884 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK, 4885 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK, 4886 .ifs_cca_h_addr = R_IFS_CCA_H, 4887 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK, 4888 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK, 4889 .ifs_total_addr = R_IFSCNT, 4890 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK, 4891 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK, 4892 }; 4893 4894 static const struct rtw89_physts_regs rtw89_physts_regs_ax = { 4895 .setting_addr = R_PLCP_HISTOGRAM, 4896 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, 4897 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, 4898 }; 4899 4900 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = { 4901 .cr_base = 0x10000, 4902 .ccx = &rtw89_ccx_regs_ax, 4903 .physts = &rtw89_physts_regs_ax, 4904 4905 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax, 4906 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax, 4907 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax, 4908 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax, 4909 }; 4910 EXPORT_SYMBOL(rtw89_phy_gen_ax); 4911