1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2023 Realtek Corporation 3 */ 4 5 #include <linux/pci.h> 6 7 #include "mac.h" 8 #include "pci.h" 9 #include "reg.h" 10 11 enum pcie_rxbd_mode { 12 PCIE_RXBD_NORM = 0, 13 PCIE_RXBD_SEP, 14 PCIE_RXBD_EXT, 15 }; 16 17 #define PL0_TMR_SCALE_ASIC 1 18 #define PL0_TMR_ANA_172US 0x800 19 #define PL0_TMR_MAC_1MS 0x27100 20 #define PL0_TMR_AUX_1MS 0x1E848 21 22 static void rtw89_pci_aspm_set_be(struct rtw89_dev *rtwdev, bool enable) 23 { 24 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 25 struct pci_dev *pdev = rtwpci->pdev; 26 u8 value = 0; 27 int ret; 28 29 ret = pci_read_config_byte(pdev, RTW89_PCIE_ASPM_CTRL, &value); 30 if (ret) 31 rtw89_warn(rtwdev, "failed to read ASPM Delay\n"); 32 33 u8p_replace_bits(&value, PCIE_L1DLY_16US, RTW89_L1DLY_MASK); 34 35 ret = pci_write_config_byte(pdev, RTW89_PCIE_ASPM_CTRL, value); 36 if (ret) 37 rtw89_warn(rtwdev, "failed to write ASPM Delay\n"); 38 39 if (enable) 40 rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1, 41 B_BE_ASPM_CTRL_L1); 42 else 43 rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1, 44 B_BE_ASPM_CTRL_L1); 45 } 46 47 static void rtw89_pci_l1ss_set_be(struct rtw89_dev *rtwdev, bool enable) 48 { 49 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 50 struct rtw89_hal *hal = &rtwdev->hal; 51 52 if (enable && chip_id == RTL8922D && hal->cid == RTL8922D_CID7090) 53 rtw89_write32_set(rtwdev, R_BE_PCIE_PS_CTRL, 54 B_BE_ASPM_L11_EN | B_BE_ASPM_L12_EN | 55 B_BE_PCIPM_L11_EN | B_BE_PCIPM_L12_EN); 56 57 if (enable) 58 rtw89_write32_set(rtwdev, R_BE_PCIE_MIX_CFG, 59 B_BE_L1SUB_ENABLE); 60 else 61 rtw89_write32_clr(rtwdev, R_BE_PCIE_MIX_CFG, 62 B_BE_L1SUB_ENABLE); 63 } 64 65 static void rtw89_pci_clkreq_set_be(struct rtw89_dev *rtwdev, bool enable) 66 { 67 rtw89_write32_mask(rtwdev, R_BE_PCIE_LAT_CTRL, B_BE_CLK_REQ_LAT_MASK, 68 PCIE_CLKDLY_HW_V1_0); 69 70 if (enable) 71 rtw89_write32_set(rtwdev, R_BE_L1_CLK_CTRL, 72 B_BE_CLK_PM_EN); 73 else 74 rtw89_write32_clr(rtwdev, R_AX_L1_CLK_CTRL, 75 B_BE_CLK_PM_EN); 76 } 77 78 static void _patch_pcie_power_wake_be(struct rtw89_dev *rtwdev, bool power_up) 79 { 80 if (power_up) 81 rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, BIT_WAKE_CTRL_V1); 82 else 83 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, BIT_WAKE_CTRL_V1); 84 } 85 86 static void rtw89_pci_set_io_rcy_be(struct rtw89_dev *rtwdev) 87 { 88 const struct rtw89_pci_info *info = rtwdev->pci_info; 89 u32 scale = PL0_TMR_SCALE_ASIC; 90 u32 val32; 91 92 if (info->io_rcy_en == MAC_AX_PCIE_ENABLE) { 93 val32 = info->io_rcy_tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ? 94 PL0_TMR_ANA_172US : info->io_rcy_tmr; 95 val32 /= scale; 96 97 rtw89_write32(rtwdev, R_BE_AON_WDT_TMR, val32); 98 rtw89_write32(rtwdev, R_BE_MDIO_WDT_TMR, val32); 99 rtw89_write32(rtwdev, R_BE_LA_MODE_WDT_TMR, val32); 100 rtw89_write32(rtwdev, R_BE_WDT_AR_TMR, val32); 101 rtw89_write32(rtwdev, R_BE_WDT_AW_TMR, val32); 102 rtw89_write32(rtwdev, R_BE_WDT_W_TMR, val32); 103 rtw89_write32(rtwdev, R_BE_WDT_B_TMR, val32); 104 rtw89_write32(rtwdev, R_BE_WDT_R_TMR, val32); 105 106 val32 = info->io_rcy_tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ? 107 PL0_TMR_MAC_1MS : info->io_rcy_tmr; 108 val32 /= scale; 109 rtw89_write32(rtwdev, R_BE_WLAN_WDT_TMR, val32); 110 rtw89_write32(rtwdev, R_BE_AXIDMA_WDT_TMR, val32); 111 112 val32 = info->io_rcy_tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ? 113 PL0_TMR_AUX_1MS : info->io_rcy_tmr; 114 val32 /= scale; 115 rtw89_write32(rtwdev, R_BE_LOCAL_WDT_TMR, val32); 116 } else { 117 rtw89_write32_clr(rtwdev, R_BE_WLAN_WDT, B_BE_WLAN_WDT_ENABLE); 118 rtw89_write32_clr(rtwdev, R_BE_AXIDMA_WDT, B_BE_AXIDMA_WDT_ENABLE); 119 rtw89_write32_clr(rtwdev, R_BE_AON_WDT, B_BE_AON_WDT_ENABLE); 120 rtw89_write32_clr(rtwdev, R_BE_LOCAL_WDT, B_BE_LOCAL_WDT_ENABLE); 121 rtw89_write32_clr(rtwdev, R_BE_MDIO_WDT, B_BE_MDIO_WDT_ENABLE); 122 rtw89_write32_clr(rtwdev, R_BE_LA_MODE_WDT, B_BE_LA_MODE_WDT_ENABLE); 123 rtw89_write32_clr(rtwdev, R_BE_WDT_AR, B_BE_WDT_AR_ENABLE); 124 rtw89_write32_clr(rtwdev, R_BE_WDT_AW, B_BE_WDT_AW_ENABLE); 125 rtw89_write32_clr(rtwdev, R_BE_WDT_W, B_BE_WDT_W_ENABLE); 126 rtw89_write32_clr(rtwdev, R_BE_WDT_B, B_BE_WDT_B_ENABLE); 127 rtw89_write32_clr(rtwdev, R_BE_WDT_R, B_BE_WDT_R_ENABLE); 128 } 129 } 130 131 static void rtw89_pci_ctrl_wpdma_pcie_be(struct rtw89_dev *rtwdev, bool en) 132 { 133 if (en) 134 rtw89_write32_clr(rtwdev, R_BE_HAXI_DMA_STOP1, B_BE_STOP_WPDMA); 135 else 136 rtw89_write32_set(rtwdev, R_BE_HAXI_DMA_STOP1, B_BE_STOP_WPDMA); 137 } 138 139 static void rtw89_pci_ctrl_trxdma_pcie_be(struct rtw89_dev *rtwdev, 140 enum mac_ax_pcie_func_ctrl tx_en, 141 enum mac_ax_pcie_func_ctrl rx_en, 142 enum mac_ax_pcie_func_ctrl io_en) 143 { 144 u32 val; 145 146 val = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1); 147 148 if (tx_en == MAC_AX_PCIE_ENABLE) 149 val |= B_BE_TXDMA_EN; 150 else if (tx_en == MAC_AX_PCIE_DISABLE) 151 val &= ~B_BE_TXDMA_EN; 152 153 if (rx_en == MAC_AX_PCIE_ENABLE) 154 val |= B_BE_RXDMA_EN; 155 else if (rx_en == MAC_AX_PCIE_DISABLE) 156 val &= ~B_BE_RXDMA_EN; 157 158 if (io_en == MAC_AX_PCIE_ENABLE) 159 val &= ~B_BE_STOP_AXI_MST; 160 else if (io_en == MAC_AX_PCIE_DISABLE) 161 val |= B_BE_STOP_AXI_MST; 162 163 rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val); 164 165 if (io_en == MAC_AX_PCIE_ENABLE && rtwdev->chip->chip_id == RTL8922A) 166 rtw89_write32_mask(rtwdev, R_BE_HAXI_MST_WDT_TIMEOUT_SEL_V1, 167 B_BE_HAXI_MST_WDT_TIMEOUT_SEL_MASK, 4); 168 } 169 170 static void rtw89_pci_clr_idx_all_be(struct rtw89_dev *rtwdev) 171 { 172 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 173 const struct rtw89_chip_info *chip = rtwdev->chip; 174 struct rtw89_pci_rx_ring *rx_ring; 175 u32 val; 176 177 if (chip->chip_id == RTL8922A) 178 val = B_BE_CLR_ALL_IDX_MASK; 179 else 180 val = B_BE_CLR_ALL_IDX_MASK_V1; 181 182 rtw89_write32(rtwdev, R_BE_TXBD_RWPTR_CLR1, val); 183 184 rtw89_write32(rtwdev, R_BE_RXBD_RWPTR_CLR1_V1, 185 B_BE_CLR_RXQ0_IDX | B_BE_CLR_RPQ0_IDX); 186 187 rx_ring = &rtwpci->rx.rings[RTW89_RXCH_RXQ]; 188 rtw89_write16(rtwdev, R_BE_RXQ0_RXBD_IDX_V1, rx_ring->bd_ring.len - 1); 189 190 rx_ring = &rtwpci->rx.rings[RTW89_RXCH_RPQ]; 191 rtw89_write16(rtwdev, R_BE_RPQ0_RXBD_IDX_V1, rx_ring->bd_ring.len - 1); 192 } 193 194 static int rtw89_pci_poll_txdma_ch_idle_be(struct rtw89_dev *rtwdev) 195 { 196 const struct rtw89_pci_info *info = rtwdev->pci_info; 197 u32 dma_busy1 = info->dma_busy1.addr; 198 u32 check = info->dma_busy1.mask; 199 u32 val; 200 201 return read_poll_timeout(rtw89_read32, val, (val & check) == 0, 202 10, 1000, false, rtwdev, dma_busy1); 203 } 204 205 static int rtw89_pci_poll_rxdma_ch_idle_be(struct rtw89_dev *rtwdev) 206 { 207 u32 check; 208 u32 val; 209 210 check = B_BE_RXQ0_BUSY_V1 | B_BE_RPQ0_BUSY_V1; 211 212 return read_poll_timeout(rtw89_read32, val, (val & check) == 0, 213 10, 1000, false, rtwdev, R_BE_HAXI_DMA_BUSY1); 214 } 215 216 static int rtw89_pci_poll_dma_all_idle_be(struct rtw89_dev *rtwdev) 217 { 218 int ret; 219 220 ret = rtw89_pci_poll_txdma_ch_idle_be(rtwdev); 221 if (ret) { 222 rtw89_err(rtwdev, "txdma ch busy\n"); 223 return ret; 224 } 225 226 ret = rtw89_pci_poll_rxdma_ch_idle_be(rtwdev); 227 if (ret) { 228 rtw89_err(rtwdev, "rxdma ch busy\n"); 229 return ret; 230 } 231 232 return 0; 233 } 234 235 static void rtw89_pci_mode_op_be(struct rtw89_dev *rtwdev) 236 { 237 const struct rtw89_pci_info *info = rtwdev->pci_info; 238 const struct rtw89_chip_info *chip = rtwdev->chip; 239 u32 val32_init1, val32_rxapp, val32_exp; 240 241 val32_init1 = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1); 242 if (chip->chip_id == RTL8922A) 243 val32_rxapp = rtw89_read32(rtwdev, R_BE_RX_APPEND_MODE); 244 val32_exp = rtw89_read32(rtwdev, R_BE_HAXI_EXP_CTRL_V1); 245 246 if (chip->chip_id == RTL8922A) { 247 if (info->rxbd_mode == MAC_AX_RXBD_PKT) { 248 val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_NORM, 249 B_BE_RXQ_RXBD_MODE_MASK); 250 } else if (info->rxbd_mode == MAC_AX_RXBD_SEP) { 251 val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_SEP, 252 B_BE_RXQ_RXBD_MODE_MASK); 253 val32_rxapp = u32_replace_bits(val32_rxapp, 0, 254 B_BE_APPEND_LEN_MASK); 255 } 256 } 257 258 val32_init1 = u32_replace_bits(val32_init1, info->tx_burst, 259 B_BE_MAX_TXDMA_MASK); 260 val32_init1 = u32_replace_bits(val32_init1, info->rx_burst, 261 B_BE_MAX_RXDMA_MASK); 262 val32_exp = u32_replace_bits(val32_exp, info->multi_tag_num, 263 B_BE_MAX_TAG_NUM_MASK); 264 val32_init1 = u32_replace_bits(val32_init1, info->wd_dma_idle_intvl, 265 B_BE_CFG_WD_PERIOD_IDLE_MASK); 266 val32_init1 = u32_replace_bits(val32_init1, info->wd_dma_act_intvl, 267 B_BE_CFG_WD_PERIOD_ACTIVE_MASK); 268 269 rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val32_init1); 270 if (chip->chip_id == RTL8922A) 271 rtw89_write32(rtwdev, R_BE_RX_APPEND_MODE, val32_rxapp); 272 rtw89_write32(rtwdev, R_BE_HAXI_EXP_CTRL_V1, val32_exp); 273 } 274 275 static int rtw89_pci_rst_bdram_be(struct rtw89_dev *rtwdev) 276 { 277 u32 val; 278 279 rtw89_write32_set(rtwdev, R_BE_HAXI_INIT_CFG1, B_BE_SET_BDRAM_BOUND); 280 281 return read_poll_timeout(rtw89_read32, val, !(val & B_BE_SET_BDRAM_BOUND), 282 50, 500000, false, rtwdev, R_BE_HAXI_INIT_CFG1); 283 } 284 285 static void rtw89_pci_debounce_be(struct rtw89_dev *rtwdev) 286 { 287 u32 val32; 288 289 val32 = rtw89_read32(rtwdev, R_BE_SYS_PAGE_CLK_GATED); 290 val32 = u32_replace_bits(val32, 0, B_BE_PCIE_PRST_DEBUNC_PERIOD_MASK); 291 val32 |= B_BE_SYM_PRST_DEBUNC_SEL; 292 rtw89_write32(rtwdev, R_BE_SYS_PAGE_CLK_GATED, val32); 293 } 294 295 static void rtw89_pci_ldo_low_pwr_be(struct rtw89_dev *rtwdev) 296 { 297 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 298 struct rtw89_hal *hal = &rtwdev->hal; 299 u32 clr; 300 301 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_PSUS_OFF_CAPC_EN); 302 rtw89_write32_set(rtwdev, R_BE_SYS_PAGE_CLK_GATED, 303 B_BE_SOP_OFFPOOBS_PC | B_BE_CPHY_AUXCLK_OP | 304 B_BE_CPHY_POWER_READY_CHK); 305 rtw89_write32_clr(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_PCIE_FORCE_IBX_EN | 306 B_BE_PCIE_DIS_L2_RTK_PERST | 307 B_BE_PCIE_DIS_L2__CTRL_LDO_HCI); 308 309 if (chip_id == RTL8922D && hal->cid == RTL8922D_CID7090) 310 clr = B_BE_PCIE_DIS_L1_2_CTRL_HCILDO | 311 B_BE_PCIE_DIS_L1_2_CTRL_APHY_SUSB | 312 B_BE_PCIE_DIS_RTK_PRST_N_L1_2 | 313 B_BE_PCIE_DIS_L2_CTRL_APHY_SUSB; 314 else 315 clr = B_BE_PCIE_DIS_L1_2_CTRL_HCILDO; 316 317 rtw89_write32_clr(rtwdev, R_BE_L1_2_CTRL_HCILDO, clr); 318 } 319 320 static void rtw89_pci_pcie_setting_be(struct rtw89_dev *rtwdev) 321 { 322 const struct rtw89_chip_info *chip = rtwdev->chip; 323 struct rtw89_hal *hal = &rtwdev->hal; 324 325 rtw89_write32_set(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_EN_AUX_CLK); 326 rtw89_write32_clr(rtwdev, R_BE_PCIE_PS_CTRL, B_BE_CMAC_EXIT_L1_EN); 327 328 if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) 329 return; 330 331 rtw89_write32_set(rtwdev, R_BE_EFUSE_CTRL_2_V1, B_BE_R_SYM_AUTOLOAD_WITH_PMC_SEL); 332 rtw89_write32_set(rtwdev, R_BE_PCIE_LAT_CTRL, B_BE_SYM_AUX_CLK_SEL); 333 334 if (chip->chip_id != RTL8922D) 335 return; 336 337 rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_R_SYM_PRST_CPHY_RST); 338 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_USUS_OFFCAPC_EN); 339 } 340 341 static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev) 342 { 343 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 344 struct rtw89_hal *hal = &rtwdev->hal; 345 u32 val32; 346 int ret; 347 348 if (chip_id == RTL8922D) 349 goto be2_chips; 350 else if (chip_id != RTL8922A) 351 return; 352 353 rtw89_write32(rtwdev, R_BE_PL1_DBG_INFO, 0x0); 354 rtw89_write32_set(rtwdev, R_BE_FWS1IMR, B_BE_PCIE_SER_TIMEOUT_INDIC_EN); 355 rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN); 356 rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_TIMER_UNIT_MASK, 1); 357 358 val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK); 359 val32 |= B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR | B_BE_SER_PM_MASTER_IMR | 360 B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK; 361 rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32); 362 363 return; 364 365 be2_chips: 366 rtw89_write32_clr(rtwdev, R_BE_PCIE_SER_DBG, B_BE_PCIE_SER_FLUSH_RSTB); 367 rtw89_write32_set(rtwdev, R_BE_PCIE_SER_DBG, B_BE_PCIE_SER_FLUSH_RSTB); 368 369 rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G1 + 370 RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN); 371 rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G2 + 372 RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN); 373 rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G1 + 374 RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN); 375 rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G2 + 376 RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN); 377 378 val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL); 379 val32 &= ~B_BE_PL1_SER_PL1_EN; 380 rtw89_write32(rtwdev, R_BE_SER_PL1_CTRL, val32); 381 382 ret = read_poll_timeout_atomic(rtw89_read32, val32, !val32, 383 1, 1000, false, rtwdev, R_BE_REG_PL1_ISR); 384 if (ret) 385 rtw89_warn(rtwdev, "[ERR] PCIE SER clear poll fail\n"); 386 387 val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK); 388 val32 |= B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR | B_BE_SER_PM_MASTER_IMR | 389 B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK | 390 B_BE_SER_LTSSM_UNSTABLE_MASK; 391 rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32); 392 393 rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_TIMER_UNIT_MASK, 394 PCIE_SER_TIMER_UNIT); 395 rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN); 396 397 if (hal->cid == RTL8922D_CID7090) 398 rtw89_write32_set(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_SER_DETECT_EN); 399 } 400 401 static void rtw89_pci_ctrl_txdma_ch_be(struct rtw89_dev *rtwdev, bool enable) 402 { 403 const struct rtw89_pci_info *info = rtwdev->pci_info; 404 u32 mask_all; 405 u32 val; 406 407 mask_all = B_BE_STOP_CH0 | B_BE_STOP_CH1 | B_BE_STOP_CH2 | 408 B_BE_STOP_CH3 | B_BE_STOP_CH4 | B_BE_STOP_CH5 | 409 B_BE_STOP_CH6 | B_BE_STOP_CH7 | B_BE_STOP_CH8 | 410 B_BE_STOP_CH9 | B_BE_STOP_CH10 | B_BE_STOP_CH11; 411 412 /* mask out unsupported channels for certains chips */ 413 mask_all &= info->dma_stop1.mask; 414 415 val = rtw89_read32(rtwdev, R_BE_HAXI_DMA_STOP1); 416 val |= B_BE_STOP_CH13 | B_BE_STOP_CH14; 417 418 if (enable) 419 val &= ~mask_all; 420 else 421 val |= mask_all; 422 423 rtw89_write32(rtwdev, R_BE_HAXI_DMA_STOP1, val); 424 } 425 426 static void rtw89_pci_ctrl_txdma_fw_ch_be(struct rtw89_dev *rtwdev, bool enable) 427 { 428 u32 val = rtw89_read32(rtwdev, R_BE_HAXI_DMA_STOP1); 429 430 if (enable) 431 val &= ~B_BE_STOP_CH12; 432 else 433 val |= B_BE_STOP_CH12; 434 435 rtw89_write32(rtwdev, R_BE_HAXI_DMA_STOP1, val); 436 } 437 438 static int rtw89_pci_ops_mac_pre_init_be(struct rtw89_dev *rtwdev) 439 { 440 int ret; 441 442 rtw89_pci_set_io_rcy_be(rtwdev); 443 _patch_pcie_power_wake_be(rtwdev, true); 444 rtw89_pci_ctrl_wpdma_pcie_be(rtwdev, false); 445 rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_DISABLE, 446 MAC_AX_PCIE_DISABLE, MAC_AX_PCIE_DISABLE); 447 rtw89_pci_clr_idx_all_be(rtwdev); 448 449 ret = rtw89_pci_poll_dma_all_idle_be(rtwdev); 450 if (ret) { 451 rtw89_err(rtwdev, "[ERR] poll pcie dma all idle\n"); 452 return ret; 453 } 454 455 rtw89_pci_mode_op_be(rtwdev); 456 rtw89_pci_ops_reset(rtwdev); 457 458 ret = rtw89_pci_rst_bdram_be(rtwdev); 459 if (ret) { 460 rtw89_err(rtwdev, "[ERR]pcie rst bdram\n"); 461 return ret; 462 } 463 464 rtw89_pci_debounce_be(rtwdev); 465 rtw89_pci_ldo_low_pwr_be(rtwdev); 466 rtw89_pci_pcie_setting_be(rtwdev); 467 rtw89_pci_ser_setting_be(rtwdev); 468 469 rtw89_pci_ctrl_txdma_ch_be(rtwdev, false); 470 rtw89_pci_ctrl_txdma_fw_ch_be(rtwdev, true); 471 rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_ENABLE, 472 MAC_AX_PCIE_ENABLE, MAC_AX_PCIE_ENABLE); 473 474 return 0; 475 } 476 477 static int rtw89_pci_ops_mac_pre_deinit_be(struct rtw89_dev *rtwdev) 478 { 479 u32 val; 480 481 _patch_pcie_power_wake_be(rtwdev, false); 482 483 val = rtw89_read32_mask(rtwdev, R_BE_IC_PWR_STATE, B_BE_WLMAC_PWR_STE_MASK); 484 if (val == 0) 485 return 0; 486 487 rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_DISABLE, 488 MAC_AX_PCIE_DISABLE, MAC_AX_PCIE_DISABLE); 489 rtw89_pci_clr_idx_all_be(rtwdev); 490 491 return 0; 492 } 493 494 int rtw89_pci_ltr_set_v2(struct rtw89_dev *rtwdev, bool en) 495 { 496 u32 ctrl0, cfg0, cfg1, dec_ctrl, idle_ltcy, act_ltcy, dis_ltcy; 497 u32 ltr_idle_lat_ctrl, ltr_act_lat_ctrl; 498 499 ctrl0 = rtw89_read32(rtwdev, R_BE_LTR_CTRL_0); 500 if (rtw89_pci_ltr_is_err_reg_val(ctrl0)) 501 return -EINVAL; 502 cfg0 = rtw89_read32(rtwdev, R_BE_LTR_CFG_0); 503 if (rtw89_pci_ltr_is_err_reg_val(cfg0)) 504 return -EINVAL; 505 cfg1 = rtw89_read32(rtwdev, R_BE_LTR_CFG_1); 506 if (rtw89_pci_ltr_is_err_reg_val(cfg1)) 507 return -EINVAL; 508 dec_ctrl = rtw89_read32(rtwdev, R_BE_LTR_DECISION_CTRL_V1); 509 if (rtw89_pci_ltr_is_err_reg_val(dec_ctrl)) 510 return -EINVAL; 511 idle_ltcy = rtw89_read32(rtwdev, R_BE_LTR_LATENCY_IDX3_V1); 512 if (rtw89_pci_ltr_is_err_reg_val(idle_ltcy)) 513 return -EINVAL; 514 act_ltcy = rtw89_read32(rtwdev, R_BE_LTR_LATENCY_IDX1_V1); 515 if (rtw89_pci_ltr_is_err_reg_val(act_ltcy)) 516 return -EINVAL; 517 dis_ltcy = rtw89_read32(rtwdev, R_BE_LTR_LATENCY_IDX0_V1); 518 if (rtw89_pci_ltr_is_err_reg_val(dis_ltcy)) 519 return -EINVAL; 520 521 if (en) { 522 dec_ctrl |= B_BE_ENABLE_LTR_CTL_DECISION | B_BE_LTR_HW_DEC_EN_V1; 523 ctrl0 |= B_BE_LTR_HW_EN; 524 } else { 525 dec_ctrl &= ~(B_BE_ENABLE_LTR_CTL_DECISION | B_BE_LTR_HW_DEC_EN_V1 | 526 B_BE_LTR_EN_PORT_V1_MASK); 527 ctrl0 &= ~B_BE_LTR_HW_EN; 528 } 529 530 dec_ctrl = u32_replace_bits(dec_ctrl, PCI_LTR_SPC_500US, 531 B_BE_LTR_SPACE_IDX_MASK); 532 cfg0 = u32_replace_bits(cfg0, PCI_LTR_IDLE_TIMER_3_2MS, 533 B_BE_LTR_IDLE_TIMER_IDX_MASK); 534 cfg1 = u32_replace_bits(cfg1, 0xC0, B_BE_LTR_CMAC0_RX_USE_PG_TH_MASK); 535 cfg1 = u32_replace_bits(cfg1, 0xC0, B_BE_LTR_CMAC1_RX_USE_PG_TH_MASK); 536 cfg0 = u32_replace_bits(cfg0, 1, B_BE_LTR_IDX_ACTIVE_MASK); 537 cfg0 = u32_replace_bits(cfg0, 3, B_BE_LTR_IDX_IDLE_MASK); 538 dec_ctrl = u32_replace_bits(dec_ctrl, 0, B_BE_LTR_IDX_DISABLE_V1_MASK); 539 540 if (rtwdev->chip->chip_id == RTL8922A) { 541 ltr_idle_lat_ctrl = 0x90039003; 542 ltr_act_lat_ctrl = 0x880b880b; 543 } else { 544 ltr_idle_lat_ctrl = 0x90019001; 545 ltr_act_lat_ctrl = 0x88018801; 546 } 547 548 rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX3_V1, ltr_idle_lat_ctrl); 549 rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX1_V1, ltr_act_lat_ctrl); 550 rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX0_V1, 0); 551 rtw89_write32(rtwdev, R_BE_LTR_DECISION_CTRL_V1, dec_ctrl); 552 rtw89_write32(rtwdev, R_BE_LTR_CFG_0, cfg0); 553 rtw89_write32(rtwdev, R_BE_LTR_CFG_1, cfg1); 554 rtw89_write32(rtwdev, R_BE_LTR_CTRL_0, ctrl0); 555 556 return 0; 557 } 558 EXPORT_SYMBOL(rtw89_pci_ltr_set_v2); 559 560 static void rtw89_pci_configure_mit_be(struct rtw89_dev *rtwdev) 561 { 562 u32 cnt; 563 u32 val; 564 565 rtw89_write32_mask(rtwdev, R_BE_PCIE_MIT0_TMR, 566 B_BE_PCIE_MIT0_RX_TMR_MASK, BE_MIT0_TMR_UNIT_1MS); 567 568 val = rtw89_read32(rtwdev, R_BE_PCIE_MIT0_CNT); 569 cnt = min_t(u32, U8_MAX, RTW89_PCI_RXBD_NUM_MAX / 2); 570 val = u32_replace_bits(val, cnt, B_BE_PCIE_RX_MIT0_CNT_MASK); 571 val = u32_replace_bits(val, 2, B_BE_PCIE_RX_MIT0_TMR_CNT_MASK); 572 rtw89_write32(rtwdev, R_BE_PCIE_MIT0_CNT, val); 573 } 574 575 static int rtw89_pci_ops_mac_post_init_be(struct rtw89_dev *rtwdev) 576 { 577 const struct rtw89_pci_info *info = rtwdev->pci_info; 578 int ret; 579 580 ret = info->ltr_set(rtwdev, true); 581 if (ret) { 582 rtw89_err(rtwdev, "pci ltr set fail\n"); 583 return ret; 584 } 585 586 rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_IGNORE, 587 MAC_AX_PCIE_IGNORE, MAC_AX_PCIE_ENABLE); 588 rtw89_pci_ctrl_wpdma_pcie_be(rtwdev, true); 589 rtw89_pci_ctrl_txdma_ch_be(rtwdev, true); 590 rtw89_pci_ctrl_txdma_fw_ch_be(rtwdev, true); 591 rtw89_pci_configure_mit_be(rtwdev); 592 593 return 0; 594 } 595 596 static int rtw89_pci_poll_io_idle_be(struct rtw89_dev *rtwdev) 597 { 598 u32 sts; 599 int ret; 600 601 ret = read_poll_timeout_atomic(rtw89_read32, sts, 602 !(sts & B_BE_HAXI_MST_BUSY), 603 10, 1000, false, rtwdev, 604 R_BE_HAXI_DMA_BUSY1); 605 if (ret) { 606 rtw89_err(rtwdev, "pci dmach busy1 0x%X\n", sts); 607 return ret; 608 } 609 610 return 0; 611 } 612 613 static int rtw89_pci_lv1rst_stop_dma_be(struct rtw89_dev *rtwdev) 614 { 615 int ret; 616 617 rtw89_pci_ctrl_dma_all(rtwdev, false); 618 ret = rtw89_pci_poll_io_idle_be(rtwdev); 619 if (!ret) 620 return 0; 621 622 rtw89_debug(rtwdev, RTW89_DBG_HCI, 623 "[PCIe] poll_io_idle fail; reset hci dma trx\n"); 624 625 rtw89_mac_ctrl_hci_dma_trx(rtwdev, false); 626 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 627 628 return rtw89_pci_poll_io_idle_be(rtwdev); 629 } 630 631 static int rtw89_pci_lv1rst_start_dma_be(struct rtw89_dev *rtwdev) 632 { 633 int ret; 634 635 rtw89_mac_ctrl_hci_dma_trx(rtwdev, false); 636 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 637 rtw89_pci_clr_idx_all(rtwdev); 638 639 ret = rtw89_pci_rst_bdram_be(rtwdev); 640 if (ret) 641 return ret; 642 643 rtw89_pci_ctrl_dma_all(rtwdev, true); 644 return 0; 645 } 646 647 static void rtw89_pci_disable_eq_be(struct rtw89_dev *rtwdev) 648 { 649 u32 backup_aspm, phy_offset; 650 u16 oobs_val, offset_cal; 651 u16 g1_oobs, g2_oobs; 652 u8 gen; 653 654 if (rtwdev->chip->chip_id != RTL8922A) 655 return; 656 657 g1_oobs = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G1 + 658 RAC_ANA09 * RAC_MULT, BAC_OOBS_SEL); 659 g2_oobs = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G2 + 660 RAC_ANA09 * RAC_MULT, BAC_OOBS_SEL); 661 if (g1_oobs && g2_oobs) 662 return; 663 664 backup_aspm = rtw89_read32(rtwdev, R_BE_PCIE_MIX_CFG); 665 rtw89_write32_clr(rtwdev, R_BE_PCIE_MIX_CFG, B_BE_RTK_ASPM_CTRL_MASK); 666 667 /* offset K */ 668 for (gen = 1; gen <= 2; gen++) { 669 phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 : 670 R_RAC_DIRECT_OFFSET_BE_LANE0_G2; 671 672 rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT, 673 B_PCIE_BIT_RD_SEL); 674 } 675 676 offset_cal = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G1 + 677 RAC_ANA1F * RAC_MULT, OFFSET_CAL_MASK); 678 679 for (gen = 1; gen <= 2; gen++) { 680 phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 : 681 R_RAC_DIRECT_OFFSET_BE_LANE0_G2; 682 683 rtw89_write16_mask(rtwdev, phy_offset + RAC_ANA0B * RAC_MULT, 684 MANUAL_LVL_MASK, offset_cal); 685 rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT, 686 OFFSET_CAL_MODE); 687 } 688 689 /* OOBS */ 690 for (gen = 1; gen <= 2; gen++) { 691 phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 : 692 R_RAC_DIRECT_OFFSET_BE_LANE0_G2; 693 694 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT, 695 BAC_RX_TEST_EN); 696 rtw89_write16_mask(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT, 697 ADDR_SEL_MASK, ADDR_SEL_VAL); 698 rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT, 699 B_PCIE_BIT_PINOUT_DIS); 700 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT, 701 B_PCIE_BIT_RD_SEL); 702 } 703 704 oobs_val = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G1 + 705 RAC_ANA1F * RAC_MULT, OOBS_LEVEL_MASK); 706 707 for (gen = 1; gen <= 2; gen++) { 708 phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 : 709 R_RAC_DIRECT_OFFSET_BE_LANE0_G2; 710 711 rtw89_write16_mask(rtwdev, phy_offset + RAC_ANA03 * RAC_MULT, 712 OOBS_SEN_MASK, oobs_val); 713 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA09 * RAC_MULT, 714 BAC_OOBS_SEL); 715 } 716 717 rtw89_write32(rtwdev, R_BE_PCIE_MIX_CFG, backup_aspm); 718 } 719 720 static int __maybe_unused rtw89_pci_suspend_be(struct device *dev) 721 { 722 struct ieee80211_hw *hw = dev_get_drvdata(dev); 723 struct rtw89_dev *rtwdev = hw->priv; 724 725 rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6); 726 rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_R_DIS_PRST); 727 rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6); 728 rtw89_write32_set(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_FRZ_REG_RST); 729 rtw89_write32_clr(rtwdev, R_BE_REG_PL1_MASK, B_BE_SER_PM_MASTER_IMR); 730 return 0; 731 } 732 733 static int __maybe_unused rtw89_pci_resume_be(struct device *dev) 734 { 735 struct ieee80211_hw *hw = dev_get_drvdata(dev); 736 struct rtw89_dev *rtwdev = hw->priv; 737 u32 polling; 738 int ret; 739 740 rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6); 741 rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_R_DIS_PRST); 742 rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6); 743 rtw89_write32_clr(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_FRZ_REG_RST); 744 rtw89_write32_clr(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN); 745 746 ret = read_poll_timeout_atomic(rtw89_read32, polling, !polling, 1, 1000, 747 false, rtwdev, R_BE_REG_PL1_ISR); 748 if (ret) 749 rtw89_warn(rtwdev, "[ERR] PCIE SER clear polling fail\n"); 750 751 rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN); 752 rtw89_write32_set(rtwdev, R_BE_REG_PL1_MASK, B_BE_SER_PM_MASTER_IMR); 753 754 rtw89_pci_basic_cfg(rtwdev, true); 755 756 return 0; 757 } 758 759 SIMPLE_DEV_PM_OPS(rtw89_pm_ops_be, rtw89_pci_suspend_be, rtw89_pci_resume_be); 760 EXPORT_SYMBOL(rtw89_pm_ops_be); 761 762 const struct rtw89_pci_isr_def rtw89_pci_isr_be = { 763 .isr_rdu = B_BE_RDU_CH1_INT_V1 | B_BE_RDU_CH0_INT_V1, 764 .isr_halt_c2h = B_BE_HALT_C2H_INT, 765 .isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT, 766 .isr_sps_ocp = 0, 767 .isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1}, 768 .isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1}, 769 }; 770 EXPORT_SYMBOL(rtw89_pci_isr_be); 771 772 const struct rtw89_pci_isr_def rtw89_pci_isr_be_v1 = { 773 .isr_rdu = B_BE_PCIE_RDU_CH1_INT | B_BE_PCIE_RDU_CH0_INT, 774 .isr_halt_c2h = B_BE_HALT_C2H_INT, 775 .isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT, 776 .isr_sps_ocp = B_BE_SPS_OCP_INT | B_BE_SPSANA_OCP_INT, 777 .isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1}, 778 .isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1}, 779 }; 780 EXPORT_SYMBOL(rtw89_pci_isr_be_v1); 781 782 const struct rtw89_pci_gen_def rtw89_pci_gen_be = { 783 .mac_pre_init = rtw89_pci_ops_mac_pre_init_be, 784 .mac_pre_deinit = rtw89_pci_ops_mac_pre_deinit_be, 785 .mac_post_init = rtw89_pci_ops_mac_post_init_be, 786 787 .clr_idx_all = rtw89_pci_clr_idx_all_be, 788 .rst_bdram = rtw89_pci_rst_bdram_be, 789 790 .lv1rst_stop_dma = rtw89_pci_lv1rst_stop_dma_be, 791 .lv1rst_start_dma = rtw89_pci_lv1rst_start_dma_be, 792 793 .ctrl_txdma_ch = rtw89_pci_ctrl_txdma_ch_be, 794 .ctrl_txdma_fw_ch = rtw89_pci_ctrl_txdma_fw_ch_be, 795 .poll_txdma_ch_idle = rtw89_pci_poll_txdma_ch_idle_be, 796 797 .aspm_set = rtw89_pci_aspm_set_be, 798 .clkreq_set = rtw89_pci_clkreq_set_be, 799 .l1ss_set = rtw89_pci_l1ss_set_be, 800 801 .disable_eq = rtw89_pci_disable_eq_be, 802 .power_wake = _patch_pcie_power_wake_be, 803 }; 804 EXPORT_SYMBOL(rtw89_pci_gen_be); 805