1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2023 Realtek Corporation 3 */ 4 5 #include <linux/pci.h> 6 7 #include "mac.h" 8 #include "pci.h" 9 #include "reg.h" 10 11 enum pcie_rxbd_mode { 12 PCIE_RXBD_NORM = 0, 13 PCIE_RXBD_SEP, 14 PCIE_RXBD_EXT, 15 }; 16 17 #define PL0_TMR_SCALE_ASIC 1 18 #define PL0_TMR_ANA_172US 0x800 19 #define PL0_TMR_MAC_1MS 0x27100 20 #define PL0_TMR_AUX_1MS 0x1E848 21 22 static void _patch_pcie_power_wake_be(struct rtw89_dev *rtwdev, bool power_up) 23 { 24 if (power_up) 25 rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, BIT_WAKE_CTRL_V1); 26 else 27 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, BIT_WAKE_CTRL_V1); 28 } 29 30 static void rtw89_pci_set_io_rcy_be(struct rtw89_dev *rtwdev) 31 { 32 const struct rtw89_pci_info *info = rtwdev->pci_info; 33 u32 scale = PL0_TMR_SCALE_ASIC; 34 u32 val32; 35 36 if (info->io_rcy_en == MAC_AX_PCIE_ENABLE) { 37 val32 = info->io_rcy_tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ? 38 PL0_TMR_ANA_172US : info->io_rcy_tmr; 39 val32 /= scale; 40 41 rtw89_write32(rtwdev, R_BE_AON_WDT_TMR, val32); 42 rtw89_write32(rtwdev, R_BE_MDIO_WDT_TMR, val32); 43 rtw89_write32(rtwdev, R_BE_LA_MODE_WDT_TMR, val32); 44 rtw89_write32(rtwdev, R_BE_WDT_AR_TMR, val32); 45 rtw89_write32(rtwdev, R_BE_WDT_AW_TMR, val32); 46 rtw89_write32(rtwdev, R_BE_WDT_W_TMR, val32); 47 rtw89_write32(rtwdev, R_BE_WDT_B_TMR, val32); 48 rtw89_write32(rtwdev, R_BE_WDT_R_TMR, val32); 49 50 val32 = info->io_rcy_tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ? 51 PL0_TMR_MAC_1MS : info->io_rcy_tmr; 52 val32 /= scale; 53 rtw89_write32(rtwdev, R_BE_WLAN_WDT_TMR, val32); 54 rtw89_write32(rtwdev, R_BE_AXIDMA_WDT_TMR, val32); 55 56 val32 = info->io_rcy_tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ? 57 PL0_TMR_AUX_1MS : info->io_rcy_tmr; 58 val32 /= scale; 59 rtw89_write32(rtwdev, R_BE_LOCAL_WDT_TMR, val32); 60 } else { 61 rtw89_write32_clr(rtwdev, R_BE_WLAN_WDT, B_BE_WLAN_WDT_ENABLE); 62 rtw89_write32_clr(rtwdev, R_BE_AXIDMA_WDT, B_BE_AXIDMA_WDT_ENABLE); 63 rtw89_write32_clr(rtwdev, R_BE_AON_WDT, B_BE_AON_WDT_ENABLE); 64 rtw89_write32_clr(rtwdev, R_BE_LOCAL_WDT, B_BE_LOCAL_WDT_ENABLE); 65 rtw89_write32_clr(rtwdev, R_BE_MDIO_WDT, B_BE_MDIO_WDT_ENABLE); 66 rtw89_write32_clr(rtwdev, R_BE_LA_MODE_WDT, B_BE_LA_MODE_WDT_ENABLE); 67 rtw89_write32_clr(rtwdev, R_BE_WDT_AR, B_BE_WDT_AR_ENABLE); 68 rtw89_write32_clr(rtwdev, R_BE_WDT_AW, B_BE_WDT_AW_ENABLE); 69 rtw89_write32_clr(rtwdev, R_BE_WDT_W, B_BE_WDT_W_ENABLE); 70 rtw89_write32_clr(rtwdev, R_BE_WDT_B, B_BE_WDT_B_ENABLE); 71 rtw89_write32_clr(rtwdev, R_BE_WDT_R, B_BE_WDT_R_ENABLE); 72 } 73 } 74 75 static void rtw89_pci_ctrl_wpdma_pcie_be(struct rtw89_dev *rtwdev, bool en) 76 { 77 if (en) 78 rtw89_write32_clr(rtwdev, R_BE_HAXI_DMA_STOP1, B_BE_STOP_WPDMA); 79 else 80 rtw89_write32_set(rtwdev, R_BE_HAXI_DMA_STOP1, B_BE_STOP_WPDMA); 81 } 82 83 static void rtw89_pci_ctrl_trxdma_pcie_be(struct rtw89_dev *rtwdev, 84 enum mac_ax_pcie_func_ctrl tx_en, 85 enum mac_ax_pcie_func_ctrl rx_en, 86 enum mac_ax_pcie_func_ctrl io_en) 87 { 88 u32 val; 89 90 val = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1); 91 92 if (tx_en == MAC_AX_PCIE_ENABLE) 93 val |= B_BE_TXDMA_EN; 94 else if (tx_en == MAC_AX_PCIE_DISABLE) 95 val &= ~B_BE_TXDMA_EN; 96 97 if (rx_en == MAC_AX_PCIE_ENABLE) 98 val |= B_BE_RXDMA_EN; 99 else if (rx_en == MAC_AX_PCIE_DISABLE) 100 val &= ~B_BE_RXDMA_EN; 101 102 if (io_en == MAC_AX_PCIE_ENABLE) 103 val &= ~B_BE_STOP_AXI_MST; 104 else if (io_en == MAC_AX_PCIE_DISABLE) 105 val |= B_BE_STOP_AXI_MST; 106 107 rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val); 108 109 if (io_en == MAC_AX_PCIE_ENABLE) 110 rtw89_write32_mask(rtwdev, R_BE_HAXI_MST_WDT_TIMEOUT_SEL_V1, 111 B_BE_HAXI_MST_WDT_TIMEOUT_SEL_MASK, 4); 112 } 113 114 static void rtw89_pci_clr_idx_all_be(struct rtw89_dev *rtwdev) 115 { 116 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 117 struct rtw89_pci_rx_ring *rx_ring; 118 u32 val; 119 120 val = B_BE_CLR_CH0_IDX | B_BE_CLR_CH1_IDX | B_BE_CLR_CH2_IDX | 121 B_BE_CLR_CH3_IDX | B_BE_CLR_CH4_IDX | B_BE_CLR_CH5_IDX | 122 B_BE_CLR_CH6_IDX | B_BE_CLR_CH7_IDX | B_BE_CLR_CH8_IDX | 123 B_BE_CLR_CH9_IDX | B_BE_CLR_CH10_IDX | B_BE_CLR_CH11_IDX | 124 B_BE_CLR_CH12_IDX | B_BE_CLR_CH13_IDX | B_BE_CLR_CH14_IDX; 125 rtw89_write32(rtwdev, R_BE_TXBD_RWPTR_CLR1, val); 126 127 rtw89_write32(rtwdev, R_BE_RXBD_RWPTR_CLR1_V1, 128 B_BE_CLR_RXQ0_IDX | B_BE_CLR_RPQ0_IDX); 129 130 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RXQ]; 131 rtw89_write16(rtwdev, R_BE_RXQ0_RXBD_IDX_V1, rx_ring->bd_ring.len - 1); 132 133 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; 134 rtw89_write16(rtwdev, R_BE_RPQ0_RXBD_IDX_V1, rx_ring->bd_ring.len - 1); 135 } 136 137 static int rtw89_pci_poll_txdma_ch_idle_be(struct rtw89_dev *rtwdev) 138 { 139 u32 val; 140 141 return read_poll_timeout(rtw89_read32, val, (val & DMA_BUSY1_CHECK_BE) == 0, 142 10, 1000, false, rtwdev, R_BE_HAXI_DMA_BUSY1); 143 } 144 145 static int rtw89_pci_poll_rxdma_ch_idle_be(struct rtw89_dev *rtwdev) 146 { 147 u32 check; 148 u32 val; 149 150 check = B_BE_RXQ0_BUSY_V1 | B_BE_RPQ0_BUSY_V1; 151 152 return read_poll_timeout(rtw89_read32, val, (val & check) == 0, 153 10, 1000, false, rtwdev, R_BE_HAXI_DMA_BUSY1); 154 } 155 156 static int rtw89_pci_poll_dma_all_idle_be(struct rtw89_dev *rtwdev) 157 { 158 int ret; 159 160 ret = rtw89_pci_poll_txdma_ch_idle_be(rtwdev); 161 if (ret) { 162 rtw89_err(rtwdev, "txdma ch busy\n"); 163 return ret; 164 } 165 166 ret = rtw89_pci_poll_rxdma_ch_idle_be(rtwdev); 167 if (ret) { 168 rtw89_err(rtwdev, "rxdma ch busy\n"); 169 return ret; 170 } 171 172 return 0; 173 } 174 175 static void rtw89_pci_mode_op_be(struct rtw89_dev *rtwdev) 176 { 177 const struct rtw89_pci_info *info = rtwdev->pci_info; 178 u32 val32_init1, val32_rxapp, val32_exp; 179 180 val32_init1 = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1); 181 val32_rxapp = rtw89_read32(rtwdev, R_BE_RX_APPEND_MODE); 182 val32_exp = rtw89_read32(rtwdev, R_BE_HAXI_EXP_CTRL_V1); 183 184 if (info->rxbd_mode == MAC_AX_RXBD_PKT) { 185 val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_NORM, 186 B_BE_RXQ_RXBD_MODE_MASK); 187 } else if (info->rxbd_mode == MAC_AX_RXBD_SEP) { 188 val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_SEP, 189 B_BE_RXQ_RXBD_MODE_MASK); 190 val32_rxapp = u32_replace_bits(val32_rxapp, 0, 191 B_BE_APPEND_LEN_MASK); 192 } 193 194 val32_init1 = u32_replace_bits(val32_init1, info->tx_burst, 195 B_BE_MAX_TXDMA_MASK); 196 val32_init1 = u32_replace_bits(val32_init1, info->rx_burst, 197 B_BE_MAX_RXDMA_MASK); 198 val32_exp = u32_replace_bits(val32_exp, info->multi_tag_num, 199 B_BE_MAX_TAG_NUM_MASK); 200 val32_init1 = u32_replace_bits(val32_init1, info->wd_dma_idle_intvl, 201 B_BE_CFG_WD_PERIOD_IDLE_MASK); 202 val32_init1 = u32_replace_bits(val32_init1, info->wd_dma_act_intvl, 203 B_BE_CFG_WD_PERIOD_ACTIVE_MASK); 204 205 rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val32_init1); 206 rtw89_write32(rtwdev, R_BE_RX_APPEND_MODE, val32_rxapp); 207 rtw89_write32(rtwdev, R_BE_HAXI_EXP_CTRL_V1, val32_exp); 208 } 209 210 static int rtw89_pci_rst_bdram_be(struct rtw89_dev *rtwdev) 211 { 212 u32 val; 213 214 rtw89_write32_set(rtwdev, R_BE_HAXI_INIT_CFG1, B_BE_SET_BDRAM_BOUND); 215 216 return read_poll_timeout(rtw89_read32, val, !(val & B_BE_SET_BDRAM_BOUND), 217 50, 500000, false, rtwdev, R_BE_HAXI_INIT_CFG1); 218 } 219 220 static void rtw89_pci_debounce_be(struct rtw89_dev *rtwdev) 221 { 222 u32 val32; 223 224 val32 = rtw89_read32(rtwdev, R_BE_SYS_PAGE_CLK_GATED); 225 val32 = u32_replace_bits(val32, 0, B_BE_PCIE_PRST_DEBUNC_PERIOD_MASK); 226 val32 |= B_BE_SYM_PRST_DEBUNC_SEL; 227 rtw89_write32(rtwdev, R_BE_SYS_PAGE_CLK_GATED, val32); 228 } 229 230 static void rtw89_pci_ldo_low_pwr_be(struct rtw89_dev *rtwdev) 231 { 232 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_PSUS_OFF_CAPC_EN); 233 rtw89_write32_set(rtwdev, R_BE_SYS_PAGE_CLK_GATED, 234 B_BE_SOP_OFFPOOBS_PC | B_BE_CPHY_AUXCLK_OP | 235 B_BE_CPHY_POWER_READY_CHK); 236 rtw89_write32_clr(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_PCIE_FORCE_IBX_EN | 237 B_BE_PCIE_DIS_L2_RTK_PERST | 238 B_BE_PCIE_DIS_L2__CTRL_LDO_HCI); 239 rtw89_write32_clr(rtwdev, R_BE_L1_2_CTRL_HCILDO, B_BE_PCIE_DIS_L1_2_CTRL_HCILDO); 240 } 241 242 static void rtw89_pci_pcie_setting_be(struct rtw89_dev *rtwdev) 243 { 244 const struct rtw89_chip_info *chip = rtwdev->chip; 245 struct rtw89_hal *hal = &rtwdev->hal; 246 247 rtw89_write32_set(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_EN_AUX_CLK); 248 rtw89_write32_clr(rtwdev, R_BE_PCIE_PS_CTRL, B_BE_CMAC_EXIT_L1_EN); 249 250 if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) 251 return; 252 253 rtw89_write32_set(rtwdev, R_BE_EFUSE_CTRL_2_V1, B_BE_R_SYM_AUTOLOAD_WITH_PMC_SEL); 254 rtw89_write32_set(rtwdev, R_BE_PCIE_LAT_CTRL, B_BE_SYM_AUX_CLK_SEL); 255 } 256 257 static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev) 258 { 259 u32 val32; 260 261 rtw89_write32(rtwdev, R_BE_PL1_DBG_INFO, 0x0); 262 rtw89_write32_set(rtwdev, R_BE_FWS1IMR, B_BE_PCIE_SER_TIMEOUT_INDIC_EN); 263 rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN); 264 rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_TIMER_UNIT_MASK, 1); 265 266 val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK); 267 val32 |= B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR | B_BE_SER_PM_MASTER_IMR | 268 B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK; 269 rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32); 270 } 271 272 static void rtw89_pci_ctrl_txdma_ch_be(struct rtw89_dev *rtwdev, bool all_en, 273 bool h2c_en) 274 { 275 u32 mask_all; 276 u32 val; 277 278 mask_all = B_BE_STOP_CH0 | B_BE_STOP_CH1 | B_BE_STOP_CH2 | 279 B_BE_STOP_CH3 | B_BE_STOP_CH4 | B_BE_STOP_CH5 | 280 B_BE_STOP_CH6 | B_BE_STOP_CH7 | B_BE_STOP_CH8 | 281 B_BE_STOP_CH9 | B_BE_STOP_CH10 | B_BE_STOP_CH11; 282 283 val = rtw89_read32(rtwdev, R_BE_HAXI_DMA_STOP1); 284 val |= B_BE_STOP_CH13 | B_BE_STOP_CH14; 285 286 if (all_en) 287 val &= ~mask_all; 288 else 289 val |= mask_all; 290 291 if (h2c_en) 292 val &= ~B_BE_STOP_CH12; 293 else 294 val |= B_BE_STOP_CH12; 295 296 rtw89_write32(rtwdev, R_BE_HAXI_DMA_STOP1, val); 297 } 298 299 static int rtw89_pci_ops_mac_pre_init_be(struct rtw89_dev *rtwdev) 300 { 301 int ret; 302 303 rtw89_pci_set_io_rcy_be(rtwdev); 304 _patch_pcie_power_wake_be(rtwdev, true); 305 rtw89_pci_ctrl_wpdma_pcie_be(rtwdev, false); 306 rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_DISABLE, 307 MAC_AX_PCIE_DISABLE, MAC_AX_PCIE_DISABLE); 308 rtw89_pci_clr_idx_all_be(rtwdev); 309 310 ret = rtw89_pci_poll_dma_all_idle_be(rtwdev); 311 if (ret) { 312 rtw89_err(rtwdev, "[ERR] poll pcie dma all idle\n"); 313 return ret; 314 } 315 316 rtw89_pci_mode_op_be(rtwdev); 317 rtw89_pci_ops_reset(rtwdev); 318 319 ret = rtw89_pci_rst_bdram_be(rtwdev); 320 if (ret) { 321 rtw89_err(rtwdev, "[ERR]pcie rst bdram\n"); 322 return ret; 323 } 324 325 rtw89_pci_debounce_be(rtwdev); 326 rtw89_pci_ldo_low_pwr_be(rtwdev); 327 rtw89_pci_pcie_setting_be(rtwdev); 328 rtw89_pci_ser_setting_be(rtwdev); 329 330 rtw89_pci_ctrl_txdma_ch_be(rtwdev, false, true); 331 rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_ENABLE, 332 MAC_AX_PCIE_ENABLE, MAC_AX_PCIE_ENABLE); 333 334 return 0; 335 } 336 337 static int rtw89_pci_ops_mac_pre_deinit_be(struct rtw89_dev *rtwdev) 338 { 339 u32 val; 340 341 _patch_pcie_power_wake_be(rtwdev, false); 342 343 val = rtw89_read32_mask(rtwdev, R_BE_IC_PWR_STATE, B_BE_WLMAC_PWR_STE_MASK); 344 if (val == 0) 345 return 0; 346 347 rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_DISABLE, 348 MAC_AX_PCIE_DISABLE, MAC_AX_PCIE_DISABLE); 349 rtw89_pci_clr_idx_all_be(rtwdev); 350 351 return 0; 352 } 353 354 int rtw89_pci_ltr_set_v2(struct rtw89_dev *rtwdev, bool en) 355 { 356 u32 ctrl0, cfg0, cfg1, dec_ctrl, idle_ltcy, act_ltcy, dis_ltcy; 357 358 ctrl0 = rtw89_read32(rtwdev, R_BE_LTR_CTRL_0); 359 if (rtw89_pci_ltr_is_err_reg_val(ctrl0)) 360 return -EINVAL; 361 cfg0 = rtw89_read32(rtwdev, R_BE_LTR_CFG_0); 362 if (rtw89_pci_ltr_is_err_reg_val(cfg0)) 363 return -EINVAL; 364 cfg1 = rtw89_read32(rtwdev, R_BE_LTR_CFG_1); 365 if (rtw89_pci_ltr_is_err_reg_val(cfg1)) 366 return -EINVAL; 367 dec_ctrl = rtw89_read32(rtwdev, R_BE_LTR_DECISION_CTRL_V1); 368 if (rtw89_pci_ltr_is_err_reg_val(dec_ctrl)) 369 return -EINVAL; 370 idle_ltcy = rtw89_read32(rtwdev, R_BE_LTR_LATENCY_IDX3_V1); 371 if (rtw89_pci_ltr_is_err_reg_val(idle_ltcy)) 372 return -EINVAL; 373 act_ltcy = rtw89_read32(rtwdev, R_BE_LTR_LATENCY_IDX1_V1); 374 if (rtw89_pci_ltr_is_err_reg_val(act_ltcy)) 375 return -EINVAL; 376 dis_ltcy = rtw89_read32(rtwdev, R_BE_LTR_LATENCY_IDX0_V1); 377 if (rtw89_pci_ltr_is_err_reg_val(dis_ltcy)) 378 return -EINVAL; 379 380 if (en) { 381 dec_ctrl |= B_BE_ENABLE_LTR_CTL_DECISION | B_BE_LTR_HW_DEC_EN_V1; 382 ctrl0 |= B_BE_LTR_HW_EN; 383 } else { 384 dec_ctrl &= ~(B_BE_ENABLE_LTR_CTL_DECISION | B_BE_LTR_HW_DEC_EN_V1 | 385 B_BE_LTR_EN_PORT_V1_MASK); 386 ctrl0 &= ~B_BE_LTR_HW_EN; 387 } 388 389 dec_ctrl = u32_replace_bits(dec_ctrl, PCI_LTR_SPC_500US, 390 B_BE_LTR_SPACE_IDX_MASK); 391 cfg0 = u32_replace_bits(cfg0, PCI_LTR_IDLE_TIMER_3_2MS, 392 B_BE_LTR_IDLE_TIMER_IDX_MASK); 393 cfg1 = u32_replace_bits(cfg1, 0xC0, B_BE_LTR_CMAC0_RX_USE_PG_TH_MASK); 394 cfg1 = u32_replace_bits(cfg1, 0xC0, B_BE_LTR_CMAC1_RX_USE_PG_TH_MASK); 395 cfg0 = u32_replace_bits(cfg0, 1, B_BE_LTR_IDX_ACTIVE_MASK); 396 cfg0 = u32_replace_bits(cfg0, 3, B_BE_LTR_IDX_IDLE_MASK); 397 dec_ctrl = u32_replace_bits(dec_ctrl, 0, B_BE_LTR_IDX_DISABLE_V1_MASK); 398 399 rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX3_V1, 0x90039003); 400 rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX1_V1, 0x880b880b); 401 rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX0_V1, 0); 402 rtw89_write32(rtwdev, R_BE_LTR_DECISION_CTRL_V1, dec_ctrl); 403 rtw89_write32(rtwdev, R_BE_LTR_CFG_0, cfg0); 404 rtw89_write32(rtwdev, R_BE_LTR_CFG_1, cfg1); 405 rtw89_write32(rtwdev, R_BE_LTR_CTRL_0, ctrl0); 406 407 return 0; 408 } 409 EXPORT_SYMBOL(rtw89_pci_ltr_set_v2); 410 411 static void rtw89_pci_configure_mit_be(struct rtw89_dev *rtwdev) 412 { 413 u32 cnt; 414 u32 val; 415 416 rtw89_write32_mask(rtwdev, R_BE_PCIE_MIT0_TMR, 417 B_BE_PCIE_MIT0_RX_TMR_MASK, BE_MIT0_TMR_UNIT_1MS); 418 419 val = rtw89_read32(rtwdev, R_BE_PCIE_MIT0_CNT); 420 cnt = min_t(u32, U8_MAX, RTW89_PCI_RXBD_NUM_MAX / 2); 421 val = u32_replace_bits(val, cnt, B_BE_PCIE_RX_MIT0_CNT_MASK); 422 val = u32_replace_bits(val, 2, B_BE_PCIE_RX_MIT0_TMR_CNT_MASK); 423 rtw89_write32(rtwdev, R_BE_PCIE_MIT0_CNT, val); 424 } 425 426 static int rtw89_pci_ops_mac_post_init_be(struct rtw89_dev *rtwdev) 427 { 428 const struct rtw89_pci_info *info = rtwdev->pci_info; 429 int ret; 430 431 ret = info->ltr_set(rtwdev, true); 432 if (ret) { 433 rtw89_err(rtwdev, "pci ltr set fail\n"); 434 return ret; 435 } 436 437 rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_IGNORE, 438 MAC_AX_PCIE_IGNORE, MAC_AX_PCIE_ENABLE); 439 rtw89_pci_ctrl_wpdma_pcie_be(rtwdev, true); 440 rtw89_pci_ctrl_txdma_ch_be(rtwdev, true, true); 441 rtw89_pci_configure_mit_be(rtwdev); 442 443 return 0; 444 } 445 446 static int rtw89_pci_poll_io_idle_be(struct rtw89_dev *rtwdev) 447 { 448 u32 sts; 449 int ret; 450 451 ret = read_poll_timeout_atomic(rtw89_read32, sts, 452 !(sts & B_BE_HAXI_MST_BUSY), 453 10, 1000, false, rtwdev, 454 R_BE_HAXI_DMA_BUSY1); 455 if (ret) { 456 rtw89_err(rtwdev, "pci dmach busy1 0x%X\n", sts); 457 return ret; 458 } 459 460 return 0; 461 } 462 463 static int rtw89_pci_lv1rst_stop_dma_be(struct rtw89_dev *rtwdev) 464 { 465 int ret; 466 467 rtw89_pci_ctrl_dma_all(rtwdev, false); 468 ret = rtw89_pci_poll_io_idle_be(rtwdev); 469 if (!ret) 470 return 0; 471 472 rtw89_debug(rtwdev, RTW89_DBG_HCI, 473 "[PCIe] poll_io_idle fail; reset hci dma trx\n"); 474 475 rtw89_mac_ctrl_hci_dma_trx(rtwdev, false); 476 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 477 478 return rtw89_pci_poll_io_idle_be(rtwdev); 479 } 480 481 static int rtw89_pci_lv1rst_start_dma_be(struct rtw89_dev *rtwdev) 482 { 483 int ret; 484 485 rtw89_mac_ctrl_hci_dma_trx(rtwdev, false); 486 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 487 rtw89_pci_clr_idx_all(rtwdev); 488 489 ret = rtw89_pci_rst_bdram_be(rtwdev); 490 if (ret) 491 return ret; 492 493 rtw89_pci_ctrl_dma_all(rtwdev, true); 494 return 0; 495 } 496 497 const struct rtw89_pci_gen_def rtw89_pci_gen_be = { 498 .isr_rdu = B_BE_RDU_CH1_INT | B_BE_RDU_CH0_INT, 499 .isr_halt_c2h = B_BE_HALT_C2H_INT, 500 .isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT, 501 .isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1}, 502 .isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1}, 503 504 .mac_pre_init = rtw89_pci_ops_mac_pre_init_be, 505 .mac_pre_deinit = rtw89_pci_ops_mac_pre_deinit_be, 506 .mac_post_init = rtw89_pci_ops_mac_post_init_be, 507 508 .clr_idx_all = rtw89_pci_clr_idx_all_be, 509 .rst_bdram = rtw89_pci_rst_bdram_be, 510 511 .lv1rst_stop_dma = rtw89_pci_lv1rst_stop_dma_be, 512 .lv1rst_start_dma = rtw89_pci_lv1rst_start_dma_be, 513 }; 514 EXPORT_SYMBOL(rtw89_pci_gen_be); 515