1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PCI_H__ 6 #define __RTW89_PCI_H__ 7 8 #include "txrx.h" 9 10 #define MDIO_PG0_G1 0 11 #define MDIO_PG1_G1 1 12 #define MDIO_PG0_G2 2 13 #define MDIO_PG1_G2 3 14 #define RAC_ANA10 0x10 15 #define RAC_ANA19 0x19 16 #define RAC_ANA1F 0x1F 17 #define RAC_ANA24 0x24 18 #define B_AX_DEGLITCH GENMASK(11, 8) 19 #define RAC_ANA26 0x26 20 #define B_AX_RXEN GENMASK(15, 14) 21 #define RAC_CTRL_PPR_V1 0x30 22 #define B_AX_CLK_CALIB_EN BIT(12) 23 #define B_AX_CALIB_EN BIT(13) 24 #define B_AX_DIV GENMASK(15, 14) 25 #define RAC_SET_PPR_V1 0x31 26 27 #define R_AX_DBI_FLAG 0x1090 28 #define B_AX_DBI_RFLAG BIT(17) 29 #define B_AX_DBI_WFLAG BIT(16) 30 #define B_AX_DBI_WREN_MSK GENMASK(15, 12) 31 #define B_AX_DBI_ADDR_MSK GENMASK(11, 2) 32 #define R_AX_DBI_WDATA 0x1094 33 #define R_AX_DBI_RDATA 0x1098 34 35 #define R_AX_MDIO_WDATA 0x10A4 36 #define R_AX_MDIO_RDATA 0x10A6 37 38 #define RTW89_PCI_WR_RETRY_CNT 20 39 40 /* Interrupts */ 41 #define R_AX_HIMR0 0x01A0 42 #define B_AX_HALT_C2H_INT_EN BIT(21) 43 #define R_AX_HISR0 0x01A4 44 45 #define R_AX_MDIO_CFG 0x10A0 46 #define B_AX_MDIO_PHY_ADDR_MASK GENMASK(13, 12) 47 #define B_AX_MDIO_RFLAG BIT(9) 48 #define B_AX_MDIO_WFLAG BIT(8) 49 #define B_AX_MDIO_ADDR_MASK GENMASK(4, 0) 50 51 #define R_AX_PCIE_HIMR00 0x10B0 52 #define B_AX_HC00ISR_IND_INT_EN BIT(27) 53 #define B_AX_HD1ISR_IND_INT_EN BIT(26) 54 #define B_AX_HD0ISR_IND_INT_EN BIT(25) 55 #define B_AX_HS0ISR_IND_INT_EN BIT(24) 56 #define B_AX_RETRAIN_INT_EN BIT(21) 57 #define B_AX_RPQBD_FULL_INT_EN BIT(20) 58 #define B_AX_RDU_INT_EN BIT(19) 59 #define B_AX_RXDMA_STUCK_INT_EN BIT(18) 60 #define B_AX_TXDMA_STUCK_INT_EN BIT(17) 61 #define B_AX_PCIE_HOTRST_INT_EN BIT(16) 62 #define B_AX_PCIE_FLR_INT_EN BIT(15) 63 #define B_AX_PCIE_PERST_INT_EN BIT(14) 64 #define B_AX_TXDMA_CH12_INT_EN BIT(13) 65 #define B_AX_TXDMA_CH9_INT_EN BIT(12) 66 #define B_AX_TXDMA_CH8_INT_EN BIT(11) 67 #define B_AX_TXDMA_ACH7_INT_EN BIT(10) 68 #define B_AX_TXDMA_ACH6_INT_EN BIT(9) 69 #define B_AX_TXDMA_ACH5_INT_EN BIT(8) 70 #define B_AX_TXDMA_ACH4_INT_EN BIT(7) 71 #define B_AX_TXDMA_ACH3_INT_EN BIT(6) 72 #define B_AX_TXDMA_ACH2_INT_EN BIT(5) 73 #define B_AX_TXDMA_ACH1_INT_EN BIT(4) 74 #define B_AX_TXDMA_ACH0_INT_EN BIT(3) 75 #define B_AX_RPQDMA_INT_EN BIT(2) 76 #define B_AX_RXP1DMA_INT_EN BIT(1) 77 #define B_AX_RXDMA_INT_EN BIT(0) 78 79 #define R_AX_PCIE_HISR00 0x10B4 80 #define B_AX_HC00ISR_IND_INT BIT(27) 81 #define B_AX_HD1ISR_IND_INT BIT(26) 82 #define B_AX_HD0ISR_IND_INT BIT(25) 83 #define B_AX_HS0ISR_IND_INT BIT(24) 84 #define B_AX_RETRAIN_INT BIT(21) 85 #define B_AX_RPQBD_FULL_INT BIT(20) 86 #define B_AX_RDU_INT BIT(19) 87 #define B_AX_RXDMA_STUCK_INT BIT(18) 88 #define B_AX_TXDMA_STUCK_INT BIT(17) 89 #define B_AX_PCIE_HOTRST_INT BIT(16) 90 #define B_AX_PCIE_FLR_INT BIT(15) 91 #define B_AX_PCIE_PERST_INT BIT(14) 92 #define B_AX_TXDMA_CH12_INT BIT(13) 93 #define B_AX_TXDMA_CH9_INT BIT(12) 94 #define B_AX_TXDMA_CH8_INT BIT(11) 95 #define B_AX_TXDMA_ACH7_INT BIT(10) 96 #define B_AX_TXDMA_ACH6_INT BIT(9) 97 #define B_AX_TXDMA_ACH5_INT BIT(8) 98 #define B_AX_TXDMA_ACH4_INT BIT(7) 99 #define B_AX_TXDMA_ACH3_INT BIT(6) 100 #define B_AX_TXDMA_ACH2_INT BIT(5) 101 #define B_AX_TXDMA_ACH1_INT BIT(4) 102 #define B_AX_TXDMA_ACH0_INT BIT(3) 103 #define B_AX_RPQDMA_INT BIT(2) 104 #define B_AX_RXP1DMA_INT BIT(1) 105 #define B_AX_RXDMA_INT BIT(0) 106 107 #define R_AX_PCIE_HIMR10 0x13B0 108 #define B_AX_HC10ISR_IND_INT_EN BIT(28) 109 #define B_AX_TXDMA_CH11_INT_EN BIT(12) 110 #define B_AX_TXDMA_CH10_INT_EN BIT(11) 111 112 #define R_AX_PCIE_HISR10 0x13B4 113 #define B_AX_HC10ISR_IND_INT BIT(28) 114 #define B_AX_TXDMA_CH11_INT BIT(12) 115 #define B_AX_TXDMA_CH10_INT BIT(11) 116 117 /* TX/RX */ 118 #define R_AX_RXQ_RXBD_IDX 0x1050 119 #define R_AX_RPQ_RXBD_IDX 0x1054 120 #define R_AX_ACH0_TXBD_IDX 0x1058 121 #define R_AX_ACH1_TXBD_IDX 0x105C 122 #define R_AX_ACH2_TXBD_IDX 0x1060 123 #define R_AX_ACH3_TXBD_IDX 0x1064 124 #define R_AX_ACH4_TXBD_IDX 0x1068 125 #define R_AX_ACH5_TXBD_IDX 0x106C 126 #define R_AX_ACH6_TXBD_IDX 0x1070 127 #define R_AX_ACH7_TXBD_IDX 0x1074 128 #define R_AX_CH8_TXBD_IDX 0x1078 /* Management Queue band 0 */ 129 #define R_AX_CH9_TXBD_IDX 0x107C /* HI Queue band 0 */ 130 #define R_AX_CH10_TXBD_IDX 0x137C /* Management Queue band 1 */ 131 #define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */ 132 #define R_AX_CH12_TXBD_IDX 0x1080 /* FWCMD Queue */ 133 #define TXBD_HW_IDX_MASK GENMASK(27, 16) 134 #define TXBD_HOST_IDX_MASK GENMASK(11, 0) 135 136 #define R_AX_ACH0_TXBD_DESA_L 0x1110 137 #define R_AX_ACH0_TXBD_DESA_H 0x1114 138 #define R_AX_ACH1_TXBD_DESA_L 0x1118 139 #define R_AX_ACH1_TXBD_DESA_H 0x111C 140 #define R_AX_ACH2_TXBD_DESA_L 0x1120 141 #define R_AX_ACH2_TXBD_DESA_H 0x1124 142 #define R_AX_ACH3_TXBD_DESA_L 0x1128 143 #define R_AX_ACH3_TXBD_DESA_H 0x112C 144 #define R_AX_ACH4_TXBD_DESA_L 0x1130 145 #define R_AX_ACH4_TXBD_DESA_H 0x1134 146 #define R_AX_ACH5_TXBD_DESA_L 0x1138 147 #define R_AX_ACH5_TXBD_DESA_H 0x113C 148 #define R_AX_ACH6_TXBD_DESA_L 0x1140 149 #define R_AX_ACH6_TXBD_DESA_H 0x1144 150 #define R_AX_ACH7_TXBD_DESA_L 0x1148 151 #define R_AX_ACH7_TXBD_DESA_H 0x114C 152 #define R_AX_CH8_TXBD_DESA_L 0x1150 153 #define R_AX_CH8_TXBD_DESA_H 0x1154 154 #define R_AX_CH9_TXBD_DESA_L 0x1158 155 #define R_AX_CH9_TXBD_DESA_H 0x115C 156 #define R_AX_CH10_TXBD_DESA_L 0x1358 157 #define R_AX_CH10_TXBD_DESA_H 0x135C 158 #define R_AX_CH11_TXBD_DESA_L 0x1360 159 #define R_AX_CH11_TXBD_DESA_H 0x1364 160 #define R_AX_CH12_TXBD_DESA_L 0x1160 161 #define R_AX_CH12_TXBD_DESA_H 0x1164 162 #define R_AX_RXQ_RXBD_DESA_L 0x1100 163 #define R_AX_RXQ_RXBD_DESA_H 0x1104 164 #define R_AX_RPQ_RXBD_DESA_L 0x1108 165 #define R_AX_RPQ_RXBD_DESA_H 0x110C 166 #define B_AX_DESC_NUM_MSK GENMASK(11, 0) 167 168 #define R_AX_RXQ_RXBD_NUM 0x1020 169 #define R_AX_RPQ_RXBD_NUM 0x1022 170 #define R_AX_ACH0_TXBD_NUM 0x1024 171 #define R_AX_ACH1_TXBD_NUM 0x1026 172 #define R_AX_ACH2_TXBD_NUM 0x1028 173 #define R_AX_ACH3_TXBD_NUM 0x102A 174 #define R_AX_ACH4_TXBD_NUM 0x102C 175 #define R_AX_ACH5_TXBD_NUM 0x102E 176 #define R_AX_ACH6_TXBD_NUM 0x1030 177 #define R_AX_ACH7_TXBD_NUM 0x1032 178 #define R_AX_CH8_TXBD_NUM 0x1034 179 #define R_AX_CH9_TXBD_NUM 0x1036 180 #define R_AX_CH10_TXBD_NUM 0x1338 181 #define R_AX_CH11_TXBD_NUM 0x133A 182 #define R_AX_CH12_TXBD_NUM 0x1038 183 184 #define R_AX_ACH0_BDRAM_CTRL 0x1200 185 #define R_AX_ACH1_BDRAM_CTRL 0x1204 186 #define R_AX_ACH2_BDRAM_CTRL 0x1208 187 #define R_AX_ACH3_BDRAM_CTRL 0x120C 188 #define R_AX_ACH4_BDRAM_CTRL 0x1210 189 #define R_AX_ACH5_BDRAM_CTRL 0x1214 190 #define R_AX_ACH6_BDRAM_CTRL 0x1218 191 #define R_AX_ACH7_BDRAM_CTRL 0x121C 192 #define R_AX_CH8_BDRAM_CTRL 0x1220 193 #define R_AX_CH9_BDRAM_CTRL 0x1224 194 #define R_AX_CH10_BDRAM_CTRL 0x1320 195 #define R_AX_CH11_BDRAM_CTRL 0x1324 196 #define R_AX_CH12_BDRAM_CTRL 0x1228 197 #define BDRAM_SIDX_MASK GENMASK(7, 0) 198 #define BDRAM_MAX_MASK GENMASK(15, 8) 199 #define BDRAM_MIN_MASK GENMASK(23, 16) 200 201 #define R_AX_PCIE_INIT_CFG1 0x1000 202 #define B_AX_PCIE_RXRST_KEEP_REG BIT(23) 203 #define B_AX_PCIE_TXRST_KEEP_REG BIT(22) 204 #define B_AX_PCIE_PERST_KEEP_REG BIT(21) 205 #define B_AX_PCIE_FLR_KEEP_REG BIT(20) 206 #define B_AX_PCIE_TRAIN_KEEP_REG BIT(19) 207 #define B_AX_RXBD_MODE BIT(18) 208 #define B_AX_PCIE_MAX_RXDMA_MASK GENMASK(16, 14) 209 #define B_AX_RXHCI_EN BIT(13) 210 #define B_AX_LATENCY_CONTROL BIT(12) 211 #define B_AX_TXHCI_EN BIT(11) 212 #define B_AX_PCIE_MAX_TXDMA_MASK GENMASK(10, 8) 213 #define B_AX_TX_TRUNC_MODE BIT(5) 214 #define B_AX_RX_TRUNC_MODE BIT(4) 215 #define B_AX_RST_BDRAM BIT(3) 216 #define B_AX_DIS_RXDMA_PRE BIT(2) 217 218 #define R_AX_TXDMA_ADDR_H 0x10F0 219 #define R_AX_RXDMA_ADDR_H 0x10F4 220 221 #define R_AX_PCIE_DMA_STOP1 0x1010 222 #define B_AX_STOP_PCIEIO BIT(20) 223 #define B_AX_STOP_WPDMA BIT(19) 224 #define B_AX_STOP_CH12 BIT(18) 225 #define B_AX_STOP_CH9 BIT(17) 226 #define B_AX_STOP_CH8 BIT(16) 227 #define B_AX_STOP_ACH7 BIT(15) 228 #define B_AX_STOP_ACH6 BIT(14) 229 #define B_AX_STOP_ACH5 BIT(13) 230 #define B_AX_STOP_ACH4 BIT(12) 231 #define B_AX_STOP_ACH3 BIT(11) 232 #define B_AX_STOP_ACH2 BIT(10) 233 #define B_AX_STOP_ACH1 BIT(9) 234 #define B_AX_STOP_ACH0 BIT(8) 235 #define B_AX_STOP_RPQ BIT(1) 236 #define B_AX_STOP_RXQ BIT(0) 237 #define B_AX_TX_STOP1_ALL GENMASK(18, 8) 238 239 #define R_AX_PCIE_DMA_STOP2 0x1310 240 #define B_AX_STOP_CH11 BIT(1) 241 #define B_AX_STOP_CH10 BIT(0) 242 #define B_AX_TX_STOP2_ALL GENMASK(1, 0) 243 244 #define R_AX_TXBD_RWPTR_CLR1 0x1014 245 #define B_AX_CLR_CH12_IDX BIT(10) 246 #define B_AX_CLR_CH9_IDX BIT(9) 247 #define B_AX_CLR_CH8_IDX BIT(8) 248 #define B_AX_CLR_ACH7_IDX BIT(7) 249 #define B_AX_CLR_ACH6_IDX BIT(6) 250 #define B_AX_CLR_ACH5_IDX BIT(5) 251 #define B_AX_CLR_ACH4_IDX BIT(4) 252 #define B_AX_CLR_ACH3_IDX BIT(3) 253 #define B_AX_CLR_ACH2_IDX BIT(2) 254 #define B_AX_CLR_ACH1_IDX BIT(1) 255 #define B_AX_CLR_ACH0_IDX BIT(0) 256 #define B_AX_TXBD_CLR1_ALL GENMASK(10, 0) 257 258 #define R_AX_RXBD_RWPTR_CLR 0x1018 259 #define B_AX_CLR_RPQ_IDX BIT(1) 260 #define B_AX_CLR_RXQ_IDX BIT(0) 261 #define B_AX_RXBD_CLR_ALL GENMASK(1, 0) 262 263 #define R_AX_TXBD_RWPTR_CLR2 0x1314 264 #define B_AX_CLR_CH11_IDX BIT(1) 265 #define B_AX_CLR_CH10_IDX BIT(0) 266 #define B_AX_TXBD_CLR2_ALL GENMASK(1, 0) 267 268 #define R_AX_PCIE_DMA_BUSY1 0x101C 269 #define B_AX_PCIEIO_RX_BUSY BIT(22) 270 #define B_AX_PCIEIO_TX_BUSY BIT(21) 271 #define B_AX_PCIEIO_BUSY BIT(20) 272 #define B_AX_WPDMA_BUSY BIT(19) 273 274 #define R_AX_PCIE_DMA_BUSY2 0x131C 275 #define B_AX_CH11_BUSY BIT(1) 276 #define B_AX_CH10_BUSY BIT(0) 277 278 /* Configure */ 279 #define R_AX_PCIE_INIT_CFG1 0x1000 280 #define B_AX_PCIE_RXRST_KEEP_REG BIT(23) 281 #define B_AX_PCIE_TXRST_KEEP_REG BIT(22) 282 #define B_AX_DIS_RXDMA_PRE BIT(2) 283 284 #define R_AX_PCIE_INIT_CFG2 0x1004 285 #define B_AX_WD_ITVL_IDLE GENMASK(27, 24) 286 #define B_AX_WD_ITVL_ACT GENMASK(19, 16) 287 288 #define R_AX_PCIE_PS_CTRL 0x1008 289 #define B_AX_L1OFF_PWR_OFF_EN BIT(5) 290 291 #define R_AX_INT_MIT_RX 0x10D4 292 #define B_AX_RXMIT_RXP2_SEL BIT(19) 293 #define B_AX_RXMIT_RXP1_SEL BIT(18) 294 #define B_AX_RXTIMER_UNIT_MASK GENMASK(17, 16) 295 #define AX_RXTIMER_UNIT_64US 0 296 #define AX_RXTIMER_UNIT_128US 1 297 #define AX_RXTIMER_UNIT_256US 2 298 #define AX_RXTIMER_UNIT_512US 3 299 #define B_AX_RXCOUNTER_MATCH_MASK GENMASK(15, 8) 300 #define B_AX_RXTIMER_MATCH_MASK GENMASK(7, 0) 301 302 #define R_AX_DBG_ERR_FLAG 0x11C4 303 #define B_AX_PCIE_RPQ_FULL BIT(29) 304 #define B_AX_PCIE_RXQ_FULL BIT(28) 305 #define B_AX_CPL_STATUS_MASK GENMASK(27, 25) 306 #define B_AX_RX_STUCK BIT(22) 307 #define B_AX_TX_STUCK BIT(21) 308 #define B_AX_PCIEDBG_TXERR0 BIT(16) 309 #define B_AX_PCIE_RXP1_ERR0 BIT(4) 310 #define B_AX_PCIE_TXBD_LEN0 BIT(1) 311 #define B_AX_PCIE_TXBD_4KBOUD_LENERR BIT(0) 312 313 #define R_AX_LBC_WATCHDOG 0x11D8 314 #define B_AX_LBC_TIMER GENMASK(7, 4) 315 #define B_AX_LBC_FLAG BIT(1) 316 #define B_AX_LBC_EN BIT(0) 317 318 #define R_AX_PCIE_EXP_CTRL 0x13F0 319 #define B_AX_EN_CHKDSC_NO_RX_STUCK BIT(20) 320 #define B_AX_MAX_TAG_NUM GENMASK(18, 16) 321 #define B_AX_SIC_EN_FORCE_CLKREQ BIT(4) 322 323 #define R_AX_PCIE_RX_PREF_ADV 0x13F4 324 #define B_AX_RXDMA_PREF_ADV_EN BIT(0) 325 326 #define RTW89_PCI_TXBD_NUM_MAX 256 327 #define RTW89_PCI_RXBD_NUM_MAX 256 328 #define RTW89_PCI_TXWD_NUM_MAX 512 329 #define RTW89_PCI_TXWD_PAGE_SIZE 128 330 #define RTW89_PCI_ADDRINFO_MAX 4 331 #define RTW89_PCI_RX_BUF_SIZE 11460 332 333 #define RTW89_PCI_POLL_BDRAM_RST_CNT 100 334 #define RTW89_PCI_MULTITAG 8 335 336 /* PCIE CFG register */ 337 #define RTW89_PCIE_ASPM_CTRL 0x070F 338 #define RTW89_L1DLY_MASK GENMASK(5, 3) 339 #define RTW89_L0DLY_MASK GENMASK(2, 0) 340 #define RTW89_PCIE_TIMER_CTRL 0x0718 341 #define RTW89_PCIE_BIT_L1SUB BIT(5) 342 #define RTW89_PCIE_L1_CTRL 0x0719 343 #define RTW89_PCIE_BIT_CLK BIT(4) 344 #define RTW89_PCIE_BIT_L1 BIT(3) 345 #define RTW89_PCIE_CLK_CTRL 0x0725 346 #define RTW89_PCIE_RST_MSTATE 0x0B48 347 #define RTW89_PCIE_BIT_CFG_RST_MSTATE BIT(0) 348 #define RTW89_PCIE_PHY_RATE 0x82 349 #define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0) 350 #define INTF_INTGRA_MINREF_V1 90 351 #define INTF_INTGRA_HOSTREF_V1 100 352 353 enum rtw89_pcie_phy { 354 PCIE_PHY_GEN1, 355 PCIE_PHY_GEN2, 356 PCIE_PHY_GEN1_UNDEFINE = 0x7F, 357 }; 358 359 enum mac_ax_func_sw { 360 MAC_AX_FUNC_DIS, 361 MAC_AX_FUNC_EN, 362 }; 363 364 enum rtw89_pcie_l0sdly { 365 PCIE_L0SDLY_1US = 0, 366 PCIE_L0SDLY_2US = 1, 367 PCIE_L0SDLY_3US = 2, 368 PCIE_L0SDLY_4US = 3, 369 PCIE_L0SDLY_5US = 4, 370 PCIE_L0SDLY_6US = 5, 371 PCIE_L0SDLY_7US = 6, 372 }; 373 374 enum rtw89_pcie_l1dly { 375 PCIE_L1DLY_16US = 4, 376 PCIE_L1DLY_32US = 5, 377 PCIE_L1DLY_64US = 6, 378 PCIE_L1DLY_HW_INFI = 7, 379 }; 380 381 enum rtw89_pcie_clkdly_hw { 382 PCIE_CLKDLY_HW_0 = 0, 383 PCIE_CLKDLY_HW_30US = 0x1, 384 PCIE_CLKDLY_HW_50US = 0x2, 385 PCIE_CLKDLY_HW_100US = 0x3, 386 PCIE_CLKDLY_HW_150US = 0x4, 387 PCIE_CLKDLY_HW_200US = 0x5, 388 }; 389 390 struct rtw89_pci_bd_ram { 391 u8 start_idx; 392 u8 max_num; 393 u8 min_num; 394 }; 395 396 struct rtw89_pci_tx_data { 397 dma_addr_t dma; 398 }; 399 400 struct rtw89_pci_rx_info { 401 dma_addr_t dma; 402 u32 fs:1, ls:1, tag:11, len:14; 403 }; 404 405 #define RTW89_PCI_TXBD_OPTION_LS BIT(14) 406 407 struct rtw89_pci_tx_bd_32 { 408 __le16 length; 409 __le16 option; 410 __le32 dma; 411 } __packed; 412 413 #define RTW89_PCI_TXWP_VALID BIT(15) 414 415 struct rtw89_pci_tx_wp_info { 416 __le16 seq0; 417 __le16 seq1; 418 __le16 seq2; 419 __le16 seq3; 420 } __packed; 421 422 #define RTW89_PCI_ADDR_MSDU_LS BIT(15) 423 #define RTW89_PCI_ADDR_LS BIT(14) 424 #define RTW89_PCI_ADDR_HIGH(a) (((a) << 6) & GENMASK(13, 6)) 425 #define RTW89_PCI_ADDR_NUM(x) ((x) & GENMASK(5, 0)) 426 427 struct rtw89_pci_tx_addr_info_32 { 428 __le16 length; 429 __le16 option; 430 __le32 dma; 431 } __packed; 432 433 #define RTW89_PCI_RPP_POLLUTED BIT(31) 434 #define RTW89_PCI_RPP_SEQ GENMASK(30, 16) 435 #define RTW89_PCI_RPP_TX_STATUS GENMASK(15, 13) 436 #define RTW89_TX_DONE 0x0 437 #define RTW89_TX_RETRY_LIMIT 0x1 438 #define RTW89_TX_LIFE_TIME 0x2 439 #define RTW89_TX_MACID_DROP 0x3 440 #define RTW89_PCI_RPP_QSEL GENMASK(12, 8) 441 #define RTW89_PCI_RPP_MACID GENMASK(7, 0) 442 443 struct rtw89_pci_rpp_fmt { 444 __le32 dword; 445 } __packed; 446 447 struct rtw89_pci_rx_bd_32 { 448 __le16 buf_size; 449 __le16 rsvd; 450 __le32 dma; 451 } __packed; 452 453 #define RTW89_PCI_RXBD_FS BIT(15) 454 #define RTW89_PCI_RXBD_LS BIT(14) 455 #define RTW89_PCI_RXBD_WRITE_SIZE GENMASK(13, 0) 456 #define RTW89_PCI_RXBD_TAG GENMASK(28, 16) 457 458 struct rtw89_pci_rxbd_info { 459 __le32 dword; 460 }; 461 462 struct rtw89_pci_tx_wd { 463 struct list_head list; 464 struct sk_buff_head queue; 465 466 void *vaddr; 467 dma_addr_t paddr; 468 u32 len; 469 u32 seq; 470 }; 471 472 struct rtw89_pci_dma_ring { 473 void *head; 474 u8 desc_size; 475 dma_addr_t dma; 476 477 u32 addr_num; 478 u32 addr_idx; 479 u32 addr_bdram; 480 u32 addr_desa_l; 481 u32 addr_desa_h; 482 483 u32 len; 484 u32 wp; /* host idx */ 485 u32 rp; /* hw idx */ 486 }; 487 488 struct rtw89_pci_tx_wd_ring { 489 void *head; 490 dma_addr_t dma; 491 492 struct rtw89_pci_tx_wd pages[RTW89_PCI_TXWD_NUM_MAX]; 493 struct list_head free_pages; 494 495 u32 page_size; 496 u32 page_num; 497 u32 curr_num; 498 }; 499 500 #define RTW89_RX_TAG_MAX 0x1fff 501 502 struct rtw89_pci_tx_ring { 503 struct rtw89_pci_tx_wd_ring wd_ring; 504 struct rtw89_pci_dma_ring bd_ring; 505 struct list_head busy_pages; 506 u8 txch; 507 bool dma_enabled; 508 u16 tag; /* range from 0x0001 ~ 0x1fff */ 509 510 u64 tx_cnt; 511 u64 tx_acked; 512 u64 tx_retry_lmt; 513 u64 tx_life_time; 514 u64 tx_mac_id_drop; 515 }; 516 517 struct rtw89_pci_rx_ring { 518 struct rtw89_pci_dma_ring bd_ring; 519 struct sk_buff *buf[RTW89_PCI_RXBD_NUM_MAX]; 520 u32 buf_sz; 521 struct sk_buff *diliver_skb; 522 struct rtw89_rx_desc_info diliver_desc; 523 }; 524 525 struct rtw89_pci_isrs { 526 u32 halt_c2h_isrs; 527 u32 isrs[2]; 528 }; 529 530 struct rtw89_pci { 531 struct pci_dev *pdev; 532 533 /* protect HW irq related registers */ 534 spinlock_t irq_lock; 535 /* protect TRX resources (exclude RXQ) */ 536 spinlock_t trx_lock; 537 bool running; 538 struct rtw89_pci_tx_ring tx_rings[RTW89_TXCH_NUM]; 539 struct rtw89_pci_rx_ring rx_rings[RTW89_RXCH_NUM]; 540 struct sk_buff_head h2c_queue; 541 struct sk_buff_head h2c_release_queue; 542 543 u32 halt_c2h_intrs; 544 u32 intrs[2]; 545 void __iomem *mmap; 546 }; 547 548 static inline struct rtw89_pci_rx_info *RTW89_PCI_RX_SKB_CB(struct sk_buff *skb) 549 { 550 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 551 552 BUILD_BUG_ON(sizeof(struct rtw89_pci_tx_data) > 553 sizeof(info->status.status_driver_data)); 554 555 return (struct rtw89_pci_rx_info *)skb->cb; 556 } 557 558 static inline struct rtw89_pci_rx_bd_32 * 559 RTW89_PCI_RX_BD(struct rtw89_pci_rx_ring *rx_ring, u32 idx) 560 { 561 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 562 u8 *head = bd_ring->head; 563 u32 desc_size = bd_ring->desc_size; 564 u32 offset = idx * desc_size; 565 566 return (struct rtw89_pci_rx_bd_32 *)(head + offset); 567 } 568 569 static inline void 570 rtw89_pci_rxbd_increase(struct rtw89_pci_rx_ring *rx_ring, u32 cnt) 571 { 572 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 573 574 bd_ring->wp += cnt; 575 576 if (bd_ring->wp >= bd_ring->len) 577 bd_ring->wp -= bd_ring->len; 578 } 579 580 static inline struct rtw89_pci_tx_data *RTW89_PCI_TX_SKB_CB(struct sk_buff *skb) 581 { 582 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 583 584 return (struct rtw89_pci_tx_data *)info->status.status_driver_data; 585 } 586 587 static inline struct rtw89_pci_tx_bd_32 * 588 rtw89_pci_get_next_txbd(struct rtw89_pci_tx_ring *tx_ring) 589 { 590 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 591 struct rtw89_pci_tx_bd_32 *tx_bd, *head; 592 593 head = bd_ring->head; 594 tx_bd = head + bd_ring->wp; 595 596 return tx_bd; 597 } 598 599 static inline struct rtw89_pci_tx_wd * 600 rtw89_pci_dequeue_txwd(struct rtw89_pci_tx_ring *tx_ring) 601 { 602 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 603 struct rtw89_pci_tx_wd *txwd; 604 605 txwd = list_first_entry_or_null(&wd_ring->free_pages, 606 struct rtw89_pci_tx_wd, list); 607 if (!txwd) 608 return NULL; 609 610 list_del_init(&txwd->list); 611 txwd->len = 0; 612 wd_ring->curr_num--; 613 614 return txwd; 615 } 616 617 static inline void 618 rtw89_pci_enqueue_txwd(struct rtw89_pci_tx_ring *tx_ring, 619 struct rtw89_pci_tx_wd *txwd) 620 { 621 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 622 623 memset(txwd->vaddr, 0, wd_ring->page_size); 624 list_add_tail(&txwd->list, &wd_ring->free_pages); 625 wd_ring->curr_num++; 626 } 627 628 static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val) 629 { 630 return val == 0xffffffff || val == 0xeaeaeaea; 631 } 632 633 extern const struct dev_pm_ops rtw89_pm_ops; 634 635 #endif 636