1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PCI_H__ 6 #define __RTW89_PCI_H__ 7 8 #include "txrx.h" 9 10 #define MDIO_PG0_G1 0 11 #define MDIO_PG1_G1 1 12 #define MDIO_PG0_G2 2 13 #define MDIO_PG1_G2 3 14 #define RAC_ANA10 0x10 15 #define RAC_ANA19 0x19 16 #define RAC_ANA1F 0x1F 17 #define RAC_ANA24 0x24 18 #define B_AX_DEGLITCH GENMASK(11, 8) 19 #define RAC_ANA26 0x26 20 #define B_AX_RXEN GENMASK(15, 14) 21 #define RAC_CTRL_PPR_V1 0x30 22 #define B_AX_CLK_CALIB_EN BIT(12) 23 #define B_AX_CALIB_EN BIT(13) 24 #define B_AX_DIV GENMASK(15, 14) 25 #define RAC_SET_PPR_V1 0x31 26 27 #define R_AX_DBI_FLAG 0x1090 28 #define B_AX_DBI_RFLAG BIT(17) 29 #define B_AX_DBI_WFLAG BIT(16) 30 #define B_AX_DBI_WREN_MSK GENMASK(15, 12) 31 #define B_AX_DBI_ADDR_MSK GENMASK(11, 2) 32 #define R_AX_DBI_WDATA 0x1094 33 #define R_AX_DBI_RDATA 0x1098 34 35 #define R_AX_MDIO_WDATA 0x10A4 36 #define R_AX_MDIO_RDATA 0x10A6 37 38 #define RTW89_PCI_WR_RETRY_CNT 20 39 40 /* Interrupts */ 41 #define R_AX_HIMR0 0x01A0 42 #define B_AX_HALT_C2H_INT_EN BIT(21) 43 #define R_AX_HISR0 0x01A4 44 45 #define R_AX_MDIO_CFG 0x10A0 46 #define B_AX_MDIO_PHY_ADDR_MASK GENMASK(13, 12) 47 #define B_AX_MDIO_RFLAG BIT(9) 48 #define B_AX_MDIO_WFLAG BIT(8) 49 #define B_AX_MDIO_ADDR_MASK GENMASK(4, 0) 50 51 #define R_AX_PCIE_HIMR00 0x10B0 52 #define B_AX_HC00ISR_IND_INT_EN BIT(27) 53 #define B_AX_HD1ISR_IND_INT_EN BIT(26) 54 #define B_AX_HD0ISR_IND_INT_EN BIT(25) 55 #define B_AX_HS0ISR_IND_INT_EN BIT(24) 56 #define B_AX_RETRAIN_INT_EN BIT(21) 57 #define B_AX_RPQBD_FULL_INT_EN BIT(20) 58 #define B_AX_RDU_INT_EN BIT(19) 59 #define B_AX_RXDMA_STUCK_INT_EN BIT(18) 60 #define B_AX_TXDMA_STUCK_INT_EN BIT(17) 61 #define B_AX_PCIE_HOTRST_INT_EN BIT(16) 62 #define B_AX_PCIE_FLR_INT_EN BIT(15) 63 #define B_AX_PCIE_PERST_INT_EN BIT(14) 64 #define B_AX_TXDMA_CH12_INT_EN BIT(13) 65 #define B_AX_TXDMA_CH9_INT_EN BIT(12) 66 #define B_AX_TXDMA_CH8_INT_EN BIT(11) 67 #define B_AX_TXDMA_ACH7_INT_EN BIT(10) 68 #define B_AX_TXDMA_ACH6_INT_EN BIT(9) 69 #define B_AX_TXDMA_ACH5_INT_EN BIT(8) 70 #define B_AX_TXDMA_ACH4_INT_EN BIT(7) 71 #define B_AX_TXDMA_ACH3_INT_EN BIT(6) 72 #define B_AX_TXDMA_ACH2_INT_EN BIT(5) 73 #define B_AX_TXDMA_ACH1_INT_EN BIT(4) 74 #define B_AX_TXDMA_ACH0_INT_EN BIT(3) 75 #define B_AX_RPQDMA_INT_EN BIT(2) 76 #define B_AX_RXP1DMA_INT_EN BIT(1) 77 #define B_AX_RXDMA_INT_EN BIT(0) 78 79 #define R_AX_PCIE_HISR00 0x10B4 80 #define B_AX_HC00ISR_IND_INT BIT(27) 81 #define B_AX_HD1ISR_IND_INT BIT(26) 82 #define B_AX_HD0ISR_IND_INT BIT(25) 83 #define B_AX_HS0ISR_IND_INT BIT(24) 84 #define B_AX_RETRAIN_INT BIT(21) 85 #define B_AX_RPQBD_FULL_INT BIT(20) 86 #define B_AX_RDU_INT BIT(19) 87 #define B_AX_RXDMA_STUCK_INT BIT(18) 88 #define B_AX_TXDMA_STUCK_INT BIT(17) 89 #define B_AX_PCIE_HOTRST_INT BIT(16) 90 #define B_AX_PCIE_FLR_INT BIT(15) 91 #define B_AX_PCIE_PERST_INT BIT(14) 92 #define B_AX_TXDMA_CH12_INT BIT(13) 93 #define B_AX_TXDMA_CH9_INT BIT(12) 94 #define B_AX_TXDMA_CH8_INT BIT(11) 95 #define B_AX_TXDMA_ACH7_INT BIT(10) 96 #define B_AX_TXDMA_ACH6_INT BIT(9) 97 #define B_AX_TXDMA_ACH5_INT BIT(8) 98 #define B_AX_TXDMA_ACH4_INT BIT(7) 99 #define B_AX_TXDMA_ACH3_INT BIT(6) 100 #define B_AX_TXDMA_ACH2_INT BIT(5) 101 #define B_AX_TXDMA_ACH1_INT BIT(4) 102 #define B_AX_TXDMA_ACH0_INT BIT(3) 103 #define B_AX_RPQDMA_INT BIT(2) 104 #define B_AX_RXP1DMA_INT BIT(1) 105 #define B_AX_RXDMA_INT BIT(0) 106 107 #define R_AX_PCIE_HIMR10 0x13B0 108 #define B_AX_HC10ISR_IND_INT_EN BIT(28) 109 #define B_AX_TXDMA_CH11_INT_EN BIT(12) 110 #define B_AX_TXDMA_CH10_INT_EN BIT(11) 111 112 #define R_AX_PCIE_HISR10 0x13B4 113 #define B_AX_HC10ISR_IND_INT BIT(28) 114 #define B_AX_TXDMA_CH11_INT BIT(12) 115 #define B_AX_TXDMA_CH10_INT BIT(11) 116 117 /* TX/RX */ 118 #define R_AX_RXQ_RXBD_IDX 0x1050 119 #define R_AX_RPQ_RXBD_IDX 0x1054 120 #define R_AX_ACH0_TXBD_IDX 0x1058 121 #define R_AX_ACH1_TXBD_IDX 0x105C 122 #define R_AX_ACH2_TXBD_IDX 0x1060 123 #define R_AX_ACH3_TXBD_IDX 0x1064 124 #define R_AX_ACH4_TXBD_IDX 0x1068 125 #define R_AX_ACH5_TXBD_IDX 0x106C 126 #define R_AX_ACH6_TXBD_IDX 0x1070 127 #define R_AX_ACH7_TXBD_IDX 0x1074 128 #define R_AX_CH8_TXBD_IDX 0x1078 /* Management Queue band 0 */ 129 #define R_AX_CH9_TXBD_IDX 0x107C /* HI Queue band 0 */ 130 #define R_AX_CH10_TXBD_IDX 0x137C /* Management Queue band 1 */ 131 #define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */ 132 #define R_AX_CH12_TXBD_IDX 0x1080 /* FWCMD Queue */ 133 #define R_AX_CH10_TXBD_IDX_V1 0x11D0 134 #define R_AX_CH11_TXBD_IDX_V1 0x11D4 135 #define R_AX_RXQ_RXBD_IDX_V1 0x1218 136 #define R_AX_RPQ_RXBD_IDX_V1 0x121C 137 #define TXBD_HW_IDX_MASK GENMASK(27, 16) 138 #define TXBD_HOST_IDX_MASK GENMASK(11, 0) 139 140 #define R_AX_ACH0_TXBD_DESA_L 0x1110 141 #define R_AX_ACH0_TXBD_DESA_H 0x1114 142 #define R_AX_ACH1_TXBD_DESA_L 0x1118 143 #define R_AX_ACH1_TXBD_DESA_H 0x111C 144 #define R_AX_ACH2_TXBD_DESA_L 0x1120 145 #define R_AX_ACH2_TXBD_DESA_H 0x1124 146 #define R_AX_ACH3_TXBD_DESA_L 0x1128 147 #define R_AX_ACH3_TXBD_DESA_H 0x112C 148 #define R_AX_ACH4_TXBD_DESA_L 0x1130 149 #define R_AX_ACH4_TXBD_DESA_H 0x1134 150 #define R_AX_ACH5_TXBD_DESA_L 0x1138 151 #define R_AX_ACH5_TXBD_DESA_H 0x113C 152 #define R_AX_ACH6_TXBD_DESA_L 0x1140 153 #define R_AX_ACH6_TXBD_DESA_H 0x1144 154 #define R_AX_ACH7_TXBD_DESA_L 0x1148 155 #define R_AX_ACH7_TXBD_DESA_H 0x114C 156 #define R_AX_CH8_TXBD_DESA_L 0x1150 157 #define R_AX_CH8_TXBD_DESA_H 0x1154 158 #define R_AX_CH9_TXBD_DESA_L 0x1158 159 #define R_AX_CH9_TXBD_DESA_H 0x115C 160 #define R_AX_CH10_TXBD_DESA_L 0x1358 161 #define R_AX_CH10_TXBD_DESA_H 0x135C 162 #define R_AX_CH11_TXBD_DESA_L 0x1360 163 #define R_AX_CH11_TXBD_DESA_H 0x1364 164 #define R_AX_CH12_TXBD_DESA_L 0x1160 165 #define R_AX_CH12_TXBD_DESA_H 0x1164 166 #define R_AX_RXQ_RXBD_DESA_L 0x1100 167 #define R_AX_RXQ_RXBD_DESA_H 0x1104 168 #define R_AX_RPQ_RXBD_DESA_L 0x1108 169 #define R_AX_RPQ_RXBD_DESA_H 0x110C 170 #define R_AX_RXQ_RXBD_DESA_L_V1 0x1220 171 #define R_AX_RXQ_RXBD_DESA_H_V1 0x1224 172 #define R_AX_RPQ_RXBD_DESA_L_V1 0x1228 173 #define R_AX_RPQ_RXBD_DESA_H_V1 0x122C 174 #define R_AX_ACH0_TXBD_DESA_L_V1 0x1230 175 #define R_AX_ACH0_TXBD_DESA_H_V1 0x1234 176 #define R_AX_ACH1_TXBD_DESA_L_V1 0x1238 177 #define R_AX_ACH1_TXBD_DESA_H_V1 0x123C 178 #define R_AX_ACH2_TXBD_DESA_L_V1 0x1240 179 #define R_AX_ACH2_TXBD_DESA_H_V1 0x1244 180 #define R_AX_ACH3_TXBD_DESA_L_V1 0x1248 181 #define R_AX_ACH3_TXBD_DESA_H_V1 0x124C 182 #define R_AX_ACH4_TXBD_DESA_L_V1 0x1250 183 #define R_AX_ACH4_TXBD_DESA_H_V1 0x1254 184 #define R_AX_ACH5_TXBD_DESA_L_V1 0x1258 185 #define R_AX_ACH5_TXBD_DESA_H_V1 0x125C 186 #define R_AX_ACH6_TXBD_DESA_L_V1 0x1260 187 #define R_AX_ACH6_TXBD_DESA_H_V1 0x1264 188 #define R_AX_ACH7_TXBD_DESA_L_V1 0x1268 189 #define R_AX_ACH7_TXBD_DESA_H_V1 0x126C 190 #define R_AX_CH8_TXBD_DESA_L_V1 0x1270 191 #define R_AX_CH8_TXBD_DESA_H_V1 0x1274 192 #define R_AX_CH9_TXBD_DESA_L_V1 0x1278 193 #define R_AX_CH9_TXBD_DESA_H_V1 0x127C 194 #define R_AX_CH12_TXBD_DESA_L_V1 0x1280 195 #define R_AX_CH12_TXBD_DESA_H_V1 0x1284 196 #define R_AX_CH10_TXBD_DESA_L_V1 0x1458 197 #define R_AX_CH10_TXBD_DESA_H_V1 0x145C 198 #define R_AX_CH11_TXBD_DESA_L_V1 0x1460 199 #define R_AX_CH11_TXBD_DESA_H_V1 0x1464 200 #define B_AX_DESC_NUM_MSK GENMASK(11, 0) 201 202 #define R_AX_RXQ_RXBD_NUM 0x1020 203 #define R_AX_RPQ_RXBD_NUM 0x1022 204 #define R_AX_ACH0_TXBD_NUM 0x1024 205 #define R_AX_ACH1_TXBD_NUM 0x1026 206 #define R_AX_ACH2_TXBD_NUM 0x1028 207 #define R_AX_ACH3_TXBD_NUM 0x102A 208 #define R_AX_ACH4_TXBD_NUM 0x102C 209 #define R_AX_ACH5_TXBD_NUM 0x102E 210 #define R_AX_ACH6_TXBD_NUM 0x1030 211 #define R_AX_ACH7_TXBD_NUM 0x1032 212 #define R_AX_CH8_TXBD_NUM 0x1034 213 #define R_AX_CH9_TXBD_NUM 0x1036 214 #define R_AX_CH10_TXBD_NUM 0x1338 215 #define R_AX_CH11_TXBD_NUM 0x133A 216 #define R_AX_CH12_TXBD_NUM 0x1038 217 #define R_AX_RXQ_RXBD_NUM_V1 0x1210 218 #define R_AX_RPQ_RXBD_NUM_V1 0x1212 219 #define R_AX_CH10_TXBD_NUM_V1 0x1438 220 #define R_AX_CH11_TXBD_NUM_V1 0x143A 221 222 #define R_AX_ACH0_BDRAM_CTRL 0x1200 223 #define R_AX_ACH1_BDRAM_CTRL 0x1204 224 #define R_AX_ACH2_BDRAM_CTRL 0x1208 225 #define R_AX_ACH3_BDRAM_CTRL 0x120C 226 #define R_AX_ACH4_BDRAM_CTRL 0x1210 227 #define R_AX_ACH5_BDRAM_CTRL 0x1214 228 #define R_AX_ACH6_BDRAM_CTRL 0x1218 229 #define R_AX_ACH7_BDRAM_CTRL 0x121C 230 #define R_AX_CH8_BDRAM_CTRL 0x1220 231 #define R_AX_CH9_BDRAM_CTRL 0x1224 232 #define R_AX_CH10_BDRAM_CTRL 0x1320 233 #define R_AX_CH11_BDRAM_CTRL 0x1324 234 #define R_AX_CH12_BDRAM_CTRL 0x1228 235 #define R_AX_ACH0_BDRAM_CTRL_V1 0x1300 236 #define R_AX_ACH1_BDRAM_CTRL_V1 0x1304 237 #define R_AX_ACH2_BDRAM_CTRL_V1 0x1308 238 #define R_AX_ACH3_BDRAM_CTRL_V1 0x130C 239 #define R_AX_ACH4_BDRAM_CTRL_V1 0x1310 240 #define R_AX_ACH5_BDRAM_CTRL_V1 0x1314 241 #define R_AX_ACH6_BDRAM_CTRL_V1 0x1318 242 #define R_AX_ACH7_BDRAM_CTRL_V1 0x131C 243 #define R_AX_CH8_BDRAM_CTRL_V1 0x1320 244 #define R_AX_CH9_BDRAM_CTRL_V1 0x1324 245 #define R_AX_CH12_BDRAM_CTRL_V1 0x1328 246 #define R_AX_CH10_BDRAM_CTRL_V1 0x1420 247 #define R_AX_CH11_BDRAM_CTRL_V1 0x1424 248 #define BDRAM_SIDX_MASK GENMASK(7, 0) 249 #define BDRAM_MAX_MASK GENMASK(15, 8) 250 #define BDRAM_MIN_MASK GENMASK(23, 16) 251 252 #define R_AX_PCIE_INIT_CFG1 0x1000 253 #define B_AX_PCIE_RXRST_KEEP_REG BIT(23) 254 #define B_AX_PCIE_TXRST_KEEP_REG BIT(22) 255 #define B_AX_PCIE_PERST_KEEP_REG BIT(21) 256 #define B_AX_PCIE_FLR_KEEP_REG BIT(20) 257 #define B_AX_PCIE_TRAIN_KEEP_REG BIT(19) 258 #define B_AX_RXBD_MODE BIT(18) 259 #define B_AX_PCIE_MAX_RXDMA_MASK GENMASK(16, 14) 260 #define B_AX_RXHCI_EN BIT(13) 261 #define B_AX_LATENCY_CONTROL BIT(12) 262 #define B_AX_TXHCI_EN BIT(11) 263 #define B_AX_PCIE_MAX_TXDMA_MASK GENMASK(10, 8) 264 #define B_AX_TX_TRUNC_MODE BIT(5) 265 #define B_AX_RX_TRUNC_MODE BIT(4) 266 #define B_AX_RST_BDRAM BIT(3) 267 #define B_AX_DIS_RXDMA_PRE BIT(2) 268 269 #define R_AX_TXDMA_ADDR_H 0x10F0 270 #define R_AX_RXDMA_ADDR_H 0x10F4 271 272 #define R_AX_PCIE_DMA_STOP1 0x1010 273 #define B_AX_STOP_PCIEIO BIT(20) 274 #define B_AX_STOP_WPDMA BIT(19) 275 #define B_AX_STOP_CH12 BIT(18) 276 #define B_AX_STOP_CH9 BIT(17) 277 #define B_AX_STOP_CH8 BIT(16) 278 #define B_AX_STOP_ACH7 BIT(15) 279 #define B_AX_STOP_ACH6 BIT(14) 280 #define B_AX_STOP_ACH5 BIT(13) 281 #define B_AX_STOP_ACH4 BIT(12) 282 #define B_AX_STOP_ACH3 BIT(11) 283 #define B_AX_STOP_ACH2 BIT(10) 284 #define B_AX_STOP_ACH1 BIT(9) 285 #define B_AX_STOP_ACH0 BIT(8) 286 #define B_AX_STOP_RPQ BIT(1) 287 #define B_AX_STOP_RXQ BIT(0) 288 #define B_AX_TX_STOP1_ALL GENMASK(18, 8) 289 290 #define R_AX_PCIE_DMA_STOP2 0x1310 291 #define B_AX_STOP_CH11 BIT(1) 292 #define B_AX_STOP_CH10 BIT(0) 293 #define B_AX_TX_STOP2_ALL GENMASK(1, 0) 294 295 #define R_AX_TXBD_RWPTR_CLR1 0x1014 296 #define B_AX_CLR_CH12_IDX BIT(10) 297 #define B_AX_CLR_CH9_IDX BIT(9) 298 #define B_AX_CLR_CH8_IDX BIT(8) 299 #define B_AX_CLR_ACH7_IDX BIT(7) 300 #define B_AX_CLR_ACH6_IDX BIT(6) 301 #define B_AX_CLR_ACH5_IDX BIT(5) 302 #define B_AX_CLR_ACH4_IDX BIT(4) 303 #define B_AX_CLR_ACH3_IDX BIT(3) 304 #define B_AX_CLR_ACH2_IDX BIT(2) 305 #define B_AX_CLR_ACH1_IDX BIT(1) 306 #define B_AX_CLR_ACH0_IDX BIT(0) 307 #define B_AX_TXBD_CLR1_ALL GENMASK(10, 0) 308 309 #define R_AX_RXBD_RWPTR_CLR 0x1018 310 #define B_AX_CLR_RPQ_IDX BIT(1) 311 #define B_AX_CLR_RXQ_IDX BIT(0) 312 #define B_AX_RXBD_CLR_ALL GENMASK(1, 0) 313 314 #define R_AX_TXBD_RWPTR_CLR2 0x1314 315 #define B_AX_CLR_CH11_IDX BIT(1) 316 #define B_AX_CLR_CH10_IDX BIT(0) 317 #define B_AX_TXBD_CLR2_ALL GENMASK(1, 0) 318 319 #define R_AX_PCIE_DMA_BUSY1 0x101C 320 #define B_AX_PCIEIO_RX_BUSY BIT(22) 321 #define B_AX_PCIEIO_TX_BUSY BIT(21) 322 #define B_AX_PCIEIO_BUSY BIT(20) 323 #define B_AX_WPDMA_BUSY BIT(19) 324 325 #define R_AX_PCIE_DMA_BUSY2 0x131C 326 #define B_AX_CH11_BUSY BIT(1) 327 #define B_AX_CH10_BUSY BIT(0) 328 329 /* Configure */ 330 #define R_AX_PCIE_INIT_CFG2 0x1004 331 #define B_AX_WD_ITVL_IDLE GENMASK(27, 24) 332 #define B_AX_WD_ITVL_ACT GENMASK(19, 16) 333 334 #define R_AX_PCIE_PS_CTRL 0x1008 335 #define B_AX_L1OFF_PWR_OFF_EN BIT(5) 336 337 #define R_AX_INT_MIT_RX 0x10D4 338 #define B_AX_RXMIT_RXP2_SEL BIT(19) 339 #define B_AX_RXMIT_RXP1_SEL BIT(18) 340 #define B_AX_RXTIMER_UNIT_MASK GENMASK(17, 16) 341 #define AX_RXTIMER_UNIT_64US 0 342 #define AX_RXTIMER_UNIT_128US 1 343 #define AX_RXTIMER_UNIT_256US 2 344 #define AX_RXTIMER_UNIT_512US 3 345 #define B_AX_RXCOUNTER_MATCH_MASK GENMASK(15, 8) 346 #define B_AX_RXTIMER_MATCH_MASK GENMASK(7, 0) 347 348 #define R_AX_DBG_ERR_FLAG 0x11C4 349 #define B_AX_PCIE_RPQ_FULL BIT(29) 350 #define B_AX_PCIE_RXQ_FULL BIT(28) 351 #define B_AX_CPL_STATUS_MASK GENMASK(27, 25) 352 #define B_AX_RX_STUCK BIT(22) 353 #define B_AX_TX_STUCK BIT(21) 354 #define B_AX_PCIEDBG_TXERR0 BIT(16) 355 #define B_AX_PCIE_RXP1_ERR0 BIT(4) 356 #define B_AX_PCIE_TXBD_LEN0 BIT(1) 357 #define B_AX_PCIE_TXBD_4KBOUD_LENERR BIT(0) 358 359 #define R_AX_LBC_WATCHDOG 0x11D8 360 #define B_AX_LBC_TIMER GENMASK(7, 4) 361 #define B_AX_LBC_FLAG BIT(1) 362 #define B_AX_LBC_EN BIT(0) 363 364 #define R_AX_PCIE_EXP_CTRL 0x13F0 365 #define B_AX_EN_CHKDSC_NO_RX_STUCK BIT(20) 366 #define B_AX_MAX_TAG_NUM GENMASK(18, 16) 367 #define B_AX_SIC_EN_FORCE_CLKREQ BIT(4) 368 369 #define R_AX_PCIE_RX_PREF_ADV 0x13F4 370 #define B_AX_RXDMA_PREF_ADV_EN BIT(0) 371 372 #define RTW89_PCI_TXBD_NUM_MAX 256 373 #define RTW89_PCI_RXBD_NUM_MAX 256 374 #define RTW89_PCI_TXWD_NUM_MAX 512 375 #define RTW89_PCI_TXWD_PAGE_SIZE 128 376 #define RTW89_PCI_ADDRINFO_MAX 4 377 #define RTW89_PCI_RX_BUF_SIZE 11460 378 379 #define RTW89_PCI_POLL_BDRAM_RST_CNT 100 380 #define RTW89_PCI_MULTITAG 8 381 382 /* PCIE CFG register */ 383 #define RTW89_PCIE_ASPM_CTRL 0x070F 384 #define RTW89_L1DLY_MASK GENMASK(5, 3) 385 #define RTW89_L0DLY_MASK GENMASK(2, 0) 386 #define RTW89_PCIE_TIMER_CTRL 0x0718 387 #define RTW89_PCIE_BIT_L1SUB BIT(5) 388 #define RTW89_PCIE_L1_CTRL 0x0719 389 #define RTW89_PCIE_BIT_CLK BIT(4) 390 #define RTW89_PCIE_BIT_L1 BIT(3) 391 #define RTW89_PCIE_CLK_CTRL 0x0725 392 #define RTW89_PCIE_RST_MSTATE 0x0B48 393 #define RTW89_PCIE_BIT_CFG_RST_MSTATE BIT(0) 394 #define RTW89_PCIE_PHY_RATE 0x82 395 #define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0) 396 #define INTF_INTGRA_MINREF_V1 90 397 #define INTF_INTGRA_HOSTREF_V1 100 398 399 enum rtw89_pcie_phy { 400 PCIE_PHY_GEN1, 401 PCIE_PHY_GEN2, 402 PCIE_PHY_GEN1_UNDEFINE = 0x7F, 403 }; 404 405 enum mac_ax_func_sw { 406 MAC_AX_FUNC_DIS, 407 MAC_AX_FUNC_EN, 408 }; 409 410 enum rtw89_pcie_l0sdly { 411 PCIE_L0SDLY_1US = 0, 412 PCIE_L0SDLY_2US = 1, 413 PCIE_L0SDLY_3US = 2, 414 PCIE_L0SDLY_4US = 3, 415 PCIE_L0SDLY_5US = 4, 416 PCIE_L0SDLY_6US = 5, 417 PCIE_L0SDLY_7US = 6, 418 }; 419 420 enum rtw89_pcie_l1dly { 421 PCIE_L1DLY_16US = 4, 422 PCIE_L1DLY_32US = 5, 423 PCIE_L1DLY_64US = 6, 424 PCIE_L1DLY_HW_INFI = 7, 425 }; 426 427 enum rtw89_pcie_clkdly_hw { 428 PCIE_CLKDLY_HW_0 = 0, 429 PCIE_CLKDLY_HW_30US = 0x1, 430 PCIE_CLKDLY_HW_50US = 0x2, 431 PCIE_CLKDLY_HW_100US = 0x3, 432 PCIE_CLKDLY_HW_150US = 0x4, 433 PCIE_CLKDLY_HW_200US = 0x5, 434 }; 435 436 struct rtw89_pci_ch_dma_addr { 437 u32 num; 438 u32 idx; 439 u32 bdram; 440 u32 desa_l; 441 u32 desa_h; 442 }; 443 444 struct rtw89_pci_ch_dma_addr_set { 445 struct rtw89_pci_ch_dma_addr tx[RTW89_TXCH_NUM]; 446 struct rtw89_pci_ch_dma_addr rx[RTW89_RXCH_NUM]; 447 }; 448 449 struct rtw89_pci_info { 450 const struct rtw89_pci_ch_dma_addr_set *dma_addr_set; 451 }; 452 453 struct rtw89_pci_bd_ram { 454 u8 start_idx; 455 u8 max_num; 456 u8 min_num; 457 }; 458 459 struct rtw89_pci_tx_data { 460 dma_addr_t dma; 461 }; 462 463 struct rtw89_pci_rx_info { 464 dma_addr_t dma; 465 u32 fs:1, ls:1, tag:11, len:14; 466 }; 467 468 #define RTW89_PCI_TXBD_OPTION_LS BIT(14) 469 470 struct rtw89_pci_tx_bd_32 { 471 __le16 length; 472 __le16 option; 473 __le32 dma; 474 } __packed; 475 476 #define RTW89_PCI_TXWP_VALID BIT(15) 477 478 struct rtw89_pci_tx_wp_info { 479 __le16 seq0; 480 __le16 seq1; 481 __le16 seq2; 482 __le16 seq3; 483 } __packed; 484 485 #define RTW89_PCI_ADDR_MSDU_LS BIT(15) 486 #define RTW89_PCI_ADDR_LS BIT(14) 487 #define RTW89_PCI_ADDR_HIGH(a) (((a) << 6) & GENMASK(13, 6)) 488 #define RTW89_PCI_ADDR_NUM(x) ((x) & GENMASK(5, 0)) 489 490 struct rtw89_pci_tx_addr_info_32 { 491 __le16 length; 492 __le16 option; 493 __le32 dma; 494 } __packed; 495 496 #define RTW89_PCI_RPP_POLLUTED BIT(31) 497 #define RTW89_PCI_RPP_SEQ GENMASK(30, 16) 498 #define RTW89_PCI_RPP_TX_STATUS GENMASK(15, 13) 499 #define RTW89_TX_DONE 0x0 500 #define RTW89_TX_RETRY_LIMIT 0x1 501 #define RTW89_TX_LIFE_TIME 0x2 502 #define RTW89_TX_MACID_DROP 0x3 503 #define RTW89_PCI_RPP_QSEL GENMASK(12, 8) 504 #define RTW89_PCI_RPP_MACID GENMASK(7, 0) 505 506 struct rtw89_pci_rpp_fmt { 507 __le32 dword; 508 } __packed; 509 510 struct rtw89_pci_rx_bd_32 { 511 __le16 buf_size; 512 __le16 rsvd; 513 __le32 dma; 514 } __packed; 515 516 #define RTW89_PCI_RXBD_FS BIT(15) 517 #define RTW89_PCI_RXBD_LS BIT(14) 518 #define RTW89_PCI_RXBD_WRITE_SIZE GENMASK(13, 0) 519 #define RTW89_PCI_RXBD_TAG GENMASK(28, 16) 520 521 struct rtw89_pci_rxbd_info { 522 __le32 dword; 523 }; 524 525 struct rtw89_pci_tx_wd { 526 struct list_head list; 527 struct sk_buff_head queue; 528 529 void *vaddr; 530 dma_addr_t paddr; 531 u32 len; 532 u32 seq; 533 }; 534 535 struct rtw89_pci_dma_ring { 536 void *head; 537 u8 desc_size; 538 dma_addr_t dma; 539 540 struct rtw89_pci_ch_dma_addr addr; 541 542 u32 len; 543 u32 wp; /* host idx */ 544 u32 rp; /* hw idx */ 545 }; 546 547 struct rtw89_pci_tx_wd_ring { 548 void *head; 549 dma_addr_t dma; 550 551 struct rtw89_pci_tx_wd pages[RTW89_PCI_TXWD_NUM_MAX]; 552 struct list_head free_pages; 553 554 u32 page_size; 555 u32 page_num; 556 u32 curr_num; 557 }; 558 559 #define RTW89_RX_TAG_MAX 0x1fff 560 561 struct rtw89_pci_tx_ring { 562 struct rtw89_pci_tx_wd_ring wd_ring; 563 struct rtw89_pci_dma_ring bd_ring; 564 struct list_head busy_pages; 565 u8 txch; 566 bool dma_enabled; 567 u16 tag; /* range from 0x0001 ~ 0x1fff */ 568 569 u64 tx_cnt; 570 u64 tx_acked; 571 u64 tx_retry_lmt; 572 u64 tx_life_time; 573 u64 tx_mac_id_drop; 574 }; 575 576 struct rtw89_pci_rx_ring { 577 struct rtw89_pci_dma_ring bd_ring; 578 struct sk_buff *buf[RTW89_PCI_RXBD_NUM_MAX]; 579 u32 buf_sz; 580 struct sk_buff *diliver_skb; 581 struct rtw89_rx_desc_info diliver_desc; 582 }; 583 584 struct rtw89_pci_isrs { 585 u32 halt_c2h_isrs; 586 u32 isrs[2]; 587 }; 588 589 struct rtw89_pci { 590 struct pci_dev *pdev; 591 592 /* protect HW irq related registers */ 593 spinlock_t irq_lock; 594 /* protect TRX resources (exclude RXQ) */ 595 spinlock_t trx_lock; 596 bool running; 597 struct rtw89_pci_tx_ring tx_rings[RTW89_TXCH_NUM]; 598 struct rtw89_pci_rx_ring rx_rings[RTW89_RXCH_NUM]; 599 struct sk_buff_head h2c_queue; 600 struct sk_buff_head h2c_release_queue; 601 602 u32 halt_c2h_intrs; 603 u32 intrs[2]; 604 void __iomem *mmap; 605 }; 606 607 static inline struct rtw89_pci_rx_info *RTW89_PCI_RX_SKB_CB(struct sk_buff *skb) 608 { 609 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 610 611 BUILD_BUG_ON(sizeof(struct rtw89_pci_tx_data) > 612 sizeof(info->status.status_driver_data)); 613 614 return (struct rtw89_pci_rx_info *)skb->cb; 615 } 616 617 static inline struct rtw89_pci_rx_bd_32 * 618 RTW89_PCI_RX_BD(struct rtw89_pci_rx_ring *rx_ring, u32 idx) 619 { 620 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 621 u8 *head = bd_ring->head; 622 u32 desc_size = bd_ring->desc_size; 623 u32 offset = idx * desc_size; 624 625 return (struct rtw89_pci_rx_bd_32 *)(head + offset); 626 } 627 628 static inline void 629 rtw89_pci_rxbd_increase(struct rtw89_pci_rx_ring *rx_ring, u32 cnt) 630 { 631 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 632 633 bd_ring->wp += cnt; 634 635 if (bd_ring->wp >= bd_ring->len) 636 bd_ring->wp -= bd_ring->len; 637 } 638 639 static inline struct rtw89_pci_tx_data *RTW89_PCI_TX_SKB_CB(struct sk_buff *skb) 640 { 641 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 642 643 return (struct rtw89_pci_tx_data *)info->status.status_driver_data; 644 } 645 646 static inline struct rtw89_pci_tx_bd_32 * 647 rtw89_pci_get_next_txbd(struct rtw89_pci_tx_ring *tx_ring) 648 { 649 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 650 struct rtw89_pci_tx_bd_32 *tx_bd, *head; 651 652 head = bd_ring->head; 653 tx_bd = head + bd_ring->wp; 654 655 return tx_bd; 656 } 657 658 static inline struct rtw89_pci_tx_wd * 659 rtw89_pci_dequeue_txwd(struct rtw89_pci_tx_ring *tx_ring) 660 { 661 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 662 struct rtw89_pci_tx_wd *txwd; 663 664 txwd = list_first_entry_or_null(&wd_ring->free_pages, 665 struct rtw89_pci_tx_wd, list); 666 if (!txwd) 667 return NULL; 668 669 list_del_init(&txwd->list); 670 txwd->len = 0; 671 wd_ring->curr_num--; 672 673 return txwd; 674 } 675 676 static inline void 677 rtw89_pci_enqueue_txwd(struct rtw89_pci_tx_ring *tx_ring, 678 struct rtw89_pci_tx_wd *txwd) 679 { 680 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 681 682 memset(txwd->vaddr, 0, wd_ring->page_size); 683 list_add_tail(&txwd->list, &wd_ring->free_pages); 684 wd_ring->curr_num++; 685 } 686 687 static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val) 688 { 689 return val == 0xffffffff || val == 0xeaeaeaea; 690 } 691 692 extern const struct dev_pm_ops rtw89_pm_ops; 693 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set; 694 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1; 695 696 struct pci_device_id; 697 698 int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); 699 void rtw89_pci_remove(struct pci_dev *pdev); 700 701 #endif 702