1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2020 Realtek Corporation 3 */ 4 5 #include <linux/pci.h> 6 7 #include "mac.h" 8 #include "pci.h" 9 #include "reg.h" 10 #include "ser.h" 11 12 static bool rtw89_pci_disable_clkreq; 13 static bool rtw89_pci_disable_aspm_l1; 14 static bool rtw89_pci_disable_l1ss; 15 module_param_named(disable_clkreq, rtw89_pci_disable_clkreq, bool, 0644); 16 module_param_named(disable_aspm_l1, rtw89_pci_disable_aspm_l1, bool, 0644); 17 module_param_named(disable_aspm_l1ss, rtw89_pci_disable_l1ss, bool, 0644); 18 MODULE_PARM_DESC(disable_clkreq, "Set Y to disable PCI clkreq support"); 19 MODULE_PARM_DESC(disable_aspm_l1, "Set Y to disable PCI ASPM L1 support"); 20 MODULE_PARM_DESC(disable_aspm_l1ss, "Set Y to disable PCI L1SS support"); 21 22 static int rtw89_pci_rst_bdram_pcie(struct rtw89_dev *rtwdev) 23 { 24 u32 val; 25 int ret; 26 27 rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1, 28 rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) | B_AX_RST_BDRAM); 29 30 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_RST_BDRAM), 31 1, RTW89_PCI_POLL_BDRAM_RST_CNT, false, 32 rtwdev, R_AX_PCIE_INIT_CFG1); 33 34 if (ret) 35 return -EBUSY; 36 37 return 0; 38 } 39 40 static u32 rtw89_pci_dma_recalc(struct rtw89_dev *rtwdev, 41 struct rtw89_pci_dma_ring *bd_ring, 42 u32 cur_idx, bool tx) 43 { 44 u32 cnt, cur_rp, wp, rp, len; 45 46 rp = bd_ring->rp; 47 wp = bd_ring->wp; 48 len = bd_ring->len; 49 50 cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx); 51 if (tx) 52 cnt = cur_rp >= rp ? cur_rp - rp : len - (rp - cur_rp); 53 else 54 cnt = cur_rp >= wp ? cur_rp - wp : len - (wp - cur_rp); 55 56 bd_ring->rp = cur_rp; 57 58 return cnt; 59 } 60 61 static u32 rtw89_pci_txbd_recalc(struct rtw89_dev *rtwdev, 62 struct rtw89_pci_tx_ring *tx_ring) 63 { 64 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 65 u32 addr_idx = bd_ring->addr_idx; 66 u32 cnt, idx; 67 68 idx = rtw89_read32(rtwdev, addr_idx); 69 cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, true); 70 71 return cnt; 72 } 73 74 static void rtw89_pci_release_fwcmd(struct rtw89_dev *rtwdev, 75 struct rtw89_pci *rtwpci, 76 u32 cnt, bool release_all) 77 { 78 struct rtw89_pci_tx_data *tx_data; 79 struct sk_buff *skb; 80 u32 qlen; 81 82 while (cnt--) { 83 skb = skb_dequeue(&rtwpci->h2c_queue); 84 if (!skb) { 85 rtw89_err(rtwdev, "failed to pre-release fwcmd\n"); 86 return; 87 } 88 skb_queue_tail(&rtwpci->h2c_release_queue, skb); 89 } 90 91 qlen = skb_queue_len(&rtwpci->h2c_release_queue); 92 if (!release_all) 93 qlen = qlen > RTW89_PCI_MULTITAG ? qlen - RTW89_PCI_MULTITAG : 0; 94 95 while (qlen--) { 96 skb = skb_dequeue(&rtwpci->h2c_release_queue); 97 if (!skb) { 98 rtw89_err(rtwdev, "failed to release fwcmd\n"); 99 return; 100 } 101 tx_data = RTW89_PCI_TX_SKB_CB(skb); 102 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, 103 DMA_TO_DEVICE); 104 dev_kfree_skb_any(skb); 105 } 106 } 107 108 static void rtw89_pci_reclaim_tx_fwcmd(struct rtw89_dev *rtwdev, 109 struct rtw89_pci *rtwpci) 110 { 111 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12]; 112 u32 cnt; 113 114 cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring); 115 if (!cnt) 116 return; 117 rtw89_pci_release_fwcmd(rtwdev, rtwpci, cnt, false); 118 } 119 120 static u32 rtw89_pci_rxbd_recalc(struct rtw89_dev *rtwdev, 121 struct rtw89_pci_rx_ring *rx_ring) 122 { 123 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 124 u32 addr_idx = bd_ring->addr_idx; 125 u32 cnt, idx; 126 127 idx = rtw89_read32(rtwdev, addr_idx); 128 cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, false); 129 130 return cnt; 131 } 132 133 static void rtw89_pci_sync_skb_for_cpu(struct rtw89_dev *rtwdev, 134 struct sk_buff *skb) 135 { 136 struct rtw89_pci_rx_info *rx_info; 137 dma_addr_t dma; 138 139 rx_info = RTW89_PCI_RX_SKB_CB(skb); 140 dma = rx_info->dma; 141 dma_sync_single_for_cpu(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE, 142 DMA_FROM_DEVICE); 143 } 144 145 static void rtw89_pci_sync_skb_for_device(struct rtw89_dev *rtwdev, 146 struct sk_buff *skb) 147 { 148 struct rtw89_pci_rx_info *rx_info; 149 dma_addr_t dma; 150 151 rx_info = RTW89_PCI_RX_SKB_CB(skb); 152 dma = rx_info->dma; 153 dma_sync_single_for_device(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE, 154 DMA_FROM_DEVICE); 155 } 156 157 static int rtw89_pci_rxbd_info_update(struct rtw89_dev *rtwdev, 158 struct sk_buff *skb) 159 { 160 struct rtw89_pci_rxbd_info *rxbd_info; 161 struct rtw89_pci_rx_info *rx_info = RTW89_PCI_RX_SKB_CB(skb); 162 163 rxbd_info = (struct rtw89_pci_rxbd_info *)skb->data; 164 rx_info->fs = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_FS); 165 rx_info->ls = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_LS); 166 rx_info->len = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_WRITE_SIZE); 167 rx_info->tag = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_TAG); 168 169 return 0; 170 } 171 172 static bool 173 rtw89_skb_put_rx_data(struct rtw89_dev *rtwdev, bool fs, bool ls, 174 struct sk_buff *new, 175 const struct sk_buff *skb, u32 offset, 176 const struct rtw89_pci_rx_info *rx_info, 177 const struct rtw89_rx_desc_info *desc_info) 178 { 179 u32 copy_len = rx_info->len - offset; 180 181 if (unlikely(skb_tailroom(new) < copy_len)) { 182 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 183 "invalid rx data length bd_len=%d desc_len=%d offset=%d (fs=%d ls=%d)\n", 184 rx_info->len, desc_info->pkt_size, offset, fs, ls); 185 rtw89_hex_dump(rtwdev, RTW89_DBG_TXRX, "rx_data: ", 186 skb->data, rx_info->len); 187 /* length of a single segment skb is desc_info->pkt_size */ 188 if (fs && ls) { 189 copy_len = desc_info->pkt_size; 190 } else { 191 rtw89_info(rtwdev, "drop rx data due to invalid length\n"); 192 return false; 193 } 194 } 195 196 skb_put_data(new, skb->data + offset, copy_len); 197 198 return true; 199 } 200 201 static u32 rtw89_pci_rxbd_deliver_skbs(struct rtw89_dev *rtwdev, 202 struct rtw89_pci_rx_ring *rx_ring) 203 { 204 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 205 struct rtw89_pci_rx_info *rx_info; 206 struct rtw89_rx_desc_info *desc_info = &rx_ring->diliver_desc; 207 struct sk_buff *new = rx_ring->diliver_skb; 208 struct sk_buff *skb; 209 u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info); 210 u32 offset; 211 u32 cnt = 1; 212 bool fs, ls; 213 int ret; 214 215 skb = rx_ring->buf[bd_ring->wp]; 216 rtw89_pci_sync_skb_for_cpu(rtwdev, skb); 217 218 ret = rtw89_pci_rxbd_info_update(rtwdev, skb); 219 if (ret) { 220 rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n", 221 bd_ring->wp, ret); 222 goto err_sync_device; 223 } 224 225 rx_info = RTW89_PCI_RX_SKB_CB(skb); 226 fs = rx_info->fs; 227 ls = rx_info->ls; 228 229 if (fs) { 230 if (new) { 231 rtw89_err(rtwdev, "skb should not be ready before first segment start\n"); 232 goto err_sync_device; 233 } 234 if (desc_info->ready) { 235 rtw89_warn(rtwdev, "desc info should not be ready before first segment start\n"); 236 goto err_sync_device; 237 } 238 239 rtw89_core_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size); 240 241 new = dev_alloc_skb(desc_info->pkt_size); 242 if (!new) 243 goto err_sync_device; 244 245 rx_ring->diliver_skb = new; 246 247 /* first segment has RX desc */ 248 offset = desc_info->offset; 249 offset += desc_info->long_rxdesc ? sizeof(struct rtw89_rxdesc_long) : 250 sizeof(struct rtw89_rxdesc_short); 251 } else { 252 offset = sizeof(struct rtw89_pci_rxbd_info); 253 if (!new) { 254 rtw89_warn(rtwdev, "no last skb\n"); 255 goto err_sync_device; 256 } 257 } 258 if (!rtw89_skb_put_rx_data(rtwdev, fs, ls, new, skb, offset, rx_info, desc_info)) 259 goto err_sync_device; 260 rtw89_pci_sync_skb_for_device(rtwdev, skb); 261 rtw89_pci_rxbd_increase(rx_ring, 1); 262 263 if (!desc_info->ready) { 264 rtw89_warn(rtwdev, "no rx desc information\n"); 265 goto err_free_resource; 266 } 267 if (ls) { 268 rtw89_core_rx(rtwdev, desc_info, new); 269 rx_ring->diliver_skb = NULL; 270 desc_info->ready = false; 271 } 272 273 return cnt; 274 275 err_sync_device: 276 rtw89_pci_sync_skb_for_device(rtwdev, skb); 277 rtw89_pci_rxbd_increase(rx_ring, 1); 278 err_free_resource: 279 if (new) 280 dev_kfree_skb_any(new); 281 rx_ring->diliver_skb = NULL; 282 desc_info->ready = false; 283 284 return cnt; 285 } 286 287 static void rtw89_pci_rxbd_deliver(struct rtw89_dev *rtwdev, 288 struct rtw89_pci_rx_ring *rx_ring, 289 u32 cnt) 290 { 291 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 292 u32 rx_cnt; 293 294 while (cnt && rtwdev->napi_budget_countdown > 0) { 295 rx_cnt = rtw89_pci_rxbd_deliver_skbs(rtwdev, rx_ring); 296 if (!rx_cnt) { 297 rtw89_err(rtwdev, "failed to deliver RXBD skb\n"); 298 299 /* skip the rest RXBD bufs */ 300 rtw89_pci_rxbd_increase(rx_ring, cnt); 301 break; 302 } 303 304 cnt -= rx_cnt; 305 } 306 307 rtw89_write16(rtwdev, bd_ring->addr_idx, bd_ring->wp); 308 } 309 310 static int rtw89_pci_poll_rxq_dma(struct rtw89_dev *rtwdev, 311 struct rtw89_pci *rtwpci, int budget) 312 { 313 struct rtw89_pci_rx_ring *rx_ring; 314 int countdown = rtwdev->napi_budget_countdown; 315 u32 cnt; 316 317 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RXQ]; 318 319 cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); 320 if (!cnt) 321 return 0; 322 323 cnt = min_t(u32, budget, cnt); 324 325 rtw89_pci_rxbd_deliver(rtwdev, rx_ring, cnt); 326 327 /* In case of flushing pending SKBs, the countdown may exceed. */ 328 if (rtwdev->napi_budget_countdown <= 0) 329 return budget; 330 331 return budget - countdown; 332 } 333 334 static void rtw89_pci_tx_status(struct rtw89_dev *rtwdev, 335 struct rtw89_pci_tx_ring *tx_ring, 336 struct sk_buff *skb, u8 tx_status) 337 { 338 struct ieee80211_tx_info *info; 339 340 info = IEEE80211_SKB_CB(skb); 341 ieee80211_tx_info_clear_status(info); 342 343 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 344 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 345 if (tx_status == RTW89_TX_DONE) { 346 info->flags |= IEEE80211_TX_STAT_ACK; 347 tx_ring->tx_acked++; 348 } else { 349 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) 350 rtw89_debug(rtwdev, RTW89_DBG_FW, 351 "failed to TX of status %x\n", tx_status); 352 switch (tx_status) { 353 case RTW89_TX_RETRY_LIMIT: 354 tx_ring->tx_retry_lmt++; 355 break; 356 case RTW89_TX_LIFE_TIME: 357 tx_ring->tx_life_time++; 358 break; 359 case RTW89_TX_MACID_DROP: 360 tx_ring->tx_mac_id_drop++; 361 break; 362 default: 363 rtw89_warn(rtwdev, "invalid TX status %x\n", tx_status); 364 break; 365 } 366 } 367 368 ieee80211_tx_status_ni(rtwdev->hw, skb); 369 } 370 371 static void rtw89_pci_reclaim_txbd(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) 372 { 373 struct rtw89_pci_tx_wd *txwd; 374 u32 cnt; 375 376 cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring); 377 while (cnt--) { 378 txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list); 379 if (!txwd) { 380 rtw89_warn(rtwdev, "No busy txwd pages available\n"); 381 break; 382 } 383 384 list_del_init(&txwd->list); 385 } 386 } 387 388 static void rtw89_pci_release_busy_txwd(struct rtw89_dev *rtwdev, 389 struct rtw89_pci_tx_ring *tx_ring) 390 { 391 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 392 struct rtw89_pci_tx_wd *txwd; 393 int i; 394 395 for (i = 0; i < wd_ring->page_num; i++) { 396 txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list); 397 if (!txwd) 398 break; 399 400 list_del_init(&txwd->list); 401 } 402 } 403 404 static void rtw89_pci_release_txwd_skb(struct rtw89_dev *rtwdev, 405 struct rtw89_pci_tx_ring *tx_ring, 406 struct rtw89_pci_tx_wd *txwd, u16 seq, 407 u8 tx_status) 408 { 409 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 410 struct rtw89_pci_tx_data *tx_data; 411 struct sk_buff *skb, *tmp; 412 u8 txch = tx_ring->txch; 413 414 if (!list_empty(&txwd->list)) { 415 rtw89_warn(rtwdev, "queue %d txwd %d is not idle\n", 416 txch, seq); 417 return; 418 } 419 420 /* currently, support for only one frame */ 421 if (skb_queue_len(&txwd->queue) != 1) { 422 rtw89_warn(rtwdev, "empty pending queue %d page %d\n", 423 txch, seq); 424 return; 425 } 426 427 skb_queue_walk_safe(&txwd->queue, skb, tmp) { 428 skb_unlink(skb, &txwd->queue); 429 430 tx_data = RTW89_PCI_TX_SKB_CB(skb); 431 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, 432 DMA_TO_DEVICE); 433 434 rtw89_pci_tx_status(rtwdev, tx_ring, skb, tx_status); 435 } 436 437 rtw89_pci_enqueue_txwd(tx_ring, txwd); 438 } 439 440 static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev, 441 struct rtw89_pci_rpp_fmt *rpp) 442 { 443 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 444 struct rtw89_pci_tx_ring *tx_ring; 445 struct rtw89_pci_tx_wd_ring *wd_ring; 446 struct rtw89_pci_tx_wd *txwd; 447 u16 seq; 448 u8 qsel, tx_status, txch; 449 450 seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ); 451 qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL); 452 tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS); 453 txch = rtw89_core_get_ch_dma(rtwdev, qsel); 454 455 if (txch == RTW89_TXCH_CH12) { 456 rtw89_warn(rtwdev, "should no fwcmd release report\n"); 457 return; 458 } 459 460 tx_ring = &rtwpci->tx_rings[txch]; 461 rtw89_pci_reclaim_txbd(rtwdev, tx_ring); 462 wd_ring = &tx_ring->wd_ring; 463 txwd = &wd_ring->pages[seq]; 464 465 rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, seq, tx_status); 466 } 467 468 static void rtw89_pci_release_pending_txwd_skb(struct rtw89_dev *rtwdev, 469 struct rtw89_pci_tx_ring *tx_ring) 470 { 471 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 472 struct rtw89_pci_tx_wd *txwd; 473 int i; 474 475 for (i = 0; i < wd_ring->page_num; i++) { 476 txwd = &wd_ring->pages[i]; 477 478 if (!list_empty(&txwd->list)) 479 continue; 480 481 rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, i, RTW89_TX_MACID_DROP); 482 } 483 } 484 485 static u32 rtw89_pci_release_tx_skbs(struct rtw89_dev *rtwdev, 486 struct rtw89_pci_rx_ring *rx_ring, 487 u32 max_cnt) 488 { 489 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 490 struct rtw89_pci_rx_info *rx_info; 491 struct rtw89_pci_rpp_fmt *rpp; 492 struct rtw89_rx_desc_info desc_info = {}; 493 struct sk_buff *skb; 494 u32 cnt = 0; 495 u32 rpp_size = sizeof(struct rtw89_pci_rpp_fmt); 496 u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info); 497 u32 offset; 498 int ret; 499 500 skb = rx_ring->buf[bd_ring->wp]; 501 rtw89_pci_sync_skb_for_cpu(rtwdev, skb); 502 503 ret = rtw89_pci_rxbd_info_update(rtwdev, skb); 504 if (ret) { 505 rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n", 506 bd_ring->wp, ret); 507 goto err_sync_device; 508 } 509 510 rx_info = RTW89_PCI_RX_SKB_CB(skb); 511 if (!rx_info->fs || !rx_info->ls) { 512 rtw89_err(rtwdev, "cannot process RP frame not set FS/LS\n"); 513 return cnt; 514 } 515 516 rtw89_core_query_rxdesc(rtwdev, &desc_info, skb->data, rxinfo_size); 517 518 /* first segment has RX desc */ 519 offset = desc_info.offset; 520 offset += desc_info.long_rxdesc ? sizeof(struct rtw89_rxdesc_long) : 521 sizeof(struct rtw89_rxdesc_short); 522 for (; offset + rpp_size <= rx_info->len; offset += rpp_size) { 523 rpp = (struct rtw89_pci_rpp_fmt *)(skb->data + offset); 524 rtw89_pci_release_rpp(rtwdev, rpp); 525 } 526 527 rtw89_pci_sync_skb_for_device(rtwdev, skb); 528 rtw89_pci_rxbd_increase(rx_ring, 1); 529 cnt++; 530 531 return cnt; 532 533 err_sync_device: 534 rtw89_pci_sync_skb_for_device(rtwdev, skb); 535 return 0; 536 } 537 538 static void rtw89_pci_release_tx(struct rtw89_dev *rtwdev, 539 struct rtw89_pci_rx_ring *rx_ring, 540 u32 cnt) 541 { 542 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 543 u32 release_cnt; 544 545 while (cnt) { 546 release_cnt = rtw89_pci_release_tx_skbs(rtwdev, rx_ring, cnt); 547 if (!release_cnt) { 548 rtw89_err(rtwdev, "failed to release TX skbs\n"); 549 550 /* skip the rest RXBD bufs */ 551 rtw89_pci_rxbd_increase(rx_ring, cnt); 552 break; 553 } 554 555 cnt -= release_cnt; 556 } 557 558 rtw89_write16(rtwdev, bd_ring->addr_idx, bd_ring->wp); 559 } 560 561 static int rtw89_pci_poll_rpq_dma(struct rtw89_dev *rtwdev, 562 struct rtw89_pci *rtwpci, int budget) 563 { 564 struct rtw89_pci_rx_ring *rx_ring; 565 u32 cnt; 566 int work_done; 567 568 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; 569 570 spin_lock_bh(&rtwpci->trx_lock); 571 572 cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); 573 if (cnt == 0) 574 goto out_unlock; 575 576 rtw89_pci_release_tx(rtwdev, rx_ring, cnt); 577 578 out_unlock: 579 spin_unlock_bh(&rtwpci->trx_lock); 580 581 /* always release all RPQ */ 582 work_done = min_t(int, cnt, budget); 583 rtwdev->napi_budget_countdown -= work_done; 584 585 return work_done; 586 } 587 588 static void rtw89_pci_isr_rxd_unavail(struct rtw89_dev *rtwdev, 589 struct rtw89_pci *rtwpci) 590 { 591 struct rtw89_pci_rx_ring *rx_ring; 592 struct rtw89_pci_dma_ring *bd_ring; 593 u32 reg_idx; 594 u16 hw_idx, hw_idx_next, host_idx; 595 int i; 596 597 for (i = 0; i < RTW89_RXCH_NUM; i++) { 598 rx_ring = &rtwpci->rx_rings[i]; 599 bd_ring = &rx_ring->bd_ring; 600 601 reg_idx = rtw89_read32(rtwdev, bd_ring->addr_idx); 602 hw_idx = FIELD_GET(TXBD_HW_IDX_MASK, reg_idx); 603 host_idx = FIELD_GET(TXBD_HOST_IDX_MASK, reg_idx); 604 hw_idx_next = (hw_idx + 1) % bd_ring->len; 605 606 if (hw_idx_next == host_idx) 607 rtw89_warn(rtwdev, "%d RXD unavailable\n", i); 608 609 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 610 "%d RXD unavailable, idx=0x%08x, len=%d\n", 611 i, reg_idx, bd_ring->len); 612 } 613 } 614 615 static void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev, 616 struct rtw89_pci *rtwpci, 617 struct rtw89_pci_isrs *isrs) 618 { 619 isrs->halt_c2h_isrs = rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs; 620 isrs->isrs[0] = rtw89_read32(rtwdev, R_AX_PCIE_HISR00) & rtwpci->intrs[0]; 621 isrs->isrs[1] = rtw89_read32(rtwdev, R_AX_PCIE_HISR10) & rtwpci->intrs[1]; 622 623 rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs); 624 rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isrs->isrs[0]); 625 rtw89_write32(rtwdev, R_AX_PCIE_HISR10, isrs->isrs[1]); 626 } 627 628 static void rtw89_pci_clear_isr0(struct rtw89_dev *rtwdev, u32 isr00) 629 { 630 /* write 1 clear */ 631 rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isr00); 632 } 633 634 static void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, 635 struct rtw89_pci *rtwpci) 636 { 637 rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs); 638 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, rtwpci->intrs[0]); 639 rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, rtwpci->intrs[1]); 640 } 641 642 static void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, 643 struct rtw89_pci *rtwpci) 644 { 645 rtw89_write32(rtwdev, R_AX_HIMR0, 0); 646 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, 0); 647 rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, 0); 648 } 649 650 static irqreturn_t rtw89_pci_interrupt_threadfn(int irq, void *dev) 651 { 652 struct rtw89_dev *rtwdev = dev; 653 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 654 struct rtw89_pci_isrs isrs; 655 unsigned long flags; 656 657 spin_lock_irqsave(&rtwpci->irq_lock, flags); 658 rtw89_pci_recognize_intrs(rtwdev, rtwpci, &isrs); 659 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 660 661 if (unlikely(isrs.isrs[0] & B_AX_RDU_INT)) 662 rtw89_pci_isr_rxd_unavail(rtwdev, rtwpci); 663 664 if (unlikely(isrs.halt_c2h_isrs & B_AX_HALT_C2H_INT_EN)) 665 rtw89_ser_notify(rtwdev, rtw89_mac_get_err_status(rtwdev)); 666 667 if (likely(rtwpci->running)) { 668 local_bh_disable(); 669 napi_schedule(&rtwdev->napi); 670 local_bh_enable(); 671 } 672 673 return IRQ_HANDLED; 674 } 675 676 static irqreturn_t rtw89_pci_interrupt_handler(int irq, void *dev) 677 { 678 struct rtw89_dev *rtwdev = dev; 679 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 680 unsigned long flags; 681 irqreturn_t irqret = IRQ_WAKE_THREAD; 682 683 spin_lock_irqsave(&rtwpci->irq_lock, flags); 684 685 /* If interrupt event is on the road, it is still trigger interrupt 686 * even we have done pci_stop() to turn off IMR. 687 */ 688 if (unlikely(!rtwpci->running)) { 689 irqret = IRQ_HANDLED; 690 goto exit; 691 } 692 693 rtw89_pci_disable_intr(rtwdev, rtwpci); 694 exit: 695 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 696 697 return irqret; 698 } 699 700 #define case_TXCHADDRS(txch) \ 701 case RTW89_TXCH_##txch: \ 702 *addr_num = R_AX_##txch##_TXBD_NUM; \ 703 *addr_idx = R_AX_##txch##_TXBD_IDX; \ 704 *addr_bdram = R_AX_##txch##_BDRAM_CTRL; \ 705 *addr_desa_l = R_AX_##txch##_TXBD_DESA_L; \ 706 *addr_desa_h = R_AX_##txch##_TXBD_DESA_H; \ 707 break 708 709 static int rtw89_pci_get_txch_addrs(enum rtw89_tx_channel txch, 710 u32 *addr_num, 711 u32 *addr_idx, 712 u32 *addr_bdram, 713 u32 *addr_desa_l, 714 u32 *addr_desa_h) 715 { 716 switch (txch) { 717 case_TXCHADDRS(ACH0); 718 case_TXCHADDRS(ACH1); 719 case_TXCHADDRS(ACH2); 720 case_TXCHADDRS(ACH3); 721 case_TXCHADDRS(ACH4); 722 case_TXCHADDRS(ACH5); 723 case_TXCHADDRS(ACH6); 724 case_TXCHADDRS(ACH7); 725 case_TXCHADDRS(CH8); 726 case_TXCHADDRS(CH9); 727 case_TXCHADDRS(CH10); 728 case_TXCHADDRS(CH11); 729 case_TXCHADDRS(CH12); 730 default: 731 return -EINVAL; 732 } 733 734 return 0; 735 } 736 737 #undef case_TXCHADDRS 738 739 #define case_RXCHADDRS(rxch) \ 740 case RTW89_RXCH_##rxch: \ 741 *addr_num = R_AX_##rxch##_RXBD_NUM; \ 742 *addr_idx = R_AX_##rxch##_RXBD_IDX; \ 743 *addr_desa_l = R_AX_##rxch##_RXBD_DESA_L; \ 744 *addr_desa_h = R_AX_##rxch##_RXBD_DESA_H; \ 745 break 746 747 static int rtw89_pci_get_rxch_addrs(enum rtw89_rx_channel rxch, 748 u32 *addr_num, 749 u32 *addr_idx, 750 u32 *addr_desa_l, 751 u32 *addr_desa_h) 752 { 753 switch (rxch) { 754 case_RXCHADDRS(RXQ); 755 case_RXCHADDRS(RPQ); 756 default: 757 return -EINVAL; 758 } 759 760 return 0; 761 } 762 763 #undef case_RXCHADDRS 764 765 static u32 rtw89_pci_get_avail_txbd_num(struct rtw89_pci_tx_ring *ring) 766 { 767 struct rtw89_pci_dma_ring *bd_ring = &ring->bd_ring; 768 769 /* reserved 1 desc check ring is full or not */ 770 if (bd_ring->rp > bd_ring->wp) 771 return bd_ring->rp - bd_ring->wp - 1; 772 773 return bd_ring->len - (bd_ring->wp - bd_ring->rp) - 1; 774 } 775 776 static 777 u32 __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(struct rtw89_dev *rtwdev) 778 { 779 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 780 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12]; 781 u32 cnt; 782 783 spin_lock_bh(&rtwpci->trx_lock); 784 rtw89_pci_reclaim_tx_fwcmd(rtwdev, rtwpci); 785 cnt = rtw89_pci_get_avail_txbd_num(tx_ring); 786 spin_unlock_bh(&rtwpci->trx_lock); 787 788 return cnt; 789 } 790 791 static u32 __rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, 792 u8 txch) 793 { 794 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 795 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; 796 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 797 u32 bd_cnt, wd_cnt, min_cnt = 0; 798 struct rtw89_pci_rx_ring *rx_ring; 799 u32 cnt; 800 801 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; 802 803 spin_lock_bh(&rtwpci->trx_lock); 804 bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); 805 wd_cnt = wd_ring->curr_num; 806 807 if (wd_cnt == 0 || bd_cnt == 0) { 808 cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); 809 if (!cnt) 810 goto out_unlock; 811 rtw89_pci_release_tx(rtwdev, rx_ring, cnt); 812 } 813 814 bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); 815 wd_cnt = wd_ring->curr_num; 816 min_cnt = min(bd_cnt, wd_cnt); 817 if (min_cnt == 0) 818 rtw89_warn(rtwdev, "still no tx resource after reclaim\n"); 819 820 out_unlock: 821 spin_unlock_bh(&rtwpci->trx_lock); 822 823 return min_cnt; 824 } 825 826 static u32 rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, 827 u8 txch) 828 { 829 if (txch == RTW89_TXCH_CH12) 830 return __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(rtwdev); 831 832 return __rtw89_pci_check_and_reclaim_tx_resource(rtwdev, txch); 833 } 834 835 static void __rtw89_pci_tx_kick_off(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) 836 { 837 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 838 u32 host_idx, addr; 839 840 addr = bd_ring->addr_idx; 841 host_idx = bd_ring->wp; 842 rtw89_write16(rtwdev, addr, host_idx); 843 } 844 845 static void rtw89_pci_tx_bd_ring_update(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring, 846 int n_txbd) 847 { 848 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 849 u32 host_idx, len; 850 851 len = bd_ring->len; 852 host_idx = bd_ring->wp + n_txbd; 853 host_idx = host_idx < len ? host_idx : host_idx - len; 854 855 bd_ring->wp = host_idx; 856 } 857 858 static void rtw89_pci_ops_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 859 { 860 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 861 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; 862 863 spin_lock_bh(&rtwpci->trx_lock); 864 __rtw89_pci_tx_kick_off(rtwdev, tx_ring); 865 spin_unlock_bh(&rtwpci->trx_lock); 866 } 867 868 static void __pci_flush_txch(struct rtw89_dev *rtwdev, u8 txch, bool drop) 869 { 870 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 871 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; 872 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 873 u32 cur_idx, cur_rp; 874 u8 i; 875 876 /* Because the time taked by the I/O is a bit dynamic, it's hard to 877 * define a reasonable fixed total timeout to use read_poll_timeout* 878 * helper. Instead, we can ensure a reasonable polling times, so we 879 * just use for loop with udelay here. 880 */ 881 for (i = 0; i < 60; i++) { 882 cur_idx = rtw89_read32(rtwdev, bd_ring->addr_idx); 883 cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx); 884 if (cur_rp == bd_ring->wp) 885 return; 886 887 udelay(1); 888 } 889 890 if (!drop) 891 rtw89_info(rtwdev, "timed out to flush pci txch: %d\n", txch); 892 } 893 894 static void __rtw89_pci_ops_flush_txchs(struct rtw89_dev *rtwdev, u32 txchs, 895 bool drop) 896 { 897 u8 i; 898 899 for (i = 0; i < RTW89_TXCH_NUM; i++) { 900 /* It may be unnecessary to flush FWCMD queue. */ 901 if (i == RTW89_TXCH_CH12) 902 continue; 903 904 if (txchs & BIT(i)) 905 __pci_flush_txch(rtwdev, i, drop); 906 } 907 } 908 909 static void rtw89_pci_ops_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 910 bool drop) 911 { 912 __rtw89_pci_ops_flush_txchs(rtwdev, BIT(RTW89_TXCH_NUM) - 1, drop); 913 } 914 915 static int rtw89_pci_txwd_submit(struct rtw89_dev *rtwdev, 916 struct rtw89_pci_tx_ring *tx_ring, 917 struct rtw89_pci_tx_wd *txwd, 918 struct rtw89_core_tx_request *tx_req) 919 { 920 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 921 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 922 struct rtw89_txwd_body *txwd_body; 923 struct rtw89_txwd_info *txwd_info; 924 struct rtw89_pci_tx_wp_info *txwp_info; 925 struct rtw89_pci_tx_addr_info_32 *txaddr_info; 926 struct pci_dev *pdev = rtwpci->pdev; 927 struct sk_buff *skb = tx_req->skb; 928 struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb); 929 bool en_wd_info = desc_info->en_wd_info; 930 u32 txwd_len; 931 u32 txwp_len; 932 u32 txaddr_info_len; 933 dma_addr_t dma; 934 int ret; 935 936 rtw89_core_fill_txdesc(rtwdev, desc_info, txwd->vaddr); 937 938 dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); 939 if (dma_mapping_error(&pdev->dev, dma)) { 940 rtw89_err(rtwdev, "failed to map skb dma data\n"); 941 ret = -EBUSY; 942 goto err; 943 } 944 945 tx_data->dma = dma; 946 947 txaddr_info_len = sizeof(*txaddr_info); 948 txwp_len = sizeof(*txwp_info); 949 txwd_len = sizeof(*txwd_body); 950 txwd_len += en_wd_info ? sizeof(*txwd_info) : 0; 951 952 txwp_info = txwd->vaddr + txwd_len; 953 txwp_info->seq0 = cpu_to_le16(txwd->seq | RTW89_PCI_TXWP_VALID); 954 txwp_info->seq1 = 0; 955 txwp_info->seq2 = 0; 956 txwp_info->seq3 = 0; 957 958 tx_ring->tx_cnt++; 959 txaddr_info = txwd->vaddr + txwd_len + txwp_len; 960 txaddr_info->length = cpu_to_le16(skb->len); 961 txaddr_info->option = cpu_to_le16(RTW89_PCI_ADDR_MSDU_LS | 962 RTW89_PCI_ADDR_NUM(1)); 963 txaddr_info->dma = cpu_to_le32(dma); 964 965 txwd->len = txwd_len + txwp_len + txaddr_info_len; 966 967 skb_queue_tail(&txwd->queue, skb); 968 969 return 0; 970 971 err: 972 return ret; 973 } 974 975 static int rtw89_pci_fwcmd_submit(struct rtw89_dev *rtwdev, 976 struct rtw89_pci_tx_ring *tx_ring, 977 struct rtw89_pci_tx_bd_32 *txbd, 978 struct rtw89_core_tx_request *tx_req) 979 { 980 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 981 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 982 struct rtw89_txwd_body *txwd_body; 983 struct pci_dev *pdev = rtwpci->pdev; 984 struct sk_buff *skb = tx_req->skb; 985 struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb); 986 dma_addr_t dma; 987 988 txwd_body = (struct rtw89_txwd_body *)skb_push(skb, sizeof(*txwd_body)); 989 memset(txwd_body, 0, sizeof(*txwd_body)); 990 rtw89_core_fill_txdesc(rtwdev, desc_info, txwd_body); 991 992 dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); 993 if (dma_mapping_error(&pdev->dev, dma)) { 994 rtw89_err(rtwdev, "failed to map fwcmd dma data\n"); 995 return -EBUSY; 996 } 997 998 tx_data->dma = dma; 999 txbd->option = cpu_to_le16(RTW89_PCI_TXBD_OPTION_LS); 1000 txbd->length = cpu_to_le16(skb->len); 1001 txbd->dma = cpu_to_le32(tx_data->dma); 1002 skb_queue_tail(&rtwpci->h2c_queue, skb); 1003 1004 rtw89_pci_tx_bd_ring_update(rtwdev, tx_ring, 1); 1005 1006 return 0; 1007 } 1008 1009 static int rtw89_pci_txbd_submit(struct rtw89_dev *rtwdev, 1010 struct rtw89_pci_tx_ring *tx_ring, 1011 struct rtw89_pci_tx_bd_32 *txbd, 1012 struct rtw89_core_tx_request *tx_req) 1013 { 1014 struct rtw89_pci_tx_wd *txwd; 1015 int ret; 1016 1017 /* FWCMD queue doesn't have wd pages. Instead, it submits the CMD 1018 * buffer with WD BODY only. So here we don't need to check the free 1019 * pages of the wd ring. 1020 */ 1021 if (tx_ring->txch == RTW89_TXCH_CH12) 1022 return rtw89_pci_fwcmd_submit(rtwdev, tx_ring, txbd, tx_req); 1023 1024 txwd = rtw89_pci_dequeue_txwd(tx_ring); 1025 if (!txwd) { 1026 rtw89_err(rtwdev, "no available TXWD\n"); 1027 ret = -ENOSPC; 1028 goto err; 1029 } 1030 1031 ret = rtw89_pci_txwd_submit(rtwdev, tx_ring, txwd, tx_req); 1032 if (ret) { 1033 rtw89_err(rtwdev, "failed to submit TXWD %d\n", txwd->seq); 1034 goto err_enqueue_wd; 1035 } 1036 1037 list_add_tail(&txwd->list, &tx_ring->busy_pages); 1038 1039 txbd->option = cpu_to_le16(RTW89_PCI_TXBD_OPTION_LS); 1040 txbd->length = cpu_to_le16(txwd->len); 1041 txbd->dma = cpu_to_le32(txwd->paddr); 1042 1043 rtw89_pci_tx_bd_ring_update(rtwdev, tx_ring, 1); 1044 1045 return 0; 1046 1047 err_enqueue_wd: 1048 rtw89_pci_enqueue_txwd(tx_ring, txwd); 1049 err: 1050 return ret; 1051 } 1052 1053 static int rtw89_pci_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req, 1054 u8 txch) 1055 { 1056 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1057 struct rtw89_pci_tx_ring *tx_ring; 1058 struct rtw89_pci_tx_bd_32 *txbd; 1059 u32 n_avail_txbd; 1060 int ret = 0; 1061 1062 /* check the tx type and dma channel for fw cmd queue */ 1063 if ((txch == RTW89_TXCH_CH12 || 1064 tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD) && 1065 (txch != RTW89_TXCH_CH12 || 1066 tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD)) { 1067 rtw89_err(rtwdev, "only fw cmd uses dma channel 12\n"); 1068 return -EINVAL; 1069 } 1070 1071 tx_ring = &rtwpci->tx_rings[txch]; 1072 spin_lock_bh(&rtwpci->trx_lock); 1073 1074 n_avail_txbd = rtw89_pci_get_avail_txbd_num(tx_ring); 1075 if (n_avail_txbd == 0) { 1076 rtw89_err(rtwdev, "no available TXBD\n"); 1077 ret = -ENOSPC; 1078 goto err_unlock; 1079 } 1080 1081 txbd = rtw89_pci_get_next_txbd(tx_ring); 1082 ret = rtw89_pci_txbd_submit(rtwdev, tx_ring, txbd, tx_req); 1083 if (ret) { 1084 rtw89_err(rtwdev, "failed to submit TXBD\n"); 1085 goto err_unlock; 1086 } 1087 1088 spin_unlock_bh(&rtwpci->trx_lock); 1089 return 0; 1090 1091 err_unlock: 1092 spin_unlock_bh(&rtwpci->trx_lock); 1093 return ret; 1094 } 1095 1096 static int rtw89_pci_ops_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req) 1097 { 1098 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1099 int ret; 1100 1101 ret = rtw89_pci_tx_write(rtwdev, tx_req, desc_info->ch_dma); 1102 if (ret) { 1103 rtw89_err(rtwdev, "failed to TX Queue %d\n", desc_info->ch_dma); 1104 return ret; 1105 } 1106 1107 return 0; 1108 } 1109 1110 static const struct rtw89_pci_bd_ram bd_ram_table[RTW89_TXCH_NUM] = { 1111 [RTW89_TXCH_ACH0] = {.start_idx = 0, .max_num = 5, .min_num = 2}, 1112 [RTW89_TXCH_ACH1] = {.start_idx = 5, .max_num = 5, .min_num = 2}, 1113 [RTW89_TXCH_ACH2] = {.start_idx = 10, .max_num = 5, .min_num = 2}, 1114 [RTW89_TXCH_ACH3] = {.start_idx = 15, .max_num = 5, .min_num = 2}, 1115 [RTW89_TXCH_ACH4] = {.start_idx = 20, .max_num = 5, .min_num = 2}, 1116 [RTW89_TXCH_ACH5] = {.start_idx = 25, .max_num = 5, .min_num = 2}, 1117 [RTW89_TXCH_ACH6] = {.start_idx = 30, .max_num = 5, .min_num = 2}, 1118 [RTW89_TXCH_ACH7] = {.start_idx = 35, .max_num = 5, .min_num = 2}, 1119 [RTW89_TXCH_CH8] = {.start_idx = 40, .max_num = 5, .min_num = 1}, 1120 [RTW89_TXCH_CH9] = {.start_idx = 45, .max_num = 5, .min_num = 1}, 1121 [RTW89_TXCH_CH10] = {.start_idx = 50, .max_num = 5, .min_num = 1}, 1122 [RTW89_TXCH_CH11] = {.start_idx = 55, .max_num = 5, .min_num = 1}, 1123 [RTW89_TXCH_CH12] = {.start_idx = 60, .max_num = 4, .min_num = 1}, 1124 }; 1125 1126 static void rtw89_pci_reset_trx_rings(struct rtw89_dev *rtwdev) 1127 { 1128 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1129 struct rtw89_pci_tx_ring *tx_ring; 1130 struct rtw89_pci_rx_ring *rx_ring; 1131 struct rtw89_pci_dma_ring *bd_ring; 1132 const struct rtw89_pci_bd_ram *bd_ram; 1133 u32 addr_num; 1134 u32 addr_bdram; 1135 u32 addr_desa_l; 1136 u32 val32; 1137 int i; 1138 1139 for (i = 0; i < RTW89_TXCH_NUM; i++) { 1140 tx_ring = &rtwpci->tx_rings[i]; 1141 bd_ring = &tx_ring->bd_ring; 1142 bd_ram = &bd_ram_table[i]; 1143 addr_num = bd_ring->addr_num; 1144 addr_bdram = bd_ring->addr_bdram; 1145 addr_desa_l = bd_ring->addr_desa_l; 1146 bd_ring->wp = 0; 1147 bd_ring->rp = 0; 1148 1149 val32 = FIELD_PREP(BDRAM_SIDX_MASK, bd_ram->start_idx) | 1150 FIELD_PREP(BDRAM_MAX_MASK, bd_ram->max_num) | 1151 FIELD_PREP(BDRAM_MIN_MASK, bd_ram->min_num); 1152 1153 rtw89_write16(rtwdev, addr_num, bd_ring->len); 1154 rtw89_write32(rtwdev, addr_bdram, val32); 1155 rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); 1156 } 1157 1158 for (i = 0; i < RTW89_RXCH_NUM; i++) { 1159 rx_ring = &rtwpci->rx_rings[i]; 1160 bd_ring = &rx_ring->bd_ring; 1161 addr_num = bd_ring->addr_num; 1162 addr_desa_l = bd_ring->addr_desa_l; 1163 bd_ring->wp = 0; 1164 bd_ring->rp = 0; 1165 rx_ring->diliver_skb = NULL; 1166 rx_ring->diliver_desc.ready = false; 1167 1168 rtw89_write16(rtwdev, addr_num, bd_ring->len); 1169 rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); 1170 } 1171 } 1172 1173 static void rtw89_pci_release_tx_ring(struct rtw89_dev *rtwdev, 1174 struct rtw89_pci_tx_ring *tx_ring) 1175 { 1176 rtw89_pci_release_busy_txwd(rtwdev, tx_ring); 1177 rtw89_pci_release_pending_txwd_skb(rtwdev, tx_ring); 1178 } 1179 1180 static void rtw89_pci_ops_reset(struct rtw89_dev *rtwdev) 1181 { 1182 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1183 int txch; 1184 1185 rtw89_pci_reset_trx_rings(rtwdev); 1186 1187 spin_lock_bh(&rtwpci->trx_lock); 1188 for (txch = 0; txch < RTW89_TXCH_NUM; txch++) { 1189 if (txch == RTW89_TXCH_CH12) { 1190 rtw89_pci_release_fwcmd(rtwdev, rtwpci, 1191 skb_queue_len(&rtwpci->h2c_queue), true); 1192 continue; 1193 } 1194 rtw89_pci_release_tx_ring(rtwdev, &rtwpci->tx_rings[txch]); 1195 } 1196 spin_unlock_bh(&rtwpci->trx_lock); 1197 } 1198 1199 static int rtw89_pci_ops_start(struct rtw89_dev *rtwdev) 1200 { 1201 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1202 unsigned long flags; 1203 1204 rtw89_core_napi_start(rtwdev); 1205 1206 spin_lock_irqsave(&rtwpci->irq_lock, flags); 1207 rtwpci->running = true; 1208 rtw89_pci_enable_intr(rtwdev, rtwpci); 1209 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 1210 1211 return 0; 1212 } 1213 1214 static void rtw89_pci_ops_stop(struct rtw89_dev *rtwdev) 1215 { 1216 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1217 struct pci_dev *pdev = rtwpci->pdev; 1218 unsigned long flags; 1219 1220 spin_lock_irqsave(&rtwpci->irq_lock, flags); 1221 rtwpci->running = false; 1222 rtw89_pci_disable_intr(rtwdev, rtwpci); 1223 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 1224 1225 synchronize_irq(pdev->irq); 1226 rtw89_core_napi_stop(rtwdev); 1227 } 1228 1229 static void rtw89_pci_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data); 1230 1231 static u32 rtw89_pci_ops_read32_cmac(struct rtw89_dev *rtwdev, u32 addr) 1232 { 1233 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1234 u32 val = readl(rtwpci->mmap + addr); 1235 int count; 1236 1237 for (count = 0; ; count++) { 1238 if (val != RTW89_R32_DEAD) 1239 return val; 1240 if (count >= MAC_REG_POOL_COUNT) { 1241 rtw89_warn(rtwdev, "addr %#x = %#x\n", addr, val); 1242 return RTW89_R32_DEAD; 1243 } 1244 rtw89_pci_ops_write32(rtwdev, R_AX_CK_EN, B_AX_CMAC_ALLCKEN); 1245 val = readl(rtwpci->mmap + addr); 1246 } 1247 1248 return val; 1249 } 1250 1251 static u8 rtw89_pci_ops_read8(struct rtw89_dev *rtwdev, u32 addr) 1252 { 1253 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1254 u32 addr32, val32, shift; 1255 1256 if (!ACCESS_CMAC(addr)) 1257 return readb(rtwpci->mmap + addr); 1258 1259 addr32 = addr & ~0x3; 1260 shift = (addr & 0x3) * 8; 1261 val32 = rtw89_pci_ops_read32_cmac(rtwdev, addr32); 1262 return val32 >> shift; 1263 } 1264 1265 static u16 rtw89_pci_ops_read16(struct rtw89_dev *rtwdev, u32 addr) 1266 { 1267 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1268 u32 addr32, val32, shift; 1269 1270 if (!ACCESS_CMAC(addr)) 1271 return readw(rtwpci->mmap + addr); 1272 1273 addr32 = addr & ~0x3; 1274 shift = (addr & 0x3) * 8; 1275 val32 = rtw89_pci_ops_read32_cmac(rtwdev, addr32); 1276 return val32 >> shift; 1277 } 1278 1279 static u32 rtw89_pci_ops_read32(struct rtw89_dev *rtwdev, u32 addr) 1280 { 1281 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1282 1283 if (!ACCESS_CMAC(addr)) 1284 return readl(rtwpci->mmap + addr); 1285 1286 return rtw89_pci_ops_read32_cmac(rtwdev, addr); 1287 } 1288 1289 static void rtw89_pci_ops_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 1290 { 1291 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1292 1293 writeb(data, rtwpci->mmap + addr); 1294 } 1295 1296 static void rtw89_pci_ops_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 1297 { 1298 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1299 1300 writew(data, rtwpci->mmap + addr); 1301 } 1302 1303 static void rtw89_pci_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 1304 { 1305 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1306 1307 writel(data, rtwpci->mmap + addr); 1308 } 1309 1310 static void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable) 1311 { 1312 if (enable) { 1313 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, 1314 B_AX_TXHCI_EN | B_AX_RXHCI_EN); 1315 rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, 1316 B_AX_STOP_PCIEIO); 1317 } else { 1318 rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP1, 1319 B_AX_STOP_PCIEIO); 1320 rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, 1321 B_AX_TXHCI_EN | B_AX_RXHCI_EN); 1322 } 1323 } 1324 1325 static int rtw89_pci_check_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 rw_bit) 1326 { 1327 u16 val; 1328 1329 rtw89_write8(rtwdev, R_AX_MDIO_CFG, addr & 0x1F); 1330 1331 val = rtw89_read16(rtwdev, R_AX_MDIO_CFG); 1332 switch (speed) { 1333 case PCIE_PHY_GEN1: 1334 if (addr < 0x20) 1335 val = u16_replace_bits(val, MDIO_PG0_G1, B_AX_MDIO_PHY_ADDR_MASK); 1336 else 1337 val = u16_replace_bits(val, MDIO_PG1_G1, B_AX_MDIO_PHY_ADDR_MASK); 1338 break; 1339 case PCIE_PHY_GEN2: 1340 if (addr < 0x20) 1341 val = u16_replace_bits(val, MDIO_PG0_G2, B_AX_MDIO_PHY_ADDR_MASK); 1342 else 1343 val = u16_replace_bits(val, MDIO_PG1_G2, B_AX_MDIO_PHY_ADDR_MASK); 1344 break; 1345 default: 1346 rtw89_err(rtwdev, "[ERR]Error Speed %d!\n", speed); 1347 return -EINVAL; 1348 } 1349 rtw89_write16(rtwdev, R_AX_MDIO_CFG, val); 1350 rtw89_write16_set(rtwdev, R_AX_MDIO_CFG, rw_bit); 1351 1352 return read_poll_timeout(rtw89_read16, val, !(val & rw_bit), 10, 2000, 1353 false, rtwdev, R_AX_MDIO_CFG); 1354 } 1355 1356 static int 1357 rtw89_read16_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 *val) 1358 { 1359 int ret; 1360 1361 ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_RFLAG); 1362 if (ret) { 1363 rtw89_err(rtwdev, "[ERR]MDIO R16 0x%X fail ret=%d!\n", addr, ret); 1364 return ret; 1365 } 1366 *val = rtw89_read16(rtwdev, R_AX_MDIO_RDATA); 1367 1368 return 0; 1369 } 1370 1371 static int 1372 rtw89_write16_mdio(struct rtw89_dev *rtwdev, u8 addr, u16 data, u8 speed) 1373 { 1374 int ret; 1375 1376 rtw89_write16(rtwdev, R_AX_MDIO_WDATA, data); 1377 ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_WFLAG); 1378 if (ret) { 1379 rtw89_err(rtwdev, "[ERR]MDIO W16 0x%X = %x fail ret=%d!\n", addr, data, ret); 1380 return ret; 1381 } 1382 1383 return 0; 1384 } 1385 1386 static int rtw89_write16_mdio_set(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed) 1387 { 1388 int ret; 1389 u16 val; 1390 1391 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); 1392 if (ret) 1393 return ret; 1394 ret = rtw89_write16_mdio(rtwdev, addr, val | mask, speed); 1395 if (ret) 1396 return ret; 1397 1398 return 0; 1399 } 1400 1401 static int rtw89_write16_mdio_clr(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed) 1402 { 1403 int ret; 1404 u16 val; 1405 1406 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); 1407 if (ret) 1408 return ret; 1409 ret = rtw89_write16_mdio(rtwdev, addr, val & ~mask, speed); 1410 if (ret) 1411 return ret; 1412 1413 return 0; 1414 } 1415 1416 static int rtw89_pci_write_config_byte(struct rtw89_dev *rtwdev, u16 addr, 1417 u8 data) 1418 { 1419 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1420 struct pci_dev *pdev = rtwpci->pdev; 1421 1422 return pci_write_config_byte(pdev, addr, data); 1423 } 1424 1425 static int rtw89_pci_read_config_byte(struct rtw89_dev *rtwdev, u16 addr, 1426 u8 *value) 1427 { 1428 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1429 struct pci_dev *pdev = rtwpci->pdev; 1430 1431 return pci_read_config_byte(pdev, addr, value); 1432 } 1433 1434 static int rtw89_pci_config_byte_set(struct rtw89_dev *rtwdev, u16 addr, 1435 u8 bit) 1436 { 1437 u8 value; 1438 int ret; 1439 1440 ret = rtw89_pci_read_config_byte(rtwdev, addr, &value); 1441 if (ret) 1442 return ret; 1443 1444 value |= bit; 1445 ret = rtw89_pci_write_config_byte(rtwdev, addr, value); 1446 1447 return ret; 1448 } 1449 1450 static int rtw89_pci_config_byte_clr(struct rtw89_dev *rtwdev, u16 addr, 1451 u8 bit) 1452 { 1453 u8 value; 1454 int ret; 1455 1456 ret = rtw89_pci_read_config_byte(rtwdev, addr, &value); 1457 if (ret) 1458 return ret; 1459 1460 value &= ~bit; 1461 ret = rtw89_pci_write_config_byte(rtwdev, addr, value); 1462 1463 return ret; 1464 } 1465 1466 static int 1467 __get_target(struct rtw89_dev *rtwdev, u16 *target, enum rtw89_pcie_phy phy_rate) 1468 { 1469 u16 val, tar; 1470 int ret; 1471 1472 /* Enable counter */ 1473 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val); 1474 if (ret) 1475 return ret; 1476 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN, 1477 phy_rate); 1478 if (ret) 1479 return ret; 1480 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val | B_AX_CLK_CALIB_EN, 1481 phy_rate); 1482 if (ret) 1483 return ret; 1484 1485 fsleep(300); 1486 1487 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &tar); 1488 if (ret) 1489 return ret; 1490 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN, 1491 phy_rate); 1492 if (ret) 1493 return ret; 1494 1495 tar = tar & 0x0FFF; 1496 if (tar == 0 || tar == 0x0FFF) { 1497 rtw89_err(rtwdev, "[ERR]Get target failed.\n"); 1498 return -EINVAL; 1499 } 1500 1501 *target = tar; 1502 1503 return 0; 1504 } 1505 1506 static int rtw89_pci_auto_refclk_cal(struct rtw89_dev *rtwdev, bool autook_en) 1507 { 1508 enum rtw89_pcie_phy phy_rate; 1509 u16 val16, mgn_set, div_set, tar; 1510 u8 val8, bdr_ori; 1511 bool l1_flag = false; 1512 int ret = 0; 1513 1514 if ((rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) || 1515 rtwdev->chip->chip_id == RTL8852C) 1516 return 0; 1517 1518 ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_PHY_RATE, &val8); 1519 if (ret) { 1520 rtw89_err(rtwdev, "[ERR]pci config read %X\n", 1521 RTW89_PCIE_PHY_RATE); 1522 return ret; 1523 } 1524 1525 if (FIELD_GET(RTW89_PCIE_PHY_RATE_MASK, val8) == 0x1) { 1526 phy_rate = PCIE_PHY_GEN1; 1527 } else if (FIELD_GET(RTW89_PCIE_PHY_RATE_MASK, val8) == 0x2) { 1528 phy_rate = PCIE_PHY_GEN2; 1529 } else { 1530 rtw89_err(rtwdev, "[ERR]PCIe PHY rate %#x not support\n", val8); 1531 return -EOPNOTSUPP; 1532 } 1533 /* Disable L1BD */ 1534 ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, &bdr_ori); 1535 if (ret) { 1536 rtw89_err(rtwdev, "[ERR]pci config read %X\n", RTW89_PCIE_L1_CTRL); 1537 return ret; 1538 } 1539 1540 if (bdr_ori & RTW89_PCIE_BIT_L1) { 1541 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, 1542 bdr_ori & ~RTW89_PCIE_BIT_L1); 1543 if (ret) { 1544 rtw89_err(rtwdev, "[ERR]pci config write %X\n", 1545 RTW89_PCIE_L1_CTRL); 1546 return ret; 1547 } 1548 l1_flag = true; 1549 } 1550 1551 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16); 1552 if (ret) { 1553 rtw89_err(rtwdev, "[ERR]mdio_r16_pcie %X\n", RAC_CTRL_PPR_V1); 1554 goto end; 1555 } 1556 1557 if (val16 & B_AX_CALIB_EN) { 1558 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, 1559 val16 & ~B_AX_CALIB_EN, phy_rate); 1560 if (ret) { 1561 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); 1562 goto end; 1563 } 1564 } 1565 1566 if (!autook_en) 1567 goto end; 1568 /* Set div */ 1569 ret = rtw89_write16_mdio_clr(rtwdev, RAC_CTRL_PPR_V1, B_AX_DIV, phy_rate); 1570 if (ret) { 1571 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); 1572 goto end; 1573 } 1574 1575 /* Obtain div and margin */ 1576 ret = __get_target(rtwdev, &tar, phy_rate); 1577 if (ret) { 1578 rtw89_err(rtwdev, "[ERR]1st get target fail %d\n", ret); 1579 goto end; 1580 } 1581 1582 mgn_set = tar * INTF_INTGRA_HOSTREF_V1 / INTF_INTGRA_MINREF_V1 - tar; 1583 1584 if (mgn_set >= 128) { 1585 div_set = 0x0003; 1586 mgn_set = 0x000F; 1587 } else if (mgn_set >= 64) { 1588 div_set = 0x0003; 1589 mgn_set >>= 3; 1590 } else if (mgn_set >= 32) { 1591 div_set = 0x0002; 1592 mgn_set >>= 2; 1593 } else if (mgn_set >= 16) { 1594 div_set = 0x0001; 1595 mgn_set >>= 1; 1596 } else if (mgn_set == 0) { 1597 rtw89_err(rtwdev, "[ERR]cal mgn is 0,tar = %d\n", tar); 1598 goto end; 1599 } else { 1600 div_set = 0x0000; 1601 } 1602 1603 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16); 1604 if (ret) { 1605 rtw89_err(rtwdev, "[ERR]mdio_r16_pcie %X\n", RAC_CTRL_PPR_V1); 1606 goto end; 1607 } 1608 1609 val16 |= u16_encode_bits(div_set, B_AX_DIV); 1610 1611 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val16, phy_rate); 1612 if (ret) { 1613 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); 1614 goto end; 1615 } 1616 1617 ret = __get_target(rtwdev, &tar, phy_rate); 1618 if (ret) { 1619 rtw89_err(rtwdev, "[ERR]2nd get target fail %d\n", ret); 1620 goto end; 1621 } 1622 1623 rtw89_debug(rtwdev, RTW89_DBG_HCI, "[TRACE]target = 0x%X, div = 0x%X, margin = 0x%X\n", 1624 tar, div_set, mgn_set); 1625 ret = rtw89_write16_mdio(rtwdev, RAC_SET_PPR_V1, 1626 (tar & 0x0FFF) | (mgn_set << 12), phy_rate); 1627 if (ret) { 1628 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_SET_PPR_V1); 1629 goto end; 1630 } 1631 1632 /* Enable function */ 1633 ret = rtw89_write16_mdio_set(rtwdev, RAC_CTRL_PPR_V1, B_AX_CALIB_EN, phy_rate); 1634 if (ret) { 1635 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); 1636 goto end; 1637 } 1638 1639 /* CLK delay = 0 */ 1640 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_CLK_CTRL, 1641 PCIE_CLKDLY_HW_0); 1642 1643 end: 1644 /* Set L1BD to ori */ 1645 if (l1_flag) { 1646 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, 1647 bdr_ori); 1648 if (ret) { 1649 rtw89_err(rtwdev, "[ERR]pci config write %X\n", 1650 RTW89_PCIE_L1_CTRL); 1651 return ret; 1652 } 1653 } 1654 1655 return ret; 1656 } 1657 1658 static int rtw89_pci_deglitch_setting(struct rtw89_dev *rtwdev) 1659 { 1660 int ret; 1661 1662 if (rtwdev->chip->chip_id != RTL8852A) 1663 return 0; 1664 1665 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH, 1666 PCIE_PHY_GEN1); 1667 if (ret) 1668 return ret; 1669 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH, 1670 PCIE_PHY_GEN2); 1671 if (ret) 1672 return ret; 1673 1674 return 0; 1675 } 1676 1677 static void rtw89_pci_rxdma_prefth(struct rtw89_dev *rtwdev) 1678 { 1679 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_DIS_RXDMA_PRE); 1680 } 1681 1682 static void rtw89_pci_l1off_pwroff(struct rtw89_dev *rtwdev) 1683 { 1684 if (rtwdev->chip->chip_id == RTL8852C) 1685 return; 1686 1687 rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL, B_AX_L1OFF_PWR_OFF_EN); 1688 } 1689 1690 static u32 rtw89_pci_l2_rxen_lat(struct rtw89_dev *rtwdev) 1691 { 1692 int ret; 1693 1694 if (rtwdev->chip->chip_id == RTL8852C) 1695 return 0; 1696 1697 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN, 1698 PCIE_PHY_GEN1); 1699 if (ret) 1700 return ret; 1701 1702 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN, 1703 PCIE_PHY_GEN2); 1704 if (ret) 1705 return ret; 1706 1707 return 0; 1708 } 1709 1710 static void rtw89_pci_aphy_pwrcut(struct rtw89_dev *rtwdev) 1711 { 1712 if (rtwdev->chip->chip_id != RTL8852A) 1713 return; 1714 1715 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_PSUS_OFF_CAPC_EN); 1716 } 1717 1718 static void rtw89_pci_hci_ldo(struct rtw89_dev *rtwdev) 1719 { 1720 if (rtwdev->chip->chip_id != RTL8852A) 1721 return; 1722 1723 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, 1724 B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); 1725 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, 1726 B_AX_PCIE_DIS_WLSUS_AFT_PDN); 1727 } 1728 1729 static void rtw89_pci_set_sic(struct rtw89_dev *rtwdev) 1730 { 1731 if (rtwdev->chip->chip_id == RTL8852C) 1732 return; 1733 1734 rtw89_write32_clr(rtwdev, R_AX_PCIE_EXP_CTRL, 1735 B_AX_SIC_EN_FORCE_CLKREQ); 1736 } 1737 1738 static void rtw89_pci_set_dbg(struct rtw89_dev *rtwdev) 1739 { 1740 if (rtwdev->chip->chip_id == RTL8852C) 1741 return; 1742 1743 rtw89_write32_set(rtwdev, R_AX_PCIE_DBG_CTRL, 1744 B_AX_ASFF_FULL_NO_STK | B_AX_EN_STUCK_DBG); 1745 1746 if (rtwdev->chip->chip_id == RTL8852A) 1747 rtw89_write32_set(rtwdev, R_AX_PCIE_EXP_CTRL, 1748 B_AX_EN_CHKDSC_NO_RX_STUCK); 1749 } 1750 1751 static void rtw89_pci_clr_idx_all(struct rtw89_dev *rtwdev) 1752 { 1753 u32 val = B_AX_CLR_ACH0_IDX | B_AX_CLR_ACH1_IDX | B_AX_CLR_ACH2_IDX | 1754 B_AX_CLR_ACH3_IDX | B_AX_CLR_CH8_IDX | B_AX_CLR_CH9_IDX | 1755 B_AX_CLR_CH12_IDX; 1756 1757 if (rtwdev->chip->chip_id == RTL8852A) 1758 val |= B_AX_CLR_ACH4_IDX | B_AX_CLR_ACH5_IDX | 1759 B_AX_CLR_ACH6_IDX | B_AX_CLR_ACH7_IDX; 1760 /* clear DMA indexes */ 1761 rtw89_write32_set(rtwdev, R_AX_TXBD_RWPTR_CLR1, val); 1762 if (rtwdev->chip->chip_id == RTL8852A) 1763 rtw89_write32_set(rtwdev, R_AX_TXBD_RWPTR_CLR2, 1764 B_AX_CLR_CH10_IDX | B_AX_CLR_CH11_IDX); 1765 rtw89_write32_set(rtwdev, R_AX_RXBD_RWPTR_CLR, 1766 B_AX_CLR_RXQ_IDX | B_AX_CLR_RPQ_IDX); 1767 } 1768 1769 static int rtw89_pci_ops_deinit(struct rtw89_dev *rtwdev) 1770 { 1771 if (rtwdev->chip->chip_id == RTL8852A) { 1772 /* ltr sw trigger */ 1773 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_IDLE); 1774 } 1775 rtw89_pci_ctrl_dma_all(rtwdev, false); 1776 rtw89_pci_clr_idx_all(rtwdev); 1777 1778 return 0; 1779 } 1780 1781 static int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev) 1782 { 1783 u32 dma_busy; 1784 u32 check; 1785 u32 lbc; 1786 int ret; 1787 1788 rtw89_pci_rxdma_prefth(rtwdev); 1789 rtw89_pci_l1off_pwroff(rtwdev); 1790 rtw89_pci_deglitch_setting(rtwdev); 1791 ret = rtw89_pci_l2_rxen_lat(rtwdev); 1792 if (ret) { 1793 rtw89_err(rtwdev, "[ERR] pcie l2 rxen lat %d\n", ret); 1794 return ret; 1795 } 1796 1797 rtw89_pci_aphy_pwrcut(rtwdev); 1798 rtw89_pci_hci_ldo(rtwdev); 1799 1800 ret = rtw89_pci_auto_refclk_cal(rtwdev, false); 1801 if (ret) { 1802 rtw89_err(rtwdev, "[ERR] pcie autok fail %d\n", ret); 1803 return ret; 1804 } 1805 1806 rtw89_pci_set_sic(rtwdev); 1807 rtw89_pci_set_dbg(rtwdev); 1808 1809 if (rtwdev->chip->chip_id == RTL8852A) 1810 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, 1811 B_AX_PCIE_AUXCLK_GATE); 1812 1813 lbc = rtw89_read32(rtwdev, R_AX_LBC_WATCHDOG); 1814 lbc = u32_replace_bits(lbc, RTW89_MAC_LBC_TMR_128US, B_AX_LBC_TIMER); 1815 lbc |= B_AX_LBC_FLAG | B_AX_LBC_EN; 1816 rtw89_write32(rtwdev, R_AX_LBC_WATCHDOG, lbc); 1817 1818 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, 1819 B_AX_PCIE_TXRST_KEEP_REG | B_AX_PCIE_RXRST_KEEP_REG); 1820 rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP1, B_AX_STOP_WPDMA); 1821 1822 /* stop DMA activities */ 1823 rtw89_pci_ctrl_dma_all(rtwdev, false); 1824 1825 /* check PCI at idle state */ 1826 check = B_AX_PCIEIO_BUSY | B_AX_PCIEIO_TX_BUSY | B_AX_PCIEIO_RX_BUSY; 1827 ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0, 1828 100, 3000, false, rtwdev, R_AX_PCIE_DMA_BUSY1); 1829 if (ret) { 1830 rtw89_err(rtwdev, "failed to poll io busy\n"); 1831 return ret; 1832 } 1833 1834 rtw89_pci_clr_idx_all(rtwdev); 1835 1836 /* configure TX/RX op modes */ 1837 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE | 1838 B_AX_RX_TRUNC_MODE); 1839 rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RXBD_MODE); 1840 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_TXDMA_MASK, 7); 1841 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_RXDMA_MASK, 3); 1842 /* multi-tag mode */ 1843 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_LATENCY_CONTROL); 1844 rtw89_write32_mask(rtwdev, R_AX_PCIE_EXP_CTRL, B_AX_MAX_TAG_NUM, 1845 RTW89_MAC_TAG_NUM_8); 1846 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_IDLE, 1847 RTW89_MAC_WD_DMA_INTVL_256NS); 1848 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_ACT, 1849 RTW89_MAC_WD_DMA_INTVL_256NS); 1850 1851 /* fill TRX BD indexes */ 1852 rtw89_pci_ops_reset(rtwdev); 1853 1854 ret = rtw89_pci_rst_bdram_pcie(rtwdev); 1855 if (ret) { 1856 rtw89_warn(rtwdev, "reset bdram busy\n"); 1857 return ret; 1858 } 1859 1860 /* enable FW CMD queue to download firmware */ 1861 rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_ALL); 1862 rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, B_AX_STOP_CH12); 1863 rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP2, B_AX_TX_STOP2_ALL); 1864 1865 /* start DMA activities */ 1866 rtw89_pci_ctrl_dma_all(rtwdev, true); 1867 1868 return 0; 1869 } 1870 1871 static int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev) 1872 { 1873 u32 val; 1874 1875 val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0); 1876 if (rtw89_pci_ltr_is_err_reg_val(val)) 1877 return -EINVAL; 1878 val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_1); 1879 if (rtw89_pci_ltr_is_err_reg_val(val)) 1880 return -EINVAL; 1881 val = rtw89_read32(rtwdev, R_AX_LTR_IDLE_LATENCY); 1882 if (rtw89_pci_ltr_is_err_reg_val(val)) 1883 return -EINVAL; 1884 val = rtw89_read32(rtwdev, R_AX_LTR_ACTIVE_LATENCY); 1885 if (rtw89_pci_ltr_is_err_reg_val(val)) 1886 return -EINVAL; 1887 1888 rtw89_write32_clr(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_HW_EN); 1889 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_EN); 1890 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_SPACE_IDX_MASK, 1891 PCI_LTR_SPC_500US); 1892 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK, 1893 PCI_LTR_IDLE_TIMER_800US); 1894 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28); 1895 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX1_TH_MASK, 0x28); 1896 rtw89_write32(rtwdev, R_AX_LTR_IDLE_LATENCY, 0x88e088e0); 1897 rtw89_write32(rtwdev, R_AX_LTR_ACTIVE_LATENCY, 0x880b880b); 1898 1899 return 0; 1900 } 1901 1902 static int rtw89_pci_ops_mac_post_init(struct rtw89_dev *rtwdev) 1903 { 1904 int ret; 1905 1906 ret = rtw89_pci_ltr_set(rtwdev); 1907 if (ret) { 1908 rtw89_err(rtwdev, "pci ltr set fail\n"); 1909 return ret; 1910 } 1911 if (rtwdev->chip->chip_id == RTL8852A) { 1912 /* ltr sw trigger */ 1913 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_ACT); 1914 } 1915 /* ADDR info 8-byte mode */ 1916 rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, 1917 B_AX_HOST_ADDR_INFO_8B_SEL); 1918 rtw89_write32_clr(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); 1919 1920 /* enable DMA for all queues */ 1921 rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_ALL); 1922 rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP2, B_AX_TX_STOP2_ALL); 1923 1924 /* Release PCI IO */ 1925 rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, 1926 B_AX_STOP_WPDMA | B_AX_STOP_PCIEIO); 1927 1928 return 0; 1929 } 1930 1931 static int rtw89_pci_claim_device(struct rtw89_dev *rtwdev, 1932 struct pci_dev *pdev) 1933 { 1934 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1935 int ret; 1936 1937 ret = pci_enable_device(pdev); 1938 if (ret) { 1939 rtw89_err(rtwdev, "failed to enable pci device\n"); 1940 return ret; 1941 } 1942 1943 pci_set_master(pdev); 1944 pci_set_drvdata(pdev, rtwdev->hw); 1945 1946 rtwpci->pdev = pdev; 1947 1948 return 0; 1949 } 1950 1951 static void rtw89_pci_declaim_device(struct rtw89_dev *rtwdev, 1952 struct pci_dev *pdev) 1953 { 1954 pci_clear_master(pdev); 1955 pci_disable_device(pdev); 1956 } 1957 1958 static int rtw89_pci_setup_mapping(struct rtw89_dev *rtwdev, 1959 struct pci_dev *pdev) 1960 { 1961 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1962 unsigned long resource_len; 1963 u8 bar_id = 2; 1964 int ret; 1965 1966 ret = pci_request_regions(pdev, KBUILD_MODNAME); 1967 if (ret) { 1968 rtw89_err(rtwdev, "failed to request pci regions\n"); 1969 goto err; 1970 } 1971 1972 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1973 if (ret) { 1974 rtw89_err(rtwdev, "failed to set dma mask to 32-bit\n"); 1975 goto err_release_regions; 1976 } 1977 1978 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 1979 if (ret) { 1980 rtw89_err(rtwdev, "failed to set consistent dma mask to 32-bit\n"); 1981 goto err_release_regions; 1982 } 1983 1984 resource_len = pci_resource_len(pdev, bar_id); 1985 rtwpci->mmap = pci_iomap(pdev, bar_id, resource_len); 1986 if (!rtwpci->mmap) { 1987 rtw89_err(rtwdev, "failed to map pci io\n"); 1988 ret = -EIO; 1989 goto err_release_regions; 1990 } 1991 1992 return 0; 1993 1994 err_release_regions: 1995 pci_release_regions(pdev); 1996 err: 1997 return ret; 1998 } 1999 2000 static void rtw89_pci_clear_mapping(struct rtw89_dev *rtwdev, 2001 struct pci_dev *pdev) 2002 { 2003 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2004 2005 if (rtwpci->mmap) { 2006 pci_iounmap(pdev, rtwpci->mmap); 2007 pci_release_regions(pdev); 2008 } 2009 } 2010 2011 static void rtw89_pci_free_tx_wd_ring(struct rtw89_dev *rtwdev, 2012 struct pci_dev *pdev, 2013 struct rtw89_pci_tx_ring *tx_ring) 2014 { 2015 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 2016 u8 *head = wd_ring->head; 2017 dma_addr_t dma = wd_ring->dma; 2018 u32 page_size = wd_ring->page_size; 2019 u32 page_num = wd_ring->page_num; 2020 u32 ring_sz = page_size * page_num; 2021 2022 dma_free_coherent(&pdev->dev, ring_sz, head, dma); 2023 wd_ring->head = NULL; 2024 } 2025 2026 static void rtw89_pci_free_tx_ring(struct rtw89_dev *rtwdev, 2027 struct pci_dev *pdev, 2028 struct rtw89_pci_tx_ring *tx_ring) 2029 { 2030 int ring_sz; 2031 u8 *head; 2032 dma_addr_t dma; 2033 2034 head = tx_ring->bd_ring.head; 2035 dma = tx_ring->bd_ring.dma; 2036 ring_sz = tx_ring->bd_ring.desc_size * tx_ring->bd_ring.len; 2037 dma_free_coherent(&pdev->dev, ring_sz, head, dma); 2038 2039 tx_ring->bd_ring.head = NULL; 2040 } 2041 2042 static void rtw89_pci_free_tx_rings(struct rtw89_dev *rtwdev, 2043 struct pci_dev *pdev) 2044 { 2045 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2046 struct rtw89_pci_tx_ring *tx_ring; 2047 int i; 2048 2049 for (i = 0; i < RTW89_TXCH_NUM; i++) { 2050 tx_ring = &rtwpci->tx_rings[i]; 2051 rtw89_pci_free_tx_wd_ring(rtwdev, pdev, tx_ring); 2052 rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); 2053 } 2054 } 2055 2056 static void rtw89_pci_free_rx_ring(struct rtw89_dev *rtwdev, 2057 struct pci_dev *pdev, 2058 struct rtw89_pci_rx_ring *rx_ring) 2059 { 2060 struct rtw89_pci_rx_info *rx_info; 2061 struct sk_buff *skb; 2062 dma_addr_t dma; 2063 u32 buf_sz; 2064 u8 *head; 2065 int ring_sz = rx_ring->bd_ring.desc_size * rx_ring->bd_ring.len; 2066 int i; 2067 2068 buf_sz = rx_ring->buf_sz; 2069 for (i = 0; i < rx_ring->bd_ring.len; i++) { 2070 skb = rx_ring->buf[i]; 2071 if (!skb) 2072 continue; 2073 2074 rx_info = RTW89_PCI_RX_SKB_CB(skb); 2075 dma = rx_info->dma; 2076 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 2077 dev_kfree_skb(skb); 2078 rx_ring->buf[i] = NULL; 2079 } 2080 2081 head = rx_ring->bd_ring.head; 2082 dma = rx_ring->bd_ring.dma; 2083 dma_free_coherent(&pdev->dev, ring_sz, head, dma); 2084 2085 rx_ring->bd_ring.head = NULL; 2086 } 2087 2088 static void rtw89_pci_free_rx_rings(struct rtw89_dev *rtwdev, 2089 struct pci_dev *pdev) 2090 { 2091 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2092 struct rtw89_pci_rx_ring *rx_ring; 2093 int i; 2094 2095 for (i = 0; i < RTW89_RXCH_NUM; i++) { 2096 rx_ring = &rtwpci->rx_rings[i]; 2097 rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); 2098 } 2099 } 2100 2101 static void rtw89_pci_free_trx_rings(struct rtw89_dev *rtwdev, 2102 struct pci_dev *pdev) 2103 { 2104 rtw89_pci_free_rx_rings(rtwdev, pdev); 2105 rtw89_pci_free_tx_rings(rtwdev, pdev); 2106 } 2107 2108 static int rtw89_pci_init_rx_bd(struct rtw89_dev *rtwdev, struct pci_dev *pdev, 2109 struct rtw89_pci_rx_ring *rx_ring, 2110 struct sk_buff *skb, int buf_sz, u32 idx) 2111 { 2112 struct rtw89_pci_rx_info *rx_info; 2113 struct rtw89_pci_rx_bd_32 *rx_bd; 2114 dma_addr_t dma; 2115 2116 if (!skb) 2117 return -EINVAL; 2118 2119 dma = dma_map_single(&pdev->dev, skb->data, buf_sz, DMA_FROM_DEVICE); 2120 if (dma_mapping_error(&pdev->dev, dma)) 2121 return -EBUSY; 2122 2123 rx_info = RTW89_PCI_RX_SKB_CB(skb); 2124 rx_bd = RTW89_PCI_RX_BD(rx_ring, idx); 2125 2126 memset(rx_bd, 0, sizeof(*rx_bd)); 2127 rx_bd->buf_size = cpu_to_le16(buf_sz); 2128 rx_bd->dma = cpu_to_le32(dma); 2129 rx_info->dma = dma; 2130 2131 return 0; 2132 } 2133 2134 static int rtw89_pci_alloc_tx_wd_ring(struct rtw89_dev *rtwdev, 2135 struct pci_dev *pdev, 2136 struct rtw89_pci_tx_ring *tx_ring, 2137 enum rtw89_tx_channel txch) 2138 { 2139 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 2140 struct rtw89_pci_tx_wd *txwd; 2141 dma_addr_t dma; 2142 dma_addr_t cur_paddr; 2143 u8 *head; 2144 u8 *cur_vaddr; 2145 u32 page_size = RTW89_PCI_TXWD_PAGE_SIZE; 2146 u32 page_num = RTW89_PCI_TXWD_NUM_MAX; 2147 u32 ring_sz = page_size * page_num; 2148 u32 page_offset; 2149 int i; 2150 2151 /* FWCMD queue doesn't use txwd as pages */ 2152 if (txch == RTW89_TXCH_CH12) 2153 return 0; 2154 2155 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 2156 if (!head) 2157 return -ENOMEM; 2158 2159 INIT_LIST_HEAD(&wd_ring->free_pages); 2160 wd_ring->head = head; 2161 wd_ring->dma = dma; 2162 wd_ring->page_size = page_size; 2163 wd_ring->page_num = page_num; 2164 2165 page_offset = 0; 2166 for (i = 0; i < page_num; i++) { 2167 txwd = &wd_ring->pages[i]; 2168 cur_paddr = dma + page_offset; 2169 cur_vaddr = head + page_offset; 2170 2171 skb_queue_head_init(&txwd->queue); 2172 INIT_LIST_HEAD(&txwd->list); 2173 txwd->paddr = cur_paddr; 2174 txwd->vaddr = cur_vaddr; 2175 txwd->len = page_size; 2176 txwd->seq = i; 2177 rtw89_pci_enqueue_txwd(tx_ring, txwd); 2178 2179 page_offset += page_size; 2180 } 2181 2182 return 0; 2183 } 2184 2185 static int rtw89_pci_alloc_tx_ring(struct rtw89_dev *rtwdev, 2186 struct pci_dev *pdev, 2187 struct rtw89_pci_tx_ring *tx_ring, 2188 u32 desc_size, u32 len, 2189 enum rtw89_tx_channel txch) 2190 { 2191 int ring_sz = desc_size * len; 2192 u8 *head; 2193 dma_addr_t dma; 2194 u32 addr_num; 2195 u32 addr_idx; 2196 u32 addr_bdram; 2197 u32 addr_desa_l; 2198 u32 addr_desa_h; 2199 int ret; 2200 2201 ret = rtw89_pci_alloc_tx_wd_ring(rtwdev, pdev, tx_ring, txch); 2202 if (ret) { 2203 rtw89_err(rtwdev, "failed to alloc txwd ring of txch %d\n", txch); 2204 goto err; 2205 } 2206 2207 ret = rtw89_pci_get_txch_addrs(txch, &addr_num, &addr_idx, &addr_bdram, 2208 &addr_desa_l, &addr_desa_h); 2209 if (ret) { 2210 rtw89_err(rtwdev, "failed to get address of txch %d", txch); 2211 goto err_free_wd_ring; 2212 } 2213 2214 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 2215 if (!head) { 2216 ret = -ENOMEM; 2217 goto err_free_wd_ring; 2218 } 2219 2220 INIT_LIST_HEAD(&tx_ring->busy_pages); 2221 tx_ring->bd_ring.head = head; 2222 tx_ring->bd_ring.dma = dma; 2223 tx_ring->bd_ring.len = len; 2224 tx_ring->bd_ring.desc_size = desc_size; 2225 tx_ring->bd_ring.addr_num = addr_num; 2226 tx_ring->bd_ring.addr_idx = addr_idx; 2227 tx_ring->bd_ring.addr_bdram = addr_bdram; 2228 tx_ring->bd_ring.addr_desa_l = addr_desa_l; 2229 tx_ring->bd_ring.addr_desa_h = addr_desa_h; 2230 tx_ring->bd_ring.wp = 0; 2231 tx_ring->bd_ring.rp = 0; 2232 tx_ring->txch = txch; 2233 2234 return 0; 2235 2236 err_free_wd_ring: 2237 rtw89_pci_free_tx_wd_ring(rtwdev, pdev, tx_ring); 2238 err: 2239 return ret; 2240 } 2241 2242 static int rtw89_pci_alloc_tx_rings(struct rtw89_dev *rtwdev, 2243 struct pci_dev *pdev) 2244 { 2245 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2246 struct rtw89_pci_tx_ring *tx_ring; 2247 u32 desc_size; 2248 u32 len; 2249 u32 i, tx_allocated; 2250 int ret; 2251 2252 for (i = 0; i < RTW89_TXCH_NUM; i++) { 2253 tx_ring = &rtwpci->tx_rings[i]; 2254 desc_size = sizeof(struct rtw89_pci_tx_bd_32); 2255 len = RTW89_PCI_TXBD_NUM_MAX; 2256 ret = rtw89_pci_alloc_tx_ring(rtwdev, pdev, tx_ring, 2257 desc_size, len, i); 2258 if (ret) { 2259 rtw89_err(rtwdev, "failed to alloc tx ring %d\n", i); 2260 goto err_free; 2261 } 2262 } 2263 2264 return 0; 2265 2266 err_free: 2267 tx_allocated = i; 2268 for (i = 0; i < tx_allocated; i++) { 2269 tx_ring = &rtwpci->tx_rings[i]; 2270 rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); 2271 } 2272 2273 return ret; 2274 } 2275 2276 static int rtw89_pci_alloc_rx_ring(struct rtw89_dev *rtwdev, 2277 struct pci_dev *pdev, 2278 struct rtw89_pci_rx_ring *rx_ring, 2279 u32 desc_size, u32 len, u32 rxch) 2280 { 2281 struct sk_buff *skb; 2282 u8 *head; 2283 dma_addr_t dma; 2284 u32 addr_num; 2285 u32 addr_idx; 2286 u32 addr_desa_l; 2287 u32 addr_desa_h; 2288 int ring_sz = desc_size * len; 2289 int buf_sz = RTW89_PCI_RX_BUF_SIZE; 2290 int i, allocated; 2291 int ret; 2292 2293 ret = rtw89_pci_get_rxch_addrs(rxch, &addr_num, &addr_idx, 2294 &addr_desa_l, &addr_desa_h); 2295 if (ret) { 2296 rtw89_err(rtwdev, "failed to get address of rxch %d", rxch); 2297 return ret; 2298 } 2299 2300 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 2301 if (!head) { 2302 ret = -ENOMEM; 2303 goto err; 2304 } 2305 2306 rx_ring->bd_ring.head = head; 2307 rx_ring->bd_ring.dma = dma; 2308 rx_ring->bd_ring.len = len; 2309 rx_ring->bd_ring.desc_size = desc_size; 2310 rx_ring->bd_ring.addr_num = addr_num; 2311 rx_ring->bd_ring.addr_idx = addr_idx; 2312 rx_ring->bd_ring.addr_desa_l = addr_desa_l; 2313 rx_ring->bd_ring.addr_desa_h = addr_desa_h; 2314 rx_ring->bd_ring.wp = 0; 2315 rx_ring->bd_ring.rp = 0; 2316 rx_ring->buf_sz = buf_sz; 2317 rx_ring->diliver_skb = NULL; 2318 rx_ring->diliver_desc.ready = false; 2319 2320 for (i = 0; i < len; i++) { 2321 skb = dev_alloc_skb(buf_sz); 2322 if (!skb) { 2323 ret = -ENOMEM; 2324 goto err_free; 2325 } 2326 2327 memset(skb->data, 0, buf_sz); 2328 rx_ring->buf[i] = skb; 2329 ret = rtw89_pci_init_rx_bd(rtwdev, pdev, rx_ring, skb, 2330 buf_sz, i); 2331 if (ret) { 2332 rtw89_err(rtwdev, "failed to init rx buf %d\n", i); 2333 dev_kfree_skb_any(skb); 2334 rx_ring->buf[i] = NULL; 2335 goto err_free; 2336 } 2337 } 2338 2339 return 0; 2340 2341 err_free: 2342 allocated = i; 2343 for (i = 0; i < allocated; i++) { 2344 skb = rx_ring->buf[i]; 2345 if (!skb) 2346 continue; 2347 dma = *((dma_addr_t *)skb->cb); 2348 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 2349 dev_kfree_skb(skb); 2350 rx_ring->buf[i] = NULL; 2351 } 2352 2353 head = rx_ring->bd_ring.head; 2354 dma = rx_ring->bd_ring.dma; 2355 dma_free_coherent(&pdev->dev, ring_sz, head, dma); 2356 2357 rx_ring->bd_ring.head = NULL; 2358 err: 2359 return ret; 2360 } 2361 2362 static int rtw89_pci_alloc_rx_rings(struct rtw89_dev *rtwdev, 2363 struct pci_dev *pdev) 2364 { 2365 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2366 struct rtw89_pci_rx_ring *rx_ring; 2367 u32 desc_size; 2368 u32 len; 2369 int i, rx_allocated; 2370 int ret; 2371 2372 for (i = 0; i < RTW89_RXCH_NUM; i++) { 2373 rx_ring = &rtwpci->rx_rings[i]; 2374 desc_size = sizeof(struct rtw89_pci_rx_bd_32); 2375 len = RTW89_PCI_RXBD_NUM_MAX; 2376 ret = rtw89_pci_alloc_rx_ring(rtwdev, pdev, rx_ring, 2377 desc_size, len, i); 2378 if (ret) { 2379 rtw89_err(rtwdev, "failed to alloc rx ring %d\n", i); 2380 goto err_free; 2381 } 2382 } 2383 2384 return 0; 2385 2386 err_free: 2387 rx_allocated = i; 2388 for (i = 0; i < rx_allocated; i++) { 2389 rx_ring = &rtwpci->rx_rings[i]; 2390 rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); 2391 } 2392 2393 return ret; 2394 } 2395 2396 static int rtw89_pci_alloc_trx_rings(struct rtw89_dev *rtwdev, 2397 struct pci_dev *pdev) 2398 { 2399 int ret; 2400 2401 ret = rtw89_pci_alloc_tx_rings(rtwdev, pdev); 2402 if (ret) { 2403 rtw89_err(rtwdev, "failed to alloc dma tx rings\n"); 2404 goto err; 2405 } 2406 2407 ret = rtw89_pci_alloc_rx_rings(rtwdev, pdev); 2408 if (ret) { 2409 rtw89_err(rtwdev, "failed to alloc dma rx rings\n"); 2410 goto err_free_tx_rings; 2411 } 2412 2413 return 0; 2414 2415 err_free_tx_rings: 2416 rtw89_pci_free_tx_rings(rtwdev, pdev); 2417 err: 2418 return ret; 2419 } 2420 2421 static void rtw89_pci_h2c_init(struct rtw89_dev *rtwdev, 2422 struct rtw89_pci *rtwpci) 2423 { 2424 skb_queue_head_init(&rtwpci->h2c_queue); 2425 skb_queue_head_init(&rtwpci->h2c_release_queue); 2426 } 2427 2428 static int rtw89_pci_setup_resource(struct rtw89_dev *rtwdev, 2429 struct pci_dev *pdev) 2430 { 2431 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2432 int ret; 2433 2434 ret = rtw89_pci_setup_mapping(rtwdev, pdev); 2435 if (ret) { 2436 rtw89_err(rtwdev, "failed to setup pci mapping\n"); 2437 goto err; 2438 } 2439 2440 ret = rtw89_pci_alloc_trx_rings(rtwdev, pdev); 2441 if (ret) { 2442 rtw89_err(rtwdev, "failed to alloc pci trx rings\n"); 2443 goto err_pci_unmap; 2444 } 2445 2446 rtw89_pci_h2c_init(rtwdev, rtwpci); 2447 2448 spin_lock_init(&rtwpci->irq_lock); 2449 spin_lock_init(&rtwpci->trx_lock); 2450 2451 return 0; 2452 2453 err_pci_unmap: 2454 rtw89_pci_clear_mapping(rtwdev, pdev); 2455 err: 2456 return ret; 2457 } 2458 2459 static void rtw89_pci_clear_resource(struct rtw89_dev *rtwdev, 2460 struct pci_dev *pdev) 2461 { 2462 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2463 2464 rtw89_pci_free_trx_rings(rtwdev, pdev); 2465 rtw89_pci_clear_mapping(rtwdev, pdev); 2466 rtw89_pci_release_fwcmd(rtwdev, rtwpci, 2467 skb_queue_len(&rtwpci->h2c_queue), true); 2468 } 2469 2470 static void rtw89_pci_default_intr_mask(struct rtw89_dev *rtwdev) 2471 { 2472 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2473 2474 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | 0; 2475 rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN | 2476 B_AX_RXDMA_INT_EN | 2477 B_AX_RXP1DMA_INT_EN | 2478 B_AX_RPQDMA_INT_EN | 2479 B_AX_RXDMA_STUCK_INT_EN | 2480 B_AX_RDU_INT_EN | 2481 B_AX_RPQBD_FULL_INT_EN | 2482 B_AX_HS0ISR_IND_INT_EN; 2483 2484 rtwpci->intrs[1] = B_AX_HC10ISR_IND_INT_EN; 2485 } 2486 2487 static int rtw89_pci_request_irq(struct rtw89_dev *rtwdev, 2488 struct pci_dev *pdev) 2489 { 2490 unsigned long flags = 0; 2491 int ret; 2492 2493 flags |= PCI_IRQ_LEGACY | PCI_IRQ_MSI; 2494 ret = pci_alloc_irq_vectors(pdev, 1, 1, flags); 2495 if (ret < 0) { 2496 rtw89_err(rtwdev, "failed to alloc irq vectors, ret %d\n", ret); 2497 goto err; 2498 } 2499 2500 ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq, 2501 rtw89_pci_interrupt_handler, 2502 rtw89_pci_interrupt_threadfn, 2503 IRQF_SHARED, KBUILD_MODNAME, rtwdev); 2504 if (ret) { 2505 rtw89_err(rtwdev, "failed to request threaded irq\n"); 2506 goto err_free_vector; 2507 } 2508 2509 rtw89_pci_default_intr_mask(rtwdev); 2510 2511 return 0; 2512 2513 err_free_vector: 2514 pci_free_irq_vectors(pdev); 2515 err: 2516 return ret; 2517 } 2518 2519 static void rtw89_pci_free_irq(struct rtw89_dev *rtwdev, 2520 struct pci_dev *pdev) 2521 { 2522 devm_free_irq(rtwdev->dev, pdev->irq, rtwdev); 2523 pci_free_irq_vectors(pdev); 2524 } 2525 2526 static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable) 2527 { 2528 int ret; 2529 2530 if (rtw89_pci_disable_clkreq) 2531 return; 2532 2533 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_CLK_CTRL, 2534 PCIE_CLKDLY_HW_30US); 2535 if (ret) 2536 rtw89_err(rtwdev, "failed to set CLKREQ Delay\n"); 2537 2538 if (enable) 2539 ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_L1_CTRL, 2540 RTW89_PCIE_BIT_CLK); 2541 else 2542 ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1_CTRL, 2543 RTW89_PCIE_BIT_CLK); 2544 if (ret) 2545 rtw89_err(rtwdev, "failed to %s CLKREQ_L1, ret=%d", 2546 enable ? "set" : "unset", ret); 2547 } 2548 2549 static void rtw89_pci_aspm_set(struct rtw89_dev *rtwdev, bool enable) 2550 { 2551 u8 value = 0; 2552 int ret; 2553 2554 if (rtw89_pci_disable_aspm_l1) 2555 return; 2556 2557 ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, &value); 2558 if (ret) 2559 rtw89_err(rtwdev, "failed to read ASPM Delay\n"); 2560 2561 value &= ~(RTW89_L1DLY_MASK | RTW89_L0DLY_MASK); 2562 value |= FIELD_PREP(RTW89_L1DLY_MASK, PCIE_L1DLY_16US) | 2563 FIELD_PREP(RTW89_L0DLY_MASK, PCIE_L0SDLY_4US); 2564 2565 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, value); 2566 if (ret) 2567 rtw89_err(rtwdev, "failed to read ASPM Delay\n"); 2568 2569 if (enable) 2570 ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_L1_CTRL, 2571 RTW89_PCIE_BIT_L1); 2572 else 2573 ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1_CTRL, 2574 RTW89_PCIE_BIT_L1); 2575 if (ret) 2576 rtw89_err(rtwdev, "failed to %s ASPM L1, ret=%d", 2577 enable ? "set" : "unset", ret); 2578 } 2579 2580 static void rtw89_pci_recalc_int_mit(struct rtw89_dev *rtwdev) 2581 { 2582 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2583 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 2584 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 2585 u32 val = 0; 2586 2587 if (!rtwdev->scanning && 2588 (tx_tfc_lv >= RTW89_TFC_HIGH || rx_tfc_lv >= RTW89_TFC_HIGH)) 2589 val = B_AX_RXMIT_RXP2_SEL | B_AX_RXMIT_RXP1_SEL | 2590 FIELD_PREP(B_AX_RXCOUNTER_MATCH_MASK, RTW89_PCI_RXBD_NUM_MAX / 2) | 2591 FIELD_PREP(B_AX_RXTIMER_UNIT_MASK, AX_RXTIMER_UNIT_64US) | 2592 FIELD_PREP(B_AX_RXTIMER_MATCH_MASK, 2048 / 64); 2593 2594 rtw89_write32(rtwdev, R_AX_INT_MIT_RX, val); 2595 } 2596 2597 static void rtw89_pci_link_cfg(struct rtw89_dev *rtwdev) 2598 { 2599 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2600 struct pci_dev *pdev = rtwpci->pdev; 2601 u16 link_ctrl; 2602 int ret; 2603 2604 /* Though there is standard PCIE configuration space to set the 2605 * link control register, but by Realtek's design, driver should 2606 * check if host supports CLKREQ/ASPM to enable the HW module. 2607 * 2608 * These functions are implemented by two HW modules associated, 2609 * one is responsible to access PCIE configuration space to 2610 * follow the host settings, and another is in charge of doing 2611 * CLKREQ/ASPM mechanisms, it is default disabled. Because sometimes 2612 * the host does not support it, and due to some reasons or wrong 2613 * settings (ex. CLKREQ# not Bi-Direction), it could lead to device 2614 * loss if HW misbehaves on the link. 2615 * 2616 * Hence it's designed that driver should first check the PCIE 2617 * configuration space is sync'ed and enabled, then driver can turn 2618 * on the other module that is actually working on the mechanism. 2619 */ 2620 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &link_ctrl); 2621 if (ret) { 2622 rtw89_err(rtwdev, "failed to read PCI cap, ret=%d\n", ret); 2623 return; 2624 } 2625 2626 if (link_ctrl & PCI_EXP_LNKCTL_CLKREQ_EN) 2627 rtw89_pci_clkreq_set(rtwdev, true); 2628 2629 if (link_ctrl & PCI_EXP_LNKCTL_ASPM_L1) 2630 rtw89_pci_aspm_set(rtwdev, true); 2631 } 2632 2633 static void rtw89_pci_l1ss_set(struct rtw89_dev *rtwdev, bool enable) 2634 { 2635 int ret; 2636 2637 if (enable) 2638 ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_TIMER_CTRL, 2639 RTW89_PCIE_BIT_L1SUB); 2640 else 2641 ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_TIMER_CTRL, 2642 RTW89_PCIE_BIT_L1SUB); 2643 if (ret) 2644 rtw89_err(rtwdev, "failed to %s L1SS, ret=%d", 2645 enable ? "set" : "unset", ret); 2646 } 2647 2648 static void rtw89_pci_l1ss_cfg(struct rtw89_dev *rtwdev) 2649 { 2650 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2651 struct pci_dev *pdev = rtwpci->pdev; 2652 u32 l1ss_cap_ptr, l1ss_ctrl; 2653 2654 if (rtw89_pci_disable_l1ss) 2655 return; 2656 2657 l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); 2658 if (!l1ss_cap_ptr) 2659 return; 2660 2661 pci_read_config_dword(pdev, l1ss_cap_ptr + PCI_L1SS_CTL1, &l1ss_ctrl); 2662 2663 if (l1ss_ctrl & PCI_L1SS_CTL1_L1SS_MASK) 2664 rtw89_pci_l1ss_set(rtwdev, true); 2665 } 2666 2667 static void rtw89_pci_ctrl_dma_all_pcie(struct rtw89_dev *rtwdev, u8 en) 2668 { 2669 u32 val32; 2670 2671 if (en == MAC_AX_FUNC_EN) { 2672 val32 = B_AX_STOP_PCIEIO; 2673 rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, val32); 2674 2675 val32 = B_AX_TXHCI_EN | B_AX_RXHCI_EN; 2676 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, val32); 2677 } else { 2678 val32 = B_AX_STOP_PCIEIO; 2679 rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP1, val32); 2680 2681 val32 = B_AX_TXHCI_EN | B_AX_RXHCI_EN; 2682 rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, val32); 2683 } 2684 } 2685 2686 static int rtw89_pci_poll_io_idle(struct rtw89_dev *rtwdev) 2687 { 2688 int ret = 0; 2689 u32 sts; 2690 u32 busy = B_AX_PCIEIO_BUSY | B_AX_PCIEIO_TX_BUSY | B_AX_PCIEIO_RX_BUSY; 2691 2692 ret = read_poll_timeout_atomic(rtw89_read32, sts, (sts & busy) == 0x0, 2693 10, 1000, false, rtwdev, 2694 R_AX_PCIE_DMA_BUSY1); 2695 if (ret) { 2696 rtw89_err(rtwdev, "pci dmach busy1 0x%X\n", 2697 rtw89_read32(rtwdev, R_AX_PCIE_DMA_BUSY1)); 2698 return -EINVAL; 2699 } 2700 return ret; 2701 } 2702 2703 static int rtw89_pci_lv1rst_stop_dma(struct rtw89_dev *rtwdev) 2704 { 2705 u32 val, dma_rst = 0; 2706 int ret; 2707 2708 rtw89_pci_ctrl_dma_all_pcie(rtwdev, MAC_AX_FUNC_DIS); 2709 ret = rtw89_pci_poll_io_idle(rtwdev); 2710 if (ret) { 2711 val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG); 2712 rtw89_debug(rtwdev, RTW89_DBG_HCI, 2713 "[PCIe] poll_io_idle fail, before 0x%08x: 0x%08x\n", 2714 R_AX_DBG_ERR_FLAG, val); 2715 if (val & B_AX_TX_STUCK || val & B_AX_PCIE_TXBD_LEN0) 2716 dma_rst |= B_AX_HCI_TXDMA_EN; 2717 if (val & B_AX_RX_STUCK) 2718 dma_rst |= B_AX_HCI_RXDMA_EN; 2719 val = rtw89_read32(rtwdev, R_AX_HCI_FUNC_EN); 2720 rtw89_write32(rtwdev, R_AX_HCI_FUNC_EN, val & ~dma_rst); 2721 rtw89_write32(rtwdev, R_AX_HCI_FUNC_EN, val | dma_rst); 2722 ret = rtw89_pci_poll_io_idle(rtwdev); 2723 val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG); 2724 rtw89_debug(rtwdev, RTW89_DBG_HCI, 2725 "[PCIe] poll_io_idle fail, after 0x%08x: 0x%08x\n", 2726 R_AX_DBG_ERR_FLAG, val); 2727 } 2728 2729 return ret; 2730 } 2731 2732 static void rtw89_pci_ctrl_hci_dma_en(struct rtw89_dev *rtwdev, u8 en) 2733 { 2734 u32 val32; 2735 2736 if (en == MAC_AX_FUNC_EN) { 2737 val32 = B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN; 2738 rtw89_write32_set(rtwdev, R_AX_HCI_FUNC_EN, val32); 2739 } else { 2740 val32 = B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN; 2741 rtw89_write32_clr(rtwdev, R_AX_HCI_FUNC_EN, val32); 2742 } 2743 } 2744 2745 static int rtw89_pci_rst_bdram(struct rtw89_dev *rtwdev) 2746 { 2747 int ret = 0; 2748 u32 val32, sts; 2749 2750 val32 = B_AX_RST_BDRAM; 2751 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, val32); 2752 2753 ret = read_poll_timeout_atomic(rtw89_read32, sts, 2754 (sts & B_AX_RST_BDRAM) == 0x0, 1, 100, 2755 true, rtwdev, R_AX_PCIE_INIT_CFG1); 2756 return ret; 2757 } 2758 2759 static int rtw89_pci_lv1rst_start_dma(struct rtw89_dev *rtwdev) 2760 { 2761 u32 ret; 2762 2763 rtw89_pci_ctrl_hci_dma_en(rtwdev, MAC_AX_FUNC_DIS); 2764 rtw89_pci_ctrl_hci_dma_en(rtwdev, MAC_AX_FUNC_EN); 2765 rtw89_pci_clr_idx_all(rtwdev); 2766 2767 ret = rtw89_pci_rst_bdram(rtwdev); 2768 if (ret) 2769 return ret; 2770 2771 rtw89_pci_ctrl_dma_all_pcie(rtwdev, MAC_AX_FUNC_EN); 2772 return ret; 2773 } 2774 2775 static int rtw89_pci_ops_mac_lv1_recovery(struct rtw89_dev *rtwdev, 2776 enum rtw89_lv1_rcvy_step step) 2777 { 2778 int ret; 2779 2780 switch (step) { 2781 case RTW89_LV1_RCVY_STEP_1: 2782 ret = rtw89_pci_lv1rst_stop_dma(rtwdev); 2783 if (ret) 2784 rtw89_err(rtwdev, "lv1 rcvy pci stop dma fail\n"); 2785 2786 break; 2787 2788 case RTW89_LV1_RCVY_STEP_2: 2789 ret = rtw89_pci_lv1rst_start_dma(rtwdev); 2790 if (ret) 2791 rtw89_err(rtwdev, "lv1 rcvy pci start dma fail\n"); 2792 break; 2793 2794 default: 2795 return -EINVAL; 2796 } 2797 2798 return ret; 2799 } 2800 2801 static void rtw89_pci_ops_dump_err_status(struct rtw89_dev *rtwdev) 2802 { 2803 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX =0x%08x\n", 2804 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 2805 rtw89_info(rtwdev, "R_AX_DBG_ERR_FLAG=0x%08x\n", 2806 rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG)); 2807 rtw89_info(rtwdev, "R_AX_LBC_WATCHDOG=0x%08x\n", 2808 rtw89_read32(rtwdev, R_AX_LBC_WATCHDOG)); 2809 } 2810 2811 static int rtw89_pci_napi_poll(struct napi_struct *napi, int budget) 2812 { 2813 struct rtw89_dev *rtwdev = container_of(napi, struct rtw89_dev, napi); 2814 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2815 unsigned long flags; 2816 int work_done; 2817 2818 rtwdev->napi_budget_countdown = budget; 2819 2820 rtw89_pci_clear_isr0(rtwdev, B_AX_RPQDMA_INT | B_AX_RPQBD_FULL_INT); 2821 work_done = rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); 2822 if (work_done == budget) 2823 return budget; 2824 2825 rtw89_pci_clear_isr0(rtwdev, B_AX_RXP1DMA_INT | B_AX_RXDMA_INT | B_AX_RDU_INT); 2826 work_done += rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); 2827 if (work_done < budget && napi_complete_done(napi, work_done)) { 2828 spin_lock_irqsave(&rtwpci->irq_lock, flags); 2829 if (likely(rtwpci->running)) 2830 rtw89_pci_enable_intr(rtwdev, rtwpci); 2831 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 2832 } 2833 2834 return work_done; 2835 } 2836 2837 static int __maybe_unused rtw89_pci_suspend(struct device *dev) 2838 { 2839 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2840 struct rtw89_dev *rtwdev = hw->priv; 2841 2842 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, 2843 B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); 2844 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); 2845 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); 2846 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); 2847 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, 2848 B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG); 2849 2850 return 0; 2851 } 2852 2853 static void rtw89_pci_l2_hci_ldo(struct rtw89_dev *rtwdev) 2854 { 2855 if (rtwdev->chip->chip_id == RTL8852C) 2856 return; 2857 2858 /* Hardware need write the reg twice to ensure the setting work */ 2859 rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_RST_MSTATE, 2860 RTW89_PCIE_BIT_CFG_RST_MSTATE); 2861 rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_RST_MSTATE, 2862 RTW89_PCIE_BIT_CFG_RST_MSTATE); 2863 } 2864 2865 static int __maybe_unused rtw89_pci_resume(struct device *dev) 2866 { 2867 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2868 struct rtw89_dev *rtwdev = hw->priv; 2869 2870 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, 2871 B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); 2872 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); 2873 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); 2874 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); 2875 rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, 2876 B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG); 2877 rtw89_pci_l2_hci_ldo(rtwdev); 2878 rtw89_pci_link_cfg(rtwdev); 2879 rtw89_pci_l1ss_cfg(rtwdev); 2880 2881 return 0; 2882 } 2883 2884 SIMPLE_DEV_PM_OPS(rtw89_pm_ops, rtw89_pci_suspend, rtw89_pci_resume); 2885 EXPORT_SYMBOL(rtw89_pm_ops); 2886 2887 static const struct rtw89_hci_ops rtw89_pci_ops = { 2888 .tx_write = rtw89_pci_ops_tx_write, 2889 .tx_kick_off = rtw89_pci_ops_tx_kick_off, 2890 .flush_queues = rtw89_pci_ops_flush_queues, 2891 .reset = rtw89_pci_ops_reset, 2892 .start = rtw89_pci_ops_start, 2893 .stop = rtw89_pci_ops_stop, 2894 .recalc_int_mit = rtw89_pci_recalc_int_mit, 2895 2896 .read8 = rtw89_pci_ops_read8, 2897 .read16 = rtw89_pci_ops_read16, 2898 .read32 = rtw89_pci_ops_read32, 2899 .write8 = rtw89_pci_ops_write8, 2900 .write16 = rtw89_pci_ops_write16, 2901 .write32 = rtw89_pci_ops_write32, 2902 2903 .mac_pre_init = rtw89_pci_ops_mac_pre_init, 2904 .mac_post_init = rtw89_pci_ops_mac_post_init, 2905 .deinit = rtw89_pci_ops_deinit, 2906 2907 .check_and_reclaim_tx_resource = rtw89_pci_check_and_reclaim_tx_resource, 2908 .mac_lv1_rcvy = rtw89_pci_ops_mac_lv1_recovery, 2909 .dump_err_status = rtw89_pci_ops_dump_err_status, 2910 .napi_poll = rtw89_pci_napi_poll, 2911 }; 2912 2913 int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2914 { 2915 struct ieee80211_hw *hw; 2916 struct rtw89_dev *rtwdev; 2917 const struct rtw89_driver_info *info; 2918 int driver_data_size; 2919 int ret; 2920 2921 driver_data_size = sizeof(struct rtw89_dev) + sizeof(struct rtw89_pci); 2922 hw = ieee80211_alloc_hw(driver_data_size, &rtw89_ops); 2923 if (!hw) { 2924 dev_err(&pdev->dev, "failed to allocate hw\n"); 2925 return -ENOMEM; 2926 } 2927 2928 rtwdev = hw->priv; 2929 rtwdev->hw = hw; 2930 rtwdev->dev = &pdev->dev; 2931 rtwdev->hci.ops = &rtw89_pci_ops; 2932 rtwdev->hci.type = RTW89_HCI_TYPE_PCIE; 2933 rtwdev->hci.rpwm_addr = R_AX_PCIE_HRPWM; 2934 rtwdev->hci.cpwm_addr = R_AX_CPWM; 2935 2936 SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev); 2937 2938 info = (const struct rtw89_driver_info *)id->driver_data; 2939 rtwdev->chip = info->chip; 2940 2941 ret = rtw89_core_init(rtwdev); 2942 if (ret) { 2943 rtw89_err(rtwdev, "failed to initialise core\n"); 2944 goto err_release_hw; 2945 } 2946 2947 ret = rtw89_pci_claim_device(rtwdev, pdev); 2948 if (ret) { 2949 rtw89_err(rtwdev, "failed to claim pci device\n"); 2950 goto err_core_deinit; 2951 } 2952 2953 ret = rtw89_pci_setup_resource(rtwdev, pdev); 2954 if (ret) { 2955 rtw89_err(rtwdev, "failed to setup pci resource\n"); 2956 goto err_declaim_pci; 2957 } 2958 2959 ret = rtw89_chip_info_setup(rtwdev); 2960 if (ret) { 2961 rtw89_err(rtwdev, "failed to setup chip information\n"); 2962 goto err_clear_resource; 2963 } 2964 2965 rtw89_pci_link_cfg(rtwdev); 2966 rtw89_pci_l1ss_cfg(rtwdev); 2967 2968 ret = rtw89_core_register(rtwdev); 2969 if (ret) { 2970 rtw89_err(rtwdev, "failed to register core\n"); 2971 goto err_clear_resource; 2972 } 2973 2974 rtw89_core_napi_init(rtwdev); 2975 2976 ret = rtw89_pci_request_irq(rtwdev, pdev); 2977 if (ret) { 2978 rtw89_err(rtwdev, "failed to request pci irq\n"); 2979 goto err_unregister; 2980 } 2981 2982 return 0; 2983 2984 err_unregister: 2985 rtw89_core_napi_deinit(rtwdev); 2986 rtw89_core_unregister(rtwdev); 2987 err_clear_resource: 2988 rtw89_pci_clear_resource(rtwdev, pdev); 2989 err_declaim_pci: 2990 rtw89_pci_declaim_device(rtwdev, pdev); 2991 err_core_deinit: 2992 rtw89_core_deinit(rtwdev); 2993 err_release_hw: 2994 ieee80211_free_hw(hw); 2995 2996 return ret; 2997 } 2998 EXPORT_SYMBOL(rtw89_pci_probe); 2999 3000 void rtw89_pci_remove(struct pci_dev *pdev) 3001 { 3002 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 3003 struct rtw89_dev *rtwdev; 3004 3005 rtwdev = hw->priv; 3006 3007 rtw89_pci_free_irq(rtwdev, pdev); 3008 rtw89_core_napi_deinit(rtwdev); 3009 rtw89_core_unregister(rtwdev); 3010 rtw89_pci_clear_resource(rtwdev, pdev); 3011 rtw89_pci_declaim_device(rtwdev, pdev); 3012 rtw89_core_deinit(rtwdev); 3013 ieee80211_free_hw(hw); 3014 } 3015 EXPORT_SYMBOL(rtw89_pci_remove); 3016 3017 MODULE_AUTHOR("Realtek Corporation"); 3018 MODULE_DESCRIPTION("Realtek 802.11ax wireless PCI driver"); 3019 MODULE_LICENSE("Dual BSD/GPL"); 3020