1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "debug.h" 6 #include "efuse.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "reg.h" 10 11 static const u32 rtw89_mac_mem_base_addrs_be[RTW89_MAC_MEM_NUM] = { 12 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR_BE, 13 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR_BE, 14 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR_BE, 15 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR_BE, 16 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR_BE, 17 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR_BE, 18 [RTW89_MAC_MEM_SECURITY_CAM] = SEC_CAM_BASE_ADDR_BE, 19 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR_BE, 20 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR_BE, 21 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR_BE, 22 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR_BE, 23 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR_BE, 24 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR_BE, 25 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR_BE, 26 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR_BE, 27 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR_BE, 28 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR_BE, 29 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR_BE, 30 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR_BE, 31 [RTW89_MAC_MEM_WD_PAGE] = WD_PAGE_BASE_ADDR_BE, 32 [RTW89_MAC_MEM_MLD_TBL] = MLD_TBL_BASE_ADDR_BE, 33 }; 34 35 static const struct rtw89_port_reg rtw89_port_base_be = { 36 .port_cfg = R_BE_PORT_CFG_P0, 37 .tbtt_prohib = R_BE_TBTT_PROHIB_P0, 38 .bcn_area = R_BE_BCN_AREA_P0, 39 .bcn_early = R_BE_BCNERLYINT_CFG_P0, 40 .tbtt_early = R_BE_TBTTERLYINT_CFG_P0, 41 .tbtt_agg = R_BE_TBTT_AGG_P0, 42 .bcn_space = R_BE_BCN_SPACE_CFG_P0, 43 .bcn_forcetx = R_BE_BCN_FORCETX_P0, 44 .bcn_err_cnt = R_BE_BCN_ERR_CNT_P0, 45 .bcn_err_flag = R_BE_BCN_ERR_FLAG_P0, 46 .dtim_ctrl = R_BE_DTIM_CTRL_P0, 47 .tbtt_shift = R_BE_TBTT_SHIFT_P0, 48 .bcn_cnt_tmr = R_BE_BCN_CNT_TMR_P0, 49 .tsftr_l = R_BE_TSFTR_LOW_P0, 50 .tsftr_h = R_BE_TSFTR_HIGH_P0, 51 .md_tsft = R_BE_WMTX_MOREDATA_TSFT_STMP_CTL, 52 .bss_color = R_BE_PTCL_BSS_COLOR_0, 53 .mbssid = R_BE_MBSSID_CTRL, 54 .mbssid_drop = R_BE_MBSSID_DROP_0, 55 .tsf_sync = R_BE_PORT_0_TSF_SYNC, 56 .ptcl_dbg = R_BE_PTCL_DBG, 57 .ptcl_dbg_info = R_BE_PTCL_DBG_INFO, 58 .bcn_drop_all = R_BE_BCN_DROP_ALL0, 59 .bcn_psr_rpt = R_BE_BCN_PSR_RPT_P0, 60 .hiq_win = {R_BE_P0MB_HGQ_WINDOW_CFG_0, R_BE_PORT_HGQ_WINDOW_CFG, 61 R_BE_PORT_HGQ_WINDOW_CFG + 1, R_BE_PORT_HGQ_WINDOW_CFG + 2, 62 R_BE_PORT_HGQ_WINDOW_CFG + 3}, 63 }; 64 65 static int rtw89_mac_check_mac_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, 66 enum rtw89_mac_hwmod_sel sel) 67 { 68 if (sel == RTW89_DMAC_SEL && 69 test_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags)) 70 return 0; 71 if (sel == RTW89_CMAC_SEL && mac_idx == RTW89_MAC_0 && 72 test_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags)) 73 return 0; 74 if (sel == RTW89_CMAC_SEL && mac_idx == RTW89_MAC_1 && 75 test_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags)) 76 return 0; 77 78 return -EFAULT; 79 } 80 81 static bool is_qta_poh(struct rtw89_dev *rtwdev) 82 { 83 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 84 } 85 86 static void hfc_get_mix_info_be(struct rtw89_dev *rtwdev) 87 { 88 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 89 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 90 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 91 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 92 u32 val; 93 94 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO1); 95 info->g0_used = u32_get_bits(val, B_BE_G0_USE_PG_MASK); 96 info->g1_used = u32_get_bits(val, B_BE_G1_USE_PG_MASK); 97 98 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO3); 99 info->g0_aval = u32_get_bits(val, B_BE_G0_AVAL_PG_MASK); 100 info->g1_aval = u32_get_bits(val, B_BE_G1_AVAL_PG_MASK); 101 info->pub_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO2), 102 B_BE_PUB_AVAL_PG_MASK); 103 info->wp_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_WP_PAGE_INFO1), 104 B_BE_WP_AVAL_PG_MASK); 105 106 val = rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL); 107 param->en = !!(val & B_BE_HCI_FC_EN); 108 param->h2c_en = !!(val & B_BE_HCI_FC_CH12_EN); 109 param->mode = u32_get_bits(val, B_BE_HCI_FC_MODE_MASK); 110 prec_cfg->ch011_full_cond = u32_get_bits(val, B_BE_HCI_FC_WD_FULL_COND_MASK); 111 prec_cfg->h2c_full_cond = u32_get_bits(val, B_BE_HCI_FC_CH12_FULL_COND_MASK); 112 prec_cfg->wp_ch07_full_cond = 113 u32_get_bits(val, B_BE_HCI_FC_WP_CH07_FULL_COND_MASK); 114 prec_cfg->wp_ch811_full_cond = 115 u32_get_bits(val, B_BE_HCI_FC_WP_CH811_FULL_COND_MASK); 116 117 val = rtw89_read32(rtwdev, R_BE_CH_PAGE_CTRL); 118 prec_cfg->ch011_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH011_V1_MASK); 119 prec_cfg->h2c_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH12_V1_MASK); 120 121 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL2); 122 pub_cfg->pub_max = u32_get_bits(val, B_BE_PUBPG_ALL_MASK); 123 124 val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL1); 125 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_MASK); 126 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_MASK); 127 128 val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL2); 129 pub_cfg->wp_thrd = u32_get_bits(val, B_BE_WP_THRD_MASK); 130 131 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL1); 132 pub_cfg->grp0 = u32_get_bits(val, B_BE_PUBPG_G0_MASK); 133 pub_cfg->grp1 = u32_get_bits(val, B_BE_PUBPG_G1_MASK); 134 } 135 136 static void hfc_h2c_cfg_be(struct rtw89_dev *rtwdev) 137 { 138 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 139 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 140 u32 val; 141 142 val = u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK); 143 rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val); 144 } 145 146 static void hfc_mix_cfg_be(struct rtw89_dev *rtwdev) 147 { 148 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 149 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 150 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 151 u32 val; 152 153 val = u32_encode_bits(prec_cfg->ch011_prec, B_BE_PREC_PAGE_CH011_V1_MASK) | 154 u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK); 155 rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val); 156 157 val = u32_encode_bits(pub_cfg->pub_max, B_BE_PUBPG_ALL_MASK); 158 rtw89_write32(rtwdev, R_BE_PUB_PAGE_CTRL2, val); 159 160 val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_MASK) | 161 u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_MASK); 162 rtw89_write32(rtwdev, R_BE_WP_PAGE_CTRL1, val); 163 164 val = u32_replace_bits(rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL), 165 param->mode, B_BE_HCI_FC_MODE_MASK); 166 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 167 B_BE_HCI_FC_WD_FULL_COND_MASK); 168 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 169 B_BE_HCI_FC_CH12_FULL_COND_MASK); 170 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 171 B_BE_HCI_FC_WP_CH07_FULL_COND_MASK); 172 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 173 B_BE_HCI_FC_WP_CH811_FULL_COND_MASK); 174 rtw89_write32(rtwdev, R_BE_HCI_FC_CTRL, val); 175 } 176 177 static void hfc_func_en_be(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 178 { 179 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 180 u32 val; 181 182 val = rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL); 183 param->en = en; 184 param->h2c_en = h2c_en; 185 val = en ? (val | B_BE_HCI_FC_EN) : (val & ~B_BE_HCI_FC_EN); 186 val = h2c_en ? (val | B_BE_HCI_FC_CH12_EN) : 187 (val & ~B_BE_HCI_FC_CH12_EN); 188 rtw89_write32(rtwdev, R_BE_HCI_FC_CTRL, val); 189 } 190 191 static void dle_func_en_be(struct rtw89_dev *rtwdev, bool enable) 192 { 193 if (enable) 194 rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN, 195 B_BE_DLE_WDE_EN | B_BE_DLE_PLE_EN); 196 else 197 rtw89_write32_clr(rtwdev, R_BE_DMAC_FUNC_EN, 198 B_BE_DLE_WDE_EN | B_BE_DLE_PLE_EN); 199 } 200 201 static void dle_clk_en_be(struct rtw89_dev *rtwdev, bool enable) 202 { 203 if (enable) 204 rtw89_write32_set(rtwdev, R_BE_DMAC_CLK_EN, 205 B_BE_DLE_WDE_CLK_EN | B_BE_DLE_PLE_CLK_EN); 206 else 207 rtw89_write32_clr(rtwdev, R_BE_DMAC_CLK_EN, 208 B_BE_DLE_WDE_CLK_EN | B_BE_DLE_PLE_CLK_EN); 209 } 210 211 static int dle_mix_cfg_be(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 212 { 213 const struct rtw89_dle_size *wde_size_cfg, *ple_size_cfg; 214 u32 bound; 215 u32 val; 216 217 wde_size_cfg = cfg->wde_size; 218 ple_size_cfg = cfg->ple_size; 219 220 val = rtw89_read32(rtwdev, R_BE_WDE_PKTBUF_CFG); 221 222 switch (wde_size_cfg->pge_size) { 223 default: 224 case RTW89_WDE_PG_64: 225 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 226 B_BE_WDE_PAGE_SEL_MASK); 227 break; 228 case RTW89_WDE_PG_128: 229 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 230 B_BE_WDE_PAGE_SEL_MASK); 231 break; 232 case RTW89_WDE_PG_256: 233 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 234 return -EINVAL; 235 } 236 237 bound = wde_size_cfg->srt_ofst / DLE_BOUND_UNIT; 238 val = u32_replace_bits(val, bound, B_BE_WDE_START_BOUND_MASK); 239 val = u32_replace_bits(val, wde_size_cfg->lnk_pge_num, 240 B_BE_WDE_FREE_PAGE_NUM_MASK); 241 rtw89_write32(rtwdev, R_BE_WDE_PKTBUF_CFG, val); 242 243 val = rtw89_read32(rtwdev, R_BE_PLE_PKTBUF_CFG); 244 245 switch (ple_size_cfg->pge_size) { 246 default: 247 case RTW89_PLE_PG_64: 248 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 249 return -EINVAL; 250 case RTW89_PLE_PG_128: 251 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 252 B_BE_PLE_PAGE_SEL_MASK); 253 break; 254 case RTW89_PLE_PG_256: 255 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 256 B_BE_PLE_PAGE_SEL_MASK); 257 break; 258 } 259 260 bound = ple_size_cfg->srt_ofst / DLE_BOUND_UNIT; 261 val = u32_replace_bits(val, bound, B_BE_PLE_START_BOUND_MASK); 262 val = u32_replace_bits(val, ple_size_cfg->lnk_pge_num, 263 B_BE_PLE_FREE_PAGE_NUM_MASK); 264 rtw89_write32(rtwdev, R_BE_PLE_PKTBUF_CFG, val); 265 266 return 0; 267 } 268 269 static int chk_dle_rdy_be(struct rtw89_dev *rtwdev, bool wde_or_ple) 270 { 271 u32 reg, mask; 272 u32 ini; 273 274 if (wde_or_ple) { 275 reg = R_AX_WDE_INI_STATUS; 276 mask = WDE_MGN_INI_RDY; 277 } else { 278 reg = R_AX_PLE_INI_STATUS; 279 mask = PLE_MGN_INI_RDY; 280 } 281 282 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 283 2000, false, rtwdev, reg); 284 } 285 286 #define INVALID_QT_WCPU U16_MAX 287 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 288 do { \ 289 val = u32_encode_bits(_min_x, B_BE_ ## _module ## _Q ## _idx ## _MIN_SIZE_MASK) | \ 290 u32_encode_bits(_max_x, B_BE_ ## _module ## _Q ## _idx ## _MAX_SIZE_MASK); \ 291 rtw89_write32(rtwdev, \ 292 R_BE_ ## _module ## _QTA ## _idx ## _CFG, \ 293 val); \ 294 } while (0) 295 #define SET_QUOTA(_x, _module, _idx) \ 296 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 297 298 static void wde_quota_cfg_be(struct rtw89_dev *rtwdev, 299 const struct rtw89_wde_quota *min_cfg, 300 const struct rtw89_wde_quota *max_cfg, 301 u16 ext_wde_min_qt_wcpu) 302 { 303 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 304 ext_wde_min_qt_wcpu : min_cfg->wcpu; 305 u16 max_qt_wcpu = max(max_cfg->wcpu, min_qt_wcpu); 306 u32 val; 307 308 SET_QUOTA(hif, WDE, 0); 309 SET_QUOTA_VAL(min_qt_wcpu, max_qt_wcpu, WDE, 1); 310 SET_QUOTA_VAL(0, 0, WDE, 2); 311 SET_QUOTA(pkt_in, WDE, 3); 312 SET_QUOTA(cpu_io, WDE, 4); 313 } 314 315 static void ple_quota_cfg_be(struct rtw89_dev *rtwdev, 316 const struct rtw89_ple_quota *min_cfg, 317 const struct rtw89_ple_quota *max_cfg) 318 { 319 u32 val; 320 321 SET_QUOTA(cma0_tx, PLE, 0); 322 SET_QUOTA(cma1_tx, PLE, 1); 323 SET_QUOTA(c2h, PLE, 2); 324 SET_QUOTA(h2c, PLE, 3); 325 SET_QUOTA(wcpu, PLE, 4); 326 SET_QUOTA(mpdu_proc, PLE, 5); 327 SET_QUOTA(cma0_dma, PLE, 6); 328 SET_QUOTA(cma1_dma, PLE, 7); 329 SET_QUOTA(bb_rpt, PLE, 8); 330 SET_QUOTA(wd_rel, PLE, 9); 331 SET_QUOTA(cpu_io, PLE, 10); 332 SET_QUOTA(tx_rpt, PLE, 11); 333 SET_QUOTA(h2d, PLE, 12); 334 } 335 336 static void rtw89_mac_hci_func_en_be(struct rtw89_dev *rtwdev) 337 { 338 rtw89_write32_set(rtwdev, R_BE_HCI_FUNC_EN, B_BE_HCI_TXDMA_EN | 339 B_BE_HCI_RXDMA_EN); 340 } 341 342 static void rtw89_mac_dmac_func_pre_en_be(struct rtw89_dev *rtwdev) 343 { 344 u32 val; 345 346 val = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1); 347 348 switch (rtwdev->hci.type) { 349 case RTW89_HCI_TYPE_PCIE: 350 val = u32_replace_bits(val, S_BE_DMA_MOD_PCIE_NO_DATA_CPU, 351 B_BE_DMA_MODE_MASK); 352 break; 353 case RTW89_HCI_TYPE_USB: 354 val = u32_replace_bits(val, S_BE_DMA_MOD_USB, B_BE_DMA_MODE_MASK); 355 val = (val & ~B_BE_STOP_AXI_MST) | B_BE_TXDMA_EN | B_BE_RXDMA_EN; 356 break; 357 case RTW89_HCI_TYPE_SDIO: 358 val = u32_replace_bits(val, S_BE_DMA_MOD_SDIO, B_BE_DMA_MODE_MASK); 359 val = (val & ~B_BE_STOP_AXI_MST) | B_BE_TXDMA_EN | B_BE_RXDMA_EN; 360 break; 361 default: 362 return; 363 } 364 365 rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val); 366 367 rtw89_write32_clr(rtwdev, R_BE_HAXI_DMA_STOP1, 368 B_BE_STOP_CH0 | B_BE_STOP_CH1 | B_BE_STOP_CH2 | 369 B_BE_STOP_CH3 | B_BE_STOP_CH4 | B_BE_STOP_CH5 | 370 B_BE_STOP_CH6 | B_BE_STOP_CH7 | B_BE_STOP_CH8 | 371 B_BE_STOP_CH9 | B_BE_STOP_CH10 | B_BE_STOP_CH11 | 372 B_BE_STOP_CH12 | B_BE_STOP_CH13 | B_BE_STOP_CH14); 373 374 rtw89_write32_set(rtwdev, R_BE_DMAC_TABLE_CTRL, B_BE_DMAC_ADDR_MODE); 375 } 376 377 static 378 int rtw89_mac_write_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 379 { 380 u32 val32; 381 int ret; 382 383 val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) | 384 u32_encode_bits(val, B_BE_WL_XTAL_SI_DATA_MASK) | 385 u32_encode_bits(mask, B_BE_WL_XTAL_SI_BITMASK_MASK) | 386 u32_encode_bits(XTAL_SI_NORMAL_WRITE, B_BE_WL_XTAL_SI_MODE_MASK) | 387 u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) | 388 B_BE_WL_XTAL_SI_CMD_POLL; 389 rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32); 390 391 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL), 392 50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL); 393 if (ret) { 394 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 395 offset, val, mask); 396 return ret; 397 } 398 399 return 0; 400 } 401 402 static 403 int rtw89_mac_read_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 404 { 405 u32 val32; 406 int ret; 407 408 val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) | 409 u32_encode_bits(0x0, B_BE_WL_XTAL_SI_DATA_MASK) | 410 u32_encode_bits(0x0, B_BE_WL_XTAL_SI_BITMASK_MASK) | 411 u32_encode_bits(XTAL_SI_NORMAL_READ, B_BE_WL_XTAL_SI_MODE_MASK) | 412 u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) | 413 B_BE_WL_XTAL_SI_CMD_POLL; 414 rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32); 415 416 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL), 417 50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL); 418 if (ret) { 419 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 420 return ret; 421 } 422 423 *val = rtw89_read8(rtwdev, R_BE_WLAN_XTAL_SI_CTRL + 1); 424 425 return 0; 426 } 427 428 static void rtw89_mac_disable_cpu_be(struct rtw89_dev *rtwdev) 429 { 430 u32 val32; 431 432 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 433 434 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN); 435 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET); 436 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN); 437 438 val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL); 439 val32 &= B_BE_RUN_ENV_MASK; 440 rtw89_write32(rtwdev, R_BE_WCPU_FW_CTRL, val32); 441 442 rtw89_write32_set(rtwdev, R_BE_DCPU_PLATFORM_ENABLE, B_BE_DCPU_PLATFORM_EN); 443 444 rtw89_write32(rtwdev, R_BE_UDM0, 0); 445 rtw89_write32(rtwdev, R_BE_HALT_C2H, 0); 446 rtw89_write32(rtwdev, R_BE_UDM2, 0); 447 } 448 449 static void set_cpu_en(struct rtw89_dev *rtwdev, bool include_bb) 450 { 451 u32 set = B_BE_WLANCPU_FWDL_EN; 452 453 if (include_bb) 454 set |= B_BE_BBMCU0_FWDL_EN; 455 456 rtw89_write32_set(rtwdev, R_BE_WCPU_FW_CTRL, set); 457 } 458 459 static int wcpu_on(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw) 460 { 461 const struct rtw89_chip_info *chip = rtwdev->chip; 462 u32 val32; 463 int ret; 464 465 val32 = rtw89_read32(rtwdev, R_BE_HALT_C2H); 466 if (val32) { 467 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n"); 468 rtw89_warn(rtwdev, "[SER] %s: R_BE_HALT_C2H = 0x%x\n", __func__, val32); 469 } 470 val32 = rtw89_read32(rtwdev, R_BE_UDM1); 471 if (val32) { 472 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n"); 473 rtw89_warn(rtwdev, "[SER] %s: R_BE_UDM1 = 0x%x\n", __func__, val32); 474 } 475 val32 = rtw89_read32(rtwdev, R_BE_UDM2); 476 if (val32) { 477 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n"); 478 rtw89_warn(rtwdev, "[SER] %s: R_BE_UDM2 = 0x%x\n", __func__, val32); 479 } 480 481 rtw89_write32(rtwdev, R_BE_UDM1, 0); 482 rtw89_write32(rtwdev, R_BE_UDM2, 0); 483 rtw89_write32(rtwdev, R_BE_BOOT_DBG, 0x0); 484 rtw89_write32(rtwdev, R_BE_HALT_H2C, 0); 485 rtw89_write32(rtwdev, R_BE_HALT_C2H, 0); 486 rtw89_write32(rtwdev, R_BE_HALT_H2C_CTRL, 0); 487 rtw89_write32(rtwdev, R_BE_HALT_C2H_CTRL, 0); 488 489 val32 = rtw89_read32(rtwdev, R_BE_HISR0); 490 rtw89_write32(rtwdev, R_BE_HISR0, B_BE_HALT_C2H_INT); 491 rtw89_debug(rtwdev, RTW89_DBG_SER, "HISR0=0x%x\n", val32); 492 493 rtw89_write32_set(rtwdev, R_BE_SYS_CLK_CTRL, B_BE_CPU_CLK_EN); 494 rtw89_write32_clr(rtwdev, R_BE_SYS_CFG5, 495 B_BE_WDT_WAKE_PCIE_EN | B_BE_WDT_WAKE_USB_EN); 496 rtw89_write32_clr(rtwdev, R_BE_WCPU_FW_CTRL, 497 B_BE_WDT_PLT_RST_EN | B_BE_WCPU_ROM_CUT_GET); 498 rtw89_write32(rtwdev, R_BE_SECURE_BOOT_MALLOC_INFO, 0); 499 rtw89_write32_clr(rtwdev, R_BE_GPIO_MUXCFG, B_BE_BOOT_MODE); 500 501 if (chip->chip_id != RTL8922A) 502 rtw89_write32_set(rtwdev, R_BE_WCPU_FW_CTRL, B_BE_HOST_EXIST); 503 504 rtw89_write16_mask(rtwdev, R_BE_BOOT_REASON, B_BE_BOOT_REASON_MASK, boot_reason); 505 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN); 506 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET); 507 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN); 508 509 if (!dlfw) { 510 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 511 if (ret) 512 return ret; 513 } 514 515 return 0; 516 } 517 518 static int rtw89_mac_fwdl_enable_wcpu_be(struct rtw89_dev *rtwdev, 519 u8 boot_reason, bool dlfw, 520 bool include_bb) 521 { 522 set_cpu_en(rtwdev, include_bb); 523 524 return wcpu_on(rtwdev, boot_reason, dlfw); 525 } 526 527 static const u8 fwdl_status_map[] = { 528 [0] = RTW89_FWDL_INITIAL_STATE, 529 [1] = RTW89_FWDL_FWDL_ONGOING, 530 [4] = RTW89_FWDL_CHECKSUM_FAIL, 531 [5] = RTW89_FWDL_SECURITY_FAIL, 532 [6] = RTW89_FWDL_SECURITY_FAIL, 533 [7] = RTW89_FWDL_CV_NOT_MATCH, 534 [8] = RTW89_FWDL_RSVD0, 535 [2] = RTW89_FWDL_WCPU_FWDL_RDY, 536 [3] = RTW89_FWDL_WCPU_FW_INIT_RDY, 537 [9] = RTW89_FWDL_RSVD0, 538 }; 539 540 static u8 fwdl_get_status_be(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 541 { 542 bool check_pass = false; 543 u32 val32; 544 u8 st; 545 546 val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL); 547 548 switch (type) { 549 case RTW89_FWDL_CHECK_WCPU_FWDL_DONE: 550 check_pass = !(val32 & B_BE_WLANCPU_FWDL_EN); 551 break; 552 case RTW89_FWDL_CHECK_DCPU_FWDL_DONE: 553 check_pass = !(val32 & B_BE_DATACPU_FWDL_EN); 554 break; 555 case RTW89_FWDL_CHECK_BB0_FWDL_DONE: 556 check_pass = !(val32 & B_BE_BBMCU0_FWDL_EN); 557 break; 558 case RTW89_FWDL_CHECK_BB1_FWDL_DONE: 559 check_pass = !(val32 & B_BE_BBMCU1_FWDL_EN); 560 break; 561 default: 562 break; 563 } 564 565 if (check_pass) 566 return RTW89_FWDL_WCPU_FW_INIT_RDY; 567 568 st = u32_get_bits(val32, B_BE_WCPU_FWDL_STATUS_MASK); 569 if (st < ARRAY_SIZE(fwdl_status_map)) 570 return fwdl_status_map[st]; 571 572 return st; 573 } 574 575 static int rtw89_fwdl_check_path_ready_be(struct rtw89_dev *rtwdev, 576 bool h2c_or_fwdl) 577 { 578 u32 check = h2c_or_fwdl ? B_BE_H2C_PATH_RDY : B_BE_DLFW_PATH_RDY; 579 u32 val; 580 581 return read_poll_timeout_atomic(rtw89_read32, val, val & check, 582 1, 1000000, false, 583 rtwdev, R_BE_WCPU_FW_CTRL); 584 } 585 586 static int dmac_func_en_be(struct rtw89_dev *rtwdev) 587 { 588 return 0; 589 } 590 591 static int cmac_func_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 592 { 593 u32 reg; 594 595 if (mac_idx > RTW89_MAC_1) 596 return -EINVAL; 597 598 if (mac_idx == RTW89_MAC_0) 599 return 0; 600 601 if (en) { 602 rtw89_write32_set(rtwdev, R_BE_AFE_CTRL1, B_BE_AFE_CTRL1_SET); 603 rtw89_write32_clr(rtwdev, R_BE_SYS_ISO_CTRL_EXTEND, B_BE_R_SYM_ISO_CMAC12PP); 604 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_CMAC1_FEN); 605 606 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx); 607 rtw89_write32_set(rtwdev, reg, B_BE_CK_EN_SET); 608 609 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx); 610 rtw89_write32_set(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET); 611 612 set_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 613 } else { 614 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx); 615 rtw89_write32_clr(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET); 616 617 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx); 618 rtw89_write32_clr(rtwdev, reg, B_BE_CK_EN_SET); 619 620 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_CMAC1_FEN); 621 rtw89_write32_set(rtwdev, R_BE_SYS_ISO_CTRL_EXTEND, B_BE_R_SYM_ISO_CMAC12PP); 622 rtw89_write32_clr(rtwdev, R_BE_AFE_CTRL1, B_BE_AFE_CTRL1_SET); 623 624 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 625 } 626 627 return 0; 628 } 629 630 static int chip_func_en_be(struct rtw89_dev *rtwdev) 631 { 632 return 0; 633 } 634 635 static int sys_init_be(struct rtw89_dev *rtwdev) 636 { 637 int ret; 638 639 ret = dmac_func_en_be(rtwdev); 640 if (ret) 641 return ret; 642 643 ret = cmac_func_en_be(rtwdev, RTW89_MAC_0, true); 644 if (ret) 645 return ret; 646 647 ret = chip_func_en_be(rtwdev); 648 if (ret) 649 return ret; 650 651 return ret; 652 } 653 654 static int sta_sch_init_be(struct rtw89_dev *rtwdev) 655 { 656 u32 p_val; 657 int ret; 658 659 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 660 if (ret) 661 return ret; 662 663 rtw89_write8_set(rtwdev, R_BE_SS_CTRL, B_BE_SS_EN); 664 665 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_BE_SS_INIT_DONE, 666 1, TRXCFG_WAIT_CNT, false, rtwdev, R_BE_SS_CTRL); 667 if (ret) { 668 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 669 return ret; 670 } 671 672 rtw89_write32_set(rtwdev, R_BE_SS_CTRL, B_BE_WARM_INIT); 673 rtw89_write32_clr(rtwdev, R_BE_SS_CTRL, B_BE_BAND_TRIG_EN | B_BE_BAND1_TRIG_EN); 674 675 return 0; 676 } 677 678 static int mpdu_proc_init_be(struct rtw89_dev *rtwdev) 679 { 680 u32 val32; 681 int ret; 682 683 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 684 if (ret) 685 return ret; 686 687 rtw89_write32_set(rtwdev, R_BE_MPDU_PROC, B_BE_APPEND_FCS); 688 rtw89_write32(rtwdev, R_BE_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 689 690 val32 = rtw89_read32(rtwdev, R_BE_HDR_SHCUT_SETTING); 691 val32 |= (B_BE_TX_HW_SEQ_EN | B_BE_TX_HW_ACK_POLICY_EN | B_BE_TX_MAC_MPDU_PROC_EN); 692 val32 &= ~B_BE_TX_ADDR_MLD_TO_LIK; 693 rtw89_write32_set(rtwdev, R_BE_HDR_SHCUT_SETTING, val32); 694 695 rtw89_write32(rtwdev, R_BE_RX_HDRTRNS, TRXCFG_MPDU_PROC_RX_HDR_CONV); 696 697 val32 = rtw89_read32(rtwdev, R_BE_DISP_FWD_WLAN_0); 698 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_DATA_MASK); 699 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_MNG_MASK); 700 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_CTL_MASK); 701 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_1_MASK); 702 rtw89_write32(rtwdev, R_BE_DISP_FWD_WLAN_0, val32); 703 704 return 0; 705 } 706 707 static int sec_eng_init_be(struct rtw89_dev *rtwdev) 708 { 709 u32 val32; 710 int ret; 711 712 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 713 if (ret) 714 return ret; 715 716 val32 = rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL); 717 val32 |= B_BE_CLK_EN_CGCMP | B_BE_CLK_EN_WAPI | B_BE_CLK_EN_WEP_TKIP | 718 B_BE_SEC_TX_ENC | B_BE_SEC_RX_DEC | 719 B_BE_MC_DEC | B_BE_BC_DEC | 720 B_BE_BMC_MGNT_DEC | B_BE_UC_MGNT_DEC | 721 B_BE_SEC_PRE_ENQUE_TX; 722 rtw89_write32(rtwdev, R_BE_SEC_ENG_CTRL, val32); 723 724 rtw89_write32_set(rtwdev, R_BE_SEC_MPDU_PROC, B_BE_APPEND_ICV | B_BE_APPEND_MIC); 725 726 return 0; 727 } 728 729 static int txpktctrl_init_be(struct rtw89_dev *rtwdev) 730 { 731 struct rtw89_mac_dle_rsvd_qt_cfg qt_cfg; 732 u32 val32; 733 int ret; 734 735 ret = rtw89_mac_get_dle_rsvd_qt_cfg(rtwdev, DLE_RSVD_QT_MPDU_INFO, &qt_cfg); 736 if (ret) { 737 rtw89_err(rtwdev, "get dle rsvd qt %d cfg fail %d\n", 738 DLE_RSVD_QT_MPDU_INFO, ret); 739 return ret; 740 } 741 742 val32 = rtw89_read32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG); 743 val32 = u32_replace_bits(val32, qt_cfg.pktid, B_BE_MPDUINFO_PKTID_MASK); 744 val32 = u32_replace_bits(val32, MPDU_INFO_B1_OFST, B_BE_MPDUINFO_B1_BADDR_MASK); 745 val32 |= B_BE_MPDUINFO_FEN; 746 rtw89_write32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG, val32); 747 748 return 0; 749 } 750 751 static int mlo_init_be(struct rtw89_dev *rtwdev) 752 { 753 u32 val32; 754 int ret; 755 756 val32 = rtw89_read32(rtwdev, R_BE_MLO_INIT_CTL); 757 758 val32 |= B_BE_MLO_TABLE_REINIT; 759 rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32); 760 val32 &= ~B_BE_MLO_TABLE_REINIT; 761 rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32); 762 763 ret = read_poll_timeout_atomic(rtw89_read32, val32, 764 val32 & B_BE_MLO_TABLE_INIT_DONE, 765 1, 1000, false, rtwdev, R_BE_MLO_INIT_CTL); 766 if (ret) 767 rtw89_err(rtwdev, "[MLO]%s: MLO init polling timeout\n", __func__); 768 769 rtw89_write32_set(rtwdev, R_BE_SS_CTRL, B_BE_MLO_HW_CHGLINK_EN); 770 rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_ACQCHK_CFG_0, B_BE_R_MACID_ACQ_CHK_EN); 771 772 return ret; 773 } 774 775 static int dmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 776 { 777 int ret; 778 779 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 780 if (ret) { 781 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 782 return ret; 783 } 784 785 ret = rtw89_mac_preload_init(rtwdev, mac_idx, rtwdev->mac.qta_mode); 786 if (ret) { 787 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 788 return ret; 789 } 790 791 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 792 if (ret) { 793 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 794 return ret; 795 } 796 797 ret = sta_sch_init_be(rtwdev); 798 if (ret) { 799 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 800 return ret; 801 } 802 803 ret = mpdu_proc_init_be(rtwdev); 804 if (ret) { 805 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 806 return ret; 807 } 808 809 ret = sec_eng_init_be(rtwdev); 810 if (ret) { 811 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 812 return ret; 813 } 814 815 ret = txpktctrl_init_be(rtwdev); 816 if (ret) { 817 rtw89_err(rtwdev, "[ERR]TX pkt ctrl init %d\n", ret); 818 return ret; 819 } 820 821 ret = mlo_init_be(rtwdev); 822 if (ret) { 823 rtw89_err(rtwdev, "[ERR]MLO init %d\n", ret); 824 return ret; 825 } 826 827 return ret; 828 } 829 830 static int scheduler_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 831 { 832 u32 val32; 833 u32 reg; 834 int ret; 835 836 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 837 if (ret) 838 return ret; 839 840 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_CTN_CHK_CCA_NAV, mac_idx); 841 val32 = B_BE_HE_CTN_CHK_CCA_P20 | B_BE_HE_CTN_CHK_EDCCA_P20 | 842 B_BE_HE_CTN_CHK_CCA_BITMAP | B_BE_HE_CTN_CHK_EDCCA_BITMAP | 843 B_BE_HE_CTN_CHK_NO_GNT_WL | B_BE_HE_CTN_CHK_BASIC_NAV | 844 B_BE_HE_CTN_CHK_INTRA_NAV | B_BE_HE_CTN_CHK_TX_NAV; 845 rtw89_write32(rtwdev, reg, val32); 846 847 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_SIFS_CHK_CCA_NAV, mac_idx); 848 val32 = B_BE_HE_SIFS_CHK_EDCCA_P20 | B_BE_HE_SIFS_CHK_EDCCA_BITMAP | 849 B_BE_HE_SIFS_CHK_NO_GNT_WL; 850 rtw89_write32(rtwdev, reg, val32); 851 852 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_CHK_CCA_NAV, mac_idx); 853 val32 = B_BE_TB_CHK_EDCCA_BITMAP | B_BE_TB_CHK_NO_GNT_WL | B_BE_TB_CHK_BASIC_NAV; 854 rtw89_write32(rtwdev, reg, val32); 855 856 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CCA_CFG_0, mac_idx); 857 rtw89_write32_clr(rtwdev, reg, B_BE_NO_GNT_WL_EN); 858 859 if (is_qta_poh(rtwdev)) { 860 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PREBKF_CFG_0, mac_idx); 861 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_MASK, 862 SCH_PREBKF_24US); 863 864 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_CFG_0, mac_idx); 865 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_NONAC_MASK, 866 SCH_PREBKF_24US); 867 } 868 869 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_EDCA_BCNQ_PARAM, mac_idx); 870 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_CW_MASK, 0x32); 871 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_AIFS_MASK, BCN_IFS_25US); 872 873 return 0; 874 } 875 876 static int addr_cam_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 877 { 878 u32 val32; 879 u16 val16; 880 u32 reg; 881 int ret; 882 883 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 884 if (ret) 885 return ret; 886 887 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx); 888 val32 = rtw89_read32(rtwdev, reg); 889 val32 = u32_replace_bits(val32, ADDR_CAM_SERCH_RANGE, B_BE_ADDR_CAM_RANGE_MASK); 890 val32 |= B_BE_ADDR_CAM_EN; 891 if (mac_idx == RTW89_MAC_0) 892 val32 |= B_BE_ADDR_CAM_CLR; 893 rtw89_write32(rtwdev, reg, val32); 894 895 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx); 896 ret = read_poll_timeout_atomic(rtw89_read16, val16, !(val16 & B_BE_ADDR_CAM_CLR), 897 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 898 if (ret) 899 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 900 901 return ret; 902 } 903 904 static int rtw89_mac_typ_fltr_opt_be(struct rtw89_dev *rtwdev, 905 enum rtw89_machdr_frame_type type, 906 enum rtw89_mac_fwd_target fwd_target, 907 u8 mac_idx) 908 { 909 u32 reg; 910 u32 val; 911 912 switch (fwd_target) { 913 case RTW89_FWD_DONT_CARE: 914 val = RX_FLTR_FRAME_DROP_BE; 915 break; 916 case RTW89_FWD_TO_HOST: 917 case RTW89_FWD_TO_WLAN_CPU: 918 val = RX_FLTR_FRAME_ACCEPT_BE; 919 break; 920 default: 921 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 922 return -EINVAL; 923 } 924 925 switch (type) { 926 case RTW89_MGNT: 927 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MGNT_FLTR, mac_idx); 928 break; 929 case RTW89_CTRL: 930 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTRL_FLTR, mac_idx); 931 break; 932 case RTW89_DATA: 933 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DATA_FLTR, mac_idx); 934 break; 935 default: 936 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 937 return -EINVAL; 938 } 939 rtw89_write32(rtwdev, reg, val); 940 941 return 0; 942 } 943 944 static int rx_fltr_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 945 { 946 u32 reg; 947 u32 val; 948 949 rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_MGNT, RTW89_FWD_TO_HOST, mac_idx); 950 rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_CTRL, RTW89_FWD_TO_HOST, mac_idx); 951 rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_DATA, RTW89_FWD_TO_HOST, mac_idx); 952 953 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_FLTR_OPT, mac_idx); 954 val = B_BE_A_BC_CAM_MATCH | B_BE_A_UC_CAM_MATCH | B_BE_A_MC | 955 B_BE_A_BC | B_BE_A_A1_MATCH | B_BE_SNIFFER_MODE | 956 u32_encode_bits(15, B_BE_UID_FILTER_MASK); 957 rtw89_write32(rtwdev, reg, val); 958 u32p_replace_bits(&rtwdev->hal.rx_fltr, 15, B_BE_UID_FILTER_MASK); 959 960 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx); 961 val = B_BE_HE_SIGB_CRC_CHK | B_BE_VHT_MU_SIGB_CRC_CHK | 962 B_BE_VHT_SU_SIGB_CRC_CHK | B_BE_SIGA_CRC_CHK | 963 B_BE_LSIG_PARITY_CHK_EN | B_BE_CCK_SIG_CHK | B_BE_CCK_CRC_CHK; 964 rtw89_write16(rtwdev, reg, val); 965 966 return 0; 967 } 968 969 static int cca_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 970 { 971 return 0; 972 } 973 974 static int nav_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 975 { 976 u32 val32; 977 u32 reg; 978 979 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_NAV_CTL, mac_idx); 980 981 val32 = rtw89_read32(rtwdev, reg); 982 val32 &= ~B_BE_WMAC_PLCP_UP_NAV_EN; 983 val32 |= B_BE_WMAC_TF_UP_NAV_EN | B_BE_WMAC_NAV_UPPER_EN; 984 val32 = u32_replace_bits(val32, NAV_25MS, B_BE_WMAC_NAV_UPPER_MASK); 985 986 rtw89_write32(rtwdev, reg, val32); 987 988 return 0; 989 } 990 991 static int spatial_reuse_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 992 { 993 u32 reg; 994 int ret; 995 996 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 997 if (ret) 998 return ret; 999 1000 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_SR_CTRL, mac_idx); 1001 rtw89_write8_clr(rtwdev, reg, B_BE_SR_EN | B_BE_SR_CTRL_PLCP_EN); 1002 1003 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BSSID_SRC_CTRL, mac_idx); 1004 rtw89_write8_set(rtwdev, reg, B_BE_PLCP_SRC_EN); 1005 1006 return 0; 1007 } 1008 1009 static int tmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 1010 { 1011 u32 reg; 1012 1013 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_PPDU_CTRL, mac_idx); 1014 rtw89_write32_clr(rtwdev, reg, B_BE_QOSNULL_UPD_MUEDCA_EN); 1015 1016 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMTX_TCR_BE_4, mac_idx); 1017 rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK, 0x12); 1018 rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK, 0xe); 1019 1020 return 0; 1021 } 1022 1023 static int trxptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 1024 { 1025 const struct rtw89_chip_info *chip = rtwdev->chip; 1026 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 1027 struct rtw89_hal *hal = &rtwdev->hal; 1028 u32 val32; 1029 u32 reg; 1030 int ret; 1031 1032 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1033 if (ret) 1034 return ret; 1035 1036 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MAC_LOOPBACK, mac_idx); 1037 val32 = rtw89_read32(rtwdev, reg); 1038 val32 = u32_replace_bits(val32, S_BE_MACLBK_PLCP_DLY_DEF, 1039 B_BE_MACLBK_PLCP_DLY_MASK); 1040 val32 &= ~B_BE_MACLBK_EN; 1041 rtw89_write32(rtwdev, reg, val32); 1042 1043 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_0, mac_idx); 1044 val32 = rtw89_read32(rtwdev, reg); 1045 val32 = u32_replace_bits(val32, WMAC_SPEC_SIFS_CCK, 1046 B_BE_WMAC_SPEC_SIFS_CCK_MASK); 1047 val32 = u32_replace_bits(val32, WMAC_SPEC_SIFS_OFDM_1115E, 1048 B_BE_WMAC_SPEC_SIFS_OFDM_MASK); 1049 rtw89_write32(rtwdev, reg, val32); 1050 1051 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY, mac_idx); 1052 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA); 1053 1054 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE, mac_idx); 1055 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_RESP_HE_CHK_EDCCA); 1056 1057 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC, mac_idx); 1058 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA); 1059 1060 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RXTRIG_TEST_USER_2, mac_idx); 1061 rtw89_write32_set(rtwdev, reg, B_BE_RXTRIG_FCSCHK_EN); 1062 1063 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_1, mac_idx); 1064 val32 = rtw89_read32(rtwdev, reg); 1065 val32 &= B_BE_FTM_RRSR_RATE_EN_MASK | B_BE_WMAC_RESP_DOPPLEB_BE_EN | 1066 B_BE_WMAC_RESP_DCM_EN | B_BE_WMAC_RESP_REF_RATE_MASK; 1067 rtw89_write32(rtwdev, reg, val32); 1068 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 1069 1070 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR1, mac_idx); 1071 val32 = rtw89_read32(rtwdev, reg); 1072 val32 &= B_BE_RRSR_RATE_EN_MASK | B_BE_RRSR_CCK_MASK | B_BE_RSC_MASK; 1073 rtw89_write32(rtwdev, reg, val32); 1074 1075 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR0, mac_idx); 1076 val32 = rtw89_read32(rtwdev, reg); 1077 val32 &= B_BE_RRSR_OFDM_MASK | B_BE_RRSR_HT_MASK | B_BE_RRSR_VHT_MASK | 1078 B_BE_RRSR_HE_MASK; 1079 rtw89_write32(rtwdev, reg, val32); 1080 1081 if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) { 1082 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR1, mac_idx); 1083 rtw89_write32_mask(rtwdev, reg, B_BE_RSC_MASK, 1); 1084 } 1085 1086 return 0; 1087 } 1088 1089 static int rst_bacam_be(struct rtw89_dev *rtwdev) 1090 { 1091 u32 val; 1092 int ret; 1093 1094 rtw89_write32_mask(rtwdev, R_BE_RESPBA_CAM_CTRL, B_BE_BACAM_RST_MASK, 1095 S_BE_BACAM_RST_ALL); 1096 1097 ret = read_poll_timeout_atomic(rtw89_read32_mask, val, val == S_BE_BACAM_RST_DONE, 1098 1, 1000, false, 1099 rtwdev, R_BE_RESPBA_CAM_CTRL, B_BE_BACAM_RST_MASK); 1100 if (ret) 1101 rtw89_err(rtwdev, "[ERR]bacam rst timeout\n"); 1102 1103 return ret; 1104 } 1105 1106 #define PLD_RLS_MAX_PG 127 1107 #define RX_MAX_LEN_UNIT 512 1108 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 1109 1110 static int rmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 1111 { 1112 u32 rx_min_qta, rx_max_len, rx_max_pg; 1113 u16 val16; 1114 u32 reg; 1115 int ret; 1116 1117 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1118 if (ret) 1119 return ret; 1120 1121 if (mac_idx == RTW89_MAC_0) { 1122 ret = rst_bacam_be(rtwdev); 1123 if (ret) 1124 return ret; 1125 } 1126 1127 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DLK_PROTECT_CTL, mac_idx); 1128 val16 = rtw89_read16(rtwdev, reg); 1129 val16 = u16_replace_bits(val16, TRXCFG_RMAC_DATA_TO, B_BE_RX_DLK_DATA_TIME_MASK); 1130 val16 = u16_replace_bits(val16, TRXCFG_RMAC_CCA_TO, B_BE_RX_DLK_CCA_TIME_MASK); 1131 val16 |= B_BE_RX_DLK_RST_EN; 1132 rtw89_write16(rtwdev, reg, val16); 1133 1134 if (mac_idx == RTW89_MAC_0) 1135 rx_min_qta = rtwdev->mac.dle_info.c0_rx_qta; 1136 else 1137 rx_min_qta = rtwdev->mac.dle_info.c1_rx_qta; 1138 rx_max_pg = min_t(u32, rx_min_qta, PLD_RLS_MAX_PG); 1139 rx_max_len = rx_max_pg * rtwdev->mac.dle_info.ple_pg_size; 1140 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 1141 rx_max_len /= RX_MAX_LEN_UNIT; 1142 1143 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_FLTR_OPT, mac_idx); 1144 rtw89_write32_mask(rtwdev, reg, B_BE_RX_MPDU_MAX_LEN_MASK, rx_max_len); 1145 1146 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx); 1147 rtw89_write8_clr(rtwdev, reg, B_BE_VHT_SU_SIGB_CRC_CHK); 1148 1149 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RCR, mac_idx); 1150 rtw89_write16_set(rtwdev, reg, B_BE_BUSY_CHKSN); 1151 1152 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_PLCP_EXT_OPTION_1, mac_idx); 1153 rtw89_write16_set(rtwdev, reg, B_BE_PLCP_SU_PSDU_LEN_SRC); 1154 1155 return 0; 1156 } 1157 1158 static int resp_pktctl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 1159 { 1160 struct rtw89_mac_dle_rsvd_qt_cfg qt_cfg; 1161 enum rtw89_mac_dle_rsvd_qt_type type; 1162 u32 reg; 1163 int ret; 1164 1165 if (mac_idx == RTW89_MAC_1) 1166 type = DLE_RSVD_QT_B1_CSI; 1167 else 1168 type = DLE_RSVD_QT_B0_CSI; 1169 1170 ret = rtw89_mac_get_dle_rsvd_qt_cfg(rtwdev, type, &qt_cfg); 1171 if (ret) { 1172 rtw89_err(rtwdev, "get dle rsvd qt %d cfg fail %d\n", type, ret); 1173 return ret; 1174 } 1175 1176 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RESP_CSI_RESERVED_PAGE, mac_idx); 1177 rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_START_PAGE_MASK, qt_cfg.pktid); 1178 rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_PAGE_NUM_MASK, qt_cfg.pg_num); 1179 1180 return 0; 1181 } 1182 1183 static int cmac_com_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 1184 { 1185 u32 val32; 1186 int ret; 1187 1188 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1189 if (ret) 1190 return ret; 1191 1192 if (mac_idx == RTW89_MAC_0) { 1193 val32 = rtw89_read32(rtwdev, R_BE_TX_SUB_BAND_VALUE); 1194 val32 = u32_replace_bits(val32, S_BE_TXSB_20M_8, B_BE_TXSB_20M_MASK); 1195 val32 = u32_replace_bits(val32, S_BE_TXSB_40M_4, B_BE_TXSB_40M_MASK); 1196 val32 = u32_replace_bits(val32, S_BE_TXSB_80M_2, B_BE_TXSB_80M_MASK); 1197 val32 = u32_replace_bits(val32, S_BE_TXSB_160M_1, B_BE_TXSB_160M_MASK); 1198 rtw89_write32(rtwdev, R_BE_TX_SUB_BAND_VALUE, val32); 1199 } else { 1200 val32 = rtw89_read32(rtwdev, R_BE_TX_SUB_BAND_VALUE_C1); 1201 val32 = u32_replace_bits(val32, S_BE_TXSB_20M_2, B_BE_TXSB_20M_MASK); 1202 val32 = u32_replace_bits(val32, S_BE_TXSB_40M_1, B_BE_TXSB_40M_MASK); 1203 val32 = u32_replace_bits(val32, S_BE_TXSB_80M_0, B_BE_TXSB_80M_MASK); 1204 val32 = u32_replace_bits(val32, S_BE_TXSB_160M_0, B_BE_TXSB_160M_MASK); 1205 rtw89_write32(rtwdev, R_BE_TX_SUB_BAND_VALUE_C1, val32); 1206 } 1207 1208 return 0; 1209 } 1210 1211 static int ptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 1212 { 1213 u32 val32; 1214 u8 val8; 1215 u32 reg; 1216 int ret; 1217 1218 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1219 if (ret) 1220 return ret; 1221 1222 if (is_qta_poh(rtwdev)) { 1223 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SIFS_SETTING, mac_idx); 1224 val32 = rtw89_read32(rtwdev, reg); 1225 val32 = u32_replace_bits(val32, S_AX_CTS2S_TH_1K, 1226 B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK); 1227 val32 = u32_replace_bits(val32, S_AX_CTS2S_TH_SEC_256B, 1228 B_BE_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 1229 val32 |= B_BE_HW_CTS2SELF_EN; 1230 rtw89_write32(rtwdev, reg, val32); 1231 1232 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_FSM_MON, mac_idx); 1233 val32 = rtw89_read32(rtwdev, reg); 1234 val32 = u32_replace_bits(val32, S_AX_PTCL_TO_2MS, 1235 B_BE_PTCL_TX_ARB_TO_THR_MASK); 1236 val32 &= ~B_BE_PTCL_TX_ARB_TO_MODE; 1237 rtw89_write32(rtwdev, reg, val32); 1238 } 1239 1240 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_COMMON_SETTING_0, mac_idx); 1241 val8 = rtw89_read8(rtwdev, reg); 1242 val8 |= B_BE_CMAC_TX_MODE_0 | B_BE_CMAC_TX_MODE_1; 1243 val8 &= ~(B_BE_PTCL_TRIGGER_SS_EN_0 | 1244 B_BE_PTCL_TRIGGER_SS_EN_1 | 1245 B_BE_PTCL_TRIGGER_SS_EN_UL); 1246 rtw89_write8(rtwdev, reg, val8); 1247 1248 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AMPDU_AGG_LIMIT, mac_idx); 1249 rtw89_write32_mask(rtwdev, reg, B_BE_AMPDU_MAX_TIME_MASK, AMPDU_MAX_TIME); 1250 1251 return 0; 1252 } 1253 1254 static int cmac_dma_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 1255 { 1256 u32 val32; 1257 u32 reg; 1258 int ret; 1259 1260 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1261 if (ret) 1262 return ret; 1263 1264 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_CTRL_1, mac_idx); 1265 1266 val32 = rtw89_read32(rtwdev, reg); 1267 val32 = u32_replace_bits(val32, WLCPU_RXCH2_QID, 1268 B_BE_RXDMA_TXRPT_QUEUE_ID_SW_MASK); 1269 val32 = u32_replace_bits(val32, WLCPU_RXCH2_QID, 1270 B_BE_RXDMA_F2PCMDRPT_QUEUE_ID_SW_MASK); 1271 rtw89_write32(rtwdev, reg, val32); 1272 1273 return 0; 1274 } 1275 1276 static int cmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) 1277 { 1278 int ret; 1279 1280 ret = scheduler_init_be(rtwdev, mac_idx); 1281 if (ret) { 1282 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 1283 return ret; 1284 } 1285 1286 ret = addr_cam_init_be(rtwdev, mac_idx); 1287 if (ret) { 1288 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 1289 ret); 1290 return ret; 1291 } 1292 1293 ret = rx_fltr_init_be(rtwdev, mac_idx); 1294 if (ret) { 1295 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 1296 ret); 1297 return ret; 1298 } 1299 1300 ret = cca_ctrl_init_be(rtwdev, mac_idx); 1301 if (ret) { 1302 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 1303 ret); 1304 return ret; 1305 } 1306 1307 ret = nav_ctrl_init_be(rtwdev, mac_idx); 1308 if (ret) { 1309 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 1310 ret); 1311 return ret; 1312 } 1313 1314 ret = spatial_reuse_init_be(rtwdev, mac_idx); 1315 if (ret) { 1316 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 1317 mac_idx, ret); 1318 return ret; 1319 } 1320 1321 ret = tmac_init_be(rtwdev, mac_idx); 1322 if (ret) { 1323 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 1324 return ret; 1325 } 1326 1327 ret = trxptcl_init_be(rtwdev, mac_idx); 1328 if (ret) { 1329 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 1330 return ret; 1331 } 1332 1333 ret = rmac_init_be(rtwdev, mac_idx); 1334 if (ret) { 1335 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 1336 return ret; 1337 } 1338 1339 ret = resp_pktctl_init_be(rtwdev, mac_idx); 1340 if (ret) { 1341 rtw89_err(rtwdev, "[ERR]CMAC%d resp pktctl init %d\n", mac_idx, ret); 1342 return ret; 1343 } 1344 1345 ret = cmac_com_init_be(rtwdev, mac_idx); 1346 if (ret) { 1347 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 1348 return ret; 1349 } 1350 1351 ret = ptcl_init_be(rtwdev, mac_idx); 1352 if (ret) { 1353 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 1354 return ret; 1355 } 1356 1357 ret = cmac_dma_init_be(rtwdev, mac_idx); 1358 if (ret) { 1359 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 1360 return ret; 1361 } 1362 1363 return ret; 1364 } 1365 1366 static int tx_idle_poll_band_be(struct rtw89_dev *rtwdev, u8 mac_idx) 1367 { 1368 u32 reg; 1369 u8 val8; 1370 int ret; 1371 1372 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1373 if (ret) 1374 return ret; 1375 1376 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_TX_CTN_SEL, mac_idx); 1377 1378 ret = read_poll_timeout_atomic(rtw89_read8, val8, !(val8 & B_BE_PTCL_BUSY), 1379 30, 66000, false, rtwdev, reg); 1380 1381 return ret; 1382 } 1383 1384 static int dle_buf_req_be(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 1385 { 1386 u32 val, reg; 1387 int ret; 1388 1389 reg = wd ? R_BE_WD_BUF_REQ : R_BE_PL_BUF_REQ; 1390 val = buf_len; 1391 val |= B_BE_WD_BUF_REQ_EXEC; 1392 rtw89_write32(rtwdev, reg, val); 1393 1394 reg = wd ? R_BE_WD_BUF_STATUS : R_BE_PL_BUF_STATUS; 1395 1396 ret = read_poll_timeout(rtw89_read32, val, val & B_BE_WD_BUF_STAT_DONE, 1397 1, 2000, false, rtwdev, reg); 1398 if (ret) 1399 return ret; 1400 1401 *pkt_id = u32_get_bits(val, B_BE_WD_BUF_STAT_PKTID_MASK); 1402 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 1403 return -ENOENT; 1404 1405 return 0; 1406 } 1407 1408 static int set_cpuio_be(struct rtw89_dev *rtwdev, 1409 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 1410 { 1411 u32 val_op0, val_op1, val_op2, val_op3; 1412 u32 val, cmd_type, reg; 1413 int ret; 1414 1415 cmd_type = ctrl_para->cmd_type; 1416 1417 reg = wd ? R_BE_WD_CPUQ_OP_3 : R_BE_PL_CPUQ_OP_3; 1418 val_op3 = u32_replace_bits(0, ctrl_para->start_pktid, 1419 B_BE_WD_CPUQ_OP_STRT_PKTID_MASK); 1420 val_op3 = u32_replace_bits(val_op3, ctrl_para->end_pktid, 1421 B_BE_WD_CPUQ_OP_END_PKTID_MASK); 1422 rtw89_write32(rtwdev, reg, val_op3); 1423 1424 reg = wd ? R_BE_WD_CPUQ_OP_1 : R_BE_PL_CPUQ_OP_1; 1425 val_op1 = u32_replace_bits(0, ctrl_para->src_pid, 1426 B_BE_WD_CPUQ_OP_SRC_PID_MASK); 1427 val_op1 = u32_replace_bits(val_op1, ctrl_para->src_qid, 1428 B_BE_WD_CPUQ_OP_SRC_QID_MASK); 1429 val_op1 = u32_replace_bits(val_op1, ctrl_para->macid, 1430 B_BE_WD_CPUQ_OP_SRC_MACID_MASK); 1431 rtw89_write32(rtwdev, reg, val_op1); 1432 1433 reg = wd ? R_BE_WD_CPUQ_OP_2 : R_BE_PL_CPUQ_OP_2; 1434 val_op2 = u32_replace_bits(0, ctrl_para->dst_pid, 1435 B_BE_WD_CPUQ_OP_DST_PID_MASK); 1436 val_op2 = u32_replace_bits(val_op2, ctrl_para->dst_qid, 1437 B_BE_WD_CPUQ_OP_DST_QID_MASK); 1438 val_op2 = u32_replace_bits(val_op2, ctrl_para->macid, 1439 B_BE_WD_CPUQ_OP_DST_MACID_MASK); 1440 rtw89_write32(rtwdev, reg, val_op2); 1441 1442 reg = wd ? R_BE_WD_CPUQ_OP_0 : R_BE_PL_CPUQ_OP_0; 1443 val_op0 = u32_replace_bits(0, cmd_type, 1444 B_BE_WD_CPUQ_OP_CMD_TYPE_MASK); 1445 val_op0 = u32_replace_bits(val_op0, ctrl_para->pkt_num, 1446 B_BE_WD_CPUQ_OP_PKTNUM_MASK); 1447 val_op0 |= B_BE_WD_CPUQ_OP_EXEC; 1448 rtw89_write32(rtwdev, reg, val_op0); 1449 1450 reg = wd ? R_BE_WD_CPUQ_OP_STATUS : R_BE_PL_CPUQ_OP_STATUS; 1451 1452 ret = read_poll_timeout(rtw89_read32, val, val & B_BE_WD_CPUQ_OP_STAT_DONE, 1453 1, 2000, false, rtwdev, reg); 1454 if (ret) { 1455 rtw89_err(rtwdev, "[ERR]set cpuio wd timeout\n"); 1456 rtw89_err(rtwdev, "[ERR]op_0=0x%X, op_1=0x%X, op_2=0x%X\n", 1457 val_op0, val_op1, val_op2); 1458 return ret; 1459 } 1460 1461 if (cmd_type == CPUIO_OP_CMD_GET_NEXT_PID || 1462 cmd_type == CPUIO_OP_CMD_GET_1ST_PID) 1463 ctrl_para->pktid = u32_get_bits(val, B_BE_WD_CPUQ_OP_PKTID_MASK); 1464 1465 return 0; 1466 } 1467 1468 static int dle_upd_qta_aval_page_be(struct rtw89_dev *rtwdev, 1469 enum rtw89_mac_dle_ctrl_type type, 1470 enum rtw89_mac_dle_ple_quota_id quota_id) 1471 { 1472 u32 val; 1473 1474 if (type == DLE_CTRL_TYPE_WDE) { 1475 rtw89_write32_mask(rtwdev, R_BE_WDE_BUFMGN_CTL, 1476 B_BE_WDE_AVAL_UPD_QTAID_MASK, quota_id); 1477 rtw89_write32_set(rtwdev, R_BE_WDE_BUFMGN_CTL, B_BE_WDE_AVAL_UPD_REQ); 1478 1479 return read_poll_timeout(rtw89_read32, val, 1480 !(val & B_BE_WDE_AVAL_UPD_REQ), 1481 1, 2000, false, rtwdev, R_BE_WDE_BUFMGN_CTL); 1482 } else if (type == DLE_CTRL_TYPE_PLE) { 1483 rtw89_write32_mask(rtwdev, R_BE_PLE_BUFMGN_CTL, 1484 B_BE_PLE_AVAL_UPD_QTAID_MASK, quota_id); 1485 rtw89_write32_set(rtwdev, R_BE_PLE_BUFMGN_CTL, B_BE_PLE_AVAL_UPD_REQ); 1486 1487 return read_poll_timeout(rtw89_read32, val, 1488 !(val & B_BE_PLE_AVAL_UPD_REQ), 1489 1, 2000, false, rtwdev, R_BE_PLE_BUFMGN_CTL); 1490 } 1491 1492 rtw89_warn(rtwdev, "%s wrong type %d\n", __func__, type); 1493 return -EINVAL; 1494 } 1495 1496 static int dle_quota_change_be(struct rtw89_dev *rtwdev, bool band1_en) 1497 { 1498 int ret; 1499 1500 if (band1_en) { 1501 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE, 1502 PLE_QTAID_B0_TXPL); 1503 if (ret) { 1504 rtw89_err(rtwdev, "update PLE B0 TX avail page fail %d\n", ret); 1505 return ret; 1506 } 1507 1508 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE, 1509 PLE_QTAID_CMAC0_RX); 1510 if (ret) { 1511 rtw89_err(rtwdev, "update PLE CMAC0 RX avail page fail %d\n", ret); 1512 return ret; 1513 } 1514 } else { 1515 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE, 1516 PLE_QTAID_B1_TXPL); 1517 if (ret) { 1518 rtw89_err(rtwdev, "update PLE B1 TX avail page fail %d\n", ret); 1519 return ret; 1520 } 1521 1522 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE, 1523 PLE_QTAID_CMAC1_RX); 1524 if (ret) { 1525 rtw89_err(rtwdev, "update PLE CMAC1 RX avail page fail %d\n", ret); 1526 return ret; 1527 } 1528 } 1529 1530 return 0; 1531 } 1532 1533 static int preload_init_be(struct rtw89_dev *rtwdev, u8 mac_idx, 1534 enum rtw89_qta_mode mode) 1535 { 1536 u32 max_preld_size, min_rsvd_size; 1537 u32 val32; 1538 u32 reg; 1539 1540 max_preld_size = mac_idx == RTW89_MAC_0 ? 1541 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM; 1542 max_preld_size *= PRELD_AMSDU_SIZE; 1543 1544 reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG0 : 1545 R_BE_TXPKTCTL_B1_PRELD_CFG0; 1546 val32 = rtw89_read32(rtwdev, reg); 1547 val32 = u32_replace_bits(val32, max_preld_size, B_BE_B0_PRELD_USEMAXSZ_MASK); 1548 val32 |= B_BE_B0_PRELD_FEN; 1549 rtw89_write32(rtwdev, reg, val32); 1550 1551 min_rsvd_size = PRELD_AMSDU_SIZE; 1552 reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG1 : 1553 R_BE_TXPKTCTL_B1_PRELD_CFG1; 1554 val32 = rtw89_read32(rtwdev, reg); 1555 val32 = u32_replace_bits(val32, PRELD_NEXT_WND, B_BE_B0_PRELD_NXT_TXENDWIN_MASK); 1556 val32 = u32_replace_bits(val32, min_rsvd_size, B_BE_B0_PRELD_NXT_RSVMINSZ_MASK); 1557 rtw89_write32(rtwdev, reg, val32); 1558 1559 return 0; 1560 } 1561 1562 static int dbcc_bb_ctrl_be(struct rtw89_dev *rtwdev, bool bb1_en) 1563 { 1564 u32 set = B_BE_FEN_BB1PLAT_RSTB | B_BE_FEN_BB1_IP_RSTN; 1565 1566 if (bb1_en) 1567 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, set); 1568 else 1569 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, set); 1570 1571 return 0; 1572 } 1573 1574 static int enable_imr_be(struct rtw89_dev *rtwdev, u8 mac_idx, 1575 enum rtw89_mac_hwmod_sel sel) 1576 { 1577 const struct rtw89_chip_info *chip = rtwdev->chip; 1578 const struct rtw89_imr_table *table; 1579 const struct rtw89_reg_imr *reg; 1580 u32 addr; 1581 u32 val; 1582 int i; 1583 1584 if (sel == RTW89_DMAC_SEL) 1585 table = chip->imr_dmac_table; 1586 else if (sel == RTW89_CMAC_SEL) 1587 table = chip->imr_cmac_table; 1588 else 1589 return -EINVAL; 1590 1591 for (i = 0; i < table->n_regs; i++) { 1592 reg = &table->regs[i]; 1593 addr = rtw89_mac_reg_by_idx(rtwdev, reg->addr, mac_idx); 1594 1595 val = rtw89_read32(rtwdev, addr); 1596 val &= ~reg->clr; 1597 val |= reg->set; 1598 rtw89_write32(rtwdev, addr, val); 1599 } 1600 1601 return 0; 1602 } 1603 1604 static void err_imr_ctrl_be(struct rtw89_dev *rtwdev, bool en) 1605 { 1606 u32 v32_dmac = en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS; 1607 u32 v32_cmac0 = en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS; 1608 u32 v32_cmac1 = en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS; 1609 1610 v32_dmac &= ~B_BE_DMAC_NOTX_ERR_INT_EN; 1611 1612 rtw89_write32(rtwdev, R_BE_DMAC_ERR_IMR, v32_dmac); 1613 rtw89_write32(rtwdev, R_BE_CMAC_ERR_IMR, v32_cmac0); 1614 1615 if (rtwdev->dbcc_en) 1616 rtw89_write32(rtwdev, R_BE_CMAC_ERR_IMR_C1, v32_cmac1); 1617 } 1618 1619 static int band1_enable_be(struct rtw89_dev *rtwdev) 1620 { 1621 int ret; 1622 1623 ret = tx_idle_poll_band_be(rtwdev, RTW89_MAC_0); 1624 if (ret) { 1625 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 1626 return ret; 1627 } 1628 1629 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 1630 if (ret) { 1631 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 1632 return ret; 1633 } 1634 1635 ret = preload_init_be(rtwdev, RTW89_MAC_1, rtwdev->mac.qta_mode); 1636 if (ret) { 1637 rtw89_err(rtwdev, "[ERR]preload init B1 %d\n", ret); 1638 return ret; 1639 } 1640 1641 ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, true); 1642 if (ret) { 1643 rtw89_err(rtwdev, "[ERR]CMAC%d func en %d\n", RTW89_MAC_1, ret); 1644 return ret; 1645 } 1646 1647 ret = cmac_init_be(rtwdev, RTW89_MAC_1); 1648 if (ret) { 1649 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", RTW89_MAC_1, ret); 1650 return ret; 1651 } 1652 1653 ret = dbcc_bb_ctrl_be(rtwdev, true); 1654 if (ret) { 1655 rtw89_err(rtwdev, "[ERR]enable bb 1 %d\n", ret); 1656 return ret; 1657 } 1658 1659 ret = enable_imr_be(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 1660 if (ret) { 1661 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 1662 return ret; 1663 } 1664 1665 return 0; 1666 } 1667 1668 static int band1_disable_be(struct rtw89_dev *rtwdev) 1669 { 1670 int ret; 1671 1672 ret = dbcc_bb_ctrl_be(rtwdev, false); 1673 if (ret) { 1674 rtw89_err(rtwdev, "[ERR]disable bb 1 %d\n", ret); 1675 return ret; 1676 } 1677 1678 ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, false); 1679 if (ret) { 1680 rtw89_err(rtwdev, "[ERR]CMAC%d func dis %d\n", RTW89_MAC_1, ret); 1681 return ret; 1682 } 1683 1684 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, false); 1685 if (ret) { 1686 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 1687 return ret; 1688 } 1689 1690 return 0; 1691 } 1692 1693 static int dbcc_enable_be(struct rtw89_dev *rtwdev, bool enable) 1694 { 1695 int ret; 1696 1697 if (enable) { 1698 ret = band1_enable_be(rtwdev); 1699 if (ret) { 1700 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 1701 return ret; 1702 } 1703 1704 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) { 1705 ret = rtw89_fw_h2c_notify_dbcc(rtwdev, true); 1706 if (ret) { 1707 rtw89_err(rtwdev, "%s:[ERR] notify dbcc1 fail %d\n", 1708 __func__, ret); 1709 return ret; 1710 } 1711 } 1712 } else { 1713 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) { 1714 ret = rtw89_fw_h2c_notify_dbcc(rtwdev, false); 1715 if (ret) { 1716 rtw89_err(rtwdev, "%s:[ERR] notify dbcc1 fail %d\n", 1717 __func__, ret); 1718 return ret; 1719 } 1720 } 1721 1722 ret = band1_disable_be(rtwdev); 1723 if (ret) { 1724 rtw89_err(rtwdev, "[ERR] band1_disable %d\n", ret); 1725 return ret; 1726 } 1727 } 1728 1729 return 0; 1730 } 1731 1732 static int set_host_rpr_be(struct rtw89_dev *rtwdev) 1733 { 1734 u32 val32; 1735 u32 mode; 1736 u32 fltr; 1737 bool poh; 1738 1739 poh = is_qta_poh(rtwdev); 1740 1741 if (poh) { 1742 mode = RTW89_RPR_MODE_POH; 1743 fltr = S_BE_WDRLS_FLTR_TXOK | S_BE_WDRLS_FLTR_RTYLMT | 1744 S_BE_WDRLS_FLTR_LIFTIM | S_BE_WDRLS_FLTR_MACID; 1745 } else { 1746 mode = RTW89_RPR_MODE_STF; 1747 fltr = 0; 1748 } 1749 1750 rtw89_write32_mask(rtwdev, R_BE_WDRLS_CFG, B_BE_WDRLS_MODE_MASK, mode); 1751 1752 val32 = rtw89_read32(rtwdev, R_BE_RLSRPT0_CFG1); 1753 val32 = u32_replace_bits(val32, fltr, B_BE_RLSRPT0_FLTR_MAP_MASK); 1754 val32 = u32_replace_bits(val32, 30, B_BE_RLSRPT0_AGGNUM_MASK); 1755 val32 = u32_replace_bits(val32, 255, B_BE_RLSRPT0_TO_MASK); 1756 rtw89_write32(rtwdev, R_BE_RLSRPT0_CFG1, val32); 1757 1758 return 0; 1759 } 1760 1761 static int trx_init_be(struct rtw89_dev *rtwdev) 1762 { 1763 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1764 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 1765 int ret; 1766 1767 ret = dmac_init_be(rtwdev, 0); 1768 if (ret) { 1769 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 1770 return ret; 1771 } 1772 1773 ret = cmac_init_be(rtwdev, 0); 1774 if (ret) { 1775 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 1776 return ret; 1777 } 1778 1779 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 1780 ret = dbcc_enable_be(rtwdev, true); 1781 if (ret) { 1782 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 1783 return ret; 1784 } 1785 } 1786 1787 ret = enable_imr_be(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1788 if (ret) { 1789 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 1790 return ret; 1791 } 1792 1793 ret = enable_imr_be(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 1794 if (ret) { 1795 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 1796 return ret; 1797 } 1798 1799 err_imr_ctrl_be(rtwdev, true); 1800 1801 ret = set_host_rpr_be(rtwdev); 1802 if (ret) { 1803 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 1804 return ret; 1805 } 1806 1807 if (chip_id == RTL8922A) 1808 rtw89_write32_clr(rtwdev, R_BE_RSP_CHK_SIG, 1809 B_BE_RSP_STATIC_RTS_CHK_SERV_BW_EN); 1810 1811 return 0; 1812 } 1813 1814 int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev, 1815 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 1816 { 1817 u32 val = 0; 1818 1819 if (gnt_cfg->band[0].gnt_bt) 1820 val |= B_BE_GNT_BT_BB0_VAL | B_BE_GNT_BT_RX_BB0_VAL | 1821 B_BE_GNT_BT_TX_BB0_VAL; 1822 1823 if (gnt_cfg->band[0].gnt_bt_sw_en) 1824 val |= B_BE_GNT_BT_BB0_SWCTRL | B_BE_GNT_BT_RX_BB0_SWCTRL | 1825 B_BE_GNT_BT_TX_BB0_SWCTRL; 1826 1827 if (gnt_cfg->band[0].gnt_wl) 1828 val |= B_BE_GNT_WL_BB0_VAL | B_BE_GNT_WL_RX_VAL | 1829 B_BE_GNT_WL_TX_VAL | B_BE_GNT_WL_BB_PWR_VAL; 1830 1831 if (gnt_cfg->band[0].gnt_wl_sw_en) 1832 val |= B_BE_GNT_WL_BB0_SWCTRL | B_BE_GNT_WL_RX_SWCTRL | 1833 B_BE_GNT_WL_TX_SWCTRL | B_BE_GNT_WL_BB_PWR_SWCTRL; 1834 1835 if (gnt_cfg->band[1].gnt_bt) 1836 val |= B_BE_GNT_BT_BB1_VAL | B_BE_GNT_BT_RX_BB1_VAL | 1837 B_BE_GNT_BT_TX_BB1_VAL; 1838 1839 if (gnt_cfg->band[1].gnt_bt_sw_en) 1840 val |= B_BE_GNT_BT_BB1_SWCTRL | B_BE_GNT_BT_RX_BB1_SWCTRL | 1841 B_BE_GNT_BT_TX_BB1_SWCTRL; 1842 1843 if (gnt_cfg->band[1].gnt_wl) 1844 val |= B_BE_GNT_WL_BB1_VAL | B_BE_GNT_WL_RX_VAL | 1845 B_BE_GNT_WL_TX_VAL | B_BE_GNT_WL_BB_PWR_VAL; 1846 1847 if (gnt_cfg->band[1].gnt_wl_sw_en) 1848 val |= B_BE_GNT_WL_BB1_SWCTRL | B_BE_GNT_WL_RX_SWCTRL | 1849 B_BE_GNT_WL_TX_SWCTRL | B_BE_GNT_WL_BB_PWR_SWCTRL; 1850 1851 if (gnt_cfg->bt[0].wlan_act_en) 1852 val |= B_BE_WL_ACT_SWCTRL; 1853 if (gnt_cfg->bt[0].wlan_act) 1854 val |= B_BE_WL_ACT_VAL; 1855 if (gnt_cfg->bt[1].wlan_act_en) 1856 val |= B_BE_WL_ACT2_SWCTRL; 1857 if (gnt_cfg->bt[1].wlan_act) 1858 val |= B_BE_WL_ACT2_VAL; 1859 1860 rtw89_write32(rtwdev, R_BE_GNT_SW_CTRL, val); 1861 1862 return 0; 1863 } 1864 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v2); 1865 1866 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl) 1867 { 1868 struct rtw89_btc *btc = &rtwdev->btc; 1869 struct rtw89_btc_dm *dm = &btc->dm; 1870 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 1871 struct rtw89_mac_ax_wl_act *gbt = dm->gnt.bt; 1872 int i; 1873 1874 if (wl) 1875 return 0; 1876 1877 for (i = 0; i < RTW89_PHY_NUM; i++) { 1878 g[i].gnt_bt_sw_en = 1; 1879 g[i].gnt_bt = 1; 1880 g[i].gnt_wl_sw_en = 1; 1881 g[i].gnt_wl = 0; 1882 gbt[i].wlan_act = 1; 1883 gbt[i].wlan_act_en = 0; 1884 } 1885 1886 return rtw89_mac_cfg_gnt_v2(rtwdev, &dm->gnt); 1887 } 1888 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v2); 1889 1890 static 1891 int rtw89_mac_cfg_plt_be(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 1892 { 1893 u32 reg; 1894 u16 val; 1895 int ret; 1896 1897 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 1898 if (ret) 1899 return ret; 1900 1901 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, plt->band); 1902 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_TX_PLT_GNT_LTE_RX : 0) | 1903 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_TX_PLT_GNT_BT_TX : 0) | 1904 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_TX_PLT_GNT_BT_RX : 0) | 1905 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_TX_PLT_GNT_WL : 0) | 1906 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_RX_PLT_GNT_LTE_RX : 0) | 1907 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_RX_PLT_GNT_BT_TX : 0) | 1908 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_RX_PLT_GNT_BT_RX : 0) | 1909 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_RX_PLT_GNT_WL : 0) | 1910 B_BE_PLT_EN; 1911 rtw89_write16(rtwdev, reg, val); 1912 1913 return 0; 1914 } 1915 1916 static u16 rtw89_mac_get_plt_cnt_be(struct rtw89_dev *rtwdev, u8 band) 1917 { 1918 u32 reg; 1919 u16 cnt; 1920 1921 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, band); 1922 cnt = rtw89_read32_mask(rtwdev, reg, B_BE_BT_PLT_PKT_CNT_MASK); 1923 rtw89_write16_set(rtwdev, reg, B_BE_BT_PLT_RST); 1924 1925 return cnt; 1926 } 1927 1928 static int rtw89_set_hw_sch_tx_en_v2(struct rtw89_dev *rtwdev, u8 mac_idx, 1929 u32 tx_en, u32 tx_en_mask) 1930 { 1931 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_DRV_TXEN, mac_idx); 1932 u32 val; 1933 int ret; 1934 1935 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1936 if (ret) 1937 return ret; 1938 1939 val = rtw89_read32(rtwdev, reg); 1940 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 1941 rtw89_write32(rtwdev, reg, val); 1942 1943 return 0; 1944 } 1945 1946 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, 1947 u32 *tx_en, enum rtw89_sch_tx_sel sel) 1948 { 1949 int ret; 1950 1951 *tx_en = rtw89_read32(rtwdev, 1952 rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_DRV_TXEN, mac_idx)); 1953 1954 switch (sel) { 1955 case RTW89_SCH_TX_SEL_ALL: 1956 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, 0, 1957 B_BE_CTN_TXEN_ALL_MASK); 1958 if (ret) 1959 return ret; 1960 break; 1961 case RTW89_SCH_TX_SEL_HIQ: 1962 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, 1963 0, B_BE_CTN_TXEN_HGQ); 1964 if (ret) 1965 return ret; 1966 break; 1967 case RTW89_SCH_TX_SEL_MG0: 1968 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, 1969 0, B_BE_CTN_TXEN_MGQ); 1970 if (ret) 1971 return ret; 1972 break; 1973 case RTW89_SCH_TX_SEL_MACID: 1974 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, 0, 1975 B_BE_CTN_TXEN_ALL_MASK); 1976 if (ret) 1977 return ret; 1978 break; 1979 default: 1980 return 0; 1981 } 1982 1983 return 0; 1984 } 1985 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v2); 1986 1987 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 1988 { 1989 int ret; 1990 1991 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, tx_en, 1992 B_BE_CTN_TXEN_ALL_MASK); 1993 if (ret) 1994 return ret; 1995 1996 return 0; 1997 } 1998 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v2); 1999 2000 void rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 2001 { 2002 u32 reg, val; 2003 2004 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RCR, mac_idx); 2005 val = enable ? MAC_AX_PHY_RPT_SIZE_8 : MAC_AX_PHY_RPT_SIZE_0; 2006 rtw89_write32_mask(rtwdev, reg, B_BE_PHY_RPT_SZ_MASK, val); 2007 rtw89_write32_mask(rtwdev, reg, B_BE_HDR_CNV_SZ_MASK, MAC_AX_HDR_CNV_SIZE_0); 2008 2009 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DRV_INFO_OPTION, mac_idx); 2010 rtw89_write32_mask(rtwdev, reg, B_BE_DRV_INFO_PHYRPT_EN, enable); 2011 } 2012 EXPORT_SYMBOL(rtw89_mac_cfg_phy_rpt_be); 2013 2014 static 2015 int rtw89_mac_cfg_ppdu_status_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 2016 { 2017 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PPDU_STAT, mac_idx); 2018 int ret; 2019 2020 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2021 if (ret) 2022 return ret; 2023 2024 if (!enable) { 2025 rtw89_write32_clr(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN); 2026 return 0; 2027 } 2028 2029 rtw89_write32_mask(rtwdev, R_BE_HW_PPDU_STATUS, B_BE_FWD_PPDU_STAT_MASK, 3); 2030 rtw89_write32(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN | 2031 B_BE_APP_RX_CNT_RPT | B_BE_APP_PLCP_HDR_RPT | 2032 B_BE_PPDU_STAT_RPT_CRC32 | B_BE_PPDU_STAT_RPT_DMA); 2033 2034 return 0; 2035 } 2036 2037 static bool rtw89_mac_get_txpwr_cr_be(struct rtw89_dev *rtwdev, 2038 enum rtw89_phy_idx phy_idx, 2039 u32 reg_base, u32 *cr) 2040 { 2041 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 2042 int ret; 2043 2044 ret = rtw89_mac_check_mac_en(rtwdev, (enum rtw89_mac_idx)phy_idx, 2045 RTW89_CMAC_SEL); 2046 if (ret) { 2047 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) 2048 return false; 2049 2050 rtw89_err(rtwdev, "[TXPWR] check mac enable failed\n"); 2051 return false; 2052 } 2053 2054 if (reg_base < R_BE_PWR_MODULE || reg_base > R_BE_CMAC_FUNC_EN_C1) { 2055 rtw89_err(rtwdev, "[TXPWR] reg_base=0x%x exceed txpwr cr\n", 2056 reg_base); 2057 return false; 2058 } 2059 2060 *cr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 2061 2062 if (*cr >= CMAC1_START_ADDR_BE && *cr <= CMAC1_END_ADDR_BE) { 2063 if (mode == RTW89_QTA_SCC) { 2064 rtw89_err(rtwdev, 2065 "[TXPWR] addr=0x%x but hw not enable\n", 2066 *cr); 2067 return false; 2068 } 2069 } 2070 2071 return true; 2072 } 2073 2074 static int rtw89_mac_init_bfee_be(struct rtw89_dev *rtwdev, u8 mac_idx) 2075 { 2076 u32 reg; 2077 u32 val; 2078 int ret; 2079 2080 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2081 if (ret) 2082 return ret; 2083 2084 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 2085 2086 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 2087 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL | 2088 B_BE_BFMEE_USE_NSTS | 2089 B_BE_BFMEE_CSI_GID_SEL | 2090 B_BE_BFMEE_CSI_FORCE_RETE_EN); 2091 rtw89_write32_mask(rtwdev, reg, B_BE_BFMEE_CSI_RSC_MASK, CSI_RX_BW_CFG); 2092 2093 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CSIRPT_OPTION, mac_idx); 2094 rtw89_write32_set(rtwdev, reg, B_BE_CSIPRT_VHTSU_AID_EN | 2095 B_BE_CSIPRT_HESU_AID_EN | 2096 B_BE_CSIPRT_EHTSU_AID_EN); 2097 2098 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RRSC, mac_idx); 2099 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP_BE); 2100 2101 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 2102 rtw89_write32_mask(rtwdev, reg, B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK, 2103 CSI_RRSC_BITMAP_CFG); 2104 2105 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RATE, mac_idx); 2106 val = u32_encode_bits(CSI_INIT_RATE_HT, B_BE_BFMEE_HT_CSI_RATE_MASK) | 2107 u32_encode_bits(CSI_INIT_RATE_VHT, B_BE_BFMEE_VHT_CSI_RATE_MASK) | 2108 u32_encode_bits(CSI_INIT_RATE_HE, B_BE_BFMEE_HE_CSI_RATE_MASK) | 2109 u32_encode_bits(CSI_INIT_RATE_EHT, B_BE_BFMEE_EHT_CSI_RATE_MASK); 2110 2111 rtw89_write32(rtwdev, reg, val); 2112 2113 return 0; 2114 } 2115 2116 static int rtw89_mac_set_csi_para_reg_be(struct rtw89_dev *rtwdev, 2117 struct rtw89_vif_link *rtwvif_link, 2118 struct rtw89_sta_link *rtwsta_link) 2119 { 2120 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 2121 struct ieee80211_link_sta *link_sta; 2122 u8 mac_idx = rtwvif_link->mac_idx; 2123 u8 port_sel = rtwvif_link->port; 2124 u8 sound_dim = 3, t; 2125 u8 *phy_cap; 2126 u32 reg; 2127 u16 val; 2128 int ret; 2129 2130 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2131 if (ret) 2132 return ret; 2133 2134 rcu_read_lock(); 2135 2136 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 2137 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; 2138 2139 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 2140 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 2141 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 2142 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 2143 t = u8_get_bits(phy_cap[5], 2144 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK); 2145 sound_dim = min(sound_dim, t); 2146 } 2147 2148 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 2149 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 2150 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 2151 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 2152 t = u32_get_bits(link_sta->vht_cap.cap, 2153 IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK); 2154 sound_dim = min(sound_dim, t); 2155 } 2156 2157 nc = min(nc, sound_dim); 2158 nr = min(nr, sound_dim); 2159 2160 rcu_read_unlock(); 2161 2162 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 2163 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL); 2164 2165 val = u16_encode_bits(nc, B_BE_BFMEE_CSIINFO0_NC_MASK) | 2166 u16_encode_bits(nr, B_BE_BFMEE_CSIINFO0_NR_MASK) | 2167 u16_encode_bits(ng, B_BE_BFMEE_CSIINFO0_NG_MASK) | 2168 u16_encode_bits(cb, B_BE_BFMEE_CSIINFO0_CB_MASK) | 2169 u16_encode_bits(cs, B_BE_BFMEE_CSIINFO0_CS_MASK) | 2170 u16_encode_bits(ldpc_en, B_BE_BFMEE_CSIINFO0_LDPC_EN) | 2171 u16_encode_bits(stbc_en, B_BE_BFMEE_CSIINFO0_STBC_EN); 2172 2173 if (port_sel == 0) 2174 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, 2175 mac_idx); 2176 else 2177 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_1, 2178 mac_idx); 2179 2180 rtw89_write16(rtwdev, reg, val); 2181 2182 return 0; 2183 } 2184 2185 static int rtw89_mac_csi_rrsc_be(struct rtw89_dev *rtwdev, 2186 struct rtw89_vif_link *rtwvif_link, 2187 struct rtw89_sta_link *rtwsta_link) 2188 { 2189 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 2190 struct ieee80211_link_sta *link_sta; 2191 u8 mac_idx = rtwvif_link->mac_idx; 2192 int ret; 2193 u32 reg; 2194 2195 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2196 if (ret) 2197 return ret; 2198 2199 rcu_read_lock(); 2200 2201 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 2202 2203 if (link_sta->he_cap.has_he) { 2204 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 2205 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 2206 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 2207 } 2208 if (link_sta->vht_cap.vht_supported) { 2209 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 2210 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 2211 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 2212 } 2213 if (link_sta->ht_cap.ht_supported) { 2214 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 2215 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 2216 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 2217 } 2218 2219 rcu_read_unlock(); 2220 2221 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 2222 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL); 2223 rtw89_write32_clr(rtwdev, reg, B_BE_BFMEE_CSI_FORCE_RETE_EN); 2224 2225 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RRSC, mac_idx); 2226 rtw89_write32(rtwdev, reg, rrsc); 2227 2228 return 0; 2229 } 2230 2231 static void rtw89_mac_bf_assoc_be(struct rtw89_dev *rtwdev, 2232 struct rtw89_vif_link *rtwvif_link, 2233 struct rtw89_sta_link *rtwsta_link) 2234 { 2235 struct ieee80211_link_sta *link_sta; 2236 bool has_beamformer_cap; 2237 2238 rcu_read_lock(); 2239 2240 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 2241 has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta); 2242 2243 rcu_read_unlock(); 2244 2245 if (has_beamformer_cap) { 2246 rtw89_debug(rtwdev, RTW89_DBG_BF, 2247 "initialize bfee for new association\n"); 2248 rtw89_mac_init_bfee_be(rtwdev, rtwvif_link->mac_idx); 2249 rtw89_mac_set_csi_para_reg_be(rtwdev, rtwvif_link, rtwsta_link); 2250 rtw89_mac_csi_rrsc_be(rtwdev, rtwvif_link, rtwsta_link); 2251 } 2252 } 2253 2254 static void dump_err_status_dispatcher_be(struct rtw89_dev *rtwdev) 2255 { 2256 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x ", 2257 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 2258 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 2259 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 2260 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x ", 2261 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 2262 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 2263 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 2264 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x ", 2265 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 2266 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 2267 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 2268 } 2269 2270 static void rtw89_mac_dump_qta_lost_be(struct rtw89_dev *rtwdev) 2271 { 2272 struct rtw89_mac_dle_dfi_qempty qempty; 2273 struct rtw89_mac_dle_dfi_quota quota; 2274 struct rtw89_mac_dle_dfi_ctrl ctrl; 2275 u32 val, not_empty, i; 2276 int ret; 2277 2278 qempty.dle_type = DLE_CTRL_TYPE_PLE; 2279 qempty.grpsel = 0; 2280 qempty.qempty = ~(u32)0; 2281 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 2282 if (ret) 2283 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 2284 else 2285 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 2286 2287 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 2288 if (!(not_empty & BIT(0))) 2289 continue; 2290 ctrl.type = DLE_CTRL_TYPE_PLE; 2291 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 2292 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 2293 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 2294 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 2295 if (ret) 2296 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 2297 else 2298 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 2299 u32_get_bits(ctrl.out_data, 2300 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 2301 } 2302 2303 quota.dle_type = DLE_CTRL_TYPE_PLE; 2304 quota.qtaid = 6; 2305 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 2306 if (ret) 2307 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 2308 else 2309 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 2310 quota.rsv_pgnum, quota.use_pgnum); 2311 2312 val = rtw89_read32(rtwdev, R_BE_PLE_QTA6_CFG); 2313 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 2314 u32_get_bits(val, B_BE_PLE_Q6_MIN_SIZE_MASK)); 2315 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 2316 u32_get_bits(val, B_BE_PLE_Q6_MAX_SIZE_MASK)); 2317 val = rtw89_read32(rtwdev, R_BE_RX_FLTR_OPT); 2318 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_BE_RX_MPDU_MAX_LEN=0x%x\n", 2319 u32_get_bits(val, B_BE_RX_MPDU_MAX_LEN_MASK)); 2320 rtw89_info(rtwdev, "R_BE_RSP_CHK_SIG=0x%08x\n", 2321 rtw89_read32(rtwdev, R_BE_RSP_CHK_SIG)); 2322 rtw89_info(rtwdev, "R_BE_TRXPTCL_RESP_0=0x%08x\n", 2323 rtw89_read32(rtwdev, R_BE_TRXPTCL_RESP_0)); 2324 2325 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 2326 quota.dle_type = DLE_CTRL_TYPE_PLE; 2327 quota.qtaid = 7; 2328 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 2329 if (ret) 2330 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 2331 else 2332 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 2333 quota.rsv_pgnum, quota.use_pgnum); 2334 2335 val = rtw89_read32(rtwdev, R_BE_PLE_QTA7_CFG); 2336 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 2337 u32_get_bits(val, B_BE_PLE_Q7_MIN_SIZE_MASK)); 2338 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 2339 u32_get_bits(val, B_BE_PLE_Q7_MAX_SIZE_MASK)); 2340 val = rtw89_read32(rtwdev, R_BE_RX_FLTR_OPT_C1); 2341 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_BE_RX_MPDU_MAX_LEN=0x%x\n", 2342 u32_get_bits(val, B_BE_RX_MPDU_MAX_LEN_MASK)); 2343 rtw89_info(rtwdev, "R_BE_RSP_CHK_SIG_C1=0x%08x\n", 2344 rtw89_read32(rtwdev, R_BE_RSP_CHK_SIG_C1)); 2345 rtw89_info(rtwdev, "R_BE_TRXPTCL_RESP_0_C1=0x%08x\n", 2346 rtw89_read32(rtwdev, R_BE_TRXPTCL_RESP_0_C1)); 2347 } 2348 2349 rtw89_info(rtwdev, "R_BE_DLE_EMPTY0=0x%08x\n", 2350 rtw89_read32(rtwdev, R_BE_DLE_EMPTY0)); 2351 rtw89_info(rtwdev, "R_BE_DLE_EMPTY1=0x%08x\n", 2352 rtw89_read32(rtwdev, R_BE_DLE_EMPTY1)); 2353 2354 dump_err_status_dispatcher_be(rtwdev); 2355 } 2356 2357 static int rtw89_wow_config_mac_be(struct rtw89_dev *rtwdev, bool enable_wow) 2358 { 2359 if (enable_wow) { 2360 rtw89_write32_set(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP); 2361 rtw89_write32_clr(rtwdev, R_BE_RX_FLTR_OPT, B_BE_SNIFFER_MODE); 2362 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 2363 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 2364 rtw89_write32(rtwdev, R_BE_FWD_ERR, 0); 2365 rtw89_write32(rtwdev, R_BE_FWD_ACTN0, 0); 2366 rtw89_write32(rtwdev, R_BE_FWD_ACTN1, 0); 2367 rtw89_write32(rtwdev, R_BE_FWD_ACTN2, 0); 2368 rtw89_write32(rtwdev, R_BE_FWD_TF0, 0); 2369 rtw89_write32(rtwdev, R_BE_FWD_TF1, 0); 2370 rtw89_write32(rtwdev, R_BE_FWD_ERR, 0); 2371 rtw89_write32(rtwdev, R_BE_HW_PPDU_STATUS, 0); 2372 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 2373 } else { 2374 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 2375 rtw89_write32_clr(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP); 2376 rtw89_write32_set(rtwdev, R_BE_RX_FLTR_OPT, R_BE_RX_FLTR_OPT); 2377 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 2378 } 2379 2380 return 0; 2381 } 2382 2383 static void rtw89_mac_dump_cmac_err_status_be(struct rtw89_dev *rtwdev, 2384 u8 band) 2385 { 2386 u32 offset = 0; 2387 u32 cmac_err; 2388 int ret; 2389 2390 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 2391 if (ret) { 2392 rtw89_info(rtwdev, "[CMAC] : CMAC%d not enabled\n", band); 2393 return; 2394 } 2395 2396 if (band) 2397 offset = RTW89_MAC_BE_BAND_REG_OFFSET; 2398 2399 cmac_err = rtw89_read32(rtwdev, R_BE_CMAC_ERR_ISR + offset); 2400 rtw89_info(rtwdev, "R_BE_CMAC_ERR_ISR [%d]=0x%08x\n", band, 2401 rtw89_read32(rtwdev, R_BE_CMAC_ERR_ISR + offset)); 2402 rtw89_info(rtwdev, "R_BE_CMAC_FUNC_EN [%d]=0x%08x\n", band, 2403 rtw89_read32(rtwdev, R_BE_CMAC_FUNC_EN + offset)); 2404 rtw89_info(rtwdev, "R_BE_CK_EN [%d]=0x%08x\n", band, 2405 rtw89_read32(rtwdev, R_BE_CK_EN + offset)); 2406 2407 if (cmac_err & B_BE_SCHEDULE_TOP_ERR_IND) { 2408 rtw89_info(rtwdev, "R_BE_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 2409 rtw89_read32(rtwdev, R_BE_SCHEDULE_ERR_IMR + offset)); 2410 rtw89_info(rtwdev, "R_BE_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 2411 rtw89_read32(rtwdev, R_BE_SCHEDULE_ERR_ISR + offset)); 2412 } 2413 2414 if (cmac_err & B_BE_PTCL_TOP_ERR_IND) { 2415 rtw89_info(rtwdev, "R_BE_PTCL_IMR0 [%d]=0x%08x\n", band, 2416 rtw89_read32(rtwdev, R_BE_PTCL_IMR0 + offset)); 2417 rtw89_info(rtwdev, "R_BE_PTCL_ISR0 [%d]=0x%08x\n", band, 2418 rtw89_read32(rtwdev, R_BE_PTCL_ISR0 + offset)); 2419 rtw89_info(rtwdev, "R_BE_PTCL_IMR1 [%d]=0x%08x\n", band, 2420 rtw89_read32(rtwdev, R_BE_PTCL_IMR1 + offset)); 2421 rtw89_info(rtwdev, "R_BE_PTCL_ISR1 [%d]=0x%08x\n", band, 2422 rtw89_read32(rtwdev, R_BE_PTCL_ISR1 + offset)); 2423 } 2424 2425 if (cmac_err & B_BE_DMA_TOP_ERR_IND) { 2426 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_IMR [%d]=0x%08x\n", band, 2427 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_IMR + offset)); 2428 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG [%d]=0x%08x\n", band, 2429 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG + offset)); 2430 rtw89_info(rtwdev, "R_BE_TX_ERROR_FLAG_IMR [%d]=0x%08x\n", band, 2431 rtw89_read32(rtwdev, R_BE_TX_ERROR_FLAG_IMR + offset)); 2432 rtw89_info(rtwdev, "R_BE_TX_ERROR_FLAG [%d]=0x%08x\n", band, 2433 rtw89_read32(rtwdev, R_BE_TX_ERROR_FLAG + offset)); 2434 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_IMR_1 [%d]=0x%08x\n", band, 2435 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_IMR_1 + offset)); 2436 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_1 [%d]=0x%08x\n", band, 2437 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_1 + offset)); 2438 } 2439 2440 if (cmac_err & B_BE_PHYINTF_ERR_IND) { 2441 rtw89_info(rtwdev, "R_BE_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 2442 rtw89_read32(rtwdev, R_BE_PHYINFO_ERR_IMR_V1 + offset)); 2443 rtw89_info(rtwdev, "R_BE_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 2444 rtw89_read32(rtwdev, R_BE_PHYINFO_ERR_ISR + offset)); 2445 } 2446 2447 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 2448 rtw89_info(rtwdev, "R_BE_TXPWR_ERR_FLAG [%d]=0x%08x\n", band, 2449 rtw89_read32(rtwdev, R_BE_TXPWR_ERR_FLAG + offset)); 2450 rtw89_info(rtwdev, "R_BE_TXPWR_ERR_IMR [%d]=0x%08x\n", band, 2451 rtw89_read32(rtwdev, R_BE_TXPWR_ERR_IMR + offset)); 2452 } 2453 2454 if (cmac_err & (B_BE_WMAC_RX_ERR_IND | B_BE_WMAC_TX_ERR_IND | 2455 B_BE_WMAC_RX_IDLETO_IDCT | B_BE_PTCL_TX_IDLETO_IDCT)) { 2456 rtw89_info(rtwdev, "R_BE_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 2457 rtw89_read32(rtwdev, R_BE_DBGSEL_TRXPTCL + offset)); 2458 rtw89_info(rtwdev, "R_BE_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 2459 rtw89_read32(rtwdev, R_BE_TRXPTCL_ERROR_INDICA_MASK + offset)); 2460 rtw89_info(rtwdev, "R_BE_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 2461 rtw89_read32(rtwdev, R_BE_TRXPTCL_ERROR_INDICA + offset)); 2462 rtw89_info(rtwdev, "R_BE_RX_ERR_IMR [%d]=0x%08x\n", band, 2463 rtw89_read32(rtwdev, R_BE_RX_ERR_IMR + offset)); 2464 rtw89_info(rtwdev, "R_BE_RX_ERR_ISR [%d]=0x%08x\n", band, 2465 rtw89_read32(rtwdev, R_BE_RX_ERR_ISR + offset)); 2466 } 2467 2468 rtw89_info(rtwdev, "R_BE_CMAC_ERR_IMR [%d]=0x%08x\n", band, 2469 rtw89_read32(rtwdev, R_BE_CMAC_ERR_IMR + offset)); 2470 } 2471 2472 static void rtw89_mac_dump_err_status_be(struct rtw89_dev *rtwdev, 2473 enum mac_ax_err_info err) 2474 { 2475 if (err != MAC_AX_ERR_L1_ERR_DMAC && 2476 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 2477 err != MAC_AX_ERR_L0_ERR_CMAC0 && 2478 err != MAC_AX_ERR_L0_ERR_CMAC1 && 2479 err != MAC_AX_ERR_RXI300) 2480 return; 2481 2482 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 2483 rtw89_info(rtwdev, "R_BE_SER_DBG_INFO=0x%08x\n", 2484 rtw89_read32(rtwdev, R_BE_SER_DBG_INFO)); 2485 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT=0x%08x\n", 2486 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT)); 2487 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT1=0x%08x\n", 2488 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT1)); 2489 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT2=0x%08x\n", 2490 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT2)); 2491 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT3=0x%08x\n", 2492 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT3)); 2493 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 2494 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT_C1=0x%08x\n", 2495 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT_C1)); 2496 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT1_C1=0x%08x\n", 2497 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT1_C1)); 2498 } 2499 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_0=0x%08x\n", 2500 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_0)); 2501 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_1=0x%08x\n", 2502 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_1)); 2503 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_2=0x%08x\n", 2504 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_2)); 2505 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_3=0x%08x\n", 2506 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_3)); 2507 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_4=0x%08x\n", 2508 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_4)); 2509 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_5=0x%08x\n", 2510 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_5)); 2511 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_6=0x%08x\n", 2512 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_6)); 2513 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_7=0x%08x\n", 2514 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_7)); 2515 2516 rtw89_mac_dump_dmac_err_status(rtwdev); 2517 rtw89_mac_dump_cmac_err_status_be(rtwdev, RTW89_MAC_0); 2518 rtw89_mac_dump_cmac_err_status_be(rtwdev, RTW89_MAC_1); 2519 2520 rtwdev->hci.ops->dump_err_status(rtwdev); 2521 2522 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 2523 rtw89_mac_dump_l0_to_l1(rtwdev, err); 2524 2525 rtw89_info(rtwdev, "<---\n"); 2526 } 2527 2528 static bool mac_is_txq_empty_be(struct rtw89_dev *rtwdev) 2529 { 2530 struct rtw89_mac_dle_dfi_qempty qempty; 2531 u32 val32, msk32; 2532 u32 grpnum; 2533 int ret; 2534 int i; 2535 2536 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 2537 qempty.dle_type = DLE_CTRL_TYPE_WDE; 2538 2539 for (i = 0; i < grpnum; i++) { 2540 qempty.grpsel = i; 2541 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 2542 if (ret) { 2543 rtw89_warn(rtwdev, 2544 "%s: failed to dle dfi acq empty: %d\n", 2545 __func__, ret); 2546 return false; 2547 } 2548 2549 /* Each acq group contains 32 queues (8 macid * 4 acq), 2550 * but here, we can simply check if all bits are set. 2551 */ 2552 if (qempty.qempty != MASKDWORD) 2553 return false; 2554 } 2555 2556 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 2557 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 2558 if (ret) { 2559 rtw89_warn(rtwdev, "%s: failed to dle dfi mgq empty: %d\n", 2560 __func__, ret); 2561 return false; 2562 } 2563 2564 msk32 = B_CMAC0_MGQ_NORMAL_BE | B_CMAC1_MGQ_NORMAL_BE; 2565 if ((qempty.qempty & msk32) != msk32) 2566 return false; 2567 2568 msk32 = B_BE_WDE_EMPTY_QUE_OTHERS; 2569 val32 = rtw89_read32(rtwdev, R_BE_DLE_EMPTY0); 2570 return (val32 & msk32) == msk32; 2571 } 2572 2573 const struct rtw89_mac_gen_def rtw89_mac_gen_be = { 2574 .band1_offset = RTW89_MAC_BE_BAND_REG_OFFSET, 2575 .filter_model_addr = R_BE_FILTER_MODEL_ADDR, 2576 .indir_access_addr = R_BE_INDIR_ACCESS_ENTRY, 2577 .mem_base_addrs = rtw89_mac_mem_base_addrs_be, 2578 .mem_page_size = MAC_MEM_DUMP_PAGE_SIZE_BE, 2579 .rx_fltr = R_BE_RX_FLTR_OPT, 2580 .port_base = &rtw89_port_base_be, 2581 .agg_len_ht = R_BE_AGG_LEN_HT_0, 2582 .ps_status = R_BE_WMTX_POWER_BE_BIT_CTL, 2583 2584 .muedca_ctrl = { 2585 .addr = R_BE_MUEDCA_EN, 2586 .mask = B_BE_MUEDCA_EN_0 | B_BE_SET_MUEDCATIMER_TF_0, 2587 }, 2588 .bfee_ctrl = { 2589 .addr = R_BE_BFMEE_RESP_OPTION, 2590 .mask = B_BE_BFMEE_HT_NDPA_EN | B_BE_BFMEE_VHT_NDPA_EN | 2591 B_BE_BFMEE_HE_NDPA_EN | B_BE_BFMEE_EHT_NDPA_EN, 2592 }, 2593 .narrow_bw_ru_dis = { 2594 .addr = R_BE_RXTRIG_TEST_USER_2, 2595 .mask = B_BE_RXTRIG_RU26_DIS, 2596 }, 2597 .wow_ctrl = {.addr = R_BE_WOW_CTRL, .mask = B_BE_WOW_WOWEN,}, 2598 .agg_limit = {.addr = R_BE_AMPDU_AGG_LIMIT, .mask = B_BE_AMPDU_MAX_TIME_MASK,}, 2599 .txcnt_limit = {.addr = R_BE_TXCNT, .mask = B_BE_L_TXCNT_LMT_MASK,}, 2600 2601 .check_mac_en = rtw89_mac_check_mac_en_be, 2602 .sys_init = sys_init_be, 2603 .trx_init = trx_init_be, 2604 .hci_func_en = rtw89_mac_hci_func_en_be, 2605 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_be, 2606 .dle_func_en = dle_func_en_be, 2607 .dle_clk_en = dle_clk_en_be, 2608 .bf_assoc = rtw89_mac_bf_assoc_be, 2609 2610 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_be, 2611 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_be, 2612 .cfg_phy_rpt = rtw89_mac_cfg_phy_rpt_be, 2613 2614 .dle_mix_cfg = dle_mix_cfg_be, 2615 .chk_dle_rdy = chk_dle_rdy_be, 2616 .dle_buf_req = dle_buf_req_be, 2617 .hfc_func_en = hfc_func_en_be, 2618 .hfc_h2c_cfg = hfc_h2c_cfg_be, 2619 .hfc_mix_cfg = hfc_mix_cfg_be, 2620 .hfc_get_mix_info = hfc_get_mix_info_be, 2621 .wde_quota_cfg = wde_quota_cfg_be, 2622 .ple_quota_cfg = ple_quota_cfg_be, 2623 .set_cpuio = set_cpuio_be, 2624 .dle_quota_change = dle_quota_change_be, 2625 2626 .disable_cpu = rtw89_mac_disable_cpu_be, 2627 .fwdl_enable_wcpu = rtw89_mac_fwdl_enable_wcpu_be, 2628 .fwdl_get_status = fwdl_get_status_be, 2629 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_be, 2630 .fwdl_secure_idmem_share_mode = NULL, 2631 .parse_efuse_map = rtw89_parse_efuse_map_be, 2632 .parse_phycap_map = rtw89_parse_phycap_map_be, 2633 .cnv_efuse_state = rtw89_cnv_efuse_state_be, 2634 .efuse_read_fw_secure = rtw89_efuse_read_fw_secure_be, 2635 2636 .cfg_plt = rtw89_mac_cfg_plt_be, 2637 .get_plt_cnt = rtw89_mac_get_plt_cnt_be, 2638 2639 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_be, 2640 2641 .write_xtal_si = rtw89_mac_write_xtal_si_be, 2642 .read_xtal_si = rtw89_mac_read_xtal_si_be, 2643 2644 .dump_qta_lost = rtw89_mac_dump_qta_lost_be, 2645 .dump_err_status = rtw89_mac_dump_err_status_be, 2646 2647 .is_txq_empty = mac_is_txq_empty_be, 2648 2649 .prep_chan_list = rtw89_hw_scan_prep_chan_list_be, 2650 .free_chan_list = rtw89_hw_scan_free_chan_list_be, 2651 .add_chan_list = rtw89_hw_scan_add_chan_list_be, 2652 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_be, 2653 .scan_offload = rtw89_fw_h2c_scan_offload_be, 2654 2655 .wow_config_mac = rtw89_wow_config_mac_be, 2656 }; 2657 EXPORT_SYMBOL(rtw89_mac_gen_be); 2658