1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "debug.h" 6 #include "efuse.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "reg.h" 10 11 static const u32 rtw89_mac_mem_base_addrs_be[RTW89_MAC_MEM_NUM] = { 12 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR_BE, 13 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR_BE, 14 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR_BE, 15 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR_BE, 16 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR_BE, 17 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR_BE, 18 [RTW89_MAC_MEM_SECURITY_CAM] = SEC_CAM_BASE_ADDR_BE, 19 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR_BE, 20 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR_BE, 21 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR_BE, 22 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR_BE, 23 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR_BE, 24 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR_BE, 25 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR_BE, 26 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR_BE, 27 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR_BE, 28 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR_BE, 29 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR_BE, 30 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR_BE, 31 [RTW89_MAC_MEM_WD_PAGE] = WD_PAGE_BASE_ADDR_BE, 32 }; 33 34 static const struct rtw89_port_reg rtw89_port_base_be = { 35 .port_cfg = R_BE_PORT_CFG_P0, 36 .tbtt_prohib = R_BE_TBTT_PROHIB_P0, 37 .bcn_area = R_BE_BCN_AREA_P0, 38 .bcn_early = R_BE_BCNERLYINT_CFG_P0, 39 .tbtt_early = R_BE_TBTTERLYINT_CFG_P0, 40 .tbtt_agg = R_BE_TBTT_AGG_P0, 41 .bcn_space = R_BE_BCN_SPACE_CFG_P0, 42 .bcn_forcetx = R_BE_BCN_FORCETX_P0, 43 .bcn_err_cnt = R_BE_BCN_ERR_CNT_P0, 44 .bcn_err_flag = R_BE_BCN_ERR_FLAG_P0, 45 .dtim_ctrl = R_BE_DTIM_CTRL_P0, 46 .tbtt_shift = R_BE_TBTT_SHIFT_P0, 47 .bcn_cnt_tmr = R_BE_BCN_CNT_TMR_P0, 48 .tsftr_l = R_BE_TSFTR_LOW_P0, 49 .tsftr_h = R_BE_TSFTR_HIGH_P0, 50 .md_tsft = R_BE_WMTX_MOREDATA_TSFT_STMP_CTL, 51 .bss_color = R_BE_PTCL_BSS_COLOR_0, 52 .mbssid = R_BE_MBSSID_CTRL, 53 .mbssid_drop = R_BE_MBSSID_DROP_0, 54 .tsf_sync = R_BE_PORT_0_TSF_SYNC, 55 .hiq_win = {R_BE_P0MB_HGQ_WINDOW_CFG_0, R_BE_PORT_HGQ_WINDOW_CFG, 56 R_BE_PORT_HGQ_WINDOW_CFG + 1, R_BE_PORT_HGQ_WINDOW_CFG + 2, 57 R_BE_PORT_HGQ_WINDOW_CFG + 3}, 58 }; 59 60 static int rtw89_mac_check_mac_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, 61 enum rtw89_mac_hwmod_sel sel) 62 { 63 if (sel == RTW89_DMAC_SEL && 64 test_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags)) 65 return 0; 66 if (sel == RTW89_CMAC_SEL && mac_idx == RTW89_MAC_0 && 67 test_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags)) 68 return 0; 69 if (sel == RTW89_CMAC_SEL && mac_idx == RTW89_MAC_1 && 70 test_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags)) 71 return 0; 72 73 return -EFAULT; 74 } 75 76 static void hfc_get_mix_info_be(struct rtw89_dev *rtwdev) 77 { 78 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 79 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 80 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 81 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 82 u32 val; 83 84 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO1); 85 info->g0_used = u32_get_bits(val, B_BE_G0_USE_PG_MASK); 86 info->g1_used = u32_get_bits(val, B_BE_G1_USE_PG_MASK); 87 88 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO3); 89 info->g0_aval = u32_get_bits(val, B_BE_G0_AVAL_PG_MASK); 90 info->g1_aval = u32_get_bits(val, B_BE_G1_AVAL_PG_MASK); 91 info->pub_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO2), 92 B_BE_PUB_AVAL_PG_MASK); 93 info->wp_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_WP_PAGE_INFO1), 94 B_BE_WP_AVAL_PG_MASK); 95 96 val = rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL); 97 param->en = !!(val & B_BE_HCI_FC_EN); 98 param->h2c_en = !!(val & B_BE_HCI_FC_CH12_EN); 99 param->mode = u32_get_bits(val, B_BE_HCI_FC_MODE_MASK); 100 prec_cfg->ch011_full_cond = u32_get_bits(val, B_BE_HCI_FC_WD_FULL_COND_MASK); 101 prec_cfg->h2c_full_cond = u32_get_bits(val, B_BE_HCI_FC_CH12_FULL_COND_MASK); 102 prec_cfg->wp_ch07_full_cond = 103 u32_get_bits(val, B_BE_HCI_FC_WP_CH07_FULL_COND_MASK); 104 prec_cfg->wp_ch811_full_cond = 105 u32_get_bits(val, B_BE_HCI_FC_WP_CH811_FULL_COND_MASK); 106 107 val = rtw89_read32(rtwdev, R_BE_CH_PAGE_CTRL); 108 prec_cfg->ch011_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH011_V1_MASK); 109 prec_cfg->h2c_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH12_V1_MASK); 110 111 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL2); 112 pub_cfg->pub_max = u32_get_bits(val, B_BE_PUBPG_ALL_MASK); 113 114 val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL1); 115 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_MASK); 116 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_MASK); 117 118 val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL2); 119 pub_cfg->wp_thrd = u32_get_bits(val, B_BE_WP_THRD_MASK); 120 121 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL1); 122 pub_cfg->grp0 = u32_get_bits(val, B_BE_PUBPG_G0_MASK); 123 pub_cfg->grp1 = u32_get_bits(val, B_BE_PUBPG_G1_MASK); 124 } 125 126 static void hfc_h2c_cfg_be(struct rtw89_dev *rtwdev) 127 { 128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 129 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 130 u32 val; 131 132 val = u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK); 133 rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val); 134 } 135 136 static void hfc_mix_cfg_be(struct rtw89_dev *rtwdev) 137 { 138 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 139 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 140 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 141 u32 val; 142 143 val = u32_encode_bits(prec_cfg->ch011_prec, B_BE_PREC_PAGE_CH011_V1_MASK) | 144 u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK); 145 rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val); 146 147 val = u32_encode_bits(pub_cfg->pub_max, B_BE_PUBPG_ALL_MASK); 148 rtw89_write32(rtwdev, R_BE_PUB_PAGE_CTRL2, val); 149 150 val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_MASK) | 151 u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_MASK); 152 rtw89_write32(rtwdev, R_BE_WP_PAGE_CTRL1, val); 153 154 val = u32_replace_bits(rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL), 155 param->mode, B_BE_HCI_FC_MODE_MASK); 156 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 157 B_BE_HCI_FC_WD_FULL_COND_MASK); 158 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 159 B_BE_HCI_FC_CH12_FULL_COND_MASK); 160 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 161 B_BE_HCI_FC_WP_CH07_FULL_COND_MASK); 162 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 163 B_BE_HCI_FC_WP_CH811_FULL_COND_MASK); 164 rtw89_write32(rtwdev, R_BE_HCI_FC_CTRL, val); 165 } 166 167 static void hfc_func_en_be(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 168 { 169 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 170 u32 val; 171 172 val = rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL); 173 param->en = en; 174 param->h2c_en = h2c_en; 175 val = en ? (val | B_BE_HCI_FC_EN) : (val & ~B_BE_HCI_FC_EN); 176 val = h2c_en ? (val | B_BE_HCI_FC_CH12_EN) : 177 (val & ~B_BE_HCI_FC_CH12_EN); 178 rtw89_write32(rtwdev, R_BE_HCI_FC_CTRL, val); 179 } 180 181 static void dle_func_en_be(struct rtw89_dev *rtwdev, bool enable) 182 { 183 if (enable) 184 rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN, 185 B_BE_DLE_WDE_EN | B_BE_DLE_PLE_EN); 186 else 187 rtw89_write32_clr(rtwdev, R_BE_DMAC_FUNC_EN, 188 B_BE_DLE_WDE_EN | B_BE_DLE_PLE_EN); 189 } 190 191 static void dle_clk_en_be(struct rtw89_dev *rtwdev, bool enable) 192 { 193 if (enable) 194 rtw89_write32_set(rtwdev, R_BE_DMAC_CLK_EN, 195 B_BE_DLE_WDE_CLK_EN | B_BE_DLE_PLE_CLK_EN); 196 else 197 rtw89_write32_clr(rtwdev, R_BE_DMAC_CLK_EN, 198 B_BE_DLE_WDE_CLK_EN | B_BE_DLE_PLE_CLK_EN); 199 } 200 201 static int dle_mix_cfg_be(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 202 { 203 const struct rtw89_dle_size *wde_size_cfg, *ple_size_cfg; 204 u32 bound; 205 u32 val; 206 207 wde_size_cfg = cfg->wde_size; 208 ple_size_cfg = cfg->ple_size; 209 210 val = rtw89_read32(rtwdev, R_BE_WDE_PKTBUF_CFG); 211 212 switch (wde_size_cfg->pge_size) { 213 default: 214 case RTW89_WDE_PG_64: 215 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 216 B_BE_WDE_PAGE_SEL_MASK); 217 break; 218 case RTW89_WDE_PG_128: 219 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 220 B_BE_WDE_PAGE_SEL_MASK); 221 break; 222 case RTW89_WDE_PG_256: 223 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 224 return -EINVAL; 225 } 226 227 bound = wde_size_cfg->srt_ofst / DLE_BOUND_UNIT; 228 val = u32_replace_bits(val, bound, B_BE_WDE_START_BOUND_MASK); 229 val = u32_replace_bits(val, wde_size_cfg->lnk_pge_num, 230 B_BE_WDE_FREE_PAGE_NUM_MASK); 231 rtw89_write32(rtwdev, R_BE_WDE_PKTBUF_CFG, val); 232 233 val = rtw89_read32(rtwdev, R_BE_PLE_PKTBUF_CFG); 234 235 switch (ple_size_cfg->pge_size) { 236 default: 237 case RTW89_PLE_PG_64: 238 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 239 return -EINVAL; 240 case RTW89_PLE_PG_128: 241 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 242 B_BE_PLE_PAGE_SEL_MASK); 243 break; 244 case RTW89_PLE_PG_256: 245 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 246 B_BE_PLE_PAGE_SEL_MASK); 247 break; 248 } 249 250 bound = ple_size_cfg->srt_ofst / DLE_BOUND_UNIT; 251 val = u32_replace_bits(val, bound, B_BE_PLE_START_BOUND_MASK); 252 val = u32_replace_bits(val, ple_size_cfg->lnk_pge_num, 253 B_BE_PLE_FREE_PAGE_NUM_MASK); 254 rtw89_write32(rtwdev, R_BE_PLE_PKTBUF_CFG, val); 255 256 return 0; 257 } 258 259 static int chk_dle_rdy_be(struct rtw89_dev *rtwdev, bool wde_or_ple) 260 { 261 u32 reg, mask; 262 u32 ini; 263 264 if (wde_or_ple) { 265 reg = R_AX_WDE_INI_STATUS; 266 mask = WDE_MGN_INI_RDY; 267 } else { 268 reg = R_AX_PLE_INI_STATUS; 269 mask = PLE_MGN_INI_RDY; 270 } 271 272 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 273 2000, false, rtwdev, reg); 274 } 275 276 #define INVALID_QT_WCPU U16_MAX 277 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 278 do { \ 279 val = u32_encode_bits(_min_x, B_BE_ ## _module ## _Q ## _idx ## _MIN_SIZE_MASK) | \ 280 u32_encode_bits(_max_x, B_BE_ ## _module ## _Q ## _idx ## _MAX_SIZE_MASK); \ 281 rtw89_write32(rtwdev, \ 282 R_BE_ ## _module ## _QTA ## _idx ## _CFG, \ 283 val); \ 284 } while (0) 285 #define SET_QUOTA(_x, _module, _idx) \ 286 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 287 288 static void wde_quota_cfg_be(struct rtw89_dev *rtwdev, 289 const struct rtw89_wde_quota *min_cfg, 290 const struct rtw89_wde_quota *max_cfg, 291 u16 ext_wde_min_qt_wcpu) 292 { 293 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 294 ext_wde_min_qt_wcpu : min_cfg->wcpu; 295 u16 max_qt_wcpu = max(max_cfg->wcpu, min_qt_wcpu); 296 u32 val; 297 298 SET_QUOTA(hif, WDE, 0); 299 SET_QUOTA_VAL(min_qt_wcpu, max_qt_wcpu, WDE, 1); 300 SET_QUOTA_VAL(0, 0, WDE, 2); 301 SET_QUOTA(pkt_in, WDE, 3); 302 SET_QUOTA(cpu_io, WDE, 4); 303 } 304 305 static void ple_quota_cfg_be(struct rtw89_dev *rtwdev, 306 const struct rtw89_ple_quota *min_cfg, 307 const struct rtw89_ple_quota *max_cfg) 308 { 309 u32 val; 310 311 SET_QUOTA(cma0_tx, PLE, 0); 312 SET_QUOTA(cma1_tx, PLE, 1); 313 SET_QUOTA(c2h, PLE, 2); 314 SET_QUOTA(h2c, PLE, 3); 315 SET_QUOTA(wcpu, PLE, 4); 316 SET_QUOTA(mpdu_proc, PLE, 5); 317 SET_QUOTA(cma0_dma, PLE, 6); 318 SET_QUOTA(cma1_dma, PLE, 7); 319 SET_QUOTA(bb_rpt, PLE, 8); 320 SET_QUOTA(wd_rel, PLE, 9); 321 SET_QUOTA(cpu_io, PLE, 10); 322 SET_QUOTA(tx_rpt, PLE, 11); 323 SET_QUOTA(h2d, PLE, 12); 324 } 325 326 static void rtw89_mac_hci_func_en_be(struct rtw89_dev *rtwdev) 327 { 328 rtw89_write32_set(rtwdev, R_BE_HCI_FUNC_EN, B_BE_HCI_TXDMA_EN | 329 B_BE_HCI_RXDMA_EN); 330 } 331 332 static void rtw89_mac_dmac_func_pre_en_be(struct rtw89_dev *rtwdev) 333 { 334 u32 val; 335 336 val = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1); 337 338 switch (rtwdev->hci.type) { 339 case RTW89_HCI_TYPE_PCIE: 340 val = u32_replace_bits(val, S_BE_DMA_MOD_PCIE_NO_DATA_CPU, 341 B_BE_DMA_MODE_MASK); 342 break; 343 case RTW89_HCI_TYPE_USB: 344 val = u32_replace_bits(val, S_BE_DMA_MOD_USB, B_BE_DMA_MODE_MASK); 345 val = (val & ~B_BE_STOP_AXI_MST) | B_BE_TXDMA_EN | B_BE_RXDMA_EN; 346 break; 347 case RTW89_HCI_TYPE_SDIO: 348 val = u32_replace_bits(val, S_BE_DMA_MOD_SDIO, B_BE_DMA_MODE_MASK); 349 val = (val & ~B_BE_STOP_AXI_MST) | B_BE_TXDMA_EN | B_BE_RXDMA_EN; 350 break; 351 default: 352 return; 353 } 354 355 rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val); 356 357 rtw89_write32_clr(rtwdev, R_BE_HAXI_DMA_STOP1, 358 B_BE_STOP_CH0 | B_BE_STOP_CH1 | B_BE_STOP_CH2 | 359 B_BE_STOP_CH3 | B_BE_STOP_CH4 | B_BE_STOP_CH5 | 360 B_BE_STOP_CH6 | B_BE_STOP_CH7 | B_BE_STOP_CH8 | 361 B_BE_STOP_CH9 | B_BE_STOP_CH10 | B_BE_STOP_CH11 | 362 B_BE_STOP_CH12 | B_BE_STOP_CH13 | B_BE_STOP_CH14); 363 364 rtw89_write32_set(rtwdev, R_BE_DMAC_TABLE_CTRL, B_BE_DMAC_ADDR_MODE); 365 } 366 367 static 368 int rtw89_mac_write_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 369 { 370 u32 val32; 371 int ret; 372 373 val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) | 374 u32_encode_bits(val, B_BE_WL_XTAL_SI_DATA_MASK) | 375 u32_encode_bits(mask, B_BE_WL_XTAL_SI_BITMASK_MASK) | 376 u32_encode_bits(XTAL_SI_NORMAL_WRITE, B_BE_WL_XTAL_SI_MODE_MASK) | 377 u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) | 378 B_BE_WL_XTAL_SI_CMD_POLL; 379 rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32); 380 381 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL), 382 50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL); 383 if (ret) { 384 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 385 offset, val, mask); 386 return ret; 387 } 388 389 return 0; 390 } 391 392 static 393 int rtw89_mac_read_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 394 { 395 u32 val32; 396 int ret; 397 398 val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) | 399 u32_encode_bits(0x0, B_BE_WL_XTAL_SI_DATA_MASK) | 400 u32_encode_bits(0x0, B_BE_WL_XTAL_SI_BITMASK_MASK) | 401 u32_encode_bits(XTAL_SI_NORMAL_READ, B_BE_WL_XTAL_SI_MODE_MASK) | 402 u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) | 403 B_BE_WL_XTAL_SI_CMD_POLL; 404 rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32); 405 406 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL), 407 50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL); 408 if (ret) { 409 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 410 return ret; 411 } 412 413 *val = rtw89_read8(rtwdev, R_BE_WLAN_XTAL_SI_CTRL + 1); 414 415 return 0; 416 } 417 418 static void rtw89_mac_disable_cpu_be(struct rtw89_dev *rtwdev) 419 { 420 u32 val32; 421 422 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 423 424 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN); 425 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET); 426 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN); 427 428 val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL); 429 val32 &= B_BE_RUN_ENV_MASK; 430 rtw89_write32(rtwdev, R_BE_WCPU_FW_CTRL, val32); 431 432 rtw89_write32_set(rtwdev, R_BE_DCPU_PLATFORM_ENABLE, B_BE_DCPU_PLATFORM_EN); 433 434 rtw89_write32(rtwdev, R_BE_UDM0, 0); 435 rtw89_write32(rtwdev, R_BE_HALT_C2H, 0); 436 rtw89_write32(rtwdev, R_BE_UDM2, 0); 437 } 438 439 static void set_cpu_en(struct rtw89_dev *rtwdev, bool include_bb) 440 { 441 u32 set = B_BE_WLANCPU_FWDL_EN; 442 443 if (include_bb) 444 set |= B_BE_BBMCU0_FWDL_EN; 445 446 rtw89_write32_set(rtwdev, R_BE_WCPU_FW_CTRL, set); 447 } 448 449 static int wcpu_on(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw) 450 { 451 u32 val32; 452 int ret; 453 454 val32 = rtw89_read32(rtwdev, R_BE_HALT_C2H); 455 if (val32) { 456 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n"); 457 rtw89_warn(rtwdev, "[SER] %s: R_BE_HALT_C2H = 0x%x\n", __func__, val32); 458 } 459 val32 = rtw89_read32(rtwdev, R_BE_UDM1); 460 if (val32) { 461 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n"); 462 rtw89_warn(rtwdev, "[SER] %s: R_BE_UDM1 = 0x%x\n", __func__, val32); 463 } 464 val32 = rtw89_read32(rtwdev, R_BE_UDM2); 465 if (val32) { 466 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n"); 467 rtw89_warn(rtwdev, "[SER] %s: R_BE_UDM2 = 0x%x\n", __func__, val32); 468 } 469 470 rtw89_write32(rtwdev, R_BE_UDM1, 0); 471 rtw89_write32(rtwdev, R_BE_UDM2, 0); 472 rtw89_write32(rtwdev, R_BE_HALT_H2C, 0); 473 rtw89_write32(rtwdev, R_BE_HALT_C2H, 0); 474 rtw89_write32(rtwdev, R_BE_HALT_H2C_CTRL, 0); 475 rtw89_write32(rtwdev, R_BE_HALT_C2H_CTRL, 0); 476 477 val32 = rtw89_read32(rtwdev, R_BE_HISR0); 478 rtw89_write32(rtwdev, R_BE_HISR0, B_BE_HALT_C2H_INT); 479 rtw89_debug(rtwdev, RTW89_DBG_SER, "HISR0=0x%x\n", val32); 480 481 rtw89_write32_set(rtwdev, R_BE_SYS_CLK_CTRL, B_BE_CPU_CLK_EN); 482 rtw89_write32_clr(rtwdev, R_BE_SYS_CFG5, 483 B_BE_WDT_WAKE_PCIE_EN | B_BE_WDT_WAKE_USB_EN); 484 rtw89_write32_clr(rtwdev, R_BE_WCPU_FW_CTRL, 485 B_BE_WDT_PLT_RST_EN | B_BE_WCPU_ROM_CUT_GET); 486 487 rtw89_write16_mask(rtwdev, R_BE_BOOT_REASON, B_BE_BOOT_REASON_MASK, boot_reason); 488 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN); 489 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET); 490 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN); 491 492 if (!dlfw) { 493 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 494 if (ret) 495 return ret; 496 } 497 498 return 0; 499 } 500 501 static int rtw89_mac_fwdl_enable_wcpu_be(struct rtw89_dev *rtwdev, 502 u8 boot_reason, bool dlfw, 503 bool include_bb) 504 { 505 set_cpu_en(rtwdev, include_bb); 506 507 return wcpu_on(rtwdev, boot_reason, dlfw); 508 } 509 510 static const u8 fwdl_status_map[] = { 511 [0] = RTW89_FWDL_INITIAL_STATE, 512 [1] = RTW89_FWDL_FWDL_ONGOING, 513 [4] = RTW89_FWDL_CHECKSUM_FAIL, 514 [5] = RTW89_FWDL_SECURITY_FAIL, 515 [6] = RTW89_FWDL_SECURITY_FAIL, 516 [7] = RTW89_FWDL_CV_NOT_MATCH, 517 [8] = RTW89_FWDL_RSVD0, 518 [2] = RTW89_FWDL_WCPU_FWDL_RDY, 519 [3] = RTW89_FWDL_WCPU_FW_INIT_RDY, 520 [9] = RTW89_FWDL_RSVD0, 521 }; 522 523 static u8 fwdl_get_status_be(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 524 { 525 bool check_pass = false; 526 u32 val32; 527 u8 st; 528 529 val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL); 530 531 switch (type) { 532 case RTW89_FWDL_CHECK_WCPU_FWDL_DONE: 533 check_pass = !(val32 & B_BE_WLANCPU_FWDL_EN); 534 break; 535 case RTW89_FWDL_CHECK_DCPU_FWDL_DONE: 536 check_pass = !(val32 & B_BE_DATACPU_FWDL_EN); 537 break; 538 case RTW89_FWDL_CHECK_BB0_FWDL_DONE: 539 check_pass = !(val32 & B_BE_BBMCU0_FWDL_EN); 540 break; 541 case RTW89_FWDL_CHECK_BB1_FWDL_DONE: 542 check_pass = !(val32 & B_BE_BBMCU1_FWDL_EN); 543 break; 544 default: 545 break; 546 } 547 548 if (check_pass) 549 return RTW89_FWDL_WCPU_FW_INIT_RDY; 550 551 st = u32_get_bits(val32, B_BE_WCPU_FWDL_STATUS_MASK); 552 if (st < ARRAY_SIZE(fwdl_status_map)) 553 return fwdl_status_map[st]; 554 555 return st; 556 } 557 558 static int rtw89_fwdl_check_path_ready_be(struct rtw89_dev *rtwdev, 559 bool h2c_or_fwdl) 560 { 561 u32 check = h2c_or_fwdl ? B_BE_H2C_PATH_RDY : B_BE_DLFW_PATH_RDY; 562 u32 val; 563 564 return read_poll_timeout_atomic(rtw89_read32, val, val & check, 565 1, 1000000, false, 566 rtwdev, R_BE_WCPU_FW_CTRL); 567 } 568 569 static int dle_buf_req_be(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 570 { 571 u32 val, reg; 572 int ret; 573 574 reg = wd ? R_BE_WD_BUF_REQ : R_BE_PL_BUF_REQ; 575 val = buf_len; 576 val |= B_BE_WD_BUF_REQ_EXEC; 577 rtw89_write32(rtwdev, reg, val); 578 579 reg = wd ? R_BE_WD_BUF_STATUS : R_BE_PL_BUF_STATUS; 580 581 ret = read_poll_timeout(rtw89_read32, val, val & B_BE_WD_BUF_STAT_DONE, 582 1, 2000, false, rtwdev, reg); 583 if (ret) 584 return ret; 585 586 *pkt_id = u32_get_bits(val, B_BE_WD_BUF_STAT_PKTID_MASK); 587 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 588 return -ENOENT; 589 590 return 0; 591 } 592 593 static int set_cpuio_be(struct rtw89_dev *rtwdev, 594 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 595 { 596 u32 val_op0, val_op1, val_op2, val_op3; 597 u32 val, cmd_type, reg; 598 int ret; 599 600 cmd_type = ctrl_para->cmd_type; 601 602 reg = wd ? R_BE_WD_CPUQ_OP_3 : R_BE_PL_CPUQ_OP_3; 603 val_op3 = u32_replace_bits(0, ctrl_para->start_pktid, 604 B_BE_WD_CPUQ_OP_STRT_PKTID_MASK); 605 val_op3 = u32_replace_bits(val_op3, ctrl_para->end_pktid, 606 B_BE_WD_CPUQ_OP_END_PKTID_MASK); 607 rtw89_write32(rtwdev, reg, val_op3); 608 609 reg = wd ? R_BE_WD_CPUQ_OP_1 : R_BE_PL_CPUQ_OP_1; 610 val_op1 = u32_replace_bits(0, ctrl_para->src_pid, 611 B_BE_WD_CPUQ_OP_SRC_PID_MASK); 612 val_op1 = u32_replace_bits(val_op1, ctrl_para->src_qid, 613 B_BE_WD_CPUQ_OP_SRC_QID_MASK); 614 val_op1 = u32_replace_bits(val_op1, ctrl_para->macid, 615 B_BE_WD_CPUQ_OP_SRC_MACID_MASK); 616 rtw89_write32(rtwdev, reg, val_op1); 617 618 reg = wd ? R_BE_WD_CPUQ_OP_2 : R_BE_PL_CPUQ_OP_2; 619 val_op2 = u32_replace_bits(0, ctrl_para->dst_pid, 620 B_BE_WD_CPUQ_OP_DST_PID_MASK); 621 val_op2 = u32_replace_bits(val_op2, ctrl_para->dst_qid, 622 B_BE_WD_CPUQ_OP_DST_QID_MASK); 623 val_op2 = u32_replace_bits(val_op2, ctrl_para->macid, 624 B_BE_WD_CPUQ_OP_DST_MACID_MASK); 625 rtw89_write32(rtwdev, reg, val_op2); 626 627 reg = wd ? R_BE_WD_CPUQ_OP_0 : R_BE_PL_CPUQ_OP_0; 628 val_op0 = u32_replace_bits(0, cmd_type, 629 B_BE_WD_CPUQ_OP_CMD_TYPE_MASK); 630 val_op0 = u32_replace_bits(val_op0, ctrl_para->pkt_num, 631 B_BE_WD_CPUQ_OP_PKTNUM_MASK); 632 val_op0 |= B_BE_WD_CPUQ_OP_EXEC; 633 rtw89_write32(rtwdev, reg, val_op0); 634 635 reg = wd ? R_BE_WD_CPUQ_OP_STATUS : R_BE_PL_CPUQ_OP_STATUS; 636 637 ret = read_poll_timeout(rtw89_read32, val, val & B_BE_WD_CPUQ_OP_STAT_DONE, 638 1, 2000, false, rtwdev, reg); 639 if (ret) { 640 rtw89_err(rtwdev, "[ERR]set cpuio wd timeout\n"); 641 rtw89_err(rtwdev, "[ERR]op_0=0x%X, op_1=0x%X, op_2=0x%X\n", 642 val_op0, val_op1, val_op2); 643 return ret; 644 } 645 646 if (cmd_type == CPUIO_OP_CMD_GET_NEXT_PID || 647 cmd_type == CPUIO_OP_CMD_GET_1ST_PID) 648 ctrl_para->pktid = u32_get_bits(val, B_BE_WD_CPUQ_OP_PKTID_MASK); 649 650 return 0; 651 } 652 653 static bool rtw89_mac_get_txpwr_cr_be(struct rtw89_dev *rtwdev, 654 enum rtw89_phy_idx phy_idx, 655 u32 reg_base, u32 *cr) 656 { 657 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 658 enum rtw89_qta_mode mode = dle_mem->mode; 659 int ret; 660 661 ret = rtw89_mac_check_mac_en(rtwdev, (enum rtw89_mac_idx)phy_idx, 662 RTW89_CMAC_SEL); 663 if (ret) { 664 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) 665 return false; 666 667 rtw89_err(rtwdev, "[TXPWR] check mac enable failed\n"); 668 return false; 669 } 670 671 if (reg_base < R_BE_PWR_MODULE || reg_base > R_BE_CMAC_FUNC_EN_C1) { 672 rtw89_err(rtwdev, "[TXPWR] reg_base=0x%x exceed txpwr cr\n", 673 reg_base); 674 return false; 675 } 676 677 *cr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 678 679 if (*cr >= CMAC1_START_ADDR_BE && *cr <= CMAC1_END_ADDR_BE) { 680 if (mode == RTW89_QTA_SCC) { 681 rtw89_err(rtwdev, 682 "[TXPWR] addr=0x%x but hw not enable\n", 683 *cr); 684 return false; 685 } 686 } 687 688 return true; 689 } 690 691 static int rtw89_mac_init_bfee_be(struct rtw89_dev *rtwdev, u8 mac_idx) 692 { 693 u32 reg; 694 u32 val; 695 int ret; 696 697 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 698 if (ret) 699 return ret; 700 701 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 702 703 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 704 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL | 705 B_BE_BFMEE_USE_NSTS | 706 B_BE_BFMEE_CSI_GID_SEL | 707 B_BE_BFMEE_CSI_FORCE_RETE_EN); 708 rtw89_write32_mask(rtwdev, reg, B_BE_BFMEE_CSI_RSC_MASK, CSI_RX_BW_CFG); 709 710 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CSIRPT_OPTION, mac_idx); 711 rtw89_write32_set(rtwdev, reg, B_BE_CSIPRT_VHTSU_AID_EN | 712 B_BE_CSIPRT_HESU_AID_EN | 713 B_BE_CSIPRT_EHTSU_AID_EN); 714 715 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RRSC, mac_idx); 716 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP_BE); 717 718 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 719 rtw89_write32_mask(rtwdev, reg, B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK, 720 CSI_RRSC_BITMAP_CFG); 721 722 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RATE, mac_idx); 723 val = u32_encode_bits(CSI_INIT_RATE_HT, B_BE_BFMEE_HT_CSI_RATE_MASK) | 724 u32_encode_bits(CSI_INIT_RATE_VHT, B_BE_BFMEE_VHT_CSI_RATE_MASK) | 725 u32_encode_bits(CSI_INIT_RATE_HE, B_BE_BFMEE_HE_CSI_RATE_MASK) | 726 u32_encode_bits(CSI_INIT_RATE_EHT, B_BE_BFMEE_EHT_CSI_RATE_MASK); 727 728 rtw89_write32(rtwdev, reg, val); 729 730 return 0; 731 } 732 733 static int rtw89_mac_set_csi_para_reg_be(struct rtw89_dev *rtwdev, 734 struct ieee80211_vif *vif, 735 struct ieee80211_sta *sta) 736 { 737 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 738 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 739 u8 mac_idx = rtwvif->mac_idx; 740 u8 port_sel = rtwvif->port; 741 u8 sound_dim = 3, t; 742 u8 *phy_cap; 743 u32 reg; 744 u16 val; 745 int ret; 746 747 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 748 if (ret) 749 return ret; 750 751 phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 752 753 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 754 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 755 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 756 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 757 t = u8_get_bits(phy_cap[5], 758 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK); 759 sound_dim = min(sound_dim, t); 760 } 761 762 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 763 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 764 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 765 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 766 t = u32_get_bits(sta->deflink.vht_cap.cap, 767 IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK); 768 sound_dim = min(sound_dim, t); 769 } 770 771 nc = min(nc, sound_dim); 772 nr = min(nr, sound_dim); 773 774 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 775 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL); 776 777 val = u16_encode_bits(nc, B_BE_BFMEE_CSIINFO0_NC_MASK) | 778 u16_encode_bits(nr, B_BE_BFMEE_CSIINFO0_NR_MASK) | 779 u16_encode_bits(ng, B_BE_BFMEE_CSIINFO0_NG_MASK) | 780 u16_encode_bits(cb, B_BE_BFMEE_CSIINFO0_CB_MASK) | 781 u16_encode_bits(cs, B_BE_BFMEE_CSIINFO0_CS_MASK) | 782 u16_encode_bits(ldpc_en, B_BE_BFMEE_CSIINFO0_LDPC_EN) | 783 u16_encode_bits(stbc_en, B_BE_BFMEE_CSIINFO0_STBC_EN); 784 785 if (port_sel == 0) 786 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, 787 mac_idx); 788 else 789 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_1, 790 mac_idx); 791 792 rtw89_write16(rtwdev, reg, val); 793 794 return 0; 795 } 796 797 static int rtw89_mac_csi_rrsc_be(struct rtw89_dev *rtwdev, 798 struct ieee80211_vif *vif, 799 struct ieee80211_sta *sta) 800 { 801 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 802 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 803 u8 mac_idx = rtwvif->mac_idx; 804 int ret; 805 u32 reg; 806 807 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 808 if (ret) 809 return ret; 810 811 if (sta->deflink.he_cap.has_he) { 812 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 813 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 814 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 815 } 816 if (sta->deflink.vht_cap.vht_supported) { 817 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 818 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 819 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 820 } 821 if (sta->deflink.ht_cap.ht_supported) { 822 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 823 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 824 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 825 } 826 827 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 828 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL); 829 rtw89_write32_clr(rtwdev, reg, B_BE_BFMEE_CSI_FORCE_RETE_EN); 830 831 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RRSC, mac_idx); 832 rtw89_write32(rtwdev, reg, rrsc); 833 834 return 0; 835 } 836 837 static void rtw89_mac_bf_assoc_be(struct rtw89_dev *rtwdev, 838 struct ieee80211_vif *vif, 839 struct ieee80211_sta *sta) 840 { 841 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 842 843 if (rtw89_sta_has_beamformer_cap(sta)) { 844 rtw89_debug(rtwdev, RTW89_DBG_BF, 845 "initialize bfee for new association\n"); 846 rtw89_mac_init_bfee_be(rtwdev, rtwvif->mac_idx); 847 rtw89_mac_set_csi_para_reg_be(rtwdev, vif, sta); 848 rtw89_mac_csi_rrsc_be(rtwdev, vif, sta); 849 } 850 } 851 852 static void dump_err_status_dispatcher_be(struct rtw89_dev *rtwdev) 853 { 854 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x ", 855 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 856 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 857 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 858 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x ", 859 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 860 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 861 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 862 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x ", 863 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 864 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 865 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 866 } 867 868 static void rtw89_mac_dump_qta_lost_be(struct rtw89_dev *rtwdev) 869 { 870 struct rtw89_mac_dle_dfi_qempty qempty; 871 struct rtw89_mac_dle_dfi_quota quota; 872 struct rtw89_mac_dle_dfi_ctrl ctrl; 873 u32 val, not_empty, i; 874 int ret; 875 876 qempty.dle_type = DLE_CTRL_TYPE_PLE; 877 qempty.grpsel = 0; 878 qempty.qempty = ~(u32)0; 879 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 880 if (ret) 881 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 882 else 883 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 884 885 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 886 if (!(not_empty & BIT(0))) 887 continue; 888 ctrl.type = DLE_CTRL_TYPE_PLE; 889 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 890 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 891 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 892 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 893 if (ret) 894 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 895 else 896 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 897 u32_get_bits(ctrl.out_data, 898 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 899 } 900 901 quota.dle_type = DLE_CTRL_TYPE_PLE; 902 quota.qtaid = 6; 903 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 904 if (ret) 905 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 906 else 907 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 908 quota.rsv_pgnum, quota.use_pgnum); 909 910 val = rtw89_read32(rtwdev, R_BE_PLE_QTA6_CFG); 911 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 912 u32_get_bits(val, B_BE_PLE_Q6_MIN_SIZE_MASK)); 913 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 914 u32_get_bits(val, B_BE_PLE_Q6_MAX_SIZE_MASK)); 915 val = rtw89_read32(rtwdev, R_BE_RX_FLTR_OPT); 916 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_BE_RX_MPDU_MAX_LEN=0x%x\n", 917 u32_get_bits(val, B_BE_RX_MPDU_MAX_LEN_MASK)); 918 rtw89_info(rtwdev, "R_BE_RSP_CHK_SIG=0x%08x\n", 919 rtw89_read32(rtwdev, R_BE_RSP_CHK_SIG)); 920 rtw89_info(rtwdev, "R_BE_TRXPTCL_RESP_0=0x%08x\n", 921 rtw89_read32(rtwdev, R_BE_TRXPTCL_RESP_0)); 922 923 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 924 quota.dle_type = DLE_CTRL_TYPE_PLE; 925 quota.qtaid = 7; 926 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 927 if (ret) 928 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 929 else 930 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 931 quota.rsv_pgnum, quota.use_pgnum); 932 933 val = rtw89_read32(rtwdev, R_BE_PLE_QTA7_CFG); 934 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 935 u32_get_bits(val, B_BE_PLE_Q7_MIN_SIZE_MASK)); 936 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 937 u32_get_bits(val, B_BE_PLE_Q7_MAX_SIZE_MASK)); 938 val = rtw89_read32(rtwdev, R_BE_RX_FLTR_OPT_C1); 939 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_BE_RX_MPDU_MAX_LEN=0x%x\n", 940 u32_get_bits(val, B_BE_RX_MPDU_MAX_LEN_MASK)); 941 rtw89_info(rtwdev, "R_BE_RSP_CHK_SIG_C1=0x%08x\n", 942 rtw89_read32(rtwdev, R_BE_RSP_CHK_SIG_C1)); 943 rtw89_info(rtwdev, "R_BE_TRXPTCL_RESP_0_C1=0x%08x\n", 944 rtw89_read32(rtwdev, R_BE_TRXPTCL_RESP_0_C1)); 945 } 946 947 rtw89_info(rtwdev, "R_BE_DLE_EMPTY0=0x%08x\n", 948 rtw89_read32(rtwdev, R_BE_DLE_EMPTY0)); 949 rtw89_info(rtwdev, "R_BE_DLE_EMPTY1=0x%08x\n", 950 rtw89_read32(rtwdev, R_BE_DLE_EMPTY1)); 951 952 dump_err_status_dispatcher_be(rtwdev); 953 } 954 955 static void rtw89_mac_dump_cmac_err_status_be(struct rtw89_dev *rtwdev, 956 u8 band) 957 { 958 u32 offset = 0; 959 u32 cmac_err; 960 int ret; 961 962 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 963 if (ret) { 964 rtw89_info(rtwdev, "[CMAC] : CMAC%d not enabled\n", band); 965 return; 966 } 967 968 if (band) 969 offset = RTW89_MAC_BE_BAND_REG_OFFSET; 970 971 cmac_err = rtw89_read32(rtwdev, R_BE_CMAC_ERR_ISR + offset); 972 rtw89_info(rtwdev, "R_BE_CMAC_ERR_ISR [%d]=0x%08x\n", band, 973 rtw89_read32(rtwdev, R_BE_CMAC_ERR_ISR + offset)); 974 rtw89_info(rtwdev, "R_BE_CMAC_FUNC_EN [%d]=0x%08x\n", band, 975 rtw89_read32(rtwdev, R_BE_CMAC_FUNC_EN + offset)); 976 rtw89_info(rtwdev, "R_BE_CK_EN [%d]=0x%08x\n", band, 977 rtw89_read32(rtwdev, R_BE_CK_EN + offset)); 978 979 if (cmac_err & B_BE_SCHEDULE_TOP_ERR_IND) { 980 rtw89_info(rtwdev, "R_BE_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 981 rtw89_read32(rtwdev, R_BE_SCHEDULE_ERR_IMR + offset)); 982 rtw89_info(rtwdev, "R_BE_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 983 rtw89_read32(rtwdev, R_BE_SCHEDULE_ERR_ISR + offset)); 984 } 985 986 if (cmac_err & B_BE_PTCL_TOP_ERR_IND) { 987 rtw89_info(rtwdev, "R_BE_PTCL_IMR0 [%d]=0x%08x\n", band, 988 rtw89_read32(rtwdev, R_BE_PTCL_IMR0 + offset)); 989 rtw89_info(rtwdev, "R_BE_PTCL_ISR0 [%d]=0x%08x\n", band, 990 rtw89_read32(rtwdev, R_BE_PTCL_ISR0 + offset)); 991 rtw89_info(rtwdev, "R_BE_PTCL_IMR1 [%d]=0x%08x\n", band, 992 rtw89_read32(rtwdev, R_BE_PTCL_IMR1 + offset)); 993 rtw89_info(rtwdev, "R_BE_PTCL_ISR1 [%d]=0x%08x\n", band, 994 rtw89_read32(rtwdev, R_BE_PTCL_ISR1 + offset)); 995 } 996 997 if (cmac_err & B_BE_DMA_TOP_ERR_IND) { 998 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_IMR [%d]=0x%08x\n", band, 999 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_IMR + offset)); 1000 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG [%d]=0x%08x\n", band, 1001 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG + offset)); 1002 rtw89_info(rtwdev, "R_BE_TX_ERROR_FLAG_IMR [%d]=0x%08x\n", band, 1003 rtw89_read32(rtwdev, R_BE_TX_ERROR_FLAG_IMR + offset)); 1004 rtw89_info(rtwdev, "R_BE_TX_ERROR_FLAG [%d]=0x%08x\n", band, 1005 rtw89_read32(rtwdev, R_BE_TX_ERROR_FLAG + offset)); 1006 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_IMR_1 [%d]=0x%08x\n", band, 1007 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_IMR_1 + offset)); 1008 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_1 [%d]=0x%08x\n", band, 1009 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_1 + offset)); 1010 } 1011 1012 if (cmac_err & B_BE_PHYINTF_ERR_IND) { 1013 rtw89_info(rtwdev, "R_BE_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1014 rtw89_read32(rtwdev, R_BE_PHYINFO_ERR_IMR_V1 + offset)); 1015 rtw89_info(rtwdev, "R_BE_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 1016 rtw89_read32(rtwdev, R_BE_PHYINFO_ERR_ISR + offset)); 1017 } 1018 1019 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1020 rtw89_info(rtwdev, "R_BE_TXPWR_ERR_FLAG [%d]=0x%08x\n", band, 1021 rtw89_read32(rtwdev, R_BE_TXPWR_ERR_FLAG + offset)); 1022 rtw89_info(rtwdev, "R_BE_TXPWR_ERR_IMR [%d]=0x%08x\n", band, 1023 rtw89_read32(rtwdev, R_BE_TXPWR_ERR_IMR + offset)); 1024 } 1025 1026 if (cmac_err & (B_BE_WMAC_RX_ERR_IND | B_BE_WMAC_TX_ERR_IND | 1027 B_BE_WMAC_RX_IDLETO_IDCT | B_BE_PTCL_TX_IDLETO_IDCT)) { 1028 rtw89_info(rtwdev, "R_BE_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1029 rtw89_read32(rtwdev, R_BE_DBGSEL_TRXPTCL + offset)); 1030 rtw89_info(rtwdev, "R_BE_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 1031 rtw89_read32(rtwdev, R_BE_TRXPTCL_ERROR_INDICA_MASK + offset)); 1032 rtw89_info(rtwdev, "R_BE_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 1033 rtw89_read32(rtwdev, R_BE_TRXPTCL_ERROR_INDICA + offset)); 1034 rtw89_info(rtwdev, "R_BE_RX_ERR_IMR [%d]=0x%08x\n", band, 1035 rtw89_read32(rtwdev, R_BE_RX_ERR_IMR + offset)); 1036 rtw89_info(rtwdev, "R_BE_RX_ERR_ISR [%d]=0x%08x\n", band, 1037 rtw89_read32(rtwdev, R_BE_RX_ERR_ISR + offset)); 1038 } 1039 1040 rtw89_info(rtwdev, "R_BE_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1041 rtw89_read32(rtwdev, R_BE_CMAC_ERR_IMR + offset)); 1042 } 1043 1044 static void rtw89_mac_dump_err_status_be(struct rtw89_dev *rtwdev, 1045 enum mac_ax_err_info err) 1046 { 1047 if (err != MAC_AX_ERR_L1_ERR_DMAC && 1048 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 1049 err != MAC_AX_ERR_L0_ERR_CMAC0 && 1050 err != MAC_AX_ERR_L0_ERR_CMAC1 && 1051 err != MAC_AX_ERR_RXI300) 1052 return; 1053 1054 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 1055 rtw89_info(rtwdev, "R_BE_SER_DBG_INFO=0x%08x\n", 1056 rtw89_read32(rtwdev, R_BE_SER_DBG_INFO)); 1057 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT=0x%08x\n", 1058 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT)); 1059 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT1=0x%08x\n", 1060 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT1)); 1061 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT2=0x%08x\n", 1062 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT2)); 1063 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT3=0x%08x\n", 1064 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT3)); 1065 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 1066 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT_C1=0x%08x\n", 1067 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT_C1)); 1068 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT1_C1=0x%08x\n", 1069 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT1_C1)); 1070 } 1071 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_0=0x%08x\n", 1072 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_0)); 1073 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_1=0x%08x\n", 1074 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_1)); 1075 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_2=0x%08x\n", 1076 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_2)); 1077 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_3=0x%08x\n", 1078 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_3)); 1079 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_4=0x%08x\n", 1080 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_4)); 1081 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_5=0x%08x\n", 1082 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_5)); 1083 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_6=0x%08x\n", 1084 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_6)); 1085 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_7=0x%08x\n", 1086 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_7)); 1087 1088 rtw89_mac_dump_dmac_err_status(rtwdev); 1089 rtw89_mac_dump_cmac_err_status_be(rtwdev, RTW89_MAC_0); 1090 rtw89_mac_dump_cmac_err_status_be(rtwdev, RTW89_MAC_1); 1091 1092 rtwdev->hci.ops->dump_err_status(rtwdev); 1093 1094 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 1095 rtw89_mac_dump_l0_to_l1(rtwdev, err); 1096 1097 rtw89_info(rtwdev, "<---\n"); 1098 } 1099 1100 static bool mac_is_txq_empty_be(struct rtw89_dev *rtwdev) 1101 { 1102 struct rtw89_mac_dle_dfi_qempty qempty; 1103 u32 val32, msk32; 1104 u32 grpnum; 1105 int ret; 1106 int i; 1107 1108 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1109 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1110 1111 for (i = 0; i < grpnum; i++) { 1112 qempty.grpsel = i; 1113 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1114 if (ret) { 1115 rtw89_warn(rtwdev, 1116 "%s: failed to dle dfi acq empty: %d\n", 1117 __func__, ret); 1118 return false; 1119 } 1120 1121 /* Each acq group contains 32 queues (8 macid * 4 acq), 1122 * but here, we can simply check if all bits are set. 1123 */ 1124 if (qempty.qempty != MASKDWORD) 1125 return false; 1126 } 1127 1128 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1129 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1130 if (ret) { 1131 rtw89_warn(rtwdev, "%s: failed to dle dfi mgq empty: %d\n", 1132 __func__, ret); 1133 return false; 1134 } 1135 1136 msk32 = B_CMAC0_MGQ_NORMAL_BE | B_CMAC1_MGQ_NORMAL_BE; 1137 if ((qempty.qempty & msk32) != msk32) 1138 return false; 1139 1140 msk32 = B_BE_WDE_EMPTY_QUE_OTHERS; 1141 val32 = rtw89_read32(rtwdev, R_BE_DLE_EMPTY0); 1142 return (val32 & msk32) == msk32; 1143 } 1144 1145 const struct rtw89_mac_gen_def rtw89_mac_gen_be = { 1146 .band1_offset = RTW89_MAC_BE_BAND_REG_OFFSET, 1147 .filter_model_addr = R_BE_FILTER_MODEL_ADDR, 1148 .indir_access_addr = R_BE_INDIR_ACCESS_ENTRY, 1149 .mem_base_addrs = rtw89_mac_mem_base_addrs_be, 1150 .rx_fltr = R_BE_RX_FLTR_OPT, 1151 .port_base = &rtw89_port_base_be, 1152 .agg_len_ht = R_BE_AGG_LEN_HT_0, 1153 1154 .muedca_ctrl = { 1155 .addr = R_BE_MUEDCA_EN, 1156 .mask = B_BE_MUEDCA_EN_0 | B_BE_SET_MUEDCATIMER_TF_0, 1157 }, 1158 .bfee_ctrl = { 1159 .addr = R_BE_BFMEE_RESP_OPTION, 1160 .mask = B_BE_BFMEE_HT_NDPA_EN | B_BE_BFMEE_VHT_NDPA_EN | 1161 B_BE_BFMEE_HE_NDPA_EN | B_BE_BFMEE_EHT_NDPA_EN, 1162 }, 1163 1164 .check_mac_en = rtw89_mac_check_mac_en_be, 1165 .hci_func_en = rtw89_mac_hci_func_en_be, 1166 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_be, 1167 .dle_func_en = dle_func_en_be, 1168 .dle_clk_en = dle_clk_en_be, 1169 .bf_assoc = rtw89_mac_bf_assoc_be, 1170 1171 .dle_mix_cfg = dle_mix_cfg_be, 1172 .chk_dle_rdy = chk_dle_rdy_be, 1173 .dle_buf_req = dle_buf_req_be, 1174 .hfc_func_en = hfc_func_en_be, 1175 .hfc_h2c_cfg = hfc_h2c_cfg_be, 1176 .hfc_mix_cfg = hfc_mix_cfg_be, 1177 .hfc_get_mix_info = hfc_get_mix_info_be, 1178 .wde_quota_cfg = wde_quota_cfg_be, 1179 .ple_quota_cfg = ple_quota_cfg_be, 1180 .set_cpuio = set_cpuio_be, 1181 1182 .disable_cpu = rtw89_mac_disable_cpu_be, 1183 .fwdl_enable_wcpu = rtw89_mac_fwdl_enable_wcpu_be, 1184 .fwdl_get_status = fwdl_get_status_be, 1185 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_be, 1186 .parse_efuse_map = rtw89_parse_efuse_map_be, 1187 .parse_phycap_map = rtw89_parse_phycap_map_be, 1188 .cnv_efuse_state = rtw89_cnv_efuse_state_be, 1189 1190 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_be, 1191 1192 .write_xtal_si = rtw89_mac_write_xtal_si_be, 1193 .read_xtal_si = rtw89_mac_read_xtal_si_be, 1194 1195 .dump_qta_lost = rtw89_mac_dump_qta_lost_be, 1196 .dump_err_status = rtw89_mac_dump_err_status_be, 1197 1198 .is_txq_empty = mac_is_txq_empty_be, 1199 }; 1200 EXPORT_SYMBOL(rtw89_mac_gen_be); 1201