1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "debug.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "reg.h" 9 10 static const u32 rtw89_mac_mem_base_addrs_be[RTW89_MAC_MEM_NUM] = { 11 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR_BE, 12 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR_BE, 13 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR_BE, 14 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR_BE, 15 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR_BE, 16 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR_BE, 17 [RTW89_MAC_MEM_SECURITY_CAM] = SEC_CAM_BASE_ADDR_BE, 18 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR_BE, 19 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR_BE, 20 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR_BE, 21 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR_BE, 22 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR_BE, 23 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR_BE, 24 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR_BE, 25 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR_BE, 26 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR_BE, 27 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR_BE, 28 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR_BE, 29 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR_BE, 30 [RTW89_MAC_MEM_WD_PAGE] = WD_PAGE_BASE_ADDR_BE, 31 }; 32 33 static const struct rtw89_port_reg rtw89_port_base_be = { 34 .port_cfg = R_BE_PORT_CFG_P0, 35 .tbtt_prohib = R_BE_TBTT_PROHIB_P0, 36 .bcn_area = R_BE_BCN_AREA_P0, 37 .bcn_early = R_BE_BCNERLYINT_CFG_P0, 38 .tbtt_early = R_BE_TBTTERLYINT_CFG_P0, 39 .tbtt_agg = R_BE_TBTT_AGG_P0, 40 .bcn_space = R_BE_BCN_SPACE_CFG_P0, 41 .bcn_forcetx = R_BE_BCN_FORCETX_P0, 42 .bcn_err_cnt = R_BE_BCN_ERR_CNT_P0, 43 .bcn_err_flag = R_BE_BCN_ERR_FLAG_P0, 44 .dtim_ctrl = R_BE_DTIM_CTRL_P0, 45 .tbtt_shift = R_BE_TBTT_SHIFT_P0, 46 .bcn_cnt_tmr = R_BE_BCN_CNT_TMR_P0, 47 .tsftr_l = R_BE_TSFTR_LOW_P0, 48 .tsftr_h = R_BE_TSFTR_HIGH_P0, 49 .md_tsft = R_BE_WMTX_MOREDATA_TSFT_STMP_CTL, 50 .bss_color = R_BE_PTCL_BSS_COLOR_0, 51 .mbssid = R_BE_MBSSID_CTRL, 52 .mbssid_drop = R_BE_MBSSID_DROP_0, 53 .tsf_sync = R_BE_PORT_0_TSF_SYNC, 54 .hiq_win = {R_BE_P0MB_HGQ_WINDOW_CFG_0, R_BE_PORT_HGQ_WINDOW_CFG, 55 R_BE_PORT_HGQ_WINDOW_CFG + 1, R_BE_PORT_HGQ_WINDOW_CFG + 2, 56 R_BE_PORT_HGQ_WINDOW_CFG + 3}, 57 }; 58 59 static void rtw89_mac_disable_cpu_be(struct rtw89_dev *rtwdev) 60 { 61 u32 val32; 62 63 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 64 65 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN); 66 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET); 67 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN); 68 69 val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL); 70 val32 &= B_BE_RUN_ENV_MASK; 71 rtw89_write32(rtwdev, R_BE_WCPU_FW_CTRL, val32); 72 73 rtw89_write32_set(rtwdev, R_BE_DCPU_PLATFORM_ENABLE, B_BE_DCPU_PLATFORM_EN); 74 75 rtw89_write32(rtwdev, R_BE_UDM0, 0); 76 rtw89_write32(rtwdev, R_BE_HALT_C2H, 0); 77 rtw89_write32(rtwdev, R_BE_UDM2, 0); 78 } 79 80 static void set_cpu_en(struct rtw89_dev *rtwdev, bool include_bb) 81 { 82 u32 set = B_BE_WLANCPU_FWDL_EN; 83 84 if (include_bb) 85 set |= B_BE_BBMCU0_FWDL_EN; 86 87 rtw89_write32_set(rtwdev, R_BE_WCPU_FW_CTRL, set); 88 } 89 90 static int wcpu_on(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw) 91 { 92 u32 val32; 93 int ret; 94 95 rtw89_write32_set(rtwdev, R_BE_UDM0, B_BE_UDM0_DBG_MODE_CTRL); 96 97 val32 = rtw89_read32(rtwdev, R_BE_HALT_C2H); 98 if (val32) { 99 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n"); 100 rtw89_warn(rtwdev, "[SER] %s: R_BE_HALT_C2H = 0x%x\n", __func__, val32); 101 } 102 val32 = rtw89_read32(rtwdev, R_BE_UDM1); 103 if (val32) { 104 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n"); 105 rtw89_warn(rtwdev, "[SER] %s: R_BE_UDM1 = 0x%x\n", __func__, val32); 106 } 107 val32 = rtw89_read32(rtwdev, R_BE_UDM2); 108 if (val32) { 109 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n"); 110 rtw89_warn(rtwdev, "[SER] %s: R_BE_UDM2 = 0x%x\n", __func__, val32); 111 } 112 113 rtw89_write32(rtwdev, R_BE_UDM1, 0); 114 rtw89_write32(rtwdev, R_BE_UDM2, 0); 115 rtw89_write32(rtwdev, R_BE_HALT_H2C, 0); 116 rtw89_write32(rtwdev, R_BE_HALT_C2H, 0); 117 rtw89_write32(rtwdev, R_BE_HALT_H2C_CTRL, 0); 118 rtw89_write32(rtwdev, R_BE_HALT_C2H_CTRL, 0); 119 120 rtw89_write32_set(rtwdev, R_BE_SYS_CLK_CTRL, B_BE_CPU_CLK_EN); 121 rtw89_write32_clr(rtwdev, R_BE_SYS_CFG5, 122 B_BE_WDT_WAKE_PCIE_EN | B_BE_WDT_WAKE_USB_EN); 123 rtw89_write32_clr(rtwdev, R_BE_WCPU_FW_CTRL, 124 B_BE_WDT_PLT_RST_EN | B_BE_WCPU_ROM_CUT_GET); 125 126 rtw89_write16_mask(rtwdev, R_BE_BOOT_REASON, B_BE_BOOT_REASON_MASK, boot_reason); 127 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN); 128 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET); 129 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN); 130 131 if (!dlfw) { 132 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 133 if (ret) 134 return ret; 135 } 136 137 return 0; 138 } 139 140 static int rtw89_mac_fwdl_enable_wcpu_be(struct rtw89_dev *rtwdev, 141 u8 boot_reason, bool dlfw, 142 bool include_bb) 143 { 144 set_cpu_en(rtwdev, include_bb); 145 146 return wcpu_on(rtwdev, boot_reason, dlfw); 147 } 148 149 static const u8 fwdl_status_map[] = { 150 [0] = RTW89_FWDL_INITIAL_STATE, 151 [1] = RTW89_FWDL_FWDL_ONGOING, 152 [4] = RTW89_FWDL_CHECKSUM_FAIL, 153 [5] = RTW89_FWDL_SECURITY_FAIL, 154 [6] = RTW89_FWDL_SECURITY_FAIL, 155 [7] = RTW89_FWDL_CV_NOT_MATCH, 156 [8] = RTW89_FWDL_RSVD0, 157 [2] = RTW89_FWDL_WCPU_FWDL_RDY, 158 [3] = RTW89_FWDL_WCPU_FW_INIT_RDY, 159 [9] = RTW89_FWDL_RSVD0, 160 }; 161 162 static u8 fwdl_get_status_be(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 163 { 164 bool check_pass = false; 165 u32 val32; 166 u8 st; 167 168 val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL); 169 170 switch (type) { 171 case RTW89_FWDL_CHECK_WCPU_FWDL_DONE: 172 check_pass = !(val32 & B_BE_WLANCPU_FWDL_EN); 173 break; 174 case RTW89_FWDL_CHECK_DCPU_FWDL_DONE: 175 check_pass = !(val32 & B_BE_DATACPU_FWDL_EN); 176 break; 177 case RTW89_FWDL_CHECK_BB0_FWDL_DONE: 178 check_pass = !(val32 & B_BE_BBMCU0_FWDL_EN); 179 break; 180 case RTW89_FWDL_CHECK_BB1_FWDL_DONE: 181 check_pass = !(val32 & B_BE_BBMCU1_FWDL_EN); 182 break; 183 default: 184 break; 185 } 186 187 if (check_pass) 188 return RTW89_FWDL_WCPU_FW_INIT_RDY; 189 190 st = u32_get_bits(val32, B_BE_WCPU_FWDL_STATUS_MASK); 191 if (st < ARRAY_SIZE(fwdl_status_map)) 192 return fwdl_status_map[st]; 193 194 return st; 195 } 196 197 static int rtw89_fwdl_check_path_ready_be(struct rtw89_dev *rtwdev, 198 bool h2c_or_fwdl) 199 { 200 u32 check = h2c_or_fwdl ? B_BE_H2C_PATH_RDY : B_BE_DLFW_PATH_RDY; 201 u32 val; 202 203 return read_poll_timeout_atomic(rtw89_read32, val, val & check, 204 1, 1000000, false, 205 rtwdev, R_BE_WCPU_FW_CTRL); 206 } 207 208 static bool rtw89_mac_get_txpwr_cr_be(struct rtw89_dev *rtwdev, 209 enum rtw89_phy_idx phy_idx, 210 u32 reg_base, u32 *cr) 211 { 212 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 213 enum rtw89_qta_mode mode = dle_mem->mode; 214 int ret; 215 216 ret = rtw89_mac_check_mac_en(rtwdev, (enum rtw89_mac_idx)phy_idx, 217 RTW89_CMAC_SEL); 218 if (ret) { 219 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) 220 return false; 221 222 rtw89_err(rtwdev, "[TXPWR] check mac enable failed\n"); 223 return false; 224 } 225 226 if (reg_base < R_BE_PWR_MODULE || reg_base > R_BE_CMAC_FUNC_EN_C1) { 227 rtw89_err(rtwdev, "[TXPWR] reg_base=0x%x exceed txpwr cr\n", 228 reg_base); 229 return false; 230 } 231 232 *cr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 233 234 if (*cr >= CMAC1_START_ADDR_BE && *cr <= CMAC1_END_ADDR_BE) { 235 if (mode == RTW89_QTA_SCC) { 236 rtw89_err(rtwdev, 237 "[TXPWR] addr=0x%x but hw not enable\n", 238 *cr); 239 return false; 240 } 241 } 242 243 return true; 244 } 245 246 const struct rtw89_mac_gen_def rtw89_mac_gen_be = { 247 .band1_offset = RTW89_MAC_BE_BAND_REG_OFFSET, 248 .filter_model_addr = R_BE_FILTER_MODEL_ADDR, 249 .indir_access_addr = R_BE_INDIR_ACCESS_ENTRY, 250 .mem_base_addrs = rtw89_mac_mem_base_addrs_be, 251 .rx_fltr = R_BE_RX_FLTR_OPT, 252 .port_base = &rtw89_port_base_be, 253 254 .disable_cpu = rtw89_mac_disable_cpu_be, 255 .fwdl_enable_wcpu = rtw89_mac_fwdl_enable_wcpu_be, 256 .fwdl_get_status = fwdl_get_status_be, 257 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_be, 258 259 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_be, 260 }; 261 EXPORT_SYMBOL(rtw89_mac_gen_be); 262