1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_MAC_H__ 6 #define __RTW89_MAC_H__ 7 8 #include "core.h" 9 #include "reg.h" 10 11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000 12 #define ADDR_CAM_ENT_SIZE 0x40 13 #define ADDR_CAM_ENT_SHORT_SIZE 0x20 14 #define BSSID_CAM_ENT_SIZE 0x08 15 #define HFC_PAGE_UNIT 64 16 #define RPWM_TRY_CNT 3 17 18 enum rtw89_mac_hwmod_sel { 19 RTW89_DMAC_SEL = 0, 20 RTW89_CMAC_SEL = 1, 21 22 RTW89_MAC_INVALID, 23 }; 24 25 enum rtw89_mac_fwd_target { 26 RTW89_FWD_DONT_CARE = 0, 27 RTW89_FWD_TO_HOST = 1, 28 RTW89_FWD_TO_WLAN_CPU = 2 29 }; 30 31 enum rtw89_mac_wd_dma_intvl { 32 RTW89_MAC_WD_DMA_INTVL_0S, 33 RTW89_MAC_WD_DMA_INTVL_256NS, 34 RTW89_MAC_WD_DMA_INTVL_512NS, 35 RTW89_MAC_WD_DMA_INTVL_768NS, 36 RTW89_MAC_WD_DMA_INTVL_1US, 37 RTW89_MAC_WD_DMA_INTVL_1_5US, 38 RTW89_MAC_WD_DMA_INTVL_2US, 39 RTW89_MAC_WD_DMA_INTVL_4US, 40 RTW89_MAC_WD_DMA_INTVL_8US, 41 RTW89_MAC_WD_DMA_INTVL_16US, 42 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE 43 }; 44 45 enum rtw89_mac_multi_tag_num { 46 RTW89_MAC_TAG_NUM_1, 47 RTW89_MAC_TAG_NUM_2, 48 RTW89_MAC_TAG_NUM_3, 49 RTW89_MAC_TAG_NUM_4, 50 RTW89_MAC_TAG_NUM_5, 51 RTW89_MAC_TAG_NUM_6, 52 RTW89_MAC_TAG_NUM_7, 53 RTW89_MAC_TAG_NUM_8, 54 RTW89_MAC_TAG_NUM_DEF = 0xFE 55 }; 56 57 enum rtw89_mac_lbc_tmr { 58 RTW89_MAC_LBC_TMR_8US = 0, 59 RTW89_MAC_LBC_TMR_16US, 60 RTW89_MAC_LBC_TMR_32US, 61 RTW89_MAC_LBC_TMR_64US, 62 RTW89_MAC_LBC_TMR_128US, 63 RTW89_MAC_LBC_TMR_256US, 64 RTW89_MAC_LBC_TMR_512US, 65 RTW89_MAC_LBC_TMR_1MS, 66 RTW89_MAC_LBC_TMR_2MS, 67 RTW89_MAC_LBC_TMR_4MS, 68 RTW89_MAC_LBC_TMR_8MS, 69 RTW89_MAC_LBC_TMR_DEF = 0xFE 70 }; 71 72 enum rtw89_mac_cpuio_op_cmd_type { 73 CPUIO_OP_CMD_GET_1ST_PID = 0, 74 CPUIO_OP_CMD_GET_NEXT_PID = 1, 75 CPUIO_OP_CMD_ENQ_TO_TAIL = 4, 76 CPUIO_OP_CMD_ENQ_TO_HEAD = 5, 77 CPUIO_OP_CMD_DEQ = 8, 78 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, 79 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 80 }; 81 82 enum rtw89_mac_wde_dle_port_id { 83 WDE_DLE_PORT_ID_DISPATCH = 0, 84 WDE_DLE_PORT_ID_PKTIN = 1, 85 WDE_DLE_PORT_ID_CMAC0 = 3, 86 WDE_DLE_PORT_ID_CMAC1 = 4, 87 WDE_DLE_PORT_ID_CPU_IO = 6, 88 WDE_DLE_PORT_ID_WDRLS = 7, 89 WDE_DLE_PORT_ID_END = 8 90 }; 91 92 enum rtw89_mac_wde_dle_queid_wdrls { 93 WDE_DLE_QUEID_TXOK = 0, 94 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, 95 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, 96 WDE_DLE_QUEID_DROP_MACID_DROP = 3, 97 WDE_DLE_QUEID_NO_REPORT = 4 98 }; 99 100 enum rtw89_mac_ple_dle_port_id { 101 PLE_DLE_PORT_ID_DISPATCH = 0, 102 PLE_DLE_PORT_ID_MPDU = 1, 103 PLE_DLE_PORT_ID_SEC = 2, 104 PLE_DLE_PORT_ID_CMAC0 = 3, 105 PLE_DLE_PORT_ID_CMAC1 = 4, 106 PLE_DLE_PORT_ID_WDRLS = 5, 107 PLE_DLE_PORT_ID_CPU_IO = 6, 108 PLE_DLE_PORT_ID_PLRLS = 7, 109 PLE_DLE_PORT_ID_END = 8 110 }; 111 112 enum rtw89_mac_ple_dle_queid_plrls { 113 PLE_DLE_QUEID_NO_REPORT = 0x0 114 }; 115 116 enum rtw89_machdr_frame_type { 117 RTW89_MGNT = 0, 118 RTW89_CTRL = 1, 119 RTW89_DATA = 2, 120 }; 121 122 enum rtw89_mac_dle_dfi_type { 123 DLE_DFI_TYPE_FREEPG = 0, 124 DLE_DFI_TYPE_QUOTA = 1, 125 DLE_DFI_TYPE_PAGELLT = 2, 126 DLE_DFI_TYPE_PKTINFO = 3, 127 DLE_DFI_TYPE_PREPKTLLT = 4, 128 DLE_DFI_TYPE_NXTPKTLLT = 5, 129 DLE_DFI_TYPE_QLNKTBL = 6, 130 DLE_DFI_TYPE_QEMPTY = 7, 131 }; 132 133 enum rtw89_mac_dle_wde_quota_id { 134 WDE_QTAID_HOST_IF = 0, 135 WDE_QTAID_WLAN_CPU = 1, 136 WDE_QTAID_DATA_CPU = 2, 137 WDE_QTAID_PKTIN = 3, 138 WDE_QTAID_CPUIO = 4, 139 }; 140 141 enum rtw89_mac_dle_ple_quota_id { 142 PLE_QTAID_B0_TXPL = 0, 143 PLE_QTAID_B1_TXPL = 1, 144 PLE_QTAID_C2H = 2, 145 PLE_QTAID_H2C = 3, 146 PLE_QTAID_WLAN_CPU = 4, 147 PLE_QTAID_MPDU = 5, 148 PLE_QTAID_CMAC0_RX = 6, 149 PLE_QTAID_CMAC1_RX = 7, 150 PLE_QTAID_CMAC1_BBRPT = 8, 151 PLE_QTAID_WDRLS = 9, 152 PLE_QTAID_CPUIO = 10, 153 }; 154 155 enum rtw89_mac_dle_ctrl_type { 156 DLE_CTRL_TYPE_WDE = 0, 157 DLE_CTRL_TYPE_PLE = 1, 158 DLE_CTRL_TYPE_NUM = 2, 159 }; 160 161 enum rtw89_mac_ax_l0_to_l1_event { 162 MAC_AX_L0_TO_L1_CHIF_IDLE = 0, 163 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, 164 MAC_AX_L0_TO_L1_RLS_PKID = 2, 165 MAC_AX_L0_TO_L1_PTCL_IDLE = 3, 166 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, 167 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, 168 MAC_AX_L0_TO_L1_PCIE_STUCK = 6, 169 MAC_AX_L0_TO_L1_EVENT_MAX = 15, 170 }; 171 172 #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32) 173 174 enum rtw89_mac_dbg_port_sel { 175 /* CMAC 0 related */ 176 RTW89_DBG_PORT_SEL_PTCL_C0 = 0, 177 RTW89_DBG_PORT_SEL_SCH_C0, 178 RTW89_DBG_PORT_SEL_TMAC_C0, 179 RTW89_DBG_PORT_SEL_RMAC_C0, 180 RTW89_DBG_PORT_SEL_RMACST_C0, 181 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, 182 RTW89_DBG_PORT_SEL_TRXPTCL_C0, 183 RTW89_DBG_PORT_SEL_TX_INFOL_C0, 184 RTW89_DBG_PORT_SEL_TX_INFOH_C0, 185 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, 186 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, 187 /* CMAC 1 related */ 188 RTW89_DBG_PORT_SEL_PTCL_C1, 189 RTW89_DBG_PORT_SEL_SCH_C1, 190 RTW89_DBG_PORT_SEL_TMAC_C1, 191 RTW89_DBG_PORT_SEL_RMAC_C1, 192 RTW89_DBG_PORT_SEL_RMACST_C1, 193 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, 194 RTW89_DBG_PORT_SEL_TRXPTCL_C1, 195 RTW89_DBG_PORT_SEL_TX_INFOL_C1, 196 RTW89_DBG_PORT_SEL_TX_INFOH_C1, 197 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, 198 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, 199 /* DLE related */ 200 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, 201 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, 202 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, 203 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, 204 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, 205 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, 206 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, 207 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, 208 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, 209 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, 210 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, 211 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, 212 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, 213 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, 214 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, 215 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, 216 RTW89_DBG_PORT_SEL_PKTINFO, 217 /* DISPATCHER related */ 218 RTW89_DBG_PORT_SEL_DSPT_HDT_TX0, 219 RTW89_DBG_PORT_SEL_DSPT_HDT_TX1, 220 RTW89_DBG_PORT_SEL_DSPT_HDT_TX2, 221 RTW89_DBG_PORT_SEL_DSPT_HDT_TX3, 222 RTW89_DBG_PORT_SEL_DSPT_HDT_TX4, 223 RTW89_DBG_PORT_SEL_DSPT_HDT_TX5, 224 RTW89_DBG_PORT_SEL_DSPT_HDT_TX6, 225 RTW89_DBG_PORT_SEL_DSPT_HDT_TX7, 226 RTW89_DBG_PORT_SEL_DSPT_HDT_TX8, 227 RTW89_DBG_PORT_SEL_DSPT_HDT_TX9, 228 RTW89_DBG_PORT_SEL_DSPT_HDT_TXA, 229 RTW89_DBG_PORT_SEL_DSPT_HDT_TXB, 230 RTW89_DBG_PORT_SEL_DSPT_HDT_TXC, 231 RTW89_DBG_PORT_SEL_DSPT_HDT_TXD, 232 RTW89_DBG_PORT_SEL_DSPT_HDT_TXE, 233 RTW89_DBG_PORT_SEL_DSPT_HDT_TXF, 234 RTW89_DBG_PORT_SEL_DSPT_CDT_TX0, 235 RTW89_DBG_PORT_SEL_DSPT_CDT_TX1, 236 RTW89_DBG_PORT_SEL_DSPT_CDT_TX3, 237 RTW89_DBG_PORT_SEL_DSPT_CDT_TX4, 238 RTW89_DBG_PORT_SEL_DSPT_CDT_TX5, 239 RTW89_DBG_PORT_SEL_DSPT_CDT_TX6, 240 RTW89_DBG_PORT_SEL_DSPT_CDT_TX7, 241 RTW89_DBG_PORT_SEL_DSPT_CDT_TX8, 242 RTW89_DBG_PORT_SEL_DSPT_CDT_TX9, 243 RTW89_DBG_PORT_SEL_DSPT_CDT_TXA, 244 RTW89_DBG_PORT_SEL_DSPT_CDT_TXB, 245 RTW89_DBG_PORT_SEL_DSPT_CDT_TXC, 246 RTW89_DBG_PORT_SEL_DSPT_HDT_RX0, 247 RTW89_DBG_PORT_SEL_DSPT_HDT_RX1, 248 RTW89_DBG_PORT_SEL_DSPT_HDT_RX2, 249 RTW89_DBG_PORT_SEL_DSPT_HDT_RX3, 250 RTW89_DBG_PORT_SEL_DSPT_HDT_RX4, 251 RTW89_DBG_PORT_SEL_DSPT_HDT_RX5, 252 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0, 253 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0, 254 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1, 255 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2, 256 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1, 257 RTW89_DBG_PORT_SEL_DSPT_STF_CTRL, 258 RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL, 259 RTW89_DBG_PORT_SEL_DSPT_WDE_INTF, 260 RTW89_DBG_PORT_SEL_DSPT_PLE_INTF, 261 RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL, 262 /* PCIE related */ 263 RTW89_DBG_PORT_SEL_PCIE_TXDMA, 264 RTW89_DBG_PORT_SEL_PCIE_RXDMA, 265 RTW89_DBG_PORT_SEL_PCIE_CVT, 266 RTW89_DBG_PORT_SEL_PCIE_CXPL, 267 RTW89_DBG_PORT_SEL_PCIE_IO, 268 RTW89_DBG_PORT_SEL_PCIE_MISC, 269 RTW89_DBG_PORT_SEL_PCIE_MISC2, 270 271 /* keep last */ 272 RTW89_DBG_PORT_SEL_LAST, 273 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, 274 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, 275 }; 276 277 /* SRAM mem dump */ 278 #define R_AX_INDIR_ACCESS_ENTRY 0x40000 279 #define R_BE_INDIR_ACCESS_ENTRY 0x80000 280 281 #define AXIDMA_BASE_ADDR 0x18006000 282 #define STA_SCHED_BASE_ADDR 0x18808000 283 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 284 #define SECURITY_CAM_BASE_ADDR 0x18814000 285 #define WOW_CAM_BASE_ADDR 0x18815000 286 #define CMAC_TBL_BASE_ADDR 0x18840000 287 #define ADDR_CAM_BASE_ADDR 0x18850000 288 #define BSSID_CAM_BASE_ADDR 0x18853000 289 #define BA_CAM_BASE_ADDR 0x18854000 290 #define BCN_IE_CAM0_BASE_ADDR 0x18855000 291 #define SHARED_BUF_BASE_ADDR 0x18700000 292 #define DMAC_TBL_BASE_ADDR 0x18800000 293 #define SHCUT_MACHDR_BASE_ADDR 0x18800800 294 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000 295 #define TXD_FIFO_0_BASE_ADDR 0x18856200 296 #define TXD_FIFO_1_BASE_ADDR 0x188A1080 297 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */ 298 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */ 299 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000 300 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 301 #define CPU_LOCAL_BASE_ADDR 0x18003000 302 303 #define WD_PAGE_BASE_ADDR_BE 0x0 304 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000 305 #define AXIDMA_BASE_ADDR_BE 0x18006000 306 #define SHARED_BUF_BASE_ADDR_BE 0x18700000 307 #define DMAC_TBL_BASE_ADDR_BE 0x18800000 308 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800 309 #define STA_SCHED_BASE_ADDR_BE 0x18818000 310 #define NAT25_CAM_BASE_ADDR_BE 0x18820000 311 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000 312 #define SEC_CAM_BASE_ADDR_BE 0x18824000 313 #define WOW_CAM_BASE_ADDR_BE 0x18828000 314 #define MLD_TBL_BASE_ADDR_BE 0x18829000 315 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000 316 #define CMAC_TBL_BASE_ADDR_BE 0x18840000 317 #define ADDR_CAM_BASE_ADDR_BE 0x18850000 318 #define BSSID_CAM_BASE_ADDR_BE 0x18858000 319 #define BA_CAM_BASE_ADDR_BE 0x18859000 320 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000 321 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000 322 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000 323 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000 324 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000 325 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800 326 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000 327 328 #define CCTL_INFO_SIZE 32 329 330 enum rtw89_mac_mem_sel { 331 RTW89_MAC_MEM_AXIDMA, 332 RTW89_MAC_MEM_SHARED_BUF, 333 RTW89_MAC_MEM_DMAC_TBL, 334 RTW89_MAC_MEM_SHCUT_MACHDR, 335 RTW89_MAC_MEM_STA_SCHED, 336 RTW89_MAC_MEM_RXPLD_FLTR_CAM, 337 RTW89_MAC_MEM_SECURITY_CAM, 338 RTW89_MAC_MEM_WOW_CAM, 339 RTW89_MAC_MEM_CMAC_TBL, 340 RTW89_MAC_MEM_ADDR_CAM, 341 RTW89_MAC_MEM_BA_CAM, 342 RTW89_MAC_MEM_BCN_IE_CAM0, 343 RTW89_MAC_MEM_BCN_IE_CAM1, 344 RTW89_MAC_MEM_TXD_FIFO_0, 345 RTW89_MAC_MEM_TXD_FIFO_1, 346 RTW89_MAC_MEM_TXDATA_FIFO_0, 347 RTW89_MAC_MEM_TXDATA_FIFO_1, 348 RTW89_MAC_MEM_CPU_LOCAL, 349 RTW89_MAC_MEM_BSSID_CAM, 350 RTW89_MAC_MEM_TXD_FIFO_0_V1, 351 RTW89_MAC_MEM_TXD_FIFO_1_V1, 352 RTW89_MAC_MEM_WD_PAGE, 353 354 /* keep last */ 355 RTW89_MAC_MEM_NUM, 356 }; 357 358 enum rtw89_rpwm_req_pwr_state { 359 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, 360 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, 361 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, 362 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, 363 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, 364 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, 365 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, 366 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, 367 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, 368 }; 369 370 struct rtw89_pwr_cfg { 371 u16 addr; 372 u8 cv_msk; 373 u8 intf_msk; 374 u8 base:4; 375 u8 cmd:4; 376 u8 msk; 377 u8 val; 378 }; 379 380 enum rtw89_mac_c2h_ofld_func { 381 RTW89_MAC_C2H_FUNC_EFUSE_DUMP, 382 RTW89_MAC_C2H_FUNC_READ_RSP, 383 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, 384 RTW89_MAC_C2H_FUNC_BCN_RESEND, 385 RTW89_MAC_C2H_FUNC_MACID_PAUSE, 386 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6, 387 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9, 388 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd, 389 RTW89_MAC_C2H_FUNC_OFLD_MAX, 390 }; 391 392 enum rtw89_mac_c2h_info_func { 393 RTW89_MAC_C2H_FUNC_REC_ACK, 394 RTW89_MAC_C2H_FUNC_DONE_ACK, 395 RTW89_MAC_C2H_FUNC_C2H_LOG, 396 RTW89_MAC_C2H_FUNC_BCN_CNT, 397 RTW89_MAC_C2H_FUNC_INFO_MAX, 398 }; 399 400 enum rtw89_mac_c2h_mcc_func { 401 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0, 402 RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1, 403 RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2, 404 RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3, 405 406 NUM_OF_RTW89_MAC_C2H_FUNC_MCC, 407 }; 408 409 enum rtw89_mac_c2h_mrc_func { 410 RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0, 411 RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT = 1, 412 413 NUM_OF_RTW89_MAC_C2H_FUNC_MRC, 414 }; 415 416 enum rtw89_mac_c2h_class { 417 RTW89_MAC_C2H_CLASS_INFO = 0x0, 418 RTW89_MAC_C2H_CLASS_OFLD = 0x1, 419 RTW89_MAC_C2H_CLASS_TWT = 0x2, 420 RTW89_MAC_C2H_CLASS_WOW = 0x3, 421 RTW89_MAC_C2H_CLASS_MCC = 0x4, 422 RTW89_MAC_C2H_CLASS_FWDBG = 0x5, 423 RTW89_MAC_C2H_CLASS_MRC = 0xe, 424 RTW89_MAC_C2H_CLASS_MAX, 425 }; 426 427 enum rtw89_mac_mcc_status { 428 RTW89_MAC_MCC_ADD_ROLE_OK = 0, 429 RTW89_MAC_MCC_START_GROUP_OK = 1, 430 RTW89_MAC_MCC_STOP_GROUP_OK = 2, 431 RTW89_MAC_MCC_DEL_GROUP_OK = 3, 432 RTW89_MAC_MCC_RESET_GROUP_OK = 4, 433 RTW89_MAC_MCC_SWITCH_CH_OK = 5, 434 RTW89_MAC_MCC_TXNULL0_OK = 6, 435 RTW89_MAC_MCC_TXNULL1_OK = 7, 436 437 RTW89_MAC_MCC_SWITCH_EARLY = 10, 438 RTW89_MAC_MCC_TBTT = 11, 439 RTW89_MAC_MCC_DURATION_START = 12, 440 RTW89_MAC_MCC_DURATION_END = 13, 441 442 RTW89_MAC_MCC_ADD_ROLE_FAIL = 20, 443 RTW89_MAC_MCC_START_GROUP_FAIL = 21, 444 RTW89_MAC_MCC_STOP_GROUP_FAIL = 22, 445 RTW89_MAC_MCC_DEL_GROUP_FAIL = 23, 446 RTW89_MAC_MCC_RESET_GROUP_FAIL = 24, 447 RTW89_MAC_MCC_SWITCH_CH_FAIL = 25, 448 RTW89_MAC_MCC_TXNULL0_FAIL = 26, 449 RTW89_MAC_MCC_TXNULL1_FAIL = 27, 450 }; 451 452 enum rtw89_mac_mrc_status { 453 RTW89_MAC_MRC_START_SCH_OK = 0, 454 RTW89_MAC_MRC_STOP_SCH_OK = 1, 455 RTW89_MAC_MRC_DEL_SCH_OK = 2, 456 }; 457 458 struct rtw89_mac_ax_coex { 459 #define RTW89_MAC_AX_COEX_RTK_MODE 0 460 #define RTW89_MAC_AX_COEX_CSR_MODE 1 461 u8 pta_mode; 462 #define RTW89_MAC_AX_COEX_INNER 0 463 #define RTW89_MAC_AX_COEX_OUTPUT 1 464 #define RTW89_MAC_AX_COEX_INPUT 2 465 u8 direction; 466 }; 467 468 struct rtw89_mac_ax_plt { 469 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0) 470 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) 471 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) 472 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3) 473 u8 band; 474 u8 tx; 475 u8 rx; 476 }; 477 478 enum rtw89_mac_bf_rrsc_rate { 479 RTW89_MAC_BF_RRSC_6M = 0, 480 RTW89_MAC_BF_RRSC_9M = 1, 481 RTW89_MAC_BF_RRSC_12M, 482 RTW89_MAC_BF_RRSC_18M, 483 RTW89_MAC_BF_RRSC_24M, 484 RTW89_MAC_BF_RRSC_36M, 485 RTW89_MAC_BF_RRSC_48M, 486 RTW89_MAC_BF_RRSC_54M, 487 RTW89_MAC_BF_RRSC_HT_MSC0, 488 RTW89_MAC_BF_RRSC_HT_MSC1, 489 RTW89_MAC_BF_RRSC_HT_MSC2, 490 RTW89_MAC_BF_RRSC_HT_MSC3, 491 RTW89_MAC_BF_RRSC_HT_MSC4, 492 RTW89_MAC_BF_RRSC_HT_MSC5, 493 RTW89_MAC_BF_RRSC_HT_MSC6, 494 RTW89_MAC_BF_RRSC_HT_MSC7, 495 RTW89_MAC_BF_RRSC_VHT_MSC0, 496 RTW89_MAC_BF_RRSC_VHT_MSC1, 497 RTW89_MAC_BF_RRSC_VHT_MSC2, 498 RTW89_MAC_BF_RRSC_VHT_MSC3, 499 RTW89_MAC_BF_RRSC_VHT_MSC4, 500 RTW89_MAC_BF_RRSC_VHT_MSC5, 501 RTW89_MAC_BF_RRSC_VHT_MSC6, 502 RTW89_MAC_BF_RRSC_VHT_MSC7, 503 RTW89_MAC_BF_RRSC_HE_MSC0, 504 RTW89_MAC_BF_RRSC_HE_MSC1, 505 RTW89_MAC_BF_RRSC_HE_MSC2, 506 RTW89_MAC_BF_RRSC_HE_MSC3, 507 RTW89_MAC_BF_RRSC_HE_MSC4, 508 RTW89_MAC_BF_RRSC_HE_MSC5, 509 RTW89_MAC_BF_RRSC_HE_MSC6, 510 RTW89_MAC_BF_RRSC_HE_MSC7 = 31, 511 RTW89_MAC_BF_RRSC_MAX = 32 512 }; 513 514 #define RTW89_R32_EA 0xEAEAEAEA 515 #define RTW89_R32_DEAD 0xDEADBEEF 516 #define MAC_REG_POOL_COUNT 10 517 #define ACCESS_CMAC(_addr) \ 518 ({typeof(_addr) __addr = (_addr); \ 519 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) 520 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000 521 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000 522 523 #define PTCL_IDLE_POLL_CNT 10000 524 #define SW_CVR_DUR_US 8 525 #define SW_CVR_CNT 8 526 527 #define DLE_BOUND_UNIT (8 * 1024) 528 #define DLE_WAIT_CNT 2000 529 #define TRXCFG_WAIT_CNT 2000 530 531 #define RTW89_WDE_PG_64 64 532 #define RTW89_WDE_PG_128 128 533 #define RTW89_WDE_PG_256 256 534 535 #define S_AX_WDE_PAGE_SEL_64 0 536 #define S_AX_WDE_PAGE_SEL_128 1 537 #define S_AX_WDE_PAGE_SEL_256 2 538 539 #define RTW89_PLE_PG_64 64 540 #define RTW89_PLE_PG_128 128 541 #define RTW89_PLE_PG_256 256 542 543 #define S_AX_PLE_PAGE_SEL_64 0 544 #define S_AX_PLE_PAGE_SEL_128 1 545 #define S_AX_PLE_PAGE_SEL_256 2 546 547 #define B_CMAC0_MGQ_NORMAL BIT(2) 548 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3) 549 #define B_CMAC0_CPUMGQ BIT(4) 550 #define B_CMAC1_MGQ_NORMAL BIT(10) 551 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11) 552 #define B_CMAC1_CPUMGQ BIT(12) 553 554 #define B_CMAC0_MGQ_NORMAL_BE BIT(2) 555 #define B_CMAC1_MGQ_NORMAL_BE BIT(30) 556 557 #define QEMP_ACQ_GRP_MACID_NUM 8 558 #define QEMP_ACQ_GRP_QSEL_SH 4 559 #define QEMP_ACQ_GRP_QSEL_MASK 0xF 560 561 #define SDIO_LOCAL_BASE_ADDR 0x80000000 562 563 #define PWR_CMD_WRITE 0 564 #define PWR_CMD_POLL 1 565 #define PWR_CMD_DELAY 2 566 #define PWR_CMD_END 3 567 568 #define PWR_INTF_MSK_SDIO BIT(0) 569 #define PWR_INTF_MSK_USB BIT(1) 570 #define PWR_INTF_MSK_PCIE BIT(2) 571 #define PWR_INTF_MSK_ALL 0x7 572 573 #define PWR_BASE_MAC 0 574 #define PWR_BASE_USB 1 575 #define PWR_BASE_PCIE 2 576 #define PWR_BASE_SDIO 3 577 578 #define PWR_CV_MSK_A BIT(0) 579 #define PWR_CV_MSK_B BIT(1) 580 #define PWR_CV_MSK_C BIT(2) 581 #define PWR_CV_MSK_D BIT(3) 582 #define PWR_CV_MSK_E BIT(4) 583 #define PWR_CV_MSK_F BIT(5) 584 #define PWR_CV_MSK_G BIT(6) 585 #define PWR_CV_MSK_TEST BIT(7) 586 #define PWR_CV_MSK_ALL 0xFF 587 588 #define PWR_DELAY_US 0 589 #define PWR_DELAY_MS 1 590 591 /* STA scheduler */ 592 #define SS_MACID_SH 8 593 #define SS_TX_LEN_MSK 0x1FFFFF 594 #define SS_CTRL1_R_TX_LEN 5 595 #define SS_CTRL1_R_NEXT_LINK 20 596 #define SS_LINK_SIZE 256 597 598 /* MAC debug port */ 599 #define TMAC_DBG_SEL_C0 0xA5 600 #define RMAC_DBG_SEL_C0 0xA6 601 #define TRXPTCL_DBG_SEL_C0 0xA7 602 #define TMAC_DBG_SEL_C1 0xB5 603 #define RMAC_DBG_SEL_C1 0xB6 604 #define TRXPTCL_DBG_SEL_C1 0xB7 605 #define FW_PROG_CNTR_DBG_SEL 0xF2 606 #define PCIE_TXDMA_DBG_SEL 0x30 607 #define PCIE_RXDMA_DBG_SEL 0x31 608 #define PCIE_CVT_DBG_SEL 0x32 609 #define PCIE_CXPL_DBG_SEL 0x33 610 #define PCIE_IO_DBG_SEL 0x37 611 #define PCIE_MISC_DBG_SEL 0x38 612 #define PCIE_MISC2_DBG_SEL 0x00 613 #define MAC_DBG_SEL 1 614 #define RMAC_CMAC_DBG_SEL 1 615 616 /* TRXPTCL dbg port sel */ 617 #define TRXPTRL_DBG_SEL_TMAC 0 618 #define TRXPTRL_DBG_SEL_RMAC 1 619 620 struct rtw89_cpuio_ctrl { 621 u16 pkt_num; 622 u16 start_pktid; 623 u16 end_pktid; 624 u8 cmd_type; 625 u8 macid; 626 u8 src_pid; 627 u8 src_qid; 628 u8 dst_pid; 629 u8 dst_qid; 630 u16 pktid; 631 }; 632 633 struct rtw89_mac_dbg_port_info { 634 u32 sel_addr; 635 u8 sel_byte; 636 u32 sel_msk; 637 u32 srt; 638 u32 end; 639 u32 rd_addr; 640 u8 rd_byte; 641 u32 rd_msk; 642 }; 643 644 #define QLNKTBL_ADDR_INFO_SEL BIT(0) 645 #define QLNKTBL_ADDR_INFO_SEL_0 0 646 #define QLNKTBL_ADDR_INFO_SEL_1 1 647 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) 648 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) 649 650 struct rtw89_mac_dle_dfi_ctrl { 651 enum rtw89_mac_dle_ctrl_type type; 652 u32 target; 653 u32 addr; 654 u32 out_data; 655 }; 656 657 struct rtw89_mac_dle_dfi_quota { 658 enum rtw89_mac_dle_ctrl_type dle_type; 659 u32 qtaid; 660 u16 rsv_pgnum; 661 u16 use_pgnum; 662 }; 663 664 struct rtw89_mac_dle_dfi_qempty { 665 enum rtw89_mac_dle_ctrl_type dle_type; 666 u32 grpsel; 667 u32 qempty; 668 }; 669 670 enum rtw89_mac_dle_rsvd_qt_type { 671 DLE_RSVD_QT_MPDU_INFO, 672 DLE_RSVD_QT_B0_CSI, 673 DLE_RSVD_QT_B1_CSI, 674 DLE_RSVD_QT_B0_LMR, 675 DLE_RSVD_QT_B1_LMR, 676 DLE_RSVD_QT_B0_FTM, 677 DLE_RSVD_QT_B1_FTM, 678 }; 679 680 struct rtw89_mac_dle_rsvd_qt_cfg { 681 u16 pktid; 682 u16 pg_num; 683 u32 size; 684 }; 685 686 enum rtw89_mac_error_scenario { 687 RTW89_RXI300_ERROR = 1, 688 RTW89_WCPU_CPU_EXCEPTION = 2, 689 RTW89_WCPU_ASSERTION = 3, 690 }; 691 692 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28) 693 694 /* Define DBG and recovery enum */ 695 enum mac_ax_err_info { 696 /* Get error info */ 697 698 /* L0 */ 699 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, 700 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, 701 MAC_AX_ERR_L0_RESET_DONE = 0x0003, 702 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, 703 704 /* L1 */ 705 MAC_AX_ERR_L1_PREERR_DMAC = 0x999, 706 MAC_AX_ERR_L1_ERR_DMAC = 0x1000, 707 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, 708 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, 709 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, 710 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, 711 712 /* L2 */ 713 /* address hole (master) */ 714 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, 715 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, 716 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, 717 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, 718 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, 719 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, 720 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, 721 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, 722 723 /* AHB bridge timeout (master) */ 724 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, 725 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, 726 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, 727 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, 728 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, 729 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, 730 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, 731 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, 732 733 /* APB_SA bridge timeout (master + slave) */ 734 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, 735 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, 736 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, 737 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, 738 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, 739 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, 740 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, 741 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, 742 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, 743 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, 744 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, 745 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, 746 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, 747 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, 748 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, 749 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, 750 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, 751 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, 752 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, 753 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, 754 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, 755 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, 756 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, 757 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, 758 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, 759 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, 760 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, 761 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, 762 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, 763 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, 764 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, 765 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, 766 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, 767 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, 768 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, 769 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, 770 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, 771 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, 772 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, 773 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, 774 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, 775 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, 776 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, 777 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, 778 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, 779 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, 780 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, 781 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, 782 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, 783 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, 784 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, 785 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, 786 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, 787 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, 788 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, 789 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, 790 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, 791 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, 792 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, 793 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, 794 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, 795 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, 796 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, 797 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, 798 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, 799 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, 800 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, 801 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, 802 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, 803 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, 804 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, 805 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, 806 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, 807 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, 808 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, 809 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, 810 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, 811 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, 812 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, 813 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, 814 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, 815 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, 816 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, 817 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, 818 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, 819 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, 820 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, 821 822 /* APB_BBRF bridge timeout (master) */ 823 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, 824 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, 825 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, 826 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, 827 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, 828 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, 829 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, 830 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, 831 MAC_AX_ERR_L2_RESET_DONE = 0x2400, 832 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599, 833 MAC_AX_ERR_CPU_EXCEPTION = 0x3000, 834 MAC_AX_ERR_ASSERTION = 0x4000, 835 MAC_AX_ERR_RXI300 = 0x5000, 836 MAC_AX_GET_ERR_MAX, 837 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, 838 839 /* set error info */ 840 MAC_AX_ERR_L1_DISABLE_EN = 0x0001, 841 MAC_AX_ERR_L1_RCVY_EN = 0x0002, 842 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, 843 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, 844 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A, 845 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, 846 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, 847 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, 848 MAC_AX_ERR_L0_RCVY_EN = 0x0013, 849 MAC_AX_SET_ERR_MAX, 850 }; 851 852 struct rtw89_mac_size_set { 853 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie; 854 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0; 855 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2; 856 const struct rtw89_dle_size wde_size0; 857 const struct rtw89_dle_size wde_size0_v1; 858 const struct rtw89_dle_size wde_size4; 859 const struct rtw89_dle_size wde_size4_v1; 860 const struct rtw89_dle_size wde_size6; 861 const struct rtw89_dle_size wde_size7; 862 const struct rtw89_dle_size wde_size9; 863 const struct rtw89_dle_size wde_size18; 864 const struct rtw89_dle_size wde_size19; 865 const struct rtw89_dle_size ple_size0; 866 const struct rtw89_dle_size ple_size0_v1; 867 const struct rtw89_dle_size ple_size3_v1; 868 const struct rtw89_dle_size ple_size4; 869 const struct rtw89_dle_size ple_size6; 870 const struct rtw89_dle_size ple_size8; 871 const struct rtw89_dle_size ple_size18; 872 const struct rtw89_dle_size ple_size19; 873 const struct rtw89_wde_quota wde_qt0; 874 const struct rtw89_wde_quota wde_qt0_v1; 875 const struct rtw89_wde_quota wde_qt4; 876 const struct rtw89_wde_quota wde_qt6; 877 const struct rtw89_wde_quota wde_qt7; 878 const struct rtw89_wde_quota wde_qt17; 879 const struct rtw89_wde_quota wde_qt18; 880 const struct rtw89_ple_quota ple_qt0; 881 const struct rtw89_ple_quota ple_qt1; 882 const struct rtw89_ple_quota ple_qt4; 883 const struct rtw89_ple_quota ple_qt5; 884 const struct rtw89_ple_quota ple_qt9; 885 const struct rtw89_ple_quota ple_qt13; 886 const struct rtw89_ple_quota ple_qt18; 887 const struct rtw89_ple_quota ple_qt44; 888 const struct rtw89_ple_quota ple_qt45; 889 const struct rtw89_ple_quota ple_qt46; 890 const struct rtw89_ple_quota ple_qt47; 891 const struct rtw89_ple_quota ple_qt58; 892 const struct rtw89_ple_quota ple_qt_52a_wow; 893 const struct rtw89_ple_quota ple_qt_52b_wow; 894 const struct rtw89_ple_quota ple_qt_51b_wow; 895 const struct rtw89_rsvd_quota ple_rsvd_qt0; 896 const struct rtw89_rsvd_quota ple_rsvd_qt1; 897 const struct rtw89_dle_rsvd_size rsvd0_size0; 898 const struct rtw89_dle_rsvd_size rsvd1_size0; 899 }; 900 901 extern const struct rtw89_mac_size_set rtw89_mac_size; 902 903 struct rtw89_mac_gen_def { 904 u32 band1_offset; 905 u32 filter_model_addr; 906 u32 indir_access_addr; 907 const u32 *mem_base_addrs; 908 u32 rx_fltr; 909 const struct rtw89_port_reg *port_base; 910 u32 agg_len_ht; 911 u32 ps_status; 912 913 struct rtw89_reg_def muedca_ctrl; 914 struct rtw89_reg_def bfee_ctrl; 915 struct rtw89_reg_def narrow_bw_ru_dis; 916 917 int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band, 918 enum rtw89_mac_hwmod_sel sel); 919 int (*sys_init)(struct rtw89_dev *rtwdev); 920 int (*trx_init)(struct rtw89_dev *rtwdev); 921 void (*hci_func_en)(struct rtw89_dev *rtwdev); 922 void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev); 923 void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable); 924 void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable); 925 void (*bf_assoc)(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 926 struct ieee80211_sta *sta); 927 928 int (*typ_fltr_opt)(struct rtw89_dev *rtwdev, 929 enum rtw89_machdr_frame_type type, 930 enum rtw89_mac_fwd_target fwd_target, 931 u8 mac_idx); 932 int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable); 933 934 int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg); 935 int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple); 936 int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id); 937 void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en); 938 void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev); 939 void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev); 940 void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev); 941 void (*wde_quota_cfg)(struct rtw89_dev *rtwdev, 942 const struct rtw89_wde_quota *min_cfg, 943 const struct rtw89_wde_quota *max_cfg, 944 u16 ext_wde_min_qt_wcpu); 945 void (*ple_quota_cfg)(struct rtw89_dev *rtwdev, 946 const struct rtw89_ple_quota *min_cfg, 947 const struct rtw89_ple_quota *max_cfg); 948 int (*set_cpuio)(struct rtw89_dev *rtwdev, 949 struct rtw89_cpuio_ctrl *ctrl_para, bool wd); 950 int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en); 951 952 void (*disable_cpu)(struct rtw89_dev *rtwdev); 953 int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason, 954 bool dlfw, bool include_bb); 955 u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type); 956 int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl); 957 int (*parse_efuse_map)(struct rtw89_dev *rtwdev); 958 int (*parse_phycap_map)(struct rtw89_dev *rtwdev); 959 int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle); 960 961 bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev, 962 enum rtw89_phy_idx phy_idx, 963 u32 reg_base, u32 *cr); 964 965 int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); 966 int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val); 967 968 void (*dump_qta_lost)(struct rtw89_dev *rtwdev); 969 void (*dump_err_status)(struct rtw89_dev *rtwdev, 970 enum mac_ax_err_info err); 971 972 bool (*is_txq_empty)(struct rtw89_dev *rtwdev); 973 974 int (*add_chan_list)(struct rtw89_dev *rtwdev, 975 struct rtw89_vif *rtwvif, bool connected); 976 int (*scan_offload)(struct rtw89_dev *rtwdev, 977 struct rtw89_scan_option *option, 978 struct rtw89_vif *rtwvif); 979 }; 980 981 extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax; 982 extern const struct rtw89_mac_gen_def rtw89_mac_gen_be; 983 984 static inline 985 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band) 986 { 987 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 988 989 return band == 0 ? reg_base : (reg_base + mac->band1_offset); 990 } 991 992 static inline 993 u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx) 994 { 995 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx); 996 } 997 998 static inline u32 999 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base) 1000 { 1001 u32 reg; 1002 1003 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1004 return rtw89_read32(rtwdev, reg); 1005 } 1006 1007 static inline u32 1008 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1009 u32 base, u32 mask) 1010 { 1011 u32 reg; 1012 1013 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1014 return rtw89_read32_mask(rtwdev, reg, mask); 1015 } 1016 1017 static inline void 1018 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, 1019 u32 data) 1020 { 1021 u32 reg; 1022 1023 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1024 rtw89_write32(rtwdev, reg, data); 1025 } 1026 1027 static inline void 1028 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1029 u32 base, u32 mask, u32 data) 1030 { 1031 u32 reg; 1032 1033 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1034 rtw89_write32_mask(rtwdev, reg, mask, data); 1035 } 1036 1037 static inline void 1038 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1039 u32 base, u32 mask, u16 data) 1040 { 1041 u32 reg; 1042 1043 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1044 rtw89_write16_mask(rtwdev, reg, mask, data); 1045 } 1046 1047 static inline void 1048 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1049 u32 base, u32 bit) 1050 { 1051 u32 reg; 1052 1053 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1054 rtw89_write32_clr(rtwdev, reg, bit); 1055 } 1056 1057 static inline void 1058 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1059 u32 base, u16 bit) 1060 { 1061 u32 reg; 1062 1063 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1064 rtw89_write16_clr(rtwdev, reg, bit); 1065 } 1066 1067 static inline void 1068 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1069 u32 base, u32 bit) 1070 { 1071 u32 reg; 1072 1073 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1074 rtw89_write32_set(rtwdev, reg, bit); 1075 } 1076 1077 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); 1078 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb); 1079 int rtw89_mac_init(struct rtw89_dev *rtwdev); 1080 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1081 enum rtw89_qta_mode ext_mode); 1082 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en); 1083 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1084 enum rtw89_qta_mode mode); 1085 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode); 1086 static inline 1087 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, 1088 enum rtw89_mac_hwmod_sel sel) 1089 { 1090 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1091 1092 return mac->check_mac_en(rtwdev, band, sel); 1093 } 1094 1095 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); 1096 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); 1097 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl); 1098 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 1099 struct rtw89_mac_dle_dfi_quota *quota); 1100 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev); 1101 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 1102 struct rtw89_mac_dle_dfi_qempty *qempty); 1103 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 1104 enum mac_ax_err_info err); 1105 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 1106 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1107 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 1108 struct rtw89_vif *rtwvif, 1109 struct rtw89_vif *rtwvif_src, 1110 u16 offset_tu); 1111 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1112 u64 *tsf); 1113 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 1114 struct rtw89_vif *rtwvif, bool en); 1115 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 1116 struct ieee80211_vif *vif); 1117 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1118 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en); 1119 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 1120 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); 1121 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); 1122 1123 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev) 1124 { 1125 const struct rtw89_chip_info *chip = rtwdev->chip; 1126 1127 return chip->ops->enable_bb_rf(rtwdev); 1128 } 1129 1130 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev) 1131 { 1132 const struct rtw89_chip_info *chip = rtwdev->chip; 1133 1134 return chip->ops->disable_bb_rf(rtwdev); 1135 } 1136 1137 static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev) 1138 { 1139 int ret; 1140 1141 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 1142 return 0; 1143 1144 ret = rtw89_chip_disable_bb_rf(rtwdev); 1145 if (ret) 1146 return ret; 1147 ret = rtw89_chip_enable_bb_rf(rtwdev); 1148 if (ret) 1149 return ret; 1150 1151 return 0; 1152 } 1153 1154 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); 1155 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); 1156 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 1157 u8 class, u8 func); 1158 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1159 u32 len, u8 class, u8 func); 1160 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); 1161 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 1162 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1163 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 1164 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1165 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, 1166 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1167 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1168 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1169 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1170 1171 static inline 1172 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 1173 { 1174 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1175 1176 return mac->cfg_ppdu_status(rtwdev, mac_idx, enable); 1177 } 1178 1179 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx); 1180 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); 1181 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); 1182 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 1183 const struct rtw89_mac_ax_coex *coex); 1184 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 1185 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1186 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 1187 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1188 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); 1189 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band); 1190 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); 1191 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); 1192 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); 1193 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); 1194 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); 1195 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); 1196 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); 1197 1198 static inline 1199 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1200 struct ieee80211_sta *sta) 1201 { 1202 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1203 1204 if (mac->bf_assoc) 1205 mac->bf_assoc(rtwdev, vif, sta); 1206 } 1207 1208 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1209 struct ieee80211_sta *sta); 1210 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1211 struct ieee80211_bss_conf *conf); 1212 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 1213 struct ieee80211_sta *sta, bool disconnect); 1214 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); 1215 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en); 1216 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1217 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1218 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 1219 struct rtw89_vif *rtwvif, bool en); 1220 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause); 1221 1222 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 1223 { 1224 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 1225 return; 1226 1227 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) 1228 return; 1229 1230 _rtw89_mac_bf_monitor_track(rtwdev); 1231 } 1232 1233 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, 1234 enum rtw89_phy_idx phy_idx, 1235 u32 reg_base, u32 *val) 1236 { 1237 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1238 u32 cr; 1239 1240 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1241 return -EINVAL; 1242 1243 *val = rtw89_read32(rtwdev, cr); 1244 return 0; 1245 } 1246 1247 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, 1248 enum rtw89_phy_idx phy_idx, 1249 u32 reg_base, u32 val) 1250 { 1251 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1252 u32 cr; 1253 1254 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1255 return -EINVAL; 1256 1257 rtw89_write32(rtwdev, cr, val); 1258 return 0; 1259 } 1260 1261 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, 1262 enum rtw89_phy_idx phy_idx, 1263 u32 reg_base, u32 mask, u32 val) 1264 { 1265 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1266 u32 cr; 1267 1268 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1269 return -EINVAL; 1270 1271 rtw89_write32_mask(rtwdev, cr, mask, val); 1272 return 0; 1273 } 1274 1275 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev, 1276 bool enable) 1277 { 1278 const struct rtw89_chip_info *chip = rtwdev->chip; 1279 1280 if (enable) 1281 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1282 B_AX_HCI_TXDMA_EN); 1283 else 1284 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1285 B_AX_HCI_TXDMA_EN); 1286 } 1287 1288 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev, 1289 bool enable) 1290 { 1291 const struct rtw89_chip_info *chip = rtwdev->chip; 1292 1293 if (enable) 1294 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1295 B_AX_HCI_RXDMA_EN); 1296 else 1297 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1298 B_AX_HCI_RXDMA_EN); 1299 } 1300 1301 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev, 1302 bool enable) 1303 { 1304 const struct rtw89_chip_info *chip = rtwdev->chip; 1305 1306 if (enable) 1307 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1308 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1309 else 1310 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1311 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1312 } 1313 1314 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev) 1315 { 1316 u32 val; 1317 1318 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, 1319 B_AX_WLMAC_PWR_STE_MASK); 1320 1321 return !!val; 1322 } 1323 1324 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 1325 bool resume, u32 tx_time); 1326 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 1327 u32 *tx_time); 1328 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 1329 struct rtw89_sta *rtwsta, 1330 bool resume, u8 tx_retry); 1331 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 1332 struct rtw89_sta *rtwsta, u8 *tx_retry); 1333 1334 enum rtw89_mac_xtal_si_offset { 1335 XTAL0 = 0x0, 1336 XTAL3 = 0x3, 1337 XTAL_SI_XTAL_SC_XI = 0x04, 1338 #define XTAL_SC_XI_MASK GENMASK(7, 0) 1339 XTAL_SI_XTAL_SC_XO = 0x05, 1340 #define XTAL_SC_XO_MASK GENMASK(7, 0) 1341 XTAL_SI_XREF_MODE = 0x0B, 1342 XTAL_SI_PWR_CUT = 0x10, 1343 #define XTAL_SI_SMALL_PWR_CUT BIT(0) 1344 #define XTAL_SI_BIG_PWR_CUT BIT(1) 1345 XTAL_SI_XTAL_DRV = 0x15, 1346 #define XTAL_SI_DRV_LATCH BIT(4) 1347 XTAL_SI_XTAL_PLL = 0x16, 1348 XTAL_SI_XTAL_XMD_2 = 0x24, 1349 #define XTAL_SI_LDO_LPS GENMASK(6, 4) 1350 XTAL_SI_XTAL_XMD_4 = 0x26, 1351 #define XTAL_SI_LPS_CAP GENMASK(3, 0) 1352 XTAL_SI_XREF_RF1 = 0x2D, 1353 XTAL_SI_XREF_RF2 = 0x2E, 1354 XTAL_SI_CV = 0x41, 1355 #define XTAL_SI_ACV_MASK GENMASK(3, 0) 1356 XTAL_SI_LOW_ADDR = 0x62, 1357 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0) 1358 XTAL_SI_CTRL = 0x63, 1359 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6) 1360 #define XTAL_SI_RDY BIT(5) 1361 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0) 1362 XTAL_SI_READ_VAL = 0x7A, 1363 XTAL_SI_WL_RFC_S0 = 0x80, 1364 #define XTAL_SI_RF00S_EN GENMASK(2, 0) 1365 #define XTAL_SI_RF00 BIT(0) 1366 XTAL_SI_WL_RFC_S1 = 0x81, 1367 #define XTAL_SI_RF10S_EN GENMASK(2, 0) 1368 #define XTAL_SI_RF10 BIT(0) 1369 XTAL_SI_ANAPAR_WL = 0x90, 1370 #define XTAL_SI_SRAM2RFC BIT(7) 1371 #define XTAL_SI_GND_SHDN_WL BIT(6) 1372 #define XTAL_SI_SHDN_WL BIT(5) 1373 #define XTAL_SI_RFC2RF BIT(4) 1374 #define XTAL_SI_OFF_EI BIT(3) 1375 #define XTAL_SI_OFF_WEI BIT(2) 1376 #define XTAL_SI_PON_EI BIT(1) 1377 #define XTAL_SI_PON_WEI BIT(0) 1378 XTAL_SI_SRAM_CTRL = 0xA1, 1379 #define XTAL_SI_SRAM_DIS BIT(1) 1380 #define FULL_BIT_MASK GENMASK(7, 0) 1381 XTAL_SI_APBT = 0xD1, 1382 XTAL_SI_PLL = 0xE0, 1383 XTAL_SI_PLL_1 = 0xE1, 1384 }; 1385 1386 static inline 1387 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 1388 { 1389 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1390 1391 return mac->write_xtal_si(rtwdev, offset, val, mask); 1392 } 1393 1394 static inline 1395 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 1396 { 1397 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1398 1399 return mac->read_xtal_si(rtwdev, offset, val); 1400 } 1401 1402 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1403 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow); 1404 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 1405 enum rtw89_mac_idx band); 1406 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow); 1407 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1408 bool band1_en); 1409 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1410 enum rtw89_mac_dle_rsvd_qt_type type, 1411 struct rtw89_mac_dle_rsvd_qt_cfg *cfg); 1412 1413 #endif 1414