1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_MAC_H__ 6 #define __RTW89_MAC_H__ 7 8 #include "core.h" 9 #include "reg.h" 10 11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000 12 #define ADDR_CAM_ENT_SIZE 0x40 13 #define ADDR_CAM_ENT_SHORT_SIZE 0x20 14 #define BSSID_CAM_ENT_SIZE 0x08 15 #define HFC_PAGE_UNIT 64 16 #define RPWM_TRY_CNT 3 17 18 enum rtw89_mac_hwmod_sel { 19 RTW89_DMAC_SEL = 0, 20 RTW89_CMAC_SEL = 1, 21 22 RTW89_MAC_INVALID, 23 }; 24 25 enum rtw89_mac_fwd_target { 26 RTW89_FWD_DONT_CARE = 0, 27 RTW89_FWD_TO_HOST = 1, 28 RTW89_FWD_TO_WLAN_CPU = 2 29 }; 30 31 enum rtw89_mac_wd_dma_intvl { 32 RTW89_MAC_WD_DMA_INTVL_0S, 33 RTW89_MAC_WD_DMA_INTVL_256NS, 34 RTW89_MAC_WD_DMA_INTVL_512NS, 35 RTW89_MAC_WD_DMA_INTVL_768NS, 36 RTW89_MAC_WD_DMA_INTVL_1US, 37 RTW89_MAC_WD_DMA_INTVL_1_5US, 38 RTW89_MAC_WD_DMA_INTVL_2US, 39 RTW89_MAC_WD_DMA_INTVL_4US, 40 RTW89_MAC_WD_DMA_INTVL_8US, 41 RTW89_MAC_WD_DMA_INTVL_16US, 42 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE 43 }; 44 45 enum rtw89_mac_multi_tag_num { 46 RTW89_MAC_TAG_NUM_1, 47 RTW89_MAC_TAG_NUM_2, 48 RTW89_MAC_TAG_NUM_3, 49 RTW89_MAC_TAG_NUM_4, 50 RTW89_MAC_TAG_NUM_5, 51 RTW89_MAC_TAG_NUM_6, 52 RTW89_MAC_TAG_NUM_7, 53 RTW89_MAC_TAG_NUM_8, 54 RTW89_MAC_TAG_NUM_DEF = 0xFE 55 }; 56 57 enum rtw89_mac_lbc_tmr { 58 RTW89_MAC_LBC_TMR_8US = 0, 59 RTW89_MAC_LBC_TMR_16US, 60 RTW89_MAC_LBC_TMR_32US, 61 RTW89_MAC_LBC_TMR_64US, 62 RTW89_MAC_LBC_TMR_128US, 63 RTW89_MAC_LBC_TMR_256US, 64 RTW89_MAC_LBC_TMR_512US, 65 RTW89_MAC_LBC_TMR_1MS, 66 RTW89_MAC_LBC_TMR_2MS, 67 RTW89_MAC_LBC_TMR_4MS, 68 RTW89_MAC_LBC_TMR_8MS, 69 RTW89_MAC_LBC_TMR_DEF = 0xFE 70 }; 71 72 enum rtw89_mac_cpuio_op_cmd_type { 73 CPUIO_OP_CMD_GET_1ST_PID = 0, 74 CPUIO_OP_CMD_GET_NEXT_PID = 1, 75 CPUIO_OP_CMD_ENQ_TO_TAIL = 4, 76 CPUIO_OP_CMD_ENQ_TO_HEAD = 5, 77 CPUIO_OP_CMD_DEQ = 8, 78 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, 79 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 80 }; 81 82 enum rtw89_mac_wde_dle_port_id { 83 WDE_DLE_PORT_ID_DISPATCH = 0, 84 WDE_DLE_PORT_ID_PKTIN = 1, 85 WDE_DLE_PORT_ID_CMAC0 = 3, 86 WDE_DLE_PORT_ID_CMAC1 = 4, 87 WDE_DLE_PORT_ID_CPU_IO = 6, 88 WDE_DLE_PORT_ID_WDRLS = 7, 89 WDE_DLE_PORT_ID_END = 8 90 }; 91 92 enum rtw89_mac_wde_dle_queid_wdrls { 93 WDE_DLE_QUEID_TXOK = 0, 94 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, 95 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, 96 WDE_DLE_QUEID_DROP_MACID_DROP = 3, 97 WDE_DLE_QUEID_NO_REPORT = 4 98 }; 99 100 enum rtw89_mac_ple_dle_port_id { 101 PLE_DLE_PORT_ID_DISPATCH = 0, 102 PLE_DLE_PORT_ID_MPDU = 1, 103 PLE_DLE_PORT_ID_SEC = 2, 104 PLE_DLE_PORT_ID_CMAC0 = 3, 105 PLE_DLE_PORT_ID_CMAC1 = 4, 106 PLE_DLE_PORT_ID_WDRLS = 5, 107 PLE_DLE_PORT_ID_CPU_IO = 6, 108 PLE_DLE_PORT_ID_PLRLS = 7, 109 PLE_DLE_PORT_ID_END = 8 110 }; 111 112 enum rtw89_mac_ple_dle_queid_plrls { 113 PLE_DLE_QUEID_NO_REPORT = 0x0 114 }; 115 116 enum rtw89_machdr_frame_type { 117 RTW89_MGNT = 0, 118 RTW89_CTRL = 1, 119 RTW89_DATA = 2, 120 }; 121 122 enum rtw89_mac_dle_dfi_type { 123 DLE_DFI_TYPE_FREEPG = 0, 124 DLE_DFI_TYPE_QUOTA = 1, 125 DLE_DFI_TYPE_PAGELLT = 2, 126 DLE_DFI_TYPE_PKTINFO = 3, 127 DLE_DFI_TYPE_PREPKTLLT = 4, 128 DLE_DFI_TYPE_NXTPKTLLT = 5, 129 DLE_DFI_TYPE_QLNKTBL = 6, 130 DLE_DFI_TYPE_QEMPTY = 7, 131 }; 132 133 enum rtw89_mac_dle_wde_quota_id { 134 WDE_QTAID_HOST_IF = 0, 135 WDE_QTAID_WLAN_CPU = 1, 136 WDE_QTAID_DATA_CPU = 2, 137 WDE_QTAID_PKTIN = 3, 138 WDE_QTAID_CPUIO = 4, 139 }; 140 141 enum rtw89_mac_dle_ple_quota_id { 142 PLE_QTAID_B0_TXPL = 0, 143 PLE_QTAID_B1_TXPL = 1, 144 PLE_QTAID_C2H = 2, 145 PLE_QTAID_H2C = 3, 146 PLE_QTAID_WLAN_CPU = 4, 147 PLE_QTAID_MPDU = 5, 148 PLE_QTAID_CMAC0_RX = 6, 149 PLE_QTAID_CMAC1_RX = 7, 150 PLE_QTAID_CMAC1_BBRPT = 8, 151 PLE_QTAID_WDRLS = 9, 152 PLE_QTAID_CPUIO = 10, 153 }; 154 155 enum rtw89_mac_dle_ctrl_type { 156 DLE_CTRL_TYPE_WDE = 0, 157 DLE_CTRL_TYPE_PLE = 1, 158 DLE_CTRL_TYPE_NUM = 2, 159 }; 160 161 enum rtw89_mac_ax_l0_to_l1_event { 162 MAC_AX_L0_TO_L1_CHIF_IDLE = 0, 163 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, 164 MAC_AX_L0_TO_L1_RLS_PKID = 2, 165 MAC_AX_L0_TO_L1_PTCL_IDLE = 3, 166 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, 167 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, 168 MAC_AX_L0_TO_L1_PCIE_STUCK = 6, 169 MAC_AX_L0_TO_L1_EVENT_MAX = 15, 170 }; 171 172 enum rtw89_mac_wow_fw_status { 173 WOWLAN_NOT_READY = 0x00, 174 WOWLAN_SLEEP_READY = 0x01, 175 WOWLAN_RESUME_READY = 0x02, 176 }; 177 178 #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32) 179 180 enum rtw89_mac_dbg_port_sel { 181 /* CMAC 0 related */ 182 RTW89_DBG_PORT_SEL_PTCL_C0 = 0, 183 RTW89_DBG_PORT_SEL_SCH_C0, 184 RTW89_DBG_PORT_SEL_TMAC_C0, 185 RTW89_DBG_PORT_SEL_RMAC_C0, 186 RTW89_DBG_PORT_SEL_RMACST_C0, 187 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, 188 RTW89_DBG_PORT_SEL_TRXPTCL_C0, 189 RTW89_DBG_PORT_SEL_TX_INFOL_C0, 190 RTW89_DBG_PORT_SEL_TX_INFOH_C0, 191 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, 192 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, 193 /* CMAC 1 related */ 194 RTW89_DBG_PORT_SEL_PTCL_C1, 195 RTW89_DBG_PORT_SEL_SCH_C1, 196 RTW89_DBG_PORT_SEL_TMAC_C1, 197 RTW89_DBG_PORT_SEL_RMAC_C1, 198 RTW89_DBG_PORT_SEL_RMACST_C1, 199 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, 200 RTW89_DBG_PORT_SEL_TRXPTCL_C1, 201 RTW89_DBG_PORT_SEL_TX_INFOL_C1, 202 RTW89_DBG_PORT_SEL_TX_INFOH_C1, 203 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, 204 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, 205 /* DLE related */ 206 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, 207 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, 208 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, 209 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, 210 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, 211 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, 212 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, 213 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, 214 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, 215 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, 216 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, 217 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, 218 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, 219 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, 220 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, 221 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, 222 RTW89_DBG_PORT_SEL_PKTINFO, 223 /* DISPATCHER related */ 224 RTW89_DBG_PORT_SEL_DSPT_HDT_TX0, 225 RTW89_DBG_PORT_SEL_DSPT_HDT_TX1, 226 RTW89_DBG_PORT_SEL_DSPT_HDT_TX2, 227 RTW89_DBG_PORT_SEL_DSPT_HDT_TX3, 228 RTW89_DBG_PORT_SEL_DSPT_HDT_TX4, 229 RTW89_DBG_PORT_SEL_DSPT_HDT_TX5, 230 RTW89_DBG_PORT_SEL_DSPT_HDT_TX6, 231 RTW89_DBG_PORT_SEL_DSPT_HDT_TX7, 232 RTW89_DBG_PORT_SEL_DSPT_HDT_TX8, 233 RTW89_DBG_PORT_SEL_DSPT_HDT_TX9, 234 RTW89_DBG_PORT_SEL_DSPT_HDT_TXA, 235 RTW89_DBG_PORT_SEL_DSPT_HDT_TXB, 236 RTW89_DBG_PORT_SEL_DSPT_HDT_TXC, 237 RTW89_DBG_PORT_SEL_DSPT_HDT_TXD, 238 RTW89_DBG_PORT_SEL_DSPT_HDT_TXE, 239 RTW89_DBG_PORT_SEL_DSPT_HDT_TXF, 240 RTW89_DBG_PORT_SEL_DSPT_CDT_TX0, 241 RTW89_DBG_PORT_SEL_DSPT_CDT_TX1, 242 RTW89_DBG_PORT_SEL_DSPT_CDT_TX3, 243 RTW89_DBG_PORT_SEL_DSPT_CDT_TX4, 244 RTW89_DBG_PORT_SEL_DSPT_CDT_TX5, 245 RTW89_DBG_PORT_SEL_DSPT_CDT_TX6, 246 RTW89_DBG_PORT_SEL_DSPT_CDT_TX7, 247 RTW89_DBG_PORT_SEL_DSPT_CDT_TX8, 248 RTW89_DBG_PORT_SEL_DSPT_CDT_TX9, 249 RTW89_DBG_PORT_SEL_DSPT_CDT_TXA, 250 RTW89_DBG_PORT_SEL_DSPT_CDT_TXB, 251 RTW89_DBG_PORT_SEL_DSPT_CDT_TXC, 252 RTW89_DBG_PORT_SEL_DSPT_HDT_RX0, 253 RTW89_DBG_PORT_SEL_DSPT_HDT_RX1, 254 RTW89_DBG_PORT_SEL_DSPT_HDT_RX2, 255 RTW89_DBG_PORT_SEL_DSPT_HDT_RX3, 256 RTW89_DBG_PORT_SEL_DSPT_HDT_RX4, 257 RTW89_DBG_PORT_SEL_DSPT_HDT_RX5, 258 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0, 259 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0, 260 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1, 261 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2, 262 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1, 263 RTW89_DBG_PORT_SEL_DSPT_STF_CTRL, 264 RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL, 265 RTW89_DBG_PORT_SEL_DSPT_WDE_INTF, 266 RTW89_DBG_PORT_SEL_DSPT_PLE_INTF, 267 RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL, 268 /* PCIE related */ 269 RTW89_DBG_PORT_SEL_PCIE_TXDMA, 270 RTW89_DBG_PORT_SEL_PCIE_RXDMA, 271 RTW89_DBG_PORT_SEL_PCIE_CVT, 272 RTW89_DBG_PORT_SEL_PCIE_CXPL, 273 RTW89_DBG_PORT_SEL_PCIE_IO, 274 RTW89_DBG_PORT_SEL_PCIE_MISC, 275 RTW89_DBG_PORT_SEL_PCIE_MISC2, 276 277 /* keep last */ 278 RTW89_DBG_PORT_SEL_LAST, 279 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, 280 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, 281 }; 282 283 /* SRAM mem dump */ 284 #define R_AX_INDIR_ACCESS_ENTRY 0x40000 285 #define R_BE_INDIR_ACCESS_ENTRY 0x80000 286 287 #define AXIDMA_BASE_ADDR 0x18006000 288 #define STA_SCHED_BASE_ADDR 0x18808000 289 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 290 #define SECURITY_CAM_BASE_ADDR 0x18814000 291 #define WOW_CAM_BASE_ADDR 0x18815000 292 #define CMAC_TBL_BASE_ADDR 0x18840000 293 #define ADDR_CAM_BASE_ADDR 0x18850000 294 #define BSSID_CAM_BASE_ADDR 0x18853000 295 #define BA_CAM_BASE_ADDR 0x18854000 296 #define BCN_IE_CAM0_BASE_ADDR 0x18855000 297 #define SHARED_BUF_BASE_ADDR 0x18700000 298 #define DMAC_TBL_BASE_ADDR 0x18800000 299 #define SHCUT_MACHDR_BASE_ADDR 0x18800800 300 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000 301 #define TXD_FIFO_0_BASE_ADDR 0x18856200 302 #define TXD_FIFO_1_BASE_ADDR 0x188A1080 303 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */ 304 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */ 305 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000 306 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 307 #define CPU_LOCAL_BASE_ADDR 0x18003000 308 309 #define WD_PAGE_BASE_ADDR_BE 0x0 310 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000 311 #define AXIDMA_BASE_ADDR_BE 0x18006000 312 #define SHARED_BUF_BASE_ADDR_BE 0x18700000 313 #define DMAC_TBL_BASE_ADDR_BE 0x18800000 314 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800 315 #define STA_SCHED_BASE_ADDR_BE 0x18818000 316 #define NAT25_CAM_BASE_ADDR_BE 0x18820000 317 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000 318 #define SEC_CAM_BASE_ADDR_BE 0x18824000 319 #define WOW_CAM_BASE_ADDR_BE 0x18828000 320 #define MLD_TBL_BASE_ADDR_BE 0x18829000 321 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000 322 #define CMAC_TBL_BASE_ADDR_BE 0x18840000 323 #define ADDR_CAM_BASE_ADDR_BE 0x18850000 324 #define BSSID_CAM_BASE_ADDR_BE 0x18858000 325 #define BA_CAM_BASE_ADDR_BE 0x18859000 326 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000 327 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000 328 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000 329 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000 330 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000 331 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800 332 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000 333 334 #define CCTL_INFO_SIZE 32 335 336 enum rtw89_mac_mem_sel { 337 RTW89_MAC_MEM_AXIDMA, 338 RTW89_MAC_MEM_SHARED_BUF, 339 RTW89_MAC_MEM_DMAC_TBL, 340 RTW89_MAC_MEM_SHCUT_MACHDR, 341 RTW89_MAC_MEM_STA_SCHED, 342 RTW89_MAC_MEM_RXPLD_FLTR_CAM, 343 RTW89_MAC_MEM_SECURITY_CAM, 344 RTW89_MAC_MEM_WOW_CAM, 345 RTW89_MAC_MEM_CMAC_TBL, 346 RTW89_MAC_MEM_ADDR_CAM, 347 RTW89_MAC_MEM_BA_CAM, 348 RTW89_MAC_MEM_BCN_IE_CAM0, 349 RTW89_MAC_MEM_BCN_IE_CAM1, 350 RTW89_MAC_MEM_TXD_FIFO_0, 351 RTW89_MAC_MEM_TXD_FIFO_1, 352 RTW89_MAC_MEM_TXDATA_FIFO_0, 353 RTW89_MAC_MEM_TXDATA_FIFO_1, 354 RTW89_MAC_MEM_CPU_LOCAL, 355 RTW89_MAC_MEM_BSSID_CAM, 356 RTW89_MAC_MEM_TXD_FIFO_0_V1, 357 RTW89_MAC_MEM_TXD_FIFO_1_V1, 358 RTW89_MAC_MEM_WD_PAGE, 359 360 /* keep last */ 361 RTW89_MAC_MEM_NUM, 362 }; 363 364 enum rtw89_rpwm_req_pwr_state { 365 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, 366 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, 367 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, 368 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, 369 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, 370 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, 371 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, 372 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, 373 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, 374 }; 375 376 struct rtw89_pwr_cfg { 377 u16 addr; 378 u8 cv_msk; 379 u8 intf_msk; 380 u8 base:4; 381 u8 cmd:4; 382 u8 msk; 383 u8 val; 384 }; 385 386 enum rtw89_mac_c2h_ofld_func { 387 RTW89_MAC_C2H_FUNC_EFUSE_DUMP, 388 RTW89_MAC_C2H_FUNC_READ_RSP, 389 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, 390 RTW89_MAC_C2H_FUNC_BCN_RESEND, 391 RTW89_MAC_C2H_FUNC_MACID_PAUSE, 392 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6, 393 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9, 394 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd, 395 RTW89_MAC_C2H_FUNC_OFLD_MAX, 396 }; 397 398 enum rtw89_mac_c2h_info_func { 399 RTW89_MAC_C2H_FUNC_REC_ACK, 400 RTW89_MAC_C2H_FUNC_DONE_ACK, 401 RTW89_MAC_C2H_FUNC_C2H_LOG, 402 RTW89_MAC_C2H_FUNC_BCN_CNT, 403 RTW89_MAC_C2H_FUNC_INFO_MAX, 404 }; 405 406 enum rtw89_mac_c2h_mcc_func { 407 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0, 408 RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1, 409 RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2, 410 RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3, 411 412 NUM_OF_RTW89_MAC_C2H_FUNC_MCC, 413 }; 414 415 enum rtw89_mac_c2h_mrc_func { 416 RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0, 417 RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT = 1, 418 419 NUM_OF_RTW89_MAC_C2H_FUNC_MRC, 420 }; 421 422 enum rtw89_mac_c2h_wow_func { 423 RTW89_MAC_C2H_FUNC_AOAC_REPORT, 424 425 NUM_OF_RTW89_MAC_C2H_FUNC_WOW, 426 }; 427 428 enum rtw89_mac_c2h_class { 429 RTW89_MAC_C2H_CLASS_INFO = 0x0, 430 RTW89_MAC_C2H_CLASS_OFLD = 0x1, 431 RTW89_MAC_C2H_CLASS_TWT = 0x2, 432 RTW89_MAC_C2H_CLASS_WOW = 0x3, 433 RTW89_MAC_C2H_CLASS_MCC = 0x4, 434 RTW89_MAC_C2H_CLASS_FWDBG = 0x5, 435 RTW89_MAC_C2H_CLASS_MRC = 0xe, 436 RTW89_MAC_C2H_CLASS_MAX, 437 }; 438 439 enum rtw89_mac_mcc_status { 440 RTW89_MAC_MCC_ADD_ROLE_OK = 0, 441 RTW89_MAC_MCC_START_GROUP_OK = 1, 442 RTW89_MAC_MCC_STOP_GROUP_OK = 2, 443 RTW89_MAC_MCC_DEL_GROUP_OK = 3, 444 RTW89_MAC_MCC_RESET_GROUP_OK = 4, 445 RTW89_MAC_MCC_SWITCH_CH_OK = 5, 446 RTW89_MAC_MCC_TXNULL0_OK = 6, 447 RTW89_MAC_MCC_TXNULL1_OK = 7, 448 449 RTW89_MAC_MCC_SWITCH_EARLY = 10, 450 RTW89_MAC_MCC_TBTT = 11, 451 RTW89_MAC_MCC_DURATION_START = 12, 452 RTW89_MAC_MCC_DURATION_END = 13, 453 454 RTW89_MAC_MCC_ADD_ROLE_FAIL = 20, 455 RTW89_MAC_MCC_START_GROUP_FAIL = 21, 456 RTW89_MAC_MCC_STOP_GROUP_FAIL = 22, 457 RTW89_MAC_MCC_DEL_GROUP_FAIL = 23, 458 RTW89_MAC_MCC_RESET_GROUP_FAIL = 24, 459 RTW89_MAC_MCC_SWITCH_CH_FAIL = 25, 460 RTW89_MAC_MCC_TXNULL0_FAIL = 26, 461 RTW89_MAC_MCC_TXNULL1_FAIL = 27, 462 }; 463 464 enum rtw89_mac_mrc_status { 465 RTW89_MAC_MRC_START_SCH_OK = 0, 466 RTW89_MAC_MRC_STOP_SCH_OK = 1, 467 RTW89_MAC_MRC_DEL_SCH_OK = 2, 468 RTW89_MAC_MRC_EMPTY_SCH_FAIL = 16, 469 RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL = 17, 470 RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL = 18, 471 RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL = 19, 472 RTW89_MAC_MRC_ALT_ROLE_FAIL = 20, 473 RTW89_MAC_MRC_ADD_PSTIMER_FAIL = 21, 474 RTW89_MAC_MRC_MALLOC_FAIL = 22, 475 RTW89_MAC_MRC_SWITCH_CH_FAIL = 23, 476 RTW89_MAC_MRC_TXNULL0_FAIL = 24, 477 RTW89_MAC_MRC_PORT_FUNC_EN_FAIL = 25, 478 }; 479 480 struct rtw89_mac_ax_coex { 481 #define RTW89_MAC_AX_COEX_RTK_MODE 0 482 #define RTW89_MAC_AX_COEX_CSR_MODE 1 483 u8 pta_mode; 484 #define RTW89_MAC_AX_COEX_INNER 0 485 #define RTW89_MAC_AX_COEX_OUTPUT 1 486 #define RTW89_MAC_AX_COEX_INPUT 2 487 u8 direction; 488 }; 489 490 struct rtw89_mac_ax_plt { 491 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0) 492 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) 493 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) 494 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3) 495 u8 band; 496 u8 tx; 497 u8 rx; 498 }; 499 500 enum rtw89_mac_bf_rrsc_rate { 501 RTW89_MAC_BF_RRSC_6M = 0, 502 RTW89_MAC_BF_RRSC_9M = 1, 503 RTW89_MAC_BF_RRSC_12M, 504 RTW89_MAC_BF_RRSC_18M, 505 RTW89_MAC_BF_RRSC_24M, 506 RTW89_MAC_BF_RRSC_36M, 507 RTW89_MAC_BF_RRSC_48M, 508 RTW89_MAC_BF_RRSC_54M, 509 RTW89_MAC_BF_RRSC_HT_MSC0, 510 RTW89_MAC_BF_RRSC_HT_MSC1, 511 RTW89_MAC_BF_RRSC_HT_MSC2, 512 RTW89_MAC_BF_RRSC_HT_MSC3, 513 RTW89_MAC_BF_RRSC_HT_MSC4, 514 RTW89_MAC_BF_RRSC_HT_MSC5, 515 RTW89_MAC_BF_RRSC_HT_MSC6, 516 RTW89_MAC_BF_RRSC_HT_MSC7, 517 RTW89_MAC_BF_RRSC_VHT_MSC0, 518 RTW89_MAC_BF_RRSC_VHT_MSC1, 519 RTW89_MAC_BF_RRSC_VHT_MSC2, 520 RTW89_MAC_BF_RRSC_VHT_MSC3, 521 RTW89_MAC_BF_RRSC_VHT_MSC4, 522 RTW89_MAC_BF_RRSC_VHT_MSC5, 523 RTW89_MAC_BF_RRSC_VHT_MSC6, 524 RTW89_MAC_BF_RRSC_VHT_MSC7, 525 RTW89_MAC_BF_RRSC_HE_MSC0, 526 RTW89_MAC_BF_RRSC_HE_MSC1, 527 RTW89_MAC_BF_RRSC_HE_MSC2, 528 RTW89_MAC_BF_RRSC_HE_MSC3, 529 RTW89_MAC_BF_RRSC_HE_MSC4, 530 RTW89_MAC_BF_RRSC_HE_MSC5, 531 RTW89_MAC_BF_RRSC_HE_MSC6, 532 RTW89_MAC_BF_RRSC_HE_MSC7 = 31, 533 RTW89_MAC_BF_RRSC_MAX = 32 534 }; 535 536 #define RTW89_R32_EA 0xEAEAEAEA 537 #define RTW89_R32_DEAD 0xDEADBEEF 538 #define MAC_REG_POOL_COUNT 10 539 #define ACCESS_CMAC(_addr) \ 540 ({typeof(_addr) __addr = (_addr); \ 541 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) 542 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000 543 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000 544 545 #define PTCL_IDLE_POLL_CNT 10000 546 #define SW_CVR_DUR_US 8 547 #define SW_CVR_CNT 8 548 549 #define DLE_BOUND_UNIT (8 * 1024) 550 #define DLE_WAIT_CNT 2000 551 #define TRXCFG_WAIT_CNT 2000 552 553 #define RTW89_WDE_PG_64 64 554 #define RTW89_WDE_PG_128 128 555 #define RTW89_WDE_PG_256 256 556 557 #define S_AX_WDE_PAGE_SEL_64 0 558 #define S_AX_WDE_PAGE_SEL_128 1 559 #define S_AX_WDE_PAGE_SEL_256 2 560 561 #define RTW89_PLE_PG_64 64 562 #define RTW89_PLE_PG_128 128 563 #define RTW89_PLE_PG_256 256 564 565 #define S_AX_PLE_PAGE_SEL_64 0 566 #define S_AX_PLE_PAGE_SEL_128 1 567 #define S_AX_PLE_PAGE_SEL_256 2 568 569 #define B_CMAC0_MGQ_NORMAL BIT(2) 570 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3) 571 #define B_CMAC0_CPUMGQ BIT(4) 572 #define B_CMAC1_MGQ_NORMAL BIT(10) 573 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11) 574 #define B_CMAC1_CPUMGQ BIT(12) 575 576 #define B_CMAC0_MGQ_NORMAL_BE BIT(2) 577 #define B_CMAC1_MGQ_NORMAL_BE BIT(30) 578 579 #define QEMP_ACQ_GRP_MACID_NUM 8 580 #define QEMP_ACQ_GRP_QSEL_SH 4 581 #define QEMP_ACQ_GRP_QSEL_MASK 0xF 582 583 #define SDIO_LOCAL_BASE_ADDR 0x80000000 584 585 #define PWR_CMD_WRITE 0 586 #define PWR_CMD_POLL 1 587 #define PWR_CMD_DELAY 2 588 #define PWR_CMD_END 3 589 590 #define PWR_INTF_MSK_SDIO BIT(0) 591 #define PWR_INTF_MSK_USB BIT(1) 592 #define PWR_INTF_MSK_PCIE BIT(2) 593 #define PWR_INTF_MSK_ALL 0x7 594 595 #define PWR_BASE_MAC 0 596 #define PWR_BASE_USB 1 597 #define PWR_BASE_PCIE 2 598 #define PWR_BASE_SDIO 3 599 600 #define PWR_CV_MSK_A BIT(0) 601 #define PWR_CV_MSK_B BIT(1) 602 #define PWR_CV_MSK_C BIT(2) 603 #define PWR_CV_MSK_D BIT(3) 604 #define PWR_CV_MSK_E BIT(4) 605 #define PWR_CV_MSK_F BIT(5) 606 #define PWR_CV_MSK_G BIT(6) 607 #define PWR_CV_MSK_TEST BIT(7) 608 #define PWR_CV_MSK_ALL 0xFF 609 610 #define PWR_DELAY_US 0 611 #define PWR_DELAY_MS 1 612 613 /* STA scheduler */ 614 #define SS_MACID_SH 8 615 #define SS_TX_LEN_MSK 0x1FFFFF 616 #define SS_CTRL1_R_TX_LEN 5 617 #define SS_CTRL1_R_NEXT_LINK 20 618 #define SS_LINK_SIZE 256 619 620 /* MAC debug port */ 621 #define TMAC_DBG_SEL_C0 0xA5 622 #define RMAC_DBG_SEL_C0 0xA6 623 #define TRXPTCL_DBG_SEL_C0 0xA7 624 #define TMAC_DBG_SEL_C1 0xB5 625 #define RMAC_DBG_SEL_C1 0xB6 626 #define TRXPTCL_DBG_SEL_C1 0xB7 627 #define FW_PROG_CNTR_DBG_SEL 0xF2 628 #define PCIE_TXDMA_DBG_SEL 0x30 629 #define PCIE_RXDMA_DBG_SEL 0x31 630 #define PCIE_CVT_DBG_SEL 0x32 631 #define PCIE_CXPL_DBG_SEL 0x33 632 #define PCIE_IO_DBG_SEL 0x37 633 #define PCIE_MISC_DBG_SEL 0x38 634 #define PCIE_MISC2_DBG_SEL 0x00 635 #define MAC_DBG_SEL 1 636 #define RMAC_CMAC_DBG_SEL 1 637 638 /* TRXPTCL dbg port sel */ 639 #define TRXPTRL_DBG_SEL_TMAC 0 640 #define TRXPTRL_DBG_SEL_RMAC 1 641 642 struct rtw89_cpuio_ctrl { 643 u16 pkt_num; 644 u16 start_pktid; 645 u16 end_pktid; 646 u8 cmd_type; 647 u8 macid; 648 u8 src_pid; 649 u8 src_qid; 650 u8 dst_pid; 651 u8 dst_qid; 652 u16 pktid; 653 }; 654 655 struct rtw89_mac_dbg_port_info { 656 u32 sel_addr; 657 u8 sel_byte; 658 u32 sel_msk; 659 u32 srt; 660 u32 end; 661 u32 rd_addr; 662 u8 rd_byte; 663 u32 rd_msk; 664 }; 665 666 #define QLNKTBL_ADDR_INFO_SEL BIT(0) 667 #define QLNKTBL_ADDR_INFO_SEL_0 0 668 #define QLNKTBL_ADDR_INFO_SEL_1 1 669 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) 670 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) 671 672 struct rtw89_mac_dle_dfi_ctrl { 673 enum rtw89_mac_dle_ctrl_type type; 674 u32 target; 675 u32 addr; 676 u32 out_data; 677 }; 678 679 struct rtw89_mac_dle_dfi_quota { 680 enum rtw89_mac_dle_ctrl_type dle_type; 681 u32 qtaid; 682 u16 rsv_pgnum; 683 u16 use_pgnum; 684 }; 685 686 struct rtw89_mac_dle_dfi_qempty { 687 enum rtw89_mac_dle_ctrl_type dle_type; 688 u32 grpsel; 689 u32 qempty; 690 }; 691 692 enum rtw89_mac_dle_rsvd_qt_type { 693 DLE_RSVD_QT_MPDU_INFO, 694 DLE_RSVD_QT_B0_CSI, 695 DLE_RSVD_QT_B1_CSI, 696 DLE_RSVD_QT_B0_LMR, 697 DLE_RSVD_QT_B1_LMR, 698 DLE_RSVD_QT_B0_FTM, 699 DLE_RSVD_QT_B1_FTM, 700 }; 701 702 struct rtw89_mac_dle_rsvd_qt_cfg { 703 u16 pktid; 704 u16 pg_num; 705 u32 size; 706 }; 707 708 enum rtw89_mac_error_scenario { 709 RTW89_RXI300_ERROR = 1, 710 RTW89_WCPU_CPU_EXCEPTION = 2, 711 RTW89_WCPU_ASSERTION = 3, 712 }; 713 714 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28) 715 716 /* Define DBG and recovery enum */ 717 enum mac_ax_err_info { 718 /* Get error info */ 719 720 /* L0 */ 721 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, 722 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, 723 MAC_AX_ERR_L0_RESET_DONE = 0x0003, 724 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, 725 726 /* L1 */ 727 MAC_AX_ERR_L1_PREERR_DMAC = 0x999, 728 MAC_AX_ERR_L1_ERR_DMAC = 0x1000, 729 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, 730 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, 731 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, 732 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, 733 734 /* L2 */ 735 /* address hole (master) */ 736 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, 737 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, 738 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, 739 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, 740 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, 741 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, 742 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, 743 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, 744 745 /* AHB bridge timeout (master) */ 746 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, 747 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, 748 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, 749 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, 750 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, 751 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, 752 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, 753 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, 754 755 /* APB_SA bridge timeout (master + slave) */ 756 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, 757 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, 758 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, 759 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, 760 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, 761 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, 762 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, 763 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, 764 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, 765 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, 766 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, 767 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, 768 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, 769 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, 770 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, 771 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, 772 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, 773 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, 774 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, 775 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, 776 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, 777 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, 778 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, 779 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, 780 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, 781 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, 782 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, 783 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, 784 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, 785 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, 786 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, 787 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, 788 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, 789 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, 790 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, 791 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, 792 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, 793 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, 794 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, 795 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, 796 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, 797 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, 798 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, 799 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, 800 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, 801 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, 802 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, 803 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, 804 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, 805 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, 806 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, 807 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, 808 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, 809 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, 810 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, 811 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, 812 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, 813 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, 814 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, 815 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, 816 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, 817 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, 818 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, 819 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, 820 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, 821 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, 822 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, 823 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, 824 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, 825 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, 826 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, 827 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, 828 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, 829 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, 830 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, 831 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, 832 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, 833 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, 834 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, 835 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, 836 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, 837 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, 838 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, 839 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, 840 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, 841 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, 842 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, 843 844 /* APB_BBRF bridge timeout (master) */ 845 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, 846 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, 847 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, 848 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, 849 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, 850 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, 851 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, 852 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, 853 MAC_AX_ERR_L2_RESET_DONE = 0x2400, 854 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599, 855 MAC_AX_ERR_CPU_EXCEPTION = 0x3000, 856 MAC_AX_ERR_ASSERTION = 0x4000, 857 MAC_AX_ERR_RXI300 = 0x5000, 858 MAC_AX_GET_ERR_MAX, 859 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, 860 861 /* set error info */ 862 MAC_AX_ERR_L1_DISABLE_EN = 0x0001, 863 MAC_AX_ERR_L1_RCVY_EN = 0x0002, 864 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, 865 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, 866 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A, 867 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, 868 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, 869 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, 870 MAC_AX_ERR_L0_RCVY_EN = 0x0013, 871 MAC_AX_SET_ERR_MAX, 872 }; 873 874 struct rtw89_mac_size_set { 875 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie; 876 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0; 877 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2; 878 const struct rtw89_dle_size wde_size0; 879 const struct rtw89_dle_size wde_size0_v1; 880 const struct rtw89_dle_size wde_size4; 881 const struct rtw89_dle_size wde_size4_v1; 882 const struct rtw89_dle_size wde_size6; 883 const struct rtw89_dle_size wde_size7; 884 const struct rtw89_dle_size wde_size9; 885 const struct rtw89_dle_size wde_size18; 886 const struct rtw89_dle_size wde_size19; 887 const struct rtw89_dle_size wde_size23; 888 const struct rtw89_dle_size ple_size0; 889 const struct rtw89_dle_size ple_size0_v1; 890 const struct rtw89_dle_size ple_size3_v1; 891 const struct rtw89_dle_size ple_size4; 892 const struct rtw89_dle_size ple_size6; 893 const struct rtw89_dle_size ple_size8; 894 const struct rtw89_dle_size ple_size9; 895 const struct rtw89_dle_size ple_size18; 896 const struct rtw89_dle_size ple_size19; 897 const struct rtw89_wde_quota wde_qt0; 898 const struct rtw89_wde_quota wde_qt0_v1; 899 const struct rtw89_wde_quota wde_qt4; 900 const struct rtw89_wde_quota wde_qt6; 901 const struct rtw89_wde_quota wde_qt7; 902 const struct rtw89_wde_quota wde_qt17; 903 const struct rtw89_wde_quota wde_qt18; 904 const struct rtw89_wde_quota wde_qt23; 905 const struct rtw89_ple_quota ple_qt0; 906 const struct rtw89_ple_quota ple_qt1; 907 const struct rtw89_ple_quota ple_qt4; 908 const struct rtw89_ple_quota ple_qt5; 909 const struct rtw89_ple_quota ple_qt9; 910 const struct rtw89_ple_quota ple_qt13; 911 const struct rtw89_ple_quota ple_qt18; 912 const struct rtw89_ple_quota ple_qt44; 913 const struct rtw89_ple_quota ple_qt45; 914 const struct rtw89_ple_quota ple_qt46; 915 const struct rtw89_ple_quota ple_qt47; 916 const struct rtw89_ple_quota ple_qt57; 917 const struct rtw89_ple_quota ple_qt58; 918 const struct rtw89_ple_quota ple_qt59; 919 const struct rtw89_ple_quota ple_qt_52a_wow; 920 const struct rtw89_ple_quota ple_qt_52b_wow; 921 const struct rtw89_ple_quota ple_qt_52bt_wow; 922 const struct rtw89_ple_quota ple_qt_51b_wow; 923 const struct rtw89_rsvd_quota ple_rsvd_qt0; 924 const struct rtw89_rsvd_quota ple_rsvd_qt1; 925 const struct rtw89_dle_rsvd_size rsvd0_size0; 926 const struct rtw89_dle_rsvd_size rsvd1_size0; 927 }; 928 929 extern const struct rtw89_mac_size_set rtw89_mac_size; 930 931 struct rtw89_mac_gen_def { 932 u32 band1_offset; 933 u32 filter_model_addr; 934 u32 indir_access_addr; 935 const u32 *mem_base_addrs; 936 u32 rx_fltr; 937 const struct rtw89_port_reg *port_base; 938 u32 agg_len_ht; 939 u32 ps_status; 940 941 struct rtw89_reg_def muedca_ctrl; 942 struct rtw89_reg_def bfee_ctrl; 943 struct rtw89_reg_def narrow_bw_ru_dis; 944 struct rtw89_reg_def wow_ctrl; 945 946 int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band, 947 enum rtw89_mac_hwmod_sel sel); 948 int (*sys_init)(struct rtw89_dev *rtwdev); 949 int (*trx_init)(struct rtw89_dev *rtwdev); 950 void (*hci_func_en)(struct rtw89_dev *rtwdev); 951 void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev); 952 void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable); 953 void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable); 954 void (*bf_assoc)(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 955 struct ieee80211_sta *sta); 956 957 int (*typ_fltr_opt)(struct rtw89_dev *rtwdev, 958 enum rtw89_machdr_frame_type type, 959 enum rtw89_mac_fwd_target fwd_target, 960 u8 mac_idx); 961 int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable); 962 963 int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg); 964 int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple); 965 int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id); 966 void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en); 967 void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev); 968 void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev); 969 void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev); 970 void (*wde_quota_cfg)(struct rtw89_dev *rtwdev, 971 const struct rtw89_wde_quota *min_cfg, 972 const struct rtw89_wde_quota *max_cfg, 973 u16 ext_wde_min_qt_wcpu); 974 void (*ple_quota_cfg)(struct rtw89_dev *rtwdev, 975 const struct rtw89_ple_quota *min_cfg, 976 const struct rtw89_ple_quota *max_cfg); 977 int (*set_cpuio)(struct rtw89_dev *rtwdev, 978 struct rtw89_cpuio_ctrl *ctrl_para, bool wd); 979 int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en); 980 981 void (*disable_cpu)(struct rtw89_dev *rtwdev); 982 int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason, 983 bool dlfw, bool include_bb); 984 u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type); 985 int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl); 986 int (*parse_efuse_map)(struct rtw89_dev *rtwdev); 987 int (*parse_phycap_map)(struct rtw89_dev *rtwdev); 988 int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle); 989 990 int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); 991 u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band); 992 993 bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev, 994 enum rtw89_phy_idx phy_idx, 995 u32 reg_base, u32 *cr); 996 997 int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); 998 int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val); 999 1000 void (*dump_qta_lost)(struct rtw89_dev *rtwdev); 1001 void (*dump_err_status)(struct rtw89_dev *rtwdev, 1002 enum mac_ax_err_info err); 1003 1004 bool (*is_txq_empty)(struct rtw89_dev *rtwdev); 1005 1006 int (*add_chan_list)(struct rtw89_dev *rtwdev, 1007 struct rtw89_vif *rtwvif, bool connected); 1008 int (*add_chan_list_pno)(struct rtw89_dev *rtwdev, 1009 struct rtw89_vif *rtwvif); 1010 int (*scan_offload)(struct rtw89_dev *rtwdev, 1011 struct rtw89_scan_option *option, 1012 struct rtw89_vif *rtwvif, 1013 bool wowlan); 1014 1015 int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow); 1016 }; 1017 1018 extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax; 1019 extern const struct rtw89_mac_gen_def rtw89_mac_gen_be; 1020 1021 static inline 1022 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band) 1023 { 1024 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1025 1026 return band == 0 ? reg_base : (reg_base + mac->band1_offset); 1027 } 1028 1029 static inline 1030 u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx) 1031 { 1032 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx); 1033 } 1034 1035 static inline u32 1036 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base) 1037 { 1038 u32 reg; 1039 1040 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1041 return rtw89_read32(rtwdev, reg); 1042 } 1043 1044 static inline u32 1045 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1046 u32 base, u32 mask) 1047 { 1048 u32 reg; 1049 1050 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1051 return rtw89_read32_mask(rtwdev, reg, mask); 1052 } 1053 1054 static inline void 1055 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, 1056 u32 data) 1057 { 1058 u32 reg; 1059 1060 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1061 rtw89_write32(rtwdev, reg, data); 1062 } 1063 1064 static inline void 1065 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1066 u32 base, u32 mask, u32 data) 1067 { 1068 u32 reg; 1069 1070 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1071 rtw89_write32_mask(rtwdev, reg, mask, data); 1072 } 1073 1074 static inline void 1075 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1076 u32 base, u32 mask, u16 data) 1077 { 1078 u32 reg; 1079 1080 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1081 rtw89_write16_mask(rtwdev, reg, mask, data); 1082 } 1083 1084 static inline void 1085 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1086 u32 base, u32 bit) 1087 { 1088 u32 reg; 1089 1090 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1091 rtw89_write32_clr(rtwdev, reg, bit); 1092 } 1093 1094 static inline void 1095 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1096 u32 base, u16 bit) 1097 { 1098 u32 reg; 1099 1100 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1101 rtw89_write16_clr(rtwdev, reg, bit); 1102 } 1103 1104 static inline void 1105 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1106 u32 base, u32 bit) 1107 { 1108 u32 reg; 1109 1110 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx); 1111 rtw89_write32_set(rtwdev, reg, bit); 1112 } 1113 1114 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); 1115 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb); 1116 int rtw89_mac_init(struct rtw89_dev *rtwdev); 1117 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1118 enum rtw89_qta_mode ext_mode); 1119 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en); 1120 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1121 enum rtw89_qta_mode mode); 1122 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode); 1123 static inline 1124 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, 1125 enum rtw89_mac_hwmod_sel sel) 1126 { 1127 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1128 1129 return mac->check_mac_en(rtwdev, band, sel); 1130 } 1131 1132 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); 1133 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); 1134 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl); 1135 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 1136 struct rtw89_mac_dle_dfi_quota *quota); 1137 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev); 1138 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 1139 struct rtw89_mac_dle_dfi_qempty *qempty); 1140 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 1141 enum mac_ax_err_info err); 1142 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 1143 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1144 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 1145 struct rtw89_vif *rtwvif, 1146 struct rtw89_vif *rtwvif_src, 1147 u16 offset_tu); 1148 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1149 u64 *tsf); 1150 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 1151 struct rtw89_vif *rtwvif, bool en); 1152 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 1153 struct ieee80211_vif *vif); 1154 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1155 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en); 1156 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 1157 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); 1158 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); 1159 1160 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev) 1161 { 1162 const struct rtw89_chip_info *chip = rtwdev->chip; 1163 1164 return chip->ops->enable_bb_rf(rtwdev); 1165 } 1166 1167 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev) 1168 { 1169 const struct rtw89_chip_info *chip = rtwdev->chip; 1170 1171 return chip->ops->disable_bb_rf(rtwdev); 1172 } 1173 1174 static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev) 1175 { 1176 int ret; 1177 1178 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 1179 return 0; 1180 1181 ret = rtw89_chip_disable_bb_rf(rtwdev); 1182 if (ret) 1183 return ret; 1184 ret = rtw89_chip_enable_bb_rf(rtwdev); 1185 if (ret) 1186 return ret; 1187 1188 return 0; 1189 } 1190 1191 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); 1192 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); 1193 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 1194 u8 class, u8 func); 1195 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1196 u32 len, u8 class, u8 func); 1197 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); 1198 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 1199 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1200 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 1201 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1202 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, 1203 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1204 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1205 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1206 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1207 1208 static inline 1209 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 1210 { 1211 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1212 1213 return mac->cfg_ppdu_status(rtwdev, mac_idx, enable); 1214 } 1215 1216 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx); 1217 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); 1218 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); 1219 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 1220 const struct rtw89_mac_ax_coex *coex); 1221 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 1222 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1223 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 1224 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1225 int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev, 1226 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1227 1228 static inline 1229 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 1230 { 1231 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1232 1233 return mac->cfg_plt(rtwdev, plt); 1234 } 1235 1236 static inline 1237 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 1238 { 1239 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1240 1241 return mac->get_plt_cnt(rtwdev, band); 1242 } 1243 1244 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); 1245 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); 1246 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); 1247 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); 1248 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); 1249 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl); 1250 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); 1251 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); 1252 1253 static inline 1254 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1255 struct ieee80211_sta *sta) 1256 { 1257 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1258 1259 if (mac->bf_assoc) 1260 mac->bf_assoc(rtwdev, vif, sta); 1261 } 1262 1263 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1264 struct ieee80211_sta *sta); 1265 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1266 struct ieee80211_bss_conf *conf); 1267 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 1268 struct ieee80211_sta *sta, bool disconnect); 1269 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); 1270 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en); 1271 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1272 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1273 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 1274 struct rtw89_vif *rtwvif, bool en); 1275 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause); 1276 1277 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 1278 { 1279 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 1280 return; 1281 1282 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) 1283 return; 1284 1285 _rtw89_mac_bf_monitor_track(rtwdev); 1286 } 1287 1288 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, 1289 enum rtw89_phy_idx phy_idx, 1290 u32 reg_base, u32 *val) 1291 { 1292 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1293 u32 cr; 1294 1295 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1296 return -EINVAL; 1297 1298 *val = rtw89_read32(rtwdev, cr); 1299 return 0; 1300 } 1301 1302 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, 1303 enum rtw89_phy_idx phy_idx, 1304 u32 reg_base, u32 val) 1305 { 1306 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1307 u32 cr; 1308 1309 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1310 return -EINVAL; 1311 1312 rtw89_write32(rtwdev, cr, val); 1313 return 0; 1314 } 1315 1316 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, 1317 enum rtw89_phy_idx phy_idx, 1318 u32 reg_base, u32 mask, u32 val) 1319 { 1320 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1321 u32 cr; 1322 1323 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1324 return -EINVAL; 1325 1326 rtw89_write32_mask(rtwdev, cr, mask, val); 1327 return 0; 1328 } 1329 1330 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev, 1331 bool enable) 1332 { 1333 const struct rtw89_chip_info *chip = rtwdev->chip; 1334 1335 if (enable) 1336 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1337 B_AX_HCI_TXDMA_EN); 1338 else 1339 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1340 B_AX_HCI_TXDMA_EN); 1341 } 1342 1343 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev, 1344 bool enable) 1345 { 1346 const struct rtw89_chip_info *chip = rtwdev->chip; 1347 1348 if (enable) 1349 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1350 B_AX_HCI_RXDMA_EN); 1351 else 1352 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1353 B_AX_HCI_RXDMA_EN); 1354 } 1355 1356 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev, 1357 bool enable) 1358 { 1359 const struct rtw89_chip_info *chip = rtwdev->chip; 1360 1361 if (enable) 1362 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1363 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1364 else 1365 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1366 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1367 } 1368 1369 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev) 1370 { 1371 u32 val; 1372 1373 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, 1374 B_AX_WLMAC_PWR_STE_MASK); 1375 1376 return !!val; 1377 } 1378 1379 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 1380 bool resume, u32 tx_time); 1381 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 1382 u32 *tx_time); 1383 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 1384 struct rtw89_sta *rtwsta, 1385 bool resume, u8 tx_retry); 1386 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 1387 struct rtw89_sta *rtwsta, u8 *tx_retry); 1388 1389 enum rtw89_mac_xtal_si_offset { 1390 XTAL0 = 0x0, 1391 XTAL3 = 0x3, 1392 XTAL_SI_XTAL_SC_XI = 0x04, 1393 #define XTAL_SC_XI_MASK GENMASK(7, 0) 1394 XTAL_SI_XTAL_SC_XO = 0x05, 1395 #define XTAL_SC_XO_MASK GENMASK(7, 0) 1396 XTAL_SI_XREF_MODE = 0x0B, 1397 XTAL_SI_PWR_CUT = 0x10, 1398 #define XTAL_SI_SMALL_PWR_CUT BIT(0) 1399 #define XTAL_SI_BIG_PWR_CUT BIT(1) 1400 XTAL_SI_XTAL_DRV = 0x15, 1401 #define XTAL_SI_DRV_LATCH BIT(4) 1402 XTAL_SI_XTAL_PLL = 0x16, 1403 XTAL_SI_XTAL_XMD_2 = 0x24, 1404 #define XTAL_SI_LDO_LPS GENMASK(6, 4) 1405 XTAL_SI_XTAL_XMD_4 = 0x26, 1406 #define XTAL_SI_LPS_CAP GENMASK(3, 0) 1407 XTAL_SI_XREF_RF1 = 0x2D, 1408 XTAL_SI_XREF_RF2 = 0x2E, 1409 XTAL_SI_CV = 0x41, 1410 #define XTAL_SI_ACV_MASK GENMASK(3, 0) 1411 XTAL_SI_LOW_ADDR = 0x62, 1412 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0) 1413 XTAL_SI_CTRL = 0x63, 1414 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6) 1415 #define XTAL_SI_RDY BIT(5) 1416 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0) 1417 XTAL_SI_READ_VAL = 0x7A, 1418 XTAL_SI_WL_RFC_S0 = 0x80, 1419 #define XTAL_SI_RF00S_EN GENMASK(2, 0) 1420 #define XTAL_SI_RF00 BIT(0) 1421 XTAL_SI_WL_RFC_S1 = 0x81, 1422 #define XTAL_SI_RF10S_EN GENMASK(2, 0) 1423 #define XTAL_SI_RF10 BIT(0) 1424 XTAL_SI_ANAPAR_WL = 0x90, 1425 #define XTAL_SI_SRAM2RFC BIT(7) 1426 #define XTAL_SI_GND_SHDN_WL BIT(6) 1427 #define XTAL_SI_SHDN_WL BIT(5) 1428 #define XTAL_SI_RFC2RF BIT(4) 1429 #define XTAL_SI_OFF_EI BIT(3) 1430 #define XTAL_SI_OFF_WEI BIT(2) 1431 #define XTAL_SI_PON_EI BIT(1) 1432 #define XTAL_SI_PON_WEI BIT(0) 1433 XTAL_SI_SRAM_CTRL = 0xA1, 1434 #define XTAL_SI_SRAM_DIS BIT(1) 1435 #define FULL_BIT_MASK GENMASK(7, 0) 1436 XTAL_SI_APBT = 0xD1, 1437 XTAL_SI_PLL = 0xE0, 1438 XTAL_SI_PLL_1 = 0xE1, 1439 }; 1440 1441 static inline 1442 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 1443 { 1444 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1445 1446 return mac->write_xtal_si(rtwdev, offset, val, mask); 1447 } 1448 1449 static inline 1450 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 1451 { 1452 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1453 1454 return mac->read_xtal_si(rtwdev, offset, val); 1455 } 1456 1457 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1458 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow); 1459 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 1460 enum rtw89_mac_idx band); 1461 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow); 1462 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1463 bool band1_en); 1464 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1465 enum rtw89_mac_dle_rsvd_qt_type type, 1466 struct rtw89_mac_dle_rsvd_qt_cfg *cfg); 1467 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable); 1468 1469 #endif 1470