1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_MAC_H__ 6 #define __RTW89_MAC_H__ 7 8 #include "core.h" 9 10 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000 11 #define ADDR_CAM_ENT_SIZE 0x40 12 #define BSSID_CAM_ENT_SIZE 0x08 13 #define HFC_PAGE_UNIT 64 14 15 enum rtw89_mac_hwmod_sel { 16 RTW89_DMAC_SEL = 0, 17 RTW89_CMAC_SEL = 1, 18 19 RTW89_MAC_INVALID, 20 }; 21 22 enum rtw89_mac_fwd_target { 23 RTW89_FWD_DONT_CARE = 0, 24 RTW89_FWD_TO_HOST = 1, 25 RTW89_FWD_TO_WLAN_CPU = 2 26 }; 27 28 enum rtw89_mac_wd_dma_intvl { 29 RTW89_MAC_WD_DMA_INTVL_0S, 30 RTW89_MAC_WD_DMA_INTVL_256NS, 31 RTW89_MAC_WD_DMA_INTVL_512NS, 32 RTW89_MAC_WD_DMA_INTVL_768NS, 33 RTW89_MAC_WD_DMA_INTVL_1US, 34 RTW89_MAC_WD_DMA_INTVL_1_5US, 35 RTW89_MAC_WD_DMA_INTVL_2US, 36 RTW89_MAC_WD_DMA_INTVL_4US, 37 RTW89_MAC_WD_DMA_INTVL_8US, 38 RTW89_MAC_WD_DMA_INTVL_16US, 39 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE 40 }; 41 42 enum rtw89_mac_multi_tag_num { 43 RTW89_MAC_TAG_NUM_1, 44 RTW89_MAC_TAG_NUM_2, 45 RTW89_MAC_TAG_NUM_3, 46 RTW89_MAC_TAG_NUM_4, 47 RTW89_MAC_TAG_NUM_5, 48 RTW89_MAC_TAG_NUM_6, 49 RTW89_MAC_TAG_NUM_7, 50 RTW89_MAC_TAG_NUM_8, 51 RTW89_MAC_TAG_NUM_DEF = 0xFE 52 }; 53 54 enum rtw89_mac_lbc_tmr { 55 RTW89_MAC_LBC_TMR_8US = 0, 56 RTW89_MAC_LBC_TMR_16US, 57 RTW89_MAC_LBC_TMR_32US, 58 RTW89_MAC_LBC_TMR_64US, 59 RTW89_MAC_LBC_TMR_128US, 60 RTW89_MAC_LBC_TMR_256US, 61 RTW89_MAC_LBC_TMR_512US, 62 RTW89_MAC_LBC_TMR_1MS, 63 RTW89_MAC_LBC_TMR_2MS, 64 RTW89_MAC_LBC_TMR_4MS, 65 RTW89_MAC_LBC_TMR_8MS, 66 RTW89_MAC_LBC_TMR_DEF = 0xFE 67 }; 68 69 enum rtw89_mac_cpuio_op_cmd_type { 70 CPUIO_OP_CMD_GET_1ST_PID = 0, 71 CPUIO_OP_CMD_GET_NEXT_PID = 1, 72 CPUIO_OP_CMD_ENQ_TO_TAIL = 4, 73 CPUIO_OP_CMD_ENQ_TO_HEAD = 5, 74 CPUIO_OP_CMD_DEQ = 8, 75 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, 76 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 77 }; 78 79 enum rtw89_mac_wde_dle_port_id { 80 WDE_DLE_PORT_ID_DISPATCH = 0, 81 WDE_DLE_PORT_ID_PKTIN = 1, 82 WDE_DLE_PORT_ID_CMAC0 = 3, 83 WDE_DLE_PORT_ID_CMAC1 = 4, 84 WDE_DLE_PORT_ID_CPU_IO = 6, 85 WDE_DLE_PORT_ID_WDRLS = 7, 86 WDE_DLE_PORT_ID_END = 8 87 }; 88 89 enum rtw89_mac_wde_dle_queid_wdrls { 90 WDE_DLE_QUEID_TXOK = 0, 91 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, 92 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, 93 WDE_DLE_QUEID_DROP_MACID_DROP = 3, 94 WDE_DLE_QUEID_NO_REPORT = 4 95 }; 96 97 enum rtw89_mac_ple_dle_port_id { 98 PLE_DLE_PORT_ID_DISPATCH = 0, 99 PLE_DLE_PORT_ID_MPDU = 1, 100 PLE_DLE_PORT_ID_SEC = 2, 101 PLE_DLE_PORT_ID_CMAC0 = 3, 102 PLE_DLE_PORT_ID_CMAC1 = 4, 103 PLE_DLE_PORT_ID_WDRLS = 5, 104 PLE_DLE_PORT_ID_CPU_IO = 6, 105 PLE_DLE_PORT_ID_PLRLS = 7, 106 PLE_DLE_PORT_ID_END = 8 107 }; 108 109 enum rtw89_mac_ple_dle_queid_plrls { 110 PLE_DLE_QUEID_NO_REPORT = 0x0 111 }; 112 113 enum rtw89_machdr_frame_type { 114 RTW89_MGNT = 0, 115 RTW89_CTRL = 1, 116 RTW89_DATA = 2, 117 }; 118 119 enum rtw89_mac_dle_dfi_type { 120 DLE_DFI_TYPE_FREEPG = 0, 121 DLE_DFI_TYPE_QUOTA = 1, 122 DLE_DFI_TYPE_PAGELLT = 2, 123 DLE_DFI_TYPE_PKTINFO = 3, 124 DLE_DFI_TYPE_PREPKTLLT = 4, 125 DLE_DFI_TYPE_NXTPKTLLT = 5, 126 DLE_DFI_TYPE_QLNKTBL = 6, 127 DLE_DFI_TYPE_QEMPTY = 7, 128 }; 129 130 enum rtw89_mac_dle_wde_quota_id { 131 WDE_QTAID_HOST_IF = 0, 132 WDE_QTAID_WLAN_CPU = 1, 133 WDE_QTAID_DATA_CPU = 2, 134 WDE_QTAID_PKTIN = 3, 135 WDE_QTAID_CPUIO = 4, 136 }; 137 138 enum rtw89_mac_dle_ple_quota_id { 139 PLE_QTAID_B0_TXPL = 0, 140 PLE_QTAID_B1_TXPL = 1, 141 PLE_QTAID_C2H = 2, 142 PLE_QTAID_H2C = 3, 143 PLE_QTAID_WLAN_CPU = 4, 144 PLE_QTAID_MPDU = 5, 145 PLE_QTAID_CMAC0_RX = 6, 146 PLE_QTAID_CMAC1_RX = 7, 147 PLE_QTAID_CMAC1_BBRPT = 8, 148 PLE_QTAID_WDRLS = 9, 149 PLE_QTAID_CPUIO = 10, 150 }; 151 152 enum rtw89_mac_dle_ctrl_type { 153 DLE_CTRL_TYPE_WDE = 0, 154 DLE_CTRL_TYPE_PLE = 1, 155 DLE_CTRL_TYPE_NUM = 2, 156 }; 157 158 enum rtw89_mac_ax_l0_to_l1_event { 159 MAC_AX_L0_TO_L1_CHIF_IDLE = 0, 160 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, 161 MAC_AX_L0_TO_L1_RLS_PKID = 2, 162 MAC_AX_L0_TO_L1_PTCL_IDLE = 3, 163 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, 164 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, 165 MAC_AX_L0_TO_L1_PCIE_STUCK = 6, 166 MAC_AX_L0_TO_L1_EVENT_MAX = 15, 167 }; 168 169 enum rtw89_mac_dbg_port_sel { 170 /* CMAC 0 related */ 171 RTW89_DBG_PORT_SEL_PTCL_C0 = 0, 172 RTW89_DBG_PORT_SEL_SCH_C0, 173 RTW89_DBG_PORT_SEL_TMAC_C0, 174 RTW89_DBG_PORT_SEL_RMAC_C0, 175 RTW89_DBG_PORT_SEL_RMACST_C0, 176 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, 177 RTW89_DBG_PORT_SEL_TRXPTCL_C0, 178 RTW89_DBG_PORT_SEL_TX_INFOL_C0, 179 RTW89_DBG_PORT_SEL_TX_INFOH_C0, 180 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, 181 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, 182 /* CMAC 1 related */ 183 RTW89_DBG_PORT_SEL_PTCL_C1, 184 RTW89_DBG_PORT_SEL_SCH_C1, 185 RTW89_DBG_PORT_SEL_TMAC_C1, 186 RTW89_DBG_PORT_SEL_RMAC_C1, 187 RTW89_DBG_PORT_SEL_RMACST_C1, 188 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, 189 RTW89_DBG_PORT_SEL_TRXPTCL_C1, 190 RTW89_DBG_PORT_SEL_TX_INFOL_C1, 191 RTW89_DBG_PORT_SEL_TX_INFOH_C1, 192 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, 193 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, 194 /* DLE related */ 195 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, 196 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, 197 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, 198 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, 199 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, 200 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, 201 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, 202 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, 203 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, 204 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, 205 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, 206 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, 207 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, 208 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, 209 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, 210 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, 211 RTW89_DBG_PORT_SEL_PKTINFO, 212 /* PCIE related */ 213 RTW89_DBG_PORT_SEL_PCIE_TXDMA, 214 RTW89_DBG_PORT_SEL_PCIE_RXDMA, 215 RTW89_DBG_PORT_SEL_PCIE_CVT, 216 RTW89_DBG_PORT_SEL_PCIE_CXPL, 217 RTW89_DBG_PORT_SEL_PCIE_IO, 218 RTW89_DBG_PORT_SEL_PCIE_MISC, 219 RTW89_DBG_PORT_SEL_PCIE_MISC2, 220 221 /* keep last */ 222 RTW89_DBG_PORT_SEL_LAST, 223 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, 224 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, 225 }; 226 227 /* SRAM mem dump */ 228 #define R_AX_INDIR_ACCESS_ENTRY 0x40000 229 230 #define AXIDMA_BASE_ADDR 0x18006000 231 #define STA_SCHED_BASE_ADDR 0x18808000 232 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 233 #define SECURITY_CAM_BASE_ADDR 0x18814000 234 #define WOW_CAM_BASE_ADDR 0x18815000 235 #define CMAC_TBL_BASE_ADDR 0x18840000 236 #define ADDR_CAM_BASE_ADDR 0x18850000 237 #define BSSID_CAM_BASE_ADDR 0x18853000 238 #define BA_CAM_BASE_ADDR 0x18854000 239 #define BCN_IE_CAM0_BASE_ADDR 0x18855000 240 #define SHARED_BUF_BASE_ADDR 0x18700000 241 #define DMAC_TBL_BASE_ADDR 0x18800000 242 #define SHCUT_MACHDR_BASE_ADDR 0x18800800 243 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000 244 #define TXD_FIFO_0_BASE_ADDR 0x18856200 245 #define TXD_FIFO_1_BASE_ADDR 0x188A1080 246 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000 247 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 248 #define CPU_LOCAL_BASE_ADDR 0x18003000 249 250 #define CCTL_INFO_SIZE 32 251 252 enum rtw89_mac_mem_sel { 253 RTW89_MAC_MEM_AXIDMA, 254 RTW89_MAC_MEM_SHARED_BUF, 255 RTW89_MAC_MEM_DMAC_TBL, 256 RTW89_MAC_MEM_SHCUT_MACHDR, 257 RTW89_MAC_MEM_STA_SCHED, 258 RTW89_MAC_MEM_RXPLD_FLTR_CAM, 259 RTW89_MAC_MEM_SECURITY_CAM, 260 RTW89_MAC_MEM_WOW_CAM, 261 RTW89_MAC_MEM_CMAC_TBL, 262 RTW89_MAC_MEM_ADDR_CAM, 263 RTW89_MAC_MEM_BA_CAM, 264 RTW89_MAC_MEM_BCN_IE_CAM0, 265 RTW89_MAC_MEM_BCN_IE_CAM1, 266 RTW89_MAC_MEM_TXD_FIFO_0, 267 RTW89_MAC_MEM_TXD_FIFO_1, 268 RTW89_MAC_MEM_TXDATA_FIFO_0, 269 RTW89_MAC_MEM_TXDATA_FIFO_1, 270 RTW89_MAC_MEM_CPU_LOCAL, 271 272 /* keep last */ 273 RTW89_MAC_MEM_NUM, 274 }; 275 276 extern const u32 rtw89_mac_mem_base_addrs[]; 277 278 enum rtw89_rpwm_req_pwr_state { 279 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, 280 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, 281 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, 282 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, 283 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, 284 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, 285 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, 286 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, 287 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, 288 }; 289 290 struct rtw89_pwr_cfg { 291 u16 addr; 292 u8 cv_msk; 293 u8 intf_msk; 294 u8 base:4; 295 u8 cmd:4; 296 u8 msk; 297 u8 val; 298 }; 299 300 enum rtw89_mac_c2h_ofld_func { 301 RTW89_MAC_C2H_FUNC_EFUSE_DUMP, 302 RTW89_MAC_C2H_FUNC_READ_RSP, 303 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, 304 RTW89_MAC_C2H_FUNC_BCN_RESEND, 305 RTW89_MAC_C2H_FUNC_MACID_PAUSE, 306 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9, 307 RTW89_MAC_C2H_FUNC_OFLD_MAX, 308 }; 309 310 enum rtw89_mac_c2h_info_func { 311 RTW89_MAC_C2H_FUNC_REC_ACK, 312 RTW89_MAC_C2H_FUNC_DONE_ACK, 313 RTW89_MAC_C2H_FUNC_C2H_LOG, 314 RTW89_MAC_C2H_FUNC_BCN_CNT, 315 RTW89_MAC_C2H_FUNC_INFO_MAX, 316 }; 317 318 enum rtw89_mac_c2h_class { 319 RTW89_MAC_C2H_CLASS_INFO, 320 RTW89_MAC_C2H_CLASS_OFLD, 321 RTW89_MAC_C2H_CLASS_TWT, 322 RTW89_MAC_C2H_CLASS_WOW, 323 RTW89_MAC_C2H_CLASS_MCC, 324 RTW89_MAC_C2H_CLASS_FWDBG, 325 RTW89_MAC_C2H_CLASS_MAX, 326 }; 327 328 struct rtw89_mac_ax_coex { 329 #define RTW89_MAC_AX_COEX_RTK_MODE 0 330 #define RTW89_MAC_AX_COEX_CSR_MODE 1 331 u8 pta_mode; 332 #define RTW89_MAC_AX_COEX_INNER 0 333 #define RTW89_MAC_AX_COEX_OUTPUT 1 334 #define RTW89_MAC_AX_COEX_INPUT 2 335 u8 direction; 336 }; 337 338 struct rtw89_mac_ax_plt { 339 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0) 340 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) 341 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) 342 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3) 343 u8 band; 344 u8 tx; 345 u8 rx; 346 }; 347 348 enum rtw89_mac_bf_rrsc_rate { 349 RTW89_MAC_BF_RRSC_6M = 0, 350 RTW89_MAC_BF_RRSC_9M = 1, 351 RTW89_MAC_BF_RRSC_12M, 352 RTW89_MAC_BF_RRSC_18M, 353 RTW89_MAC_BF_RRSC_24M, 354 RTW89_MAC_BF_RRSC_36M, 355 RTW89_MAC_BF_RRSC_48M, 356 RTW89_MAC_BF_RRSC_54M, 357 RTW89_MAC_BF_RRSC_HT_MSC0, 358 RTW89_MAC_BF_RRSC_HT_MSC1, 359 RTW89_MAC_BF_RRSC_HT_MSC2, 360 RTW89_MAC_BF_RRSC_HT_MSC3, 361 RTW89_MAC_BF_RRSC_HT_MSC4, 362 RTW89_MAC_BF_RRSC_HT_MSC5, 363 RTW89_MAC_BF_RRSC_HT_MSC6, 364 RTW89_MAC_BF_RRSC_HT_MSC7, 365 RTW89_MAC_BF_RRSC_VHT_MSC0, 366 RTW89_MAC_BF_RRSC_VHT_MSC1, 367 RTW89_MAC_BF_RRSC_VHT_MSC2, 368 RTW89_MAC_BF_RRSC_VHT_MSC3, 369 RTW89_MAC_BF_RRSC_VHT_MSC4, 370 RTW89_MAC_BF_RRSC_VHT_MSC5, 371 RTW89_MAC_BF_RRSC_VHT_MSC6, 372 RTW89_MAC_BF_RRSC_VHT_MSC7, 373 RTW89_MAC_BF_RRSC_HE_MSC0, 374 RTW89_MAC_BF_RRSC_HE_MSC1, 375 RTW89_MAC_BF_RRSC_HE_MSC2, 376 RTW89_MAC_BF_RRSC_HE_MSC3, 377 RTW89_MAC_BF_RRSC_HE_MSC4, 378 RTW89_MAC_BF_RRSC_HE_MSC5, 379 RTW89_MAC_BF_RRSC_HE_MSC6, 380 RTW89_MAC_BF_RRSC_HE_MSC7 = 31, 381 RTW89_MAC_BF_RRSC_MAX = 32 382 }; 383 384 #define RTW89_R32_EA 0xEAEAEAEA 385 #define RTW89_R32_DEAD 0xDEADBEEF 386 #define MAC_REG_POOL_COUNT 10 387 #define ACCESS_CMAC(_addr) \ 388 ({typeof(_addr) __addr = (_addr); \ 389 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) 390 391 #define PTCL_IDLE_POLL_CNT 10000 392 #define SW_CVR_DUR_US 8 393 #define SW_CVR_CNT 8 394 395 #define DLE_BOUND_UNIT (8 * 1024) 396 #define DLE_WAIT_CNT 2000 397 #define TRXCFG_WAIT_CNT 2000 398 399 #define RTW89_WDE_PG_64 64 400 #define RTW89_WDE_PG_128 128 401 #define RTW89_WDE_PG_256 256 402 403 #define S_AX_WDE_PAGE_SEL_64 0 404 #define S_AX_WDE_PAGE_SEL_128 1 405 #define S_AX_WDE_PAGE_SEL_256 2 406 407 #define RTW89_PLE_PG_64 64 408 #define RTW89_PLE_PG_128 128 409 #define RTW89_PLE_PG_256 256 410 411 #define S_AX_PLE_PAGE_SEL_64 0 412 #define S_AX_PLE_PAGE_SEL_128 1 413 #define S_AX_PLE_PAGE_SEL_256 2 414 415 #define SDIO_LOCAL_BASE_ADDR 0x80000000 416 417 #define PWR_CMD_WRITE 0 418 #define PWR_CMD_POLL 1 419 #define PWR_CMD_DELAY 2 420 #define PWR_CMD_END 3 421 422 #define PWR_INTF_MSK_SDIO BIT(0) 423 #define PWR_INTF_MSK_USB BIT(1) 424 #define PWR_INTF_MSK_PCIE BIT(2) 425 #define PWR_INTF_MSK_ALL 0x7 426 427 #define PWR_BASE_MAC 0 428 #define PWR_BASE_USB 1 429 #define PWR_BASE_PCIE 2 430 #define PWR_BASE_SDIO 3 431 432 #define PWR_CV_MSK_A BIT(0) 433 #define PWR_CV_MSK_B BIT(1) 434 #define PWR_CV_MSK_C BIT(2) 435 #define PWR_CV_MSK_D BIT(3) 436 #define PWR_CV_MSK_E BIT(4) 437 #define PWR_CV_MSK_F BIT(5) 438 #define PWR_CV_MSK_G BIT(6) 439 #define PWR_CV_MSK_TEST BIT(7) 440 #define PWR_CV_MSK_ALL 0xFF 441 442 #define PWR_DELAY_US 0 443 #define PWR_DELAY_MS 1 444 445 /* STA scheduler */ 446 #define SS_MACID_SH 8 447 #define SS_TX_LEN_MSK 0x1FFFFF 448 #define SS_CTRL1_R_TX_LEN 5 449 #define SS_CTRL1_R_NEXT_LINK 20 450 #define SS_LINK_SIZE 256 451 452 /* MAC debug port */ 453 #define TMAC_DBG_SEL_C0 0xA5 454 #define RMAC_DBG_SEL_C0 0xA6 455 #define TRXPTCL_DBG_SEL_C0 0xA7 456 #define TMAC_DBG_SEL_C1 0xB5 457 #define RMAC_DBG_SEL_C1 0xB6 458 #define TRXPTCL_DBG_SEL_C1 0xB7 459 #define FW_PROG_CNTR_DBG_SEL 0xF2 460 #define PCIE_TXDMA_DBG_SEL 0x30 461 #define PCIE_RXDMA_DBG_SEL 0x31 462 #define PCIE_CVT_DBG_SEL 0x32 463 #define PCIE_CXPL_DBG_SEL 0x33 464 #define PCIE_IO_DBG_SEL 0x37 465 #define PCIE_MISC_DBG_SEL 0x38 466 #define PCIE_MISC2_DBG_SEL 0x00 467 #define MAC_DBG_SEL 1 468 #define RMAC_CMAC_DBG_SEL 1 469 470 /* TRXPTCL dbg port sel */ 471 #define TRXPTRL_DBG_SEL_TMAC 0 472 #define TRXPTRL_DBG_SEL_RMAC 1 473 474 struct rtw89_cpuio_ctrl { 475 u16 pkt_num; 476 u16 start_pktid; 477 u16 end_pktid; 478 u8 cmd_type; 479 u8 macid; 480 u8 src_pid; 481 u8 src_qid; 482 u8 dst_pid; 483 u8 dst_qid; 484 u16 pktid; 485 }; 486 487 struct rtw89_mac_dbg_port_info { 488 u32 sel_addr; 489 u8 sel_byte; 490 u32 sel_msk; 491 u32 srt; 492 u32 end; 493 u32 rd_addr; 494 u8 rd_byte; 495 u32 rd_msk; 496 }; 497 498 #define QLNKTBL_ADDR_INFO_SEL BIT(0) 499 #define QLNKTBL_ADDR_INFO_SEL_0 0 500 #define QLNKTBL_ADDR_INFO_SEL_1 1 501 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) 502 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) 503 504 struct rtw89_mac_dle_dfi_ctrl { 505 enum rtw89_mac_dle_ctrl_type type; 506 u32 target; 507 u32 addr; 508 u32 out_data; 509 }; 510 511 struct rtw89_mac_dle_dfi_quota { 512 enum rtw89_mac_dle_ctrl_type dle_type; 513 u32 qtaid; 514 u16 rsv_pgnum; 515 u16 use_pgnum; 516 }; 517 518 struct rtw89_mac_dle_dfi_qempty { 519 enum rtw89_mac_dle_ctrl_type dle_type; 520 u32 grpsel; 521 u32 qempty; 522 }; 523 524 enum rtw89_mac_error_scenario { 525 RTW89_WCPU_CPU_EXCEPTION = 2, 526 RTW89_WCPU_ASSERTION = 3, 527 }; 528 529 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28) 530 531 /* Define DBG and recovery enum */ 532 enum mac_ax_err_info { 533 /* Get error info */ 534 535 /* L0 */ 536 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, 537 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, 538 MAC_AX_ERR_L0_RESET_DONE = 0x0003, 539 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, 540 541 /* L1 */ 542 MAC_AX_ERR_L1_ERR_DMAC = 0x1000, 543 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, 544 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, 545 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, 546 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, 547 548 /* L2 */ 549 /* address hole (master) */ 550 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, 551 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, 552 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, 553 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, 554 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, 555 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, 556 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, 557 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, 558 559 /* AHB bridge timeout (master) */ 560 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, 561 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, 562 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, 563 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, 564 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, 565 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, 566 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, 567 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, 568 569 /* APB_SA bridge timeout (master + slave) */ 570 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, 571 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, 572 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, 573 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, 574 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, 575 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, 576 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, 577 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, 578 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, 579 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, 580 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, 581 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, 582 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, 583 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, 584 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, 585 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, 586 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, 587 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, 588 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, 589 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, 590 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, 591 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, 592 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, 593 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, 594 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, 595 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, 596 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, 597 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, 598 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, 599 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, 600 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, 601 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, 602 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, 603 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, 604 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, 605 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, 606 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, 607 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, 608 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, 609 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, 610 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, 611 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, 612 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, 613 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, 614 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, 615 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, 616 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, 617 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, 618 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, 619 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, 620 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, 621 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, 622 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, 623 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, 624 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, 625 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, 626 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, 627 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, 628 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, 629 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, 630 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, 631 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, 632 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, 633 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, 634 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, 635 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, 636 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, 637 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, 638 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, 639 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, 640 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, 641 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, 642 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, 643 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, 644 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, 645 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, 646 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, 647 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, 648 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, 649 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, 650 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, 651 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, 652 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, 653 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, 654 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, 655 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, 656 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, 657 658 /* APB_BBRF bridge timeout (master) */ 659 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, 660 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, 661 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, 662 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, 663 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, 664 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, 665 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, 666 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, 667 MAC_AX_ERR_L2_RESET_DONE = 0x2400, 668 MAC_AX_ERR_CPU_EXCEPTION = 0x3000, 669 MAC_AX_ERR_ASSERTION = 0x4000, 670 MAC_AX_GET_ERR_MAX, 671 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, 672 673 /* set error info */ 674 MAC_AX_ERR_L1_DISABLE_EN = 0x0001, 675 MAC_AX_ERR_L1_RCVY_EN = 0x0002, 676 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, 677 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, 678 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, 679 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, 680 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, 681 MAC_AX_ERR_L0_RCVY_EN = 0x0013, 682 MAC_AX_SET_ERR_MAX, 683 }; 684 685 struct rtw89_mac_size_set { 686 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie; 687 const struct rtw89_dle_size wde_size0; 688 const struct rtw89_dle_size wde_size4; 689 const struct rtw89_dle_size wde_size18; 690 const struct rtw89_dle_size wde_size19; 691 const struct rtw89_dle_size ple_size0; 692 const struct rtw89_dle_size ple_size4; 693 const struct rtw89_dle_size ple_size18; 694 const struct rtw89_dle_size ple_size19; 695 const struct rtw89_wde_quota wde_qt0; 696 const struct rtw89_wde_quota wde_qt4; 697 const struct rtw89_wde_quota wde_qt17; 698 const struct rtw89_wde_quota wde_qt18; 699 const struct rtw89_ple_quota ple_qt4; 700 const struct rtw89_ple_quota ple_qt5; 701 const struct rtw89_ple_quota ple_qt13; 702 const struct rtw89_ple_quota ple_qt44; 703 const struct rtw89_ple_quota ple_qt45; 704 const struct rtw89_ple_quota ple_qt46; 705 const struct rtw89_ple_quota ple_qt47; 706 }; 707 708 extern const struct rtw89_mac_size_set rtw89_mac_size; 709 710 static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band) 711 { 712 return band == 0 ? reg_base : (reg_base + 0x2000); 713 } 714 715 static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx) 716 { 717 return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx); 718 } 719 720 static inline u32 721 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 722 u32 base, u32 mask) 723 { 724 u32 reg; 725 726 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 727 return rtw89_read32_mask(rtwdev, reg, mask); 728 } 729 730 static inline void 731 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, 732 u32 data) 733 { 734 u32 reg; 735 736 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 737 rtw89_write32(rtwdev, reg, data); 738 } 739 740 static inline void 741 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 742 u32 base, u32 mask, u32 data) 743 { 744 u32 reg; 745 746 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 747 rtw89_write32_mask(rtwdev, reg, mask, data); 748 } 749 750 static inline void 751 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 752 u32 base, u32 mask, u16 data) 753 { 754 u32 reg; 755 756 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 757 rtw89_write16_mask(rtwdev, reg, mask, data); 758 } 759 760 static inline void 761 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 762 u32 base, u32 bit) 763 { 764 u32 reg; 765 766 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 767 rtw89_write32_clr(rtwdev, reg, bit); 768 } 769 770 static inline void 771 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 772 u32 base, u16 bit) 773 { 774 u32 reg; 775 776 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 777 rtw89_write16_clr(rtwdev, reg, bit); 778 } 779 780 static inline void 781 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 782 u32 base, u32 bit) 783 { 784 u32 reg; 785 786 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 787 rtw89_write32_set(rtwdev, reg, bit); 788 } 789 790 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); 791 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev); 792 int rtw89_mac_init(struct rtw89_dev *rtwdev); 793 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, 794 enum rtw89_mac_hwmod_sel sel); 795 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); 796 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); 797 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 798 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 799 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 800 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); 801 void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); 802 803 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev) 804 { 805 const struct rtw89_chip_info *chip = rtwdev->chip; 806 807 return chip->ops->enable_bb_rf(rtwdev); 808 } 809 810 static inline void rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev) 811 { 812 const struct rtw89_chip_info *chip = rtwdev->chip; 813 814 chip->ops->disable_bb_rf(rtwdev); 815 } 816 817 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); 818 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); 819 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 820 u32 len, u8 class, u8 func); 821 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); 822 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 823 u32 *tx_en, enum rtw89_sch_tx_sel sel); 824 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 825 u32 *tx_en, enum rtw89_sch_tx_sel sel); 826 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 827 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 828 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable); 829 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx); 830 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); 831 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); 832 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 833 const struct rtw89_mac_ax_coex *coex); 834 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 835 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 836 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 837 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 838 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); 839 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band); 840 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); 841 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); 842 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); 843 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); 844 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); 845 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 846 enum rtw89_phy_idx phy_idx, 847 u32 reg_base, u32 *cr); 848 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); 849 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); 850 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 851 struct ieee80211_sta *sta); 852 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 853 struct ieee80211_sta *sta); 854 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 855 struct ieee80211_bss_conf *conf); 856 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 857 struct ieee80211_sta *sta, bool disconnect); 858 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); 859 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 860 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 861 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 862 struct rtw89_vif *rtwvif, bool en); 863 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause); 864 865 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 866 { 867 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) 868 return; 869 870 _rtw89_mac_bf_monitor_track(rtwdev); 871 } 872 873 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, 874 enum rtw89_phy_idx phy_idx, 875 u32 reg_base, u32 *val) 876 { 877 u32 cr; 878 879 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 880 return -EINVAL; 881 882 *val = rtw89_read32(rtwdev, cr); 883 return 0; 884 } 885 886 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, 887 enum rtw89_phy_idx phy_idx, 888 u32 reg_base, u32 val) 889 { 890 u32 cr; 891 892 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 893 return -EINVAL; 894 895 rtw89_write32(rtwdev, cr, val); 896 return 0; 897 } 898 899 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, 900 enum rtw89_phy_idx phy_idx, 901 u32 reg_base, u32 mask, u32 val) 902 { 903 u32 cr; 904 905 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 906 return -EINVAL; 907 908 rtw89_write32_mask(rtwdev, cr, mask, val); 909 return 0; 910 } 911 912 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 913 bool resume, u32 tx_time); 914 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 915 u32 *tx_time); 916 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 917 struct rtw89_sta *rtwsta, 918 bool resume, u8 tx_retry); 919 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 920 struct rtw89_sta *rtwsta, u8 *tx_retry); 921 922 enum rtw89_mac_xtal_si_offset { 923 XTAL0 = 0x0, 924 XTAL3 = 0x3, 925 XTAL_SI_XTAL_SC_XI = 0x04, 926 #define XTAL_SC_XI_MASK GENMASK(7, 0) 927 XTAL_SI_XTAL_SC_XO = 0x05, 928 #define XTAL_SC_XO_MASK GENMASK(7, 0) 929 XTAL_SI_PWR_CUT = 0x10, 930 #define XTAL_SI_SMALL_PWR_CUT BIT(0) 931 #define XTAL_SI_BIG_PWR_CUT BIT(1) 932 XTAL_SI_XTAL_XMD_2 = 0x24, 933 #define XTAL_SI_LDO_LPS GENMASK(6, 4) 934 XTAL_SI_XTAL_XMD_4 = 0x26, 935 #define XTAL_SI_LPS_CAP GENMASK(3, 0) 936 XTAL_SI_CV = 0x41, 937 XTAL_SI_LOW_ADDR = 0x62, 938 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0) 939 XTAL_SI_CTRL = 0x63, 940 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6) 941 #define XTAL_SI_RDY BIT(5) 942 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0) 943 XTAL_SI_READ_VAL = 0x7A, 944 XTAL_SI_WL_RFC_S0 = 0x80, 945 #define XTAL_SI_RF00 BIT(0) 946 XTAL_SI_WL_RFC_S1 = 0x81, 947 #define XTAL_SI_RF10 BIT(0) 948 XTAL_SI_ANAPAR_WL = 0x90, 949 #define XTAL_SI_SRAM2RFC BIT(7) 950 #define XTAL_SI_GND_SHDN_WL BIT(6) 951 #define XTAL_SI_SHDN_WL BIT(5) 952 #define XTAL_SI_RFC2RF BIT(4) 953 #define XTAL_SI_OFF_EI BIT(3) 954 #define XTAL_SI_OFF_WEI BIT(2) 955 #define XTAL_SI_PON_EI BIT(1) 956 #define XTAL_SI_PON_WEI BIT(0) 957 XTAL_SI_SRAM_CTRL = 0xA1, 958 #define FULL_BIT_MASK GENMASK(7, 0) 959 }; 960 961 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); 962 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val); 963 964 #endif 965