1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_MAC_H__ 6 #define __RTW89_MAC_H__ 7 8 #include "core.h" 9 #include "reg.h" 10 11 #define MAC_MEM_DUMP_PAGE_SIZE_AX 0x40000 12 #define MAC_MEM_DUMP_PAGE_SIZE_BE 0x80000 13 14 #define ADDR_CAM_ENT_SIZE 0x40 15 #define ADDR_CAM_ENT_SHORT_SIZE 0x20 16 #define BSSID_CAM_ENT_SIZE 0x08 17 #define HFC_PAGE_UNIT 64 18 #define RPWM_TRY_CNT 3 19 20 enum rtw89_mac_hwmod_sel { 21 RTW89_DMAC_SEL = 0, 22 RTW89_CMAC_SEL = 1, 23 24 RTW89_MAC_INVALID, 25 }; 26 27 enum rtw89_mac_fwd_target { 28 RTW89_FWD_DONT_CARE = 0, 29 RTW89_FWD_TO_HOST = 1, 30 RTW89_FWD_TO_WLAN_CPU = 2 31 }; 32 33 enum rtw89_mac_wd_dma_intvl { 34 RTW89_MAC_WD_DMA_INTVL_0S, 35 RTW89_MAC_WD_DMA_INTVL_256NS, 36 RTW89_MAC_WD_DMA_INTVL_512NS, 37 RTW89_MAC_WD_DMA_INTVL_768NS, 38 RTW89_MAC_WD_DMA_INTVL_1US, 39 RTW89_MAC_WD_DMA_INTVL_1_5US, 40 RTW89_MAC_WD_DMA_INTVL_2US, 41 RTW89_MAC_WD_DMA_INTVL_4US, 42 RTW89_MAC_WD_DMA_INTVL_8US, 43 RTW89_MAC_WD_DMA_INTVL_16US, 44 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE 45 }; 46 47 enum rtw89_mac_multi_tag_num { 48 RTW89_MAC_TAG_NUM_1, 49 RTW89_MAC_TAG_NUM_2, 50 RTW89_MAC_TAG_NUM_3, 51 RTW89_MAC_TAG_NUM_4, 52 RTW89_MAC_TAG_NUM_5, 53 RTW89_MAC_TAG_NUM_6, 54 RTW89_MAC_TAG_NUM_7, 55 RTW89_MAC_TAG_NUM_8, 56 RTW89_MAC_TAG_NUM_DEF = 0xFE 57 }; 58 59 enum rtw89_mac_lbc_tmr { 60 RTW89_MAC_LBC_TMR_8US = 0, 61 RTW89_MAC_LBC_TMR_16US, 62 RTW89_MAC_LBC_TMR_32US, 63 RTW89_MAC_LBC_TMR_64US, 64 RTW89_MAC_LBC_TMR_128US, 65 RTW89_MAC_LBC_TMR_256US, 66 RTW89_MAC_LBC_TMR_512US, 67 RTW89_MAC_LBC_TMR_1MS, 68 RTW89_MAC_LBC_TMR_2MS, 69 RTW89_MAC_LBC_TMR_4MS, 70 RTW89_MAC_LBC_TMR_8MS, 71 RTW89_MAC_LBC_TMR_DEF = 0xFE 72 }; 73 74 enum rtw89_mac_cpuio_op_cmd_type { 75 CPUIO_OP_CMD_GET_1ST_PID = 0, 76 CPUIO_OP_CMD_GET_NEXT_PID = 1, 77 CPUIO_OP_CMD_ENQ_TO_TAIL = 4, 78 CPUIO_OP_CMD_ENQ_TO_HEAD = 5, 79 CPUIO_OP_CMD_DEQ = 8, 80 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, 81 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 82 }; 83 84 enum rtw89_mac_wde_dle_port_id { 85 WDE_DLE_PORT_ID_DISPATCH = 0, 86 WDE_DLE_PORT_ID_PKTIN = 1, 87 WDE_DLE_PORT_ID_CMAC0 = 3, 88 WDE_DLE_PORT_ID_CMAC1 = 4, 89 WDE_DLE_PORT_ID_CPU_IO = 6, 90 WDE_DLE_PORT_ID_WDRLS = 7, 91 WDE_DLE_PORT_ID_END = 8 92 }; 93 94 enum rtw89_mac_wde_dle_queid_wdrls { 95 WDE_DLE_QUEID_TXOK = 0, 96 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, 97 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, 98 WDE_DLE_QUEID_DROP_MACID_DROP = 3, 99 WDE_DLE_QUEID_NO_REPORT = 4 100 }; 101 102 enum rtw89_mac_ple_dle_port_id { 103 PLE_DLE_PORT_ID_DISPATCH = 0, 104 PLE_DLE_PORT_ID_MPDU = 1, 105 PLE_DLE_PORT_ID_SEC = 2, 106 PLE_DLE_PORT_ID_CMAC0 = 3, 107 PLE_DLE_PORT_ID_CMAC1 = 4, 108 PLE_DLE_PORT_ID_WDRLS = 5, 109 PLE_DLE_PORT_ID_CPU_IO = 6, 110 PLE_DLE_PORT_ID_PLRLS = 7, 111 PLE_DLE_PORT_ID_END = 8 112 }; 113 114 enum rtw89_mac_ple_dle_queid_plrls { 115 PLE_DLE_QUEID_NO_REPORT = 0x0 116 }; 117 118 enum rtw89_machdr_frame_type { 119 RTW89_MGNT = 0, 120 RTW89_CTRL = 1, 121 RTW89_DATA = 2, 122 }; 123 124 enum rtw89_mac_dle_dfi_type { 125 DLE_DFI_TYPE_FREEPG = 0, 126 DLE_DFI_TYPE_QUOTA = 1, 127 DLE_DFI_TYPE_PAGELLT = 2, 128 DLE_DFI_TYPE_PKTINFO = 3, 129 DLE_DFI_TYPE_PREPKTLLT = 4, 130 DLE_DFI_TYPE_NXTPKTLLT = 5, 131 DLE_DFI_TYPE_QLNKTBL = 6, 132 DLE_DFI_TYPE_QEMPTY = 7, 133 }; 134 135 enum rtw89_mac_dle_wde_quota_id { 136 WDE_QTAID_HOST_IF = 0, 137 WDE_QTAID_WLAN_CPU = 1, 138 WDE_QTAID_DATA_CPU = 2, 139 WDE_QTAID_PKTIN = 3, 140 WDE_QTAID_CPUIO = 4, 141 }; 142 143 enum rtw89_mac_dle_ple_quota_id { 144 PLE_QTAID_B0_TXPL = 0, 145 PLE_QTAID_B1_TXPL = 1, 146 PLE_QTAID_C2H = 2, 147 PLE_QTAID_H2C = 3, 148 PLE_QTAID_WLAN_CPU = 4, 149 PLE_QTAID_MPDU = 5, 150 PLE_QTAID_CMAC0_RX = 6, 151 PLE_QTAID_CMAC1_RX = 7, 152 PLE_QTAID_CMAC1_BBRPT = 8, 153 PLE_QTAID_WDRLS = 9, 154 PLE_QTAID_CPUIO = 10, 155 }; 156 157 enum rtw89_mac_dle_ctrl_type { 158 DLE_CTRL_TYPE_WDE = 0, 159 DLE_CTRL_TYPE_PLE = 1, 160 DLE_CTRL_TYPE_NUM = 2, 161 }; 162 163 enum rtw89_mac_ax_l0_to_l1_event { 164 MAC_AX_L0_TO_L1_CHIF_IDLE = 0, 165 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, 166 MAC_AX_L0_TO_L1_RLS_PKID = 2, 167 MAC_AX_L0_TO_L1_PTCL_IDLE = 3, 168 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, 169 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, 170 MAC_AX_L0_TO_L1_PCIE_STUCK = 6, 171 MAC_AX_L0_TO_L1_EVENT_MAX = 15, 172 }; 173 174 enum rtw89_mac_phy_rpt_size { 175 MAC_AX_PHY_RPT_SIZE_0 = 0, 176 MAC_AX_PHY_RPT_SIZE_8 = 1, 177 MAC_AX_PHY_RPT_SIZE_16 = 2, 178 MAC_AX_PHY_RPT_SIZE_24 = 3, 179 }; 180 181 enum rtw89_mac_hdr_cnv_size { 182 MAC_AX_HDR_CNV_SIZE_0 = 0, 183 MAC_AX_HDR_CNV_SIZE_32 = 1, 184 MAC_AX_HDR_CNV_SIZE_64 = 2, 185 MAC_AX_HDR_CNV_SIZE_96 = 3, 186 }; 187 188 enum rtw89_mac_wow_fw_status { 189 WOWLAN_NOT_READY = 0x00, 190 WOWLAN_SLEEP_READY = 0x01, 191 WOWLAN_RESUME_READY = 0x02, 192 }; 193 194 #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32) 195 196 enum rtw89_mac_dbg_port_sel { 197 /* CMAC 0 related */ 198 RTW89_DBG_PORT_SEL_PTCL_C0 = 0, 199 RTW89_DBG_PORT_SEL_SCH_C0, 200 RTW89_DBG_PORT_SEL_TMAC_C0, 201 RTW89_DBG_PORT_SEL_RMAC_C0, 202 RTW89_DBG_PORT_SEL_RMACST_C0, 203 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, 204 RTW89_DBG_PORT_SEL_TRXPTCL_C0, 205 RTW89_DBG_PORT_SEL_TX_INFOL_C0, 206 RTW89_DBG_PORT_SEL_TX_INFOH_C0, 207 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, 208 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, 209 /* CMAC 1 related */ 210 RTW89_DBG_PORT_SEL_PTCL_C1, 211 RTW89_DBG_PORT_SEL_SCH_C1, 212 RTW89_DBG_PORT_SEL_TMAC_C1, 213 RTW89_DBG_PORT_SEL_RMAC_C1, 214 RTW89_DBG_PORT_SEL_RMACST_C1, 215 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, 216 RTW89_DBG_PORT_SEL_TRXPTCL_C1, 217 RTW89_DBG_PORT_SEL_TX_INFOL_C1, 218 RTW89_DBG_PORT_SEL_TX_INFOH_C1, 219 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, 220 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, 221 /* DLE related */ 222 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, 223 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, 224 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, 225 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, 226 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, 227 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, 228 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, 229 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, 230 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, 231 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, 232 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, 233 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, 234 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, 235 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, 236 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, 237 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, 238 RTW89_DBG_PORT_SEL_PKTINFO, 239 /* DISPATCHER related */ 240 RTW89_DBG_PORT_SEL_DSPT_HDT_TX0, 241 RTW89_DBG_PORT_SEL_DSPT_HDT_TX1, 242 RTW89_DBG_PORT_SEL_DSPT_HDT_TX2, 243 RTW89_DBG_PORT_SEL_DSPT_HDT_TX3, 244 RTW89_DBG_PORT_SEL_DSPT_HDT_TX4, 245 RTW89_DBG_PORT_SEL_DSPT_HDT_TX5, 246 RTW89_DBG_PORT_SEL_DSPT_HDT_TX6, 247 RTW89_DBG_PORT_SEL_DSPT_HDT_TX7, 248 RTW89_DBG_PORT_SEL_DSPT_HDT_TX8, 249 RTW89_DBG_PORT_SEL_DSPT_HDT_TX9, 250 RTW89_DBG_PORT_SEL_DSPT_HDT_TXA, 251 RTW89_DBG_PORT_SEL_DSPT_HDT_TXB, 252 RTW89_DBG_PORT_SEL_DSPT_HDT_TXC, 253 RTW89_DBG_PORT_SEL_DSPT_HDT_TXD, 254 RTW89_DBG_PORT_SEL_DSPT_HDT_TXE, 255 RTW89_DBG_PORT_SEL_DSPT_HDT_TXF, 256 RTW89_DBG_PORT_SEL_DSPT_CDT_TX0, 257 RTW89_DBG_PORT_SEL_DSPT_CDT_TX1, 258 RTW89_DBG_PORT_SEL_DSPT_CDT_TX3, 259 RTW89_DBG_PORT_SEL_DSPT_CDT_TX4, 260 RTW89_DBG_PORT_SEL_DSPT_CDT_TX5, 261 RTW89_DBG_PORT_SEL_DSPT_CDT_TX6, 262 RTW89_DBG_PORT_SEL_DSPT_CDT_TX7, 263 RTW89_DBG_PORT_SEL_DSPT_CDT_TX8, 264 RTW89_DBG_PORT_SEL_DSPT_CDT_TX9, 265 RTW89_DBG_PORT_SEL_DSPT_CDT_TXA, 266 RTW89_DBG_PORT_SEL_DSPT_CDT_TXB, 267 RTW89_DBG_PORT_SEL_DSPT_CDT_TXC, 268 RTW89_DBG_PORT_SEL_DSPT_HDT_RX0, 269 RTW89_DBG_PORT_SEL_DSPT_HDT_RX1, 270 RTW89_DBG_PORT_SEL_DSPT_HDT_RX2, 271 RTW89_DBG_PORT_SEL_DSPT_HDT_RX3, 272 RTW89_DBG_PORT_SEL_DSPT_HDT_RX4, 273 RTW89_DBG_PORT_SEL_DSPT_HDT_RX5, 274 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0, 275 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0, 276 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1, 277 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2, 278 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1, 279 RTW89_DBG_PORT_SEL_DSPT_STF_CTRL, 280 RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL, 281 RTW89_DBG_PORT_SEL_DSPT_WDE_INTF, 282 RTW89_DBG_PORT_SEL_DSPT_PLE_INTF, 283 RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL, 284 /* PCIE related */ 285 RTW89_DBG_PORT_SEL_PCIE_TXDMA, 286 RTW89_DBG_PORT_SEL_PCIE_RXDMA, 287 RTW89_DBG_PORT_SEL_PCIE_CVT, 288 RTW89_DBG_PORT_SEL_PCIE_CXPL, 289 RTW89_DBG_PORT_SEL_PCIE_IO, 290 RTW89_DBG_PORT_SEL_PCIE_MISC, 291 RTW89_DBG_PORT_SEL_PCIE_MISC2, 292 293 /* keep last */ 294 RTW89_DBG_PORT_SEL_LAST, 295 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, 296 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, 297 }; 298 299 /* SRAM mem dump */ 300 #define R_AX_INDIR_ACCESS_ENTRY 0x40000 301 #define R_BE_INDIR_ACCESS_ENTRY 0x80000 302 303 #define AXIDMA_BASE_ADDR 0x18006000 304 #define STA_SCHED_BASE_ADDR 0x18808000 305 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 306 #define SECURITY_CAM_BASE_ADDR 0x18814000 307 #define WOW_CAM_BASE_ADDR 0x18815000 308 #define CMAC_TBL_BASE_ADDR 0x18840000 309 #define ADDR_CAM_BASE_ADDR 0x18850000 310 #define BSSID_CAM_BASE_ADDR 0x18853000 311 #define BA_CAM_BASE_ADDR 0x18854000 312 #define BCN_IE_CAM0_BASE_ADDR 0x18855000 313 #define SHARED_BUF_BASE_ADDR 0x18700000 314 #define DMAC_TBL_BASE_ADDR 0x18800000 315 #define SHCUT_MACHDR_BASE_ADDR 0x18800800 316 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000 317 #define TXD_FIFO_0_BASE_ADDR 0x18856200 318 #define TXD_FIFO_1_BASE_ADDR 0x188A1080 319 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */ 320 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */ 321 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000 322 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 323 #define CPU_LOCAL_BASE_ADDR 0x18003000 324 325 #define WD_PAGE_BASE_ADDR_BE 0x0 326 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000 327 #define AXIDMA_BASE_ADDR_BE 0x18006000 328 #define SHARED_BUF_BASE_ADDR_BE 0x18700000 329 #define DMAC_TBL_BASE_ADDR_BE 0x18800000 330 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800 331 #define STA_SCHED_BASE_ADDR_BE 0x18818000 332 #define NAT25_CAM_BASE_ADDR_BE 0x18820000 333 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000 334 #define SEC_CAM_BASE_ADDR_BE 0x18824000 335 #define WOW_CAM_BASE_ADDR_BE 0x18828000 336 #define MLD_TBL_BASE_ADDR_BE 0x18829000 337 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000 338 #define CMAC_TBL_BASE_ADDR_BE 0x18840000 339 #define ADDR_CAM_BASE_ADDR_BE 0x18850000 340 #define BSSID_CAM_BASE_ADDR_BE 0x18858000 341 #define BA_CAM_BASE_ADDR_BE 0x18859000 342 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000 343 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000 344 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000 345 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000 346 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000 347 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800 348 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000 349 350 #define CCTL_INFO_SIZE 32 351 352 enum rtw89_mac_mem_sel { 353 RTW89_MAC_MEM_AXIDMA, 354 RTW89_MAC_MEM_SHARED_BUF, 355 RTW89_MAC_MEM_DMAC_TBL, 356 RTW89_MAC_MEM_SHCUT_MACHDR, 357 RTW89_MAC_MEM_STA_SCHED, 358 RTW89_MAC_MEM_RXPLD_FLTR_CAM, 359 RTW89_MAC_MEM_SECURITY_CAM, 360 RTW89_MAC_MEM_WOW_CAM, 361 RTW89_MAC_MEM_CMAC_TBL, 362 RTW89_MAC_MEM_ADDR_CAM, 363 RTW89_MAC_MEM_BA_CAM, 364 RTW89_MAC_MEM_BCN_IE_CAM0, 365 RTW89_MAC_MEM_BCN_IE_CAM1, 366 RTW89_MAC_MEM_TXD_FIFO_0, 367 RTW89_MAC_MEM_TXD_FIFO_1, 368 RTW89_MAC_MEM_TXDATA_FIFO_0, 369 RTW89_MAC_MEM_TXDATA_FIFO_1, 370 RTW89_MAC_MEM_CPU_LOCAL, 371 RTW89_MAC_MEM_BSSID_CAM, 372 RTW89_MAC_MEM_TXD_FIFO_0_V1, 373 RTW89_MAC_MEM_TXD_FIFO_1_V1, 374 RTW89_MAC_MEM_WD_PAGE, 375 RTW89_MAC_MEM_MLD_TBL, 376 377 /* keep last */ 378 RTW89_MAC_MEM_NUM, 379 }; 380 381 enum rtw89_rpwm_req_pwr_state { 382 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, 383 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, 384 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, 385 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, 386 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, 387 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, 388 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, 389 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, 390 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, 391 }; 392 393 struct rtw89_pwr_cfg { 394 u16 addr; 395 u8 cv_msk; 396 u8 intf_msk; 397 u8 base:4; 398 u8 cmd:4; 399 u8 msk; 400 u8 val; 401 }; 402 403 enum rtw89_mac_c2h_ofld_func { 404 RTW89_MAC_C2H_FUNC_EFUSE_DUMP, 405 RTW89_MAC_C2H_FUNC_READ_RSP, 406 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, 407 RTW89_MAC_C2H_FUNC_BCN_RESEND, 408 RTW89_MAC_C2H_FUNC_MACID_PAUSE, 409 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6, 410 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9, 411 RTW89_MAC_C2H_FUNC_TX_DUTY_RPT = 0xa, 412 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd, 413 RTW89_MAC_C2H_FUNC_OFLD_MAX, 414 }; 415 416 enum rtw89_mac_c2h_info_func { 417 RTW89_MAC_C2H_FUNC_REC_ACK, 418 RTW89_MAC_C2H_FUNC_DONE_ACK, 419 RTW89_MAC_C2H_FUNC_C2H_LOG, 420 RTW89_MAC_C2H_FUNC_BCN_CNT, 421 RTW89_MAC_C2H_FUNC_INFO_MAX, 422 }; 423 424 enum rtw89_mac_c2h_mcc_func { 425 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0, 426 RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1, 427 RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2, 428 RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3, 429 430 NUM_OF_RTW89_MAC_C2H_FUNC_MCC, 431 }; 432 433 enum rtw89_mac_c2h_mlo_func { 434 RTW89_MAC_C2H_FUNC_MLO_GET_TBL = 0x0, 435 RTW89_MAC_C2H_FUNC_MLO_EMLSR_TRANS_DONE = 0x1, 436 RTW89_MAC_C2H_FUNC_MLO_EMLSR_STA_CFG_DONE = 0x2, 437 RTW89_MAC_C2H_FUNC_MCMLO_RELINK_RPT = 0x3, 438 RTW89_MAC_C2H_FUNC_MCMLO_SN_SYNC_RPT = 0x4, 439 RTW89_MAC_C2H_FUNC_MLO_LINK_CFG_STAT = 0x5, 440 RTW89_MAC_C2H_FUNC_MLO_DM_DBG_DUMP = 0x6, 441 442 NUM_OF_RTW89_MAC_C2H_FUNC_MLO, 443 }; 444 445 enum rtw89_mac_c2h_mrc_func { 446 RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0, 447 RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT = 1, 448 449 NUM_OF_RTW89_MAC_C2H_FUNC_MRC, 450 }; 451 452 enum rtw89_mac_c2h_wow_func { 453 RTW89_MAC_C2H_FUNC_AOAC_REPORT, 454 455 NUM_OF_RTW89_MAC_C2H_FUNC_WOW, 456 }; 457 458 enum rtw89_mac_c2h_ap_func { 459 RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY = 0, 460 461 NUM_OF_RTW89_MAC_C2H_FUNC_AP, 462 }; 463 464 enum rtw89_mac_c2h_class { 465 RTW89_MAC_C2H_CLASS_INFO = 0x0, 466 RTW89_MAC_C2H_CLASS_OFLD = 0x1, 467 RTW89_MAC_C2H_CLASS_TWT = 0x2, 468 RTW89_MAC_C2H_CLASS_WOW = 0x3, 469 RTW89_MAC_C2H_CLASS_MCC = 0x4, 470 RTW89_MAC_C2H_CLASS_FWDBG = 0x5, 471 RTW89_MAC_C2H_CLASS_MLO = 0xc, 472 RTW89_MAC_C2H_CLASS_MRC = 0xe, 473 RTW89_MAC_C2H_CLASS_AP = 0x18, 474 RTW89_MAC_C2H_CLASS_ROLE = 0x1b, 475 RTW89_MAC_C2H_CLASS_MAX, 476 }; 477 478 enum rtw89_mac_mcc_status { 479 RTW89_MAC_MCC_ADD_ROLE_OK = 0, 480 RTW89_MAC_MCC_START_GROUP_OK = 1, 481 RTW89_MAC_MCC_STOP_GROUP_OK = 2, 482 RTW89_MAC_MCC_DEL_GROUP_OK = 3, 483 RTW89_MAC_MCC_RESET_GROUP_OK = 4, 484 RTW89_MAC_MCC_SWITCH_CH_OK = 5, 485 RTW89_MAC_MCC_TXNULL0_OK = 6, 486 RTW89_MAC_MCC_TXNULL1_OK = 7, 487 488 RTW89_MAC_MCC_SWITCH_EARLY = 10, 489 RTW89_MAC_MCC_TBTT = 11, 490 RTW89_MAC_MCC_DURATION_START = 12, 491 RTW89_MAC_MCC_DURATION_END = 13, 492 493 RTW89_MAC_MCC_ADD_ROLE_FAIL = 20, 494 RTW89_MAC_MCC_START_GROUP_FAIL = 21, 495 RTW89_MAC_MCC_STOP_GROUP_FAIL = 22, 496 RTW89_MAC_MCC_DEL_GROUP_FAIL = 23, 497 RTW89_MAC_MCC_RESET_GROUP_FAIL = 24, 498 RTW89_MAC_MCC_SWITCH_CH_FAIL = 25, 499 RTW89_MAC_MCC_TXNULL0_FAIL = 26, 500 RTW89_MAC_MCC_TXNULL1_FAIL = 27, 501 }; 502 503 enum rtw89_mac_mrc_status { 504 RTW89_MAC_MRC_START_SCH_OK = 0, 505 RTW89_MAC_MRC_STOP_SCH_OK = 1, 506 RTW89_MAC_MRC_DEL_SCH_OK = 2, 507 RTW89_MAC_MRC_EMPTY_SCH_FAIL = 16, 508 RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL = 17, 509 RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL = 18, 510 RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL = 19, 511 RTW89_MAC_MRC_ALT_ROLE_FAIL = 20, 512 RTW89_MAC_MRC_ADD_PSTIMER_FAIL = 21, 513 RTW89_MAC_MRC_MALLOC_FAIL = 22, 514 RTW89_MAC_MRC_SWITCH_CH_FAIL = 23, 515 RTW89_MAC_MRC_TXNULL0_FAIL = 24, 516 RTW89_MAC_MRC_PORT_FUNC_EN_FAIL = 25, 517 }; 518 519 struct rtw89_mac_ax_coex { 520 #define RTW89_MAC_AX_COEX_RTK_MODE 0 521 #define RTW89_MAC_AX_COEX_CSR_MODE 1 522 u8 pta_mode; 523 #define RTW89_MAC_AX_COEX_INNER 0 524 #define RTW89_MAC_AX_COEX_OUTPUT 1 525 #define RTW89_MAC_AX_COEX_INPUT 2 526 u8 direction; 527 }; 528 529 struct rtw89_mac_ax_plt { 530 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0) 531 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) 532 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) 533 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3) 534 u8 band; 535 u8 tx; 536 u8 rx; 537 }; 538 539 enum rtw89_mac_bf_rrsc_rate { 540 RTW89_MAC_BF_RRSC_6M = 0, 541 RTW89_MAC_BF_RRSC_9M = 1, 542 RTW89_MAC_BF_RRSC_12M, 543 RTW89_MAC_BF_RRSC_18M, 544 RTW89_MAC_BF_RRSC_24M, 545 RTW89_MAC_BF_RRSC_36M, 546 RTW89_MAC_BF_RRSC_48M, 547 RTW89_MAC_BF_RRSC_54M, 548 RTW89_MAC_BF_RRSC_HT_MSC0, 549 RTW89_MAC_BF_RRSC_HT_MSC1, 550 RTW89_MAC_BF_RRSC_HT_MSC2, 551 RTW89_MAC_BF_RRSC_HT_MSC3, 552 RTW89_MAC_BF_RRSC_HT_MSC4, 553 RTW89_MAC_BF_RRSC_HT_MSC5, 554 RTW89_MAC_BF_RRSC_HT_MSC6, 555 RTW89_MAC_BF_RRSC_HT_MSC7, 556 RTW89_MAC_BF_RRSC_VHT_MSC0, 557 RTW89_MAC_BF_RRSC_VHT_MSC1, 558 RTW89_MAC_BF_RRSC_VHT_MSC2, 559 RTW89_MAC_BF_RRSC_VHT_MSC3, 560 RTW89_MAC_BF_RRSC_VHT_MSC4, 561 RTW89_MAC_BF_RRSC_VHT_MSC5, 562 RTW89_MAC_BF_RRSC_VHT_MSC6, 563 RTW89_MAC_BF_RRSC_VHT_MSC7, 564 RTW89_MAC_BF_RRSC_HE_MSC0, 565 RTW89_MAC_BF_RRSC_HE_MSC1, 566 RTW89_MAC_BF_RRSC_HE_MSC2, 567 RTW89_MAC_BF_RRSC_HE_MSC3, 568 RTW89_MAC_BF_RRSC_HE_MSC4, 569 RTW89_MAC_BF_RRSC_HE_MSC5, 570 RTW89_MAC_BF_RRSC_HE_MSC6, 571 RTW89_MAC_BF_RRSC_HE_MSC7 = 31, 572 RTW89_MAC_BF_RRSC_MAX = 32 573 }; 574 575 #define RTW89_R32_EA 0xEAEAEAEA 576 #define RTW89_R32_DEAD 0xDEADBEEF 577 #define MAC_REG_POOL_COUNT 10 578 #define ACCESS_CMAC(_addr) \ 579 ({typeof(_addr) __addr = (_addr); \ 580 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) 581 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000 582 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000 583 584 #define PTCL_IDLE_POLL_CNT 10000 585 #define SW_CVR_DUR_US 8 586 #define SW_CVR_CNT 8 587 588 #define DLE_BOUND_UNIT (8 * 1024) 589 #define DLE_WAIT_CNT 2000 590 #define TRXCFG_WAIT_CNT 2000 591 592 #define RTW89_WDE_PG_64 64 593 #define RTW89_WDE_PG_128 128 594 #define RTW89_WDE_PG_256 256 595 596 #define S_AX_WDE_PAGE_SEL_64 0 597 #define S_AX_WDE_PAGE_SEL_128 1 598 #define S_AX_WDE_PAGE_SEL_256 2 599 600 #define RTW89_PLE_PG_64 64 601 #define RTW89_PLE_PG_128 128 602 #define RTW89_PLE_PG_256 256 603 604 #define S_AX_PLE_PAGE_SEL_64 0 605 #define S_AX_PLE_PAGE_SEL_128 1 606 #define S_AX_PLE_PAGE_SEL_256 2 607 608 #define B_CMAC0_MGQ_NORMAL BIT(2) 609 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3) 610 #define B_CMAC0_CPUMGQ BIT(4) 611 #define B_CMAC1_MGQ_NORMAL BIT(10) 612 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11) 613 #define B_CMAC1_CPUMGQ BIT(12) 614 615 #define B_CMAC0_MGQ_NORMAL_BE BIT(2) 616 #define B_CMAC1_MGQ_NORMAL_BE BIT(30) 617 618 #define QEMP_ACQ_GRP_MACID_NUM 8 619 #define QEMP_ACQ_GRP_QSEL_SH 4 620 #define QEMP_ACQ_GRP_QSEL_MASK 0xF 621 622 #define SDIO_LOCAL_BASE_ADDR 0x80000000 623 624 #define PWR_CMD_WRITE 0 625 #define PWR_CMD_POLL 1 626 #define PWR_CMD_DELAY 2 627 #define PWR_CMD_END 3 628 629 #define PWR_INTF_MSK_SDIO BIT(0) 630 #define PWR_INTF_MSK_USB BIT(1) 631 #define PWR_INTF_MSK_PCIE BIT(2) 632 #define PWR_INTF_MSK_ALL 0x7 633 634 #define PWR_BASE_MAC 0 635 #define PWR_BASE_USB 1 636 #define PWR_BASE_PCIE 2 637 #define PWR_BASE_SDIO 3 638 639 #define PWR_CV_MSK_A BIT(0) 640 #define PWR_CV_MSK_B BIT(1) 641 #define PWR_CV_MSK_C BIT(2) 642 #define PWR_CV_MSK_D BIT(3) 643 #define PWR_CV_MSK_E BIT(4) 644 #define PWR_CV_MSK_F BIT(5) 645 #define PWR_CV_MSK_G BIT(6) 646 #define PWR_CV_MSK_TEST BIT(7) 647 #define PWR_CV_MSK_ALL 0xFF 648 649 #define PWR_DELAY_US 0 650 #define PWR_DELAY_MS 1 651 652 /* STA scheduler */ 653 #define SS_MACID_SH 8 654 #define SS_TX_LEN_MSK 0x1FFFFF 655 #define SS_CTRL1_R_TX_LEN 5 656 #define SS_CTRL1_R_NEXT_LINK 20 657 #define SS_LINK_SIZE 256 658 659 /* MAC debug port */ 660 #define TMAC_DBG_SEL_C0 0xA5 661 #define RMAC_DBG_SEL_C0 0xA6 662 #define TRXPTCL_DBG_SEL_C0 0xA7 663 #define TMAC_DBG_SEL_C1 0xB5 664 #define RMAC_DBG_SEL_C1 0xB6 665 #define TRXPTCL_DBG_SEL_C1 0xB7 666 #define FW_PROG_CNTR_DBG_SEL 0xF2 667 #define PCIE_TXDMA_DBG_SEL 0x30 668 #define PCIE_RXDMA_DBG_SEL 0x31 669 #define PCIE_CVT_DBG_SEL 0x32 670 #define PCIE_CXPL_DBG_SEL 0x33 671 #define PCIE_IO_DBG_SEL 0x37 672 #define PCIE_MISC_DBG_SEL 0x38 673 #define PCIE_MISC2_DBG_SEL 0x00 674 #define MAC_DBG_SEL 1 675 #define RMAC_CMAC_DBG_SEL 1 676 677 /* TRXPTCL dbg port sel */ 678 #define TRXPTRL_DBG_SEL_TMAC 0 679 #define TRXPTRL_DBG_SEL_RMAC 1 680 681 struct rtw89_cpuio_ctrl { 682 u16 pkt_num; 683 u16 start_pktid; 684 u16 end_pktid; 685 u8 cmd_type; 686 u8 macid; 687 u8 src_pid; 688 u8 src_qid; 689 u8 dst_pid; 690 u8 dst_qid; 691 u16 pktid; 692 }; 693 694 struct rtw89_mac_dbg_port_info { 695 u32 sel_addr; 696 u8 sel_byte; 697 u32 sel_msk; 698 u32 srt; 699 u32 end; 700 u32 rd_addr; 701 u8 rd_byte; 702 u32 rd_msk; 703 }; 704 705 #define QLNKTBL_ADDR_INFO_SEL BIT(0) 706 #define QLNKTBL_ADDR_INFO_SEL_0 0 707 #define QLNKTBL_ADDR_INFO_SEL_1 1 708 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) 709 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) 710 711 struct rtw89_mac_dle_dfi_ctrl { 712 enum rtw89_mac_dle_ctrl_type type; 713 u32 target; 714 u32 addr; 715 u32 out_data; 716 }; 717 718 struct rtw89_mac_dle_dfi_quota { 719 enum rtw89_mac_dle_ctrl_type dle_type; 720 u32 qtaid; 721 u16 rsv_pgnum; 722 u16 use_pgnum; 723 }; 724 725 struct rtw89_mac_dle_dfi_qempty { 726 enum rtw89_mac_dle_ctrl_type dle_type; 727 u32 grpsel; 728 u32 qempty; 729 }; 730 731 enum rtw89_mac_dle_rsvd_qt_type { 732 DLE_RSVD_QT_MPDU_INFO, 733 DLE_RSVD_QT_B0_CSI, 734 DLE_RSVD_QT_B1_CSI, 735 DLE_RSVD_QT_B0_LMR, 736 DLE_RSVD_QT_B1_LMR, 737 DLE_RSVD_QT_B0_FTM, 738 DLE_RSVD_QT_B1_FTM, 739 }; 740 741 struct rtw89_mac_dle_rsvd_qt_cfg { 742 u16 pktid; 743 u16 pg_num; 744 u32 size; 745 }; 746 747 enum rtw89_mac_error_scenario { 748 RTW89_RXI300_ERROR = 1, 749 RTW89_WCPU_CPU_EXCEPTION = 2, 750 RTW89_WCPU_ASSERTION = 3, 751 }; 752 753 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28) 754 755 /* Define DBG and recovery enum */ 756 enum mac_ax_err_info { 757 /* Get error info */ 758 759 /* L0 */ 760 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, 761 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, 762 MAC_AX_ERR_L0_RESET_DONE = 0x0003, 763 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, 764 765 /* L1 */ 766 MAC_AX_ERR_L1_PREERR_DMAC = 0x999, 767 MAC_AX_ERR_L1_ERR_DMAC = 0x1000, 768 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, 769 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, 770 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, 771 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, 772 773 /* L2 */ 774 /* address hole (master) */ 775 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, 776 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, 777 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, 778 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, 779 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, 780 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, 781 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, 782 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, 783 784 /* AHB bridge timeout (master) */ 785 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, 786 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, 787 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, 788 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, 789 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, 790 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, 791 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, 792 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, 793 794 /* APB_SA bridge timeout (master + slave) */ 795 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, 796 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, 797 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, 798 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, 799 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, 800 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, 801 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, 802 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, 803 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, 804 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, 805 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, 806 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, 807 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, 808 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, 809 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, 810 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, 811 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, 812 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, 813 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, 814 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, 815 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, 816 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, 817 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, 818 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, 819 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, 820 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, 821 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, 822 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, 823 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, 824 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, 825 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, 826 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, 827 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, 828 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, 829 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, 830 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, 831 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, 832 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, 833 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, 834 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, 835 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, 836 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, 837 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, 838 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, 839 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, 840 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, 841 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, 842 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, 843 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, 844 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, 845 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, 846 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, 847 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, 848 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, 849 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, 850 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, 851 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, 852 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, 853 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, 854 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, 855 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, 856 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, 857 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, 858 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, 859 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, 860 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, 861 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, 862 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, 863 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, 864 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, 865 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, 866 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, 867 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, 868 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, 869 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, 870 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, 871 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, 872 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, 873 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, 874 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, 875 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, 876 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, 877 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, 878 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, 879 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, 880 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, 881 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, 882 883 /* APB_BBRF bridge timeout (master) */ 884 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, 885 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, 886 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, 887 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, 888 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, 889 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, 890 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, 891 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, 892 MAC_AX_ERR_L2_RESET_DONE = 0x2400, 893 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599, 894 MAC_AX_ERR_CPU_EXCEPTION = 0x3000, 895 MAC_AX_ERR_ASSERTION = 0x4000, 896 MAC_AX_ERR_RXI300 = 0x5000, 897 MAC_AX_GET_ERR_MAX, 898 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, 899 900 /* set error info */ 901 MAC_AX_ERR_L1_DISABLE_EN = 0x0001, 902 MAC_AX_ERR_L1_RCVY_EN = 0x0002, 903 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, 904 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, 905 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A, 906 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, 907 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, 908 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, 909 MAC_AX_ERR_L0_RCVY_EN = 0x0013, 910 MAC_AX_SET_ERR_MAX, 911 }; 912 913 struct rtw89_mac_size_set { 914 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie; 915 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0; 916 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2; 917 const struct rtw89_dle_size wde_size0; 918 const struct rtw89_dle_size wde_size0_v1; 919 const struct rtw89_dle_size wde_size4; 920 const struct rtw89_dle_size wde_size4_v1; 921 const struct rtw89_dle_size wde_size6; 922 const struct rtw89_dle_size wde_size7; 923 const struct rtw89_dle_size wde_size9; 924 const struct rtw89_dle_size wde_size18; 925 const struct rtw89_dle_size wde_size19; 926 const struct rtw89_dle_size wde_size23; 927 const struct rtw89_dle_size ple_size0; 928 const struct rtw89_dle_size ple_size0_v1; 929 const struct rtw89_dle_size ple_size3_v1; 930 const struct rtw89_dle_size ple_size4; 931 const struct rtw89_dle_size ple_size6; 932 const struct rtw89_dle_size ple_size8; 933 const struct rtw89_dle_size ple_size9; 934 const struct rtw89_dle_size ple_size18; 935 const struct rtw89_dle_size ple_size19; 936 const struct rtw89_wde_quota wde_qt0; 937 const struct rtw89_wde_quota wde_qt0_v1; 938 const struct rtw89_wde_quota wde_qt4; 939 const struct rtw89_wde_quota wde_qt6; 940 const struct rtw89_wde_quota wde_qt7; 941 const struct rtw89_wde_quota wde_qt17; 942 const struct rtw89_wde_quota wde_qt18; 943 const struct rtw89_wde_quota wde_qt23; 944 const struct rtw89_ple_quota ple_qt0; 945 const struct rtw89_ple_quota ple_qt1; 946 const struct rtw89_ple_quota ple_qt4; 947 const struct rtw89_ple_quota ple_qt5; 948 const struct rtw89_ple_quota ple_qt9; 949 const struct rtw89_ple_quota ple_qt13; 950 const struct rtw89_ple_quota ple_qt18; 951 const struct rtw89_ple_quota ple_qt44; 952 const struct rtw89_ple_quota ple_qt45; 953 const struct rtw89_ple_quota ple_qt46; 954 const struct rtw89_ple_quota ple_qt47; 955 const struct rtw89_ple_quota ple_qt57; 956 const struct rtw89_ple_quota ple_qt58; 957 const struct rtw89_ple_quota ple_qt59; 958 const struct rtw89_ple_quota ple_qt_52a_wow; 959 const struct rtw89_ple_quota ple_qt_52b_wow; 960 const struct rtw89_ple_quota ple_qt_52bt_wow; 961 const struct rtw89_ple_quota ple_qt_51b_wow; 962 const struct rtw89_rsvd_quota ple_rsvd_qt0; 963 const struct rtw89_rsvd_quota ple_rsvd_qt1; 964 const struct rtw89_dle_rsvd_size rsvd0_size0; 965 const struct rtw89_dle_rsvd_size rsvd1_size0; 966 }; 967 968 extern const struct rtw89_mac_size_set rtw89_mac_size; 969 970 struct rtw89_mac_gen_def { 971 u32 band1_offset; 972 u32 filter_model_addr; 973 u32 indir_access_addr; 974 const u32 *mem_base_addrs; 975 u32 mem_page_size; 976 u32 rx_fltr; 977 const struct rtw89_port_reg *port_base; 978 u32 agg_len_ht; 979 u32 ps_status; 980 981 struct rtw89_reg_def muedca_ctrl; 982 struct rtw89_reg_def bfee_ctrl; 983 struct rtw89_reg_def narrow_bw_ru_dis; 984 struct rtw89_reg_def wow_ctrl; 985 struct rtw89_reg_def agg_limit; 986 struct rtw89_reg_def txcnt_limit; 987 988 int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band, 989 enum rtw89_mac_hwmod_sel sel); 990 int (*sys_init)(struct rtw89_dev *rtwdev); 991 int (*trx_init)(struct rtw89_dev *rtwdev); 992 void (*hci_func_en)(struct rtw89_dev *rtwdev); 993 void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev); 994 void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable); 995 void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable); 996 void (*bf_assoc)(struct rtw89_dev *rtwdev, 997 struct rtw89_vif_link *rtwvif_link, 998 struct rtw89_sta_link *rtwsta_link); 999 1000 int (*typ_fltr_opt)(struct rtw89_dev *rtwdev, 1001 enum rtw89_machdr_frame_type type, 1002 enum rtw89_mac_fwd_target fwd_target, 1003 u8 mac_idx); 1004 int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable); 1005 void (*cfg_phy_rpt)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable); 1006 1007 int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg); 1008 int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple); 1009 int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id); 1010 void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en); 1011 void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev); 1012 void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev); 1013 void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev); 1014 void (*wde_quota_cfg)(struct rtw89_dev *rtwdev, 1015 const struct rtw89_wde_quota *min_cfg, 1016 const struct rtw89_wde_quota *max_cfg, 1017 u16 ext_wde_min_qt_wcpu); 1018 void (*ple_quota_cfg)(struct rtw89_dev *rtwdev, 1019 const struct rtw89_ple_quota *min_cfg, 1020 const struct rtw89_ple_quota *max_cfg); 1021 int (*set_cpuio)(struct rtw89_dev *rtwdev, 1022 struct rtw89_cpuio_ctrl *ctrl_para, bool wd); 1023 int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en); 1024 1025 void (*disable_cpu)(struct rtw89_dev *rtwdev); 1026 int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason, 1027 bool dlfw, bool include_bb); 1028 u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type); 1029 int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl); 1030 void (*fwdl_secure_idmem_share_mode)(struct rtw89_dev *rtwdev, u8 mode); 1031 int (*parse_efuse_map)(struct rtw89_dev *rtwdev); 1032 int (*parse_phycap_map)(struct rtw89_dev *rtwdev); 1033 int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle); 1034 int (*efuse_read_fw_secure)(struct rtw89_dev *rtwdev); 1035 1036 int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); 1037 u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band); 1038 1039 bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev, 1040 enum rtw89_phy_idx phy_idx, 1041 u32 reg_base, u32 *cr); 1042 1043 int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); 1044 int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val); 1045 1046 void (*dump_qta_lost)(struct rtw89_dev *rtwdev); 1047 void (*dump_err_status)(struct rtw89_dev *rtwdev, 1048 enum mac_ax_err_info err); 1049 1050 bool (*is_txq_empty)(struct rtw89_dev *rtwdev); 1051 1052 int (*prep_chan_list)(struct rtw89_dev *rtwdev, 1053 struct rtw89_vif_link *rtwvif_link); 1054 void (*free_chan_list)(struct rtw89_dev *rtwdev); 1055 int (*add_chan_list)(struct rtw89_dev *rtwdev, 1056 struct rtw89_vif_link *rtwvif_link); 1057 int (*add_chan_list_pno)(struct rtw89_dev *rtwdev, 1058 struct rtw89_vif_link *rtwvif_link); 1059 int (*scan_offload)(struct rtw89_dev *rtwdev, 1060 struct rtw89_scan_option *option, 1061 struct rtw89_vif_link *rtwvif_link, 1062 bool wowlan); 1063 1064 int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow); 1065 }; 1066 1067 extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax; 1068 extern const struct rtw89_mac_gen_def rtw89_mac_gen_be; 1069 1070 static inline 1071 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band) 1072 { 1073 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1074 1075 return band == 0 ? reg_base : (reg_base + mac->band1_offset); 1076 } 1077 1078 static inline 1079 u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx) 1080 { 1081 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx); 1082 } 1083 1084 static inline u32 1085 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base) 1086 { 1087 u32 reg; 1088 1089 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1090 rtwvif_link->mac_idx); 1091 return rtw89_read32(rtwdev, reg); 1092 } 1093 1094 static inline u32 1095 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1096 u32 base, u32 mask) 1097 { 1098 u32 reg; 1099 1100 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1101 rtwvif_link->mac_idx); 1102 return rtw89_read32_mask(rtwdev, reg, mask); 1103 } 1104 1105 static inline void 1106 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base, 1107 u32 data) 1108 { 1109 u32 reg; 1110 1111 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1112 rtwvif_link->mac_idx); 1113 rtw89_write32(rtwdev, reg, data); 1114 } 1115 1116 static inline void 1117 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1118 u32 base, u32 mask, u32 data) 1119 { 1120 u32 reg; 1121 1122 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1123 rtwvif_link->mac_idx); 1124 rtw89_write32_mask(rtwdev, reg, mask, data); 1125 } 1126 1127 static inline void 1128 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1129 u32 base, u32 mask, u16 data) 1130 { 1131 u32 reg; 1132 1133 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1134 rtwvif_link->mac_idx); 1135 rtw89_write16_mask(rtwdev, reg, mask, data); 1136 } 1137 1138 static inline void 1139 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1140 u32 base, u32 bit) 1141 { 1142 u32 reg; 1143 1144 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1145 rtwvif_link->mac_idx); 1146 rtw89_write32_clr(rtwdev, reg, bit); 1147 } 1148 1149 static inline void 1150 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1151 u32 base, u16 bit) 1152 { 1153 u32 reg; 1154 1155 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1156 rtwvif_link->mac_idx); 1157 rtw89_write16_clr(rtwdev, reg, bit); 1158 } 1159 1160 static inline void 1161 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1162 u32 base, u32 bit) 1163 { 1164 u32 reg; 1165 1166 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1167 rtwvif_link->mac_idx); 1168 rtw89_write32_set(rtwdev, reg, bit); 1169 } 1170 1171 int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev); 1172 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); 1173 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb); 1174 int rtw89_mac_init(struct rtw89_dev *rtwdev); 1175 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1176 enum rtw89_qta_mode ext_mode); 1177 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en); 1178 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1179 enum rtw89_qta_mode mode); 1180 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode); 1181 static inline 1182 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, 1183 enum rtw89_mac_hwmod_sel sel) 1184 { 1185 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1186 1187 return mac->check_mac_en(rtwdev, band, sel); 1188 } 1189 1190 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); 1191 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); 1192 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl); 1193 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 1194 struct rtw89_mac_dle_dfi_quota *quota); 1195 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev); 1196 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 1197 struct rtw89_mac_dle_dfi_qempty *qempty); 1198 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 1199 enum mac_ax_err_info err); 1200 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif); 1201 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1202 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 1203 struct rtw89_vif_link *rtwvif_link, 1204 struct rtw89_vif_link *rtwvif_src, 1205 u16 offset_tu); 1206 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1207 u64 *tsf); 1208 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 1209 struct rtw89_vif_link *rtwvif_link, bool en); 1210 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 1211 struct rtw89_vif_link *rtwvif_link); 1212 void rtw89_mac_set_he_tb(struct rtw89_dev *rtwdev, 1213 struct rtw89_vif_link *rtwvif_link); 1214 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1215 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en); 1216 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif); 1217 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); 1218 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); 1219 1220 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev) 1221 { 1222 const struct rtw89_chip_info *chip = rtwdev->chip; 1223 1224 return chip->ops->enable_bb_rf(rtwdev); 1225 } 1226 1227 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev) 1228 { 1229 const struct rtw89_chip_info *chip = rtwdev->chip; 1230 1231 return chip->ops->disable_bb_rf(rtwdev); 1232 } 1233 1234 static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev) 1235 { 1236 int ret; 1237 1238 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 1239 return 0; 1240 1241 ret = rtw89_chip_disable_bb_rf(rtwdev); 1242 if (ret) 1243 return ret; 1244 ret = rtw89_chip_enable_bb_rf(rtwdev); 1245 if (ret) 1246 return ret; 1247 1248 return 0; 1249 } 1250 1251 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); 1252 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); 1253 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 1254 u8 class, u8 func); 1255 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1256 u32 len, u8 class, u8 func); 1257 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); 1258 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 1259 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1260 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 1261 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1262 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, 1263 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1264 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1265 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1266 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1267 void rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable); 1268 1269 static inline 1270 void rtw89_mac_cfg_phy_rpt(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 1271 { 1272 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1273 1274 if (mac->cfg_phy_rpt) 1275 mac->cfg_phy_rpt(rtwdev, mac_idx, enable); 1276 } 1277 1278 static inline 1279 void rtw89_mac_cfg_phy_rpt_bands(struct rtw89_dev *rtwdev, bool enable) 1280 { 1281 rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_0, enable); 1282 1283 if (!rtwdev->dbcc_en) 1284 return; 1285 1286 rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_1, enable); 1287 } 1288 1289 static inline 1290 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 1291 { 1292 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1293 1294 return mac->cfg_ppdu_status(rtwdev, mac_idx, enable); 1295 } 1296 1297 static inline 1298 int rtw89_mac_cfg_ppdu_status_bands(struct rtw89_dev *rtwdev, bool enable) 1299 { 1300 int ret; 1301 1302 ret = rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, enable); 1303 if (ret) 1304 return ret; 1305 1306 if (!rtwdev->dbcc_en) 1307 return 0; 1308 1309 return rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_1, enable); 1310 } 1311 1312 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev); 1313 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); 1314 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); 1315 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 1316 const struct rtw89_mac_ax_coex *coex); 1317 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 1318 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1319 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 1320 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1321 int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev, 1322 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1323 1324 static inline 1325 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 1326 { 1327 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1328 1329 return mac->cfg_plt(rtwdev, plt); 1330 } 1331 1332 static inline 1333 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 1334 { 1335 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1336 1337 return mac->get_plt_cnt(rtwdev, band); 1338 } 1339 1340 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); 1341 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); 1342 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); 1343 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); 1344 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); 1345 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl); 1346 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); 1347 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); 1348 1349 static inline 1350 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, 1351 struct rtw89_vif_link *rtwvif_link, 1352 struct rtw89_sta_link *rtwsta_link) 1353 { 1354 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1355 1356 if (mac->bf_assoc) 1357 mac->bf_assoc(rtwdev, rtwvif_link, rtwsta_link); 1358 } 1359 1360 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, 1361 struct rtw89_vif_link *rtwvif_link, 1362 struct rtw89_sta_link *rtwsta_link); 1363 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1364 struct ieee80211_bss_conf *conf); 1365 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 1366 struct rtw89_sta_link *rtwsta_link, 1367 bool disconnect); 1368 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); 1369 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en); 1370 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1371 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1372 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 1373 struct rtw89_vif_link *rtwvif_link, bool en); 1374 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause); 1375 1376 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 1377 { 1378 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 1379 return; 1380 1381 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) 1382 return; 1383 1384 _rtw89_mac_bf_monitor_track(rtwdev); 1385 } 1386 1387 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, 1388 enum rtw89_phy_idx phy_idx, 1389 u32 reg_base, u32 *val) 1390 { 1391 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1392 u32 cr; 1393 1394 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1395 return -EINVAL; 1396 1397 *val = rtw89_read32(rtwdev, cr); 1398 return 0; 1399 } 1400 1401 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, 1402 enum rtw89_phy_idx phy_idx, 1403 u32 reg_base, u32 val) 1404 { 1405 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1406 u32 cr; 1407 1408 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1409 return -EINVAL; 1410 1411 rtw89_write32(rtwdev, cr, val); 1412 return 0; 1413 } 1414 1415 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, 1416 enum rtw89_phy_idx phy_idx, 1417 u32 reg_base, u32 mask, u32 val) 1418 { 1419 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1420 u32 cr; 1421 1422 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1423 return -EINVAL; 1424 1425 rtw89_write32_mask(rtwdev, cr, mask, val); 1426 return 0; 1427 } 1428 1429 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev, 1430 bool enable) 1431 { 1432 const struct rtw89_chip_info *chip = rtwdev->chip; 1433 1434 if (enable) 1435 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1436 B_AX_HCI_TXDMA_EN); 1437 else 1438 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1439 B_AX_HCI_TXDMA_EN); 1440 } 1441 1442 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev, 1443 bool enable) 1444 { 1445 const struct rtw89_chip_info *chip = rtwdev->chip; 1446 1447 if (enable) 1448 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1449 B_AX_HCI_RXDMA_EN); 1450 else 1451 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1452 B_AX_HCI_RXDMA_EN); 1453 } 1454 1455 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev, 1456 bool enable) 1457 { 1458 const struct rtw89_chip_info *chip = rtwdev->chip; 1459 1460 if (enable) 1461 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1462 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1463 else 1464 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1465 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1466 } 1467 1468 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev) 1469 { 1470 u32 val; 1471 1472 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, 1473 B_AX_WLMAC_PWR_STE_MASK); 1474 1475 return !!val; 1476 } 1477 1478 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 1479 bool resume, u32 tx_time); 1480 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 1481 u32 *tx_time); 1482 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 1483 struct rtw89_sta_link *rtwsta_link, 1484 bool resume, u8 tx_retry); 1485 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 1486 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry); 1487 1488 enum rtw89_mac_xtal_si_offset { 1489 XTAL0 = 0x0, 1490 XTAL3 = 0x3, 1491 XTAL_SI_XTAL_SC_XI = 0x04, 1492 #define XTAL_SC_XI_MASK GENMASK(7, 0) 1493 XTAL_SI_XTAL_SC_XO = 0x05, 1494 #define XTAL_SC_XO_MASK GENMASK(7, 0) 1495 XTAL_SI_XREF_MODE = 0x0B, 1496 XTAL_SI_PWR_CUT = 0x10, 1497 #define XTAL_SI_SMALL_PWR_CUT BIT(0) 1498 #define XTAL_SI_BIG_PWR_CUT BIT(1) 1499 XTAL_SI_XTAL_DRV = 0x15, 1500 #define XTAL_SI_DRV_LATCH BIT(4) 1501 XTAL_SI_XTAL_PLL = 0x16, 1502 XTAL_SI_XTAL_XMD_2 = 0x24, 1503 #define XTAL_SI_LDO_LPS GENMASK(6, 4) 1504 XTAL_SI_XTAL_XMD_4 = 0x26, 1505 #define XTAL_SI_LPS_CAP GENMASK(3, 0) 1506 XTAL_SI_XREF_RF1 = 0x2D, 1507 XTAL_SI_XREF_RF2 = 0x2E, 1508 XTAL_SI_CV = 0x41, 1509 #define XTAL_SI_ACV_MASK GENMASK(3, 0) 1510 XTAL_SI_LOW_ADDR = 0x62, 1511 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0) 1512 XTAL_SI_CTRL = 0x63, 1513 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6) 1514 #define XTAL_SI_RDY BIT(5) 1515 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0) 1516 XTAL_SI_READ_VAL = 0x7A, 1517 XTAL_SI_WL_RFC_S0 = 0x80, 1518 #define XTAL_SI_RF00S_EN GENMASK(2, 0) 1519 #define XTAL_SI_RF00 BIT(0) 1520 XTAL_SI_WL_RFC_S1 = 0x81, 1521 #define XTAL_SI_RF10S_EN GENMASK(2, 0) 1522 #define XTAL_SI_RF10 BIT(0) 1523 XTAL_SI_ANAPAR_WL = 0x90, 1524 #define XTAL_SI_SRAM2RFC BIT(7) 1525 #define XTAL_SI_GND_SHDN_WL BIT(6) 1526 #define XTAL_SI_SHDN_WL BIT(5) 1527 #define XTAL_SI_RFC2RF BIT(4) 1528 #define XTAL_SI_OFF_EI BIT(3) 1529 #define XTAL_SI_OFF_WEI BIT(2) 1530 #define XTAL_SI_PON_EI BIT(1) 1531 #define XTAL_SI_PON_WEI BIT(0) 1532 XTAL_SI_SRAM_CTRL = 0xA1, 1533 #define XTAL_SI_SRAM_DIS BIT(1) 1534 #define FULL_BIT_MASK GENMASK(7, 0) 1535 XTAL_SI_APBT = 0xD1, 1536 XTAL_SI_PLL = 0xE0, 1537 XTAL_SI_PLL_1 = 0xE1, 1538 }; 1539 1540 static inline 1541 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 1542 { 1543 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1544 1545 return mac->write_xtal_si(rtwdev, offset, val, mask); 1546 } 1547 1548 static inline 1549 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 1550 { 1551 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1552 1553 return mac->read_xtal_si(rtwdev, offset, val); 1554 } 1555 1556 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1557 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow); 1558 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 1559 enum rtw89_mac_idx band); 1560 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow); 1561 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1562 bool band1_en); 1563 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1564 enum rtw89_mac_dle_rsvd_qt_type type, 1565 struct rtw89_mac_dle_rsvd_qt_cfg *cfg); 1566 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable); 1567 1568 static inline 1569 void rtw89_fwdl_secure_idmem_share_mode(struct rtw89_dev *rtwdev, u8 mode) 1570 { 1571 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1572 1573 if (!mac->fwdl_secure_idmem_share_mode) 1574 return; 1575 1576 return mac->fwdl_secure_idmem_share_mode(rtwdev, mode); 1577 } 1578 #endif 1579