1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_MAC_H__ 6 #define __RTW89_MAC_H__ 7 8 #include "core.h" 9 #include "fw.h" 10 #include "reg.h" 11 12 #define MAC_MEM_DUMP_PAGE_SIZE_AX 0x40000 13 #define MAC_MEM_DUMP_PAGE_SIZE_BE 0x80000 14 15 #define ADDR_CAM_ENT_SIZE 0x40 16 #define ADDR_CAM_ENT_SHORT_SIZE 0x20 17 #define BSSID_CAM_ENT_SIZE 0x08 18 #define HFC_PAGE_UNIT 64 19 #define RPWM_TRY_CNT 3 20 21 enum rtw89_mac_hwmod_sel { 22 RTW89_DMAC_SEL = 0, 23 RTW89_CMAC_SEL = 1, 24 25 RTW89_MAC_INVALID, 26 }; 27 28 enum rtw89_mac_fwd_target { 29 RTW89_FWD_DONT_CARE = 0, 30 RTW89_FWD_TO_HOST = 1, 31 RTW89_FWD_TO_WLAN_CPU = 2 32 }; 33 34 enum rtw89_mac_wd_dma_intvl { 35 RTW89_MAC_WD_DMA_INTVL_0S, 36 RTW89_MAC_WD_DMA_INTVL_256NS, 37 RTW89_MAC_WD_DMA_INTVL_512NS, 38 RTW89_MAC_WD_DMA_INTVL_768NS, 39 RTW89_MAC_WD_DMA_INTVL_1US, 40 RTW89_MAC_WD_DMA_INTVL_1_5US, 41 RTW89_MAC_WD_DMA_INTVL_2US, 42 RTW89_MAC_WD_DMA_INTVL_4US, 43 RTW89_MAC_WD_DMA_INTVL_8US, 44 RTW89_MAC_WD_DMA_INTVL_16US, 45 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE 46 }; 47 48 enum rtw89_mac_multi_tag_num { 49 RTW89_MAC_TAG_NUM_1, 50 RTW89_MAC_TAG_NUM_2, 51 RTW89_MAC_TAG_NUM_3, 52 RTW89_MAC_TAG_NUM_4, 53 RTW89_MAC_TAG_NUM_5, 54 RTW89_MAC_TAG_NUM_6, 55 RTW89_MAC_TAG_NUM_7, 56 RTW89_MAC_TAG_NUM_8, 57 RTW89_MAC_TAG_NUM_DEF = 0xFE 58 }; 59 60 enum rtw89_mac_lbc_tmr { 61 RTW89_MAC_LBC_TMR_8US = 0, 62 RTW89_MAC_LBC_TMR_16US, 63 RTW89_MAC_LBC_TMR_32US, 64 RTW89_MAC_LBC_TMR_64US, 65 RTW89_MAC_LBC_TMR_128US, 66 RTW89_MAC_LBC_TMR_256US, 67 RTW89_MAC_LBC_TMR_512US, 68 RTW89_MAC_LBC_TMR_1MS, 69 RTW89_MAC_LBC_TMR_2MS, 70 RTW89_MAC_LBC_TMR_4MS, 71 RTW89_MAC_LBC_TMR_8MS, 72 RTW89_MAC_LBC_TMR_DEF = 0xFE 73 }; 74 75 enum rtw89_mac_cpuio_op_cmd_type { 76 CPUIO_OP_CMD_GET_1ST_PID = 0, 77 CPUIO_OP_CMD_GET_NEXT_PID = 1, 78 CPUIO_OP_CMD_ENQ_TO_TAIL = 4, 79 CPUIO_OP_CMD_ENQ_TO_HEAD = 5, 80 CPUIO_OP_CMD_DEQ = 8, 81 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, 82 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 83 }; 84 85 enum rtw89_mac_wde_dle_port_id { 86 WDE_DLE_PORT_ID_DISPATCH = 0, 87 WDE_DLE_PORT_ID_PKTIN = 1, 88 WDE_DLE_PORT_ID_CMAC0 = 3, 89 WDE_DLE_PORT_ID_CMAC1 = 4, 90 WDE_DLE_PORT_ID_CPU_IO = 6, 91 WDE_DLE_PORT_ID_WDRLS = 7, 92 WDE_DLE_PORT_ID_END = 8 93 }; 94 95 enum rtw89_mac_wde_dle_queid_wdrls { 96 WDE_DLE_QUEID_TXOK = 0, 97 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, 98 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, 99 WDE_DLE_QUEID_DROP_MACID_DROP = 3, 100 WDE_DLE_QUEID_NO_REPORT = 4 101 }; 102 103 enum rtw89_mac_ple_dle_port_id { 104 PLE_DLE_PORT_ID_DISPATCH = 0, 105 PLE_DLE_PORT_ID_MPDU = 1, 106 PLE_DLE_PORT_ID_SEC = 2, 107 PLE_DLE_PORT_ID_CMAC0 = 3, 108 PLE_DLE_PORT_ID_CMAC1 = 4, 109 PLE_DLE_PORT_ID_WDRLS = 5, 110 PLE_DLE_PORT_ID_CPU_IO = 6, 111 PLE_DLE_PORT_ID_PLRLS = 7, 112 PLE_DLE_PORT_ID_END = 8 113 }; 114 115 enum rtw89_mac_ple_dle_queid_plrls { 116 PLE_DLE_QUEID_NO_REPORT = 0x0 117 }; 118 119 enum rtw89_machdr_frame_type { 120 RTW89_MGNT = 0, 121 RTW89_CTRL = 1, 122 RTW89_DATA = 2, 123 }; 124 125 enum rtw89_mac_dle_dfi_type { 126 DLE_DFI_TYPE_FREEPG = 0, 127 DLE_DFI_TYPE_QUOTA = 1, 128 DLE_DFI_TYPE_PAGELLT = 2, 129 DLE_DFI_TYPE_PKTINFO = 3, 130 DLE_DFI_TYPE_PREPKTLLT = 4, 131 DLE_DFI_TYPE_NXTPKTLLT = 5, 132 DLE_DFI_TYPE_QLNKTBL = 6, 133 DLE_DFI_TYPE_QEMPTY = 7, 134 }; 135 136 enum rtw89_mac_dle_wde_quota_id { 137 WDE_QTAID_HOST_IF = 0, 138 WDE_QTAID_WLAN_CPU = 1, 139 WDE_QTAID_DATA_CPU = 2, 140 WDE_QTAID_PKTIN = 3, 141 WDE_QTAID_CPUIO = 4, 142 }; 143 144 enum rtw89_mac_dle_ple_quota_id { 145 PLE_QTAID_B0_TXPL = 0, 146 PLE_QTAID_B1_TXPL = 1, 147 PLE_QTAID_C2H = 2, 148 PLE_QTAID_H2C = 3, 149 PLE_QTAID_WLAN_CPU = 4, 150 PLE_QTAID_MPDU = 5, 151 PLE_QTAID_CMAC0_RX = 6, 152 PLE_QTAID_CMAC1_RX = 7, 153 PLE_QTAID_CMAC1_BBRPT = 8, 154 PLE_QTAID_WDRLS = 9, 155 PLE_QTAID_CPUIO = 10, 156 }; 157 158 enum rtw89_mac_dle_ctrl_type { 159 DLE_CTRL_TYPE_WDE = 0, 160 DLE_CTRL_TYPE_PLE = 1, 161 DLE_CTRL_TYPE_NUM = 2, 162 }; 163 164 enum rtw89_mac_ax_l0_to_l1_event { 165 MAC_AX_L0_TO_L1_CHIF_IDLE = 0, 166 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, 167 MAC_AX_L0_TO_L1_RLS_PKID = 2, 168 MAC_AX_L0_TO_L1_PTCL_IDLE = 3, 169 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, 170 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, 171 MAC_AX_L0_TO_L1_PCIE_STUCK = 6, 172 MAC_AX_L0_TO_L1_EVENT_MAX = 15, 173 }; 174 175 enum rtw89_mac_phy_rpt_size { 176 MAC_AX_PHY_RPT_SIZE_0 = 0, 177 MAC_AX_PHY_RPT_SIZE_8 = 1, 178 MAC_AX_PHY_RPT_SIZE_16 = 2, 179 MAC_AX_PHY_RPT_SIZE_24 = 3, 180 }; 181 182 enum rtw89_mac_hdr_cnv_size { 183 MAC_AX_HDR_CNV_SIZE_0 = 0, 184 MAC_AX_HDR_CNV_SIZE_32 = 1, 185 MAC_AX_HDR_CNV_SIZE_64 = 2, 186 MAC_AX_HDR_CNV_SIZE_96 = 3, 187 }; 188 189 enum rtw89_mac_wow_fw_status { 190 WOWLAN_NOT_READY = 0x00, 191 WOWLAN_SLEEP_READY = 0x01, 192 WOWLAN_RESUME_READY = 0x02, 193 }; 194 195 #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32) 196 197 enum rtw89_mac_dbg_port_sel { 198 /* CMAC 0 related */ 199 RTW89_DBG_PORT_SEL_PTCL_C0 = 0, 200 RTW89_DBG_PORT_SEL_SCH_C0, 201 RTW89_DBG_PORT_SEL_TMAC_C0, 202 RTW89_DBG_PORT_SEL_RMAC_C0, 203 RTW89_DBG_PORT_SEL_RMACST_C0, 204 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, 205 RTW89_DBG_PORT_SEL_TRXPTCL_C0, 206 RTW89_DBG_PORT_SEL_TX_INFOL_C0, 207 RTW89_DBG_PORT_SEL_TX_INFOH_C0, 208 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, 209 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, 210 /* CMAC 1 related */ 211 RTW89_DBG_PORT_SEL_PTCL_C1, 212 RTW89_DBG_PORT_SEL_SCH_C1, 213 RTW89_DBG_PORT_SEL_TMAC_C1, 214 RTW89_DBG_PORT_SEL_RMAC_C1, 215 RTW89_DBG_PORT_SEL_RMACST_C1, 216 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, 217 RTW89_DBG_PORT_SEL_TRXPTCL_C1, 218 RTW89_DBG_PORT_SEL_TX_INFOL_C1, 219 RTW89_DBG_PORT_SEL_TX_INFOH_C1, 220 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, 221 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, 222 /* DLE related */ 223 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, 224 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, 225 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, 226 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, 227 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, 228 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, 229 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, 230 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, 231 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, 232 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, 233 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, 234 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, 235 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, 236 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, 237 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, 238 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, 239 RTW89_DBG_PORT_SEL_PKTINFO, 240 /* DISPATCHER related */ 241 RTW89_DBG_PORT_SEL_DSPT_HDT_TX0, 242 RTW89_DBG_PORT_SEL_DSPT_HDT_TX1, 243 RTW89_DBG_PORT_SEL_DSPT_HDT_TX2, 244 RTW89_DBG_PORT_SEL_DSPT_HDT_TX3, 245 RTW89_DBG_PORT_SEL_DSPT_HDT_TX4, 246 RTW89_DBG_PORT_SEL_DSPT_HDT_TX5, 247 RTW89_DBG_PORT_SEL_DSPT_HDT_TX6, 248 RTW89_DBG_PORT_SEL_DSPT_HDT_TX7, 249 RTW89_DBG_PORT_SEL_DSPT_HDT_TX8, 250 RTW89_DBG_PORT_SEL_DSPT_HDT_TX9, 251 RTW89_DBG_PORT_SEL_DSPT_HDT_TXA, 252 RTW89_DBG_PORT_SEL_DSPT_HDT_TXB, 253 RTW89_DBG_PORT_SEL_DSPT_HDT_TXC, 254 RTW89_DBG_PORT_SEL_DSPT_HDT_TXD, 255 RTW89_DBG_PORT_SEL_DSPT_HDT_TXE, 256 RTW89_DBG_PORT_SEL_DSPT_HDT_TXF, 257 RTW89_DBG_PORT_SEL_DSPT_CDT_TX0, 258 RTW89_DBG_PORT_SEL_DSPT_CDT_TX1, 259 RTW89_DBG_PORT_SEL_DSPT_CDT_TX3, 260 RTW89_DBG_PORT_SEL_DSPT_CDT_TX4, 261 RTW89_DBG_PORT_SEL_DSPT_CDT_TX5, 262 RTW89_DBG_PORT_SEL_DSPT_CDT_TX6, 263 RTW89_DBG_PORT_SEL_DSPT_CDT_TX7, 264 RTW89_DBG_PORT_SEL_DSPT_CDT_TX8, 265 RTW89_DBG_PORT_SEL_DSPT_CDT_TX9, 266 RTW89_DBG_PORT_SEL_DSPT_CDT_TXA, 267 RTW89_DBG_PORT_SEL_DSPT_CDT_TXB, 268 RTW89_DBG_PORT_SEL_DSPT_CDT_TXC, 269 RTW89_DBG_PORT_SEL_DSPT_HDT_RX0, 270 RTW89_DBG_PORT_SEL_DSPT_HDT_RX1, 271 RTW89_DBG_PORT_SEL_DSPT_HDT_RX2, 272 RTW89_DBG_PORT_SEL_DSPT_HDT_RX3, 273 RTW89_DBG_PORT_SEL_DSPT_HDT_RX4, 274 RTW89_DBG_PORT_SEL_DSPT_HDT_RX5, 275 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0, 276 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0, 277 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1, 278 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2, 279 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1, 280 RTW89_DBG_PORT_SEL_DSPT_STF_CTRL, 281 RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL, 282 RTW89_DBG_PORT_SEL_DSPT_WDE_INTF, 283 RTW89_DBG_PORT_SEL_DSPT_PLE_INTF, 284 RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL, 285 /* PCIE related */ 286 RTW89_DBG_PORT_SEL_PCIE_TXDMA, 287 RTW89_DBG_PORT_SEL_PCIE_RXDMA, 288 RTW89_DBG_PORT_SEL_PCIE_CVT, 289 RTW89_DBG_PORT_SEL_PCIE_CXPL, 290 RTW89_DBG_PORT_SEL_PCIE_IO, 291 RTW89_DBG_PORT_SEL_PCIE_MISC, 292 RTW89_DBG_PORT_SEL_PCIE_MISC2, 293 294 /* keep last */ 295 RTW89_DBG_PORT_SEL_LAST, 296 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, 297 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, 298 }; 299 300 /* SRAM mem dump */ 301 #define R_AX_INDIR_ACCESS_ENTRY 0x40000 302 #define R_BE_INDIR_ACCESS_ENTRY 0x80000 303 304 #define AXIDMA_BASE_ADDR 0x18006000 305 #define STA_SCHED_BASE_ADDR 0x18808000 306 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 307 #define SECURITY_CAM_BASE_ADDR 0x18814000 308 #define WOW_CAM_BASE_ADDR 0x18815000 309 #define CMAC_TBL_BASE_ADDR 0x18840000 310 #define ADDR_CAM_BASE_ADDR 0x18850000 311 #define BSSID_CAM_BASE_ADDR 0x18853000 312 #define BA_CAM_BASE_ADDR 0x18854000 313 #define BCN_IE_CAM0_BASE_ADDR 0x18855000 314 #define SHARED_BUF_BASE_ADDR 0x18700000 315 #define DMAC_TBL_BASE_ADDR 0x18800000 316 #define SHCUT_MACHDR_BASE_ADDR 0x18800800 317 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000 318 #define TXD_FIFO_0_BASE_ADDR 0x18856200 319 #define TXD_FIFO_1_BASE_ADDR 0x188A1080 320 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */ 321 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */ 322 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000 323 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 324 #define CPU_LOCAL_BASE_ADDR 0x18003000 325 326 #define WD_PAGE_BASE_ADDR_BE 0x0 327 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000 328 #define AXIDMA_BASE_ADDR_BE 0x18006000 329 #define SHARED_BUF_BASE_ADDR_BE 0x18700000 330 #define DMAC_TBL_BASE_ADDR_BE 0x18800000 331 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800 332 #define STA_SCHED_BASE_ADDR_BE 0x18818000 333 #define NAT25_CAM_BASE_ADDR_BE 0x18820000 334 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000 335 #define SEC_CAM_BASE_ADDR_BE 0x18824000 336 #define WOW_CAM_BASE_ADDR_BE 0x18828000 337 #define MLD_TBL_BASE_ADDR_BE 0x18829000 338 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000 339 #define CMAC_TBL_BASE_ADDR_BE 0x18840000 340 #define ADDR_CAM_BASE_ADDR_BE 0x18850000 341 #define BSSID_CAM_BASE_ADDR_BE 0x18858000 342 #define BA_CAM_BASE_ADDR_BE 0x18859000 343 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000 344 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000 345 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000 346 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000 347 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000 348 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800 349 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000 350 351 #define CCTL_INFO_SIZE 32 352 353 enum rtw89_mac_mem_sel { 354 RTW89_MAC_MEM_AXIDMA, 355 RTW89_MAC_MEM_SHARED_BUF, 356 RTW89_MAC_MEM_DMAC_TBL, 357 RTW89_MAC_MEM_SHCUT_MACHDR, 358 RTW89_MAC_MEM_STA_SCHED, 359 RTW89_MAC_MEM_RXPLD_FLTR_CAM, 360 RTW89_MAC_MEM_SECURITY_CAM, 361 RTW89_MAC_MEM_WOW_CAM, 362 RTW89_MAC_MEM_CMAC_TBL, 363 RTW89_MAC_MEM_ADDR_CAM, 364 RTW89_MAC_MEM_BA_CAM, 365 RTW89_MAC_MEM_BCN_IE_CAM0, 366 RTW89_MAC_MEM_BCN_IE_CAM1, 367 RTW89_MAC_MEM_TXD_FIFO_0, 368 RTW89_MAC_MEM_TXD_FIFO_1, 369 RTW89_MAC_MEM_TXDATA_FIFO_0, 370 RTW89_MAC_MEM_TXDATA_FIFO_1, 371 RTW89_MAC_MEM_CPU_LOCAL, 372 RTW89_MAC_MEM_BSSID_CAM, 373 RTW89_MAC_MEM_TXD_FIFO_0_V1, 374 RTW89_MAC_MEM_TXD_FIFO_1_V1, 375 RTW89_MAC_MEM_WD_PAGE, 376 RTW89_MAC_MEM_MLD_TBL, 377 378 /* keep last */ 379 RTW89_MAC_MEM_NUM, 380 }; 381 382 enum rtw89_rpwm_req_pwr_state { 383 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, 384 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, 385 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, 386 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, 387 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, 388 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, 389 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, 390 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, 391 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, 392 }; 393 394 struct rtw89_pwr_cfg { 395 u16 addr; 396 u8 cv_msk; 397 u8 intf_msk; 398 u8 base:4; 399 u8 cmd:4; 400 u8 msk; 401 u8 val; 402 }; 403 404 enum rtw89_mac_c2h_ofld_func { 405 RTW89_MAC_C2H_FUNC_EFUSE_DUMP, 406 RTW89_MAC_C2H_FUNC_READ_RSP, 407 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, 408 RTW89_MAC_C2H_FUNC_BCN_RESEND, 409 RTW89_MAC_C2H_FUNC_MACID_PAUSE, 410 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6, 411 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9, 412 RTW89_MAC_C2H_FUNC_TX_DUTY_RPT = 0xa, 413 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd, 414 RTW89_MAC_C2H_FUNC_OFLD_MAX, 415 }; 416 417 enum rtw89_mac_c2h_info_func { 418 RTW89_MAC_C2H_FUNC_REC_ACK, 419 RTW89_MAC_C2H_FUNC_DONE_ACK, 420 RTW89_MAC_C2H_FUNC_C2H_LOG, 421 RTW89_MAC_C2H_FUNC_BCN_CNT, 422 RTW89_MAC_C2H_FUNC_BCN_UPD_DONE = 0x06, 423 RTW89_MAC_C2H_FUNC_INFO_MAX, 424 }; 425 426 enum rtw89_mac_c2h_mcc_func { 427 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0, 428 RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1, 429 RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2, 430 RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3, 431 432 NUM_OF_RTW89_MAC_C2H_FUNC_MCC, 433 }; 434 435 enum rtw89_mac_c2h_misc_func { 436 RTW89_MAC_C2H_FUNC_TX_REPORT = 1, 437 438 NUM_OF_RTW89_MAC_C2H_FUNC_MISC, 439 }; 440 441 enum rtw89_mac_c2h_mlo_func { 442 RTW89_MAC_C2H_FUNC_MLO_GET_TBL = 0x0, 443 RTW89_MAC_C2H_FUNC_MLO_EMLSR_TRANS_DONE = 0x1, 444 RTW89_MAC_C2H_FUNC_MLO_EMLSR_STA_CFG_DONE = 0x2, 445 RTW89_MAC_C2H_FUNC_MCMLO_RELINK_RPT = 0x3, 446 RTW89_MAC_C2H_FUNC_MCMLO_SN_SYNC_RPT = 0x4, 447 RTW89_MAC_C2H_FUNC_MLO_LINK_CFG_STAT = 0x5, 448 RTW89_MAC_C2H_FUNC_MLO_DM_DBG_DUMP = 0x6, 449 450 NUM_OF_RTW89_MAC_C2H_FUNC_MLO, 451 }; 452 453 enum rtw89_mac_c2h_mrc_func { 454 RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0, 455 RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT = 1, 456 457 NUM_OF_RTW89_MAC_C2H_FUNC_MRC, 458 }; 459 460 enum rtw89_mac_c2h_wow_func { 461 RTW89_MAC_C2H_FUNC_AOAC_REPORT, 462 463 NUM_OF_RTW89_MAC_C2H_FUNC_WOW, 464 }; 465 466 enum rtw89_mac_c2h_ap_func { 467 RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY = 0, 468 469 NUM_OF_RTW89_MAC_C2H_FUNC_AP, 470 }; 471 472 enum rtw89_mac_c2h_class { 473 RTW89_MAC_C2H_CLASS_INFO = 0x0, 474 RTW89_MAC_C2H_CLASS_OFLD = 0x1, 475 RTW89_MAC_C2H_CLASS_TWT = 0x2, 476 RTW89_MAC_C2H_CLASS_WOW = 0x3, 477 RTW89_MAC_C2H_CLASS_MCC = 0x4, 478 RTW89_MAC_C2H_CLASS_FWDBG = 0x5, 479 RTW89_MAC_C2H_CLASS_MISC = 0x9, 480 RTW89_MAC_C2H_CLASS_MLO = 0xc, 481 RTW89_MAC_C2H_CLASS_MRC = 0xe, 482 RTW89_MAC_C2H_CLASS_AP = 0x18, 483 RTW89_MAC_C2H_CLASS_ROLE = 0x1b, 484 RTW89_MAC_C2H_CLASS_MAX, 485 }; 486 487 enum rtw89_mac_mcc_status { 488 RTW89_MAC_MCC_ADD_ROLE_OK = 0, 489 RTW89_MAC_MCC_START_GROUP_OK = 1, 490 RTW89_MAC_MCC_STOP_GROUP_OK = 2, 491 RTW89_MAC_MCC_DEL_GROUP_OK = 3, 492 RTW89_MAC_MCC_RESET_GROUP_OK = 4, 493 RTW89_MAC_MCC_SWITCH_CH_OK = 5, 494 RTW89_MAC_MCC_TXNULL0_OK = 6, 495 RTW89_MAC_MCC_TXNULL1_OK = 7, 496 497 RTW89_MAC_MCC_SWITCH_EARLY = 10, 498 RTW89_MAC_MCC_TBTT = 11, 499 RTW89_MAC_MCC_DURATION_START = 12, 500 RTW89_MAC_MCC_DURATION_END = 13, 501 502 RTW89_MAC_MCC_ADD_ROLE_FAIL = 20, 503 RTW89_MAC_MCC_START_GROUP_FAIL = 21, 504 RTW89_MAC_MCC_STOP_GROUP_FAIL = 22, 505 RTW89_MAC_MCC_DEL_GROUP_FAIL = 23, 506 RTW89_MAC_MCC_RESET_GROUP_FAIL = 24, 507 RTW89_MAC_MCC_SWITCH_CH_FAIL = 25, 508 RTW89_MAC_MCC_TXNULL0_FAIL = 26, 509 RTW89_MAC_MCC_TXNULL1_FAIL = 27, 510 }; 511 512 enum rtw89_mac_mrc_status { 513 RTW89_MAC_MRC_START_SCH_OK = 0, 514 RTW89_MAC_MRC_STOP_SCH_OK = 1, 515 RTW89_MAC_MRC_DEL_SCH_OK = 2, 516 RTW89_MAC_MRC_EMPTY_SCH_FAIL = 16, 517 RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL = 17, 518 RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL = 18, 519 RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL = 19, 520 RTW89_MAC_MRC_ALT_ROLE_FAIL = 20, 521 RTW89_MAC_MRC_ADD_PSTIMER_FAIL = 21, 522 RTW89_MAC_MRC_MALLOC_FAIL = 22, 523 RTW89_MAC_MRC_SWITCH_CH_FAIL = 23, 524 RTW89_MAC_MRC_TXNULL0_FAIL = 24, 525 RTW89_MAC_MRC_PORT_FUNC_EN_FAIL = 25, 526 }; 527 528 struct rtw89_mac_ax_coex { 529 #define RTW89_MAC_AX_COEX_RTK_MODE 0 530 #define RTW89_MAC_AX_COEX_CSR_MODE 1 531 u8 pta_mode; 532 #define RTW89_MAC_AX_COEX_INNER 0 533 #define RTW89_MAC_AX_COEX_OUTPUT 1 534 #define RTW89_MAC_AX_COEX_INPUT 2 535 u8 direction; 536 }; 537 538 struct rtw89_mac_ax_plt { 539 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0) 540 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) 541 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) 542 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3) 543 u8 band; 544 u8 tx; 545 u8 rx; 546 }; 547 548 enum rtw89_mac_bf_rrsc_rate { 549 RTW89_MAC_BF_RRSC_6M = 0, 550 RTW89_MAC_BF_RRSC_9M = 1, 551 RTW89_MAC_BF_RRSC_12M, 552 RTW89_MAC_BF_RRSC_18M, 553 RTW89_MAC_BF_RRSC_24M, 554 RTW89_MAC_BF_RRSC_36M, 555 RTW89_MAC_BF_RRSC_48M, 556 RTW89_MAC_BF_RRSC_54M, 557 RTW89_MAC_BF_RRSC_HT_MSC0, 558 RTW89_MAC_BF_RRSC_HT_MSC1, 559 RTW89_MAC_BF_RRSC_HT_MSC2, 560 RTW89_MAC_BF_RRSC_HT_MSC3, 561 RTW89_MAC_BF_RRSC_HT_MSC4, 562 RTW89_MAC_BF_RRSC_HT_MSC5, 563 RTW89_MAC_BF_RRSC_HT_MSC6, 564 RTW89_MAC_BF_RRSC_HT_MSC7, 565 RTW89_MAC_BF_RRSC_VHT_MSC0, 566 RTW89_MAC_BF_RRSC_VHT_MSC1, 567 RTW89_MAC_BF_RRSC_VHT_MSC2, 568 RTW89_MAC_BF_RRSC_VHT_MSC3, 569 RTW89_MAC_BF_RRSC_VHT_MSC4, 570 RTW89_MAC_BF_RRSC_VHT_MSC5, 571 RTW89_MAC_BF_RRSC_VHT_MSC6, 572 RTW89_MAC_BF_RRSC_VHT_MSC7, 573 RTW89_MAC_BF_RRSC_HE_MSC0, 574 RTW89_MAC_BF_RRSC_HE_MSC1, 575 RTW89_MAC_BF_RRSC_HE_MSC2, 576 RTW89_MAC_BF_RRSC_HE_MSC3, 577 RTW89_MAC_BF_RRSC_HE_MSC4, 578 RTW89_MAC_BF_RRSC_HE_MSC5, 579 RTW89_MAC_BF_RRSC_HE_MSC6, 580 RTW89_MAC_BF_RRSC_HE_MSC7 = 31, 581 RTW89_MAC_BF_RRSC_MAX = 32 582 }; 583 584 #define MAC_REG_POOL_COUNT 10 585 #define ACCESS_CMAC(_addr) \ 586 ({typeof(_addr) __addr = (_addr); \ 587 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) 588 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000 589 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000 590 591 #define PTCL_IDLE_POLL_CNT 10000 592 #define SW_CVR_DUR_US 8 593 #define SW_CVR_CNT 8 594 595 #define DLE_BOUND_UNIT (8 * 1024) 596 #define DLE_WAIT_CNT 2000 597 #define TRXCFG_WAIT_CNT 2000 598 599 #define RTW89_WDE_PG_64 64 600 #define RTW89_WDE_PG_128 128 601 #define RTW89_WDE_PG_256 256 602 603 #define S_AX_WDE_PAGE_SEL_64 0 604 #define S_AX_WDE_PAGE_SEL_128 1 605 #define S_AX_WDE_PAGE_SEL_256 2 606 607 #define RTW89_PLE_PG_64 64 608 #define RTW89_PLE_PG_128 128 609 #define RTW89_PLE_PG_256 256 610 611 #define S_AX_PLE_PAGE_SEL_64 0 612 #define S_AX_PLE_PAGE_SEL_128 1 613 #define S_AX_PLE_PAGE_SEL_256 2 614 615 #define B_CMAC0_MGQ_NORMAL BIT(2) 616 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3) 617 #define B_CMAC0_CPUMGQ BIT(4) 618 #define B_CMAC1_MGQ_NORMAL BIT(10) 619 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11) 620 #define B_CMAC1_CPUMGQ BIT(12) 621 622 #define B_CMAC0_MGQ_NORMAL_BE BIT(2) 623 #define B_CMAC1_MGQ_NORMAL_BE BIT(30) 624 625 #define QEMP_ACQ_GRP_MACID_NUM 8 626 #define QEMP_ACQ_GRP_QSEL_SH 4 627 #define QEMP_ACQ_GRP_QSEL_MASK 0xF 628 629 #define SDIO_LOCAL_BASE_ADDR 0x80000000 630 631 #define PWR_CMD_WRITE 0 632 #define PWR_CMD_POLL 1 633 #define PWR_CMD_DELAY 2 634 #define PWR_CMD_END 3 635 636 #define PWR_INTF_MSK_SDIO BIT(0) 637 #define PWR_INTF_MSK_USB BIT(1) 638 #define PWR_INTF_MSK_PCIE BIT(2) 639 #define PWR_INTF_MSK_ALL 0x7 640 641 #define PWR_BASE_MAC 0 642 #define PWR_BASE_USB 1 643 #define PWR_BASE_PCIE 2 644 #define PWR_BASE_SDIO 3 645 646 #define PWR_CV_MSK_A BIT(0) 647 #define PWR_CV_MSK_B BIT(1) 648 #define PWR_CV_MSK_C BIT(2) 649 #define PWR_CV_MSK_D BIT(3) 650 #define PWR_CV_MSK_E BIT(4) 651 #define PWR_CV_MSK_F BIT(5) 652 #define PWR_CV_MSK_G BIT(6) 653 #define PWR_CV_MSK_TEST BIT(7) 654 #define PWR_CV_MSK_ALL 0xFF 655 656 #define PWR_DELAY_US 0 657 #define PWR_DELAY_MS 1 658 659 /* STA scheduler */ 660 #define SS_MACID_SH 8 661 #define SS_TX_LEN_MSK 0x1FFFFF 662 #define SS_CTRL1_R_TX_LEN 5 663 #define SS_CTRL1_R_NEXT_LINK 20 664 #define SS_LINK_SIZE 256 665 666 /* MAC debug port */ 667 #define TMAC_DBG_SEL_C0 0xA5 668 #define RMAC_DBG_SEL_C0 0xA6 669 #define TRXPTCL_DBG_SEL_C0 0xA7 670 #define TMAC_DBG_SEL_C1 0xB5 671 #define RMAC_DBG_SEL_C1 0xB6 672 #define TRXPTCL_DBG_SEL_C1 0xB7 673 #define FW_PROG_CNTR_DBG_SEL 0xF2 674 #define PCIE_TXDMA_DBG_SEL 0x30 675 #define PCIE_RXDMA_DBG_SEL 0x31 676 #define PCIE_CVT_DBG_SEL 0x32 677 #define PCIE_CXPL_DBG_SEL 0x33 678 #define PCIE_IO_DBG_SEL 0x37 679 #define PCIE_MISC_DBG_SEL 0x38 680 #define PCIE_MISC2_DBG_SEL 0x00 681 #define MAC_DBG_SEL 1 682 #define RMAC_CMAC_DBG_SEL 1 683 684 /* TRXPTCL dbg port sel */ 685 #define TRXPTRL_DBG_SEL_TMAC 0 686 #define TRXPTRL_DBG_SEL_RMAC 1 687 688 struct rtw89_cpuio_ctrl { 689 u16 pkt_num; 690 u16 start_pktid; 691 u16 end_pktid; 692 u8 cmd_type; 693 u8 macid; 694 u8 src_pid; 695 u8 src_qid; 696 u8 dst_pid; 697 u8 dst_qid; 698 u16 pktid; 699 }; 700 701 struct rtw89_mac_dbg_port_info { 702 u32 sel_addr; 703 u8 sel_byte; 704 u32 sel_msk; 705 u32 srt; 706 u32 end; 707 u32 rd_addr; 708 u8 rd_byte; 709 u32 rd_msk; 710 }; 711 712 #define QLNKTBL_ADDR_INFO_SEL BIT(0) 713 #define QLNKTBL_ADDR_INFO_SEL_0 0 714 #define QLNKTBL_ADDR_INFO_SEL_1 1 715 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) 716 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) 717 718 struct rtw89_mac_dle_dfi_ctrl { 719 enum rtw89_mac_dle_ctrl_type type; 720 u32 target; 721 u32 addr; 722 u32 out_data; 723 }; 724 725 struct rtw89_mac_dle_dfi_quota { 726 enum rtw89_mac_dle_ctrl_type dle_type; 727 u32 qtaid; 728 u16 rsv_pgnum; 729 u16 use_pgnum; 730 }; 731 732 struct rtw89_mac_dle_dfi_qempty { 733 enum rtw89_mac_dle_ctrl_type dle_type; 734 u32 grpsel; 735 u32 qempty; 736 }; 737 738 enum rtw89_mac_dle_rsvd_qt_type { 739 DLE_RSVD_QT_MPDU_INFO, 740 DLE_RSVD_QT_B0_CSI, 741 DLE_RSVD_QT_B1_CSI, 742 DLE_RSVD_QT_B0_LMR, 743 DLE_RSVD_QT_B1_LMR, 744 DLE_RSVD_QT_B0_FTM, 745 DLE_RSVD_QT_B1_FTM, 746 }; 747 748 struct rtw89_mac_dle_rsvd_qt_cfg { 749 u16 pktid; 750 u16 pg_num; 751 u32 size; 752 }; 753 754 enum rtw89_mac_error_scenario { 755 RTW89_RXI300_ERROR = 1, 756 RTW89_WCPU_CPU_EXCEPTION = 2, 757 RTW89_WCPU_ASSERTION = 3, 758 }; 759 760 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28) 761 762 /* Define DBG and recovery enum */ 763 enum mac_ax_err_info { 764 /* Get error info */ 765 766 /* L0 */ 767 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, 768 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, 769 MAC_AX_ERR_L0_RESET_DONE = 0x0003, 770 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, 771 772 /* L1 */ 773 MAC_AX_ERR_L1_PREERR_DMAC = 0x999, 774 MAC_AX_ERR_L1_ERR_DMAC = 0x1000, 775 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, 776 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, 777 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, 778 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, 779 780 /* L2 */ 781 /* address hole (master) */ 782 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, 783 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, 784 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, 785 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, 786 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, 787 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, 788 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, 789 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, 790 791 /* AHB bridge timeout (master) */ 792 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, 793 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, 794 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, 795 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, 796 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, 797 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, 798 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, 799 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, 800 801 /* APB_SA bridge timeout (master + slave) */ 802 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, 803 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, 804 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, 805 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, 806 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, 807 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, 808 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, 809 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, 810 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, 811 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, 812 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, 813 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, 814 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, 815 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, 816 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, 817 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, 818 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, 819 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, 820 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, 821 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, 822 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, 823 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, 824 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, 825 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, 826 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, 827 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, 828 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, 829 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, 830 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, 831 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, 832 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, 833 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, 834 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, 835 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, 836 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, 837 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, 838 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, 839 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, 840 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, 841 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, 842 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, 843 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, 844 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, 845 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, 846 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, 847 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, 848 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, 849 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, 850 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, 851 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, 852 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, 853 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, 854 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, 855 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, 856 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, 857 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, 858 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, 859 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, 860 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, 861 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, 862 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, 863 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, 864 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, 865 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, 866 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, 867 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, 868 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, 869 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, 870 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, 871 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, 872 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, 873 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, 874 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, 875 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, 876 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, 877 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, 878 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, 879 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, 880 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, 881 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, 882 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, 883 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, 884 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, 885 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, 886 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, 887 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, 888 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, 889 890 /* APB_BBRF bridge timeout (master) */ 891 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, 892 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, 893 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, 894 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, 895 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, 896 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, 897 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, 898 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, 899 MAC_AX_ERR_L2_RESET_DONE = 0x2400, 900 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599, 901 MAC_AX_ERR_CPU_EXCEPTION = 0x3000, 902 MAC_AX_ERR_ASSERTION = 0x4000, 903 MAC_AX_ERR_RXI300 = 0x5000, 904 MAC_AX_GET_ERR_MAX, 905 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, 906 907 /* set error info */ 908 MAC_AX_ERR_L1_DISABLE_EN = 0x0001, 909 MAC_AX_ERR_L1_RCVY_EN = 0x0002, 910 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, 911 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, 912 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A, 913 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, 914 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, 915 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, 916 MAC_AX_ERR_L0_RCVY_EN = 0x0013, 917 MAC_AX_ERR_L0_RESET_FORCE = 0x0020, 918 MAC_AX_ERR_L0_RESET_FORCE_C1 = 0x0021, 919 MAC_AX_ERR_L1_RESET_FORCE = 0x0022, 920 MAC_AX_SET_ERR_MAX, 921 }; 922 923 struct rtw89_mac_size_set { 924 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie; 925 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0; 926 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2; 927 const struct rtw89_dle_size wde_size0; 928 const struct rtw89_dle_size wde_size1; 929 const struct rtw89_dle_size wde_size0_v1; 930 const struct rtw89_dle_size wde_size4; 931 const struct rtw89_dle_size wde_size4_v1; 932 const struct rtw89_dle_size wde_size6; 933 const struct rtw89_dle_size wde_size7; 934 const struct rtw89_dle_size wde_size9; 935 const struct rtw89_dle_size wde_size16_v1; 936 const struct rtw89_dle_size wde_size17; 937 const struct rtw89_dle_size wde_size18; 938 const struct rtw89_dle_size wde_size18_v1; 939 const struct rtw89_dle_size wde_size19; 940 const struct rtw89_dle_size wde_size23; 941 const struct rtw89_dle_size wde_size25; 942 const struct rtw89_dle_size wde_size31; 943 const struct rtw89_dle_size ple_size0; 944 const struct rtw89_dle_size ple_size1; 945 const struct rtw89_dle_size ple_size0_v1; 946 const struct rtw89_dle_size ple_size3_v1; 947 const struct rtw89_dle_size ple_size4; 948 const struct rtw89_dle_size ple_size6; 949 const struct rtw89_dle_size ple_size8; 950 const struct rtw89_dle_size ple_size9; 951 const struct rtw89_dle_size ple_size17; 952 const struct rtw89_dle_size ple_size18; 953 const struct rtw89_dle_size ple_size19; 954 const struct rtw89_dle_size ple_size20_v1; 955 const struct rtw89_dle_size ple_size22_v1; 956 const struct rtw89_dle_size ple_size32; 957 const struct rtw89_dle_size ple_size33; 958 const struct rtw89_dle_size ple_size34; 959 const struct rtw89_wde_quota wde_qt0; 960 const struct rtw89_wde_quota wde_qt1; 961 const struct rtw89_wde_quota wde_qt0_v1; 962 const struct rtw89_wde_quota wde_qt3; 963 const struct rtw89_wde_quota wde_qt4; 964 const struct rtw89_wde_quota wde_qt6; 965 const struct rtw89_wde_quota wde_qt7; 966 const struct rtw89_wde_quota wde_qt16; 967 const struct rtw89_wde_quota wde_qt17; 968 const struct rtw89_wde_quota wde_qt18; 969 const struct rtw89_wde_quota wde_qt19_v1; 970 const struct rtw89_wde_quota wde_qt23; 971 const struct rtw89_wde_quota wde_qt25; 972 const struct rtw89_wde_quota wde_qt31; 973 const struct rtw89_ple_quota ple_qt0; 974 const struct rtw89_ple_quota ple_qt1; 975 const struct rtw89_ple_quota ple_qt4; 976 const struct rtw89_ple_quota ple_qt5; 977 const struct rtw89_ple_quota ple_qt5_v2; 978 const struct rtw89_ple_quota ple_qt9; 979 const struct rtw89_ple_quota ple_qt13; 980 const struct rtw89_ple_quota ple_qt18; 981 const struct rtw89_ple_quota ple_qt25; 982 const struct rtw89_ple_quota ple_qt26; 983 const struct rtw89_ple_quota ple_qt42; 984 const struct rtw89_ple_quota ple_qt42_v2; 985 const struct rtw89_ple_quota ple_qt43; 986 const struct rtw89_ple_quota ple_qt43_v2; 987 const struct rtw89_ple_quota ple_qt44; 988 const struct rtw89_ple_quota ple_qt45; 989 const struct rtw89_ple_quota ple_qt46; 990 const struct rtw89_ple_quota ple_qt47; 991 const struct rtw89_ple_quota ple_qt57; 992 const struct rtw89_ple_quota ple_qt58; 993 const struct rtw89_ple_quota ple_qt59; 994 const struct rtw89_ple_quota ple_qt72; 995 const struct rtw89_ple_quota ple_qt73; 996 const struct rtw89_ple_quota ple_qt74; 997 const struct rtw89_ple_quota ple_qt75; 998 const struct rtw89_ple_quota ple_qt78; 999 const struct rtw89_ple_quota ple_qt79; 1000 const struct rtw89_ple_quota ple_qt_52a_wow; 1001 const struct rtw89_ple_quota ple_qt_52b_wow; 1002 const struct rtw89_ple_quota ple_qt_52bt_wow; 1003 const struct rtw89_ple_quota ple_qt_51b_wow; 1004 const struct rtw89_rsvd_quota ple_rsvd_qt0; 1005 const struct rtw89_rsvd_quota ple_rsvd_qt1; 1006 const struct rtw89_rsvd_quota ple_rsvd_qt1_v1; 1007 const struct rtw89_rsvd_quota ple_rsvd_qt9; 1008 const struct rtw89_dle_rsvd_size rsvd0_size0; 1009 const struct rtw89_dle_rsvd_size rsvd0_size6; 1010 const struct rtw89_dle_rsvd_size rsvd1_size0; 1011 const struct rtw89_dle_rsvd_size rsvd1_size2; 1012 const struct rtw89_dle_input dle_input3; 1013 const struct rtw89_dle_input dle_input18; 1014 }; 1015 1016 extern const struct rtw89_mac_size_set rtw89_mac_size; 1017 1018 struct rtw89_mac_mu_gid_addr { 1019 u32 position_en[2]; 1020 u32 position[4]; 1021 }; 1022 1023 struct rtw89_mac_gen_def { 1024 u32 band1_offset; 1025 u32 filter_model_addr; 1026 u32 indir_access_addr; 1027 const u32 *mem_base_addrs; 1028 u32 mem_page_size; 1029 u32 rx_fltr; 1030 const struct rtw89_port_reg *port_base; 1031 u32 agg_len_ht; 1032 u32 ps_status; 1033 const struct rtw89_mac_mu_gid_addr *mu_gid; 1034 1035 struct rtw89_reg_def muedca_ctrl; 1036 struct rtw89_reg_def bfee_ctrl; 1037 struct rtw89_reg_def narrow_bw_ru_dis; 1038 struct rtw89_reg_def wow_ctrl; 1039 struct rtw89_reg_def agg_limit; 1040 struct rtw89_reg_def txcnt_limit; 1041 1042 int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band, 1043 enum rtw89_mac_hwmod_sel sel); 1044 int (*sys_init)(struct rtw89_dev *rtwdev); 1045 int (*trx_init)(struct rtw89_dev *rtwdev); 1046 int (*preload_init)(struct rtw89_dev *rtwdev, u8 mac_idx, 1047 enum rtw89_qta_mode mode); 1048 void (*clr_aon_intr)(struct rtw89_dev *rtwdev); 1049 void (*err_imr_ctrl)(struct rtw89_dev *rtwdev, bool en); 1050 int (*mac_func_en)(struct rtw89_dev *rtwdev); 1051 void (*hci_func_en)(struct rtw89_dev *rtwdev); 1052 void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev); 1053 void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable); 1054 void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable); 1055 void (*bf_assoc)(struct rtw89_dev *rtwdev, 1056 struct rtw89_vif_link *rtwvif_link, 1057 struct rtw89_sta_link *rtwsta_link); 1058 1059 int (*typ_fltr_opt)(struct rtw89_dev *rtwdev, 1060 enum rtw89_machdr_frame_type type, 1061 enum rtw89_mac_fwd_target fwd_target, 1062 u8 mac_idx); 1063 int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable); 1064 void (*cfg_phy_rpt)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable); 1065 void (*set_edcca_mode)(struct rtw89_dev *rtwdev, u8 mac_idx, bool normal); 1066 1067 int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg); 1068 int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple); 1069 int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id); 1070 void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en); 1071 void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev); 1072 void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev); 1073 void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev); 1074 void (*wde_quota_cfg)(struct rtw89_dev *rtwdev, 1075 const struct rtw89_wde_quota *min_cfg, 1076 const struct rtw89_wde_quota *max_cfg, 1077 u16 ext_wde_min_qt_wcpu); 1078 void (*ple_quota_cfg)(struct rtw89_dev *rtwdev, 1079 const struct rtw89_ple_quota *min_cfg, 1080 const struct rtw89_ple_quota *max_cfg); 1081 int (*set_cpuio)(struct rtw89_dev *rtwdev, 1082 struct rtw89_cpuio_ctrl *ctrl_para, bool wd); 1083 int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en); 1084 1085 int (*reset_pwr_state)(struct rtw89_dev *rtwdev); 1086 void (*disable_cpu)(struct rtw89_dev *rtwdev); 1087 int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason, 1088 bool dlfw, bool include_bb); 1089 u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type); 1090 int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl); 1091 void (*fwdl_secure_idmem_share_mode)(struct rtw89_dev *rtwdev, u8 mode); 1092 int (*parse_efuse_map)(struct rtw89_dev *rtwdev); 1093 int (*parse_phycap_map)(struct rtw89_dev *rtwdev); 1094 int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle); 1095 int (*efuse_read_fw_secure)(struct rtw89_dev *rtwdev); 1096 int (*efuse_read_ecv)(struct rtw89_dev *rtwdev); 1097 1098 int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); 1099 u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band); 1100 1101 bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev, 1102 enum rtw89_phy_idx phy_idx, 1103 u32 reg_base, u32 *cr); 1104 1105 int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); 1106 int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val); 1107 1108 void (*dump_qta_lost)(struct rtw89_dev *rtwdev); 1109 void (*dump_err_status)(struct rtw89_dev *rtwdev, 1110 enum mac_ax_err_info err); 1111 1112 bool (*is_txq_empty)(struct rtw89_dev *rtwdev); 1113 1114 int (*prep_chan_list)(struct rtw89_dev *rtwdev, 1115 struct rtw89_vif_link *rtwvif_link); 1116 void (*free_chan_list)(struct rtw89_dev *rtwdev); 1117 int (*add_chan_list)(struct rtw89_dev *rtwdev, 1118 struct rtw89_vif_link *rtwvif_link); 1119 int (*add_chan_list_pno)(struct rtw89_dev *rtwdev, 1120 struct rtw89_vif_link *rtwvif_link); 1121 int (*scan_offload)(struct rtw89_dev *rtwdev, 1122 struct rtw89_scan_option *option, 1123 struct rtw89_vif_link *rtwvif_link, 1124 bool wowlan); 1125 1126 int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow); 1127 }; 1128 1129 extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax; 1130 extern const struct rtw89_mac_gen_def rtw89_mac_gen_be; 1131 1132 static inline 1133 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band) 1134 { 1135 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1136 1137 return band == 0 ? reg_base : (reg_base + mac->band1_offset); 1138 } 1139 1140 static inline void 1141 rtw89_write16_idx(struct rtw89_dev *rtwdev, u32 addr, u16 data, u8 band) 1142 { 1143 addr = rtw89_mac_reg_by_idx(rtwdev, addr, band); 1144 1145 rtw89_write16(rtwdev, addr, data); 1146 } 1147 1148 static inline void 1149 rtw89_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data, u8 band) 1150 { 1151 addr = rtw89_mac_reg_by_idx(rtwdev, addr, band); 1152 1153 rtw89_write32_mask(rtwdev, addr, mask, data); 1154 } 1155 1156 static inline 1157 u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx) 1158 { 1159 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx); 1160 } 1161 1162 static inline u32 1163 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base) 1164 { 1165 u32 reg; 1166 1167 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1168 rtwvif_link->mac_idx); 1169 return rtw89_read32(rtwdev, reg); 1170 } 1171 1172 static inline u32 1173 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1174 u32 base, u32 mask) 1175 { 1176 u32 reg; 1177 1178 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1179 rtwvif_link->mac_idx); 1180 return rtw89_read32_mask(rtwdev, reg, mask); 1181 } 1182 1183 static inline void 1184 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base, 1185 u32 data) 1186 { 1187 u32 reg; 1188 1189 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1190 rtwvif_link->mac_idx); 1191 rtw89_write32(rtwdev, reg, data); 1192 } 1193 1194 static inline void 1195 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1196 u32 base, u32 mask, u32 data) 1197 { 1198 u32 reg; 1199 1200 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1201 rtwvif_link->mac_idx); 1202 rtw89_write32_mask(rtwdev, reg, mask, data); 1203 } 1204 1205 static inline void 1206 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1207 u32 base, u32 mask, u16 data) 1208 { 1209 u32 reg; 1210 1211 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1212 rtwvif_link->mac_idx); 1213 rtw89_write16_mask(rtwdev, reg, mask, data); 1214 } 1215 1216 static inline void 1217 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1218 u32 base, u32 bit) 1219 { 1220 u32 reg; 1221 1222 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1223 rtwvif_link->mac_idx); 1224 rtw89_write32_clr(rtwdev, reg, bit); 1225 } 1226 1227 static inline void 1228 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1229 u32 base, u16 bit) 1230 { 1231 u32 reg; 1232 1233 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1234 rtwvif_link->mac_idx); 1235 rtw89_write16_clr(rtwdev, reg, bit); 1236 } 1237 1238 static inline void 1239 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1240 u32 base, u32 bit) 1241 { 1242 u32 reg; 1243 1244 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port, 1245 rtwvif_link->mac_idx); 1246 rtw89_write32_set(rtwdev, reg, bit); 1247 } 1248 1249 int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev); 1250 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); 1251 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb); 1252 int rtw89_mac_preinit(struct rtw89_dev *rtwdev); 1253 int rtw89_mac_init(struct rtw89_dev *rtwdev); 1254 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1255 enum rtw89_qta_mode ext_mode); 1256 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en); 1257 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1258 enum rtw89_qta_mode mode); 1259 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode); 1260 static inline 1261 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, 1262 enum rtw89_mac_hwmod_sel sel) 1263 { 1264 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1265 1266 return mac->check_mac_en(rtwdev, band, sel); 1267 } 1268 1269 static inline void rtw89_mac_clr_aon_intr(struct rtw89_dev *rtwdev) 1270 { 1271 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1272 1273 if (mac->clr_aon_intr) 1274 mac->clr_aon_intr(rtwdev); 1275 } 1276 1277 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); 1278 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); 1279 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl); 1280 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 1281 struct rtw89_mac_dle_dfi_quota *quota); 1282 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev); 1283 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 1284 struct rtw89_mac_dle_dfi_qempty *qempty); 1285 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 1286 enum mac_ax_err_info err); 1287 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif); 1288 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1289 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 1290 struct rtw89_vif_link *rtwvif_link, 1291 struct rtw89_vif_link *rtwvif_src, 1292 u16 offset_tu); 1293 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 1294 u64 *tsf); 1295 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 1296 struct rtw89_vif_link *rtwvif_link, bool en); 1297 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 1298 struct rtw89_vif_link *rtwvif_link); 1299 void rtw89_mac_set_he_tb(struct rtw89_dev *rtwdev, 1300 struct rtw89_vif_link *rtwvif_link); 1301 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1302 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en); 1303 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif); 1304 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); 1305 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); 1306 1307 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev) 1308 { 1309 const struct rtw89_chip_info *chip = rtwdev->chip; 1310 1311 return chip->ops->enable_bb_rf(rtwdev); 1312 } 1313 1314 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev) 1315 { 1316 const struct rtw89_chip_info *chip = rtwdev->chip; 1317 1318 return chip->ops->disable_bb_rf(rtwdev); 1319 } 1320 1321 static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev) 1322 { 1323 int ret; 1324 1325 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 1326 return 0; 1327 1328 ret = rtw89_chip_disable_bb_rf(rtwdev); 1329 if (ret) 1330 return ret; 1331 ret = rtw89_chip_enable_bb_rf(rtwdev); 1332 if (ret) 1333 return ret; 1334 1335 return 0; 1336 } 1337 1338 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); 1339 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); 1340 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 1341 u8 class, u8 func); 1342 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1343 u32 len, u8 class, u8 func); 1344 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); 1345 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 1346 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1347 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 1348 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1349 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, 1350 u32 *tx_en, enum rtw89_sch_tx_sel sel); 1351 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1352 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1353 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 1354 void rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable); 1355 1356 static inline 1357 void rtw89_mac_cfg_phy_rpt(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 1358 { 1359 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1360 1361 if (mac->cfg_phy_rpt) 1362 mac->cfg_phy_rpt(rtwdev, mac_idx, enable); 1363 } 1364 1365 static inline 1366 void rtw89_mac_cfg_phy_rpt_bands(struct rtw89_dev *rtwdev, bool enable) 1367 { 1368 rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_0, enable); 1369 1370 if (!rtwdev->dbcc_en) 1371 return; 1372 1373 rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_1, enable); 1374 } 1375 1376 static inline 1377 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 1378 { 1379 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1380 1381 return mac->cfg_ppdu_status(rtwdev, mac_idx, enable); 1382 } 1383 1384 static inline 1385 int rtw89_mac_cfg_ppdu_status_bands(struct rtw89_dev *rtwdev, bool enable) 1386 { 1387 int ret; 1388 1389 ret = rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, enable); 1390 if (ret) 1391 return ret; 1392 1393 if (!rtwdev->dbcc_en) 1394 return 0; 1395 1396 return rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_1, enable); 1397 } 1398 1399 static inline 1400 void rtw89_mac_set_edcca_mode(struct rtw89_dev *rtwdev, u8 mac_idx, bool normal) 1401 { 1402 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1403 1404 if (!mac->set_edcca_mode) 1405 return; 1406 1407 mac->set_edcca_mode(rtwdev, mac_idx, normal); 1408 } 1409 1410 static inline 1411 void rtw89_mac_set_edcca_mode_bands(struct rtw89_dev *rtwdev, bool normal) 1412 { 1413 rtw89_mac_set_edcca_mode(rtwdev, RTW89_MAC_0, normal); 1414 rtw89_mac_set_edcca_mode(rtwdev, RTW89_MAC_1, normal); 1415 } 1416 1417 void rtw89_mac_set_rx_fltr(struct rtw89_dev *rtwdev, u8 mac_idx, u32 rx_fltr); 1418 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev); 1419 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); 1420 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); 1421 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 1422 const struct rtw89_mac_ax_coex *coex); 1423 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 1424 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1425 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 1426 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1427 int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev, 1428 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1429 int rtw89_mac_cfg_gnt_v3(struct rtw89_dev *rtwdev, 1430 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 1431 1432 static inline 1433 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 1434 { 1435 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1436 1437 return mac->cfg_plt(rtwdev, plt); 1438 } 1439 1440 static inline 1441 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 1442 { 1443 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1444 1445 return mac->get_plt_cnt(rtwdev, band); 1446 } 1447 1448 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); 1449 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); 1450 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); 1451 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); 1452 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); 1453 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl); 1454 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); 1455 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); 1456 1457 static inline 1458 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, 1459 struct rtw89_vif_link *rtwvif_link, 1460 struct rtw89_sta_link *rtwsta_link) 1461 { 1462 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1463 1464 if (mac->bf_assoc) 1465 mac->bf_assoc(rtwdev, rtwvif_link, rtwsta_link); 1466 } 1467 1468 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, 1469 struct rtw89_vif_link *rtwvif_link, 1470 struct rtw89_sta_link *rtwsta_link); 1471 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1472 struct ieee80211_bss_conf *conf); 1473 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 1474 struct rtw89_sta_link *rtwsta_link, 1475 bool disconnect); 1476 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); 1477 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en); 1478 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1479 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 1480 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 1481 struct rtw89_vif_link *rtwvif_link, bool en); 1482 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause); 1483 1484 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 1485 { 1486 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 1487 return; 1488 1489 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) 1490 return; 1491 1492 _rtw89_mac_bf_monitor_track(rtwdev); 1493 } 1494 1495 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, 1496 enum rtw89_phy_idx phy_idx, 1497 u32 reg_base, u32 *val) 1498 { 1499 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1500 u32 cr; 1501 1502 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1503 return -EINVAL; 1504 1505 *val = rtw89_read32(rtwdev, cr); 1506 return 0; 1507 } 1508 1509 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, 1510 enum rtw89_phy_idx phy_idx, 1511 u32 reg_base, u32 val) 1512 { 1513 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1514 u32 cr; 1515 1516 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1517 return -EINVAL; 1518 1519 rtw89_write32(rtwdev, cr, val); 1520 return 0; 1521 } 1522 1523 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, 1524 enum rtw89_phy_idx phy_idx, 1525 u32 reg_base, u32 mask, u32 val) 1526 { 1527 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1528 u32 cr; 1529 1530 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 1531 return -EINVAL; 1532 1533 rtw89_write32_mask(rtwdev, cr, mask, val); 1534 return 0; 1535 } 1536 1537 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev, 1538 bool enable) 1539 { 1540 const struct rtw89_chip_info *chip = rtwdev->chip; 1541 1542 if (enable) 1543 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1544 B_AX_HCI_TXDMA_EN); 1545 else 1546 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1547 B_AX_HCI_TXDMA_EN); 1548 } 1549 1550 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev, 1551 bool enable) 1552 { 1553 const struct rtw89_chip_info *chip = rtwdev->chip; 1554 1555 if (enable) 1556 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1557 B_AX_HCI_RXDMA_EN); 1558 else 1559 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1560 B_AX_HCI_RXDMA_EN); 1561 } 1562 1563 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev, 1564 bool enable) 1565 { 1566 const struct rtw89_chip_info *chip = rtwdev->chip; 1567 1568 if (enable) 1569 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1570 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1571 else 1572 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1573 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1574 } 1575 1576 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev) 1577 { 1578 u32 val; 1579 1580 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, 1581 B_AX_WLMAC_PWR_STE_MASK); 1582 1583 return !!val; 1584 } 1585 1586 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 1587 bool resume, u32 tx_time); 1588 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 1589 u32 *tx_time); 1590 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 1591 struct rtw89_sta_link *rtwsta_link, 1592 bool resume, u8 tx_retry); 1593 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 1594 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry); 1595 1596 enum rtw89_mac_xtal_si_offset { 1597 XTAL0 = 0x0, 1598 XTAL3 = 0x3, 1599 XTAL_SI_XTAL_SC_XI = 0x04, 1600 #define XTAL_SC_XI_MASK GENMASK(7, 0) 1601 XTAL_SI_XTAL_SC_XO = 0x05, 1602 #define XTAL_SC_XO_MASK GENMASK(7, 0) 1603 XTAL_SI_XREF_MODE = 0x0B, 1604 XTAL_SI_PWR_CUT = 0x10, 1605 #define XTAL_SI_SMALL_PWR_CUT BIT(0) 1606 #define XTAL_SI_BIG_PWR_CUT BIT(1) 1607 XTAL_SI_XTAL_DRV = 0x15, 1608 #define XTAL_SI_DRV_LATCH BIT(4) 1609 XTAL_SI_XTAL_PLL = 0x16, 1610 XTAL_SI_XTAL_XMD_2 = 0x24, 1611 #define XTAL_SI_LDO_LPS GENMASK(6, 4) 1612 XTAL_SI_XTAL_XMD_4 = 0x26, 1613 #define XTAL_SI_LPS_CAP GENMASK(3, 0) 1614 XTAL_SI_XREF_RF1 = 0x2D, 1615 XTAL_SI_XREF_RF2 = 0x2E, 1616 XTAL_SI_CV = 0x41, 1617 #define XTAL_SI_ACV_MASK GENMASK(3, 0) 1618 XTAL_SI_LOW_ADDR = 0x62, 1619 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0) 1620 XTAL_SI_CTRL = 0x63, 1621 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6) 1622 #define XTAL_SI_RDY BIT(5) 1623 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0) 1624 XTAL_SI_READ_VAL = 0x7A, 1625 XTAL_SI_WL_RFC_S0 = 0x80, 1626 #define XTAL_SI_RF00S_EN GENMASK(2, 0) 1627 #define XTAL_SI_RF00 BIT(0) 1628 XTAL_SI_WL_RFC_S1 = 0x81, 1629 #define XTAL_SI_RF10S_EN GENMASK(2, 0) 1630 #define XTAL_SI_RF10 BIT(0) 1631 XTAL_SI_ANAPAR_WL = 0x90, 1632 #define XTAL_SI_SRAM2RFC BIT(7) 1633 #define XTAL_SI_GND_SHDN_WL BIT(6) 1634 #define XTAL_SI_SHDN_WL BIT(5) 1635 #define XTAL_SI_RFC2RF BIT(4) 1636 #define XTAL_SI_OFF_EI BIT(3) 1637 #define XTAL_SI_OFF_WEI BIT(2) 1638 #define XTAL_SI_PON_EI BIT(1) 1639 #define XTAL_SI_PON_WEI BIT(0) 1640 XTAL_SI_SRAM_CTRL = 0xA1, 1641 #define XTAL_SI_SRAM_DIS BIT(1) 1642 #define FULL_BIT_MASK GENMASK(7, 0) 1643 XTAL_SI_APBT = 0xD1, 1644 XTAL_SI_PLL = 0xE0, 1645 XTAL_SI_PLL_1 = 0xE1, 1646 XTAL_SI_CHIP_ID_L = 0xFD, 1647 XTAL_SI_CHIP_ID_H = 0xFE, 1648 }; 1649 1650 static inline 1651 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 1652 { 1653 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1654 1655 return mac->write_xtal_si(rtwdev, offset, val, mask); 1656 } 1657 1658 static inline 1659 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 1660 { 1661 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1662 1663 return mac->read_xtal_si(rtwdev, offset, val); 1664 } 1665 1666 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1667 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow); 1668 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 1669 enum rtw89_mac_idx band); 1670 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow); 1671 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1672 bool band1_en); 1673 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1674 enum rtw89_mac_dle_rsvd_qt_type type, 1675 struct rtw89_mac_dle_rsvd_qt_cfg *cfg); 1676 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable); 1677 1678 static inline int rtw89_mac_efuse_read_ecv(struct rtw89_dev *rtwdev) 1679 { 1680 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1681 1682 if (!mac->efuse_read_ecv) 1683 return -ENOENT; 1684 1685 return mac->efuse_read_ecv(rtwdev); 1686 } 1687 1688 static inline 1689 void rtw89_fwdl_secure_idmem_share_mode(struct rtw89_dev *rtwdev, u8 mode) 1690 { 1691 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1692 1693 if (!mac->fwdl_secure_idmem_share_mode) 1694 return; 1695 1696 mac->fwdl_secure_idmem_share_mode(rtwdev, mode); 1697 } 1698 1699 static inline 1700 int rtw89_mac_scan_offload(struct rtw89_dev *rtwdev, 1701 struct rtw89_scan_option *option, 1702 struct rtw89_vif_link *rtwvif_link, 1703 bool wowlan) 1704 { 1705 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1706 int ret; 1707 1708 ret = mac->scan_offload(rtwdev, option, rtwvif_link, wowlan); 1709 1710 if (option->enable) { 1711 /* 1712 * At this point, new scan request is acknowledged by firmware, 1713 * so scan events of previous scan request become obsoleted. 1714 * Purge the queued scan events to prevent interference to 1715 * current new request. 1716 */ 1717 rtw89_fw_c2h_purge_obsoleted_scan_events(rtwdev); 1718 } 1719 1720 return ret; 1721 } 1722 1723 static inline 1724 void rtw89_tx_rpt_init(struct rtw89_dev *rtwdev, 1725 struct rtw89_core_tx_request *tx_req) 1726 { 1727 struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt; 1728 1729 if (!rtwdev->hci.tx_rpt_enabled) 1730 return; 1731 1732 tx_req->desc_info.report = true; 1733 /* firmware maintains a 4-bit sequence number */ 1734 tx_req->desc_info.sn = atomic_inc_return(&tx_rpt->sn) & 1735 RTW89_MAX_TX_RPTS_MASK; 1736 tx_req->desc_info.tx_cnt_lmt_en = true; 1737 tx_req->desc_info.tx_cnt_lmt = 8; 1738 } 1739 1740 static inline 1741 bool rtw89_is_tx_rpt_skb(struct rtw89_dev *rtwdev, struct sk_buff *skb) 1742 { 1743 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 1744 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1745 1746 return rtw89_core_is_tx_wait(rtwdev, skb_data) || 1747 (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS); 1748 } 1749 1750 static inline 1751 void rtw89_tx_rpt_tx_status(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1752 u8 tx_status) 1753 { 1754 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 1755 struct ieee80211_tx_info *info; 1756 1757 if (rtw89_core_tx_wait_complete(rtwdev, skb_data, tx_status)) 1758 return; 1759 1760 info = IEEE80211_SKB_CB(skb); 1761 ieee80211_tx_info_clear_status(info); 1762 1763 if (tx_status == RTW89_TX_DONE) 1764 info->flags |= IEEE80211_TX_STAT_ACK; 1765 else 1766 info->flags &= ~IEEE80211_TX_STAT_ACK; 1767 1768 ieee80211_tx_status_irqsafe(rtwdev->hw, skb); 1769 } 1770 1771 static inline 1772 void rtw89_tx_rpt_skb_add(struct rtw89_dev *rtwdev, struct sk_buff *skb) 1773 { 1774 struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt; 1775 struct rtw89_tx_skb_data *skb_data; 1776 u8 idx; 1777 1778 skb_data = RTW89_TX_SKB_CB(skb); 1779 idx = skb_data->tx_rpt_sn; 1780 1781 scoped_guard(spinlock_irqsave, &tx_rpt->skb_lock) { 1782 /* if skb having the similar seq number is still in the queue, 1783 * this means the queue is overflowed - it isn't normal and 1784 * should indicate firmware doesn't provide TX reports in time; 1785 * report the old skb as dropped, we can't do much more here 1786 */ 1787 if (tx_rpt->skbs[idx]) 1788 rtw89_tx_rpt_tx_status(rtwdev, tx_rpt->skbs[idx], 1789 RTW89_TX_MACID_DROP); 1790 tx_rpt->skbs[idx] = skb; 1791 } 1792 } 1793 1794 static inline 1795 void rtw89_tx_rpt_skbs_purge(struct rtw89_dev *rtwdev) 1796 { 1797 struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt; 1798 struct sk_buff *skbs[RTW89_MAX_TX_RPTS]; 1799 1800 scoped_guard(spinlock_irqsave, &tx_rpt->skb_lock) { 1801 memcpy(skbs, tx_rpt->skbs, sizeof(tx_rpt->skbs)); 1802 memset(tx_rpt->skbs, 0, sizeof(tx_rpt->skbs)); 1803 } 1804 1805 for (int i = 0; i < ARRAY_SIZE(skbs); i++) 1806 if (skbs[i]) 1807 rtw89_tx_rpt_tx_status(rtwdev, skbs[i], 1808 RTW89_TX_MACID_DROP); 1809 } 1810 1811 static inline bool rtw89_mac_chk_preload_allow(struct rtw89_dev *rtwdev) 1812 { 1813 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE) 1814 return false; 1815 1816 if (rtwdev->chip->chip_id == RTL8922D && rtwdev->hal.cid == RTL8922D_CID7090) 1817 return true; 1818 1819 return false; 1820 } 1821 1822 #endif 1823