1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_MAC_H__ 6 #define __RTW89_MAC_H__ 7 8 #include "core.h" 9 10 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000 11 #define ADDR_CAM_ENT_SIZE 0x40 12 #define BSSID_CAM_ENT_SIZE 0x08 13 #define HFC_PAGE_UNIT 64 14 15 enum rtw89_mac_hwmod_sel { 16 RTW89_DMAC_SEL = 0, 17 RTW89_CMAC_SEL = 1, 18 19 RTW89_MAC_INVALID, 20 }; 21 22 enum rtw89_mac_fwd_target { 23 RTW89_FWD_DONT_CARE = 0, 24 RTW89_FWD_TO_HOST = 1, 25 RTW89_FWD_TO_WLAN_CPU = 2 26 }; 27 28 enum rtw89_mac_wd_dma_intvl { 29 RTW89_MAC_WD_DMA_INTVL_0S, 30 RTW89_MAC_WD_DMA_INTVL_256NS, 31 RTW89_MAC_WD_DMA_INTVL_512NS, 32 RTW89_MAC_WD_DMA_INTVL_768NS, 33 RTW89_MAC_WD_DMA_INTVL_1US, 34 RTW89_MAC_WD_DMA_INTVL_1_5US, 35 RTW89_MAC_WD_DMA_INTVL_2US, 36 RTW89_MAC_WD_DMA_INTVL_4US, 37 RTW89_MAC_WD_DMA_INTVL_8US, 38 RTW89_MAC_WD_DMA_INTVL_16US, 39 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE 40 }; 41 42 enum rtw89_mac_multi_tag_num { 43 RTW89_MAC_TAG_NUM_1, 44 RTW89_MAC_TAG_NUM_2, 45 RTW89_MAC_TAG_NUM_3, 46 RTW89_MAC_TAG_NUM_4, 47 RTW89_MAC_TAG_NUM_5, 48 RTW89_MAC_TAG_NUM_6, 49 RTW89_MAC_TAG_NUM_7, 50 RTW89_MAC_TAG_NUM_8, 51 RTW89_MAC_TAG_NUM_DEF = 0xFE 52 }; 53 54 enum rtw89_mac_lbc_tmr { 55 RTW89_MAC_LBC_TMR_8US = 0, 56 RTW89_MAC_LBC_TMR_16US, 57 RTW89_MAC_LBC_TMR_32US, 58 RTW89_MAC_LBC_TMR_64US, 59 RTW89_MAC_LBC_TMR_128US, 60 RTW89_MAC_LBC_TMR_256US, 61 RTW89_MAC_LBC_TMR_512US, 62 RTW89_MAC_LBC_TMR_1MS, 63 RTW89_MAC_LBC_TMR_2MS, 64 RTW89_MAC_LBC_TMR_4MS, 65 RTW89_MAC_LBC_TMR_8MS, 66 RTW89_MAC_LBC_TMR_DEF = 0xFE 67 }; 68 69 enum rtw89_mac_cpuio_op_cmd_type { 70 CPUIO_OP_CMD_GET_1ST_PID = 0, 71 CPUIO_OP_CMD_GET_NEXT_PID = 1, 72 CPUIO_OP_CMD_ENQ_TO_TAIL = 4, 73 CPUIO_OP_CMD_ENQ_TO_HEAD = 5, 74 CPUIO_OP_CMD_DEQ = 8, 75 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, 76 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 77 }; 78 79 enum rtw89_mac_wde_dle_port_id { 80 WDE_DLE_PORT_ID_DISPATCH = 0, 81 WDE_DLE_PORT_ID_PKTIN = 1, 82 WDE_DLE_PORT_ID_CMAC0 = 3, 83 WDE_DLE_PORT_ID_CMAC1 = 4, 84 WDE_DLE_PORT_ID_CPU_IO = 6, 85 WDE_DLE_PORT_ID_WDRLS = 7, 86 WDE_DLE_PORT_ID_END = 8 87 }; 88 89 enum rtw89_mac_wde_dle_queid_wdrls { 90 WDE_DLE_QUEID_TXOK = 0, 91 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, 92 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, 93 WDE_DLE_QUEID_DROP_MACID_DROP = 3, 94 WDE_DLE_QUEID_NO_REPORT = 4 95 }; 96 97 enum rtw89_mac_ple_dle_port_id { 98 PLE_DLE_PORT_ID_DISPATCH = 0, 99 PLE_DLE_PORT_ID_MPDU = 1, 100 PLE_DLE_PORT_ID_SEC = 2, 101 PLE_DLE_PORT_ID_CMAC0 = 3, 102 PLE_DLE_PORT_ID_CMAC1 = 4, 103 PLE_DLE_PORT_ID_WDRLS = 5, 104 PLE_DLE_PORT_ID_CPU_IO = 6, 105 PLE_DLE_PORT_ID_PLRLS = 7, 106 PLE_DLE_PORT_ID_END = 8 107 }; 108 109 enum rtw89_mac_ple_dle_queid_plrls { 110 PLE_DLE_QUEID_NO_REPORT = 0x0 111 }; 112 113 enum rtw89_machdr_frame_type { 114 RTW89_MGNT = 0, 115 RTW89_CTRL = 1, 116 RTW89_DATA = 2, 117 }; 118 119 enum rtw89_mac_dle_dfi_type { 120 DLE_DFI_TYPE_FREEPG = 0, 121 DLE_DFI_TYPE_QUOTA = 1, 122 DLE_DFI_TYPE_PAGELLT = 2, 123 DLE_DFI_TYPE_PKTINFO = 3, 124 DLE_DFI_TYPE_PREPKTLLT = 4, 125 DLE_DFI_TYPE_NXTPKTLLT = 5, 126 DLE_DFI_TYPE_QLNKTBL = 6, 127 DLE_DFI_TYPE_QEMPTY = 7, 128 }; 129 130 enum rtw89_mac_dle_wde_quota_id { 131 WDE_QTAID_HOST_IF = 0, 132 WDE_QTAID_WLAN_CPU = 1, 133 WDE_QTAID_DATA_CPU = 2, 134 WDE_QTAID_PKTIN = 3, 135 WDE_QTAID_CPUIO = 4, 136 }; 137 138 enum rtw89_mac_dle_ple_quota_id { 139 PLE_QTAID_B0_TXPL = 0, 140 PLE_QTAID_B1_TXPL = 1, 141 PLE_QTAID_C2H = 2, 142 PLE_QTAID_H2C = 3, 143 PLE_QTAID_WLAN_CPU = 4, 144 PLE_QTAID_MPDU = 5, 145 PLE_QTAID_CMAC0_RX = 6, 146 PLE_QTAID_CMAC1_RX = 7, 147 PLE_QTAID_CMAC1_BBRPT = 8, 148 PLE_QTAID_WDRLS = 9, 149 PLE_QTAID_CPUIO = 10, 150 }; 151 152 enum rtw89_mac_dle_ctrl_type { 153 DLE_CTRL_TYPE_WDE = 0, 154 DLE_CTRL_TYPE_PLE = 1, 155 DLE_CTRL_TYPE_NUM = 2, 156 }; 157 158 enum rtw89_mac_ax_l0_to_l1_event { 159 MAC_AX_L0_TO_L1_CHIF_IDLE = 0, 160 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, 161 MAC_AX_L0_TO_L1_RLS_PKID = 2, 162 MAC_AX_L0_TO_L1_PTCL_IDLE = 3, 163 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, 164 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, 165 MAC_AX_L0_TO_L1_PCIE_STUCK = 6, 166 MAC_AX_L0_TO_L1_EVENT_MAX = 15, 167 }; 168 169 enum rtw89_mac_dbg_port_sel { 170 /* CMAC 0 related */ 171 RTW89_DBG_PORT_SEL_PTCL_C0 = 0, 172 RTW89_DBG_PORT_SEL_SCH_C0, 173 RTW89_DBG_PORT_SEL_TMAC_C0, 174 RTW89_DBG_PORT_SEL_RMAC_C0, 175 RTW89_DBG_PORT_SEL_RMACST_C0, 176 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, 177 RTW89_DBG_PORT_SEL_TRXPTCL_C0, 178 RTW89_DBG_PORT_SEL_TX_INFOL_C0, 179 RTW89_DBG_PORT_SEL_TX_INFOH_C0, 180 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, 181 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, 182 /* CMAC 1 related */ 183 RTW89_DBG_PORT_SEL_PTCL_C1, 184 RTW89_DBG_PORT_SEL_SCH_C1, 185 RTW89_DBG_PORT_SEL_TMAC_C1, 186 RTW89_DBG_PORT_SEL_RMAC_C1, 187 RTW89_DBG_PORT_SEL_RMACST_C1, 188 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, 189 RTW89_DBG_PORT_SEL_TRXPTCL_C1, 190 RTW89_DBG_PORT_SEL_TX_INFOL_C1, 191 RTW89_DBG_PORT_SEL_TX_INFOH_C1, 192 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, 193 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, 194 /* DLE related */ 195 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, 196 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, 197 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, 198 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, 199 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, 200 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, 201 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, 202 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, 203 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, 204 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, 205 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, 206 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, 207 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, 208 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, 209 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, 210 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, 211 RTW89_DBG_PORT_SEL_PKTINFO, 212 /* PCIE related */ 213 RTW89_DBG_PORT_SEL_PCIE_TXDMA, 214 RTW89_DBG_PORT_SEL_PCIE_RXDMA, 215 RTW89_DBG_PORT_SEL_PCIE_CVT, 216 RTW89_DBG_PORT_SEL_PCIE_CXPL, 217 RTW89_DBG_PORT_SEL_PCIE_IO, 218 RTW89_DBG_PORT_SEL_PCIE_MISC, 219 RTW89_DBG_PORT_SEL_PCIE_MISC2, 220 221 /* keep last */ 222 RTW89_DBG_PORT_SEL_LAST, 223 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, 224 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, 225 }; 226 227 /* SRAM mem dump */ 228 #define R_AX_INDIR_ACCESS_ENTRY 0x40000 229 230 #define AXIDMA_BASE_ADDR 0x18006000 231 #define STA_SCHED_BASE_ADDR 0x18808000 232 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 233 #define SECURITY_CAM_BASE_ADDR 0x18814000 234 #define WOW_CAM_BASE_ADDR 0x18815000 235 #define CMAC_TBL_BASE_ADDR 0x18840000 236 #define ADDR_CAM_BASE_ADDR 0x18850000 237 #define BSSID_CAM_BASE_ADDR 0x18853000 238 #define BA_CAM_BASE_ADDR 0x18854000 239 #define BCN_IE_CAM0_BASE_ADDR 0x18855000 240 #define SHARED_BUF_BASE_ADDR 0x18700000 241 #define DMAC_TBL_BASE_ADDR 0x18800000 242 #define SHCUT_MACHDR_BASE_ADDR 0x18800800 243 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000 244 #define TXD_FIFO_0_BASE_ADDR 0x18856200 245 #define TXD_FIFO_1_BASE_ADDR 0x188A1080 246 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000 247 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 248 249 #define CCTL_INFO_SIZE 32 250 251 enum rtw89_mac_mem_sel { 252 RTW89_MAC_MEM_AXIDMA, 253 RTW89_MAC_MEM_SHARED_BUF, 254 RTW89_MAC_MEM_DMAC_TBL, 255 RTW89_MAC_MEM_SHCUT_MACHDR, 256 RTW89_MAC_MEM_STA_SCHED, 257 RTW89_MAC_MEM_RXPLD_FLTR_CAM, 258 RTW89_MAC_MEM_SECURITY_CAM, 259 RTW89_MAC_MEM_WOW_CAM, 260 RTW89_MAC_MEM_CMAC_TBL, 261 RTW89_MAC_MEM_ADDR_CAM, 262 RTW89_MAC_MEM_BA_CAM, 263 RTW89_MAC_MEM_BCN_IE_CAM0, 264 RTW89_MAC_MEM_BCN_IE_CAM1, 265 RTW89_MAC_MEM_TXD_FIFO_0, 266 RTW89_MAC_MEM_TXD_FIFO_1, 267 RTW89_MAC_MEM_TXDATA_FIFO_0, 268 RTW89_MAC_MEM_TXDATA_FIFO_1, 269 270 /* keep last */ 271 RTW89_MAC_MEM_LAST, 272 RTW89_MAC_MEM_MAX = RTW89_MAC_MEM_LAST, 273 RTW89_MAC_MEM_INVALID = RTW89_MAC_MEM_LAST, 274 }; 275 276 enum rtw89_rpwm_req_pwr_state { 277 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, 278 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, 279 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, 280 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, 281 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, 282 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, 283 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, 284 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, 285 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, 286 }; 287 288 struct rtw89_pwr_cfg { 289 u16 addr; 290 u8 cv_msk; 291 u8 intf_msk; 292 u8 base:4; 293 u8 cmd:4; 294 u8 msk; 295 u8 val; 296 }; 297 298 enum rtw89_mac_c2h_ofld_func { 299 RTW89_MAC_C2H_FUNC_EFUSE_DUMP, 300 RTW89_MAC_C2H_FUNC_READ_RSP, 301 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, 302 RTW89_MAC_C2H_FUNC_BCN_RESEND, 303 RTW89_MAC_C2H_FUNC_MACID_PAUSE, 304 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9, 305 RTW89_MAC_C2H_FUNC_OFLD_MAX, 306 }; 307 308 enum rtw89_mac_c2h_info_func { 309 RTW89_MAC_C2H_FUNC_REC_ACK, 310 RTW89_MAC_C2H_FUNC_DONE_ACK, 311 RTW89_MAC_C2H_FUNC_C2H_LOG, 312 RTW89_MAC_C2H_FUNC_BCN_CNT, 313 RTW89_MAC_C2H_FUNC_INFO_MAX, 314 }; 315 316 enum rtw89_mac_c2h_class { 317 RTW89_MAC_C2H_CLASS_INFO, 318 RTW89_MAC_C2H_CLASS_OFLD, 319 RTW89_MAC_C2H_CLASS_TWT, 320 RTW89_MAC_C2H_CLASS_WOW, 321 RTW89_MAC_C2H_CLASS_MCC, 322 RTW89_MAC_C2H_CLASS_FWDBG, 323 RTW89_MAC_C2H_CLASS_MAX, 324 }; 325 326 struct rtw89_mac_ax_coex { 327 #define RTW89_MAC_AX_COEX_RTK_MODE 0 328 #define RTW89_MAC_AX_COEX_CSR_MODE 1 329 u8 pta_mode; 330 #define RTW89_MAC_AX_COEX_INNER 0 331 #define RTW89_MAC_AX_COEX_OUTPUT 1 332 #define RTW89_MAC_AX_COEX_INPUT 2 333 u8 direction; 334 }; 335 336 struct rtw89_mac_ax_plt { 337 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0) 338 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) 339 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) 340 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3) 341 u8 band; 342 u8 tx; 343 u8 rx; 344 }; 345 346 enum rtw89_mac_bf_rrsc_rate { 347 RTW89_MAC_BF_RRSC_6M = 0, 348 RTW89_MAC_BF_RRSC_9M = 1, 349 RTW89_MAC_BF_RRSC_12M, 350 RTW89_MAC_BF_RRSC_18M, 351 RTW89_MAC_BF_RRSC_24M, 352 RTW89_MAC_BF_RRSC_36M, 353 RTW89_MAC_BF_RRSC_48M, 354 RTW89_MAC_BF_RRSC_54M, 355 RTW89_MAC_BF_RRSC_HT_MSC0, 356 RTW89_MAC_BF_RRSC_HT_MSC1, 357 RTW89_MAC_BF_RRSC_HT_MSC2, 358 RTW89_MAC_BF_RRSC_HT_MSC3, 359 RTW89_MAC_BF_RRSC_HT_MSC4, 360 RTW89_MAC_BF_RRSC_HT_MSC5, 361 RTW89_MAC_BF_RRSC_HT_MSC6, 362 RTW89_MAC_BF_RRSC_HT_MSC7, 363 RTW89_MAC_BF_RRSC_VHT_MSC0, 364 RTW89_MAC_BF_RRSC_VHT_MSC1, 365 RTW89_MAC_BF_RRSC_VHT_MSC2, 366 RTW89_MAC_BF_RRSC_VHT_MSC3, 367 RTW89_MAC_BF_RRSC_VHT_MSC4, 368 RTW89_MAC_BF_RRSC_VHT_MSC5, 369 RTW89_MAC_BF_RRSC_VHT_MSC6, 370 RTW89_MAC_BF_RRSC_VHT_MSC7, 371 RTW89_MAC_BF_RRSC_HE_MSC0, 372 RTW89_MAC_BF_RRSC_HE_MSC1, 373 RTW89_MAC_BF_RRSC_HE_MSC2, 374 RTW89_MAC_BF_RRSC_HE_MSC3, 375 RTW89_MAC_BF_RRSC_HE_MSC4, 376 RTW89_MAC_BF_RRSC_HE_MSC5, 377 RTW89_MAC_BF_RRSC_HE_MSC6, 378 RTW89_MAC_BF_RRSC_HE_MSC7 = 31, 379 RTW89_MAC_BF_RRSC_MAX = 32 380 }; 381 382 #define RTW89_R32_EA 0xEAEAEAEA 383 #define RTW89_R32_DEAD 0xDEADBEEF 384 #define MAC_REG_POOL_COUNT 10 385 #define ACCESS_CMAC(_addr) \ 386 ({typeof(_addr) __addr = (_addr); \ 387 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) 388 389 #define PTCL_IDLE_POLL_CNT 10000 390 #define SW_CVR_DUR_US 8 391 #define SW_CVR_CNT 8 392 393 #define DLE_BOUND_UNIT (8 * 1024) 394 #define DLE_WAIT_CNT 2000 395 #define TRXCFG_WAIT_CNT 2000 396 397 #define RTW89_WDE_PG_64 64 398 #define RTW89_WDE_PG_128 128 399 #define RTW89_WDE_PG_256 256 400 401 #define S_AX_WDE_PAGE_SEL_64 0 402 #define S_AX_WDE_PAGE_SEL_128 1 403 #define S_AX_WDE_PAGE_SEL_256 2 404 405 #define RTW89_PLE_PG_64 64 406 #define RTW89_PLE_PG_128 128 407 #define RTW89_PLE_PG_256 256 408 409 #define S_AX_PLE_PAGE_SEL_64 0 410 #define S_AX_PLE_PAGE_SEL_128 1 411 #define S_AX_PLE_PAGE_SEL_256 2 412 413 #define SDIO_LOCAL_BASE_ADDR 0x80000000 414 415 #define PWR_CMD_WRITE 0 416 #define PWR_CMD_POLL 1 417 #define PWR_CMD_DELAY 2 418 #define PWR_CMD_END 3 419 420 #define PWR_INTF_MSK_SDIO BIT(0) 421 #define PWR_INTF_MSK_USB BIT(1) 422 #define PWR_INTF_MSK_PCIE BIT(2) 423 #define PWR_INTF_MSK_ALL 0x7 424 425 #define PWR_BASE_MAC 0 426 #define PWR_BASE_USB 1 427 #define PWR_BASE_PCIE 2 428 #define PWR_BASE_SDIO 3 429 430 #define PWR_CV_MSK_A BIT(0) 431 #define PWR_CV_MSK_B BIT(1) 432 #define PWR_CV_MSK_C BIT(2) 433 #define PWR_CV_MSK_D BIT(3) 434 #define PWR_CV_MSK_E BIT(4) 435 #define PWR_CV_MSK_F BIT(5) 436 #define PWR_CV_MSK_G BIT(6) 437 #define PWR_CV_MSK_TEST BIT(7) 438 #define PWR_CV_MSK_ALL 0xFF 439 440 #define PWR_DELAY_US 0 441 #define PWR_DELAY_MS 1 442 443 /* STA scheduler */ 444 #define SS_MACID_SH 8 445 #define SS_TX_LEN_MSK 0x1FFFFF 446 #define SS_CTRL1_R_TX_LEN 5 447 #define SS_CTRL1_R_NEXT_LINK 20 448 #define SS_LINK_SIZE 256 449 450 /* MAC debug port */ 451 #define TMAC_DBG_SEL_C0 0xA5 452 #define RMAC_DBG_SEL_C0 0xA6 453 #define TRXPTCL_DBG_SEL_C0 0xA7 454 #define TMAC_DBG_SEL_C1 0xB5 455 #define RMAC_DBG_SEL_C1 0xB6 456 #define TRXPTCL_DBG_SEL_C1 0xB7 457 #define FW_PROG_CNTR_DBG_SEL 0xF2 458 #define PCIE_TXDMA_DBG_SEL 0x30 459 #define PCIE_RXDMA_DBG_SEL 0x31 460 #define PCIE_CVT_DBG_SEL 0x32 461 #define PCIE_CXPL_DBG_SEL 0x33 462 #define PCIE_IO_DBG_SEL 0x37 463 #define PCIE_MISC_DBG_SEL 0x38 464 #define PCIE_MISC2_DBG_SEL 0x00 465 #define MAC_DBG_SEL 1 466 #define RMAC_CMAC_DBG_SEL 1 467 468 /* TRXPTCL dbg port sel */ 469 #define TRXPTRL_DBG_SEL_TMAC 0 470 #define TRXPTRL_DBG_SEL_RMAC 1 471 472 struct rtw89_cpuio_ctrl { 473 u16 pkt_num; 474 u16 start_pktid; 475 u16 end_pktid; 476 u8 cmd_type; 477 u8 macid; 478 u8 src_pid; 479 u8 src_qid; 480 u8 dst_pid; 481 u8 dst_qid; 482 u16 pktid; 483 }; 484 485 struct rtw89_mac_dbg_port_info { 486 u32 sel_addr; 487 u8 sel_byte; 488 u32 sel_msk; 489 u32 srt; 490 u32 end; 491 u32 rd_addr; 492 u8 rd_byte; 493 u32 rd_msk; 494 }; 495 496 #define QLNKTBL_ADDR_INFO_SEL BIT(0) 497 #define QLNKTBL_ADDR_INFO_SEL_0 0 498 #define QLNKTBL_ADDR_INFO_SEL_1 1 499 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) 500 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) 501 502 struct rtw89_mac_dle_dfi_ctrl { 503 enum rtw89_mac_dle_ctrl_type type; 504 u32 target; 505 u32 addr; 506 u32 out_data; 507 }; 508 509 struct rtw89_mac_dle_dfi_quota { 510 enum rtw89_mac_dle_ctrl_type dle_type; 511 u32 qtaid; 512 u16 rsv_pgnum; 513 u16 use_pgnum; 514 }; 515 516 struct rtw89_mac_dle_dfi_qempty { 517 enum rtw89_mac_dle_ctrl_type dle_type; 518 u32 grpsel; 519 u32 qempty; 520 }; 521 522 /* Define DBG and recovery enum */ 523 enum mac_ax_err_info { 524 /* Get error info */ 525 526 /* L0 */ 527 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, 528 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, 529 MAC_AX_ERR_L0_RESET_DONE = 0x0003, 530 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, 531 532 /* L1 */ 533 MAC_AX_ERR_L1_ERR_DMAC = 0x1000, 534 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, 535 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, 536 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, 537 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, 538 539 /* L2 */ 540 /* address hole (master) */ 541 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, 542 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, 543 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, 544 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, 545 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, 546 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, 547 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, 548 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, 549 550 /* AHB bridge timeout (master) */ 551 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, 552 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, 553 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, 554 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, 555 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, 556 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, 557 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, 558 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, 559 560 /* APB_SA bridge timeout (master + slave) */ 561 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, 562 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, 563 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, 564 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, 565 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, 566 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, 567 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, 568 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, 569 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, 570 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, 571 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, 572 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, 573 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, 574 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, 575 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, 576 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, 577 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, 578 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, 579 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, 580 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, 581 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, 582 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, 583 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, 584 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, 585 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, 586 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, 587 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, 588 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, 589 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, 590 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, 591 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, 592 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, 593 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, 594 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, 595 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, 596 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, 597 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, 598 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, 599 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, 600 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, 601 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, 602 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, 603 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, 604 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, 605 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, 606 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, 607 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, 608 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, 609 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, 610 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, 611 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, 612 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, 613 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, 614 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, 615 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, 616 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, 617 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, 618 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, 619 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, 620 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, 621 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, 622 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, 623 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, 624 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, 625 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, 626 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, 627 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, 628 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, 629 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, 630 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, 631 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, 632 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, 633 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, 634 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, 635 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, 636 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, 637 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, 638 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, 639 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, 640 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, 641 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, 642 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, 643 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, 644 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, 645 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, 646 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, 647 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, 648 649 /* APB_BBRF bridge timeout (master) */ 650 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, 651 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, 652 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, 653 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, 654 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, 655 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, 656 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, 657 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, 658 MAC_AX_ERR_L2_RESET_DONE = 0x2400, 659 MAC_AX_ERR_CPU_EXCEPTION = 0x3000, 660 MAC_AX_GET_ERR_MAX, 661 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, 662 663 /* set error info */ 664 MAC_AX_ERR_L1_DISABLE_EN = 0x0001, 665 MAC_AX_ERR_L1_RCVY_EN = 0x0002, 666 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, 667 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, 668 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, 669 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, 670 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, 671 MAC_AX_ERR_L0_RCVY_EN = 0x0013, 672 MAC_AX_SET_ERR_MAX, 673 }; 674 675 extern const struct rtw89_hfc_prec_cfg rtw89_hfc_preccfg_pcie; 676 extern const struct rtw89_dle_size rtw89_wde_size0; 677 extern const struct rtw89_dle_size rtw89_wde_size4; 678 extern const struct rtw89_dle_size rtw89_wde_size18; 679 extern const struct rtw89_dle_size rtw89_wde_size19; 680 extern const struct rtw89_dle_size rtw89_ple_size0; 681 extern const struct rtw89_dle_size rtw89_ple_size4; 682 extern const struct rtw89_dle_size rtw89_ple_size18; 683 extern const struct rtw89_dle_size rtw89_ple_size19; 684 extern const struct rtw89_wde_quota rtw89_wde_qt0; 685 extern const struct rtw89_wde_quota rtw89_wde_qt4; 686 extern const struct rtw89_wde_quota rtw89_wde_qt17; 687 extern const struct rtw89_wde_quota rtw89_wde_qt18; 688 extern const struct rtw89_ple_quota rtw89_ple_qt4; 689 extern const struct rtw89_ple_quota rtw89_ple_qt5; 690 extern const struct rtw89_ple_quota rtw89_ple_qt13; 691 extern const struct rtw89_ple_quota rtw89_ple_qt44; 692 extern const struct rtw89_ple_quota rtw89_ple_qt45; 693 extern const struct rtw89_ple_quota rtw89_ple_qt46; 694 extern const struct rtw89_ple_quota rtw89_ple_qt47; 695 696 static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band) 697 { 698 return band == 0 ? reg_base : (reg_base + 0x2000); 699 } 700 701 static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx) 702 { 703 return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx); 704 } 705 706 static inline u32 707 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 708 u32 base, u32 mask) 709 { 710 u32 reg; 711 712 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 713 return rtw89_read32_mask(rtwdev, reg, mask); 714 } 715 716 static inline void 717 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, 718 u32 data) 719 { 720 u32 reg; 721 722 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 723 rtw89_write32(rtwdev, reg, data); 724 } 725 726 static inline void 727 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 728 u32 base, u32 mask, u32 data) 729 { 730 u32 reg; 731 732 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 733 rtw89_write32_mask(rtwdev, reg, mask, data); 734 } 735 736 static inline void 737 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 738 u32 base, u32 mask, u16 data) 739 { 740 u32 reg; 741 742 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 743 rtw89_write16_mask(rtwdev, reg, mask, data); 744 } 745 746 static inline void 747 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 748 u32 base, u32 bit) 749 { 750 u32 reg; 751 752 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 753 rtw89_write32_clr(rtwdev, reg, bit); 754 } 755 756 static inline void 757 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 758 u32 base, u16 bit) 759 { 760 u32 reg; 761 762 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 763 rtw89_write16_clr(rtwdev, reg, bit); 764 } 765 766 static inline void 767 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 768 u32 base, u32 bit) 769 { 770 u32 reg; 771 772 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 773 rtw89_write32_set(rtwdev, reg, bit); 774 } 775 776 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); 777 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev); 778 int rtw89_mac_init(struct rtw89_dev *rtwdev); 779 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, 780 enum rtw89_mac_hwmod_sel sel); 781 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); 782 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); 783 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 784 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 785 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 786 void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); 787 void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); 788 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); 789 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); 790 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 791 u32 len, u8 class, u8 func); 792 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); 793 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 794 u32 *tx_en, enum rtw89_sch_tx_sel sel); 795 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 796 u32 *tx_en, enum rtw89_sch_tx_sel sel); 797 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 798 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 799 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable); 800 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx); 801 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); 802 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); 803 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 804 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 805 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 806 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 807 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); 808 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band); 809 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); 810 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); 811 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); 812 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); 813 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); 814 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 815 enum rtw89_phy_idx phy_idx, 816 u32 reg_base, u32 *cr); 817 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); 818 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); 819 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 820 struct ieee80211_sta *sta); 821 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 822 struct ieee80211_sta *sta); 823 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 824 struct ieee80211_bss_conf *conf); 825 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 826 struct ieee80211_sta *sta, bool disconnect); 827 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); 828 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 829 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 830 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 831 struct rtw89_vif *rtwvif, bool en); 832 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause); 833 834 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 835 { 836 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) 837 return; 838 839 _rtw89_mac_bf_monitor_track(rtwdev); 840 } 841 842 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, 843 enum rtw89_phy_idx phy_idx, 844 u32 reg_base, u32 *val) 845 { 846 u32 cr; 847 848 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 849 return -EINVAL; 850 851 *val = rtw89_read32(rtwdev, cr); 852 return 0; 853 } 854 855 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, 856 enum rtw89_phy_idx phy_idx, 857 u32 reg_base, u32 val) 858 { 859 u32 cr; 860 861 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 862 return -EINVAL; 863 864 rtw89_write32(rtwdev, cr, val); 865 return 0; 866 } 867 868 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, 869 enum rtw89_phy_idx phy_idx, 870 u32 reg_base, u32 mask, u32 val) 871 { 872 u32 cr; 873 874 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 875 return -EINVAL; 876 877 rtw89_write32_mask(rtwdev, cr, mask, val); 878 return 0; 879 } 880 881 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 882 bool resume, u32 tx_time); 883 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 884 u32 *tx_time); 885 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 886 struct rtw89_sta *rtwsta, 887 bool resume, u8 tx_retry); 888 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 889 struct rtw89_sta *rtwsta, u8 *tx_retry); 890 891 enum rtw89_mac_xtal_si_offset { 892 XTAL_SI_XTAL_SC_XI = 0x04, 893 #define XTAL_SC_XI_MASK GENMASK(7, 0) 894 XTAL_SI_XTAL_SC_XO = 0x05, 895 #define XTAL_SC_XO_MASK GENMASK(7, 0) 896 XTAL_SI_PWR_CUT = 0x10, 897 #define XTAL_SI_SMALL_PWR_CUT BIT(0) 898 #define XTAL_SI_BIG_PWR_CUT BIT(1) 899 XTAL_SI_XTAL_XMD_2 = 0x24, 900 #define XTAL_SI_LDO_LPS GENMASK(6, 4) 901 XTAL_SI_XTAL_XMD_4 = 0x26, 902 #define XTAL_SI_LPS_CAP GENMASK(3, 0) 903 XTAL_SI_CV = 0x41, 904 XTAL_SI_LOW_ADDR = 0x62, 905 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0) 906 XTAL_SI_CTRL = 0x63, 907 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6) 908 #define XTAL_SI_RDY BIT(5) 909 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0) 910 XTAL_SI_READ_VAL = 0x7A, 911 XTAL_SI_WL_RFC_S0 = 0x80, 912 #define XTAL_SI_RF00 BIT(0) 913 XTAL_SI_WL_RFC_S1 = 0x81, 914 #define XTAL_SI_RF10 BIT(0) 915 XTAL_SI_ANAPAR_WL = 0x90, 916 #define XTAL_SI_SRAM2RFC BIT(7) 917 #define XTAL_SI_GND_SHDN_WL BIT(6) 918 #define XTAL_SI_SHDN_WL BIT(5) 919 #define XTAL_SI_RFC2RF BIT(4) 920 #define XTAL_SI_OFF_EI BIT(3) 921 #define XTAL_SI_OFF_WEI BIT(2) 922 #define XTAL_SI_PON_EI BIT(1) 923 #define XTAL_SI_PON_WEI BIT(0) 924 XTAL_SI_SRAM_CTRL = 0xA1, 925 #define FULL_BIT_MASK GENMASK(7, 0) 926 }; 927 928 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); 929 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val); 930 931 #endif 932