1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "util.h" 15 16 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 17 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 18 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 19 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 20 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 21 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 22 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 26 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 29 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 31 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 35 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 36 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 37 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 38 }; 39 40 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 41 u32 val, enum rtw89_mac_mem_sel sel) 42 { 43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44 u32 addr = mac->mem_base_addrs[sel] + offset; 45 46 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 47 rtw89_write32(rtwdev, mac->indir_access_addr, val); 48 } 49 50 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 51 enum rtw89_mac_mem_sel sel) 52 { 53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 54 u32 addr = mac->mem_base_addrs[sel] + offset; 55 56 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 57 return rtw89_read32(rtwdev, mac->indir_access_addr); 58 } 59 60 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 61 enum rtw89_mac_hwmod_sel sel) 62 { 63 u32 val, r_val; 64 65 if (sel == RTW89_DMAC_SEL) { 66 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 67 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 69 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 70 val = B_AX_CMAC_EN; 71 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 72 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 73 val = B_AX_CMAC1_FEN; 74 } else { 75 return -EINVAL; 76 } 77 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 78 (val & r_val) != val) 79 return -EFAULT; 80 81 return 0; 82 } 83 84 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 85 { 86 u8 lte_ctrl; 87 int ret; 88 89 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 90 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 91 if (ret) 92 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 93 94 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 95 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 96 97 return ret; 98 } 99 100 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 101 { 102 u8 lte_ctrl; 103 int ret; 104 105 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 106 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 107 if (ret) 108 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 109 110 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 111 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 112 113 return ret; 114 } 115 116 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 117 { 118 u32 ctrl_reg, data_reg, ctrl_data; 119 u32 val; 120 int ret; 121 122 switch (ctrl->type) { 123 case DLE_CTRL_TYPE_WDE: 124 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 125 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 126 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 127 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 128 B_AX_WDE_DFI_ACTIVE; 129 break; 130 case DLE_CTRL_TYPE_PLE: 131 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 132 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 133 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 134 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 135 B_AX_PLE_DFI_ACTIVE; 136 break; 137 default: 138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 139 return -EINVAL; 140 } 141 142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 143 144 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 145 1, 1000, false, rtwdev, ctrl_reg); 146 if (ret) { 147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 148 ctrl_reg, ctrl_data); 149 return ret; 150 } 151 152 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 153 return 0; 154 } 155 156 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 157 struct rtw89_mac_dle_dfi_quota *quota) 158 { 159 struct rtw89_mac_dle_dfi_ctrl ctrl; 160 int ret; 161 162 ctrl.type = quota->dle_type; 163 ctrl.target = DLE_DFI_TYPE_QUOTA; 164 ctrl.addr = quota->qtaid; 165 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 166 if (ret) { 167 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 168 return ret; 169 } 170 171 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 172 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 173 return 0; 174 } 175 176 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 177 struct rtw89_mac_dle_dfi_qempty *qempty) 178 { 179 struct rtw89_mac_dle_dfi_ctrl ctrl; 180 u32 ret; 181 182 ctrl.type = qempty->dle_type; 183 ctrl.target = DLE_DFI_TYPE_QEMPTY; 184 ctrl.addr = qempty->grpsel; 185 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 186 if (ret) { 187 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 188 return ret; 189 } 190 191 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 192 return 0; 193 } 194 195 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 196 { 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 209 } 210 211 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 212 { 213 struct rtw89_mac_dle_dfi_qempty qempty; 214 struct rtw89_mac_dle_dfi_quota quota; 215 struct rtw89_mac_dle_dfi_ctrl ctrl; 216 u32 val, not_empty, i; 217 int ret; 218 219 qempty.dle_type = DLE_CTRL_TYPE_PLE; 220 qempty.grpsel = 0; 221 qempty.qempty = ~(u32)0; 222 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 223 if (ret) 224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 225 else 226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 227 228 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 229 if (!(not_empty & BIT(0))) 230 continue; 231 ctrl.type = DLE_CTRL_TYPE_PLE; 232 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 233 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 234 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 235 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 236 if (ret) 237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 238 else 239 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 240 u32_get_bits(ctrl.out_data, 241 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 242 } 243 244 quota.dle_type = DLE_CTRL_TYPE_PLE; 245 quota.qtaid = 6; 246 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 247 if (ret) 248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 249 else 250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 251 quota.rsv_pgnum, quota.use_pgnum); 252 253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 255 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 257 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 258 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 259 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 260 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 261 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 262 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 263 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 264 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 265 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 266 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 267 268 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 269 quota.dle_type = DLE_CTRL_TYPE_PLE; 270 quota.qtaid = 7; 271 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 272 if (ret) 273 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 274 else 275 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 276 quota.rsv_pgnum, quota.use_pgnum); 277 278 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 279 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 280 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 282 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 283 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 284 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 285 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 286 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 287 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 288 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 289 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 290 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 291 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 292 } 293 294 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 295 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 298 299 dump_err_status_dispatcher_ax(rtwdev); 300 } 301 302 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 303 enum mac_ax_err_info err) 304 { 305 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 306 u32 dbg, event; 307 308 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 309 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 310 311 switch (event) { 312 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 313 rtw89_info(rtwdev, "quota lost!\n"); 314 mac->dump_qta_lost(rtwdev); 315 break; 316 default: 317 break; 318 } 319 } 320 321 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 322 { 323 const struct rtw89_chip_info *chip = rtwdev->chip; 324 u32 dmac_err; 325 int i, ret; 326 327 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 328 if (ret) { 329 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 330 return; 331 } 332 333 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 334 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 335 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 337 338 if (dmac_err) { 339 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 341 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 343 if (chip->chip_id == RTL8852C) { 344 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 345 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 346 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 348 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 352 } 353 } 354 355 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 356 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 357 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 360 if (chip->chip_id == RTL8852C) 361 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 363 else 364 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 365 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 366 } 367 368 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 369 if (chip->chip_id == RTL8852C) { 370 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 371 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 372 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 374 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 376 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 378 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 380 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 382 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 384 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 386 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 388 389 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 390 B_AX_DBG_SEL0, 0x8B); 391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392 B_AX_DBG_SEL1, 0x8B); 393 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 394 B_AX_SEL_0XC0_MASK, 1); 395 for (i = 0; i < 0x10; i++) { 396 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 397 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 398 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 399 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 400 } 401 } else if (chip->chip_id == RTL8922A) { 402 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 403 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 406 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 407 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 408 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 409 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 410 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 411 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 412 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 413 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 414 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 415 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 416 } else { 417 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 419 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 421 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 423 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 425 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 427 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 429 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 430 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 431 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 432 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 433 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 435 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 437 } 438 } 439 440 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 441 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 442 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 445 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 449 } 450 451 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 452 if (chip->chip_id == RTL8922A) { 453 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 454 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 455 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 456 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 457 } else { 458 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 459 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 462 } 463 } 464 465 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 466 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 468 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 470 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 471 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 472 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 474 } 475 476 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 477 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 478 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 479 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 486 } else { 487 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 491 } 492 } 493 494 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 495 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 501 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 503 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 509 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 510 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 515 if (chip->chip_id == RTL8922A) { 516 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 517 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 520 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 521 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 522 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 524 } else { 525 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 526 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 527 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 529 if (chip->chip_id == RTL8852C) { 530 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 531 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 532 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 533 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 534 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 535 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 536 } else { 537 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 538 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 543 } 544 } 545 } 546 547 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 548 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 549 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 552 } 553 554 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 555 if (chip->chip_id == RTL8922A) { 556 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 557 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 558 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 559 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 560 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 561 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 562 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 563 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 564 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 565 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 566 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 567 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 568 } else { 569 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 570 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 573 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 574 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 577 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 578 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 581 } 582 } 583 584 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 585 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 586 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 587 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 590 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 591 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 594 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 595 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 598 } else { 599 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 600 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 601 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 602 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 605 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 606 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 609 } 610 if (chip->chip_id == RTL8922A) { 611 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 612 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 615 } 616 } 617 618 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 619 if (chip->chip_id == RTL8922A) { 620 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 621 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 624 } else if (chip->chip_id == RTL8852C) { 625 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 626 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 629 } 630 } 631 632 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 633 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 634 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 635 RTW89_MAC_MEM_AXIDMA)); 636 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 637 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 638 RTW89_MAC_MEM_AXIDMA)); 639 } 640 641 if (dmac_err & B_BE_MLO_ERR_INT) { 642 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 643 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 644 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 646 } 647 648 if (dmac_err & B_BE_PLRLS_ERR_INT) { 649 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 650 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 653 } 654 } 655 656 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 657 u8 band) 658 { 659 const struct rtw89_chip_info *chip = rtwdev->chip; 660 u32 offset = 0; 661 u32 cmac_err; 662 int ret; 663 664 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 665 if (ret) { 666 if (band) 667 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 668 else 669 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 670 return; 671 } 672 673 if (band) 674 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 675 676 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 677 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 678 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 679 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 680 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 681 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 682 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 683 684 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 685 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 686 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 689 } 690 691 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 692 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 693 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 694 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 695 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 696 } 697 698 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 699 if (chip->chip_id == RTL8852C) { 700 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 701 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 704 } else { 705 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 706 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 707 } 708 } 709 710 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 711 if (chip->chip_id == RTL8852C) { 712 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 713 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 716 } else { 717 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 718 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 719 } 720 } 721 722 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 723 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 724 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 725 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 726 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 727 } 728 729 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 730 if (chip->chip_id == RTL8852C) { 731 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 732 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 735 } else { 736 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 737 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 738 } 739 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 740 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 741 } 742 743 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 744 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 745 } 746 747 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 748 enum mac_ax_err_info err) 749 { 750 if (err != MAC_AX_ERR_L1_ERR_DMAC && 751 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 752 err != MAC_AX_ERR_L0_ERR_CMAC0 && 753 err != MAC_AX_ERR_L0_ERR_CMAC1 && 754 err != MAC_AX_ERR_RXI300) 755 return; 756 757 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 758 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 759 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 762 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 763 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 764 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 766 767 rtw89_mac_dump_dmac_err_status(rtwdev); 768 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 769 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 770 771 rtwdev->hci.ops->dump_err_status(rtwdev); 772 773 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 774 rtw89_mac_dump_l0_to_l1(rtwdev, err); 775 776 rtw89_info(rtwdev, "<---\n"); 777 } 778 779 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 780 { 781 struct rtw89_ser *ser = &rtwdev->ser; 782 u32 dmac_err, imr, isr; 783 int ret; 784 785 if (rtwdev->chip->chip_id == RTL8852C) { 786 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 787 if (ret) 788 return true; 789 790 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 791 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 792 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 793 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 794 795 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 796 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 797 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 798 return true; 799 } 800 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 801 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 802 return true; 803 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 804 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 805 return true; 806 } 807 } 808 809 return false; 810 } 811 812 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 813 { 814 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 815 u32 err, err_scnr; 816 int ret; 817 818 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 819 false, rtwdev, R_AX_HALT_C2H_CTRL); 820 if (ret) { 821 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 822 return ret; 823 } 824 825 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 826 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 827 828 err_scnr = RTW89_ERROR_SCENARIO(err); 829 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 830 err = MAC_AX_ERR_CPU_EXCEPTION; 831 else if (err_scnr == RTW89_WCPU_ASSERTION) 832 err = MAC_AX_ERR_ASSERTION; 833 else if (err_scnr == RTW89_RXI300_ERROR) 834 err = MAC_AX_ERR_RXI300; 835 836 if (rtw89_mac_suppress_log(rtwdev, err)) 837 return err; 838 839 rtw89_fw_st_dbg_dump(rtwdev); 840 mac->dump_err_status(rtwdev, err); 841 842 return err; 843 } 844 EXPORT_SYMBOL(rtw89_mac_get_err_status); 845 846 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 847 { 848 struct rtw89_ser *ser = &rtwdev->ser; 849 u32 halt; 850 int ret = 0; 851 852 if (err > MAC_AX_SET_ERR_MAX) { 853 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 854 return -EINVAL; 855 } 856 857 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 858 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 859 if (ret) { 860 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 861 return -EFAULT; 862 } 863 864 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 865 866 if (ser->prehandle_l1 && 867 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 868 return 0; 869 870 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 871 872 return 0; 873 } 874 EXPORT_SYMBOL(rtw89_mac_set_err_status); 875 876 static int hfc_reset_param(struct rtw89_dev *rtwdev) 877 { 878 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 879 struct rtw89_hfc_param_ini param_ini = {NULL}; 880 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 881 882 switch (rtwdev->hci.type) { 883 case RTW89_HCI_TYPE_PCIE: 884 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 885 param->en = 0; 886 break; 887 default: 888 return -EINVAL; 889 } 890 891 if (param_ini.pub_cfg) 892 param->pub_cfg = *param_ini.pub_cfg; 893 894 if (param_ini.prec_cfg) 895 param->prec_cfg = *param_ini.prec_cfg; 896 897 if (param_ini.ch_cfg) 898 param->ch_cfg = param_ini.ch_cfg; 899 900 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 901 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 902 param->mode = param_ini.mode; 903 904 return 0; 905 } 906 907 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 908 { 909 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 910 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 911 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 912 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 913 914 if (ch >= RTW89_DMA_CH_NUM) 915 return -EINVAL; 916 917 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 918 ch_cfg[ch].max > pub_cfg->pub_max) 919 return -EINVAL; 920 if (ch_cfg[ch].grp >= grp_num) 921 return -EINVAL; 922 923 return 0; 924 } 925 926 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 927 { 928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 929 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 930 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 931 932 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 933 if (rtwdev->chip->chip_id == RTL8852A) 934 return 0; 935 else 936 return -EFAULT; 937 } 938 939 return 0; 940 } 941 942 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 943 { 944 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 945 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 946 947 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 948 return -EFAULT; 949 950 return 0; 951 } 952 953 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 954 { 955 const struct rtw89_chip_info *chip = rtwdev->chip; 956 const struct rtw89_page_regs *regs = chip->page_regs; 957 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 958 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 959 int ret = 0; 960 u32 val = 0; 961 962 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 963 if (ret) 964 return ret; 965 966 ret = hfc_ch_cfg_chk(rtwdev, ch); 967 if (ret) 968 return ret; 969 970 if (ch > RTW89_DMA_B1HI) 971 return -EINVAL; 972 973 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 974 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 975 (cfg[ch].grp ? B_AX_GRP : 0); 976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 977 978 return 0; 979 } 980 981 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 982 { 983 const struct rtw89_chip_info *chip = rtwdev->chip; 984 const struct rtw89_page_regs *regs = chip->page_regs; 985 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 986 struct rtw89_hfc_ch_info *info = param->ch_info; 987 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 988 u32 val; 989 u32 ret; 990 991 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 992 if (ret) 993 return ret; 994 995 if (ch > RTW89_DMA_H2C) 996 return -EINVAL; 997 998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 999 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1000 if (ch < RTW89_DMA_H2C) 1001 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1002 else 1003 info[ch].used = cfg[ch].min - info[ch].aval; 1004 1005 return 0; 1006 } 1007 1008 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1009 { 1010 const struct rtw89_chip_info *chip = rtwdev->chip; 1011 const struct rtw89_page_regs *regs = chip->page_regs; 1012 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1013 u32 val; 1014 int ret; 1015 1016 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1017 if (ret) 1018 return ret; 1019 1020 ret = hfc_pub_cfg_chk(rtwdev); 1021 if (ret) 1022 return ret; 1023 1024 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1025 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1027 1028 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1030 1031 return 0; 1032 } 1033 1034 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1035 { 1036 const struct rtw89_chip_info *chip = rtwdev->chip; 1037 const struct rtw89_page_regs *regs = chip->page_regs; 1038 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1039 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1040 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1041 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1042 u32 val; 1043 1044 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1045 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1046 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1047 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1048 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1049 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1050 info->pub_aval = 1051 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1052 B_AX_PUB_AVAL_PG_MASK); 1053 info->wp_aval = 1054 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1055 B_AX_WP_AVAL_PG_MASK); 1056 1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1058 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1059 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1060 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1061 prec_cfg->ch011_full_cond = 1062 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1063 prec_cfg->h2c_full_cond = 1064 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1065 prec_cfg->wp_ch07_full_cond = 1066 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1067 prec_cfg->wp_ch811_full_cond = 1068 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1069 1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1071 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1072 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1073 1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1075 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1076 1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1078 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1079 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1080 1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1082 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1083 1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1085 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1086 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1087 } 1088 1089 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1090 { 1091 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1092 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1093 int ret; 1094 1095 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1096 if (ret) 1097 return ret; 1098 1099 mac->hfc_get_mix_info(rtwdev); 1100 1101 ret = hfc_pub_info_chk(rtwdev); 1102 if (param->en && ret) 1103 return ret; 1104 1105 return 0; 1106 } 1107 1108 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1109 { 1110 const struct rtw89_chip_info *chip = rtwdev->chip; 1111 const struct rtw89_page_regs *regs = chip->page_regs; 1112 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1113 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1114 u32 val; 1115 1116 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1118 1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1120 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1121 prec_cfg->h2c_full_cond); 1122 } 1123 1124 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1125 { 1126 const struct rtw89_chip_info *chip = rtwdev->chip; 1127 const struct rtw89_page_regs *regs = chip->page_regs; 1128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1129 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1130 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1131 u32 val; 1132 1133 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1134 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1136 1137 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1139 1140 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1141 B_AX_PREC_PAGE_WP_CH07_MASK) | 1142 u32_encode_bits(prec_cfg->wp_ch811_prec, 1143 B_AX_PREC_PAGE_WP_CH811_MASK); 1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1145 1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1147 param->mode, B_AX_HCI_FC_MODE_MASK); 1148 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1149 B_AX_HCI_FC_WD_FULL_COND_MASK); 1150 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1151 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1152 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1153 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1154 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1155 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1157 } 1158 1159 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1160 { 1161 const struct rtw89_chip_info *chip = rtwdev->chip; 1162 const struct rtw89_page_regs *regs = chip->page_regs; 1163 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1164 u32 val; 1165 1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1167 param->en = en; 1168 param->h2c_en = h2c_en; 1169 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1170 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1171 (val & ~B_AX_HCI_FC_CH12_EN); 1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1173 } 1174 1175 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1176 { 1177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1178 const struct rtw89_chip_info *chip = rtwdev->chip; 1179 u32 dma_ch_mask = chip->dma_ch_mask; 1180 u8 ch; 1181 u32 ret = 0; 1182 1183 if (reset) 1184 ret = hfc_reset_param(rtwdev); 1185 if (ret) 1186 return ret; 1187 1188 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1189 if (ret) 1190 return ret; 1191 1192 mac->hfc_func_en(rtwdev, false, false); 1193 1194 if (!en && h2c_en) { 1195 mac->hfc_h2c_cfg(rtwdev); 1196 mac->hfc_func_en(rtwdev, en, h2c_en); 1197 return ret; 1198 } 1199 1200 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1201 if (dma_ch_mask & BIT(ch)) 1202 continue; 1203 ret = hfc_ch_ctrl(rtwdev, ch); 1204 if (ret) 1205 return ret; 1206 } 1207 1208 ret = hfc_pub_ctrl(rtwdev); 1209 if (ret) 1210 return ret; 1211 1212 mac->hfc_mix_cfg(rtwdev); 1213 if (en || h2c_en) { 1214 mac->hfc_func_en(rtwdev, en, h2c_en); 1215 udelay(10); 1216 } 1217 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1218 if (dma_ch_mask & BIT(ch)) 1219 continue; 1220 ret = hfc_upd_ch_info(rtwdev, ch); 1221 if (ret) 1222 return ret; 1223 } 1224 ret = hfc_upd_mix_info(rtwdev); 1225 1226 return ret; 1227 } 1228 1229 #define PWR_POLL_CNT 2000 1230 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1231 const struct rtw89_pwr_cfg *cfg) 1232 { 1233 u8 val = 0; 1234 int ret; 1235 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1236 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1237 1238 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1239 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1240 1241 if (!ret) 1242 return 0; 1243 1244 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1245 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1247 1248 return -EBUSY; 1249 } 1250 1251 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1252 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1253 { 1254 const struct rtw89_pwr_cfg *cur_cfg; 1255 u32 addr; 1256 u8 val; 1257 1258 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1259 if (!(cur_cfg->intf_msk & intf_msk) || 1260 !(cur_cfg->cv_msk & cv_msk)) 1261 continue; 1262 1263 switch (cur_cfg->cmd) { 1264 case PWR_CMD_WRITE: 1265 addr = cur_cfg->addr; 1266 1267 if (cur_cfg->base == PWR_BASE_SDIO) 1268 addr |= SDIO_LOCAL_BASE_ADDR; 1269 1270 val = rtw89_read8(rtwdev, addr); 1271 val &= ~(cur_cfg->msk); 1272 val |= (cur_cfg->val & cur_cfg->msk); 1273 1274 rtw89_write8(rtwdev, addr, val); 1275 break; 1276 case PWR_CMD_POLL: 1277 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1278 return -EBUSY; 1279 break; 1280 case PWR_CMD_DELAY: 1281 if (cur_cfg->val == PWR_DELAY_US) 1282 udelay(cur_cfg->addr); 1283 else 1284 fsleep(cur_cfg->addr * 1000); 1285 break; 1286 default: 1287 return -EINVAL; 1288 } 1289 } 1290 1291 return 0; 1292 } 1293 1294 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1295 const struct rtw89_pwr_cfg * const *cfg_seq) 1296 { 1297 int ret; 1298 1299 for (; *cfg_seq; cfg_seq++) { 1300 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1301 PWR_INTF_MSK_PCIE, *cfg_seq); 1302 if (ret) 1303 return -EBUSY; 1304 } 1305 1306 return 0; 1307 } 1308 1309 static enum rtw89_rpwm_req_pwr_state 1310 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1311 { 1312 enum rtw89_rpwm_req_pwr_state state; 1313 1314 switch (rtwdev->ps_mode) { 1315 case RTW89_PS_MODE_RFOFF: 1316 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1317 break; 1318 case RTW89_PS_MODE_CLK_GATED: 1319 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1320 break; 1321 case RTW89_PS_MODE_PWR_GATED: 1322 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1323 break; 1324 default: 1325 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1326 break; 1327 } 1328 return state; 1329 } 1330 1331 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1332 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1333 bool notify_wake) 1334 { 1335 u16 request; 1336 1337 spin_lock_bh(&rtwdev->rpwm_lock); 1338 1339 request = rtw89_read16(rtwdev, R_AX_RPWM); 1340 request ^= request | PS_RPWM_TOGGLE; 1341 request |= req_pwr_state; 1342 1343 if (notify_wake) { 1344 request |= PS_RPWM_NOTIFY_WAKE; 1345 } else { 1346 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1347 RPWM_SEQ_NUM_MAX; 1348 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1349 rtwdev->mac.rpwm_seq_num); 1350 1351 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1352 request |= PS_RPWM_ACK; 1353 } 1354 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1355 1356 spin_unlock_bh(&rtwdev->rpwm_lock); 1357 } 1358 1359 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1360 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1361 { 1362 bool request_deep_mode; 1363 bool in_deep_mode; 1364 u8 rpwm_req_num; 1365 u8 cpwm_rsp_seq; 1366 u8 cpwm_seq; 1367 u8 cpwm_status; 1368 1369 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1370 request_deep_mode = true; 1371 else 1372 request_deep_mode = false; 1373 1374 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1375 in_deep_mode = true; 1376 else 1377 in_deep_mode = false; 1378 1379 if (request_deep_mode != in_deep_mode) 1380 return -EPERM; 1381 1382 if (request_deep_mode) 1383 return 0; 1384 1385 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1386 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1387 PS_CPWM_RSP_SEQ_NUM); 1388 1389 if (rpwm_req_num != cpwm_rsp_seq) 1390 return -EPERM; 1391 1392 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1393 CPWM_SEQ_NUM_MAX; 1394 1395 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1396 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1397 return -EPERM; 1398 1399 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1400 if (cpwm_status != req_pwr_state) 1401 return -EPERM; 1402 1403 return 0; 1404 } 1405 1406 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1407 { 1408 enum rtw89_rpwm_req_pwr_state state; 1409 unsigned long delay = enter ? 10 : 150; 1410 int ret; 1411 int i; 1412 1413 if (enter) 1414 state = rtw89_mac_get_req_pwr_state(rtwdev); 1415 else 1416 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1417 1418 for (i = 0; i < RPWM_TRY_CNT; i++) { 1419 rtw89_mac_send_rpwm(rtwdev, state, false); 1420 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1421 !ret, delay, 15000, false, 1422 rtwdev, state); 1423 if (!ret) 1424 break; 1425 1426 if (i == RPWM_TRY_CNT - 1) 1427 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1428 enter ? "entering" : "leaving"); 1429 else 1430 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1431 "%d time firmware failed to ack for %s ps mode\n", 1432 i + 1, enter ? "entering" : "leaving"); 1433 } 1434 } 1435 1436 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1437 { 1438 enum rtw89_rpwm_req_pwr_state state; 1439 1440 state = rtw89_mac_get_req_pwr_state(rtwdev); 1441 rtw89_mac_send_rpwm(rtwdev, state, true); 1442 } 1443 1444 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1445 { 1446 #define PWR_ACT 1 1447 const struct rtw89_chip_info *chip = rtwdev->chip; 1448 const struct rtw89_pwr_cfg * const *cfg_seq; 1449 int (*cfg_func)(struct rtw89_dev *rtwdev); 1450 int ret; 1451 u8 val; 1452 1453 if (on) { 1454 cfg_seq = chip->pwr_on_seq; 1455 cfg_func = chip->ops->pwr_on_func; 1456 } else { 1457 cfg_seq = chip->pwr_off_seq; 1458 cfg_func = chip->ops->pwr_off_func; 1459 } 1460 1461 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1462 __rtw89_leave_ps_mode(rtwdev); 1463 1464 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1465 if (on && val == PWR_ACT) { 1466 rtw89_err(rtwdev, "MAC has already powered on\n"); 1467 return -EBUSY; 1468 } 1469 1470 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1471 if (ret) 1472 return ret; 1473 1474 if (on) { 1475 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1476 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1477 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1478 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1479 } else { 1480 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1481 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1482 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1483 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1484 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1485 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1486 rtw89_set_entity_state(rtwdev, RTW89_PHY_0, false); 1487 rtw89_set_entity_state(rtwdev, RTW89_PHY_1, false); 1488 } 1489 1490 return 0; 1491 #undef PWR_ACT 1492 } 1493 1494 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1495 { 1496 rtw89_mac_power_switch(rtwdev, false); 1497 } 1498 1499 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1500 { 1501 u32 func_en = 0; 1502 u32 ck_en = 0; 1503 u32 c1pc_en = 0; 1504 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1505 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1506 1507 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1508 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1509 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1510 B_AX_CMAC_CRPRT; 1511 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1512 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1513 B_AX_RMAC_CKEN; 1514 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1515 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1516 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1517 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1518 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1519 1520 if (en) { 1521 if (mac_idx == RTW89_MAC_1) { 1522 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1523 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1524 B_AX_R_SYM_ISO_CMAC12PP); 1525 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1526 B_AX_CMAC1_FEN); 1527 } 1528 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1529 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1530 } else { 1531 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1532 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1533 if (mac_idx == RTW89_MAC_1) { 1534 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1535 B_AX_CMAC1_FEN); 1536 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1537 B_AX_R_SYM_ISO_CMAC12PP); 1538 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1539 } 1540 } 1541 1542 return 0; 1543 } 1544 1545 static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1546 { 1547 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1548 u32 val32; 1549 1550 if (chip_id == RTL8852C) 1551 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1552 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1553 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1554 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1555 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1556 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1557 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1558 else 1559 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1560 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1561 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1562 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1563 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1564 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1565 B_AX_DMAC_CRPRT); 1566 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1567 1568 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1569 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1570 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1571 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1572 if (chip_id == RTL8852BT) 1573 val32 |= B_AX_AXIDMA_CLK_EN; 1574 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1575 1576 return 0; 1577 } 1578 1579 static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1580 { 1581 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1582 1583 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 1584 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1585 B_AX_OCP_L1_MASK); 1586 1587 return 0; 1588 } 1589 1590 static int sys_init_ax(struct rtw89_dev *rtwdev) 1591 { 1592 int ret; 1593 1594 ret = dmac_func_en_ax(rtwdev); 1595 if (ret) 1596 return ret; 1597 1598 ret = cmac_func_en_ax(rtwdev, 0, true); 1599 if (ret) 1600 return ret; 1601 1602 ret = chip_func_en_ax(rtwdev); 1603 if (ret) 1604 return ret; 1605 1606 return ret; 1607 } 1608 1609 const struct rtw89_mac_size_set rtw89_mac_size = { 1610 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1611 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0}, 1612 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0}, 1613 /* PCIE 64 */ 1614 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1615 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1616 /* DLFW */ 1617 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1618 .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1619 /* PCIE 64 */ 1620 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1621 /* 8852B PCIE SCC */ 1622 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1623 /* DLFW */ 1624 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1625 /* 8852C DLFW */ 1626 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1627 /* 8852C PCIE SCC */ 1628 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1629 .wde_size23 = {RTW89_WDE_PG_64, 1022, 2,}, 1630 /* PCIE */ 1631 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1632 .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1633 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1634 /* DLFW */ 1635 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1636 /* PCIE 64 */ 1637 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1638 /* DLFW */ 1639 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1640 .ple_size9 = {RTW89_PLE_PG_128, 2288, 16,}, 1641 /* 8852C DLFW */ 1642 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1643 /* 8852C PCIE SCC */ 1644 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1645 /* PCIE 64 */ 1646 .wde_qt0 = {3792, 196, 0, 107,}, 1647 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1648 /* DLFW */ 1649 .wde_qt4 = {0, 0, 0, 0,}, 1650 /* PCIE 64 */ 1651 .wde_qt6 = {448, 48, 0, 16,}, 1652 /* 8852B PCIE SCC */ 1653 .wde_qt7 = {446, 48, 0, 16,}, 1654 /* 8852C DLFW */ 1655 .wde_qt17 = {0, 0, 0, 0,}, 1656 /* 8852C PCIE SCC */ 1657 .wde_qt18 = {3228, 60, 0, 40,}, 1658 .wde_qt23 = {958, 48, 0, 16,}, 1659 .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 1660 .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1661 /* PCIE SCC */ 1662 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1663 /* PCIE SCC */ 1664 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1665 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1666 /* DLFW */ 1667 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1668 /* PCIE 64 */ 1669 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1670 /* DLFW 52C */ 1671 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1672 /* DLFW 52C */ 1673 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1674 /* 8852C PCIE SCC */ 1675 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1676 /* 8852C PCIE SCC */ 1677 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1678 .ple_qt57 = {147, 0, 16, 20, 13, 13, 178, 0, 32, 14, 8, 0,}, 1679 /* PCIE 64 */ 1680 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1681 .ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,}, 1682 /* 8852A PCIE WOW */ 1683 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1684 /* 8852B PCIE WOW */ 1685 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1686 /* 8852BT PCIE WOW */ 1687 .ple_qt_52bt_wow = {147, 0, 32, 20, 1860, 13, 1929, 0, 1879, 14, 24, 0,}, 1688 /* 8851B PCIE WOW */ 1689 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1690 .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1691 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1692 .rsvd0_size0 = {212992, 0,}, 1693 .rsvd1_size0 = {587776, 2048,}, 1694 }; 1695 EXPORT_SYMBOL(rtw89_mac_size); 1696 1697 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1698 enum rtw89_qta_mode mode) 1699 { 1700 struct rtw89_mac_info *mac = &rtwdev->mac; 1701 const struct rtw89_dle_mem *cfg; 1702 1703 cfg = &rtwdev->chip->dle_mem[mode]; 1704 if (!cfg) 1705 return NULL; 1706 1707 if (cfg->mode != mode) { 1708 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1709 return NULL; 1710 } 1711 1712 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1713 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1714 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1715 mac->dle_info.qta_mode = mode; 1716 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1717 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1718 1719 return cfg; 1720 } 1721 1722 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1723 enum rtw89_mac_dle_rsvd_qt_type type, 1724 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1725 { 1726 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1727 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1728 1729 switch (type) { 1730 case DLE_RSVD_QT_MPDU_INFO: 1731 cfg->pktid = dle_info->ple_free_pg; 1732 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1733 break; 1734 case DLE_RSVD_QT_B0_CSI: 1735 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1736 cfg->pg_num = rsvd_qt->b0_csi; 1737 break; 1738 case DLE_RSVD_QT_B1_CSI: 1739 cfg->pktid = dle_info->ple_free_pg + 1740 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1741 cfg->pg_num = rsvd_qt->b1_csi; 1742 break; 1743 case DLE_RSVD_QT_B0_LMR: 1744 cfg->pktid = dle_info->ple_free_pg + 1745 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1746 cfg->pg_num = rsvd_qt->b0_lmr; 1747 break; 1748 case DLE_RSVD_QT_B1_LMR: 1749 cfg->pktid = dle_info->ple_free_pg + 1750 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1751 rsvd_qt->b0_lmr; 1752 cfg->pg_num = rsvd_qt->b1_lmr; 1753 break; 1754 case DLE_RSVD_QT_B0_FTM: 1755 cfg->pktid = dle_info->ple_free_pg + 1756 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1757 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1758 cfg->pg_num = rsvd_qt->b0_ftm; 1759 break; 1760 case DLE_RSVD_QT_B1_FTM: 1761 cfg->pktid = dle_info->ple_free_pg + 1762 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1763 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1764 cfg->pg_num = rsvd_qt->b1_ftm; 1765 break; 1766 default: 1767 return -EINVAL; 1768 } 1769 1770 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1771 1772 return 0; 1773 } 1774 1775 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1776 { 1777 struct rtw89_mac_dle_dfi_qempty qempty; 1778 u32 grpnum, qtmp, val32, msk32; 1779 int i, j, ret; 1780 1781 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1782 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1783 1784 for (i = 0; i < grpnum; i++) { 1785 qempty.grpsel = i; 1786 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1787 if (ret) { 1788 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1789 return false; 1790 } 1791 qtmp = qempty.qempty; 1792 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1793 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 1794 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1795 return false; 1796 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1797 } 1798 } 1799 1800 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1801 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1802 if (ret) { 1803 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1804 return false; 1805 } 1806 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1807 if ((qempty.qempty & msk32) != msk32) 1808 return false; 1809 1810 if (rtwdev->dbcc_en) { 1811 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1812 if ((qempty.qempty & msk32) != msk32) 1813 return false; 1814 } 1815 1816 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1817 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1818 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1819 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1820 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1821 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1822 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1823 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1824 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1825 1826 return (val32 & msk32) == msk32; 1827 } 1828 1829 static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1830 { 1831 const struct rtw89_dle_size *wde = cfg->wde_size; 1832 const struct rtw89_dle_size *ple = cfg->ple_size; 1833 u32 used; 1834 1835 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1836 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1837 1838 if (cfg->rsvd0_size && cfg->rsvd1_size) { 1839 used += cfg->rsvd0_size->size; 1840 used += cfg->rsvd1_size->size; 1841 } 1842 1843 return used; 1844 } 1845 1846 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1847 enum rtw89_qta_mode mode) 1848 { 1849 u32 size = rtwdev->chip->fifo_size; 1850 1851 if (mode == RTW89_QTA_SCC) 1852 size -= rtwdev->chip->dle_scc_rsvd_size; 1853 1854 return size; 1855 } 1856 1857 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 1858 { 1859 if (enable) 1860 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1861 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1862 else 1863 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1864 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1865 } 1866 1867 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 1868 { 1869 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1870 1871 if (enable) { 1872 if (rtwdev->chip->chip_id == RTL8851B) 1873 val |= B_AX_AXIDMA_CLK_EN; 1874 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1875 } else { 1876 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1877 } 1878 } 1879 1880 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1881 { 1882 const struct rtw89_dle_size *size_cfg; 1883 u32 val; 1884 u8 bound = 0; 1885 1886 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1887 size_cfg = cfg->wde_size; 1888 1889 switch (size_cfg->pge_size) { 1890 default: 1891 case RTW89_WDE_PG_64: 1892 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1893 B_AX_WDE_PAGE_SEL_MASK); 1894 break; 1895 case RTW89_WDE_PG_128: 1896 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1897 B_AX_WDE_PAGE_SEL_MASK); 1898 break; 1899 case RTW89_WDE_PG_256: 1900 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1901 return -EINVAL; 1902 } 1903 1904 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1905 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1906 B_AX_WDE_FREE_PAGE_NUM_MASK); 1907 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1908 1909 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1910 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1911 * size_cfg->pge_size / DLE_BOUND_UNIT; 1912 size_cfg = cfg->ple_size; 1913 1914 switch (size_cfg->pge_size) { 1915 default: 1916 case RTW89_PLE_PG_64: 1917 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1918 return -EINVAL; 1919 case RTW89_PLE_PG_128: 1920 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1921 B_AX_PLE_PAGE_SEL_MASK); 1922 break; 1923 case RTW89_PLE_PG_256: 1924 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1925 B_AX_PLE_PAGE_SEL_MASK); 1926 break; 1927 } 1928 1929 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1930 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1931 B_AX_PLE_FREE_PAGE_NUM_MASK); 1932 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1933 1934 return 0; 1935 } 1936 1937 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 1938 { 1939 u32 reg, mask; 1940 u32 ini; 1941 1942 if (wde_or_ple) { 1943 reg = R_AX_WDE_INI_STATUS; 1944 mask = WDE_MGN_INI_RDY; 1945 } else { 1946 reg = R_AX_PLE_INI_STATUS; 1947 mask = PLE_MGN_INI_RDY; 1948 } 1949 1950 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 1951 2000, false, rtwdev, reg); 1952 } 1953 1954 #define INVALID_QT_WCPU U16_MAX 1955 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1956 do { \ 1957 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1958 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1959 rtw89_write32(rtwdev, \ 1960 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1961 val); \ 1962 } while (0) 1963 #define SET_QUOTA(_x, _module, _idx) \ 1964 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1965 1966 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 1967 const struct rtw89_wde_quota *min_cfg, 1968 const struct rtw89_wde_quota *max_cfg, 1969 u16 ext_wde_min_qt_wcpu) 1970 { 1971 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1972 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1973 u32 val; 1974 1975 SET_QUOTA(hif, WDE, 0); 1976 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1977 SET_QUOTA(pkt_in, WDE, 3); 1978 SET_QUOTA(cpu_io, WDE, 4); 1979 } 1980 1981 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 1982 const struct rtw89_ple_quota *min_cfg, 1983 const struct rtw89_ple_quota *max_cfg) 1984 { 1985 u32 val; 1986 1987 SET_QUOTA(cma0_tx, PLE, 0); 1988 SET_QUOTA(cma1_tx, PLE, 1); 1989 SET_QUOTA(c2h, PLE, 2); 1990 SET_QUOTA(h2c, PLE, 3); 1991 SET_QUOTA(wcpu, PLE, 4); 1992 SET_QUOTA(mpdu_proc, PLE, 5); 1993 SET_QUOTA(cma0_dma, PLE, 6); 1994 SET_QUOTA(cma1_dma, PLE, 7); 1995 SET_QUOTA(bb_rpt, PLE, 8); 1996 SET_QUOTA(wd_rel, PLE, 9); 1997 SET_QUOTA(cpu_io, PLE, 10); 1998 if (rtwdev->chip->chip_id == RTL8852C) 1999 SET_QUOTA(tx_rpt, PLE, 11); 2000 } 2001 2002 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 2003 { 2004 const struct rtw89_ple_quota *min_cfg, *max_cfg; 2005 const struct rtw89_dle_mem *cfg; 2006 u32 val; 2007 2008 if (rtwdev->chip->chip_id == RTL8852C) 2009 return 0; 2010 2011 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2012 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2013 return -EINVAL; 2014 } 2015 2016 if (wow) 2017 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2018 else 2019 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2020 if (!cfg) { 2021 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2022 return -EINVAL; 2023 } 2024 2025 min_cfg = cfg->ple_min_qt; 2026 max_cfg = cfg->ple_max_qt; 2027 SET_QUOTA(cma0_dma, PLE, 6); 2028 SET_QUOTA(cma1_dma, PLE, 7); 2029 2030 return 0; 2031 } 2032 #undef SET_QUOTA 2033 2034 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2035 { 2036 const struct rtw89_chip_info *chip = rtwdev->chip; 2037 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2038 2039 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2040 return; 2041 2042 /* 8852C enable B_AX_UC_MGNT_DEC by default */ 2043 if (chip->chip_id == RTL8852C) 2044 msk32 = B_AX_BMC_MGNT_DEC; 2045 2046 if (enable) 2047 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2048 else 2049 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2050 } 2051 2052 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2053 const struct rtw89_dle_mem *cfg, 2054 u16 ext_wde_min_qt_wcpu) 2055 { 2056 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2057 2058 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2059 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2060 } 2061 2062 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2063 enum rtw89_qta_mode ext_mode) 2064 { 2065 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2066 const struct rtw89_dle_mem *cfg, *ext_cfg; 2067 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2068 int ret; 2069 2070 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2071 if (ret) 2072 return ret; 2073 2074 cfg = get_dle_mem_cfg(rtwdev, mode); 2075 if (!cfg) { 2076 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2077 ret = -EINVAL; 2078 goto error; 2079 } 2080 2081 if (mode == RTW89_QTA_DLFW) { 2082 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2083 if (!ext_cfg) { 2084 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2085 ext_mode); 2086 ret = -EINVAL; 2087 goto error; 2088 } 2089 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2090 } 2091 2092 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2093 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2094 ret = -EINVAL; 2095 goto error; 2096 } 2097 2098 mac->dle_func_en(rtwdev, false); 2099 mac->dle_clk_en(rtwdev, true); 2100 2101 ret = mac->dle_mix_cfg(rtwdev, cfg); 2102 if (ret) { 2103 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2104 goto error; 2105 } 2106 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2107 2108 mac->dle_func_en(rtwdev, true); 2109 2110 ret = mac->chk_dle_rdy(rtwdev, true); 2111 if (ret) { 2112 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2113 return ret; 2114 } 2115 2116 ret = mac->chk_dle_rdy(rtwdev, false); 2117 if (ret) { 2118 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2119 return ret; 2120 } 2121 2122 return 0; 2123 error: 2124 mac->dle_func_en(rtwdev, false); 2125 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2126 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2127 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2128 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2129 2130 return ret; 2131 } 2132 2133 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2134 enum rtw89_qta_mode mode) 2135 { 2136 u32 reg, max_preld_size, min_rsvd_size; 2137 2138 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2139 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2140 reg = mac_idx == RTW89_MAC_0 ? 2141 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2142 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2143 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2144 2145 min_rsvd_size = PRELD_AMSDU_SIZE; 2146 reg = mac_idx == RTW89_MAC_0 ? 2147 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2148 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2149 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2150 2151 return 0; 2152 } 2153 2154 static bool is_qta_poh(struct rtw89_dev *rtwdev) 2155 { 2156 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2157 } 2158 2159 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2160 enum rtw89_qta_mode mode) 2161 { 2162 const struct rtw89_chip_info *chip = rtwdev->chip; 2163 2164 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) || 2165 !is_qta_poh(rtwdev)) 2166 return 0; 2167 2168 return preload_init_set(rtwdev, mac_idx, mode); 2169 } 2170 2171 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2172 { 2173 u32 msk32; 2174 u32 val32; 2175 2176 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2177 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2178 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2179 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2180 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2181 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2182 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2183 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2184 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2185 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2186 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2187 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2188 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2189 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2190 2191 if ((val32 & msk32) == msk32) 2192 return true; 2193 2194 return false; 2195 } 2196 2197 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2198 { 2199 const struct rtw89_chip_info *chip = rtwdev->chip; 2200 2201 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2202 return; 2203 2204 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2205 SS2F_PATH_WLCPU); 2206 } 2207 2208 static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2209 { 2210 u32 p_val; 2211 u8 val; 2212 int ret; 2213 2214 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2215 if (ret) 2216 return ret; 2217 2218 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2219 val |= B_AX_SS_EN; 2220 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2221 2222 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2223 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2224 if (ret) { 2225 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2226 return ret; 2227 } 2228 2229 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2230 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2231 2232 _patch_ss2f_path(rtwdev); 2233 2234 return 0; 2235 } 2236 2237 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2238 { 2239 int ret; 2240 2241 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2242 if (ret) 2243 return ret; 2244 2245 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2246 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2247 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2248 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2249 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2250 2251 return 0; 2252 } 2253 2254 static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2255 { 2256 const struct rtw89_chip_info *chip = rtwdev->chip; 2257 u32 val = 0; 2258 int ret; 2259 2260 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2261 if (ret) 2262 return ret; 2263 2264 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2265 /* init clock */ 2266 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2267 /* init TX encryption */ 2268 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2269 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2270 if (chip->chip_id == RTL8852C) 2271 val |= B_AX_UC_MGNT_DEC; 2272 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2273 chip->chip_id == RTL8851B) 2274 val &= ~B_AX_TX_PARTIAL_MODE; 2275 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2276 2277 /* init MIC ICV append */ 2278 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2279 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2280 2281 /* option init */ 2282 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2283 2284 if (chip->chip_id == RTL8852C) 2285 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2286 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2287 2288 return 0; 2289 } 2290 2291 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2292 { 2293 int ret; 2294 2295 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2296 if (ret) { 2297 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2298 return ret; 2299 } 2300 2301 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2302 if (ret) { 2303 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2304 return ret; 2305 } 2306 2307 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2308 if (ret) { 2309 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2310 return ret; 2311 } 2312 2313 ret = sta_sch_init_ax(rtwdev); 2314 if (ret) { 2315 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2316 return ret; 2317 } 2318 2319 ret = mpdu_proc_init_ax(rtwdev); 2320 if (ret) { 2321 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2322 return ret; 2323 } 2324 2325 ret = sec_eng_init_ax(rtwdev); 2326 if (ret) { 2327 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2328 return ret; 2329 } 2330 2331 return ret; 2332 } 2333 2334 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2335 { 2336 u32 val, reg; 2337 u16 p_val; 2338 int ret; 2339 2340 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2341 if (ret) 2342 return ret; 2343 2344 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2345 2346 val = rtw89_read32(rtwdev, reg); 2347 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2348 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2349 rtw89_write32(rtwdev, reg, val); 2350 2351 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2352 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2353 if (ret) { 2354 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2355 return ret; 2356 } 2357 2358 return 0; 2359 } 2360 2361 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2362 { 2363 u32 ret; 2364 u32 reg; 2365 u32 val; 2366 2367 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2368 if (ret) 2369 return ret; 2370 2371 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2372 if (rtwdev->chip->chip_id == RTL8852C) 2373 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2374 SIFS_MACTXEN_T1_V1); 2375 else 2376 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2377 SIFS_MACTXEN_T1); 2378 2379 if (rtw89_is_rtl885xb(rtwdev)) { 2380 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2381 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2382 } 2383 2384 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2385 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2386 2387 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2388 if (rtwdev->chip->chip_id == RTL8852C) { 2389 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2390 B_AX_TX_PARTIAL_MODE); 2391 if (!val) 2392 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2393 SCH_PREBKF_24US); 2394 } else { 2395 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2396 SCH_PREBKF_24US); 2397 } 2398 2399 return 0; 2400 } 2401 2402 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2403 enum rtw89_machdr_frame_type type, 2404 enum rtw89_mac_fwd_target fwd_target, 2405 u8 mac_idx) 2406 { 2407 u32 reg; 2408 u32 val; 2409 2410 switch (fwd_target) { 2411 case RTW89_FWD_DONT_CARE: 2412 val = RX_FLTR_FRAME_DROP; 2413 break; 2414 case RTW89_FWD_TO_HOST: 2415 val = RX_FLTR_FRAME_TO_HOST; 2416 break; 2417 case RTW89_FWD_TO_WLAN_CPU: 2418 val = RX_FLTR_FRAME_TO_WLCPU; 2419 break; 2420 default: 2421 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2422 return -EINVAL; 2423 } 2424 2425 switch (type) { 2426 case RTW89_MGNT: 2427 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2428 break; 2429 case RTW89_CTRL: 2430 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2431 break; 2432 case RTW89_DATA: 2433 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2434 break; 2435 default: 2436 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2437 return -EINVAL; 2438 } 2439 rtw89_write32(rtwdev, reg, val); 2440 2441 return 0; 2442 } 2443 2444 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2445 { 2446 int ret, i; 2447 u32 mac_ftlr, plcp_ftlr; 2448 2449 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2450 if (ret) 2451 return ret; 2452 2453 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2454 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2455 mac_idx); 2456 if (ret) 2457 return ret; 2458 } 2459 mac_ftlr = rtwdev->hal.rx_fltr; 2460 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2461 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2462 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2463 B_AX_HE_SIGB_CRC_CHK; 2464 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2465 mac_ftlr); 2466 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2467 plcp_ftlr); 2468 2469 return 0; 2470 } 2471 2472 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2473 { 2474 u32 reg, val32; 2475 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2476 2477 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2478 B_AX_RSP_CHK_BASIC_NAV; 2479 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2480 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2481 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2482 2483 switch (rtwdev->chip->chip_id) { 2484 case RTL8852A: 2485 case RTL8852B: 2486 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2487 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2488 rtw89_write32(rtwdev, reg, val32); 2489 2490 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2491 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2492 rtw89_write32(rtwdev, reg, val32); 2493 break; 2494 default: 2495 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2496 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2497 rtw89_write32(rtwdev, reg, val32); 2498 2499 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2500 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2501 rtw89_write32(rtwdev, reg, val32); 2502 break; 2503 } 2504 } 2505 2506 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2507 { 2508 u32 val, reg; 2509 int ret; 2510 2511 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2512 if (ret) 2513 return ret; 2514 2515 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2516 val = rtw89_read32(rtwdev, reg); 2517 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2518 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2519 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2520 B_AX_CTN_CHK_INTRA_NAV | 2521 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2522 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2523 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2524 B_AX_CTN_CHK_CCA_P20); 2525 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2526 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2527 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2528 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2529 B_AX_SIFS_CHK_EDCCA); 2530 2531 rtw89_write32(rtwdev, reg, val); 2532 2533 _patch_dis_resp_chk(rtwdev, mac_idx); 2534 2535 return 0; 2536 } 2537 2538 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2539 { 2540 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2541 B_AX_WMAC_TF_UP_NAV_EN | 2542 B_AX_WMAC_NAV_UPPER_EN); 2543 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2544 2545 return 0; 2546 } 2547 2548 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2549 { 2550 u32 reg; 2551 int ret; 2552 2553 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2554 if (ret) 2555 return ret; 2556 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2557 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2558 2559 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2560 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2561 2562 return 0; 2563 } 2564 2565 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2566 { 2567 u32 reg; 2568 int ret; 2569 2570 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2571 if (ret) 2572 return ret; 2573 2574 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2575 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2576 2577 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2578 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2579 2580 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2581 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2582 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2583 2584 return 0; 2585 } 2586 2587 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2588 { 2589 const struct rtw89_chip_info *chip = rtwdev->chip; 2590 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2591 u32 reg, val, sifs; 2592 int ret; 2593 2594 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2595 if (ret) 2596 return ret; 2597 2598 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2599 val = rtw89_read32(rtwdev, reg); 2600 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2601 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2602 2603 switch (rtwdev->chip->chip_id) { 2604 case RTL8852A: 2605 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2606 break; 2607 case RTL8851B: 2608 case RTL8852B: 2609 case RTL8852BT: 2610 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2611 break; 2612 default: 2613 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2614 break; 2615 } 2616 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2617 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2618 rtw89_write32(rtwdev, reg, val); 2619 2620 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2621 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2622 2623 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2624 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2625 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2626 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2627 2628 return 0; 2629 } 2630 2631 static void rst_bacam(struct rtw89_dev *rtwdev) 2632 { 2633 u32 val32; 2634 int ret; 2635 2636 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2637 S_AX_BACAM_RST_ALL); 2638 2639 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2640 1, 1000, false, 2641 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2642 if (ret) 2643 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2644 } 2645 2646 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2647 { 2648 #define TRXCFG_RMAC_CCA_TO 32 2649 #define TRXCFG_RMAC_DATA_TO 15 2650 #define RX_MAX_LEN_UNIT 512 2651 #define PLD_RLS_MAX_PG 127 2652 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2653 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2654 int ret; 2655 u32 reg, rx_max_len, rx_qta; 2656 u16 val; 2657 2658 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2659 if (ret) 2660 return ret; 2661 2662 if (mac_idx == RTW89_MAC_0) 2663 rst_bacam(rtwdev); 2664 2665 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2666 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2667 2668 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2669 val = rtw89_read16(rtwdev, reg); 2670 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2671 B_AX_RX_DLK_DATA_TIME_MASK); 2672 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2673 B_AX_RX_DLK_CCA_TIME_MASK); 2674 if (chip_id == RTL8852BT) 2675 val |= B_AX_RX_DLK_RST_EN; 2676 rtw89_write16(rtwdev, reg, val); 2677 2678 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2679 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2680 2681 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2682 if (mac_idx == RTW89_MAC_0) 2683 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2684 else 2685 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2686 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2687 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2688 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2689 rx_max_len /= RX_MAX_LEN_UNIT; 2690 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2691 2692 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) { 2693 rtw89_write16_mask(rtwdev, 2694 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2695 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2696 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2697 BIT(12)); 2698 } 2699 2700 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2701 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2702 2703 return ret; 2704 } 2705 2706 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2707 { 2708 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2709 u32 val, reg; 2710 int ret; 2711 2712 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2713 if (ret) 2714 return ret; 2715 2716 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2717 val = rtw89_read32(rtwdev, reg); 2718 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2719 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2720 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2721 rtw89_write32(rtwdev, reg, val); 2722 2723 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2724 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2725 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2726 } 2727 2728 return 0; 2729 } 2730 2731 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2732 { 2733 const struct rtw89_dle_mem *cfg; 2734 2735 cfg = get_dle_mem_cfg(rtwdev, mode); 2736 if (!cfg) { 2737 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2738 return false; 2739 } 2740 2741 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2742 } 2743 2744 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2745 { 2746 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2747 u32 val, reg; 2748 int ret; 2749 2750 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2751 if (ret) 2752 return ret; 2753 2754 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2755 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2756 val = rtw89_read32(rtwdev, reg); 2757 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2758 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2759 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2760 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2761 val |= B_AX_HW_CTS2SELF_EN; 2762 rtw89_write32(rtwdev, reg, val); 2763 2764 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2765 val = rtw89_read32(rtwdev, reg); 2766 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2767 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2768 rtw89_write32(rtwdev, reg, val); 2769 } 2770 2771 if (mac_idx == RTW89_MAC_0) { 2772 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2773 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2774 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2775 B_AX_PTCL_TRIGGER_SS_EN_0 | 2776 B_AX_PTCL_TRIGGER_SS_EN_1 | 2777 B_AX_PTCL_TRIGGER_SS_EN_UL); 2778 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2779 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2780 } else if (mac_idx == RTW89_MAC_1) { 2781 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2782 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2783 } 2784 2785 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2786 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_VHT_0, mac_idx); 2787 rtw89_write32_mask(rtwdev, reg, 2788 B_AX_AMPDU_MAX_LEN_VHT_MASK, 0x3FF80); 2789 } 2790 2791 return 0; 2792 } 2793 2794 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2795 { 2796 u32 reg; 2797 int ret; 2798 2799 if (!rtw89_is_rtl885xb(rtwdev)) 2800 return 0; 2801 2802 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2803 if (ret) 2804 return ret; 2805 2806 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2807 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2808 2809 return 0; 2810 } 2811 2812 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2813 { 2814 int ret; 2815 2816 ret = scheduler_init_ax(rtwdev, mac_idx); 2817 if (ret) { 2818 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2819 return ret; 2820 } 2821 2822 ret = addr_cam_init_ax(rtwdev, mac_idx); 2823 if (ret) { 2824 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2825 ret); 2826 return ret; 2827 } 2828 2829 ret = rx_fltr_init_ax(rtwdev, mac_idx); 2830 if (ret) { 2831 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2832 ret); 2833 return ret; 2834 } 2835 2836 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 2837 if (ret) { 2838 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2839 ret); 2840 return ret; 2841 } 2842 2843 ret = nav_ctrl_init_ax(rtwdev); 2844 if (ret) { 2845 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2846 ret); 2847 return ret; 2848 } 2849 2850 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 2851 if (ret) { 2852 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2853 mac_idx, ret); 2854 return ret; 2855 } 2856 2857 ret = tmac_init_ax(rtwdev, mac_idx); 2858 if (ret) { 2859 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2860 return ret; 2861 } 2862 2863 ret = trxptcl_init_ax(rtwdev, mac_idx); 2864 if (ret) { 2865 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2866 return ret; 2867 } 2868 2869 ret = rmac_init_ax(rtwdev, mac_idx); 2870 if (ret) { 2871 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2872 return ret; 2873 } 2874 2875 ret = cmac_com_init_ax(rtwdev, mac_idx); 2876 if (ret) { 2877 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2878 return ret; 2879 } 2880 2881 ret = ptcl_init_ax(rtwdev, mac_idx); 2882 if (ret) { 2883 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2884 return ret; 2885 } 2886 2887 ret = cmac_dma_init_ax(rtwdev, mac_idx); 2888 if (ret) { 2889 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2890 return ret; 2891 } 2892 2893 return ret; 2894 } 2895 2896 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2897 struct rtw89_mac_c2h_info *c2h_info) 2898 { 2899 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2900 struct rtw89_mac_h2c_info h2c_info = {0}; 2901 u32 ret; 2902 2903 mac->cnv_efuse_state(rtwdev, false); 2904 2905 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2906 h2c_info.content_len = 0; 2907 2908 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2909 if (ret) 2910 goto out; 2911 2912 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2913 ret = -EINVAL; 2914 2915 out: 2916 mac->cnv_efuse_state(rtwdev, true); 2917 2918 return ret; 2919 } 2920 2921 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2922 { 2923 struct rtw89_efuse *efuse = &rtwdev->efuse; 2924 struct rtw89_hal *hal = &rtwdev->hal; 2925 const struct rtw89_chip_info *chip = rtwdev->chip; 2926 struct rtw89_mac_c2h_info c2h_info = {0}; 2927 const struct rtw89_c2hreg_phycap *phycap; 2928 u8 tx_nss; 2929 u8 rx_nss; 2930 u8 tx_ant; 2931 u8 rx_ant; 2932 u32 ret; 2933 2934 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2935 if (ret) 2936 return ret; 2937 2938 phycap = &c2h_info.u.phycap; 2939 2940 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 2941 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 2942 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 2943 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2944 2945 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2946 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2947 2948 if (tx_ant == 1) 2949 hal->antenna_tx = RF_B; 2950 if (rx_ant == 1) 2951 hal->antenna_rx = RF_B; 2952 2953 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2954 hal->antenna_tx = RF_B; 2955 hal->tx_path_diversity = true; 2956 } 2957 2958 if (chip->rf_path_num == 1) { 2959 hal->antenna_tx = RF_A; 2960 hal->antenna_rx = RF_A; 2961 if ((efuse->rfe_type % 3) == 2) 2962 hal->ant_diversity = true; 2963 } 2964 2965 rtw89_debug(rtwdev, RTW89_DBG_FW, 2966 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2967 hal->tx_nss, tx_nss, chip->tx_nss, 2968 hal->rx_nss, rx_nss, chip->rx_nss); 2969 rtw89_debug(rtwdev, RTW89_DBG_FW, 2970 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2971 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2972 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2973 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2974 2975 return 0; 2976 } 2977 2978 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2979 u16 tx_en_u16, u16 mask_u16) 2980 { 2981 u32 ret; 2982 struct rtw89_mac_c2h_info c2h_info = {0}; 2983 struct rtw89_mac_h2c_info h2c_info = {0}; 2984 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 2985 2986 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2987 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 2988 2989 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 2990 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 2991 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 2992 2993 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2994 if (ret) 2995 return ret; 2996 2997 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2998 return -EINVAL; 2999 3000 return 0; 3001 } 3002 3003 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 3004 u16 tx_en, u16 tx_en_mask) 3005 { 3006 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 3007 u16 val; 3008 int ret; 3009 3010 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3011 if (ret) 3012 return ret; 3013 3014 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3015 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 3016 tx_en, tx_en_mask); 3017 3018 val = rtw89_read16(rtwdev, reg); 3019 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3020 rtw89_write16(rtwdev, reg, val); 3021 3022 return 0; 3023 } 3024 3025 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3026 u32 tx_en, u32 tx_en_mask) 3027 { 3028 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3029 u32 val; 3030 int ret; 3031 3032 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3033 if (ret) 3034 return ret; 3035 3036 val = rtw89_read32(rtwdev, reg); 3037 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3038 rtw89_write32(rtwdev, reg, val); 3039 3040 return 0; 3041 } 3042 3043 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3044 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3045 { 3046 int ret; 3047 3048 *tx_en = rtw89_read16(rtwdev, 3049 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3050 3051 switch (sel) { 3052 case RTW89_SCH_TX_SEL_ALL: 3053 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3054 B_AX_CTN_TXEN_ALL_MASK); 3055 if (ret) 3056 return ret; 3057 break; 3058 case RTW89_SCH_TX_SEL_HIQ: 3059 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3060 0, B_AX_CTN_TXEN_HGQ); 3061 if (ret) 3062 return ret; 3063 break; 3064 case RTW89_SCH_TX_SEL_MG0: 3065 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3066 0, B_AX_CTN_TXEN_MGQ); 3067 if (ret) 3068 return ret; 3069 break; 3070 case RTW89_SCH_TX_SEL_MACID: 3071 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3072 B_AX_CTN_TXEN_ALL_MASK); 3073 if (ret) 3074 return ret; 3075 break; 3076 default: 3077 return 0; 3078 } 3079 3080 return 0; 3081 } 3082 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3083 3084 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3085 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3086 { 3087 int ret; 3088 3089 *tx_en = rtw89_read32(rtwdev, 3090 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3091 3092 switch (sel) { 3093 case RTW89_SCH_TX_SEL_ALL: 3094 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3095 B_AX_CTN_TXEN_ALL_MASK_V1); 3096 if (ret) 3097 return ret; 3098 break; 3099 case RTW89_SCH_TX_SEL_HIQ: 3100 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3101 0, B_AX_CTN_TXEN_HGQ); 3102 if (ret) 3103 return ret; 3104 break; 3105 case RTW89_SCH_TX_SEL_MG0: 3106 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3107 0, B_AX_CTN_TXEN_MGQ); 3108 if (ret) 3109 return ret; 3110 break; 3111 case RTW89_SCH_TX_SEL_MACID: 3112 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3113 B_AX_CTN_TXEN_ALL_MASK_V1); 3114 if (ret) 3115 return ret; 3116 break; 3117 default: 3118 return 0; 3119 } 3120 3121 return 0; 3122 } 3123 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3124 3125 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3126 { 3127 int ret; 3128 3129 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3130 if (ret) 3131 return ret; 3132 3133 return 0; 3134 } 3135 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3136 3137 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3138 { 3139 int ret; 3140 3141 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3142 B_AX_CTN_TXEN_ALL_MASK_V1); 3143 if (ret) 3144 return ret; 3145 3146 return 0; 3147 } 3148 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3149 3150 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3151 { 3152 u32 val, reg; 3153 int ret; 3154 3155 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3156 val = buf_len; 3157 val |= B_AX_WD_BUF_REQ_EXEC; 3158 rtw89_write32(rtwdev, reg, val); 3159 3160 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3161 3162 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3163 1, 2000, false, rtwdev, reg); 3164 if (ret) 3165 return ret; 3166 3167 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3168 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3169 return -ENOENT; 3170 3171 return 0; 3172 } 3173 3174 static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3175 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3176 { 3177 u32 val, cmd_type, reg; 3178 int ret; 3179 3180 cmd_type = ctrl_para->cmd_type; 3181 3182 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3183 val = 0; 3184 val = u32_replace_bits(val, ctrl_para->start_pktid, 3185 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3186 val = u32_replace_bits(val, ctrl_para->end_pktid, 3187 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3188 rtw89_write32(rtwdev, reg, val); 3189 3190 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3191 val = 0; 3192 val = u32_replace_bits(val, ctrl_para->src_pid, 3193 B_AX_CPUQ_OP_SRC_PID_MASK); 3194 val = u32_replace_bits(val, ctrl_para->src_qid, 3195 B_AX_CPUQ_OP_SRC_QID_MASK); 3196 val = u32_replace_bits(val, ctrl_para->dst_pid, 3197 B_AX_CPUQ_OP_DST_PID_MASK); 3198 val = u32_replace_bits(val, ctrl_para->dst_qid, 3199 B_AX_CPUQ_OP_DST_QID_MASK); 3200 rtw89_write32(rtwdev, reg, val); 3201 3202 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3203 val = 0; 3204 val = u32_replace_bits(val, cmd_type, 3205 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3206 val = u32_replace_bits(val, ctrl_para->macid, 3207 B_AX_CPUQ_OP_MACID_MASK); 3208 val = u32_replace_bits(val, ctrl_para->pkt_num, 3209 B_AX_CPUQ_OP_PKTNUM_MASK); 3210 val |= B_AX_WD_CPUQ_OP_EXEC; 3211 rtw89_write32(rtwdev, reg, val); 3212 3213 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3214 3215 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3216 1, 2000, false, rtwdev, reg); 3217 if (ret) 3218 return ret; 3219 3220 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3221 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3222 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3223 3224 return 0; 3225 } 3226 3227 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3228 bool band1_en) 3229 { 3230 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3231 const struct rtw89_dle_mem *cfg; 3232 3233 cfg = get_dle_mem_cfg(rtwdev, mode); 3234 if (!cfg) { 3235 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3236 return -EINVAL; 3237 } 3238 3239 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3240 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3241 return -EINVAL; 3242 } 3243 3244 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3245 3246 return mac->dle_quota_change(rtwdev, band1_en); 3247 } 3248 3249 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3250 { 3251 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3252 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3253 u16 pkt_id; 3254 int ret; 3255 3256 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3257 if (ret) { 3258 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3259 return ret; 3260 } 3261 3262 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3263 ctrl_para.start_pktid = pkt_id; 3264 ctrl_para.end_pktid = pkt_id; 3265 ctrl_para.pkt_num = 0; 3266 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3267 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3268 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3269 if (ret) { 3270 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3271 return -EFAULT; 3272 } 3273 3274 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3275 if (ret) { 3276 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3277 return ret; 3278 } 3279 3280 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3281 ctrl_para.start_pktid = pkt_id; 3282 ctrl_para.end_pktid = pkt_id; 3283 ctrl_para.pkt_num = 0; 3284 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3285 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3286 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3287 if (ret) { 3288 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3289 return -EFAULT; 3290 } 3291 3292 return 0; 3293 } 3294 3295 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3296 { 3297 int ret; 3298 u32 reg; 3299 u8 val; 3300 3301 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3302 if (ret) 3303 return ret; 3304 3305 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3306 3307 ret = read_poll_timeout(rtw89_read8, val, 3308 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3309 SW_CVR_DUR_US, 3310 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3311 false, rtwdev, reg); 3312 if (ret) 3313 return ret; 3314 3315 return 0; 3316 } 3317 3318 static int band1_enable_ax(struct rtw89_dev *rtwdev) 3319 { 3320 int ret, i; 3321 u32 sleep_bak[4] = {0}; 3322 u32 pause_bak[4] = {0}; 3323 u32 tx_en; 3324 3325 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3326 if (ret) { 3327 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3328 return ret; 3329 } 3330 3331 for (i = 0; i < 4; i++) { 3332 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3333 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3334 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3335 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3336 } 3337 3338 ret = band_idle_ck_b(rtwdev, 0); 3339 if (ret) { 3340 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3341 return ret; 3342 } 3343 3344 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3345 if (ret) { 3346 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3347 return ret; 3348 } 3349 3350 for (i = 0; i < 4; i++) { 3351 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3352 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3353 } 3354 3355 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3356 if (ret) { 3357 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3358 return ret; 3359 } 3360 3361 ret = cmac_func_en_ax(rtwdev, 1, true); 3362 if (ret) { 3363 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3364 return ret; 3365 } 3366 3367 ret = cmac_init_ax(rtwdev, 1); 3368 if (ret) { 3369 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3370 return ret; 3371 } 3372 3373 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3374 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3375 3376 return 0; 3377 } 3378 3379 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3380 { 3381 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3382 3383 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3384 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3385 } 3386 3387 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3388 { 3389 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3390 3391 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3392 } 3393 3394 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3395 { 3396 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3397 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3398 3399 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3400 B_AX_TX_GET_ERRPKTID_INT_EN | 3401 B_AX_TX_NXT_ERRPKTID_INT_EN | 3402 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3403 B_AX_TX_OFFSET_ERR_INT_EN | 3404 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3405 if (chip_id == RTL8852C) 3406 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3407 B_AX_TX_ETH_TYPE_ERR_EN | 3408 B_AX_TX_LLC_PRE_ERR_EN | 3409 B_AX_TX_NW_TYPE_ERR_EN | 3410 B_AX_TX_KSRCH_ERR_EN); 3411 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3412 imr->mpdu_tx_imr_set); 3413 3414 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3415 B_AX_GETPKTID_ERR_INT_EN | 3416 B_AX_MHDRLEN_ERR_INT_EN | 3417 B_AX_RPT_ERR_INT_EN); 3418 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3419 imr->mpdu_rx_imr_set); 3420 } 3421 3422 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3423 { 3424 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3425 3426 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3427 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3428 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3429 B_AX_PLE_B_PKTID_ERR_INT_EN); 3430 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3431 imr->sta_sch_imr_set); 3432 } 3433 3434 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3435 { 3436 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3437 3438 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3439 imr->txpktctl_imr_b0_clr); 3440 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3441 imr->txpktctl_imr_b0_set); 3442 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3443 imr->txpktctl_imr_b1_clr); 3444 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3445 imr->txpktctl_imr_b1_set); 3446 } 3447 3448 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3449 { 3450 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3451 3452 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3453 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3454 } 3455 3456 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3457 { 3458 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3459 3460 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3461 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3462 } 3463 3464 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3465 { 3466 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3467 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3468 } 3469 3470 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3471 { 3472 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3473 3474 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3475 imr->host_disp_imr_clr); 3476 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3477 imr->host_disp_imr_set); 3478 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3479 imr->cpu_disp_imr_clr); 3480 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3481 imr->cpu_disp_imr_set); 3482 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3483 imr->other_disp_imr_clr); 3484 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3485 imr->other_disp_imr_set); 3486 } 3487 3488 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3489 { 3490 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3491 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3492 } 3493 3494 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3495 { 3496 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3497 3498 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3499 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3500 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3501 B_AX_BBRPT_CHINFO_IMR_CLR); 3502 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3503 imr->bbrpt_err_imr_set); 3504 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3505 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3506 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3507 } 3508 3509 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3510 { 3511 u32 reg; 3512 3513 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3514 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3515 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3516 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3517 } 3518 3519 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3520 { 3521 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3522 u32 reg; 3523 3524 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3525 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3526 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3527 } 3528 3529 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3530 { 3531 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3532 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3533 u32 reg; 3534 3535 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3536 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3537 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3538 3539 if (chip_id == RTL8852C) { 3540 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3541 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3542 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3543 } 3544 } 3545 3546 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3547 { 3548 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3549 u32 reg; 3550 3551 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3552 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3553 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3554 } 3555 3556 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3557 { 3558 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3559 u32 reg; 3560 3561 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3562 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3563 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3564 } 3565 3566 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3567 { 3568 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3569 u32 reg; 3570 3571 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3572 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3573 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3574 } 3575 3576 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3577 enum rtw89_mac_hwmod_sel sel) 3578 { 3579 int ret; 3580 3581 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3582 if (ret) { 3583 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3584 sel, mac_idx); 3585 return ret; 3586 } 3587 3588 if (sel == RTW89_DMAC_SEL) { 3589 rtw89_wdrls_imr_enable(rtwdev); 3590 rtw89_wsec_imr_enable(rtwdev); 3591 rtw89_mpdu_trx_imr_enable(rtwdev); 3592 rtw89_sta_sch_imr_enable(rtwdev); 3593 rtw89_txpktctl_imr_enable(rtwdev); 3594 rtw89_wde_imr_enable(rtwdev); 3595 rtw89_ple_imr_enable(rtwdev); 3596 rtw89_pktin_imr_enable(rtwdev); 3597 rtw89_dispatcher_imr_enable(rtwdev); 3598 rtw89_cpuio_imr_enable(rtwdev); 3599 rtw89_bbrpt_imr_enable(rtwdev); 3600 } else if (sel == RTW89_CMAC_SEL) { 3601 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3602 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3603 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3604 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3605 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3606 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3607 } else { 3608 return -EINVAL; 3609 } 3610 3611 return 0; 3612 } 3613 3614 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3615 { 3616 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3617 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3618 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3619 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3620 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta) 3621 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3622 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3623 } 3624 3625 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3626 { 3627 int ret = 0; 3628 3629 if (enable) { 3630 ret = band1_enable_ax(rtwdev); 3631 if (ret) { 3632 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3633 return ret; 3634 } 3635 3636 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3637 if (ret) { 3638 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3639 return ret; 3640 } 3641 } else { 3642 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3643 return -EINVAL; 3644 } 3645 3646 return 0; 3647 } 3648 3649 static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3650 { 3651 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3652 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3653 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3654 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3655 B_AX_RLSRPT0_FLTR_MAP_MASK); 3656 } else { 3657 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3658 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3659 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3660 B_AX_RLSRPT0_FLTR_MAP_MASK); 3661 } 3662 3663 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3664 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3665 3666 return 0; 3667 } 3668 3669 static int trx_init_ax(struct rtw89_dev *rtwdev) 3670 { 3671 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3672 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3673 int ret; 3674 3675 ret = dmac_init_ax(rtwdev, 0); 3676 if (ret) { 3677 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3678 return ret; 3679 } 3680 3681 ret = cmac_init_ax(rtwdev, 0); 3682 if (ret) { 3683 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3684 return ret; 3685 } 3686 3687 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3688 ret = dbcc_enable_ax(rtwdev, true); 3689 if (ret) { 3690 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3691 return ret; 3692 } 3693 } 3694 3695 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3696 if (ret) { 3697 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3698 return ret; 3699 } 3700 3701 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3702 if (ret) { 3703 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3704 return ret; 3705 } 3706 3707 err_imr_ctrl_ax(rtwdev, true); 3708 3709 ret = set_host_rpr_ax(rtwdev); 3710 if (ret) { 3711 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3712 return ret; 3713 } 3714 3715 if (chip_id == RTL8852C) 3716 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG, 3717 B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN); 3718 3719 return 0; 3720 } 3721 3722 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 3723 { 3724 #define BACAM_1024BMP_OCC_ENTRY 4 3725 #define BACAM_MAX_RU_SUPPORT_B0_STA 1 3726 #define BACAM_MAX_RU_SUPPORT_B1_STA 1 3727 const struct rtw89_chip_info *chip = rtwdev->chip; 3728 u8 users, offset; 3729 3730 if (chip->bacam_ver != RTW89_BACAM_V1) 3731 return 0; 3732 3733 offset = 0; 3734 users = BACAM_MAX_RU_SUPPORT_B0_STA; 3735 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 3736 3737 offset += users * BACAM_1024BMP_OCC_ENTRY; 3738 users = BACAM_MAX_RU_SUPPORT_B1_STA; 3739 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 3740 3741 return 0; 3742 } 3743 3744 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3745 { 3746 u32 val32; 3747 3748 if (rtw89_is_rtl885xb(rtwdev)) { 3749 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3750 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3751 return; 3752 } 3753 3754 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3755 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3756 3757 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3758 val32 |= B_AX_FS_WDT_INT; 3759 val32 &= ~B_AX_FS_WDT_INT_MSK; 3760 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3761 } 3762 3763 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3764 { 3765 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3766 3767 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3768 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3769 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3770 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3771 3772 rtw89_disable_fw_watchdog(rtwdev); 3773 3774 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3775 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3776 } 3777 3778 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3779 bool dlfw, bool include_bb) 3780 { 3781 u32 val; 3782 int ret; 3783 3784 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3785 return -EFAULT; 3786 3787 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3788 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3789 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3790 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3791 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3792 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3793 3794 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3795 3796 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3797 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3798 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3799 B_AX_WCPU_FWDL_STS_MASK); 3800 3801 if (dlfw) 3802 val |= B_AX_WCPU_FWDL_EN; 3803 3804 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3805 3806 if (rtw89_is_rtl885xb(rtwdev)) 3807 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3808 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3809 3810 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3811 boot_reason); 3812 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3813 3814 if (!dlfw) { 3815 mdelay(5); 3816 3817 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3818 if (ret) 3819 return ret; 3820 } 3821 3822 return 0; 3823 } 3824 3825 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 3826 { 3827 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3828 u32 val; 3829 3830 if (chip_id == RTL8852C) 3831 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3832 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3833 else 3834 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3835 B_AX_PKT_BUF_EN; 3836 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3837 } 3838 3839 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 3840 { 3841 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3842 u32 val; 3843 3844 if (chip_id == RTL8851B || chip_id == RTL8852BT) 3845 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3846 else 3847 val = B_AX_DISPATCHER_CLK_EN; 3848 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3849 3850 if (chip_id != RTL8852C) 3851 return; 3852 3853 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3854 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3855 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3856 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3857 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3858 3859 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3860 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3861 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3862 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3863 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3864 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3865 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3866 } 3867 3868 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3869 { 3870 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3871 int ret; 3872 3873 mac->hci_func_en(rtwdev); 3874 mac->dmac_func_pre_en(rtwdev); 3875 3876 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3877 if (ret) { 3878 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3879 return ret; 3880 } 3881 3882 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 3883 if (ret) { 3884 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3885 return ret; 3886 } 3887 3888 return ret; 3889 } 3890 3891 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3892 { 3893 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3894 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3895 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3896 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3897 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3898 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3899 3900 return 0; 3901 } 3902 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3903 3904 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3905 { 3906 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3907 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3908 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3909 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3910 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3911 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3912 3913 return 0; 3914 } 3915 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3916 3917 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 3918 { 3919 int ret; 3920 3921 ret = rtw89_mac_power_switch(rtwdev, true); 3922 if (ret) { 3923 rtw89_mac_power_switch(rtwdev, false); 3924 ret = rtw89_mac_power_switch(rtwdev, true); 3925 if (ret) 3926 return ret; 3927 } 3928 3929 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3930 3931 if (include_bb) { 3932 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 3933 if (rtwdev->dbcc_en) 3934 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 3935 } 3936 3937 ret = rtw89_mac_dmac_pre_init(rtwdev); 3938 if (ret) 3939 return ret; 3940 3941 if (rtwdev->hci.ops->mac_pre_init) { 3942 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3943 if (ret) 3944 return ret; 3945 } 3946 3947 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 3948 if (ret) 3949 return ret; 3950 3951 return 0; 3952 } 3953 3954 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3955 { 3956 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3957 const struct rtw89_chip_info *chip = rtwdev->chip; 3958 bool include_bb = !!chip->bbmcu_nr; 3959 int ret; 3960 3961 ret = rtw89_mac_partial_init(rtwdev, include_bb); 3962 if (ret) 3963 goto fail; 3964 3965 ret = rtw89_chip_enable_bb_rf(rtwdev); 3966 if (ret) 3967 goto fail; 3968 3969 ret = mac->sys_init(rtwdev); 3970 if (ret) 3971 goto fail; 3972 3973 ret = mac->trx_init(rtwdev); 3974 if (ret) 3975 goto fail; 3976 3977 ret = rtw89_mac_feat_init(rtwdev); 3978 if (ret) 3979 goto fail; 3980 3981 if (rtwdev->hci.ops->mac_post_init) { 3982 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3983 if (ret) 3984 goto fail; 3985 } 3986 3987 rtw89_fw_send_all_early_h2c(rtwdev); 3988 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3989 3990 return ret; 3991 fail: 3992 rtw89_mac_power_switch(rtwdev, false); 3993 3994 return ret; 3995 } 3996 3997 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3998 { 3999 u8 i; 4000 4001 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 4002 return; 4003 4004 for (i = 0; i < 4; i++) { 4005 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4006 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 4007 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 4008 } 4009 } 4010 4011 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4012 { 4013 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 4014 return; 4015 4016 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4017 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 4018 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 4019 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 4020 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 4021 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 4022 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 4023 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 4024 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 4025 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 4026 } 4027 4028 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4029 { 4030 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4031 u8 grp = macid >> 5; 4032 int ret; 4033 4034 /* If this is called by change_interface() in the case of P2P, it could 4035 * be power-off, so ignore this operation. 4036 */ 4037 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4038 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4039 return 0; 4040 4041 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4042 if (ret) 4043 return ret; 4044 4045 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4046 4047 return 0; 4048 } 4049 4050 static const struct rtw89_port_reg rtw89_port_base_ax = { 4051 .port_cfg = R_AX_PORT_CFG_P0, 4052 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4053 .bcn_area = R_AX_BCN_AREA_P0, 4054 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4055 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4056 .tbtt_agg = R_AX_TBTT_AGG_P0, 4057 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4058 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4059 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4060 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4061 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4062 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4063 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4064 .tsftr_l = R_AX_TSFTR_LOW_P0, 4065 .tsftr_h = R_AX_TSFTR_HIGH_P0, 4066 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 4067 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4068 .mbssid = R_AX_MBSSID_CTRL, 4069 .mbssid_drop = R_AX_MBSSID_DROP_0, 4070 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4071 .ptcl_dbg = R_AX_PTCL_DBG, 4072 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4073 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4074 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4075 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4076 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4077 }; 4078 4079 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4080 struct rtw89_vif_link *rtwvif_link, u8 type) 4081 { 4082 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4083 const struct rtw89_port_reg *p = mac->port_base; 4084 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif_link->port); 4085 u32 reg_info, reg_ctrl; 4086 u32 val; 4087 int ret; 4088 4089 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif_link->mac_idx); 4090 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif_link->mac_idx); 4091 4092 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4093 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4094 fsleep(100); 4095 4096 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4097 true, rtwdev, reg_info, mask); 4098 if (ret) 4099 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4100 } 4101 4102 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, 4103 struct rtw89_vif_link *rtwvif_link) 4104 { 4105 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4106 const struct rtw89_port_reg *p = mac->port_base; 4107 4108 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4109 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 4110 1); 4111 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 4112 0); 4113 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 4114 0); 4115 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4116 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4117 B_AX_TBTTERLY_MASK, 1); 4118 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, 4119 B_AX_BCN_SPACE_MASK, 1); 4120 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4121 4122 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM0); 4123 if (rtwvif_link->port == RTW89_PORT_0) 4124 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM1); 4125 4126 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4127 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4128 fsleep(2000); 4129 } 4130 4131 #define BCN_INTERVAL 100 4132 #define BCN_ERLY_DEF 160 4133 #define BCN_SETUP_DEF 2 4134 #define BCN_HOLD_DEF 200 4135 #define BCN_MASK_DEF 0 4136 #define TBTT_ERLY_DEF 5 4137 #define BCN_SET_UNIT 32 4138 #define BCN_ERLY_SET_DLY (10 * 2) 4139 4140 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4141 struct rtw89_vif_link *rtwvif_link) 4142 { 4143 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4144 const struct rtw89_port_reg *p = mac->port_base; 4145 const struct rtw89_chip_info *chip = rtwdev->chip; 4146 struct ieee80211_bss_conf *bss_conf; 4147 bool need_backup = false; 4148 u32 backup_val; 4149 u16 beacon_int; 4150 4151 if (!rtw89_read32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN)) 4152 return; 4153 4154 if (chip->chip_id == RTL8852A && rtwvif_link->port != RTW89_PORT_0) { 4155 need_backup = true; 4156 backup_val = rtw89_read32_port(rtwdev, rtwvif_link, p->tbtt_prohib); 4157 } 4158 4159 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4160 rtw89_mac_bcn_drop(rtwdev, rtwvif_link); 4161 4162 if (chip->chip_id == RTL8852A) { 4163 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->tbtt_prohib, 4164 B_AX_TBTT_SETUP_MASK); 4165 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4166 B_AX_TBTT_HOLD_MASK, 1); 4167 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->tbtt_early, 4168 B_AX_TBTTERLY_MASK); 4169 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->bcn_early, 4170 B_AX_BCNERLY_MASK); 4171 } 4172 4173 rcu_read_lock(); 4174 4175 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4176 beacon_int = bss_conf->beacon_int; 4177 4178 rcu_read_unlock(); 4179 4180 msleep(beacon_int + 1); 4181 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN | 4182 B_AX_BRK_SETUP); 4183 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSFTR_RST); 4184 rtw89_write32_port(rtwdev, rtwvif_link, p->bcn_cnt_tmr, 0); 4185 4186 if (need_backup) 4187 rtw89_write32_port(rtwdev, rtwvif_link, p->tbtt_prohib, backup_val); 4188 } 4189 4190 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4191 struct rtw89_vif_link *rtwvif_link, bool en) 4192 { 4193 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4194 const struct rtw89_port_reg *p = mac->port_base; 4195 4196 if (en) 4197 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4198 B_AX_TXBCN_RPT_EN); 4199 else 4200 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4201 B_AX_TXBCN_RPT_EN); 4202 } 4203 4204 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4205 struct rtw89_vif_link *rtwvif_link, bool en) 4206 { 4207 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4208 const struct rtw89_port_reg *p = mac->port_base; 4209 4210 if (en) 4211 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4212 B_AX_RXBCN_RPT_EN); 4213 else 4214 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4215 B_AX_RXBCN_RPT_EN); 4216 } 4217 4218 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4219 struct rtw89_vif_link *rtwvif_link) 4220 { 4221 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4222 const struct rtw89_port_reg *p = mac->port_base; 4223 4224 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_NET_TYPE_MASK, 4225 rtwvif_link->net_type); 4226 } 4227 4228 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4229 struct rtw89_vif_link *rtwvif_link) 4230 { 4231 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4232 const struct rtw89_port_reg *p = mac->port_base; 4233 bool en = rtwvif_link->net_type != RTW89_NET_TYPE_NO_LINK; 4234 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4235 4236 if (en) 4237 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bits); 4238 else 4239 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bits); 4240 } 4241 4242 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4243 struct rtw89_vif_link *rtwvif_link) 4244 { 4245 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4246 const struct rtw89_port_reg *p = mac->port_base; 4247 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4248 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4249 u32 bit = B_AX_RX_BSSID_FIT_EN; 4250 4251 if (en) 4252 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bit); 4253 else 4254 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bit); 4255 } 4256 4257 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4258 struct rtw89_vif_link *rtwvif_link, bool en) 4259 { 4260 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4261 const struct rtw89_port_reg *p = mac->port_base; 4262 4263 if (en) 4264 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4265 else 4266 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4267 } 4268 4269 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4270 struct rtw89_vif_link *rtwvif_link) 4271 { 4272 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4273 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4274 4275 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif_link, en); 4276 } 4277 4278 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4279 struct rtw89_vif_link *rtwvif_link, bool en) 4280 { 4281 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4282 const struct rtw89_port_reg *p = mac->port_base; 4283 4284 if (en) 4285 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4286 else 4287 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4288 } 4289 4290 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4291 struct rtw89_vif_link *rtwvif_link) 4292 { 4293 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || 4294 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4295 4296 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4297 } 4298 4299 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4300 { 4301 struct rtw89_vif_link *rtwvif_link; 4302 struct rtw89_vif *rtwvif; 4303 unsigned int link_id; 4304 4305 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4306 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4307 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4308 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4309 } 4310 4311 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4312 struct rtw89_vif_link *rtwvif_link) 4313 { 4314 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4315 const struct rtw89_port_reg *p = mac->port_base; 4316 struct ieee80211_bss_conf *bss_conf; 4317 u16 bcn_int; 4318 4319 rcu_read_lock(); 4320 4321 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4322 if (bss_conf->beacon_int) 4323 bcn_int = bss_conf->beacon_int; 4324 else 4325 bcn_int = BCN_INTERVAL; 4326 4327 rcu_read_unlock(); 4328 4329 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, B_AX_BCN_SPACE_MASK, 4330 bcn_int); 4331 } 4332 4333 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4334 struct rtw89_vif_link *rtwvif_link) 4335 { 4336 u8 win = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4337 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4338 const struct rtw89_port_reg *p = mac->port_base; 4339 u8 port = rtwvif_link->port; 4340 u32 reg; 4341 4342 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif_link->mac_idx); 4343 rtw89_write8(rtwdev, reg, win); 4344 } 4345 4346 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4347 struct rtw89_vif_link *rtwvif_link) 4348 { 4349 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4350 const struct rtw89_port_reg *p = mac->port_base; 4351 struct ieee80211_bss_conf *bss_conf; 4352 u8 dtim_period; 4353 u32 addr; 4354 4355 rcu_read_lock(); 4356 4357 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4358 dtim_period = bss_conf->dtim_period; 4359 4360 rcu_read_unlock(); 4361 4362 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif_link->mac_idx); 4363 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4364 4365 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4366 dtim_period); 4367 } 4368 4369 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4370 struct rtw89_vif_link *rtwvif_link) 4371 { 4372 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4373 const struct rtw89_port_reg *p = mac->port_base; 4374 4375 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4376 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4377 } 4378 4379 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4380 struct rtw89_vif_link *rtwvif_link) 4381 { 4382 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4383 const struct rtw89_port_reg *p = mac->port_base; 4384 4385 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4386 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4387 } 4388 4389 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4390 struct rtw89_vif_link *rtwvif_link) 4391 { 4392 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4393 const struct rtw89_port_reg *p = mac->port_base; 4394 4395 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, 4396 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4397 } 4398 4399 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4400 struct rtw89_vif_link *rtwvif_link) 4401 { 4402 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4403 const struct rtw89_port_reg *p = mac->port_base; 4404 4405 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4406 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4407 } 4408 4409 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4410 struct rtw89_vif_link *rtwvif_link) 4411 { 4412 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4413 const struct rtw89_port_reg *p = mac->port_base; 4414 static const u32 masks[RTW89_PORT_NUM] = { 4415 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4416 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4417 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4418 }; 4419 struct ieee80211_bss_conf *bss_conf; 4420 u8 port = rtwvif_link->port; 4421 u32 reg_base; 4422 u32 reg; 4423 u8 bss_color; 4424 4425 rcu_read_lock(); 4426 4427 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4428 bss_color = bss_conf->he_bss_color.color; 4429 4430 rcu_read_unlock(); 4431 4432 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4433 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif_link->mac_idx); 4434 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4435 } 4436 4437 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4438 struct rtw89_vif_link *rtwvif_link) 4439 { 4440 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4441 const struct rtw89_port_reg *p = mac->port_base; 4442 u8 port = rtwvif_link->port; 4443 u32 reg; 4444 4445 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4446 return; 4447 4448 if (port == 0) { 4449 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif_link->mac_idx); 4450 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4451 } 4452 } 4453 4454 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4455 struct rtw89_vif_link *rtwvif_link) 4456 { 4457 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4458 const struct rtw89_port_reg *p = mac->port_base; 4459 u8 port = rtwvif_link->port; 4460 u32 reg; 4461 u32 val; 4462 4463 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif_link->mac_idx); 4464 val = rtw89_read32(rtwdev, reg); 4465 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4466 if (port == 0) 4467 val &= ~BIT(0); 4468 rtw89_write32(rtwdev, reg, val); 4469 } 4470 4471 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4472 struct rtw89_vif_link *rtwvif_link, bool enable) 4473 { 4474 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4475 const struct rtw89_port_reg *p = mac->port_base; 4476 4477 if (enable) 4478 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4479 B_AX_PORT_FUNC_EN); 4480 else 4481 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4482 B_AX_PORT_FUNC_EN); 4483 } 4484 4485 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4486 struct rtw89_vif_link *rtwvif_link) 4487 { 4488 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4489 const struct rtw89_port_reg *p = mac->port_base; 4490 4491 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 4492 BCN_ERLY_DEF); 4493 } 4494 4495 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4496 struct rtw89_vif_link *rtwvif_link) 4497 { 4498 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4499 const struct rtw89_port_reg *p = mac->port_base; 4500 u16 val; 4501 4502 if (rtwdev->chip->chip_id != RTL8852C) 4503 return; 4504 4505 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4506 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION) 4507 return; 4508 4509 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4510 B_AX_TBTT_SHIFT_OFST_SIGN; 4511 4512 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift, 4513 B_AX_TBTT_SHIFT_OFST_MASK, val); 4514 } 4515 4516 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4517 struct rtw89_vif_link *rtwvif_link, 4518 struct rtw89_vif_link *rtwvif_src, 4519 u16 offset_tu) 4520 { 4521 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4522 const struct rtw89_port_reg *p = mac->port_base; 4523 u32 val, reg; 4524 4525 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4526 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif_link->port * 4, 4527 rtwvif_link->mac_idx); 4528 4529 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4530 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4531 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4532 } 4533 4534 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4535 struct rtw89_vif_link *rtwvif_link, 4536 struct rtw89_vif_link *rtwvif_src, 4537 u8 offset, int *n_offset) 4538 { 4539 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif_link == rtwvif_src) 4540 return; 4541 4542 /* adjust offset randomly to avoid beacon conflict */ 4543 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4544 rtw89_mac_port_tsf_sync(rtwdev, rtwvif_link, rtwvif_src, 4545 (*n_offset) * offset); 4546 4547 (*n_offset)++; 4548 } 4549 4550 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4551 { 4552 struct rtw89_vif_link *src = NULL, *tmp; 4553 u8 offset = 100, vif_aps = 0; 4554 struct rtw89_vif *rtwvif; 4555 unsigned int link_id; 4556 int n_offset = 1; 4557 4558 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4559 rtw89_vif_for_each_link(rtwvif, tmp, link_id) { 4560 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4561 src = tmp; 4562 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4563 vif_aps++; 4564 } 4565 } 4566 4567 if (vif_aps == 0) 4568 return; 4569 4570 offset /= (vif_aps + 1); 4571 4572 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4573 rtw89_vif_for_each_link(rtwvif, tmp, link_id) 4574 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, 4575 &n_offset); 4576 } 4577 4578 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4579 { 4580 int ret; 4581 4582 ret = rtw89_mac_port_update(rtwdev, rtwvif_link); 4583 if (ret) 4584 return ret; 4585 4586 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4587 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4588 4589 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif_link->mac_id, false); 4590 if (ret) 4591 return ret; 4592 4593 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_CREATE); 4594 if (ret) 4595 return ret; 4596 4597 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, NULL, true); 4598 if (ret) 4599 return ret; 4600 4601 ret = rtw89_cam_init(rtwdev, rtwvif_link); 4602 if (ret) 4603 return ret; 4604 4605 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 4606 if (ret) 4607 return ret; 4608 4609 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, NULL); 4610 if (ret) 4611 return ret; 4612 4613 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, NULL); 4614 if (ret) 4615 return ret; 4616 4617 return 0; 4618 } 4619 4620 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4621 { 4622 int ret; 4623 4624 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_REMOVE); 4625 if (ret) 4626 return ret; 4627 4628 rtw89_cam_deinit(rtwdev, rtwvif_link); 4629 4630 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 4631 if (ret) 4632 return ret; 4633 4634 return 0; 4635 } 4636 4637 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4638 { 4639 u8 port = rtwvif_link->port; 4640 4641 if (port >= RTW89_PORT_NUM) 4642 return -EINVAL; 4643 4644 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 4645 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif_link, false); 4646 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif_link, false); 4647 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif_link); 4648 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif_link); 4649 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif_link); 4650 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif_link); 4651 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif_link); 4652 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif_link); 4653 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif_link); 4654 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif_link); 4655 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif_link); 4656 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif_link); 4657 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif_link); 4658 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif_link); 4659 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif_link); 4660 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif_link); 4661 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif_link); 4662 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif_link); 4663 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif_link, true); 4664 rtw89_mac_port_tsf_resync_all(rtwdev); 4665 fsleep(BCN_ERLY_SET_DLY); 4666 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif_link); 4667 4668 return 0; 4669 } 4670 4671 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4672 u64 *tsf) 4673 { 4674 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4675 const struct rtw89_port_reg *p = mac->port_base; 4676 u32 tsf_low, tsf_high; 4677 int ret; 4678 4679 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif_link->mac_idx, RTW89_CMAC_SEL); 4680 if (ret) 4681 return ret; 4682 4683 tsf_low = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_l); 4684 tsf_high = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_h); 4685 *tsf = (u64)tsf_high << 32 | tsf_low; 4686 4687 return 0; 4688 } 4689 4690 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4691 struct cfg80211_bss *bss, 4692 void *data) 4693 { 4694 const struct cfg80211_bss_ies *ies; 4695 const struct element *elem; 4696 bool *tolerated = data; 4697 4698 rcu_read_lock(); 4699 ies = rcu_dereference(bss->ies); 4700 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4701 ies->len); 4702 4703 if (!elem || elem->datalen < 10 || 4704 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4705 *tolerated = false; 4706 rcu_read_unlock(); 4707 } 4708 4709 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4710 struct rtw89_vif_link *rtwvif_link) 4711 { 4712 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4713 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4714 struct ieee80211_hw *hw = rtwdev->hw; 4715 struct ieee80211_bss_conf *bss_conf; 4716 struct cfg80211_chan_def oper; 4717 bool tolerated = true; 4718 u32 reg; 4719 4720 rcu_read_lock(); 4721 4722 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4723 if (!bss_conf->he_support || vif->type != NL80211_IFTYPE_STATION) { 4724 rcu_read_unlock(); 4725 return; 4726 } 4727 4728 oper = bss_conf->chanreq.oper; 4729 if (!(oper.chan->flags & IEEE80211_CHAN_RADAR)) { 4730 rcu_read_unlock(); 4731 return; 4732 } 4733 4734 rcu_read_unlock(); 4735 4736 cfg80211_bss_iter(hw->wiphy, &oper, 4737 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4738 &tolerated); 4739 4740 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 4741 rtwvif_link->mac_idx); 4742 if (tolerated) 4743 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4744 else 4745 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4746 } 4747 4748 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4749 { 4750 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 4751 } 4752 4753 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4754 { 4755 return rtw89_mac_vif_init(rtwdev, rtwvif_link); 4756 } 4757 4758 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4759 { 4760 return rtw89_mac_vif_deinit(rtwdev, rtwvif_link); 4761 } 4762 4763 static void 4764 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4765 { 4766 } 4767 4768 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4769 { 4770 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4771 4772 return band == op->band_type && channel == op->primary_channel; 4773 } 4774 4775 static void 4776 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4777 u32 len) 4778 { 4779 const struct rtw89_c2h_scanofld *c2h = 4780 (const struct rtw89_c2h_scanofld *)skb->data; 4781 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 4782 struct rtw89_vif *rtwvif; 4783 struct rtw89_chan new; 4784 u8 reason, status, tx_fail, band, actual_period, expect_period; 4785 u32 last_chan = rtwdev->scan_info.last_chan_idx, report_tsf; 4786 u8 mac_idx, sw_def, fw_def; 4787 u16 chan; 4788 int ret; 4789 4790 if (!rtwvif_link) 4791 return; 4792 4793 rtwvif = rtwvif_link->rtwvif; 4794 4795 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 4796 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 4797 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 4798 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 4799 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 4800 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 4801 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 4802 4803 4804 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4805 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4806 4807 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4808 "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4809 mac_idx, band, chan, reason, status, tx_fail, actual_period); 4810 4811 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4812 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 4813 expect_period = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 4814 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 4815 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 4816 4817 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4818 "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 4819 sw_def, fw_def, report_tsf, expect_period); 4820 } 4821 4822 switch (reason) { 4823 case RTW89_SCAN_LEAVE_OP_NOTIFY: 4824 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4825 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4826 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, false); 4827 ieee80211_stop_queues(rtwdev->hw); 4828 } 4829 return; 4830 case RTW89_SCAN_END_SCAN_NOTIFY: 4831 if (rtwdev->scan_info.abort) 4832 return; 4833 4834 if (rtwvif_link && rtwvif->scan_req && 4835 last_chan < rtwvif->scan_req->n_channels) { 4836 ret = rtw89_hw_scan_offload(rtwdev, rtwvif_link, true); 4837 if (ret) { 4838 rtw89_hw_scan_abort(rtwdev, rtwvif_link); 4839 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4840 } 4841 } else { 4842 rtw89_hw_scan_complete(rtwdev, rtwvif_link, false); 4843 } 4844 break; 4845 case RTW89_SCAN_ENTER_OP_NOTIFY: 4846 case RTW89_SCAN_ENTER_CH_NOTIFY: 4847 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4848 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, 4849 &rtwdev->scan_info.op_chan); 4850 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, true); 4851 ieee80211_wake_queues(rtwdev->hw); 4852 } else { 4853 rtw89_chan_create(&new, chan, chan, band, 4854 RTW89_CHANNEL_WIDTH_20); 4855 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, 4856 &new); 4857 } 4858 break; 4859 default: 4860 return; 4861 } 4862 } 4863 4864 static void 4865 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4866 struct sk_buff *skb) 4867 { 4868 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4869 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 4870 enum nl80211_cqm_rssi_threshold_event nl_event; 4871 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4872 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4873 u8 type, event, mac_id; 4874 s8 sig; 4875 4876 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4877 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4878 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4879 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4880 4881 if (mac_id != rtwvif_link->mac_id) 4882 return; 4883 4884 rtw89_debug(rtwdev, RTW89_DBG_FW, 4885 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4886 mac_id, type, sig, event); 4887 4888 switch (type) { 4889 case RTW89_BCN_FLTR_BEACON_LOSS: 4890 if (!rtwdev->scanning && !rtwvif->offchan) 4891 ieee80211_connection_loss(vif); 4892 else 4893 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 4894 return; 4895 case RTW89_BCN_FLTR_NOTIFY: 4896 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4897 break; 4898 case RTW89_BCN_FLTR_RSSI: 4899 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4900 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4901 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4902 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4903 else 4904 return; 4905 break; 4906 default: 4907 return; 4908 } 4909 4910 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4911 } 4912 4913 static void 4914 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4915 u32 len) 4916 { 4917 struct rtw89_vif_link *rtwvif_link; 4918 struct rtw89_vif *rtwvif; 4919 unsigned int link_id; 4920 4921 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4922 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4923 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif_link, c2h); 4924 } 4925 4926 static void 4927 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4928 { 4929 /* N.B. This will run in interrupt context. */ 4930 4931 rtw89_debug(rtwdev, RTW89_DBG_FW, 4932 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4933 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4934 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4935 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4936 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4937 } 4938 4939 static void 4940 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4941 { 4942 /* N.B. This will run in interrupt context. */ 4943 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4944 struct rtw89_wait_info *ps_wait = &rtwdev->mac.ps_wait; 4945 const struct rtw89_c2h_done_ack *c2h = 4946 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4947 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4948 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4949 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4950 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4951 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4952 struct rtw89_completion_data data = {}; 4953 unsigned int cond; 4954 4955 rtw89_debug(rtwdev, RTW89_DBG_FW, 4956 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4957 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4958 4959 if (h2c_cat != H2C_CAT_MAC) 4960 return; 4961 4962 switch (h2c_class) { 4963 default: 4964 return; 4965 case H2C_CL_MAC_PS: 4966 switch (h2c_func) { 4967 default: 4968 return; 4969 case H2C_FUNC_IPS_CFG: 4970 cond = RTW89_PS_WAIT_COND_IPS_CFG; 4971 break; 4972 } 4973 4974 data.err = !!h2c_return; 4975 rtw89_complete_cond(ps_wait, cond, &data); 4976 return; 4977 case H2C_CL_MAC_FW_OFLD: 4978 switch (h2c_func) { 4979 default: 4980 return; 4981 case H2C_FUNC_ADD_SCANOFLD_CH: 4982 cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 4983 break; 4984 case H2C_FUNC_SCANOFLD: 4985 cond = RTW89_SCANOFLD_WAIT_COND_START; 4986 break; 4987 case H2C_FUNC_SCANOFLD_BE: 4988 cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 4989 break; 4990 } 4991 4992 data.err = !!h2c_return; 4993 rtw89_complete_cond(fw_ofld_wait, cond, &data); 4994 return; 4995 } 4996 } 4997 4998 static void 4999 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5000 { 5001 rtw89_fw_log_dump(rtwdev, c2h->data, len); 5002 } 5003 5004 static void 5005 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5006 { 5007 } 5008 5009 static void 5010 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 5011 u32 len) 5012 { 5013 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 5014 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 5015 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 5016 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 5017 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 5018 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 5019 struct rtw89_completion_data data = {}; 5020 unsigned int cond; 5021 5022 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 5023 pkt_id, pkt_op, pkt_len); 5024 5025 data.err = !pkt_len; 5026 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 5027 5028 rtw89_complete_cond(wait, cond, &data); 5029 } 5030 5031 static void 5032 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5033 u32 len) 5034 { 5035 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 5036 } 5037 5038 static void 5039 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5040 { 5041 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 5042 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 5043 5044 switch (func) { 5045 case H2C_FUNC_ADD_MCC: 5046 case H2C_FUNC_START_MCC: 5047 case H2C_FUNC_STOP_MCC: 5048 case H2C_FUNC_DEL_MCC_GROUP: 5049 case H2C_FUNC_RESET_MCC_GROUP: 5050 case H2C_FUNC_MCC_REQ_TSF: 5051 case H2C_FUNC_MCC_MACID_BITMAP: 5052 case H2C_FUNC_MCC_SYNC: 5053 case H2C_FUNC_MCC_SET_DURATION: 5054 break; 5055 default: 5056 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5057 "invalid MCC C2H RCV ACK: func %d\n", func); 5058 return; 5059 } 5060 5061 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5062 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 5063 } 5064 5065 static void 5066 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5067 { 5068 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 5069 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 5070 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 5071 struct rtw89_completion_data data = {}; 5072 unsigned int cond; 5073 bool next = false; 5074 5075 switch (func) { 5076 case H2C_FUNC_MCC_REQ_TSF: 5077 next = true; 5078 break; 5079 case H2C_FUNC_MCC_MACID_BITMAP: 5080 case H2C_FUNC_MCC_SYNC: 5081 case H2C_FUNC_MCC_SET_DURATION: 5082 break; 5083 case H2C_FUNC_ADD_MCC: 5084 case H2C_FUNC_START_MCC: 5085 case H2C_FUNC_STOP_MCC: 5086 case H2C_FUNC_DEL_MCC_GROUP: 5087 case H2C_FUNC_RESET_MCC_GROUP: 5088 default: 5089 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5090 "invalid MCC C2H REQ ACK: func %d\n", func); 5091 return; 5092 } 5093 5094 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5095 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5096 group, func, retcode); 5097 5098 if (!retcode && next) 5099 return; 5100 5101 data.err = !!retcode; 5102 cond = RTW89_MCC_WAIT_COND(group, func); 5103 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5104 } 5105 5106 static void 5107 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5108 { 5109 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5110 struct rtw89_completion_data data = {}; 5111 struct rtw89_mac_mcc_tsf_rpt *rpt; 5112 unsigned int cond; 5113 5114 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5115 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5116 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5117 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5118 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5119 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5120 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5121 5122 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5123 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5124 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5125 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5126 5127 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5128 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5129 } 5130 5131 static void 5132 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5133 { 5134 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5135 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5136 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5137 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5138 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5139 struct rtw89_completion_data data = {}; 5140 unsigned int cond; 5141 bool rsp = true; 5142 bool err; 5143 u8 func; 5144 5145 switch (status) { 5146 case RTW89_MAC_MCC_ADD_ROLE_OK: 5147 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5148 func = H2C_FUNC_ADD_MCC; 5149 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5150 break; 5151 case RTW89_MAC_MCC_START_GROUP_OK: 5152 case RTW89_MAC_MCC_START_GROUP_FAIL: 5153 func = H2C_FUNC_START_MCC; 5154 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5155 break; 5156 case RTW89_MAC_MCC_STOP_GROUP_OK: 5157 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5158 func = H2C_FUNC_STOP_MCC; 5159 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5160 break; 5161 case RTW89_MAC_MCC_DEL_GROUP_OK: 5162 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5163 func = H2C_FUNC_DEL_MCC_GROUP; 5164 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5165 break; 5166 case RTW89_MAC_MCC_RESET_GROUP_OK: 5167 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5168 func = H2C_FUNC_RESET_MCC_GROUP; 5169 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5170 break; 5171 case RTW89_MAC_MCC_SWITCH_CH_OK: 5172 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5173 case RTW89_MAC_MCC_TXNULL0_OK: 5174 case RTW89_MAC_MCC_TXNULL0_FAIL: 5175 case RTW89_MAC_MCC_TXNULL1_OK: 5176 case RTW89_MAC_MCC_TXNULL1_FAIL: 5177 case RTW89_MAC_MCC_SWITCH_EARLY: 5178 case RTW89_MAC_MCC_TBTT: 5179 case RTW89_MAC_MCC_DURATION_START: 5180 case RTW89_MAC_MCC_DURATION_END: 5181 rsp = false; 5182 break; 5183 default: 5184 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5185 "invalid MCC C2H STS RPT: status %d\n", status); 5186 return; 5187 } 5188 5189 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5190 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5191 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5192 5193 if (!rsp) 5194 return; 5195 5196 data.err = err; 5197 cond = RTW89_MCC_WAIT_COND(group, func); 5198 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5199 } 5200 5201 static void 5202 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5203 { 5204 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5205 const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5206 struct rtw89_completion_data data = {}; 5207 struct rtw89_mac_mrc_tsf_rpt *rpt; 5208 unsigned int i; 5209 5210 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5211 rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5212 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5213 le32_get_bits(c2h_rpt->w2, 5214 RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5215 5216 for (i = 0; i < rpt->num; i++) { 5217 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5218 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5219 5220 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5221 5222 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5223 "MRC C2H TSF RPT: index %u> %llu\n", 5224 i, rpt->tsfs[i]); 5225 } 5226 5227 rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5228 } 5229 5230 static void 5231 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5232 { 5233 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 5234 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 5235 struct rtw89_wait_info *wait = &rtw_wow->wait; 5236 const struct rtw89_c2h_wow_aoac_report *c2h = 5237 (const struct rtw89_c2h_wow_aoac_report *)skb->data; 5238 struct rtw89_completion_data data = {}; 5239 5240 aoac_rpt->rpt_ver = c2h->rpt_ver; 5241 aoac_rpt->sec_type = c2h->sec_type; 5242 aoac_rpt->key_idx = c2h->key_idx; 5243 aoac_rpt->pattern_idx = c2h->pattern_idx; 5244 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok, 5245 RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX); 5246 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv)); 5247 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count, 5248 sizeof(aoac_rpt->eapol_key_replay_count)); 5249 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk)); 5250 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv)); 5251 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv)); 5252 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id); 5253 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn); 5254 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk)); 5255 5256 rtw89_complete_cond(wait, RTW89_WOW_WAIT_COND_AOAC, &data); 5257 } 5258 5259 static void 5260 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5261 { 5262 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5263 const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5264 struct rtw89_completion_data data = {}; 5265 enum rtw89_mac_mrc_status status; 5266 unsigned int cond; 5267 bool next = false; 5268 u32 tsf_high; 5269 u32 tsf_low; 5270 u8 sch_idx; 5271 u8 func; 5272 5273 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5274 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5275 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5276 tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5277 tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5278 5279 switch (status) { 5280 case RTW89_MAC_MRC_START_SCH_OK: 5281 func = H2C_FUNC_START_MRC; 5282 break; 5283 case RTW89_MAC_MRC_STOP_SCH_OK: 5284 /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5285 func = H2C_FUNC_DEL_MRC; 5286 next = true; 5287 break; 5288 case RTW89_MAC_MRC_DEL_SCH_OK: 5289 func = H2C_FUNC_DEL_MRC; 5290 break; 5291 case RTW89_MAC_MRC_EMPTY_SCH_FAIL: 5292 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5293 "MRC C2H STS RPT: empty sch fail\n"); 5294 return; 5295 case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL: 5296 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5297 "MRC C2H STS RPT: role not exist fail\n"); 5298 return; 5299 case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL: 5300 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5301 "MRC C2H STS RPT: data not found fail\n"); 5302 return; 5303 case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL: 5304 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5305 "MRC C2H STS RPT: get next slot fail\n"); 5306 return; 5307 case RTW89_MAC_MRC_ALT_ROLE_FAIL: 5308 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5309 "MRC C2H STS RPT: alt role fail\n"); 5310 return; 5311 case RTW89_MAC_MRC_ADD_PSTIMER_FAIL: 5312 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5313 "MRC C2H STS RPT: add ps timer fail\n"); 5314 return; 5315 case RTW89_MAC_MRC_MALLOC_FAIL: 5316 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5317 "MRC C2H STS RPT: malloc fail\n"); 5318 return; 5319 case RTW89_MAC_MRC_SWITCH_CH_FAIL: 5320 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5321 "MRC C2H STS RPT: switch ch fail\n"); 5322 return; 5323 case RTW89_MAC_MRC_TXNULL0_FAIL: 5324 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5325 "MRC C2H STS RPT: tx null-0 fail\n"); 5326 return; 5327 case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL: 5328 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5329 "MRC C2H STS RPT: port func en fail\n"); 5330 return; 5331 default: 5332 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5333 "invalid MRC C2H STS RPT: status %d\n", status); 5334 return; 5335 } 5336 5337 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5338 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 5339 sch_idx, status, (u64)tsf_high << 32 | tsf_low); 5340 5341 if (next) 5342 return; 5343 5344 cond = RTW89_MRC_WAIT_COND(sch_idx, func); 5345 rtw89_complete_cond(wait, cond, &data); 5346 } 5347 5348 static 5349 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5350 struct sk_buff *c2h, u32 len) = { 5351 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5352 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5353 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5354 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 5355 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5356 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5357 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5358 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5359 }; 5360 5361 static 5362 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5363 struct sk_buff *c2h, u32 len) = { 5364 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5365 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5366 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5367 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5368 }; 5369 5370 static 5371 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5372 struct sk_buff *c2h, u32 len) = { 5373 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5374 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5375 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5376 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5377 }; 5378 5379 static 5380 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 5381 struct sk_buff *c2h, u32 len) = { 5382 [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 5383 [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 5384 }; 5385 5386 static 5387 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev, 5388 struct sk_buff *c2h, u32 len) = { 5389 [RTW89_MAC_C2H_FUNC_AOAC_REPORT] = rtw89_mac_c2h_wow_aoac_rpt, 5390 }; 5391 5392 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 5393 struct sk_buff *skb) 5394 { 5395 const struct rtw89_c2h_scanofld *c2h = 5396 (const struct rtw89_c2h_scanofld *)skb->data; 5397 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5398 struct rtw89_completion_data data = {}; 5399 unsigned int cond; 5400 u8 status, reason; 5401 5402 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5403 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5404 data.err = status != RTW89_SCAN_STATUS_SUCCESS; 5405 5406 if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 5407 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 5408 cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 5409 else 5410 cond = RTW89_SCANOFLD_WAIT_COND_STOP; 5411 5412 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5413 } 5414 } 5415 5416 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5417 u8 class, u8 func) 5418 { 5419 switch (class) { 5420 default: 5421 return false; 5422 case RTW89_MAC_C2H_CLASS_INFO: 5423 switch (func) { 5424 default: 5425 return false; 5426 case RTW89_MAC_C2H_FUNC_REC_ACK: 5427 case RTW89_MAC_C2H_FUNC_DONE_ACK: 5428 return true; 5429 } 5430 case RTW89_MAC_C2H_CLASS_OFLD: 5431 switch (func) { 5432 default: 5433 return false; 5434 case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 5435 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 5436 return false; 5437 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 5438 return true; 5439 } 5440 case RTW89_MAC_C2H_CLASS_MCC: 5441 return true; 5442 case RTW89_MAC_C2H_CLASS_MRC: 5443 return true; 5444 case RTW89_MAC_C2H_CLASS_WOW: 5445 return true; 5446 } 5447 } 5448 5449 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5450 u32 len, u8 class, u8 func) 5451 { 5452 void (*handler)(struct rtw89_dev *rtwdev, 5453 struct sk_buff *c2h, u32 len) = NULL; 5454 5455 switch (class) { 5456 case RTW89_MAC_C2H_CLASS_INFO: 5457 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 5458 handler = rtw89_mac_c2h_info_handler[func]; 5459 break; 5460 case RTW89_MAC_C2H_CLASS_OFLD: 5461 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 5462 handler = rtw89_mac_c2h_ofld_handler[func]; 5463 break; 5464 case RTW89_MAC_C2H_CLASS_MCC: 5465 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 5466 handler = rtw89_mac_c2h_mcc_handler[func]; 5467 break; 5468 case RTW89_MAC_C2H_CLASS_MRC: 5469 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 5470 handler = rtw89_mac_c2h_mrc_handler[func]; 5471 break; 5472 case RTW89_MAC_C2H_CLASS_WOW: 5473 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_WOW) 5474 handler = rtw89_mac_c2h_wow_handler[func]; 5475 break; 5476 case RTW89_MAC_C2H_CLASS_FWDBG: 5477 return; 5478 default: 5479 rtw89_info(rtwdev, "c2h class %d not support\n", class); 5480 return; 5481 } 5482 if (!handler) { 5483 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 5484 func); 5485 return; 5486 } 5487 handler(rtwdev, skb, len); 5488 } 5489 5490 static 5491 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 5492 enum rtw89_phy_idx phy_idx, 5493 u32 reg_base, u32 *cr) 5494 { 5495 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 5496 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 5497 5498 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 5499 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 5500 addr); 5501 goto error; 5502 } 5503 5504 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 5505 if (mode == RTW89_QTA_SCC) { 5506 rtw89_err(rtwdev, 5507 "[TXPWR] addr=0x%x but hw not enable\n", 5508 addr); 5509 goto error; 5510 } 5511 5512 *cr = addr; 5513 return true; 5514 5515 error: 5516 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 5517 addr, phy_idx); 5518 5519 return false; 5520 } 5521 5522 static 5523 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 5524 { 5525 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 5526 int ret; 5527 5528 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5529 if (ret) 5530 return ret; 5531 5532 if (!enable) { 5533 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 5534 return 0; 5535 } 5536 5537 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 5538 B_AX_APP_MAC_INFO_RPT | 5539 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 5540 B_AX_PPDU_STAT_RPT_CRC32); 5541 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 5542 RTW89_PRPT_DEST_HOST); 5543 5544 return 0; 5545 } 5546 5547 static 5548 void __rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 5549 { 5550 #define MAC_AX_TIME_TH_SH 5 5551 #define MAC_AX_LEN_TH_SH 4 5552 #define MAC_AX_TIME_TH_MAX 255 5553 #define MAC_AX_LEN_TH_MAX 255 5554 #define MAC_AX_TIME_TH_DEF 88 5555 #define MAC_AX_LEN_TH_DEF 4080 5556 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5557 struct ieee80211_hw *hw = rtwdev->hw; 5558 u32 rts_threshold = hw->wiphy->rts_threshold; 5559 u32 time_th, len_th; 5560 u32 reg; 5561 5562 if (rts_threshold == (u32)-1) { 5563 time_th = MAC_AX_TIME_TH_DEF; 5564 len_th = MAC_AX_LEN_TH_DEF; 5565 } else { 5566 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 5567 len_th = rts_threshold; 5568 } 5569 5570 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 5571 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 5572 5573 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 5574 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 5575 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 5576 } 5577 5578 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev) 5579 { 5580 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 5581 if (rtwdev->dbcc_en) 5582 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_1); 5583 } 5584 5585 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 5586 { 5587 bool empty; 5588 int ret; 5589 5590 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5591 return; 5592 5593 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 5594 10000, 200000, false, rtwdev); 5595 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 5596 rtw89_info(rtwdev, "timed out to flush queues\n"); 5597 } 5598 5599 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 5600 { 5601 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 5602 u8 val; 5603 u16 val16; 5604 u32 val32; 5605 int ret; 5606 5607 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 5608 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5609 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 5610 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 5611 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 5612 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 5613 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5614 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 5615 5616 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 5617 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 5618 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 5619 5620 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 5621 if (ret) { 5622 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 5623 return ret; 5624 } 5625 val32 = val32 & B_AX_WL_RX_CTRL; 5626 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 5627 if (ret) { 5628 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 5629 return ret; 5630 } 5631 5632 switch (coex->pta_mode) { 5633 case RTW89_MAC_AX_COEX_RTK_MODE: 5634 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5635 val &= ~B_AX_BTMODE_MASK; 5636 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 5637 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5638 5639 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 5640 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 5641 5642 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 5643 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 5644 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 5645 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 5646 break; 5647 case RTW89_MAC_AX_COEX_CSR_MODE: 5648 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5649 val &= ~B_AX_BTMODE_MASK; 5650 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 5651 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5652 5653 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 5654 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 5655 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 5656 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 5657 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 5658 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 5659 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 5660 val16 |= B_AX_ENHANCED_BT; 5661 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 5662 5663 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 5664 break; 5665 default: 5666 return -EINVAL; 5667 } 5668 5669 switch (coex->direction) { 5670 case RTW89_MAC_AX_COEX_INNER: 5671 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5672 val = (val & ~BIT(2)) | BIT(1); 5673 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5674 break; 5675 case RTW89_MAC_AX_COEX_OUTPUT: 5676 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5677 val = val | BIT(1) | BIT(0); 5678 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5679 break; 5680 case RTW89_MAC_AX_COEX_INPUT: 5681 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5682 val = val & ~(BIT(2) | BIT(1)); 5683 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5684 break; 5685 default: 5686 return -EINVAL; 5687 } 5688 5689 return 0; 5690 } 5691 EXPORT_SYMBOL(rtw89_mac_coex_init); 5692 5693 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 5694 const struct rtw89_mac_ax_coex *coex) 5695 { 5696 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 5697 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 5698 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 5699 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 5700 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 5701 5702 switch (coex->pta_mode) { 5703 case RTW89_MAC_AX_COEX_RTK_MODE: 5704 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5705 MAC_AX_RTK_MODE); 5706 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 5707 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 5708 break; 5709 case RTW89_MAC_AX_COEX_CSR_MODE: 5710 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5711 MAC_AX_CSR_MODE); 5712 break; 5713 default: 5714 return -EINVAL; 5715 } 5716 5717 return 0; 5718 } 5719 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 5720 5721 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5722 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5723 { 5724 u32 val = 0, ret; 5725 5726 if (gnt_cfg->band[0].gnt_bt) 5727 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 5728 5729 if (gnt_cfg->band[0].gnt_bt_sw_en) 5730 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 5731 5732 if (gnt_cfg->band[0].gnt_wl) 5733 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 5734 5735 if (gnt_cfg->band[0].gnt_wl_sw_en) 5736 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 5737 5738 if (gnt_cfg->band[1].gnt_bt) 5739 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 5740 5741 if (gnt_cfg->band[1].gnt_bt_sw_en) 5742 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 5743 5744 if (gnt_cfg->band[1].gnt_wl) 5745 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 5746 5747 if (gnt_cfg->band[1].gnt_wl_sw_en) 5748 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 5749 5750 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 5751 if (ret) { 5752 rtw89_err(rtwdev, "Write LTE fail!\n"); 5753 return ret; 5754 } 5755 5756 return 0; 5757 } 5758 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 5759 5760 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 5761 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5762 { 5763 u32 val = 0; 5764 5765 if (gnt_cfg->band[0].gnt_bt) 5766 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5767 B_AX_GNT_BT_TX_VAL; 5768 else 5769 val |= B_AX_WL_ACT_VAL; 5770 5771 if (gnt_cfg->band[0].gnt_bt_sw_en) 5772 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5773 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5774 5775 if (gnt_cfg->band[0].gnt_wl) 5776 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5777 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5778 5779 if (gnt_cfg->band[0].gnt_wl_sw_en) 5780 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5781 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5782 5783 if (gnt_cfg->band[1].gnt_bt) 5784 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5785 B_AX_GNT_BT_TX_VAL; 5786 else 5787 val |= B_AX_WL_ACT_VAL; 5788 5789 if (gnt_cfg->band[1].gnt_bt_sw_en) 5790 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5791 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5792 5793 if (gnt_cfg->band[1].gnt_wl) 5794 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5795 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5796 5797 if (gnt_cfg->band[1].gnt_wl_sw_en) 5798 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5799 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5800 5801 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5802 5803 return 0; 5804 } 5805 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5806 5807 static 5808 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5809 { 5810 u32 reg; 5811 u16 val; 5812 int ret; 5813 5814 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5815 if (ret) 5816 return ret; 5817 5818 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 5819 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5820 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5821 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5822 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5823 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5824 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5825 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 5826 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 5827 B_AX_PLT_EN; 5828 rtw89_write16(rtwdev, reg, val); 5829 5830 return 0; 5831 } 5832 5833 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5834 { 5835 u32 fw_sb; 5836 5837 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5838 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5839 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5840 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5841 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5842 else 5843 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5844 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5845 val = B_AX_TOGGLE | 5846 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5847 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5848 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5849 fsleep(1000); /* avoid BT FW loss information */ 5850 } 5851 5852 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5853 { 5854 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5855 } 5856 5857 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5858 { 5859 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5860 5861 val = wl ? val | BIT(2) : val & ~BIT(2); 5862 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5863 5864 return 0; 5865 } 5866 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5867 5868 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5869 { 5870 struct rtw89_btc *btc = &rtwdev->btc; 5871 struct rtw89_btc_dm *dm = &btc->dm; 5872 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5873 int i; 5874 5875 if (wl) 5876 return 0; 5877 5878 for (i = 0; i < RTW89_PHY_MAX; i++) { 5879 g[i].gnt_bt_sw_en = 1; 5880 g[i].gnt_bt = 1; 5881 g[i].gnt_wl_sw_en = 1; 5882 g[i].gnt_wl = 0; 5883 } 5884 5885 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5886 } 5887 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5888 5889 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5890 { 5891 const struct rtw89_chip_info *chip = rtwdev->chip; 5892 u8 val = 0; 5893 5894 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) 5895 return false; 5896 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 5897 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5898 B_AX_LTE_MUX_CTRL_PATH >> 24); 5899 5900 return !!val; 5901 } 5902 5903 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 5904 { 5905 u32 reg; 5906 u16 cnt; 5907 5908 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 5909 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 5910 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 5911 5912 return cnt; 5913 } 5914 5915 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 5916 bool keep) 5917 { 5918 u32 reg; 5919 5920 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 5921 return; 5922 5923 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5924 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5925 if (keep) { 5926 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5927 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5928 BFRP_RX_STANDBY_TIMER_KEEP); 5929 } else { 5930 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5931 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5932 BFRP_RX_STANDBY_TIMER_RELEASE); 5933 } 5934 } 5935 5936 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5937 { 5938 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5939 u32 reg; 5940 u32 mask = mac->bfee_ctrl.mask; 5941 5942 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5943 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 5944 if (en) { 5945 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5946 rtw89_write32_set(rtwdev, reg, mask); 5947 } else { 5948 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5949 rtw89_write32_clr(rtwdev, reg, mask); 5950 } 5951 } 5952 5953 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 5954 { 5955 u32 reg; 5956 u32 val32; 5957 int ret; 5958 5959 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5960 if (ret) 5961 return ret; 5962 5963 /* AP mode set tx gid to 63 */ 5964 /* STA mode set tx gid to 0(default) */ 5965 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 5966 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5967 5968 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5969 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5970 5971 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5972 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5973 rtw89_write32(rtwdev, reg, val32); 5974 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5975 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5976 5977 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5978 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5979 B_AX_BFMEE_USE_NSTS | 5980 B_AX_BFMEE_CSI_GID_SEL | 5981 B_AX_BFMEE_CSI_FORCE_RETE_EN); 5982 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5983 rtw89_write32(rtwdev, reg, 5984 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5985 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5986 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5987 5988 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 5989 rtw89_write32_set(rtwdev, reg, 5990 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 5991 5992 return 0; 5993 } 5994 5995 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 5996 struct rtw89_vif_link *rtwvif_link, 5997 struct rtw89_sta_link *rtwsta_link) 5998 { 5999 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 6000 struct ieee80211_link_sta *link_sta; 6001 u8 mac_idx = rtwvif_link->mac_idx; 6002 u8 port_sel = rtwvif_link->port; 6003 u8 sound_dim = 3, t; 6004 u8 *phy_cap; 6005 u32 reg; 6006 u16 val; 6007 int ret; 6008 6009 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6010 if (ret) 6011 return ret; 6012 6013 rcu_read_lock(); 6014 6015 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6016 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; 6017 6018 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6019 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 6020 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 6021 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 6022 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 6023 phy_cap[5]); 6024 sound_dim = min(sound_dim, t); 6025 } 6026 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6027 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 6028 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 6029 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 6030 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 6031 link_sta->vht_cap.cap); 6032 sound_dim = min(sound_dim, t); 6033 } 6034 nc = min(nc, sound_dim); 6035 nr = min(nr, sound_dim); 6036 6037 rcu_read_unlock(); 6038 6039 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6040 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6041 6042 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 6043 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 6044 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 6045 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 6046 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 6047 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 6048 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 6049 6050 if (port_sel == 0) 6051 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6052 else 6053 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 6054 6055 rtw89_write16(rtwdev, reg, val); 6056 6057 return 0; 6058 } 6059 6060 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 6061 struct rtw89_vif_link *rtwvif_link, 6062 struct rtw89_sta_link *rtwsta_link) 6063 { 6064 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 6065 struct ieee80211_link_sta *link_sta; 6066 u8 mac_idx = rtwvif_link->mac_idx; 6067 u32 reg; 6068 int ret; 6069 6070 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6071 if (ret) 6072 return ret; 6073 6074 rcu_read_lock(); 6075 6076 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6077 6078 if (link_sta->he_cap.has_he) { 6079 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 6080 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 6081 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 6082 } 6083 if (link_sta->vht_cap.vht_supported) { 6084 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 6085 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 6086 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 6087 } 6088 if (link_sta->ht_cap.ht_supported) { 6089 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 6090 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 6091 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 6092 } 6093 6094 rcu_read_unlock(); 6095 6096 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6097 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6098 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 6099 rtw89_write32(rtwdev, 6100 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 6101 rrsc); 6102 6103 return 0; 6104 } 6105 6106 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 6107 struct rtw89_vif_link *rtwvif_link, 6108 struct rtw89_sta_link *rtwsta_link) 6109 { 6110 struct ieee80211_link_sta *link_sta; 6111 bool has_beamformer_cap; 6112 6113 rcu_read_lock(); 6114 6115 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6116 has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta); 6117 6118 rcu_read_unlock(); 6119 6120 if (has_beamformer_cap) { 6121 rtw89_debug(rtwdev, RTW89_DBG_BF, 6122 "initialize bfee for new association\n"); 6123 rtw89_mac_init_bfee_ax(rtwdev, rtwvif_link->mac_idx); 6124 rtw89_mac_set_csi_para_reg_ax(rtwdev, rtwvif_link, rtwsta_link); 6125 rtw89_mac_csi_rrsc_ax(rtwdev, rtwvif_link, rtwsta_link); 6126 } 6127 } 6128 6129 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, 6130 struct rtw89_vif_link *rtwvif_link, 6131 struct rtw89_sta_link *rtwsta_link) 6132 { 6133 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, false); 6134 } 6135 6136 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6137 struct ieee80211_bss_conf *conf) 6138 { 6139 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 6140 struct rtw89_vif_link *rtwvif_link; 6141 u8 mac_idx; 6142 __le32 *p; 6143 6144 rtwvif_link = rtwvif->links[conf->link_id]; 6145 if (unlikely(!rtwvif_link)) { 6146 rtw89_err(rtwdev, 6147 "%s: rtwvif link (link_id %u) is not active\n", 6148 __func__, conf->link_id); 6149 return; 6150 } 6151 6152 mac_idx = rtwvif_link->mac_idx; 6153 6154 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 6155 6156 p = (__le32 *)conf->mu_group.membership; 6157 rtw89_write32(rtwdev, 6158 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 6159 le32_to_cpu(p[0])); 6160 rtw89_write32(rtwdev, 6161 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 6162 le32_to_cpu(p[1])); 6163 6164 p = (__le32 *)conf->mu_group.position; 6165 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 6166 le32_to_cpu(p[0])); 6167 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 6168 le32_to_cpu(p[1])); 6169 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 6170 le32_to_cpu(p[2])); 6171 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 6172 le32_to_cpu(p[3])); 6173 } 6174 6175 struct rtw89_mac_bf_monitor_iter_data { 6176 struct rtw89_dev *rtwdev; 6177 struct rtw89_sta_link *down_rtwsta_link; 6178 int count; 6179 }; 6180 6181 static 6182 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 6183 { 6184 struct rtw89_mac_bf_monitor_iter_data *iter_data = 6185 (struct rtw89_mac_bf_monitor_iter_data *)data; 6186 struct rtw89_sta_link *down_rtwsta_link = iter_data->down_rtwsta_link; 6187 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6188 struct ieee80211_link_sta *link_sta; 6189 struct rtw89_sta_link *rtwsta_link; 6190 bool has_beamformer_cap = false; 6191 int *count = &iter_data->count; 6192 unsigned int link_id; 6193 6194 rcu_read_lock(); 6195 6196 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6197 if (rtwsta_link == down_rtwsta_link) 6198 continue; 6199 6200 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 6201 if (rtw89_sta_has_beamformer_cap(link_sta)) { 6202 has_beamformer_cap = true; 6203 break; 6204 } 6205 } 6206 6207 if (has_beamformer_cap) 6208 (*count)++; 6209 6210 rcu_read_unlock(); 6211 } 6212 6213 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 6214 struct rtw89_sta_link *rtwsta_link, 6215 bool disconnect) 6216 { 6217 struct rtw89_mac_bf_monitor_iter_data data; 6218 6219 data.rtwdev = rtwdev; 6220 data.down_rtwsta_link = disconnect ? rtwsta_link : NULL; 6221 data.count = 0; 6222 ieee80211_iterate_stations_atomic(rtwdev->hw, 6223 rtw89_mac_bf_monitor_calc_iter, 6224 &data); 6225 6226 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 6227 if (data.count) 6228 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6229 else 6230 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6231 } 6232 6233 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 6234 { 6235 struct rtw89_traffic_stats *stats = &rtwdev->stats; 6236 struct rtw89_vif_link *rtwvif_link; 6237 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 6238 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6239 struct rtw89_vif *rtwvif; 6240 bool keep_timer = true; 6241 unsigned int link_id; 6242 bool old_keep_timer; 6243 6244 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6245 6246 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 6247 keep_timer = false; 6248 6249 if (keep_timer != old_keep_timer) { 6250 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6251 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6252 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif_link->mac_idx, 6253 keep_timer); 6254 } 6255 6256 if (en == old) 6257 return; 6258 6259 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6260 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6261 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, en); 6262 } 6263 6264 static int 6265 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6266 u32 tx_time) 6267 { 6268 #define MAC_AX_DFLT_TX_TIME 5280 6269 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6270 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 6271 u32 reg; 6272 int ret = 0; 6273 6274 if (rtwsta_link->cctl_tx_time) { 6275 rtwsta_link->ampdu_max_time = (max_tx_time - 512) >> 9; 6276 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6277 } else { 6278 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6279 if (ret) { 6280 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 6281 return ret; 6282 } 6283 6284 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6285 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 6286 max_tx_time >> 5); 6287 } 6288 6289 return ret; 6290 } 6291 6292 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6293 bool resume, u32 tx_time) 6294 { 6295 int ret = 0; 6296 6297 if (!resume) { 6298 rtwsta_link->cctl_tx_time = true; 6299 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6300 } else { 6301 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6302 rtwsta_link->cctl_tx_time = false; 6303 } 6304 6305 return ret; 6306 } 6307 6308 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6309 u32 *tx_time) 6310 { 6311 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6312 u32 reg; 6313 int ret = 0; 6314 6315 if (rtwsta_link->cctl_tx_time) { 6316 *tx_time = (rtwsta_link->ampdu_max_time + 1) << 9; 6317 } else { 6318 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6319 if (ret) { 6320 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 6321 return ret; 6322 } 6323 6324 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6325 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 6326 } 6327 6328 return ret; 6329 } 6330 6331 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 6332 struct rtw89_sta_link *rtwsta_link, 6333 bool resume, u8 tx_retry) 6334 { 6335 int ret = 0; 6336 6337 rtwsta_link->data_tx_cnt_lmt = tx_retry; 6338 6339 if (!resume) { 6340 rtwsta_link->cctl_tx_retry_limit = true; 6341 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6342 } else { 6343 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6344 rtwsta_link->cctl_tx_retry_limit = false; 6345 } 6346 6347 return ret; 6348 } 6349 6350 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 6351 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry) 6352 { 6353 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6354 u32 reg; 6355 int ret = 0; 6356 6357 if (rtwsta_link->cctl_tx_retry_limit) { 6358 *tx_retry = rtwsta_link->data_tx_cnt_lmt; 6359 } else { 6360 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6361 if (ret) { 6362 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 6363 return ret; 6364 } 6365 6366 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); 6367 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 6368 } 6369 6370 return ret; 6371 } 6372 6373 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 6374 struct rtw89_vif_link *rtwvif_link, bool en) 6375 { 6376 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6377 u8 mac_idx = rtwvif_link->mac_idx; 6378 u16 set = mac->muedca_ctrl.mask; 6379 u32 reg; 6380 u32 ret; 6381 6382 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6383 if (ret) 6384 return ret; 6385 6386 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 6387 if (en) 6388 rtw89_write16_set(rtwdev, reg, set); 6389 else 6390 rtw89_write16_clr(rtwdev, reg, set); 6391 6392 return 0; 6393 } 6394 6395 static 6396 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 6397 { 6398 u32 val32; 6399 int ret; 6400 6401 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6402 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 6403 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 6404 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 6405 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6406 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6407 6408 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6409 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6410 if (ret) { 6411 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 6412 offset, val, mask); 6413 return ret; 6414 } 6415 6416 return 0; 6417 } 6418 6419 static 6420 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 6421 { 6422 u32 val32; 6423 int ret; 6424 6425 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6426 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 6427 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 6428 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 6429 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6430 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6431 6432 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6433 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6434 if (ret) { 6435 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 6436 return ret; 6437 } 6438 6439 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 6440 6441 return 0; 6442 } 6443 6444 static 6445 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, 6446 struct rtw89_vif_link *rtwvif_link, 6447 struct rtw89_sta_link *rtwsta_link) 6448 { 6449 static const enum rtw89_pkt_drop_sel sels[] = { 6450 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 6451 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 6452 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 6453 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 6454 }; 6455 struct rtw89_pkt_drop_params params = {0}; 6456 int i; 6457 6458 params.mac_band = rtwvif_link->mac_idx; 6459 params.macid = rtwsta_link->mac_id; 6460 params.port = rtwvif_link->port; 6461 params.mbssid = 0; 6462 params.tf_trs = rtwvif_link->trigger; 6463 6464 for (i = 0; i < ARRAY_SIZE(sels); i++) { 6465 params.sel = sels[i]; 6466 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6467 } 6468 } 6469 6470 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 6471 { 6472 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6473 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6474 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6475 struct rtw89_vif_link *rtwvif_link; 6476 struct rtw89_sta_link *rtwsta_link; 6477 struct rtw89_vif *target = data; 6478 unsigned int link_id; 6479 6480 if (rtwvif != target) 6481 return; 6482 6483 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6484 rtwvif_link = rtwsta_link->rtwvif_link; 6485 rtw89_mac_pkt_drop_sta(rtwdev, rtwvif_link, rtwsta_link); 6486 } 6487 } 6488 6489 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 6490 { 6491 ieee80211_iterate_stations_atomic(rtwdev->hw, 6492 rtw89_mac_pkt_drop_vif_iter, 6493 rtwvif); 6494 } 6495 6496 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 6497 enum rtw89_mac_idx band) 6498 { 6499 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6500 struct rtw89_pkt_drop_params params = {0}; 6501 bool empty; 6502 int i, ret = 0, try_cnt = 3; 6503 6504 params.mac_band = band; 6505 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 6506 6507 for (i = 0; i < try_cnt; i++) { 6508 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 6509 50000, false, rtwdev); 6510 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 6511 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6512 else 6513 return 0; 6514 } 6515 return ret; 6516 } 6517 6518 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 6519 { 6520 struct rtw89_mac_h2c_info h2c_info = {}; 6521 struct rtw89_mac_c2h_info c2h_info = {}; 6522 u32 ret; 6523 6524 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 6525 return 0; 6526 6527 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; 6528 h2c_info.content_len = sizeof(h2c_info.u.hdr); 6529 h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); 6530 6531 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 6532 if (ret) 6533 return ret; 6534 6535 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) 6536 ret = -EINVAL; 6537 6538 return ret; 6539 } 6540 6541 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 6542 { 6543 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6544 const struct rtw89_chip_info *chip = rtwdev->chip; 6545 int ret; 6546 6547 if (enable_wow) { 6548 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 6549 if (ret) { 6550 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6551 return ret; 6552 } 6553 6554 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6555 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6556 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 6557 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 6558 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 6559 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 6560 rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 6561 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 6562 6563 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 6564 return 0; 6565 6566 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6567 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 6568 else 6569 rtw89_write32_set(rtwdev, R_AX_DBG_WOW, 6570 B_AX_DBG_WOW_CPU_IO_RX_EN); 6571 } else { 6572 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 6573 if (ret) { 6574 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6575 return ret; 6576 } 6577 6578 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6579 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6580 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 6581 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 6582 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 6583 } 6584 6585 return 0; 6586 } 6587 6588 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 6589 { 6590 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 6591 6592 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 6593 } 6594 6595 static 6596 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 6597 bool h2c_or_fwdl) 6598 { 6599 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 6600 u8 val; 6601 6602 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 6603 1, FWDL_WAIT_CNT, false, 6604 rtwdev, R_AX_WCPU_FW_CTRL); 6605 } 6606 6607 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 6608 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 6609 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 6610 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 6611 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 6612 .rx_fltr = R_AX_RX_FLTR_OPT, 6613 .port_base = &rtw89_port_base_ax, 6614 .agg_len_ht = R_AX_AGG_LEN_HT_0, 6615 .ps_status = R_AX_PPWRBIT_SETTING, 6616 6617 .muedca_ctrl = { 6618 .addr = R_AX_MUEDCA_EN, 6619 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 6620 }, 6621 .bfee_ctrl = { 6622 .addr = R_AX_BFMEE_RESP_OPTION, 6623 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 6624 B_AX_BFMEE_HE_NDPA_EN, 6625 }, 6626 .narrow_bw_ru_dis = { 6627 .addr = R_AX_RXTRIG_TEST_USER_2, 6628 .mask = B_AX_RXTRIG_RU26_DIS, 6629 }, 6630 .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 6631 6632 .check_mac_en = rtw89_mac_check_mac_en_ax, 6633 .sys_init = sys_init_ax, 6634 .trx_init = trx_init_ax, 6635 .hci_func_en = rtw89_mac_hci_func_en_ax, 6636 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 6637 .dle_func_en = dle_func_en_ax, 6638 .dle_clk_en = dle_clk_en_ax, 6639 .bf_assoc = rtw89_mac_bf_assoc_ax, 6640 6641 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 6642 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 6643 6644 .dle_mix_cfg = dle_mix_cfg_ax, 6645 .chk_dle_rdy = chk_dle_rdy_ax, 6646 .dle_buf_req = dle_buf_req_ax, 6647 .hfc_func_en = hfc_func_en_ax, 6648 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 6649 .hfc_mix_cfg = hfc_mix_cfg_ax, 6650 .hfc_get_mix_info = hfc_get_mix_info_ax, 6651 .wde_quota_cfg = wde_quota_cfg_ax, 6652 .ple_quota_cfg = ple_quota_cfg_ax, 6653 .set_cpuio = set_cpuio_ax, 6654 .dle_quota_change = dle_quota_change_ax, 6655 6656 .disable_cpu = rtw89_mac_disable_cpu_ax, 6657 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 6658 .fwdl_get_status = rtw89_fw_get_rdy_ax, 6659 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 6660 .parse_efuse_map = rtw89_parse_efuse_map_ax, 6661 .parse_phycap_map = rtw89_parse_phycap_map_ax, 6662 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 6663 6664 .cfg_plt = rtw89_mac_cfg_plt_ax, 6665 .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 6666 6667 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 6668 6669 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 6670 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 6671 6672 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 6673 .dump_err_status = rtw89_mac_dump_err_status_ax, 6674 6675 .is_txq_empty = mac_is_txq_empty_ax, 6676 6677 .add_chan_list = rtw89_hw_scan_add_chan_list_ax, 6678 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_ax, 6679 .scan_offload = rtw89_fw_h2c_scan_offload_ax, 6680 6681 .wow_config_mac = rtw89_wow_config_mac_ax, 6682 }; 6683 EXPORT_SYMBOL(rtw89_mac_gen_ax); 6684