1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "phy.h" 13 #include "ps.h" 14 #include "reg.h" 15 #include "ser.h" 16 #include "util.h" 17 18 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 19 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 20 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 21 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 22 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 23 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 24 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 26 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 28 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 29 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 30 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 31 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 35 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 36 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 37 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 38 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 39 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 40 }; 41 42 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 43 u32 val, enum rtw89_mac_mem_sel sel) 44 { 45 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 46 u32 addr = mac->mem_base_addrs[sel] + offset; 47 48 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 49 rtw89_write32(rtwdev, mac->indir_access_addr, val); 50 } 51 52 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 53 enum rtw89_mac_mem_sel sel) 54 { 55 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 56 u32 addr = mac->mem_base_addrs[sel] + offset; 57 58 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 59 return rtw89_read32(rtwdev, mac->indir_access_addr); 60 } 61 62 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 63 enum rtw89_mac_hwmod_sel sel) 64 { 65 u32 val, r_val; 66 67 if (sel == RTW89_DMAC_SEL) { 68 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 69 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 70 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 71 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 72 val = B_AX_CMAC_EN; 73 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 74 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 75 val = B_AX_CMAC1_FEN; 76 } else { 77 return -EINVAL; 78 } 79 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 80 (val & r_val) != val) 81 return -EFAULT; 82 83 return 0; 84 } 85 86 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 87 { 88 u8 lte_ctrl; 89 int ret; 90 91 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 92 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 93 if (ret && !test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 94 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 95 96 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 97 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 98 99 return ret; 100 } 101 102 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 103 { 104 u8 lte_ctrl; 105 int ret; 106 107 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 108 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 109 if (ret && !test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 110 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 111 112 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 113 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 114 115 return ret; 116 } 117 118 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 119 { 120 u32 ctrl_reg, data_reg, ctrl_data; 121 u32 val; 122 int ret; 123 124 switch (ctrl->type) { 125 case DLE_CTRL_TYPE_WDE: 126 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 127 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 128 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 129 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 130 B_AX_WDE_DFI_ACTIVE; 131 break; 132 case DLE_CTRL_TYPE_PLE: 133 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 134 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 135 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 136 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 137 B_AX_PLE_DFI_ACTIVE; 138 break; 139 default: 140 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 141 return -EINVAL; 142 } 143 144 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 145 146 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 147 1, 1000, false, rtwdev, ctrl_reg); 148 if (ret) { 149 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 150 ctrl_reg, ctrl_data); 151 return ret; 152 } 153 154 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 155 return 0; 156 } 157 158 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 159 struct rtw89_mac_dle_dfi_quota *quota) 160 { 161 struct rtw89_mac_dle_dfi_ctrl ctrl; 162 int ret; 163 164 ctrl.type = quota->dle_type; 165 ctrl.target = DLE_DFI_TYPE_QUOTA; 166 ctrl.addr = quota->qtaid; 167 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 168 if (ret) { 169 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 170 return ret; 171 } 172 173 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 174 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 175 return 0; 176 } 177 178 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 179 struct rtw89_mac_dle_dfi_qempty *qempty) 180 { 181 struct rtw89_mac_dle_dfi_ctrl ctrl; 182 int ret; 183 184 ctrl.type = qempty->dle_type; 185 ctrl.target = DLE_DFI_TYPE_QEMPTY; 186 ctrl.addr = qempty->grpsel; 187 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 188 if (ret) { 189 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 190 return ret; 191 } 192 193 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 194 return 0; 195 } 196 197 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 198 { 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 201 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 202 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 205 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 206 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 209 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 210 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 211 } 212 213 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 214 { 215 struct rtw89_mac_dle_dfi_qempty qempty; 216 struct rtw89_mac_dle_dfi_quota quota; 217 struct rtw89_mac_dle_dfi_ctrl ctrl; 218 u32 val, not_empty, i; 219 int ret; 220 221 qempty.dle_type = DLE_CTRL_TYPE_PLE; 222 qempty.grpsel = 0; 223 qempty.qempty = ~(u32)0; 224 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 225 if (ret) 226 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 227 else 228 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 229 230 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 231 if (!(not_empty & BIT(0))) 232 continue; 233 ctrl.type = DLE_CTRL_TYPE_PLE; 234 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 235 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 236 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 237 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 238 if (ret) 239 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 240 else 241 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 242 u32_get_bits(ctrl.out_data, 243 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 244 } 245 246 quota.dle_type = DLE_CTRL_TYPE_PLE; 247 quota.qtaid = 6; 248 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 249 if (ret) 250 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 251 else 252 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 253 quota.rsv_pgnum, quota.use_pgnum); 254 255 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 257 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 258 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 259 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 260 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 261 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 262 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 263 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 264 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 265 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 266 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 267 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 268 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 269 270 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 271 quota.dle_type = DLE_CTRL_TYPE_PLE; 272 quota.qtaid = 7; 273 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 274 if (ret) 275 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 276 else 277 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 278 quota.rsv_pgnum, quota.use_pgnum); 279 280 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 282 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 283 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 284 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 285 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 286 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 287 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 288 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 289 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 290 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 291 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 292 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 293 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 294 } 295 296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 298 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 299 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 300 301 dump_err_status_dispatcher_ax(rtwdev); 302 } 303 304 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 305 enum mac_ax_err_info err) 306 { 307 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 308 u32 dbg, event; 309 310 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 311 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 312 313 switch (event) { 314 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 315 rtw89_info(rtwdev, "quota lost!\n"); 316 mac->dump_qta_lost(rtwdev); 317 break; 318 default: 319 break; 320 } 321 } 322 323 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 324 { 325 const struct rtw89_chip_info *chip = rtwdev->chip; 326 u32 dmac_err; 327 int i, ret; 328 329 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 330 if (ret) { 331 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 332 return; 333 } 334 335 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 336 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 337 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 339 340 if (dmac_err) { 341 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 343 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 344 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 345 if (chip->chip_id == RTL8852C) { 346 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 348 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 352 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 353 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 354 } 355 } 356 357 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 360 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 361 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 362 if (chip->chip_id == RTL8852C) 363 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 364 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 365 else 366 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 367 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 368 } 369 370 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 371 if (chip->chip_id == RTL8852C) { 372 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 374 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 376 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 378 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 380 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 382 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 384 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 386 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 388 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 389 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 390 391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392 B_AX_DBG_SEL0, 0x8B); 393 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 394 B_AX_DBG_SEL1, 0x8B); 395 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 396 B_AX_SEL_0XC0_MASK, 1); 397 for (i = 0; i < 0x10; i++) { 398 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 399 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 400 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 401 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 402 } 403 } else if (chip->chip_id == RTL8922A) { 404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 406 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 407 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 408 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 409 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 410 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 411 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 412 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 413 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 414 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 415 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 416 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 417 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 418 } else { 419 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 421 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 423 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 425 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 427 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 429 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 430 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 431 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 432 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 433 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 435 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 437 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 438 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 439 } 440 } 441 442 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 445 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 449 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 450 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 451 } 452 453 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 454 if (chip->chip_id == RTL8922A) { 455 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 456 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 457 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 458 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 459 } else { 460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 462 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 463 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 464 } 465 } 466 467 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 468 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 470 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 471 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 472 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 474 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 475 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 476 } 477 478 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 479 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 486 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 487 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 488 } else { 489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 491 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 492 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 493 } 494 } 495 496 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 497 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 499 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 501 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 503 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 509 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 510 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 515 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 516 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 517 if (chip->chip_id == RTL8922A) { 518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 520 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 521 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 522 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 524 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 525 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 526 } else { 527 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 529 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 530 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 531 if (chip->chip_id == RTL8852C) { 532 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 533 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 534 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 535 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 536 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 537 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 538 } else { 539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 543 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 544 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 545 } 546 } 547 } 548 549 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 552 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 553 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 554 } 555 556 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 557 if (chip->chip_id == RTL8922A) { 558 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 559 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 560 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 561 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 562 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 563 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 564 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 565 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 566 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 567 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 568 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 569 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 570 } else { 571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 573 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 574 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 577 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 578 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 581 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 582 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 583 } 584 } 585 586 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 587 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 590 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 591 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 594 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 595 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 598 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 599 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 600 } else { 601 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 602 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 605 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 606 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 609 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 610 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 611 } 612 if (chip->chip_id == RTL8922A) { 613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 615 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 616 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 617 } 618 } 619 620 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 621 if (chip->chip_id == RTL8922A) { 622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 624 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 625 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 626 } else if (chip->chip_id == RTL8852C) { 627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 629 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 630 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 631 } 632 } 633 634 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 635 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 636 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 637 RTW89_MAC_MEM_AXIDMA)); 638 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 639 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 640 RTW89_MAC_MEM_AXIDMA)); 641 } 642 643 if (dmac_err & B_BE_MLO_ERR_INT) { 644 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 646 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 647 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 648 } 649 650 if (dmac_err & B_BE_PLRLS_ERR_INT) { 651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 653 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 654 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 655 } 656 } 657 658 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 659 u8 band) 660 { 661 const struct rtw89_chip_info *chip = rtwdev->chip; 662 u32 offset = 0; 663 u32 cmac_err; 664 int ret; 665 666 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 667 if (ret) { 668 if (band) 669 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 670 else 671 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 672 return; 673 } 674 675 if (band) 676 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 677 678 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 679 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 680 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 681 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 682 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 683 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 684 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 685 686 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 689 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 690 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 691 } 692 693 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 694 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 695 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 696 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 697 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 698 } 699 700 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 701 if (chip->chip_id == RTL8852C) { 702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 704 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 705 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 706 } else { 707 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 708 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 709 } 710 } 711 712 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 713 if (chip->chip_id == RTL8852C) { 714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 716 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 717 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 718 } else { 719 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 720 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 721 } 722 } 723 724 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 725 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 726 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 727 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 728 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 729 } 730 731 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 732 if (chip->chip_id == RTL8852C) { 733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 735 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 736 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 737 } else { 738 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 739 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 740 } 741 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 742 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 743 } 744 745 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 746 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 747 } 748 749 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 750 enum mac_ax_err_info err) 751 { 752 if (err != MAC_AX_ERR_L1_ERR_DMAC && 753 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 754 err != MAC_AX_ERR_L0_ERR_CMAC0 && 755 err != MAC_AX_ERR_L0_ERR_CMAC1 && 756 err != MAC_AX_ERR_RXI300) 757 return; 758 759 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 762 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 763 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 764 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 766 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 767 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 768 769 rtw89_mac_dump_dmac_err_status(rtwdev); 770 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 771 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 772 773 rtwdev->hci.ops->dump_err_status(rtwdev); 774 775 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 776 rtw89_mac_dump_l0_to_l1(rtwdev, err); 777 778 rtw89_info(rtwdev, "<---\n"); 779 } 780 781 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 782 { 783 struct rtw89_ser *ser = &rtwdev->ser; 784 u32 dmac_err, imr, isr; 785 int ret; 786 787 if (rtwdev->chip->chip_id == RTL8852C) { 788 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 789 if (ret) 790 return true; 791 792 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 793 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 794 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 795 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 796 797 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 798 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 799 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 800 return true; 801 } 802 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 803 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 804 return true; 805 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 806 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 807 return true; 808 } 809 } 810 811 return false; 812 } 813 814 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 815 { 816 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 817 u32 err, err_scnr; 818 int ret; 819 820 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 821 false, rtwdev, R_AX_HALT_C2H_CTRL); 822 if (ret) { 823 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 824 return ret; 825 } 826 827 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 828 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 829 830 err_scnr = RTW89_ERROR_SCENARIO(err); 831 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 832 err = MAC_AX_ERR_CPU_EXCEPTION; 833 else if (err_scnr == RTW89_WCPU_ASSERTION) 834 err = MAC_AX_ERR_ASSERTION; 835 else if (err_scnr == RTW89_RXI300_ERROR) 836 err = MAC_AX_ERR_RXI300; 837 838 if (rtw89_mac_suppress_log(rtwdev, err)) 839 return err; 840 841 rtw89_fw_st_dbg_dump(rtwdev); 842 mac->dump_err_status(rtwdev, err); 843 844 return err; 845 } 846 EXPORT_SYMBOL(rtw89_mac_get_err_status); 847 848 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 849 { 850 struct rtw89_ser *ser = &rtwdev->ser; 851 u32 halt; 852 int ret = 0; 853 854 if (err > MAC_AX_SET_ERR_MAX) { 855 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 856 return -EINVAL; 857 } 858 859 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 860 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 861 if (ret) { 862 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 863 return -EFAULT; 864 } 865 866 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 867 868 if (ser->prehandle_l1 && 869 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 870 return 0; 871 872 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 873 874 return 0; 875 } 876 EXPORT_SYMBOL(rtw89_mac_set_err_status); 877 878 static int hfc_reset_param(struct rtw89_dev *rtwdev) 879 { 880 const struct rtw89_hfc_param_ini *param_ini, *param_inis; 881 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 882 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 883 884 param_inis = rtwdev->chip->hfc_param_ini[rtwdev->hci.type]; 885 if (!param_inis) 886 return -EINVAL; 887 888 param_ini = ¶m_inis[qta_mode]; 889 890 param->en = 0; 891 892 if (param_ini->pub_cfg) 893 param->pub_cfg = *param_ini->pub_cfg; 894 895 if (param_ini->prec_cfg) 896 param->prec_cfg = *param_ini->prec_cfg; 897 898 if (param_ini->ch_cfg) 899 param->ch_cfg = param_ini->ch_cfg; 900 901 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 902 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 903 param->mode = param_ini->mode; 904 905 return 0; 906 } 907 908 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 909 { 910 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 911 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 912 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 913 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 914 915 if (ch >= RTW89_DMA_CH_NUM) 916 return -EINVAL; 917 918 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 919 ch_cfg[ch].max > pub_cfg->pub_max) 920 return -EINVAL; 921 if (ch_cfg[ch].grp >= grp_num) 922 return -EINVAL; 923 924 return 0; 925 } 926 927 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 928 { 929 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 930 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 931 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 932 933 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 934 if (rtwdev->chip->chip_id == RTL8852A) 935 return 0; 936 else 937 return -EFAULT; 938 } 939 940 return 0; 941 } 942 943 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 944 { 945 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 946 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 947 948 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 949 return -EFAULT; 950 951 return 0; 952 } 953 954 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 955 { 956 const struct rtw89_chip_info *chip = rtwdev->chip; 957 const struct rtw89_page_regs *regs = chip->page_regs; 958 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 959 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 960 int ret = 0; 961 u32 val = 0; 962 963 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 964 if (ret) 965 return ret; 966 967 ret = hfc_ch_cfg_chk(rtwdev, ch); 968 if (ret) 969 return ret; 970 971 if (ch > RTW89_DMA_B1HI) 972 return -EINVAL; 973 974 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 975 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 976 (cfg[ch].grp ? B_AX_GRP : 0); 977 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 978 979 return 0; 980 } 981 982 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 983 { 984 const struct rtw89_chip_info *chip = rtwdev->chip; 985 const struct rtw89_page_regs *regs = chip->page_regs; 986 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 987 struct rtw89_hfc_ch_info *info = param->ch_info; 988 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 989 u32 val; 990 int ret; 991 992 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 993 if (ret) 994 return ret; 995 996 if (ch > RTW89_DMA_H2C) 997 return -EINVAL; 998 999 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 1000 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1001 if (ch < RTW89_DMA_H2C) 1002 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1003 else 1004 info[ch].used = cfg[ch].min - info[ch].aval; 1005 1006 return 0; 1007 } 1008 1009 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1010 { 1011 const struct rtw89_chip_info *chip = rtwdev->chip; 1012 const struct rtw89_page_regs *regs = chip->page_regs; 1013 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1014 u32 val; 1015 int ret; 1016 1017 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1018 if (ret) 1019 return ret; 1020 1021 ret = hfc_pub_cfg_chk(rtwdev); 1022 if (ret) 1023 return ret; 1024 1025 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1026 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1027 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1028 1029 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1030 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1031 1032 return 0; 1033 } 1034 1035 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1036 { 1037 const struct rtw89_chip_info *chip = rtwdev->chip; 1038 const struct rtw89_page_regs *regs = chip->page_regs; 1039 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1040 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1041 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1042 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1043 u32 val; 1044 1045 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1046 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1047 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1048 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1049 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1050 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1051 info->pub_aval = 1052 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1053 B_AX_PUB_AVAL_PG_MASK); 1054 info->wp_aval = 1055 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1056 B_AX_WP_AVAL_PG_MASK); 1057 1058 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1059 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1060 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1061 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1062 prec_cfg->ch011_full_cond = 1063 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1064 prec_cfg->h2c_full_cond = 1065 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1066 prec_cfg->wp_ch07_full_cond = 1067 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1068 prec_cfg->wp_ch811_full_cond = 1069 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1070 1071 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1072 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1073 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1074 1075 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1076 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1077 1078 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1079 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1080 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1081 1082 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1083 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1084 1085 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1086 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1087 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1088 } 1089 1090 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1091 { 1092 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1093 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1094 int ret; 1095 1096 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1097 if (ret) 1098 return ret; 1099 1100 mac->hfc_get_mix_info(rtwdev); 1101 1102 ret = hfc_pub_info_chk(rtwdev); 1103 if (param->en && ret) 1104 return ret; 1105 1106 return 0; 1107 } 1108 1109 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1110 { 1111 const struct rtw89_chip_info *chip = rtwdev->chip; 1112 const struct rtw89_page_regs *regs = chip->page_regs; 1113 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1114 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1115 u32 val; 1116 1117 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1118 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1119 1120 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1121 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1122 prec_cfg->h2c_full_cond); 1123 } 1124 1125 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1126 { 1127 const struct rtw89_chip_info *chip = rtwdev->chip; 1128 const struct rtw89_page_regs *regs = chip->page_regs; 1129 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1130 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1131 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1132 u32 val; 1133 1134 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1135 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1136 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1137 1138 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1139 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1140 1141 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1142 B_AX_PREC_PAGE_WP_CH07_MASK) | 1143 u32_encode_bits(prec_cfg->wp_ch811_prec, 1144 B_AX_PREC_PAGE_WP_CH811_MASK); 1145 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1146 1147 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1148 param->mode, B_AX_HCI_FC_MODE_MASK); 1149 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1150 B_AX_HCI_FC_WD_FULL_COND_MASK); 1151 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1152 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1153 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1154 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1155 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1156 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1157 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1158 } 1159 1160 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1161 { 1162 const struct rtw89_chip_info *chip = rtwdev->chip; 1163 const struct rtw89_page_regs *regs = chip->page_regs; 1164 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1165 u32 val; 1166 1167 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1168 param->en = en; 1169 param->h2c_en = h2c_en; 1170 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1171 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1172 (val & ~B_AX_HCI_FC_CH12_EN); 1173 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1174 } 1175 1176 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1177 { 1178 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1179 const struct rtw89_chip_info *chip = rtwdev->chip; 1180 u32 dma_ch_mask = chip->dma_ch_mask; 1181 int ret = 0; 1182 u8 ch; 1183 1184 if (reset) 1185 ret = hfc_reset_param(rtwdev); 1186 if (ret) 1187 return ret; 1188 1189 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1190 if (ret) 1191 return ret; 1192 1193 mac->hfc_func_en(rtwdev, false, false); 1194 1195 if (!en && h2c_en) { 1196 mac->hfc_h2c_cfg(rtwdev); 1197 mac->hfc_func_en(rtwdev, en, h2c_en); 1198 return 0; 1199 } 1200 1201 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1202 if (dma_ch_mask & BIT(ch)) 1203 continue; 1204 ret = hfc_ch_ctrl(rtwdev, ch); 1205 if (ret) 1206 return ret; 1207 } 1208 1209 ret = hfc_pub_ctrl(rtwdev); 1210 if (ret) 1211 return ret; 1212 1213 mac->hfc_mix_cfg(rtwdev); 1214 if (en || h2c_en) { 1215 mac->hfc_func_en(rtwdev, en, h2c_en); 1216 udelay(10); 1217 } 1218 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1219 if (dma_ch_mask & BIT(ch)) 1220 continue; 1221 ret = hfc_upd_ch_info(rtwdev, ch); 1222 if (ret) 1223 return ret; 1224 } 1225 ret = hfc_upd_mix_info(rtwdev); 1226 1227 return ret; 1228 } 1229 1230 #define PWR_POLL_CNT 2000 1231 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1232 const struct rtw89_pwr_cfg *cfg) 1233 { 1234 u8 val = 0; 1235 int ret; 1236 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1237 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1238 1239 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1240 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1241 1242 if (!ret) 1243 return 0; 1244 1245 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1246 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1247 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1248 1249 return -EBUSY; 1250 } 1251 1252 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1253 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1254 { 1255 const struct rtw89_pwr_cfg *cur_cfg; 1256 u32 addr; 1257 u8 val; 1258 1259 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1260 if (!(cur_cfg->intf_msk & intf_msk) || 1261 !(cur_cfg->cv_msk & cv_msk)) 1262 continue; 1263 1264 switch (cur_cfg->cmd) { 1265 case PWR_CMD_WRITE: 1266 addr = cur_cfg->addr; 1267 1268 if (cur_cfg->base == PWR_BASE_SDIO) 1269 addr |= SDIO_LOCAL_BASE_ADDR; 1270 1271 val = rtw89_read8(rtwdev, addr); 1272 val &= ~(cur_cfg->msk); 1273 val |= (cur_cfg->val & cur_cfg->msk); 1274 1275 rtw89_write8(rtwdev, addr, val); 1276 break; 1277 case PWR_CMD_POLL: 1278 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1279 return -EBUSY; 1280 break; 1281 case PWR_CMD_DELAY: 1282 if (cur_cfg->val == PWR_DELAY_US) 1283 udelay(cur_cfg->addr); 1284 else 1285 fsleep(cur_cfg->addr * 1000); 1286 break; 1287 default: 1288 return -EINVAL; 1289 } 1290 } 1291 1292 return 0; 1293 } 1294 1295 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1296 const struct rtw89_pwr_cfg * const *cfg_seq) 1297 { 1298 u8 intf_msk; 1299 int ret; 1300 1301 switch (rtwdev->hci.type) { 1302 case RTW89_HCI_TYPE_PCIE: 1303 intf_msk = PWR_INTF_MSK_PCIE; 1304 break; 1305 case RTW89_HCI_TYPE_USB: 1306 intf_msk = PWR_INTF_MSK_USB; 1307 break; 1308 case RTW89_HCI_TYPE_SDIO: 1309 intf_msk = PWR_INTF_MSK_SDIO; 1310 break; 1311 default: 1312 return -EOPNOTSUPP; 1313 } 1314 1315 for (; *cfg_seq; cfg_seq++) { 1316 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1317 intf_msk, *cfg_seq); 1318 if (ret) 1319 return -EBUSY; 1320 } 1321 1322 return 0; 1323 } 1324 1325 static enum rtw89_rpwm_req_pwr_state 1326 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1327 { 1328 enum rtw89_rpwm_req_pwr_state state; 1329 1330 switch (rtwdev->ps_mode) { 1331 case RTW89_PS_MODE_RFOFF: 1332 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1333 break; 1334 case RTW89_PS_MODE_CLK_GATED: 1335 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1336 break; 1337 case RTW89_PS_MODE_PWR_GATED: 1338 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1339 break; 1340 default: 1341 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1342 break; 1343 } 1344 return state; 1345 } 1346 1347 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1348 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1349 bool notify_wake) 1350 { 1351 u16 request; 1352 1353 spin_lock_bh(&rtwdev->rpwm_lock); 1354 1355 request = rtw89_read16(rtwdev, R_AX_RPWM); 1356 request ^= request | PS_RPWM_TOGGLE; 1357 request |= req_pwr_state; 1358 1359 if (notify_wake) { 1360 request |= PS_RPWM_NOTIFY_WAKE; 1361 } else { 1362 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1363 RPWM_SEQ_NUM_MAX; 1364 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1365 rtwdev->mac.rpwm_seq_num); 1366 1367 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1368 request |= PS_RPWM_ACK; 1369 } 1370 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1371 1372 spin_unlock_bh(&rtwdev->rpwm_lock); 1373 } 1374 1375 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1376 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1377 { 1378 bool request_deep_mode; 1379 bool in_deep_mode; 1380 u8 rpwm_req_num; 1381 u8 cpwm_rsp_seq; 1382 u8 cpwm_seq; 1383 u8 cpwm_status; 1384 1385 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1386 request_deep_mode = true; 1387 else 1388 request_deep_mode = false; 1389 1390 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1391 in_deep_mode = true; 1392 else 1393 in_deep_mode = false; 1394 1395 if (request_deep_mode != in_deep_mode) 1396 return -EPERM; 1397 1398 if (request_deep_mode) 1399 return 0; 1400 1401 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1402 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1403 PS_CPWM_RSP_SEQ_NUM); 1404 1405 if (rpwm_req_num != cpwm_rsp_seq) 1406 return -EPERM; 1407 1408 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1409 CPWM_SEQ_NUM_MAX; 1410 1411 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1412 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1413 return -EPERM; 1414 1415 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1416 if (cpwm_status != req_pwr_state) 1417 return -EPERM; 1418 1419 return 0; 1420 } 1421 1422 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1423 { 1424 enum rtw89_rpwm_req_pwr_state state; 1425 unsigned long delay = enter ? 10 : 150; 1426 int ret; 1427 int i; 1428 1429 if (enter) 1430 state = rtw89_mac_get_req_pwr_state(rtwdev); 1431 else 1432 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1433 1434 for (i = 0; i < RPWM_TRY_CNT; i++) { 1435 rtw89_mac_send_rpwm(rtwdev, state, false); 1436 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1437 !ret, delay, 15000, false, 1438 rtwdev, state); 1439 if (!ret) 1440 break; 1441 1442 if (i == RPWM_TRY_CNT - 1) { 1443 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1444 enter ? "entering" : "leaving"); 1445 rtw89_ser_notify(rtwdev, MAC_AX_ERR_ASSERTION); 1446 } else { 1447 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1448 "%d time firmware failed to ack for %s ps mode\n", 1449 i + 1, enter ? "entering" : "leaving"); 1450 } 1451 } 1452 } 1453 1454 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1455 { 1456 enum rtw89_rpwm_req_pwr_state state; 1457 1458 state = rtw89_mac_get_req_pwr_state(rtwdev); 1459 rtw89_mac_send_rpwm(rtwdev, state, true); 1460 } 1461 1462 static void rtw89_mac_power_switch_boot_mode(struct rtw89_dev *rtwdev) 1463 { 1464 u32 boot_mode; 1465 1466 if (rtwdev->hci.type != RTW89_HCI_TYPE_USB) 1467 return; 1468 1469 boot_mode = rtw89_read32_mask(rtwdev, R_AX_GPIO_MUXCFG, B_AX_BOOT_MODE); 1470 if (!boot_mode) 1471 return; 1472 1473 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 1474 rtw89_write32_clr(rtwdev, R_AX_SYS_STATUS1, B_AX_AUTO_WLPON); 1475 rtw89_write32_clr(rtwdev, R_AX_GPIO_MUXCFG, B_AX_BOOT_MODE); 1476 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); 1477 } 1478 1479 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1480 { 1481 #define PWR_ACT 1 1482 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1483 const struct rtw89_chip_info *chip = rtwdev->chip; 1484 const struct rtw89_pwr_cfg * const *cfg_seq; 1485 int (*cfg_func)(struct rtw89_dev *rtwdev); 1486 int ret; 1487 u8 val; 1488 1489 rtw89_mac_power_switch_boot_mode(rtwdev); 1490 1491 if (on) { 1492 cfg_seq = chip->pwr_on_seq; 1493 cfg_func = chip->ops->pwr_on_func; 1494 } else { 1495 cfg_seq = chip->pwr_off_seq; 1496 cfg_func = chip->ops->pwr_off_func; 1497 } 1498 1499 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1500 __rtw89_leave_ps_mode(rtwdev); 1501 1502 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1503 if (on && val == PWR_ACT) { 1504 rtw89_err(rtwdev, "MAC has already powered on\n"); 1505 return -EBUSY; 1506 } 1507 1508 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1509 if (ret) 1510 return ret; 1511 1512 if (on) { 1513 if (!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags)) 1514 mac->efuse_read_fw_secure(rtwdev); 1515 1516 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1517 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1518 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1519 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1520 } else { 1521 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1522 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1523 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1524 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1525 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1526 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1527 rtw89_set_entity_state(rtwdev, RTW89_PHY_0, false); 1528 rtw89_set_entity_state(rtwdev, RTW89_PHY_1, false); 1529 } 1530 1531 return 0; 1532 #undef PWR_ACT 1533 } 1534 1535 int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev) 1536 { 1537 int ret; 1538 1539 ret = rtw89_mac_power_switch(rtwdev, true); 1540 if (ret) { 1541 rtw89_mac_power_switch(rtwdev, false); 1542 ret = rtw89_mac_power_switch(rtwdev, true); 1543 if (ret) 1544 return ret; 1545 } 1546 1547 return 0; 1548 } 1549 1550 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1551 { 1552 rtw89_mac_power_switch(rtwdev, false); 1553 } 1554 1555 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1556 { 1557 u32 func_en = 0; 1558 u32 ck_en = 0; 1559 u32 c1pc_en = 0; 1560 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1561 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1562 1563 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1564 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1565 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1566 B_AX_CMAC_CRPRT; 1567 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1568 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1569 B_AX_RMAC_CKEN; 1570 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1571 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1572 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1573 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1574 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1575 1576 if (en) { 1577 if (mac_idx == RTW89_MAC_1) { 1578 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1579 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1580 B_AX_R_SYM_ISO_CMAC12PP); 1581 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1582 B_AX_CMAC1_FEN); 1583 } 1584 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1585 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1586 } else { 1587 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1588 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1589 if (mac_idx == RTW89_MAC_1) { 1590 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1591 B_AX_CMAC1_FEN); 1592 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1593 B_AX_R_SYM_ISO_CMAC12PP); 1594 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1595 } 1596 } 1597 1598 return 0; 1599 } 1600 1601 static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1602 { 1603 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1604 u32 val32; 1605 1606 if (chip_id == RTL8852C) 1607 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1608 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1609 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1610 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1611 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1612 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1613 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1614 else 1615 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1616 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1617 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1618 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1619 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1620 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1621 B_AX_DMAC_CRPRT); 1622 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1623 1624 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1625 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1626 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1627 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1628 if (chip_id == RTL8852BT) 1629 val32 |= B_AX_AXIDMA_CLK_EN; 1630 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1631 1632 return 0; 1633 } 1634 1635 static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1636 { 1637 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1638 1639 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 1640 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1641 B_AX_OCP_L1_MASK); 1642 1643 return 0; 1644 } 1645 1646 static int sys_init_ax(struct rtw89_dev *rtwdev) 1647 { 1648 int ret; 1649 1650 ret = dmac_func_en_ax(rtwdev); 1651 if (ret) 1652 return ret; 1653 1654 ret = cmac_func_en_ax(rtwdev, 0, true); 1655 if (ret) 1656 return ret; 1657 1658 ret = chip_func_en_ax(rtwdev); 1659 if (ret) 1660 return ret; 1661 1662 return ret; 1663 } 1664 1665 const struct rtw89_mac_size_set rtw89_mac_size = { 1666 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1667 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0}, 1668 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0}, 1669 /* PCIE 64 */ 1670 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1671 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1672 /* 8852A USB */ 1673 .wde_size1 = {RTW89_WDE_PG_64, 768, 0,}, 1674 /* DLFW */ 1675 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1676 .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1677 /* PCIE 64 */ 1678 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1679 /* 8852B PCIE SCC */ 1680 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1681 /* DLFW */ 1682 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1683 /* 8852C USB3.0 */ 1684 .wde_size17 = {RTW89_WDE_PG_64, 354, 30,}, 1685 /* 8852C DLFW */ 1686 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1687 /* 8852C PCIE SCC */ 1688 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1689 .wde_size23 = {RTW89_WDE_PG_64, 1022, 2,}, 1690 /* 8852B USB2.0/USB3.0 SCC */ 1691 .wde_size25 = {RTW89_WDE_PG_64, 162, 94,}, 1692 /* 8852C USB2.0 */ 1693 .wde_size31 = {RTW89_WDE_PG_64, 384, 0,}, 1694 /* PCIE */ 1695 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1696 .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1697 /* 8852A USB */ 1698 .ple_size1 = {RTW89_PLE_PG_128, 3184, 16,}, 1699 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1700 /* DLFW */ 1701 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1702 /* PCIE 64 */ 1703 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1704 /* DLFW */ 1705 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1706 .ple_size9 = {RTW89_PLE_PG_128, 2288, 16,}, 1707 /* 8852C USB */ 1708 .ple_size17 = {RTW89_PLE_PG_128, 3368, 24,}, 1709 /* 8852C DLFW */ 1710 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1711 /* 8852C PCIE SCC */ 1712 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1713 /* 8852B USB2.0 SCC */ 1714 .ple_size32 = {RTW89_PLE_PG_128, 620, 20,}, 1715 /* 8852B USB3.0 SCC */ 1716 .ple_size33 = {RTW89_PLE_PG_128, 632, 8,}, 1717 /* 8852C USB2.0 */ 1718 .ple_size34 = {RTW89_PLE_PG_128, 3374, 18,}, 1719 /* PCIE 64 */ 1720 .wde_qt0 = {3792, 196, 0, 107,}, 1721 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1722 /* 8852A USB */ 1723 .wde_qt1 = {512, 196, 0, 60,}, 1724 /* DLFW */ 1725 .wde_qt4 = {0, 0, 0, 0,}, 1726 /* PCIE 64 */ 1727 .wde_qt6 = {448, 48, 0, 16,}, 1728 /* 8852B PCIE SCC */ 1729 .wde_qt7 = {446, 48, 0, 16,}, 1730 /* 8852C USB3.0 */ 1731 .wde_qt16 = {344, 2, 0, 8,}, 1732 /* 8852C DLFW */ 1733 .wde_qt17 = {0, 0, 0, 0,}, 1734 /* 8852C PCIE SCC */ 1735 .wde_qt18 = {3228, 60, 0, 40,}, 1736 .wde_qt23 = {958, 48, 0, 16,}, 1737 /* 8852B USB2.0/USB3.0 SCC */ 1738 .wde_qt25 = {152, 2, 0, 8,}, 1739 /* 8852C USB2.0 */ 1740 .wde_qt31 = {338, 6, 0, 40,}, 1741 .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 1742 .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1743 /* PCIE SCC */ 1744 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1745 /* PCIE SCC */ 1746 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1747 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1748 /* DLFW */ 1749 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1750 /* PCIE 64 */ 1751 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1752 /* 8852A USB SCC */ 1753 .ple_qt25 = {1536, 0, 16, 48, 13, 13, 360, 0, 32, 40, 8, 0,}, 1754 .ple_qt26 = {2654, 0, 1134, 48, 64, 13, 1478, 0, 64, 128, 120, 0,}, 1755 /* USB 52C USB3.0 */ 1756 .ple_qt42 = {1068, 0, 16, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,}, 1757 /* USB 52C USB3.0 */ 1758 .ple_qt43 = {3068, 0, 32, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,}, 1759 /* DLFW 52C */ 1760 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1761 /* DLFW 52C */ 1762 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1763 /* 8852C PCIE SCC */ 1764 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1765 /* 8852C PCIE SCC */ 1766 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1767 .ple_qt57 = {147, 0, 16, 20, 13, 13, 178, 0, 32, 14, 8, 0,}, 1768 /* PCIE 64 */ 1769 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1770 .ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,}, 1771 /* USB2.0 52B SCC */ 1772 .ple_qt72 = {130, 0, 16, 48, 4, 13, 322, 0, 32, 14, 8, 0, 0,}, 1773 /* USB2.0 52B 92K */ 1774 .ple_qt73 = {130, 0, 32, 48, 37, 13, 355, 0, 65, 14, 24, 0, 0,}, 1775 /* USB3.0 52B 92K */ 1776 .ple_qt74 = {286, 0, 16, 48, 4, 13, 178, 0, 32, 14, 8, 0, 0,}, 1777 .ple_qt75 = {286, 0, 32, 48, 37, 13, 211, 0, 65, 14, 24, 0, 0,}, 1778 /* USB2.0 52C */ 1779 .ple_qt78 = {1560, 0, 16, 48, 13, 13, 390, 0, 32, 38, 8, 16, 0,}, 1780 /* USB2.0 52C */ 1781 .ple_qt79 = {1560, 0, 32, 48, 1253, 13, 1630, 0, 1272, 38, 120, 1256, 0,}, 1782 /* 8852A PCIE WOW */ 1783 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1784 /* 8852B PCIE WOW */ 1785 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1786 /* 8852BT PCIE WOW */ 1787 .ple_qt_52bt_wow = {147, 0, 32, 20, 1860, 13, 1929, 0, 1879, 14, 24, 0,}, 1788 /* 8851B PCIE WOW */ 1789 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1790 .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1791 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1792 .rsvd0_size0 = {212992, 0,}, 1793 .rsvd1_size0 = {587776, 2048,}, 1794 }; 1795 EXPORT_SYMBOL(rtw89_mac_size); 1796 1797 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1798 enum rtw89_qta_mode mode) 1799 { 1800 struct rtw89_mac_info *mac = &rtwdev->mac; 1801 const struct rtw89_dle_mem *cfg, *cfgs; 1802 1803 cfgs = rtwdev->chip->dle_mem[rtwdev->hci.dle_type]; 1804 if (!cfgs) 1805 return NULL; 1806 1807 cfg = &cfgs[mode]; 1808 if (cfg->mode != mode) { 1809 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1810 return NULL; 1811 } 1812 1813 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1814 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1815 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1816 mac->dle_info.qta_mode = mode; 1817 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1818 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1819 1820 return cfg; 1821 } 1822 1823 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1824 enum rtw89_mac_dle_rsvd_qt_type type, 1825 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1826 { 1827 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1828 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1829 1830 switch (type) { 1831 case DLE_RSVD_QT_MPDU_INFO: 1832 cfg->pktid = dle_info->ple_free_pg; 1833 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1834 break; 1835 case DLE_RSVD_QT_B0_CSI: 1836 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1837 cfg->pg_num = rsvd_qt->b0_csi; 1838 break; 1839 case DLE_RSVD_QT_B1_CSI: 1840 cfg->pktid = dle_info->ple_free_pg + 1841 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1842 cfg->pg_num = rsvd_qt->b1_csi; 1843 break; 1844 case DLE_RSVD_QT_B0_LMR: 1845 cfg->pktid = dle_info->ple_free_pg + 1846 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1847 cfg->pg_num = rsvd_qt->b0_lmr; 1848 break; 1849 case DLE_RSVD_QT_B1_LMR: 1850 cfg->pktid = dle_info->ple_free_pg + 1851 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1852 rsvd_qt->b0_lmr; 1853 cfg->pg_num = rsvd_qt->b1_lmr; 1854 break; 1855 case DLE_RSVD_QT_B0_FTM: 1856 cfg->pktid = dle_info->ple_free_pg + 1857 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1858 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1859 cfg->pg_num = rsvd_qt->b0_ftm; 1860 break; 1861 case DLE_RSVD_QT_B1_FTM: 1862 cfg->pktid = dle_info->ple_free_pg + 1863 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1864 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1865 cfg->pg_num = rsvd_qt->b1_ftm; 1866 break; 1867 default: 1868 return -EINVAL; 1869 } 1870 1871 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1872 1873 return 0; 1874 } 1875 1876 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1877 { 1878 struct rtw89_mac_dle_dfi_qempty qempty; 1879 u32 grpnum, qtmp, val32, msk32; 1880 int i, j, ret; 1881 1882 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1883 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1884 1885 for (i = 0; i < grpnum; i++) { 1886 qempty.grpsel = i; 1887 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1888 if (ret) { 1889 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1890 return false; 1891 } 1892 qtmp = qempty.qempty; 1893 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1894 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 1895 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1896 return false; 1897 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1898 } 1899 } 1900 1901 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1902 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1903 if (ret) { 1904 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1905 return false; 1906 } 1907 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1908 if ((qempty.qempty & msk32) != msk32) 1909 return false; 1910 1911 if (rtwdev->dbcc_en) { 1912 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1913 if ((qempty.qempty & msk32) != msk32) 1914 return false; 1915 } 1916 1917 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1918 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1919 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1920 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1921 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1922 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1923 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1924 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1925 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1926 1927 return (val32 & msk32) == msk32; 1928 } 1929 1930 static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1931 { 1932 const struct rtw89_dle_size *wde = cfg->wde_size; 1933 const struct rtw89_dle_size *ple = cfg->ple_size; 1934 u32 used; 1935 1936 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1937 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1938 1939 if (cfg->rsvd0_size && cfg->rsvd1_size) { 1940 used += cfg->rsvd0_size->size; 1941 used += cfg->rsvd1_size->size; 1942 } 1943 1944 return used; 1945 } 1946 1947 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1948 enum rtw89_qta_mode mode) 1949 { 1950 u32 size = rtwdev->chip->fifo_size; 1951 1952 if (mode == RTW89_QTA_SCC) 1953 size -= rtwdev->chip->dle_scc_rsvd_size; 1954 1955 return size; 1956 } 1957 1958 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 1959 { 1960 if (enable) 1961 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1962 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1963 else 1964 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1965 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1966 } 1967 1968 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 1969 { 1970 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1971 1972 if (enable) { 1973 if (rtwdev->chip->chip_id == RTL8851B) 1974 val |= B_AX_AXIDMA_CLK_EN; 1975 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1976 } else { 1977 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1978 } 1979 } 1980 1981 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1982 { 1983 const struct rtw89_dle_size *size_cfg; 1984 u32 val; 1985 u8 bound = 0; 1986 1987 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1988 size_cfg = cfg->wde_size; 1989 1990 switch (size_cfg->pge_size) { 1991 default: 1992 case RTW89_WDE_PG_64: 1993 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1994 B_AX_WDE_PAGE_SEL_MASK); 1995 break; 1996 case RTW89_WDE_PG_128: 1997 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1998 B_AX_WDE_PAGE_SEL_MASK); 1999 break; 2000 case RTW89_WDE_PG_256: 2001 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 2002 return -EINVAL; 2003 } 2004 2005 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 2006 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 2007 B_AX_WDE_FREE_PAGE_NUM_MASK); 2008 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 2009 2010 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 2011 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 2012 * size_cfg->pge_size / DLE_BOUND_UNIT; 2013 size_cfg = cfg->ple_size; 2014 2015 switch (size_cfg->pge_size) { 2016 default: 2017 case RTW89_PLE_PG_64: 2018 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 2019 return -EINVAL; 2020 case RTW89_PLE_PG_128: 2021 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 2022 B_AX_PLE_PAGE_SEL_MASK); 2023 break; 2024 case RTW89_PLE_PG_256: 2025 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 2026 B_AX_PLE_PAGE_SEL_MASK); 2027 break; 2028 } 2029 2030 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 2031 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 2032 B_AX_PLE_FREE_PAGE_NUM_MASK); 2033 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 2034 2035 return 0; 2036 } 2037 2038 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 2039 { 2040 u32 reg, mask; 2041 u32 ini; 2042 2043 if (wde_or_ple) { 2044 reg = R_AX_WDE_INI_STATUS; 2045 mask = WDE_MGN_INI_RDY; 2046 } else { 2047 reg = R_AX_PLE_INI_STATUS; 2048 mask = PLE_MGN_INI_RDY; 2049 } 2050 2051 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 2052 2000, false, rtwdev, reg); 2053 } 2054 2055 #define INVALID_QT_WCPU U16_MAX 2056 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 2057 do { \ 2058 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 2059 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 2060 rtw89_write32(rtwdev, \ 2061 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 2062 val); \ 2063 } while (0) 2064 #define SET_QUOTA(_x, _module, _idx) \ 2065 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 2066 2067 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 2068 const struct rtw89_wde_quota *min_cfg, 2069 const struct rtw89_wde_quota *max_cfg, 2070 u16 ext_wde_min_qt_wcpu) 2071 { 2072 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 2073 ext_wde_min_qt_wcpu : min_cfg->wcpu; 2074 u32 val; 2075 2076 SET_QUOTA(hif, WDE, 0); 2077 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 2078 SET_QUOTA(pkt_in, WDE, 3); 2079 SET_QUOTA(cpu_io, WDE, 4); 2080 } 2081 2082 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 2083 const struct rtw89_ple_quota *min_cfg, 2084 const struct rtw89_ple_quota *max_cfg) 2085 { 2086 u32 val; 2087 2088 SET_QUOTA(cma0_tx, PLE, 0); 2089 SET_QUOTA(cma1_tx, PLE, 1); 2090 SET_QUOTA(c2h, PLE, 2); 2091 SET_QUOTA(h2c, PLE, 3); 2092 SET_QUOTA(wcpu, PLE, 4); 2093 SET_QUOTA(mpdu_proc, PLE, 5); 2094 SET_QUOTA(cma0_dma, PLE, 6); 2095 SET_QUOTA(cma1_dma, PLE, 7); 2096 SET_QUOTA(bb_rpt, PLE, 8); 2097 SET_QUOTA(wd_rel, PLE, 9); 2098 SET_QUOTA(cpu_io, PLE, 10); 2099 if (rtwdev->chip->chip_id == RTL8852C) 2100 SET_QUOTA(tx_rpt, PLE, 11); 2101 } 2102 2103 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 2104 { 2105 const struct rtw89_ple_quota *min_cfg, *max_cfg; 2106 const struct rtw89_dle_mem *cfg; 2107 u32 val; 2108 2109 if (rtwdev->chip->chip_id == RTL8852C) 2110 return 0; 2111 2112 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2113 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2114 return -EINVAL; 2115 } 2116 2117 if (wow) 2118 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2119 else 2120 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2121 if (!cfg) { 2122 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2123 return -EINVAL; 2124 } 2125 2126 min_cfg = cfg->ple_min_qt; 2127 max_cfg = cfg->ple_max_qt; 2128 SET_QUOTA(cma0_dma, PLE, 6); 2129 SET_QUOTA(cma1_dma, PLE, 7); 2130 2131 return 0; 2132 } 2133 #undef SET_QUOTA 2134 2135 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2136 { 2137 const struct rtw89_chip_info *chip = rtwdev->chip; 2138 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2139 2140 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2141 return; 2142 2143 /* 8852C enable B_AX_UC_MGNT_DEC by default */ 2144 if (chip->chip_id == RTL8852C) 2145 msk32 = B_AX_BMC_MGNT_DEC; 2146 2147 if (enable) 2148 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2149 else 2150 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2151 } 2152 2153 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2154 const struct rtw89_dle_mem *cfg, 2155 u16 ext_wde_min_qt_wcpu) 2156 { 2157 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2158 2159 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2160 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2161 } 2162 2163 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2164 enum rtw89_qta_mode ext_mode) 2165 { 2166 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2167 const struct rtw89_dle_mem *cfg, *ext_cfg; 2168 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2169 int ret; 2170 2171 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2172 if (ret) 2173 return ret; 2174 2175 cfg = get_dle_mem_cfg(rtwdev, mode); 2176 if (!cfg) { 2177 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2178 ret = -EINVAL; 2179 goto error; 2180 } 2181 2182 if (mode == RTW89_QTA_DLFW) { 2183 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2184 if (!ext_cfg) { 2185 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2186 ext_mode); 2187 ret = -EINVAL; 2188 goto error; 2189 } 2190 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2191 } 2192 2193 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2194 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2195 ret = -EINVAL; 2196 goto error; 2197 } 2198 2199 mac->dle_func_en(rtwdev, false); 2200 mac->dle_clk_en(rtwdev, true); 2201 2202 ret = mac->dle_mix_cfg(rtwdev, cfg); 2203 if (ret) { 2204 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2205 goto error; 2206 } 2207 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2208 2209 mac->dle_func_en(rtwdev, true); 2210 2211 ret = mac->chk_dle_rdy(rtwdev, true); 2212 if (ret) { 2213 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2214 return ret; 2215 } 2216 2217 ret = mac->chk_dle_rdy(rtwdev, false); 2218 if (ret) { 2219 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2220 return ret; 2221 } 2222 2223 return 0; 2224 error: 2225 mac->dle_func_en(rtwdev, false); 2226 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2227 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2228 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2229 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2230 2231 return ret; 2232 } 2233 2234 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2235 enum rtw89_qta_mode mode) 2236 { 2237 u32 reg, max_preld_size, min_rsvd_size; 2238 2239 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2240 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2241 reg = mac_idx == RTW89_MAC_0 ? 2242 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2243 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2244 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2245 2246 min_rsvd_size = PRELD_AMSDU_SIZE; 2247 reg = mac_idx == RTW89_MAC_0 ? 2248 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2249 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2250 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2251 2252 return 0; 2253 } 2254 2255 static bool is_qta_poh(struct rtw89_dev *rtwdev) 2256 { 2257 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2258 } 2259 2260 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2261 enum rtw89_qta_mode mode) 2262 { 2263 const struct rtw89_chip_info *chip = rtwdev->chip; 2264 2265 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) || 2266 !is_qta_poh(rtwdev)) 2267 return 0; 2268 2269 return preload_init_set(rtwdev, mac_idx, mode); 2270 } 2271 2272 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2273 { 2274 u32 msk32; 2275 u32 val32; 2276 2277 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2278 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2279 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2280 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2281 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2282 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2283 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2284 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2285 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2286 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2287 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2288 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2289 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2290 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2291 2292 if ((val32 & msk32) == msk32) 2293 return true; 2294 2295 return false; 2296 } 2297 2298 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2299 { 2300 const struct rtw89_chip_info *chip = rtwdev->chip; 2301 2302 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2303 return; 2304 2305 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2306 SS2F_PATH_WLCPU); 2307 } 2308 2309 static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2310 { 2311 u32 p_val; 2312 u8 val; 2313 int ret; 2314 2315 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2316 if (ret) 2317 return ret; 2318 2319 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2320 val |= B_AX_SS_EN; 2321 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2322 2323 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2324 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2325 if (ret) { 2326 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2327 return ret; 2328 } 2329 2330 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2331 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2332 2333 _patch_ss2f_path(rtwdev); 2334 2335 return 0; 2336 } 2337 2338 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2339 { 2340 int ret; 2341 2342 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2343 if (ret) 2344 return ret; 2345 2346 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2347 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2348 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2349 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2350 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2351 2352 return 0; 2353 } 2354 2355 static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2356 { 2357 const struct rtw89_chip_info *chip = rtwdev->chip; 2358 u32 val = 0; 2359 int ret; 2360 2361 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2362 if (ret) 2363 return ret; 2364 2365 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2366 /* init clock */ 2367 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2368 /* init TX encryption */ 2369 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2370 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2371 if (chip->chip_id == RTL8852C) 2372 val |= B_AX_UC_MGNT_DEC; 2373 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2374 chip->chip_id == RTL8851B || 2375 (chip->chip_id == RTL8852C && rtwdev->hci.type == RTW89_HCI_TYPE_USB)) 2376 val &= ~B_AX_TX_PARTIAL_MODE; 2377 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2378 2379 /* init MIC ICV append */ 2380 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2381 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2382 2383 /* option init */ 2384 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2385 2386 if (chip->chip_id == RTL8852C) 2387 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2388 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2389 2390 return 0; 2391 } 2392 2393 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2394 { 2395 int ret; 2396 2397 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2398 if (ret) { 2399 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2400 return ret; 2401 } 2402 2403 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2404 if (ret) { 2405 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2406 return ret; 2407 } 2408 2409 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2410 if (ret) { 2411 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2412 return ret; 2413 } 2414 2415 ret = sta_sch_init_ax(rtwdev); 2416 if (ret) { 2417 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2418 return ret; 2419 } 2420 2421 ret = mpdu_proc_init_ax(rtwdev); 2422 if (ret) { 2423 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2424 return ret; 2425 } 2426 2427 ret = sec_eng_init_ax(rtwdev); 2428 if (ret) { 2429 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2430 return ret; 2431 } 2432 2433 return ret; 2434 } 2435 2436 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2437 { 2438 u32 val, reg; 2439 u16 p_val; 2440 int ret; 2441 2442 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2443 if (ret) 2444 return ret; 2445 2446 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2447 2448 val = rtw89_read32(rtwdev, reg); 2449 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2450 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2451 rtw89_write32(rtwdev, reg, val); 2452 2453 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2454 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2455 if (ret) { 2456 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2457 return ret; 2458 } 2459 2460 return 0; 2461 } 2462 2463 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2464 { 2465 int ret; 2466 u32 reg; 2467 u32 val; 2468 2469 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2470 if (ret) 2471 return ret; 2472 2473 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2474 if (rtwdev->chip->chip_id == RTL8852C) 2475 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2476 SIFS_MACTXEN_T1_V1); 2477 else 2478 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2479 SIFS_MACTXEN_T1); 2480 2481 if (rtw89_is_rtl885xb(rtwdev)) { 2482 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2483 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2484 } 2485 2486 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2487 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2488 2489 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2490 if (rtwdev->chip->chip_id == RTL8852C) { 2491 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2492 B_AX_TX_PARTIAL_MODE); 2493 if (!val) 2494 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2495 SCH_PREBKF_24US); 2496 } else { 2497 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2498 SCH_PREBKF_24US); 2499 } 2500 2501 return 0; 2502 } 2503 2504 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2505 enum rtw89_machdr_frame_type type, 2506 enum rtw89_mac_fwd_target fwd_target, 2507 u8 mac_idx) 2508 { 2509 u32 reg; 2510 u32 val; 2511 2512 switch (fwd_target) { 2513 case RTW89_FWD_DONT_CARE: 2514 val = RX_FLTR_FRAME_DROP; 2515 break; 2516 case RTW89_FWD_TO_HOST: 2517 val = RX_FLTR_FRAME_TO_HOST; 2518 break; 2519 case RTW89_FWD_TO_WLAN_CPU: 2520 val = RX_FLTR_FRAME_TO_WLCPU; 2521 break; 2522 default: 2523 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2524 return -EINVAL; 2525 } 2526 2527 switch (type) { 2528 case RTW89_MGNT: 2529 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2530 break; 2531 case RTW89_CTRL: 2532 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2533 break; 2534 case RTW89_DATA: 2535 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2536 break; 2537 default: 2538 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2539 return -EINVAL; 2540 } 2541 rtw89_write32(rtwdev, reg, val); 2542 2543 return 0; 2544 } 2545 2546 void rtw89_mac_set_rx_fltr(struct rtw89_dev *rtwdev, u8 mac_idx, u32 rx_fltr) 2547 { 2548 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2549 u32 reg; 2550 u32 val; 2551 2552 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, mac_idx); 2553 2554 val = rtw89_read32(rtwdev, reg); 2555 /* B_AX_RX_FLTR_CFG_MASK is not a consecutive bit mask */ 2556 val = (val & ~B_AX_RX_FLTR_CFG_MASK) | (rx_fltr & B_AX_RX_FLTR_CFG_MASK); 2557 rtw89_write32(rtwdev, reg, val); 2558 } 2559 2560 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2561 { 2562 int ret, i; 2563 u32 mac_ftlr, plcp_ftlr; 2564 2565 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2566 if (ret) 2567 return ret; 2568 2569 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2570 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2571 mac_idx); 2572 if (ret) 2573 return ret; 2574 } 2575 mac_ftlr = rtwdev->hal.rx_fltr; 2576 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2577 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2578 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2579 B_AX_HE_SIGB_CRC_CHK; 2580 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2581 mac_ftlr); 2582 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2583 plcp_ftlr); 2584 2585 return 0; 2586 } 2587 2588 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2589 { 2590 u32 reg, val32; 2591 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2592 2593 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2594 B_AX_RSP_CHK_BASIC_NAV; 2595 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2596 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2597 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2598 2599 switch (rtwdev->chip->chip_id) { 2600 case RTL8852A: 2601 case RTL8852B: 2602 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2603 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2604 rtw89_write32(rtwdev, reg, val32); 2605 2606 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2607 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2608 rtw89_write32(rtwdev, reg, val32); 2609 break; 2610 default: 2611 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2612 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2613 rtw89_write32(rtwdev, reg, val32); 2614 2615 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2616 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2617 rtw89_write32(rtwdev, reg, val32); 2618 break; 2619 } 2620 } 2621 2622 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2623 { 2624 u32 val, reg; 2625 int ret; 2626 2627 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2628 if (ret) 2629 return ret; 2630 2631 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2632 val = rtw89_read32(rtwdev, reg); 2633 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2634 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2635 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2636 B_AX_CTN_CHK_INTRA_NAV | 2637 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2638 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2639 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2640 B_AX_CTN_CHK_CCA_P20); 2641 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2642 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2643 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2644 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2645 B_AX_SIFS_CHK_EDCCA); 2646 2647 rtw89_write32(rtwdev, reg, val); 2648 2649 _patch_dis_resp_chk(rtwdev, mac_idx); 2650 2651 return 0; 2652 } 2653 2654 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2655 { 2656 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2657 B_AX_WMAC_TF_UP_NAV_EN | 2658 B_AX_WMAC_NAV_UPPER_EN); 2659 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2660 2661 return 0; 2662 } 2663 2664 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2665 { 2666 u32 reg; 2667 int ret; 2668 2669 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2670 if (ret) 2671 return ret; 2672 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2673 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2674 2675 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2676 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2677 2678 return 0; 2679 } 2680 2681 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2682 { 2683 u32 reg; 2684 int ret; 2685 2686 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2687 if (ret) 2688 return ret; 2689 2690 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2691 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2692 2693 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2694 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2695 2696 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2697 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2698 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2699 2700 return 0; 2701 } 2702 2703 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2704 { 2705 const struct rtw89_chip_info *chip = rtwdev->chip; 2706 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2707 u32 reg, val, sifs; 2708 int ret; 2709 2710 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2711 if (ret) 2712 return ret; 2713 2714 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2715 val = rtw89_read32(rtwdev, reg); 2716 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2717 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2718 2719 switch (rtwdev->chip->chip_id) { 2720 case RTL8852A: 2721 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2722 break; 2723 case RTL8851B: 2724 case RTL8852B: 2725 case RTL8852BT: 2726 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2727 break; 2728 default: 2729 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2730 break; 2731 } 2732 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2733 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2734 rtw89_write32(rtwdev, reg, val); 2735 2736 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2737 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2738 2739 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2740 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2741 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2742 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2743 2744 return 0; 2745 } 2746 2747 static void rst_bacam(struct rtw89_dev *rtwdev) 2748 { 2749 u32 val32; 2750 int ret; 2751 2752 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2753 S_AX_BACAM_RST_ALL); 2754 2755 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2756 1, 1000, false, 2757 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2758 if (ret) 2759 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2760 } 2761 2762 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2763 { 2764 #define TRXCFG_RMAC_CCA_TO 32 2765 #define TRXCFG_RMAC_DATA_TO 15 2766 #define RX_MAX_LEN_UNIT 512 2767 #define PLD_RLS_MAX_PG 127 2768 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2769 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2770 int ret; 2771 u32 reg, rx_max_len, rx_qta; 2772 u16 val; 2773 2774 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2775 if (ret) 2776 return ret; 2777 2778 if (mac_idx == RTW89_MAC_0) 2779 rst_bacam(rtwdev); 2780 2781 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2782 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2783 2784 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2785 val = rtw89_read16(rtwdev, reg); 2786 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2787 B_AX_RX_DLK_DATA_TIME_MASK); 2788 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2789 B_AX_RX_DLK_CCA_TIME_MASK); 2790 if (chip_id == RTL8852BT) 2791 val |= B_AX_RX_DLK_RST_EN; 2792 rtw89_write16(rtwdev, reg, val); 2793 2794 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2795 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2796 2797 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2798 if (mac_idx == RTW89_MAC_0) 2799 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2800 else 2801 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2802 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2803 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2804 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2805 rx_max_len /= RX_MAX_LEN_UNIT; 2806 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2807 2808 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) { 2809 rtw89_write16_mask(rtwdev, 2810 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2811 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2812 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2813 BIT(12)); 2814 } 2815 2816 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2817 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2818 2819 return ret; 2820 } 2821 2822 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2823 { 2824 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2825 u32 val, reg; 2826 int ret; 2827 2828 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2829 if (ret) 2830 return ret; 2831 2832 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2833 val = rtw89_read32(rtwdev, reg); 2834 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2835 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2836 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2837 rtw89_write32(rtwdev, reg, val); 2838 2839 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2840 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2841 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2842 } 2843 2844 return 0; 2845 } 2846 2847 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2848 { 2849 const struct rtw89_dle_mem *cfg; 2850 2851 cfg = get_dle_mem_cfg(rtwdev, mode); 2852 if (!cfg) { 2853 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2854 return false; 2855 } 2856 2857 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2858 } 2859 2860 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2861 { 2862 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2863 u32 val, reg; 2864 int ret; 2865 2866 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2867 if (ret) 2868 return ret; 2869 2870 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2871 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2872 val = rtw89_read32(rtwdev, reg); 2873 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2874 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2875 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2876 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2877 val |= B_AX_HW_CTS2SELF_EN; 2878 rtw89_write32(rtwdev, reg, val); 2879 2880 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2881 val = rtw89_read32(rtwdev, reg); 2882 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2883 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2884 rtw89_write32(rtwdev, reg, val); 2885 } 2886 2887 if (mac_idx == RTW89_MAC_0) { 2888 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2889 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2890 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2891 B_AX_PTCL_TRIGGER_SS_EN_0 | 2892 B_AX_PTCL_TRIGGER_SS_EN_1 | 2893 B_AX_PTCL_TRIGGER_SS_EN_UL); 2894 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2895 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2896 } else if (mac_idx == RTW89_MAC_1) { 2897 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2898 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2899 } 2900 2901 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2902 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_VHT_0, mac_idx); 2903 rtw89_write32_mask(rtwdev, reg, 2904 B_AX_AMPDU_MAX_LEN_VHT_MASK, 0x3FF80); 2905 } 2906 2907 return 0; 2908 } 2909 2910 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2911 { 2912 u32 reg; 2913 int ret; 2914 2915 if (!rtw89_is_rtl885xb(rtwdev)) 2916 return 0; 2917 2918 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2919 if (ret) 2920 return ret; 2921 2922 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2923 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2924 2925 return 0; 2926 } 2927 2928 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2929 { 2930 int ret; 2931 2932 ret = scheduler_init_ax(rtwdev, mac_idx); 2933 if (ret) { 2934 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2935 return ret; 2936 } 2937 2938 ret = addr_cam_init_ax(rtwdev, mac_idx); 2939 if (ret) { 2940 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2941 ret); 2942 return ret; 2943 } 2944 2945 ret = rx_fltr_init_ax(rtwdev, mac_idx); 2946 if (ret) { 2947 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2948 ret); 2949 return ret; 2950 } 2951 2952 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 2953 if (ret) { 2954 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2955 ret); 2956 return ret; 2957 } 2958 2959 ret = nav_ctrl_init_ax(rtwdev); 2960 if (ret) { 2961 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2962 ret); 2963 return ret; 2964 } 2965 2966 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 2967 if (ret) { 2968 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2969 mac_idx, ret); 2970 return ret; 2971 } 2972 2973 ret = tmac_init_ax(rtwdev, mac_idx); 2974 if (ret) { 2975 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2976 return ret; 2977 } 2978 2979 ret = trxptcl_init_ax(rtwdev, mac_idx); 2980 if (ret) { 2981 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2982 return ret; 2983 } 2984 2985 ret = rmac_init_ax(rtwdev, mac_idx); 2986 if (ret) { 2987 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2988 return ret; 2989 } 2990 2991 ret = cmac_com_init_ax(rtwdev, mac_idx); 2992 if (ret) { 2993 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2994 return ret; 2995 } 2996 2997 ret = ptcl_init_ax(rtwdev, mac_idx); 2998 if (ret) { 2999 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 3000 return ret; 3001 } 3002 3003 ret = cmac_dma_init_ax(rtwdev, mac_idx); 3004 if (ret) { 3005 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 3006 return ret; 3007 } 3008 3009 return ret; 3010 } 3011 3012 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 3013 struct rtw89_mac_c2h_info *c2h_info, u8 part_num) 3014 { 3015 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3016 const struct rtw89_chip_info *chip = rtwdev->chip; 3017 struct rtw89_mac_h2c_info h2c_info = {}; 3018 enum rtw89_mac_c2h_type c2h_type; 3019 u8 content_len; 3020 int ret; 3021 3022 if (chip->chip_gen == RTW89_CHIP_AX) 3023 content_len = 0; 3024 else 3025 content_len = 2; 3026 3027 switch (part_num) { 3028 case 0: 3029 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP; 3030 break; 3031 case 1: 3032 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1; 3033 break; 3034 default: 3035 return -EINVAL; 3036 } 3037 3038 mac->cnv_efuse_state(rtwdev, false); 3039 3040 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 3041 h2c_info.content_len = content_len; 3042 h2c_info.u.hdr.w0 = u32_encode_bits(part_num, RTW89_H2CREG_GET_FEATURE_PART_NUM); 3043 3044 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 3045 if (ret) 3046 goto out; 3047 3048 if (c2h_info->id != c2h_type) 3049 ret = -EINVAL; 3050 3051 out: 3052 mac->cnv_efuse_state(rtwdev, true); 3053 3054 return ret; 3055 } 3056 3057 static int rtw89_mac_setup_phycap_part0(struct rtw89_dev *rtwdev) 3058 { 3059 const struct rtw89_chip_info *chip = rtwdev->chip; 3060 const struct rtw89_c2hreg_phycap *phycap; 3061 struct rtw89_efuse *efuse = &rtwdev->efuse; 3062 struct rtw89_mac_c2h_info c2h_info = {}; 3063 struct rtw89_hal *hal = &rtwdev->hal; 3064 u8 tx_nss; 3065 u8 rx_nss; 3066 u8 tx_ant; 3067 u8 rx_ant; 3068 int ret; 3069 3070 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 0); 3071 if (ret) 3072 return ret; 3073 3074 phycap = &c2h_info.u.phycap; 3075 3076 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 3077 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 3078 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 3079 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 3080 3081 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 3082 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 3083 3084 if (tx_ant == 1) 3085 hal->antenna_tx = RF_B; 3086 if (rx_ant == 1) 3087 hal->antenna_rx = RF_B; 3088 3089 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 3090 hal->antenna_tx = RF_B; 3091 hal->tx_path_diversity = true; 3092 } 3093 3094 if (chip->rf_path_num == 1) { 3095 hal->antenna_tx = RF_A; 3096 hal->antenna_rx = RF_A; 3097 if ((efuse->rfe_type % 3) == 2) 3098 hal->ant_diversity = true; 3099 } 3100 3101 rtw89_debug(rtwdev, RTW89_DBG_FW, 3102 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 3103 hal->tx_nss, tx_nss, chip->tx_nss, 3104 hal->rx_nss, rx_nss, chip->rx_nss); 3105 rtw89_debug(rtwdev, RTW89_DBG_FW, 3106 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 3107 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 3108 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 3109 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 3110 3111 return 0; 3112 } 3113 3114 static int rtw89_mac_setup_phycap_part1(struct rtw89_dev *rtwdev) 3115 { 3116 const struct rtw89_chip_variant *variant = rtwdev->variant; 3117 const struct rtw89_c2hreg_phycap *phycap; 3118 struct rtw89_mac_c2h_info c2h_info = {}; 3119 struct rtw89_hal *hal = &rtwdev->hal; 3120 u8 qam_raw, qam; 3121 int ret; 3122 3123 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 1); 3124 if (ret) 3125 return ret; 3126 3127 phycap = &c2h_info.u.phycap; 3128 3129 qam_raw = u32_get_bits(phycap->w2, RTW89_C2HREG_PHYCAP_P1_W2_QAM); 3130 3131 switch (qam_raw) { 3132 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_256: 3133 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024: 3134 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096: 3135 qam = qam_raw; 3136 break; 3137 default: 3138 qam = RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096; 3139 break; 3140 } 3141 3142 if ((variant && variant->no_mcs_12_13) || 3143 qam <= RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024) 3144 hal->no_mcs_12_13 = true; 3145 3146 rtw89_debug(rtwdev, RTW89_DBG_FW, "phycap qam=%d/%d no_mcs_12_13=%d\n", 3147 qam_raw, qam, hal->no_mcs_12_13); 3148 3149 return 0; 3150 } 3151 3152 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 3153 { 3154 const struct rtw89_chip_info *chip = rtwdev->chip; 3155 int ret; 3156 3157 ret = rtw89_mac_setup_phycap_part0(rtwdev); 3158 if (ret) 3159 return ret; 3160 3161 if (chip->chip_gen == RTW89_CHIP_AX || 3162 RTW89_CHK_FW_FEATURE(NO_PHYCAP_P1, &rtwdev->fw)) 3163 return 0; 3164 3165 return rtw89_mac_setup_phycap_part1(rtwdev); 3166 } 3167 3168 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 3169 u16 tx_en_u16, u16 mask_u16) 3170 { 3171 struct rtw89_mac_c2h_info c2h_info = {0}; 3172 struct rtw89_mac_h2c_info h2c_info = {0}; 3173 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 3174 int ret; 3175 3176 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 3177 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 3178 3179 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 3180 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 3181 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 3182 3183 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 3184 if (ret) 3185 return ret; 3186 3187 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 3188 return -EINVAL; 3189 3190 return 0; 3191 } 3192 3193 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 3194 u16 tx_en, u16 tx_en_mask) 3195 { 3196 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 3197 u16 val; 3198 int ret; 3199 3200 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3201 if (ret) 3202 return ret; 3203 3204 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3205 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 3206 tx_en, tx_en_mask); 3207 3208 val = rtw89_read16(rtwdev, reg); 3209 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3210 rtw89_write16(rtwdev, reg, val); 3211 3212 return 0; 3213 } 3214 3215 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3216 u32 tx_en, u32 tx_en_mask) 3217 { 3218 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3219 u32 val; 3220 int ret; 3221 3222 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3223 if (ret) 3224 return ret; 3225 3226 val = rtw89_read32(rtwdev, reg); 3227 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3228 rtw89_write32(rtwdev, reg, val); 3229 3230 return 0; 3231 } 3232 3233 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3234 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3235 { 3236 int ret; 3237 3238 *tx_en = rtw89_read16(rtwdev, 3239 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3240 3241 switch (sel) { 3242 case RTW89_SCH_TX_SEL_ALL: 3243 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3244 B_AX_CTN_TXEN_ALL_MASK); 3245 if (ret) 3246 return ret; 3247 break; 3248 case RTW89_SCH_TX_SEL_HIQ: 3249 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3250 0, B_AX_CTN_TXEN_HGQ); 3251 if (ret) 3252 return ret; 3253 break; 3254 case RTW89_SCH_TX_SEL_MG0: 3255 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3256 0, B_AX_CTN_TXEN_MGQ); 3257 if (ret) 3258 return ret; 3259 break; 3260 case RTW89_SCH_TX_SEL_MACID: 3261 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3262 B_AX_CTN_TXEN_ALL_MASK); 3263 if (ret) 3264 return ret; 3265 break; 3266 default: 3267 return 0; 3268 } 3269 3270 return 0; 3271 } 3272 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3273 3274 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3275 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3276 { 3277 int ret; 3278 3279 *tx_en = rtw89_read32(rtwdev, 3280 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3281 3282 switch (sel) { 3283 case RTW89_SCH_TX_SEL_ALL: 3284 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3285 B_AX_CTN_TXEN_ALL_MASK_V1); 3286 if (ret) 3287 return ret; 3288 break; 3289 case RTW89_SCH_TX_SEL_HIQ: 3290 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3291 0, B_AX_CTN_TXEN_HGQ); 3292 if (ret) 3293 return ret; 3294 break; 3295 case RTW89_SCH_TX_SEL_MG0: 3296 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3297 0, B_AX_CTN_TXEN_MGQ); 3298 if (ret) 3299 return ret; 3300 break; 3301 case RTW89_SCH_TX_SEL_MACID: 3302 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3303 B_AX_CTN_TXEN_ALL_MASK_V1); 3304 if (ret) 3305 return ret; 3306 break; 3307 default: 3308 return 0; 3309 } 3310 3311 return 0; 3312 } 3313 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3314 3315 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3316 { 3317 int ret; 3318 3319 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3320 if (ret) 3321 return ret; 3322 3323 return 0; 3324 } 3325 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3326 3327 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3328 { 3329 int ret; 3330 3331 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3332 B_AX_CTN_TXEN_ALL_MASK_V1); 3333 if (ret) 3334 return ret; 3335 3336 return 0; 3337 } 3338 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3339 3340 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3341 { 3342 u32 val, reg; 3343 int ret; 3344 3345 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3346 val = buf_len; 3347 val |= B_AX_WD_BUF_REQ_EXEC; 3348 rtw89_write32(rtwdev, reg, val); 3349 3350 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3351 3352 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3353 1, 2000, false, rtwdev, reg); 3354 if (ret) 3355 return ret; 3356 3357 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3358 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3359 return -ENOENT; 3360 3361 return 0; 3362 } 3363 3364 static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3365 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3366 { 3367 u32 val, cmd_type, reg; 3368 int ret; 3369 3370 cmd_type = ctrl_para->cmd_type; 3371 3372 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3373 val = 0; 3374 val = u32_replace_bits(val, ctrl_para->start_pktid, 3375 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3376 val = u32_replace_bits(val, ctrl_para->end_pktid, 3377 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3378 rtw89_write32(rtwdev, reg, val); 3379 3380 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3381 val = 0; 3382 val = u32_replace_bits(val, ctrl_para->src_pid, 3383 B_AX_CPUQ_OP_SRC_PID_MASK); 3384 val = u32_replace_bits(val, ctrl_para->src_qid, 3385 B_AX_CPUQ_OP_SRC_QID_MASK); 3386 val = u32_replace_bits(val, ctrl_para->dst_pid, 3387 B_AX_CPUQ_OP_DST_PID_MASK); 3388 val = u32_replace_bits(val, ctrl_para->dst_qid, 3389 B_AX_CPUQ_OP_DST_QID_MASK); 3390 rtw89_write32(rtwdev, reg, val); 3391 3392 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3393 val = 0; 3394 val = u32_replace_bits(val, cmd_type, 3395 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3396 val = u32_replace_bits(val, ctrl_para->macid, 3397 B_AX_CPUQ_OP_MACID_MASK); 3398 val = u32_replace_bits(val, ctrl_para->pkt_num, 3399 B_AX_CPUQ_OP_PKTNUM_MASK); 3400 val |= B_AX_WD_CPUQ_OP_EXEC; 3401 rtw89_write32(rtwdev, reg, val); 3402 3403 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3404 3405 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3406 1, 2000, false, rtwdev, reg); 3407 if (ret) 3408 return ret; 3409 3410 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3411 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3412 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3413 3414 return 0; 3415 } 3416 3417 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3418 bool band1_en) 3419 { 3420 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3421 const struct rtw89_dle_mem *cfg; 3422 3423 cfg = get_dle_mem_cfg(rtwdev, mode); 3424 if (!cfg) { 3425 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3426 return -EINVAL; 3427 } 3428 3429 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3430 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3431 return -EINVAL; 3432 } 3433 3434 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3435 3436 return mac->dle_quota_change(rtwdev, band1_en); 3437 } 3438 3439 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3440 { 3441 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3442 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3443 u16 pkt_id; 3444 int ret; 3445 3446 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3447 if (ret) { 3448 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3449 return ret; 3450 } 3451 3452 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3453 ctrl_para.start_pktid = pkt_id; 3454 ctrl_para.end_pktid = pkt_id; 3455 ctrl_para.pkt_num = 0; 3456 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3457 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3458 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3459 if (ret) { 3460 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3461 return -EFAULT; 3462 } 3463 3464 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3465 if (ret) { 3466 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3467 return ret; 3468 } 3469 3470 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3471 ctrl_para.start_pktid = pkt_id; 3472 ctrl_para.end_pktid = pkt_id; 3473 ctrl_para.pkt_num = 0; 3474 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3475 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3476 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3477 if (ret) { 3478 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3479 return -EFAULT; 3480 } 3481 3482 return 0; 3483 } 3484 3485 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3486 { 3487 int ret; 3488 u32 reg; 3489 u8 val; 3490 3491 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3492 if (ret) 3493 return ret; 3494 3495 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3496 3497 ret = read_poll_timeout(rtw89_read8, val, 3498 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3499 SW_CVR_DUR_US, 3500 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3501 false, rtwdev, reg); 3502 if (ret) 3503 return ret; 3504 3505 return 0; 3506 } 3507 3508 static int band1_enable_ax(struct rtw89_dev *rtwdev) 3509 { 3510 int ret, i; 3511 u32 sleep_bak[4] = {0}; 3512 u32 pause_bak[4] = {0}; 3513 u32 tx_en; 3514 3515 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3516 if (ret) { 3517 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3518 return ret; 3519 } 3520 3521 for (i = 0; i < 4; i++) { 3522 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3523 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3524 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3525 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3526 } 3527 3528 ret = band_idle_ck_b(rtwdev, 0); 3529 if (ret) { 3530 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3531 return ret; 3532 } 3533 3534 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3535 if (ret) { 3536 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3537 return ret; 3538 } 3539 3540 for (i = 0; i < 4; i++) { 3541 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3542 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3543 } 3544 3545 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3546 if (ret) { 3547 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3548 return ret; 3549 } 3550 3551 ret = cmac_func_en_ax(rtwdev, 1, true); 3552 if (ret) { 3553 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3554 return ret; 3555 } 3556 3557 ret = cmac_init_ax(rtwdev, 1); 3558 if (ret) { 3559 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3560 return ret; 3561 } 3562 3563 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3564 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3565 3566 return 0; 3567 } 3568 3569 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3570 { 3571 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3572 3573 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3574 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3575 } 3576 3577 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3578 { 3579 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3580 3581 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3582 } 3583 3584 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3585 { 3586 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3587 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3588 3589 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3590 B_AX_TX_GET_ERRPKTID_INT_EN | 3591 B_AX_TX_NXT_ERRPKTID_INT_EN | 3592 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3593 B_AX_TX_OFFSET_ERR_INT_EN | 3594 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3595 if (chip_id == RTL8852C) 3596 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3597 B_AX_TX_ETH_TYPE_ERR_EN | 3598 B_AX_TX_LLC_PRE_ERR_EN | 3599 B_AX_TX_NW_TYPE_ERR_EN | 3600 B_AX_TX_KSRCH_ERR_EN); 3601 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3602 imr->mpdu_tx_imr_set); 3603 3604 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3605 B_AX_GETPKTID_ERR_INT_EN | 3606 B_AX_MHDRLEN_ERR_INT_EN | 3607 B_AX_RPT_ERR_INT_EN); 3608 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3609 imr->mpdu_rx_imr_set); 3610 } 3611 3612 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3613 { 3614 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3615 3616 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3617 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3618 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3619 B_AX_PLE_B_PKTID_ERR_INT_EN); 3620 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3621 imr->sta_sch_imr_set); 3622 } 3623 3624 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3625 { 3626 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3627 3628 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3629 imr->txpktctl_imr_b0_clr); 3630 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3631 imr->txpktctl_imr_b0_set); 3632 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3633 imr->txpktctl_imr_b1_clr); 3634 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3635 imr->txpktctl_imr_b1_set); 3636 } 3637 3638 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3639 { 3640 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3641 3642 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3643 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3644 } 3645 3646 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3647 { 3648 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3649 3650 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3651 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3652 } 3653 3654 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3655 { 3656 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3657 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3658 } 3659 3660 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3661 { 3662 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3663 3664 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3665 imr->host_disp_imr_clr); 3666 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3667 imr->host_disp_imr_set); 3668 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3669 imr->cpu_disp_imr_clr); 3670 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3671 imr->cpu_disp_imr_set); 3672 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3673 imr->other_disp_imr_clr); 3674 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3675 imr->other_disp_imr_set); 3676 } 3677 3678 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3679 { 3680 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3681 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3682 } 3683 3684 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3685 { 3686 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3687 3688 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3689 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3690 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3691 B_AX_BBRPT_CHINFO_IMR_CLR); 3692 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3693 imr->bbrpt_err_imr_set); 3694 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3695 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3696 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3697 } 3698 3699 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3700 { 3701 u32 reg; 3702 3703 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3704 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3705 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3706 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3707 } 3708 3709 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3710 { 3711 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3712 u32 reg; 3713 3714 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3715 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3716 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3717 } 3718 3719 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3720 { 3721 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3722 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3723 u32 reg; 3724 3725 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3726 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3727 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3728 3729 if (chip_id == RTL8852C) { 3730 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3731 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3732 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3733 } 3734 } 3735 3736 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3737 { 3738 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3739 u32 reg; 3740 3741 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3742 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3743 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3744 } 3745 3746 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3747 { 3748 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3749 u32 reg; 3750 3751 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3752 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3753 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3754 } 3755 3756 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3757 { 3758 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3759 u32 reg; 3760 3761 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3762 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3763 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3764 } 3765 3766 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3767 enum rtw89_mac_hwmod_sel sel) 3768 { 3769 int ret; 3770 3771 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3772 if (ret) { 3773 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3774 sel, mac_idx); 3775 return ret; 3776 } 3777 3778 if (sel == RTW89_DMAC_SEL) { 3779 rtw89_wdrls_imr_enable(rtwdev); 3780 rtw89_wsec_imr_enable(rtwdev); 3781 rtw89_mpdu_trx_imr_enable(rtwdev); 3782 rtw89_sta_sch_imr_enable(rtwdev); 3783 rtw89_txpktctl_imr_enable(rtwdev); 3784 rtw89_wde_imr_enable(rtwdev); 3785 rtw89_ple_imr_enable(rtwdev); 3786 rtw89_pktin_imr_enable(rtwdev); 3787 rtw89_dispatcher_imr_enable(rtwdev); 3788 rtw89_cpuio_imr_enable(rtwdev); 3789 rtw89_bbrpt_imr_enable(rtwdev); 3790 } else if (sel == RTW89_CMAC_SEL) { 3791 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3792 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3793 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3794 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3795 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3796 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3797 } else { 3798 return -EINVAL; 3799 } 3800 3801 return 0; 3802 } 3803 3804 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3805 { 3806 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3807 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3808 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3809 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3810 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta) 3811 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3812 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3813 } 3814 3815 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3816 { 3817 int ret = 0; 3818 3819 if (enable) { 3820 ret = band1_enable_ax(rtwdev); 3821 if (ret) { 3822 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3823 return ret; 3824 } 3825 3826 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3827 if (ret) { 3828 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3829 return ret; 3830 } 3831 } else { 3832 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3833 return -EINVAL; 3834 } 3835 3836 return 0; 3837 } 3838 3839 static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3840 { 3841 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3842 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3843 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3844 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3845 B_AX_RLSRPT0_FLTR_MAP_MASK); 3846 } else { 3847 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3848 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3849 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3850 B_AX_RLSRPT0_FLTR_MAP_MASK); 3851 } 3852 3853 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3854 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3855 3856 return 0; 3857 } 3858 3859 static int trx_init_ax(struct rtw89_dev *rtwdev) 3860 { 3861 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3862 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3863 int ret; 3864 3865 ret = dmac_init_ax(rtwdev, 0); 3866 if (ret) { 3867 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3868 return ret; 3869 } 3870 3871 ret = cmac_init_ax(rtwdev, 0); 3872 if (ret) { 3873 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3874 return ret; 3875 } 3876 3877 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3878 ret = dbcc_enable_ax(rtwdev, true); 3879 if (ret) { 3880 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3881 return ret; 3882 } 3883 } 3884 3885 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3886 if (ret) { 3887 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3888 return ret; 3889 } 3890 3891 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3892 if (ret) { 3893 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3894 return ret; 3895 } 3896 3897 err_imr_ctrl_ax(rtwdev, true); 3898 3899 ret = set_host_rpr_ax(rtwdev); 3900 if (ret) { 3901 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3902 return ret; 3903 } 3904 3905 if (chip_id == RTL8852C) 3906 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG, 3907 B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN); 3908 3909 return 0; 3910 } 3911 3912 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 3913 { 3914 #define BACAM_1024BMP_OCC_ENTRY 4 3915 #define BACAM_MAX_RU_SUPPORT_B0_STA 1 3916 #define BACAM_MAX_RU_SUPPORT_B1_STA 1 3917 const struct rtw89_chip_info *chip = rtwdev->chip; 3918 u8 users, offset; 3919 3920 if (chip->bacam_ver != RTW89_BACAM_V1) 3921 return 0; 3922 3923 offset = 0; 3924 users = BACAM_MAX_RU_SUPPORT_B0_STA; 3925 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 3926 3927 offset += users * BACAM_1024BMP_OCC_ENTRY; 3928 users = BACAM_MAX_RU_SUPPORT_B1_STA; 3929 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 3930 3931 return 0; 3932 } 3933 3934 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3935 { 3936 u32 val32; 3937 3938 if (rtw89_is_rtl885xb(rtwdev)) { 3939 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3940 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3941 return; 3942 } 3943 3944 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3945 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3946 3947 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3948 val32 |= B_AX_FS_WDT_INT; 3949 val32 &= ~B_AX_FS_WDT_INT_MSK; 3950 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3951 } 3952 3953 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3954 { 3955 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3956 3957 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3958 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3959 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3960 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3961 3962 rtw89_disable_fw_watchdog(rtwdev); 3963 3964 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3965 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3966 } 3967 3968 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3969 bool dlfw, bool include_bb) 3970 { 3971 u32 val; 3972 int ret; 3973 3974 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3975 return -EFAULT; 3976 3977 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3978 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3979 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3980 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3981 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3982 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3983 3984 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3985 3986 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3987 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3988 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3989 B_AX_WCPU_FWDL_STS_MASK); 3990 3991 if (dlfw) 3992 val |= B_AX_WCPU_FWDL_EN; 3993 3994 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3995 3996 if (rtw89_is_rtl885xb(rtwdev)) 3997 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3998 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3999 4000 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 4001 boot_reason); 4002 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 4003 4004 if (!dlfw) { 4005 mdelay(5); 4006 4007 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 4008 if (ret) 4009 return ret; 4010 } 4011 4012 return 0; 4013 } 4014 4015 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 4016 { 4017 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4018 u32 val; 4019 4020 if (chip_id == RTL8852C) 4021 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 4022 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 4023 else 4024 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 4025 B_AX_PKT_BUF_EN; 4026 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 4027 } 4028 4029 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 4030 { 4031 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4032 u32 val; 4033 4034 if (chip_id == RTL8851B || chip_id == RTL8852BT) 4035 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 4036 else 4037 val = B_AX_DISPATCHER_CLK_EN; 4038 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 4039 4040 if (chip_id != RTL8852C) 4041 return; 4042 4043 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 4044 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 4045 val |= B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 4046 4047 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) 4048 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B); 4049 else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 4050 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_USB); 4051 else 4052 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_SDIO); 4053 4054 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 4055 4056 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 4057 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 4058 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 4059 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 4060 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 4061 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 4062 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 4063 } 4064 4065 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 4066 { 4067 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4068 int ret; 4069 4070 mac->hci_func_en(rtwdev); 4071 mac->dmac_func_pre_en(rtwdev); 4072 4073 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 4074 if (ret) { 4075 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 4076 return ret; 4077 } 4078 4079 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 4080 if (ret) { 4081 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 4082 return ret; 4083 } 4084 4085 return ret; 4086 } 4087 4088 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 4089 { 4090 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 4091 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 4092 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 4093 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 4094 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 4095 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 4096 4097 return 0; 4098 } 4099 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 4100 4101 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 4102 { 4103 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 4104 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 4105 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 4106 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 4107 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 4108 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 4109 4110 return 0; 4111 } 4112 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 4113 4114 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 4115 { 4116 int ret; 4117 4118 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 4119 4120 if (include_bb) { 4121 /* Only call BB preinit including configuration of BB MCU for 4122 * the chips which need to download BB MCU firmware. Otherwise, 4123 * calling preinit later to prevent touching registers affecting 4124 * download firmware. 4125 */ 4126 rtw89_chip_bb_preinit(rtwdev); 4127 } 4128 4129 ret = rtw89_mac_dmac_pre_init(rtwdev); 4130 if (ret) 4131 return ret; 4132 4133 if (rtwdev->hci.ops->mac_pre_init) { 4134 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 4135 if (ret) 4136 return ret; 4137 } 4138 4139 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 4140 if (ret) 4141 return ret; 4142 4143 return 0; 4144 } 4145 4146 int rtw89_mac_preinit(struct rtw89_dev *rtwdev) 4147 { 4148 int ret; 4149 4150 ret = rtw89_mac_pwr_on(rtwdev); 4151 if (ret) 4152 return ret; 4153 4154 return 0; 4155 } 4156 4157 int rtw89_mac_init(struct rtw89_dev *rtwdev) 4158 { 4159 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4160 const struct rtw89_chip_info *chip = rtwdev->chip; 4161 bool include_bb = !!chip->bbmcu_nr; 4162 int ret; 4163 4164 ret = rtw89_mac_partial_init(rtwdev, include_bb); 4165 if (ret) 4166 goto fail; 4167 4168 ret = rtw89_chip_enable_bb_rf(rtwdev); 4169 if (ret) 4170 goto fail; 4171 4172 ret = mac->sys_init(rtwdev); 4173 if (ret) 4174 goto fail; 4175 4176 ret = mac->trx_init(rtwdev); 4177 if (ret) 4178 goto fail; 4179 4180 ret = rtw89_mac_feat_init(rtwdev); 4181 if (ret) 4182 goto fail; 4183 4184 if (rtwdev->hci.ops->mac_post_init) { 4185 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 4186 if (ret) 4187 goto fail; 4188 } 4189 4190 rtw89_fw_send_all_early_h2c(rtwdev); 4191 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 4192 4193 return ret; 4194 fail: 4195 rtw89_mac_pwr_off(rtwdev); 4196 4197 return ret; 4198 } 4199 4200 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4201 { 4202 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4203 u8 i; 4204 4205 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4206 return; 4207 4208 for (i = 0; i < 4; i++) { 4209 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4210 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 4211 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 4212 } 4213 } 4214 4215 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4216 { 4217 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4218 4219 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4220 return; 4221 4222 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4223 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 4224 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 4225 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 4226 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 4227 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 4228 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 4229 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 4230 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 4231 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 4232 } 4233 4234 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4235 { 4236 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4237 u8 grp = macid >> 5; 4238 int ret; 4239 4240 /* If this is called by change_interface() in the case of P2P, it could 4241 * be power-off, so ignore this operation. 4242 */ 4243 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4244 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4245 return 0; 4246 4247 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4248 if (ret) 4249 return ret; 4250 4251 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4252 4253 return 0; 4254 } 4255 4256 static const struct rtw89_port_reg rtw89_port_base_ax = { 4257 .port_cfg = R_AX_PORT_CFG_P0, 4258 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4259 .bcn_area = R_AX_BCN_AREA_P0, 4260 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4261 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4262 .tbtt_agg = R_AX_TBTT_AGG_P0, 4263 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4264 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4265 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4266 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4267 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4268 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4269 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4270 .tsftr_l = R_AX_TSFTR_LOW_P0, 4271 .tsftr_h = R_AX_TSFTR_HIGH_P0, 4272 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 4273 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4274 .mbssid = R_AX_MBSSID_CTRL, 4275 .mbssid_drop = R_AX_MBSSID_DROP_0, 4276 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4277 .ptcl_dbg = R_AX_PTCL_DBG, 4278 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4279 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4280 .bcn_psr_rpt = R_AX_BCN_PSR_RPT_P0, 4281 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4282 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4283 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4284 }; 4285 4286 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4287 struct rtw89_vif_link *rtwvif_link, u8 type) 4288 { 4289 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4290 const struct rtw89_port_reg *p = mac->port_base; 4291 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif_link->port); 4292 u32 reg_info, reg_ctrl; 4293 u32 val; 4294 int ret; 4295 4296 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif_link->mac_idx); 4297 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif_link->mac_idx); 4298 4299 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4300 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4301 fsleep(100); 4302 4303 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4304 true, rtwdev, reg_info, mask); 4305 if (ret) 4306 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4307 } 4308 4309 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, 4310 struct rtw89_vif_link *rtwvif_link) 4311 { 4312 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4313 const struct rtw89_port_reg *p = mac->port_base; 4314 4315 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4316 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 4317 1); 4318 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 4319 0); 4320 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 4321 0); 4322 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4323 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4324 B_AX_TBTTERLY_MASK, 1); 4325 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, 4326 B_AX_BCN_SPACE_MASK, 1); 4327 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4328 4329 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM0); 4330 if (rtwvif_link->port == RTW89_PORT_0) 4331 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM1); 4332 4333 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4334 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4335 fsleep(2000); 4336 } 4337 4338 #define BCN_INTERVAL 100 4339 #define BCN_ERLY_DEF 160 4340 #define BCN_SETUP_DEF 2 4341 #define BCN_HOLD_DEF 200 4342 #define BCN_MASK_DEF 0 4343 #define TBTT_ERLY_DEF 5 4344 #define BCN_SET_UNIT 32 4345 #define BCN_ERLY_SET_DLY (10 * 2) 4346 4347 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4348 struct rtw89_vif_link *rtwvif_link) 4349 { 4350 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4351 const struct rtw89_port_reg *p = mac->port_base; 4352 const struct rtw89_chip_info *chip = rtwdev->chip; 4353 struct ieee80211_bss_conf *bss_conf; 4354 bool need_backup = false; 4355 u32 backup_val; 4356 u16 beacon_int; 4357 4358 if (!rtw89_read32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN)) 4359 return; 4360 4361 if (chip->chip_id == RTL8852A && rtwvif_link->port != RTW89_PORT_0) { 4362 need_backup = true; 4363 backup_val = rtw89_read32_port(rtwdev, rtwvif_link, p->tbtt_prohib); 4364 } 4365 4366 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4367 rtw89_mac_bcn_drop(rtwdev, rtwvif_link); 4368 4369 if (chip->chip_id == RTL8852A) { 4370 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->tbtt_prohib, 4371 B_AX_TBTT_SETUP_MASK); 4372 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4373 B_AX_TBTT_HOLD_MASK, 1); 4374 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->tbtt_early, 4375 B_AX_TBTTERLY_MASK); 4376 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->bcn_early, 4377 B_AX_BCNERLY_MASK); 4378 } 4379 4380 rcu_read_lock(); 4381 4382 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4383 beacon_int = bss_conf->beacon_int; 4384 4385 rcu_read_unlock(); 4386 4387 msleep(beacon_int + 1); 4388 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN | 4389 B_AX_BRK_SETUP); 4390 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSFTR_RST); 4391 rtw89_write32_port(rtwdev, rtwvif_link, p->bcn_cnt_tmr, 0); 4392 4393 if (need_backup) 4394 rtw89_write32_port(rtwdev, rtwvif_link, p->tbtt_prohib, backup_val); 4395 } 4396 4397 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4398 struct rtw89_vif_link *rtwvif_link, bool en) 4399 { 4400 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4401 const struct rtw89_port_reg *p = mac->port_base; 4402 4403 if (en) 4404 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4405 B_AX_TXBCN_RPT_EN); 4406 else 4407 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4408 B_AX_TXBCN_RPT_EN); 4409 } 4410 4411 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4412 struct rtw89_vif_link *rtwvif_link, bool en) 4413 { 4414 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4415 const struct rtw89_port_reg *p = mac->port_base; 4416 4417 if (en) 4418 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4419 B_AX_RXBCN_RPT_EN); 4420 else 4421 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4422 B_AX_RXBCN_RPT_EN); 4423 } 4424 4425 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4426 struct rtw89_vif_link *rtwvif_link) 4427 { 4428 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4429 const struct rtw89_port_reg *p = mac->port_base; 4430 4431 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_NET_TYPE_MASK, 4432 rtwvif_link->net_type); 4433 } 4434 4435 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4436 struct rtw89_vif_link *rtwvif_link) 4437 { 4438 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4439 const struct rtw89_port_reg *p = mac->port_base; 4440 bool en = rtwvif_link->net_type != RTW89_NET_TYPE_NO_LINK; 4441 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4442 4443 if (en) 4444 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bits); 4445 else 4446 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bits); 4447 } 4448 4449 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4450 struct rtw89_vif_link *rtwvif_link) 4451 { 4452 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4453 const struct rtw89_port_reg *p = mac->port_base; 4454 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4455 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4456 u32 bit = B_AX_RX_BSSID_FIT_EN; 4457 4458 if (en) 4459 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bit); 4460 else 4461 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bit); 4462 } 4463 4464 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4465 struct rtw89_vif_link *rtwvif_link, bool en) 4466 { 4467 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4468 const struct rtw89_port_reg *p = mac->port_base; 4469 4470 if (en) 4471 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4472 else 4473 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4474 } 4475 4476 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4477 struct rtw89_vif_link *rtwvif_link) 4478 { 4479 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4480 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4481 4482 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif_link, en); 4483 } 4484 4485 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4486 struct rtw89_vif_link *rtwvif_link, bool en) 4487 { 4488 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4489 const struct rtw89_port_reg *p = mac->port_base; 4490 4491 if (en) 4492 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4493 else 4494 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4495 } 4496 4497 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4498 struct rtw89_vif_link *rtwvif_link) 4499 { 4500 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || 4501 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4502 4503 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4504 } 4505 4506 static void rtw89_mac_enable_ap_bcn_by_chan(struct rtw89_dev *rtwdev, 4507 struct rtw89_vif_link *rtwvif_link, 4508 const struct rtw89_chan *to_match, 4509 bool en) 4510 { 4511 const struct rtw89_chan *chan; 4512 4513 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 4514 return; 4515 4516 if (!to_match) 4517 goto doit; 4518 4519 /* @to_match may not be in the same domain as return of calling 4520 * rtw89_chan_get(). So, cannot compare their addresses directly. 4521 */ 4522 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 4523 if (chan->channel != to_match->channel) 4524 return; 4525 4526 doit: 4527 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4528 } 4529 4530 static void rtw89_mac_enable_aps_bcn_by_chan(struct rtw89_dev *rtwdev, 4531 const struct rtw89_chan *to_match, 4532 bool en) 4533 { 4534 struct rtw89_vif_link *rtwvif_link; 4535 struct rtw89_vif *rtwvif; 4536 unsigned int link_id; 4537 4538 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4539 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4540 rtw89_mac_enable_ap_bcn_by_chan(rtwdev, rtwvif_link, 4541 to_match, en); 4542 } 4543 4544 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4545 { 4546 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, NULL, en); 4547 } 4548 4549 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4550 struct rtw89_vif_link *rtwvif_link) 4551 { 4552 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4553 const struct rtw89_port_reg *p = mac->port_base; 4554 struct ieee80211_bss_conf *bss_conf; 4555 u16 bcn_int; 4556 4557 rcu_read_lock(); 4558 4559 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4560 if (bss_conf->beacon_int) 4561 bcn_int = bss_conf->beacon_int; 4562 else 4563 bcn_int = BCN_INTERVAL; 4564 4565 rcu_read_unlock(); 4566 4567 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, B_AX_BCN_SPACE_MASK, 4568 bcn_int); 4569 } 4570 4571 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4572 struct rtw89_vif_link *rtwvif_link) 4573 { 4574 u8 win = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4575 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4576 const struct rtw89_port_reg *p = mac->port_base; 4577 u8 port = rtwvif_link->port; 4578 u32 reg; 4579 4580 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif_link->mac_idx); 4581 rtw89_write8(rtwdev, reg, win); 4582 } 4583 4584 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4585 struct rtw89_vif_link *rtwvif_link) 4586 { 4587 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4588 const struct rtw89_port_reg *p = mac->port_base; 4589 struct ieee80211_bss_conf *bss_conf; 4590 u8 dtim_period; 4591 u32 addr; 4592 4593 rcu_read_lock(); 4594 4595 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4596 dtim_period = bss_conf->dtim_period; 4597 4598 rcu_read_unlock(); 4599 4600 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif_link->mac_idx); 4601 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4602 4603 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4604 dtim_period); 4605 } 4606 4607 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4608 struct rtw89_vif_link *rtwvif_link) 4609 { 4610 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4611 const struct rtw89_port_reg *p = mac->port_base; 4612 4613 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4614 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4615 } 4616 4617 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4618 struct rtw89_vif_link *rtwvif_link) 4619 { 4620 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4621 const struct rtw89_port_reg *p = mac->port_base; 4622 4623 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4624 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4625 } 4626 4627 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4628 struct rtw89_vif_link *rtwvif_link) 4629 { 4630 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4631 const struct rtw89_port_reg *p = mac->port_base; 4632 4633 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, 4634 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4635 } 4636 4637 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4638 struct rtw89_vif_link *rtwvif_link) 4639 { 4640 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4641 const struct rtw89_port_reg *p = mac->port_base; 4642 4643 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4644 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4645 } 4646 4647 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4648 struct rtw89_vif_link *rtwvif_link) 4649 { 4650 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4651 const struct rtw89_port_reg *p = mac->port_base; 4652 static const u32 masks[RTW89_PORT_NUM] = { 4653 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4654 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4655 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4656 }; 4657 struct ieee80211_bss_conf *bss_conf; 4658 u8 port = rtwvif_link->port; 4659 u32 reg_base; 4660 u32 reg; 4661 u8 bss_color; 4662 4663 rcu_read_lock(); 4664 4665 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4666 bss_color = bss_conf->he_bss_color.color; 4667 4668 rcu_read_unlock(); 4669 4670 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4671 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif_link->mac_idx); 4672 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4673 } 4674 4675 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4676 struct rtw89_vif_link *rtwvif_link) 4677 { 4678 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4679 const struct rtw89_port_reg *p = mac->port_base; 4680 u8 port = rtwvif_link->port; 4681 u32 reg; 4682 4683 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4684 return; 4685 4686 if (port == 0) { 4687 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif_link->mac_idx); 4688 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4689 } 4690 } 4691 4692 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4693 struct rtw89_vif_link *rtwvif_link) 4694 { 4695 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4696 const struct rtw89_port_reg *p = mac->port_base; 4697 u8 port = rtwvif_link->port; 4698 u32 reg; 4699 u32 val; 4700 4701 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif_link->mac_idx); 4702 val = rtw89_read32(rtwdev, reg); 4703 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4704 if (port == 0) 4705 val &= ~BIT(0); 4706 rtw89_write32(rtwdev, reg, val); 4707 } 4708 4709 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4710 struct rtw89_vif_link *rtwvif_link, bool enable) 4711 { 4712 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4713 const struct rtw89_port_reg *p = mac->port_base; 4714 4715 if (enable) 4716 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4717 B_AX_PORT_FUNC_EN); 4718 else 4719 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4720 B_AX_PORT_FUNC_EN); 4721 } 4722 4723 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4724 struct rtw89_vif_link *rtwvif_link) 4725 { 4726 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4727 const struct rtw89_port_reg *p = mac->port_base; 4728 4729 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 4730 BCN_ERLY_DEF); 4731 } 4732 4733 static void rtw89_mac_port_cfg_bcn_psr_rpt(struct rtw89_dev *rtwdev, 4734 struct rtw89_vif_link *rtwvif_link) 4735 { 4736 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4737 const struct rtw89_port_reg *p = mac->port_base; 4738 struct ieee80211_bss_conf *bss_conf; 4739 u8 bssid_index; 4740 u32 reg; 4741 4742 rcu_read_lock(); 4743 4744 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4745 if (bss_conf->nontransmitted) 4746 bssid_index = bss_conf->bssid_index; 4747 else 4748 bssid_index = 0; 4749 4750 rcu_read_unlock(); 4751 4752 reg = rtw89_mac_reg_by_idx(rtwdev, p->bcn_psr_rpt + rtwvif_link->port * 4, 4753 rtwvif_link->mac_idx); 4754 rtw89_write32_mask(rtwdev, reg, B_AX_BCAID_P0_MASK, bssid_index); 4755 } 4756 4757 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4758 struct rtw89_vif_link *rtwvif_link, 4759 struct rtw89_vif_link *rtwvif_src, 4760 u16 offset_tu) 4761 { 4762 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4763 const struct rtw89_port_reg *p = mac->port_base; 4764 u32 val, reg; 4765 4766 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4767 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif_link->port * 4, 4768 rtwvif_link->mac_idx); 4769 4770 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4771 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4772 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4773 } 4774 4775 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4776 struct rtw89_vif_link *rtwvif_link, 4777 struct rtw89_vif_link *rtwvif_src, 4778 u8 offset, int *n_offset) 4779 { 4780 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif_link == rtwvif_src) 4781 return; 4782 4783 if (rtwvif_link->rand_tsf_done) 4784 goto out; 4785 4786 /* adjust offset randomly to avoid beacon conflict */ 4787 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4788 rtw89_mac_port_tsf_sync(rtwdev, rtwvif_link, rtwvif_src, 4789 (*n_offset) * offset); 4790 4791 rtwvif_link->rand_tsf_done = true; 4792 4793 out: 4794 (*n_offset)++; 4795 } 4796 4797 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4798 { 4799 struct rtw89_vif_link *src = NULL, *tmp; 4800 u8 offset = 100, vif_aps = 0; 4801 struct rtw89_vif *rtwvif; 4802 unsigned int link_id; 4803 int n_offset = 1; 4804 4805 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4806 rtw89_vif_for_each_link(rtwvif, tmp, link_id) { 4807 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4808 src = tmp; 4809 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4810 vif_aps++; 4811 } 4812 } 4813 4814 if (vif_aps == 0) 4815 return; 4816 4817 offset /= (vif_aps + 1); 4818 4819 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4820 rtw89_vif_for_each_link(rtwvif, tmp, link_id) 4821 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, 4822 &n_offset); 4823 } 4824 4825 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4826 { 4827 int ret; 4828 4829 ret = rtw89_mac_port_update(rtwdev, rtwvif_link); 4830 if (ret) 4831 return ret; 4832 4833 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4834 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4835 4836 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif_link->mac_id, false); 4837 if (ret) 4838 return ret; 4839 4840 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_CREATE); 4841 if (ret) 4842 return ret; 4843 4844 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, NULL, true); 4845 if (ret) 4846 return ret; 4847 4848 ret = rtw89_cam_init(rtwdev, rtwvif_link); 4849 if (ret) 4850 return ret; 4851 4852 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, RTW89_ROLE_CREATE); 4853 if (ret) 4854 return ret; 4855 4856 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, NULL); 4857 if (ret) 4858 return ret; 4859 4860 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, NULL); 4861 if (ret) 4862 return ret; 4863 4864 return 0; 4865 } 4866 4867 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4868 { 4869 int ret; 4870 4871 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_REMOVE); 4872 if (ret) 4873 return ret; 4874 4875 rtw89_cam_deinit(rtwdev, rtwvif_link); 4876 4877 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, RTW89_ROLE_REMOVE); 4878 if (ret) 4879 return ret; 4880 4881 return 0; 4882 } 4883 4884 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4885 { 4886 u8 port = rtwvif_link->port; 4887 4888 if (port >= RTW89_PORT_NUM) 4889 return -EINVAL; 4890 4891 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 4892 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif_link, false); 4893 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif_link, false); 4894 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif_link); 4895 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif_link); 4896 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif_link); 4897 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif_link); 4898 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif_link); 4899 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif_link); 4900 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif_link); 4901 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif_link); 4902 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif_link); 4903 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif_link); 4904 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif_link); 4905 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif_link); 4906 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif_link); 4907 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif_link); 4908 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif_link); 4909 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif_link, true); 4910 rtw89_mac_port_tsf_resync_all(rtwdev); 4911 fsleep(BCN_ERLY_SET_DLY); 4912 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif_link); 4913 rtw89_mac_port_cfg_bcn_psr_rpt(rtwdev, rtwvif_link); 4914 4915 return 0; 4916 } 4917 4918 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4919 u64 *tsf) 4920 { 4921 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4922 const struct rtw89_port_reg *p = mac->port_base; 4923 u32 tsf_low, tsf_high; 4924 int ret; 4925 4926 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif_link->mac_idx, RTW89_CMAC_SEL); 4927 if (ret) 4928 return ret; 4929 4930 tsf_low = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_l); 4931 tsf_high = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_h); 4932 *tsf = (u64)tsf_high << 32 | tsf_low; 4933 4934 return 0; 4935 } 4936 4937 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4938 struct cfg80211_bss *bss, 4939 void *data) 4940 { 4941 const struct cfg80211_bss_ies *ies; 4942 const struct element *elem; 4943 bool *tolerated = data; 4944 4945 rcu_read_lock(); 4946 ies = rcu_dereference(bss->ies); 4947 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4948 ies->len); 4949 4950 if (!elem || elem->datalen < 10 || 4951 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4952 *tolerated = false; 4953 rcu_read_unlock(); 4954 } 4955 4956 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4957 struct rtw89_vif_link *rtwvif_link) 4958 { 4959 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4960 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4961 struct ieee80211_hw *hw = rtwdev->hw; 4962 struct ieee80211_bss_conf *bss_conf; 4963 struct cfg80211_chan_def oper; 4964 bool tolerated = true; 4965 u32 reg; 4966 4967 rcu_read_lock(); 4968 4969 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4970 if (!bss_conf->he_support || vif->type != NL80211_IFTYPE_STATION) { 4971 rcu_read_unlock(); 4972 return; 4973 } 4974 4975 oper = bss_conf->chanreq.oper; 4976 if (!(oper.chan->flags & IEEE80211_CHAN_RADAR)) { 4977 rcu_read_unlock(); 4978 return; 4979 } 4980 4981 rcu_read_unlock(); 4982 4983 cfg80211_bss_iter(hw->wiphy, &oper, 4984 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4985 &tolerated); 4986 4987 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 4988 rtwvif_link->mac_idx); 4989 if (tolerated) 4990 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4991 else 4992 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4993 } 4994 4995 void rtw89_mac_set_he_tb(struct rtw89_dev *rtwdev, 4996 struct rtw89_vif_link *rtwvif_link) 4997 { 4998 struct ieee80211_bss_conf *bss_conf; 4999 bool set; 5000 u32 reg; 5001 5002 if (rtwdev->chip->chip_gen != RTW89_CHIP_BE) 5003 return; 5004 5005 rcu_read_lock(); 5006 5007 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5008 set = bss_conf->he_support && !bss_conf->eht_support; 5009 5010 rcu_read_unlock(); 5011 5012 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CLIENT_OM_CTRL, 5013 rtwvif_link->mac_idx); 5014 5015 if (set) 5016 rtw89_write32_set(rtwdev, reg, B_BE_TRIG_DIS_EHTTB); 5017 else 5018 rtw89_write32_clr(rtwdev, reg, B_BE_TRIG_DIS_EHTTB); 5019 } 5020 5021 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5022 { 5023 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 5024 5025 rtwvif_link->rand_tsf_done = false; 5026 } 5027 5028 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5029 { 5030 return rtw89_mac_vif_init(rtwdev, rtwvif_link); 5031 } 5032 5033 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5034 { 5035 return rtw89_mac_vif_deinit(rtwdev, rtwvif_link); 5036 } 5037 5038 static void 5039 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5040 { 5041 } 5042 5043 static const struct rtw89_chan * 5044 rtw89_hw_scan_search_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 5045 { 5046 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 5047 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 5048 5049 if (band == op->band_type && channel == op->primary_channel) 5050 return op; 5051 5052 if (scan_info->extra_op.set) { 5053 op = &scan_info->extra_op.chan; 5054 if (band == op->band_type && channel == op->primary_channel) 5055 return op; 5056 } 5057 5058 return NULL; 5059 } 5060 5061 static void 5062 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5063 u32 len) 5064 { 5065 const struct rtw89_c2h_scanofld *c2h = 5066 (const struct rtw89_c2h_scanofld *)skb->data; 5067 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 5068 const struct rtw89_chan *op_chan; 5069 struct rtw89_vif *rtwvif; 5070 struct rtw89_chan new; 5071 u16 actual_period, expect_period; 5072 u8 reason, status, tx_fail, band; 5073 u8 mac_idx, sw_def, fw_def; 5074 u8 ver = U8_MAX; 5075 u32 report_tsf; 5076 u16 chan; 5077 int ret; 5078 5079 if (!rtwvif_link) 5080 return; 5081 5082 rtwvif = rtwvif_link->rtwvif; 5083 5084 if (RTW89_CHK_FW_FEATURE(CH_INFO_BE_V0, &rtwdev->fw)) 5085 ver = 0; 5086 5087 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 5088 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5089 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 5090 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5091 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 5092 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 5093 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 5094 5095 5096 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 5097 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 5098 5099 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 5100 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 5101 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 5102 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 5103 if (ver == 0) { 5104 expect_period = 5105 le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 5106 } else { 5107 actual_period = le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_PERIOD_V1); 5108 expect_period = 5109 le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1); 5110 } 5111 5112 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 5113 "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 5114 sw_def, fw_def, report_tsf, expect_period); 5115 } 5116 5117 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 5118 "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 5119 mac_idx, band, chan, reason, status, tx_fail, actual_period); 5120 5121 switch (reason) { 5122 case RTW89_SCAN_LEAVE_OP_NOTIFY: 5123 case RTW89_SCAN_LEAVE_CH_NOTIFY: 5124 op_chan = rtw89_hw_scan_search_op_chan(rtwdev, band, chan); 5125 if (op_chan) { 5126 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, op_chan, false); 5127 ieee80211_stop_queues(rtwdev->hw); 5128 } else { 5129 rtw89_phy_nhm_get_result(rtwdev, band, chan); 5130 } 5131 return; 5132 case RTW89_SCAN_END_SCAN_NOTIFY: 5133 if (rtwdev->scan_info.abort) 5134 return; 5135 5136 if (rtwvif_link && rtwvif->scan_req && 5137 !list_empty(&rtwdev->scan_info.chan_list)) { 5138 rtwdev->scan_info.delay = 0; 5139 ret = rtw89_hw_scan_offload(rtwdev, rtwvif_link, true); 5140 if (ret) { 5141 rtw89_hw_scan_abort(rtwdev, rtwvif_link); 5142 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 5143 } 5144 } else { 5145 rtw89_hw_scan_complete(rtwdev, rtwvif_link, false); 5146 } 5147 break; 5148 case RTW89_SCAN_ENTER_OP_NOTIFY: 5149 case RTW89_SCAN_ENTER_CH_NOTIFY: 5150 op_chan = rtw89_hw_scan_search_op_chan(rtwdev, band, chan); 5151 if (op_chan) { 5152 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, op_chan); 5153 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, op_chan, true); 5154 ieee80211_wake_queues(rtwdev->hw); 5155 } else { 5156 rtw89_chan_create(&new, chan, chan, band, 5157 RTW89_CHANNEL_WIDTH_20); 5158 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, 5159 &new); 5160 rtw89_phy_nhm_trigger(rtwdev); 5161 } 5162 break; 5163 default: 5164 return; 5165 } 5166 } 5167 5168 static void 5169 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5170 struct sk_buff *skb) 5171 { 5172 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5173 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5174 enum nl80211_cqm_rssi_threshold_event nl_event; 5175 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 5176 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 5177 u8 type, event, mac_id; 5178 bool start_detect; 5179 s8 sig; 5180 5181 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 5182 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 5183 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 5184 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 5185 5186 if (mac_id != rtwvif_link->mac_id) 5187 return; 5188 5189 rtw89_debug(rtwdev, RTW89_DBG_FW, 5190 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 5191 mac_id, type, sig, event); 5192 5193 switch (type) { 5194 case RTW89_BCN_FLTR_BEACON_LOSS: 5195 if (!rtwdev->scanning && !rtwvif->offchan && 5196 !rtwvif_link->noa_once.in_duration) { 5197 start_detect = rtw89_mcc_detect_go_bcn(rtwdev, rtwvif_link); 5198 if (start_detect) 5199 return; 5200 5201 ieee80211_connection_loss(vif); 5202 } else { 5203 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 5204 } 5205 return; 5206 case RTW89_BCN_FLTR_NOTIFY: 5207 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 5208 break; 5209 case RTW89_BCN_FLTR_RSSI: 5210 if (event == RTW89_BCN_FLTR_RSSI_LOW) 5211 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 5212 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 5213 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 5214 else 5215 return; 5216 break; 5217 default: 5218 return; 5219 } 5220 5221 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 5222 } 5223 5224 static void 5225 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5226 u32 len) 5227 { 5228 struct rtw89_vif_link *rtwvif_link; 5229 struct rtw89_vif *rtwvif; 5230 unsigned int link_id; 5231 5232 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5233 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 5234 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif_link, c2h); 5235 } 5236 5237 static void 5238 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5239 { 5240 /* N.B. This will run in interrupt context. */ 5241 5242 rtw89_debug(rtwdev, RTW89_DBG_FW, 5243 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 5244 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 5245 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 5246 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 5247 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 5248 } 5249 5250 static void 5251 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5252 { 5253 /* N.B. This will run in interrupt context. */ 5254 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5255 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 5256 struct rtw89_wait_info *ps_wait = &rtwdev->mac.ps_wait; 5257 const struct rtw89_c2h_done_ack *c2h = 5258 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 5259 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 5260 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 5261 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 5262 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 5263 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 5264 struct rtw89_completion_data data = {}; 5265 unsigned int cond; 5266 5267 rtw89_debug(rtwdev, RTW89_DBG_FW, 5268 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 5269 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 5270 5271 if (h2c_cat != H2C_CAT_MAC) 5272 return; 5273 5274 switch (h2c_class) { 5275 default: 5276 return; 5277 case H2C_CL_MAC_PS: 5278 switch (h2c_func) { 5279 default: 5280 return; 5281 case H2C_FUNC_IPS_CFG: 5282 cond = RTW89_PS_WAIT_COND_IPS_CFG; 5283 break; 5284 } 5285 5286 data.err = !!h2c_return; 5287 rtw89_complete_cond(ps_wait, cond, &data); 5288 return; 5289 case H2C_CL_MAC_FW_OFLD: 5290 switch (h2c_func) { 5291 default: 5292 return; 5293 case H2C_FUNC_ADD_SCANOFLD_CH: 5294 cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 5295 h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN; 5296 break; 5297 case H2C_FUNC_SCANOFLD: 5298 scan_info->seq++; 5299 cond = RTW89_SCANOFLD_WAIT_COND_START; 5300 break; 5301 case H2C_FUNC_SCANOFLD_BE: 5302 scan_info->seq++; 5303 cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 5304 h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN; 5305 break; 5306 } 5307 5308 data.err = !!h2c_return; 5309 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5310 return; 5311 } 5312 } 5313 5314 static void 5315 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5316 { 5317 rtw89_fw_log_dump(rtwdev, c2h->data, len); 5318 } 5319 5320 static void 5321 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5322 { 5323 } 5324 5325 static void 5326 rtw89_mac_c2h_bcn_upd_done(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5327 { 5328 const struct rtw89_c2h_bcn_upd_done *c2h = 5329 (const struct rtw89_c2h_bcn_upd_done *)skb_c2h->data; 5330 u8 band, port, mbssid; 5331 5332 port = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_PORT); 5333 mbssid = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_MBSSID); 5334 band = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_BAND_IDX); 5335 5336 rtw89_debug(rtwdev, RTW89_DBG_FW, 5337 "BCN update done on port:%d mbssid:%d band:%d\n", 5338 port, mbssid, band); 5339 } 5340 5341 static void 5342 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 5343 u32 len) 5344 { 5345 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 5346 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 5347 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 5348 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 5349 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 5350 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 5351 struct rtw89_completion_data data = {}; 5352 unsigned int cond; 5353 5354 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 5355 pkt_id, pkt_op, pkt_len); 5356 5357 data.err = !pkt_len; 5358 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 5359 5360 rtw89_complete_cond(wait, cond, &data); 5361 } 5362 5363 static void 5364 rtw89_mac_c2h_bcn_resend(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5365 { 5366 } 5367 5368 static void 5369 rtw89_mac_c2h_tx_duty_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5370 { 5371 struct rtw89_c2h_tx_duty_rpt *c2h = 5372 (struct rtw89_c2h_tx_duty_rpt *)skb_c2h->data; 5373 u8 err; 5374 5375 err = le32_get_bits(c2h->w2, RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR); 5376 5377 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "C2H TX duty rpt with err=%d\n", err); 5378 } 5379 5380 static void 5381 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5382 u32 len) 5383 { 5384 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 5385 } 5386 5387 static void 5388 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5389 { 5390 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 5391 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 5392 5393 switch (func) { 5394 case H2C_FUNC_ADD_MCC: 5395 case H2C_FUNC_START_MCC: 5396 case H2C_FUNC_STOP_MCC: 5397 case H2C_FUNC_DEL_MCC_GROUP: 5398 case H2C_FUNC_RESET_MCC_GROUP: 5399 case H2C_FUNC_MCC_REQ_TSF: 5400 case H2C_FUNC_MCC_MACID_BITMAP: 5401 case H2C_FUNC_MCC_SYNC: 5402 case H2C_FUNC_MCC_SET_DURATION: 5403 break; 5404 default: 5405 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5406 "invalid MCC C2H RCV ACK: func %d\n", func); 5407 return; 5408 } 5409 5410 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5411 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 5412 } 5413 5414 static void 5415 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5416 { 5417 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 5418 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 5419 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 5420 struct rtw89_completion_data data = {}; 5421 unsigned int cond; 5422 bool next = false; 5423 5424 switch (func) { 5425 case H2C_FUNC_MCC_REQ_TSF: 5426 next = true; 5427 break; 5428 case H2C_FUNC_MCC_MACID_BITMAP: 5429 case H2C_FUNC_MCC_SYNC: 5430 case H2C_FUNC_MCC_SET_DURATION: 5431 break; 5432 case H2C_FUNC_ADD_MCC: 5433 case H2C_FUNC_START_MCC: 5434 case H2C_FUNC_STOP_MCC: 5435 case H2C_FUNC_DEL_MCC_GROUP: 5436 case H2C_FUNC_RESET_MCC_GROUP: 5437 default: 5438 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5439 "invalid MCC C2H REQ ACK: func %d\n", func); 5440 return; 5441 } 5442 5443 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5444 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5445 group, func, retcode); 5446 5447 if (!retcode && next) 5448 return; 5449 5450 data.err = !!retcode; 5451 cond = RTW89_MCC_WAIT_COND(group, func); 5452 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5453 } 5454 5455 static void 5456 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5457 { 5458 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5459 struct rtw89_completion_data data = {}; 5460 struct rtw89_mac_mcc_tsf_rpt *rpt; 5461 unsigned int cond; 5462 5463 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5464 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5465 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5466 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5467 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5468 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5469 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5470 5471 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5472 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5473 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5474 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5475 5476 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5477 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5478 } 5479 5480 static void 5481 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5482 { 5483 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5484 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5485 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5486 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5487 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5488 struct rtw89_completion_data data = {}; 5489 unsigned int cond; 5490 bool rsp = true; 5491 bool err; 5492 u8 func; 5493 5494 switch (status) { 5495 case RTW89_MAC_MCC_ADD_ROLE_OK: 5496 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5497 func = H2C_FUNC_ADD_MCC; 5498 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5499 break; 5500 case RTW89_MAC_MCC_START_GROUP_OK: 5501 case RTW89_MAC_MCC_START_GROUP_FAIL: 5502 func = H2C_FUNC_START_MCC; 5503 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5504 break; 5505 case RTW89_MAC_MCC_STOP_GROUP_OK: 5506 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5507 func = H2C_FUNC_STOP_MCC; 5508 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5509 break; 5510 case RTW89_MAC_MCC_DEL_GROUP_OK: 5511 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5512 func = H2C_FUNC_DEL_MCC_GROUP; 5513 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5514 break; 5515 case RTW89_MAC_MCC_RESET_GROUP_OK: 5516 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5517 func = H2C_FUNC_RESET_MCC_GROUP; 5518 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5519 break; 5520 case RTW89_MAC_MCC_SWITCH_CH_OK: 5521 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5522 case RTW89_MAC_MCC_TXNULL0_OK: 5523 case RTW89_MAC_MCC_TXNULL0_FAIL: 5524 case RTW89_MAC_MCC_TXNULL1_OK: 5525 case RTW89_MAC_MCC_TXNULL1_FAIL: 5526 case RTW89_MAC_MCC_SWITCH_EARLY: 5527 case RTW89_MAC_MCC_TBTT: 5528 case RTW89_MAC_MCC_DURATION_START: 5529 case RTW89_MAC_MCC_DURATION_END: 5530 rsp = false; 5531 break; 5532 default: 5533 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5534 "invalid MCC C2H STS RPT: status %d\n", status); 5535 return; 5536 } 5537 5538 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5539 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5540 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5541 5542 if (!rsp) 5543 return; 5544 5545 data.err = err; 5546 cond = RTW89_MCC_WAIT_COND(group, func); 5547 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5548 } 5549 5550 static void 5551 rtw89_mac_c2h_tx_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5552 { 5553 struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt; 5554 struct rtw89_tx_skb_data *skb_data; 5555 u8 sw_define, tx_status, txcnt; 5556 struct sk_buff *skb; 5557 5558 if (rtwdev->chip->chip_id == RTL8922A) { 5559 const struct rtw89_c2h_mac_tx_rpt_v2 *rpt_v2; 5560 5561 rpt_v2 = (const struct rtw89_c2h_mac_tx_rpt_v2 *)c2h->data; 5562 sw_define = le32_get_bits(rpt_v2->w12, 5563 RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2); 5564 tx_status = le32_get_bits(rpt_v2->w12, 5565 RTW89_C2H_MAC_TX_RPT_W12_TX_STATE_V2); 5566 txcnt = le32_get_bits(rpt_v2->w14, 5567 RTW89_C2H_MAC_TX_RPT_W14_DATA_TX_CNT_V2); 5568 } else { 5569 const struct rtw89_c2h_mac_tx_rpt *rpt; 5570 5571 rpt = (const struct rtw89_c2h_mac_tx_rpt *)c2h->data; 5572 sw_define = le32_get_bits(rpt->w2, RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE); 5573 tx_status = le32_get_bits(rpt->w2, RTW89_C2H_MAC_TX_RPT_W2_TX_STATE); 5574 if (rtwdev->chip->chip_id == RTL8852C) 5575 txcnt = le32_get_bits(rpt->w5, 5576 RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT_V1); 5577 else 5578 txcnt = le32_get_bits(rpt->w5, 5579 RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT); 5580 } 5581 5582 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 5583 "C2H TX RPT: sn %d, tx_status %d, txcnt %d\n", 5584 sw_define, tx_status, txcnt); 5585 5586 /* claim sw_define is not over size of tx_rpt->skbs[] */ 5587 static_assert(hweight32(RTW89_MAX_TX_RPTS_MASK) == 5588 hweight32(RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2) && 5589 hweight32(RTW89_MAX_TX_RPTS_MASK) == 5590 hweight32(RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE)); 5591 5592 scoped_guard(spinlock_irqsave, &tx_rpt->skb_lock) { 5593 skb = tx_rpt->skbs[sw_define]; 5594 5595 /* skip if no skb (normally shouldn't happen) */ 5596 if (!skb) { 5597 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 5598 "C2H TX RPT: no skb found in queue\n"); 5599 return; 5600 } 5601 5602 skb_data = RTW89_TX_SKB_CB(skb); 5603 5604 /* skip if TX attempt has failed and retry limit has not been 5605 * reached yet 5606 */ 5607 if (tx_status != RTW89_TX_DONE && 5608 txcnt != skb_data->tx_pkt_cnt_lmt) 5609 return; 5610 5611 tx_rpt->skbs[sw_define] = NULL; 5612 rtw89_tx_rpt_tx_status(rtwdev, skb, tx_status); 5613 } 5614 } 5615 5616 static void 5617 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5618 { 5619 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5620 const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5621 struct rtw89_completion_data data = {}; 5622 struct rtw89_mac_mrc_tsf_rpt *rpt; 5623 unsigned int i; 5624 5625 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5626 rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5627 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5628 le32_get_bits(c2h_rpt->w2, 5629 RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5630 5631 for (i = 0; i < rpt->num; i++) { 5632 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5633 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5634 5635 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5636 5637 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5638 "MRC C2H TSF RPT: index %u> %llu\n", 5639 i, rpt->tsfs[i]); 5640 } 5641 5642 rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5643 } 5644 5645 static void 5646 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5647 { 5648 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 5649 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 5650 struct rtw89_wait_info *wait = &rtw_wow->wait; 5651 const struct rtw89_c2h_wow_aoac_report *c2h = 5652 (const struct rtw89_c2h_wow_aoac_report *)skb->data; 5653 struct rtw89_completion_data data = {}; 5654 5655 aoac_rpt->rpt_ver = c2h->rpt_ver; 5656 aoac_rpt->sec_type = c2h->sec_type; 5657 aoac_rpt->key_idx = c2h->key_idx; 5658 aoac_rpt->pattern_idx = c2h->pattern_idx; 5659 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok, 5660 RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX); 5661 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv)); 5662 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count, 5663 sizeof(aoac_rpt->eapol_key_replay_count)); 5664 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk)); 5665 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv)); 5666 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv)); 5667 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id); 5668 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn); 5669 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk)); 5670 5671 rtw89_complete_cond(wait, RTW89_WOW_WAIT_COND_AOAC, &data); 5672 } 5673 5674 static void 5675 rtw89_mac_c2h_mlo_link_cfg_stat(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5676 { 5677 const struct rtw89_c2h_mlo_link_cfg_rpt *c2h_rpt; 5678 struct rtw89_wait_info *wait = &rtwdev->mlo.wait; 5679 struct rtw89_completion_data data = {}; 5680 unsigned int cond; 5681 u16 mac_id; 5682 u8 status; 5683 5684 c2h_rpt = (const struct rtw89_c2h_mlo_link_cfg_rpt *)c2h->data; 5685 5686 mac_id = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MLO_LINK_CFG_RPT_W2_MACID); 5687 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MLO_LINK_CFG_RPT_W2_STATUS); 5688 5689 data.err = status == RTW89_C2H_MLO_LINK_CFG_ROLE_NOT_EXIST || 5690 status == RTW89_C2H_MLO_LINK_CFG_RUNNING; 5691 cond = RTW89_MLO_WAIT_COND(mac_id, H2C_FUNC_MLO_LINK_CFG); 5692 rtw89_complete_cond(wait, cond, &data); 5693 } 5694 5695 static void 5696 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5697 { 5698 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5699 const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5700 struct rtw89_completion_data data = {}; 5701 enum rtw89_mac_mrc_status status; 5702 unsigned int cond; 5703 bool next = false; 5704 u32 tsf_high; 5705 u32 tsf_low; 5706 u8 sch_idx; 5707 u8 func; 5708 5709 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5710 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5711 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5712 tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5713 tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5714 5715 switch (status) { 5716 case RTW89_MAC_MRC_START_SCH_OK: 5717 func = H2C_FUNC_START_MRC; 5718 break; 5719 case RTW89_MAC_MRC_STOP_SCH_OK: 5720 /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5721 func = H2C_FUNC_DEL_MRC; 5722 next = true; 5723 break; 5724 case RTW89_MAC_MRC_DEL_SCH_OK: 5725 func = H2C_FUNC_DEL_MRC; 5726 break; 5727 case RTW89_MAC_MRC_EMPTY_SCH_FAIL: 5728 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5729 "MRC C2H STS RPT: empty sch fail\n"); 5730 return; 5731 case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL: 5732 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5733 "MRC C2H STS RPT: role not exist fail\n"); 5734 return; 5735 case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL: 5736 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5737 "MRC C2H STS RPT: data not found fail\n"); 5738 return; 5739 case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL: 5740 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5741 "MRC C2H STS RPT: get next slot fail\n"); 5742 return; 5743 case RTW89_MAC_MRC_ALT_ROLE_FAIL: 5744 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5745 "MRC C2H STS RPT: alt role fail\n"); 5746 return; 5747 case RTW89_MAC_MRC_ADD_PSTIMER_FAIL: 5748 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5749 "MRC C2H STS RPT: add ps timer fail\n"); 5750 return; 5751 case RTW89_MAC_MRC_MALLOC_FAIL: 5752 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5753 "MRC C2H STS RPT: malloc fail\n"); 5754 return; 5755 case RTW89_MAC_MRC_SWITCH_CH_FAIL: 5756 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5757 "MRC C2H STS RPT: switch ch fail\n"); 5758 return; 5759 case RTW89_MAC_MRC_TXNULL0_FAIL: 5760 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5761 "MRC C2H STS RPT: tx null-0 fail\n"); 5762 return; 5763 case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL: 5764 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5765 "MRC C2H STS RPT: port func en fail\n"); 5766 return; 5767 default: 5768 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5769 "invalid MRC C2H STS RPT: status %d\n", status); 5770 return; 5771 } 5772 5773 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5774 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 5775 sch_idx, status, (u64)tsf_high << 32 | tsf_low); 5776 5777 if (next) 5778 return; 5779 5780 cond = RTW89_MRC_WAIT_COND(sch_idx, func); 5781 rtw89_complete_cond(wait, cond, &data); 5782 } 5783 5784 static void 5785 rtw89_mac_c2h_pwr_int_notify(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5786 { 5787 const struct rtw89_c2h_pwr_int_notify *c2h; 5788 struct rtw89_sta_link *rtwsta_link; 5789 struct ieee80211_sta *sta; 5790 struct rtw89_sta *rtwsta; 5791 u16 macid; 5792 bool ps; 5793 5794 c2h = (const struct rtw89_c2h_pwr_int_notify *)skb->data; 5795 macid = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_MACID); 5796 ps = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS); 5797 5798 rcu_read_lock(); 5799 5800 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 5801 if (unlikely(!rtwsta_link)) 5802 goto out; 5803 5804 rtwsta = rtwsta_link->rtwsta; 5805 if (ps) 5806 set_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5807 else 5808 clear_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5809 5810 sta = rtwsta_to_sta(rtwsta); 5811 ieee80211_sta_ps_transition(sta, ps); 5812 5813 out: 5814 rcu_read_unlock(); 5815 } 5816 5817 static 5818 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5819 struct sk_buff *c2h, u32 len) = { 5820 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5821 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5822 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5823 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = rtw89_mac_c2h_bcn_resend, 5824 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5825 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5826 [RTW89_MAC_C2H_FUNC_TX_DUTY_RPT] = rtw89_mac_c2h_tx_duty_rpt, 5827 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5828 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5829 }; 5830 5831 static 5832 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5833 struct sk_buff *c2h, u32 len) = { 5834 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5835 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5836 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5837 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5838 [RTW89_MAC_C2H_FUNC_BCN_UPD_DONE] = rtw89_mac_c2h_bcn_upd_done, 5839 }; 5840 5841 static 5842 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5843 struct sk_buff *c2h, u32 len) = { 5844 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5845 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5846 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5847 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5848 }; 5849 5850 static 5851 void (* const rtw89_mac_c2h_misc_handler[])(struct rtw89_dev *rtwdev, 5852 struct sk_buff *c2h, u32 len) = { 5853 [RTW89_MAC_C2H_FUNC_TX_REPORT] = rtw89_mac_c2h_tx_rpt, 5854 }; 5855 5856 static 5857 void (* const rtw89_mac_c2h_mlo_handler[])(struct rtw89_dev *rtwdev, 5858 struct sk_buff *c2h, u32 len) = { 5859 [RTW89_MAC_C2H_FUNC_MLO_GET_TBL] = NULL, 5860 [RTW89_MAC_C2H_FUNC_MLO_EMLSR_TRANS_DONE] = NULL, 5861 [RTW89_MAC_C2H_FUNC_MLO_EMLSR_STA_CFG_DONE] = NULL, 5862 [RTW89_MAC_C2H_FUNC_MCMLO_RELINK_RPT] = NULL, 5863 [RTW89_MAC_C2H_FUNC_MCMLO_SN_SYNC_RPT] = NULL, 5864 [RTW89_MAC_C2H_FUNC_MLO_LINK_CFG_STAT] = rtw89_mac_c2h_mlo_link_cfg_stat, 5865 [RTW89_MAC_C2H_FUNC_MLO_DM_DBG_DUMP] = NULL, 5866 }; 5867 5868 static 5869 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 5870 struct sk_buff *c2h, u32 len) = { 5871 [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 5872 [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 5873 }; 5874 5875 static 5876 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev, 5877 struct sk_buff *c2h, u32 len) = { 5878 [RTW89_MAC_C2H_FUNC_AOAC_REPORT] = rtw89_mac_c2h_wow_aoac_rpt, 5879 }; 5880 5881 static 5882 void (* const rtw89_mac_c2h_ap_handler[])(struct rtw89_dev *rtwdev, 5883 struct sk_buff *c2h, u32 len) = { 5884 [RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY] = rtw89_mac_c2h_pwr_int_notify, 5885 }; 5886 5887 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 5888 struct sk_buff *skb) 5889 { 5890 const struct rtw89_c2h_scanofld *c2h = 5891 (const struct rtw89_c2h_scanofld *)skb->data; 5892 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5893 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 5894 struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(skb); 5895 struct rtw89_completion_data data = {}; 5896 unsigned int cond; 5897 u8 status, reason; 5898 5899 attr->is_scan_event = 1; 5900 attr->scan_seq = scan_info->seq; 5901 5902 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5903 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5904 data.err = status != RTW89_SCAN_STATUS_SUCCESS; 5905 5906 if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 5907 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 5908 cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 5909 else 5910 cond = RTW89_SCANOFLD_WAIT_COND_STOP; 5911 5912 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5913 } 5914 } 5915 5916 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5917 u8 class, u8 func) 5918 { 5919 switch (class) { 5920 default: 5921 return false; 5922 case RTW89_MAC_C2H_CLASS_INFO: 5923 switch (func) { 5924 default: 5925 return false; 5926 case RTW89_MAC_C2H_FUNC_REC_ACK: 5927 case RTW89_MAC_C2H_FUNC_DONE_ACK: 5928 return true; 5929 } 5930 case RTW89_MAC_C2H_CLASS_OFLD: 5931 switch (func) { 5932 default: 5933 return false; 5934 case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 5935 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 5936 return false; 5937 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 5938 return true; 5939 } 5940 case RTW89_MAC_C2H_CLASS_MCC: 5941 return true; 5942 case RTW89_MAC_C2H_CLASS_MISC: 5943 return true; 5944 case RTW89_MAC_C2H_CLASS_MLO: 5945 return true; 5946 case RTW89_MAC_C2H_CLASS_MRC: 5947 return true; 5948 case RTW89_MAC_C2H_CLASS_WOW: 5949 return true; 5950 case RTW89_MAC_C2H_CLASS_AP: 5951 switch (func) { 5952 default: 5953 return false; 5954 case RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY: 5955 return true; 5956 } 5957 } 5958 } 5959 5960 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5961 u32 len, u8 class, u8 func) 5962 { 5963 void (*handler)(struct rtw89_dev *rtwdev, 5964 struct sk_buff *c2h, u32 len) = NULL; 5965 5966 switch (class) { 5967 case RTW89_MAC_C2H_CLASS_INFO: 5968 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 5969 handler = rtw89_mac_c2h_info_handler[func]; 5970 break; 5971 case RTW89_MAC_C2H_CLASS_OFLD: 5972 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 5973 handler = rtw89_mac_c2h_ofld_handler[func]; 5974 break; 5975 case RTW89_MAC_C2H_CLASS_MCC: 5976 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 5977 handler = rtw89_mac_c2h_mcc_handler[func]; 5978 break; 5979 case RTW89_MAC_C2H_CLASS_MISC: 5980 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MISC) 5981 handler = rtw89_mac_c2h_misc_handler[func]; 5982 break; 5983 case RTW89_MAC_C2H_CLASS_MLO: 5984 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MLO) 5985 handler = rtw89_mac_c2h_mlo_handler[func]; 5986 break; 5987 case RTW89_MAC_C2H_CLASS_MRC: 5988 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 5989 handler = rtw89_mac_c2h_mrc_handler[func]; 5990 break; 5991 case RTW89_MAC_C2H_CLASS_WOW: 5992 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_WOW) 5993 handler = rtw89_mac_c2h_wow_handler[func]; 5994 break; 5995 case RTW89_MAC_C2H_CLASS_AP: 5996 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_AP) 5997 handler = rtw89_mac_c2h_ap_handler[func]; 5998 break; 5999 case RTW89_MAC_C2H_CLASS_FWDBG: 6000 case RTW89_MAC_C2H_CLASS_ROLE: 6001 return; 6002 default: 6003 break; 6004 } 6005 if (!handler) { 6006 rtw89_info_once(rtwdev, "MAC c2h class %d func %d not support\n", 6007 class, func); 6008 return; 6009 } 6010 handler(rtwdev, skb, len); 6011 } 6012 6013 static 6014 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 6015 enum rtw89_phy_idx phy_idx, 6016 u32 reg_base, u32 *cr) 6017 { 6018 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 6019 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 6020 6021 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 6022 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 6023 addr); 6024 goto error; 6025 } 6026 6027 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 6028 if (mode == RTW89_QTA_SCC) { 6029 rtw89_err(rtwdev, 6030 "[TXPWR] addr=0x%x but hw not enable\n", 6031 addr); 6032 goto error; 6033 } 6034 6035 *cr = addr; 6036 return true; 6037 6038 error: 6039 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 6040 addr, phy_idx); 6041 6042 return false; 6043 } 6044 6045 static 6046 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 6047 { 6048 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 6049 int ret; 6050 6051 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6052 if (ret) 6053 return ret; 6054 6055 if (!enable) { 6056 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 6057 return 0; 6058 } 6059 6060 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 6061 B_AX_APP_MAC_INFO_RPT | 6062 B_AX_APP_PLCP_HDR_RPT | 6063 B_AX_PPDU_STAT_RPT_CRC32); 6064 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 6065 RTW89_PRPT_DEST_HOST); 6066 6067 return 0; 6068 } 6069 6070 static 6071 void __rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 6072 { 6073 #define MAC_AX_TIME_TH_SH 5 6074 #define MAC_AX_LEN_TH_SH 4 6075 #define MAC_AX_TIME_TH_MAX 255 6076 #define MAC_AX_LEN_TH_MAX 255 6077 #define MAC_AX_TIME_TH_DEF 88 6078 #define MAC_AX_LEN_TH_DEF 4080 6079 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6080 struct ieee80211_hw *hw = rtwdev->hw; 6081 u32 rts_threshold = hw->wiphy->rts_threshold; 6082 u32 time_th, len_th; 6083 u32 reg; 6084 6085 if (rts_threshold == (u32)-1) { 6086 time_th = MAC_AX_TIME_TH_DEF; 6087 len_th = MAC_AX_LEN_TH_DEF; 6088 } else { 6089 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 6090 len_th = rts_threshold; 6091 } 6092 6093 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 6094 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 6095 6096 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 6097 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 6098 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 6099 } 6100 6101 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev) 6102 { 6103 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 6104 if (rtwdev->dbcc_en) 6105 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_1); 6106 } 6107 6108 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 6109 { 6110 bool empty; 6111 int ret; 6112 6113 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6114 return; 6115 6116 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 6117 10000, 200000, false, rtwdev); 6118 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 6119 rtw89_info(rtwdev, "timed out to flush queues\n"); 6120 } 6121 6122 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 6123 { 6124 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 6125 u8 val; 6126 u16 val16; 6127 u32 val32; 6128 int ret; 6129 6130 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 6131 if (chip_id != RTL8851B && chip_id != RTL8852BT) 6132 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 6133 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 6134 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 6135 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 6136 if (chip_id != RTL8851B && chip_id != RTL8852BT) 6137 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 6138 6139 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 6140 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 6141 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 6142 6143 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 6144 if (ret) { 6145 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6146 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 6147 return ret; 6148 } 6149 val32 = val32 & B_AX_WL_RX_CTRL; 6150 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 6151 if (ret) { 6152 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6153 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 6154 return ret; 6155 } 6156 6157 switch (coex->pta_mode) { 6158 case RTW89_MAC_AX_COEX_RTK_MODE: 6159 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 6160 val &= ~B_AX_BTMODE_MASK; 6161 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 6162 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 6163 6164 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 6165 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 6166 6167 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 6168 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 6169 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 6170 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 6171 break; 6172 case RTW89_MAC_AX_COEX_CSR_MODE: 6173 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 6174 val &= ~B_AX_BTMODE_MASK; 6175 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 6176 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 6177 6178 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 6179 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 6180 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 6181 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 6182 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 6183 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 6184 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 6185 val16 |= B_AX_ENHANCED_BT; 6186 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 6187 6188 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 6189 break; 6190 default: 6191 return -EINVAL; 6192 } 6193 6194 switch (coex->direction) { 6195 case RTW89_MAC_AX_COEX_INNER: 6196 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6197 val = (val & ~BIT(2)) | BIT(1); 6198 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6199 break; 6200 case RTW89_MAC_AX_COEX_OUTPUT: 6201 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6202 val = val | BIT(1) | BIT(0); 6203 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6204 break; 6205 case RTW89_MAC_AX_COEX_INPUT: 6206 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6207 val = val & ~(BIT(2) | BIT(1)); 6208 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6209 break; 6210 default: 6211 return -EINVAL; 6212 } 6213 6214 return 0; 6215 } 6216 EXPORT_SYMBOL(rtw89_mac_coex_init); 6217 6218 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 6219 const struct rtw89_mac_ax_coex *coex) 6220 { 6221 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 6222 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 6223 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 6224 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 6225 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 6226 6227 switch (coex->pta_mode) { 6228 case RTW89_MAC_AX_COEX_RTK_MODE: 6229 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 6230 MAC_AX_RTK_MODE); 6231 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 6232 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 6233 break; 6234 case RTW89_MAC_AX_COEX_CSR_MODE: 6235 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 6236 MAC_AX_CSR_MODE); 6237 break; 6238 default: 6239 return -EINVAL; 6240 } 6241 6242 return 0; 6243 } 6244 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 6245 6246 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6247 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6248 { 6249 u32 val = 0, ret; 6250 6251 if (gnt_cfg->band[0].gnt_bt) 6252 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 6253 6254 if (gnt_cfg->band[0].gnt_bt_sw_en) 6255 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 6256 6257 if (gnt_cfg->band[0].gnt_wl) 6258 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 6259 6260 if (gnt_cfg->band[0].gnt_wl_sw_en) 6261 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 6262 6263 if (gnt_cfg->band[1].gnt_bt) 6264 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 6265 6266 if (gnt_cfg->band[1].gnt_bt_sw_en) 6267 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 6268 6269 if (gnt_cfg->band[1].gnt_wl) 6270 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 6271 6272 if (gnt_cfg->band[1].gnt_wl_sw_en) 6273 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 6274 6275 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 6276 if (ret) { 6277 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6278 rtw89_err(rtwdev, "Write LTE fail!\n"); 6279 return ret; 6280 } 6281 6282 return 0; 6283 } 6284 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 6285 6286 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 6287 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6288 { 6289 u32 val = 0; 6290 6291 if (gnt_cfg->band[0].gnt_bt) 6292 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 6293 B_AX_GNT_BT_TX_VAL; 6294 else 6295 val |= B_AX_WL_ACT_VAL; 6296 6297 if (gnt_cfg->band[0].gnt_bt_sw_en) 6298 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 6299 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 6300 6301 if (gnt_cfg->band[0].gnt_wl) 6302 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 6303 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 6304 6305 if (gnt_cfg->band[0].gnt_wl_sw_en) 6306 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 6307 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 6308 6309 if (gnt_cfg->band[1].gnt_bt) 6310 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 6311 B_AX_GNT_BT_TX_VAL; 6312 else 6313 val |= B_AX_WL_ACT_VAL; 6314 6315 if (gnt_cfg->band[1].gnt_bt_sw_en) 6316 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 6317 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 6318 6319 if (gnt_cfg->band[1].gnt_wl) 6320 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 6321 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 6322 6323 if (gnt_cfg->band[1].gnt_wl_sw_en) 6324 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 6325 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 6326 6327 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 6328 6329 return 0; 6330 } 6331 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 6332 6333 static 6334 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 6335 { 6336 u32 reg; 6337 u16 val; 6338 int ret; 6339 6340 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 6341 if (ret) 6342 return ret; 6343 6344 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 6345 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 6346 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 6347 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 6348 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 6349 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 6350 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 6351 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 6352 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 6353 B_AX_PLT_EN; 6354 rtw89_write16(rtwdev, reg, val); 6355 6356 return 0; 6357 } 6358 6359 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 6360 { 6361 u32 fw_sb; 6362 6363 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 6364 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 6365 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 6366 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6367 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 6368 else 6369 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 6370 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 6371 val = B_AX_TOGGLE | 6372 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 6373 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 6374 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 6375 fsleep(1000); /* avoid BT FW loss information */ 6376 } 6377 6378 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 6379 { 6380 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 6381 } 6382 6383 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6384 { 6385 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 6386 6387 val = wl ? val | BIT(2) : val & ~BIT(2); 6388 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 6389 6390 return 0; 6391 } 6392 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 6393 6394 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 6395 { 6396 struct rtw89_btc *btc = &rtwdev->btc; 6397 struct rtw89_btc_dm *dm = &btc->dm; 6398 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 6399 int i; 6400 6401 if (wl) 6402 return 0; 6403 6404 for (i = 0; i < RTW89_PHY_NUM; i++) { 6405 g[i].gnt_bt_sw_en = 1; 6406 g[i].gnt_bt = 1; 6407 g[i].gnt_wl_sw_en = 1; 6408 g[i].gnt_wl = 0; 6409 } 6410 6411 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 6412 } 6413 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 6414 6415 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 6416 { 6417 const struct rtw89_chip_info *chip = rtwdev->chip; 6418 u8 val = 0; 6419 6420 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) 6421 return false; 6422 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6423 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 6424 B_AX_LTE_MUX_CTRL_PATH >> 24); 6425 6426 return !!val; 6427 } 6428 6429 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 6430 { 6431 u32 reg; 6432 u16 cnt; 6433 6434 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 6435 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 6436 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 6437 6438 return cnt; 6439 } 6440 6441 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 6442 bool keep) 6443 { 6444 u32 reg; 6445 6446 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 6447 return; 6448 6449 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 6450 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6451 if (keep) { 6452 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6453 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6454 BFRP_RX_STANDBY_TIMER_KEEP); 6455 } else { 6456 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6457 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6458 BFRP_RX_STANDBY_TIMER_RELEASE); 6459 } 6460 } 6461 6462 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 6463 { 6464 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6465 u32 reg; 6466 u32 mask = mac->bfee_ctrl.mask; 6467 6468 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 6469 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 6470 if (en) { 6471 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6472 rtw89_write32_set(rtwdev, reg, mask); 6473 } else { 6474 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6475 rtw89_write32_clr(rtwdev, reg, mask); 6476 } 6477 } 6478 6479 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 6480 { 6481 u32 reg; 6482 u32 val32; 6483 int ret; 6484 6485 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6486 if (ret) 6487 return ret; 6488 6489 /* AP mode set tx gid to 63 */ 6490 /* STA mode set tx gid to 0(default) */ 6491 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 6492 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 6493 6494 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 6495 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 6496 6497 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6498 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 6499 rtw89_write32(rtwdev, reg, val32); 6500 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 6501 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 6502 6503 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6504 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 6505 B_AX_BFMEE_USE_NSTS | 6506 B_AX_BFMEE_CSI_GID_SEL | 6507 B_AX_BFMEE_CSI_FORCE_RETE_EN); 6508 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 6509 rtw89_write32(rtwdev, reg, 6510 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 6511 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 6512 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 6513 6514 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 6515 rtw89_write32_set(rtwdev, reg, 6516 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 6517 6518 return 0; 6519 } 6520 6521 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 6522 struct rtw89_vif_link *rtwvif_link, 6523 struct rtw89_sta_link *rtwsta_link) 6524 { 6525 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 6526 struct ieee80211_link_sta *link_sta; 6527 u8 mac_idx = rtwvif_link->mac_idx; 6528 u8 port_sel = rtwvif_link->port; 6529 u8 sound_dim = 3, t; 6530 u8 *phy_cap; 6531 u32 reg; 6532 u16 val; 6533 int ret; 6534 6535 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6536 if (ret) 6537 return ret; 6538 6539 rcu_read_lock(); 6540 6541 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6542 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; 6543 6544 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6545 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 6546 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 6547 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 6548 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 6549 phy_cap[5]); 6550 sound_dim = min(sound_dim, t); 6551 } 6552 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6553 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 6554 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 6555 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 6556 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 6557 link_sta->vht_cap.cap); 6558 sound_dim = min(sound_dim, t); 6559 } 6560 nc = min(nc, sound_dim); 6561 nr = min(nr, sound_dim); 6562 6563 rcu_read_unlock(); 6564 6565 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6566 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6567 6568 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 6569 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 6570 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 6571 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 6572 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 6573 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 6574 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 6575 6576 if (port_sel == 0) 6577 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6578 else 6579 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 6580 6581 rtw89_write16(rtwdev, reg, val); 6582 6583 return 0; 6584 } 6585 6586 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 6587 struct rtw89_vif_link *rtwvif_link, 6588 struct rtw89_sta_link *rtwsta_link) 6589 { 6590 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 6591 struct ieee80211_link_sta *link_sta; 6592 u8 mac_idx = rtwvif_link->mac_idx; 6593 u32 reg; 6594 int ret; 6595 6596 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6597 if (ret) 6598 return ret; 6599 6600 rcu_read_lock(); 6601 6602 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6603 6604 if (link_sta->he_cap.has_he) { 6605 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 6606 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 6607 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 6608 } 6609 if (link_sta->vht_cap.vht_supported) { 6610 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 6611 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 6612 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 6613 } 6614 if (link_sta->ht_cap.ht_supported) { 6615 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 6616 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 6617 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 6618 } 6619 6620 rcu_read_unlock(); 6621 6622 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6623 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6624 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 6625 rtw89_write32(rtwdev, 6626 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 6627 rrsc); 6628 6629 return 0; 6630 } 6631 6632 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 6633 struct rtw89_vif_link *rtwvif_link, 6634 struct rtw89_sta_link *rtwsta_link) 6635 { 6636 struct ieee80211_link_sta *link_sta; 6637 bool has_beamformer_cap; 6638 6639 rcu_read_lock(); 6640 6641 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6642 has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta); 6643 6644 rcu_read_unlock(); 6645 6646 if (has_beamformer_cap) { 6647 rtw89_debug(rtwdev, RTW89_DBG_BF, 6648 "initialize bfee for new association\n"); 6649 rtw89_mac_init_bfee_ax(rtwdev, rtwvif_link->mac_idx); 6650 rtw89_mac_set_csi_para_reg_ax(rtwdev, rtwvif_link, rtwsta_link); 6651 rtw89_mac_csi_rrsc_ax(rtwdev, rtwvif_link, rtwsta_link); 6652 } 6653 } 6654 6655 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, 6656 struct rtw89_vif_link *rtwvif_link, 6657 struct rtw89_sta_link *rtwsta_link) 6658 { 6659 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, false); 6660 } 6661 6662 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6663 struct ieee80211_bss_conf *conf) 6664 { 6665 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 6666 struct rtw89_vif_link *rtwvif_link; 6667 u8 mac_idx; 6668 __le32 *p; 6669 6670 rtwvif_link = rtwvif->links[conf->link_id]; 6671 if (unlikely(!rtwvif_link)) { 6672 rtw89_err(rtwdev, 6673 "%s: rtwvif link (link_id %u) is not active\n", 6674 __func__, conf->link_id); 6675 return; 6676 } 6677 6678 mac_idx = rtwvif_link->mac_idx; 6679 6680 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 6681 6682 p = (__le32 *)conf->mu_group.membership; 6683 rtw89_write32(rtwdev, 6684 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 6685 le32_to_cpu(p[0])); 6686 rtw89_write32(rtwdev, 6687 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 6688 le32_to_cpu(p[1])); 6689 6690 p = (__le32 *)conf->mu_group.position; 6691 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 6692 le32_to_cpu(p[0])); 6693 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 6694 le32_to_cpu(p[1])); 6695 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 6696 le32_to_cpu(p[2])); 6697 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 6698 le32_to_cpu(p[3])); 6699 } 6700 6701 struct rtw89_mac_bf_monitor_iter_data { 6702 struct rtw89_dev *rtwdev; 6703 struct rtw89_sta_link *down_rtwsta_link; 6704 int count; 6705 }; 6706 6707 static 6708 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 6709 { 6710 struct rtw89_mac_bf_monitor_iter_data *iter_data = 6711 (struct rtw89_mac_bf_monitor_iter_data *)data; 6712 struct rtw89_sta_link *down_rtwsta_link = iter_data->down_rtwsta_link; 6713 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6714 struct ieee80211_link_sta *link_sta; 6715 struct rtw89_sta_link *rtwsta_link; 6716 bool has_beamformer_cap = false; 6717 int *count = &iter_data->count; 6718 unsigned int link_id; 6719 6720 rcu_read_lock(); 6721 6722 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6723 if (rtwsta_link == down_rtwsta_link) 6724 continue; 6725 6726 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 6727 if (rtw89_sta_has_beamformer_cap(link_sta)) { 6728 has_beamformer_cap = true; 6729 break; 6730 } 6731 } 6732 6733 if (has_beamformer_cap) 6734 (*count)++; 6735 6736 rcu_read_unlock(); 6737 } 6738 6739 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 6740 struct rtw89_sta_link *rtwsta_link, 6741 bool disconnect) 6742 { 6743 struct rtw89_mac_bf_monitor_iter_data data; 6744 6745 data.rtwdev = rtwdev; 6746 data.down_rtwsta_link = disconnect ? rtwsta_link : NULL; 6747 data.count = 0; 6748 ieee80211_iterate_stations_atomic(rtwdev->hw, 6749 rtw89_mac_bf_monitor_calc_iter, 6750 &data); 6751 6752 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 6753 if (data.count) 6754 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6755 else 6756 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6757 } 6758 6759 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 6760 { 6761 struct rtw89_traffic_stats *stats = &rtwdev->stats; 6762 struct rtw89_vif_link *rtwvif_link; 6763 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 6764 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6765 struct rtw89_vif *rtwvif; 6766 bool keep_timer = true; 6767 unsigned int link_id; 6768 bool old_keep_timer; 6769 6770 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6771 6772 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 6773 keep_timer = false; 6774 6775 if (keep_timer != old_keep_timer) { 6776 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6777 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6778 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif_link->mac_idx, 6779 keep_timer); 6780 } 6781 6782 if (en == old) 6783 return; 6784 6785 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6786 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6787 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, en); 6788 } 6789 6790 static int 6791 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6792 u32 tx_time) 6793 { 6794 #define MAC_AX_DFLT_TX_TIME 5280 6795 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6796 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6797 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 6798 u32 reg; 6799 int ret = 0; 6800 6801 if (rtwsta_link->cctl_tx_time) { 6802 rtwsta_link->ampdu_max_time = (max_tx_time - 512) >> 9; 6803 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6804 } else { 6805 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6806 if (ret) { 6807 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 6808 return ret; 6809 } 6810 6811 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_limit.addr, mac_idx); 6812 rtw89_write32_mask(rtwdev, reg, mac->agg_limit.mask, 6813 max_tx_time >> 5); 6814 } 6815 6816 return ret; 6817 } 6818 6819 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6820 bool resume, u32 tx_time) 6821 { 6822 int ret = 0; 6823 6824 if (!resume) { 6825 rtwsta_link->cctl_tx_time = true; 6826 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6827 } else { 6828 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6829 rtwsta_link->cctl_tx_time = false; 6830 } 6831 6832 return ret; 6833 } 6834 6835 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6836 u32 *tx_time) 6837 { 6838 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6839 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6840 u32 reg; 6841 int ret = 0; 6842 6843 if (rtwsta_link->cctl_tx_time) { 6844 *tx_time = (rtwsta_link->ampdu_max_time + 1) << 9; 6845 } else { 6846 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6847 if (ret) { 6848 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 6849 return ret; 6850 } 6851 6852 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_limit.addr, mac_idx); 6853 *tx_time = rtw89_read32_mask(rtwdev, reg, mac->agg_limit.mask) << 5; 6854 } 6855 6856 return ret; 6857 } 6858 6859 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 6860 struct rtw89_sta_link *rtwsta_link, 6861 bool resume, u8 tx_retry) 6862 { 6863 int ret = 0; 6864 6865 rtwsta_link->data_tx_cnt_lmt = tx_retry; 6866 6867 if (!resume) { 6868 rtwsta_link->cctl_tx_retry_limit = true; 6869 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6870 } else { 6871 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6872 rtwsta_link->cctl_tx_retry_limit = false; 6873 } 6874 6875 return ret; 6876 } 6877 6878 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 6879 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry) 6880 { 6881 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6882 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6883 u32 reg; 6884 int ret = 0; 6885 6886 if (rtwsta_link->cctl_tx_retry_limit) { 6887 *tx_retry = rtwsta_link->data_tx_cnt_lmt; 6888 } else { 6889 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6890 if (ret) { 6891 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 6892 return ret; 6893 } 6894 6895 reg = rtw89_mac_reg_by_idx(rtwdev, mac->txcnt_limit.addr, mac_idx); 6896 *tx_retry = rtw89_read32_mask(rtwdev, reg, mac->txcnt_limit.mask); 6897 } 6898 6899 return ret; 6900 } 6901 6902 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 6903 struct rtw89_vif_link *rtwvif_link, bool en) 6904 { 6905 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6906 u8 mac_idx = rtwvif_link->mac_idx; 6907 u16 set = mac->muedca_ctrl.mask; 6908 u32 reg; 6909 int ret; 6910 6911 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6912 if (ret) 6913 return ret; 6914 6915 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 6916 if (en) 6917 rtw89_write16_set(rtwdev, reg, set); 6918 else 6919 rtw89_write16_clr(rtwdev, reg, set); 6920 6921 return 0; 6922 } 6923 6924 static 6925 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 6926 { 6927 u32 val32; 6928 int ret; 6929 6930 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6931 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 6932 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 6933 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 6934 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6935 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6936 6937 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6938 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6939 if (ret) { 6940 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 6941 offset, val, mask); 6942 return ret; 6943 } 6944 6945 return 0; 6946 } 6947 6948 static 6949 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 6950 { 6951 u32 val32; 6952 int ret; 6953 6954 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6955 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 6956 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 6957 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 6958 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6959 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6960 6961 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6962 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6963 if (ret) { 6964 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 6965 return ret; 6966 } 6967 6968 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 6969 6970 return 0; 6971 } 6972 6973 static 6974 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, 6975 struct rtw89_vif_link *rtwvif_link, 6976 struct rtw89_sta_link *rtwsta_link) 6977 { 6978 static const enum rtw89_pkt_drop_sel sels[] = { 6979 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 6980 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 6981 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 6982 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 6983 }; 6984 struct rtw89_pkt_drop_params params = {0}; 6985 int i; 6986 6987 params.mac_band = rtwvif_link->mac_idx; 6988 params.macid = rtwsta_link->mac_id; 6989 params.port = rtwvif_link->port; 6990 params.mbssid = 0; 6991 params.tf_trs = rtwvif_link->trigger; 6992 6993 for (i = 0; i < ARRAY_SIZE(sels); i++) { 6994 params.sel = sels[i]; 6995 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6996 } 6997 } 6998 6999 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 7000 { 7001 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 7002 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 7003 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 7004 struct rtw89_vif_link *rtwvif_link; 7005 struct rtw89_sta_link *rtwsta_link; 7006 struct rtw89_vif *target = data; 7007 unsigned int link_id; 7008 7009 if (rtwvif != target) 7010 return; 7011 7012 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 7013 rtwvif_link = rtwsta_link->rtwvif_link; 7014 rtw89_mac_pkt_drop_sta(rtwdev, rtwvif_link, rtwsta_link); 7015 } 7016 } 7017 7018 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 7019 { 7020 ieee80211_iterate_stations_atomic(rtwdev->hw, 7021 rtw89_mac_pkt_drop_vif_iter, 7022 rtwvif); 7023 } 7024 7025 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 7026 enum rtw89_mac_idx band) 7027 { 7028 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7029 struct rtw89_pkt_drop_params params = {0}; 7030 bool empty; 7031 int i, ret = 0, try_cnt = 3; 7032 7033 params.mac_band = band; 7034 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 7035 7036 for (i = 0; i < try_cnt; i++) { 7037 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 7038 50000, false, rtwdev); 7039 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 7040 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 7041 else 7042 return 0; 7043 } 7044 return ret; 7045 } 7046 7047 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 7048 { 7049 struct rtw89_mac_h2c_info h2c_info = {}; 7050 struct rtw89_mac_c2h_info c2h_info = {}; 7051 int ret; 7052 7053 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 7054 return 0; 7055 7056 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; 7057 h2c_info.content_len = sizeof(h2c_info.u.hdr); 7058 h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); 7059 7060 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 7061 if (ret) 7062 return ret; 7063 7064 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) 7065 ret = -EINVAL; 7066 7067 return ret; 7068 } 7069 7070 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 7071 { 7072 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7073 const struct rtw89_chip_info *chip = rtwdev->chip; 7074 int ret; 7075 7076 if (enable_wow) { 7077 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 7078 if (ret) { 7079 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 7080 return ret; 7081 } 7082 7083 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 7084 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 7085 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 7086 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 7087 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 7088 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 7089 rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 7090 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 7091 7092 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 7093 return 0; 7094 7095 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 7096 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 7097 else 7098 rtw89_write32_set(rtwdev, R_AX_DBG_WOW, 7099 B_AX_DBG_WOW_CPU_IO_RX_EN); 7100 } else { 7101 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 7102 if (ret) { 7103 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 7104 return ret; 7105 } 7106 7107 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 7108 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 7109 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 7110 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 7111 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 7112 } 7113 7114 return 0; 7115 } 7116 7117 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 7118 { 7119 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 7120 7121 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 7122 } 7123 7124 static 7125 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 7126 bool h2c_or_fwdl) 7127 { 7128 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 7129 u32 timeout; 7130 u8 val; 7131 7132 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 7133 timeout = FWDL_WAIT_CNT_USB; 7134 else 7135 timeout = FWDL_WAIT_CNT; 7136 7137 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 7138 1, timeout, false, 7139 rtwdev, R_AX_WCPU_FW_CTRL); 7140 } 7141 7142 static 7143 void rtw89_fwdl_secure_idmem_share_mode_ax(struct rtw89_dev *rtwdev, u8 mode) 7144 { 7145 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 7146 7147 if (!sec->secure_boot) 7148 return; 7149 7150 rtw89_write32_mask(rtwdev, R_AX_WCPU_FW_CTRL, 7151 B_AX_IDMEM_SHARE_MODE_RECORD_MASK, mode); 7152 rtw89_write32_set(rtwdev, R_AX_WCPU_FW_CTRL, 7153 B_AX_IDMEM_SHARE_MODE_RECORD_VALID); 7154 } 7155 7156 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 7157 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 7158 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 7159 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 7160 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 7161 .mem_page_size = MAC_MEM_DUMP_PAGE_SIZE_AX, 7162 .rx_fltr = R_AX_RX_FLTR_OPT, 7163 .port_base = &rtw89_port_base_ax, 7164 .agg_len_ht = R_AX_AGG_LEN_HT_0, 7165 .ps_status = R_AX_PPWRBIT_SETTING, 7166 7167 .muedca_ctrl = { 7168 .addr = R_AX_MUEDCA_EN, 7169 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 7170 }, 7171 .bfee_ctrl = { 7172 .addr = R_AX_BFMEE_RESP_OPTION, 7173 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 7174 B_AX_BFMEE_HE_NDPA_EN, 7175 }, 7176 .narrow_bw_ru_dis = { 7177 .addr = R_AX_RXTRIG_TEST_USER_2, 7178 .mask = B_AX_RXTRIG_RU26_DIS, 7179 }, 7180 .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 7181 .agg_limit = {.addr = R_AX_AMPDU_AGG_LIMIT, .mask = B_AX_AMPDU_MAX_TIME_MASK,}, 7182 .txcnt_limit = {.addr = R_AX_TXCNT, .mask = B_AX_L_TXCNT_LMT_MASK,}, 7183 7184 .check_mac_en = rtw89_mac_check_mac_en_ax, 7185 .sys_init = sys_init_ax, 7186 .trx_init = trx_init_ax, 7187 .hci_func_en = rtw89_mac_hci_func_en_ax, 7188 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 7189 .dle_func_en = dle_func_en_ax, 7190 .dle_clk_en = dle_clk_en_ax, 7191 .bf_assoc = rtw89_mac_bf_assoc_ax, 7192 7193 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 7194 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 7195 .cfg_phy_rpt = NULL, 7196 7197 .dle_mix_cfg = dle_mix_cfg_ax, 7198 .chk_dle_rdy = chk_dle_rdy_ax, 7199 .dle_buf_req = dle_buf_req_ax, 7200 .hfc_func_en = hfc_func_en_ax, 7201 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 7202 .hfc_mix_cfg = hfc_mix_cfg_ax, 7203 .hfc_get_mix_info = hfc_get_mix_info_ax, 7204 .wde_quota_cfg = wde_quota_cfg_ax, 7205 .ple_quota_cfg = ple_quota_cfg_ax, 7206 .set_cpuio = set_cpuio_ax, 7207 .dle_quota_change = dle_quota_change_ax, 7208 7209 .disable_cpu = rtw89_mac_disable_cpu_ax, 7210 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 7211 .fwdl_get_status = rtw89_fw_get_rdy_ax, 7212 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 7213 .fwdl_secure_idmem_share_mode = rtw89_fwdl_secure_idmem_share_mode_ax, 7214 .parse_efuse_map = rtw89_parse_efuse_map_ax, 7215 .parse_phycap_map = rtw89_parse_phycap_map_ax, 7216 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 7217 .efuse_read_fw_secure = rtw89_efuse_read_fw_secure_ax, 7218 7219 .cfg_plt = rtw89_mac_cfg_plt_ax, 7220 .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 7221 7222 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 7223 7224 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 7225 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 7226 7227 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 7228 .dump_err_status = rtw89_mac_dump_err_status_ax, 7229 7230 .is_txq_empty = mac_is_txq_empty_ax, 7231 7232 .prep_chan_list = rtw89_hw_scan_prep_chan_list_ax, 7233 .free_chan_list = rtw89_hw_scan_free_chan_list_ax, 7234 .add_chan_list = rtw89_hw_scan_add_chan_list_ax, 7235 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_ax, 7236 .scan_offload = rtw89_fw_h2c_scan_offload_ax, 7237 7238 .wow_config_mac = rtw89_wow_config_mac_ax, 7239 }; 7240 EXPORT_SYMBOL(rtw89_mac_gen_ax); 7241