1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "util.h" 15 16 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 17 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 18 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 19 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 20 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 21 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 22 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 26 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 29 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 31 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 35 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 36 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 37 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 38 }; 39 40 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 41 u32 val, enum rtw89_mac_mem_sel sel) 42 { 43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44 u32 addr = mac->mem_base_addrs[sel] + offset; 45 46 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 47 rtw89_write32(rtwdev, mac->indir_access_addr, val); 48 } 49 50 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 51 enum rtw89_mac_mem_sel sel) 52 { 53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 54 u32 addr = mac->mem_base_addrs[sel] + offset; 55 56 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 57 return rtw89_read32(rtwdev, mac->indir_access_addr); 58 } 59 60 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 61 enum rtw89_mac_hwmod_sel sel) 62 { 63 u32 val, r_val; 64 65 if (sel == RTW89_DMAC_SEL) { 66 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 67 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 69 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 70 val = B_AX_CMAC_EN; 71 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 72 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 73 val = B_AX_CMAC1_FEN; 74 } else { 75 return -EINVAL; 76 } 77 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 78 (val & r_val) != val) 79 return -EFAULT; 80 81 return 0; 82 } 83 84 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 85 { 86 u8 lte_ctrl; 87 int ret; 88 89 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 90 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 91 if (ret) 92 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 93 94 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 95 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 96 97 return ret; 98 } 99 100 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 101 { 102 u8 lte_ctrl; 103 int ret; 104 105 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 106 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 107 if (ret) 108 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 109 110 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 111 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 112 113 return ret; 114 } 115 116 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 117 { 118 u32 ctrl_reg, data_reg, ctrl_data; 119 u32 val; 120 int ret; 121 122 switch (ctrl->type) { 123 case DLE_CTRL_TYPE_WDE: 124 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 125 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 126 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 127 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 128 B_AX_WDE_DFI_ACTIVE; 129 break; 130 case DLE_CTRL_TYPE_PLE: 131 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 132 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 133 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 134 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 135 B_AX_PLE_DFI_ACTIVE; 136 break; 137 default: 138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 139 return -EINVAL; 140 } 141 142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 143 144 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 145 1, 1000, false, rtwdev, ctrl_reg); 146 if (ret) { 147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 148 ctrl_reg, ctrl_data); 149 return ret; 150 } 151 152 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 153 return 0; 154 } 155 156 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 157 struct rtw89_mac_dle_dfi_quota *quota) 158 { 159 struct rtw89_mac_dle_dfi_ctrl ctrl; 160 int ret; 161 162 ctrl.type = quota->dle_type; 163 ctrl.target = DLE_DFI_TYPE_QUOTA; 164 ctrl.addr = quota->qtaid; 165 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 166 if (ret) { 167 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 168 return ret; 169 } 170 171 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 172 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 173 return 0; 174 } 175 176 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 177 struct rtw89_mac_dle_dfi_qempty *qempty) 178 { 179 struct rtw89_mac_dle_dfi_ctrl ctrl; 180 u32 ret; 181 182 ctrl.type = qempty->dle_type; 183 ctrl.target = DLE_DFI_TYPE_QEMPTY; 184 ctrl.addr = qempty->grpsel; 185 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 186 if (ret) { 187 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 188 return ret; 189 } 190 191 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 192 return 0; 193 } 194 195 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 196 { 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 209 } 210 211 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 212 { 213 struct rtw89_mac_dle_dfi_qempty qempty; 214 struct rtw89_mac_dle_dfi_quota quota; 215 struct rtw89_mac_dle_dfi_ctrl ctrl; 216 u32 val, not_empty, i; 217 int ret; 218 219 qempty.dle_type = DLE_CTRL_TYPE_PLE; 220 qempty.grpsel = 0; 221 qempty.qempty = ~(u32)0; 222 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 223 if (ret) 224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 225 else 226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 227 228 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 229 if (!(not_empty & BIT(0))) 230 continue; 231 ctrl.type = DLE_CTRL_TYPE_PLE; 232 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 233 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 234 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 235 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 236 if (ret) 237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 238 else 239 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 240 u32_get_bits(ctrl.out_data, 241 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 242 } 243 244 quota.dle_type = DLE_CTRL_TYPE_PLE; 245 quota.qtaid = 6; 246 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 247 if (ret) 248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 249 else 250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 251 quota.rsv_pgnum, quota.use_pgnum); 252 253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 255 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 257 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 258 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 259 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 260 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 261 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 262 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 263 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 264 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 265 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 266 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 267 268 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 269 quota.dle_type = DLE_CTRL_TYPE_PLE; 270 quota.qtaid = 7; 271 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 272 if (ret) 273 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 274 else 275 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 276 quota.rsv_pgnum, quota.use_pgnum); 277 278 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 279 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 280 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 282 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 283 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 284 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 285 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 286 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 287 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 288 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 289 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 290 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 291 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 292 } 293 294 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 295 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 298 299 dump_err_status_dispatcher_ax(rtwdev); 300 } 301 302 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 303 enum mac_ax_err_info err) 304 { 305 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 306 u32 dbg, event; 307 308 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 309 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 310 311 switch (event) { 312 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 313 rtw89_info(rtwdev, "quota lost!\n"); 314 mac->dump_qta_lost(rtwdev); 315 break; 316 default: 317 break; 318 } 319 } 320 321 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 322 { 323 const struct rtw89_chip_info *chip = rtwdev->chip; 324 u32 dmac_err; 325 int i, ret; 326 327 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 328 if (ret) { 329 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 330 return; 331 } 332 333 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 334 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 335 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 337 338 if (dmac_err) { 339 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 341 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 343 if (chip->chip_id == RTL8852C) { 344 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 345 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 346 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 348 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 352 } 353 } 354 355 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 356 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 357 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 360 if (chip->chip_id == RTL8852C) 361 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 363 else 364 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 365 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 366 } 367 368 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 369 if (chip->chip_id == RTL8852C) { 370 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 371 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 372 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 374 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 376 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 378 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 380 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 382 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 384 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 386 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 388 389 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 390 B_AX_DBG_SEL0, 0x8B); 391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392 B_AX_DBG_SEL1, 0x8B); 393 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 394 B_AX_SEL_0XC0_MASK, 1); 395 for (i = 0; i < 0x10; i++) { 396 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 397 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 398 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 399 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 400 } 401 } else if (chip->chip_id == RTL8922A) { 402 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 403 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 406 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 407 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 408 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 409 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 410 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 411 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 412 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 413 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 414 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 415 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 416 } else { 417 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 419 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 421 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 423 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 425 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 427 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 429 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 430 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 431 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 432 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 433 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 435 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 437 } 438 } 439 440 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 441 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 442 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 445 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 449 } 450 451 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 452 if (chip->chip_id == RTL8922A) { 453 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 454 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 455 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 456 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 457 } else { 458 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 459 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 462 } 463 } 464 465 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 466 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 468 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 470 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 471 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 472 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 474 } 475 476 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 477 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 478 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 479 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 486 } else { 487 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 491 } 492 } 493 494 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 495 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 501 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 503 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 509 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 510 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 515 if (chip->chip_id == RTL8922A) { 516 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 517 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 520 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 521 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 522 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 524 } else { 525 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 526 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 527 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 529 if (chip->chip_id == RTL8852C) { 530 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 531 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 532 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 533 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 534 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 535 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 536 } else { 537 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 538 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 543 } 544 } 545 } 546 547 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 548 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 549 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 552 } 553 554 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 555 if (chip->chip_id == RTL8922A) { 556 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 557 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 558 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 559 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 560 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 561 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 562 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 563 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 564 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 565 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 566 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 567 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 568 } else { 569 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 570 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 573 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 574 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 577 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 578 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 581 } 582 } 583 584 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 585 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 586 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 587 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 590 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 591 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 594 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 595 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 598 } else { 599 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 600 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 601 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 602 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 605 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 606 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 609 } 610 if (chip->chip_id == RTL8922A) { 611 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 612 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 615 } 616 } 617 618 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 619 if (chip->chip_id == RTL8922A) { 620 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 621 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 624 } else if (chip->chip_id == RTL8852C) { 625 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 626 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 629 } 630 } 631 632 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 633 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 634 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 635 RTW89_MAC_MEM_AXIDMA)); 636 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 637 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 638 RTW89_MAC_MEM_AXIDMA)); 639 } 640 641 if (dmac_err & B_BE_MLO_ERR_INT) { 642 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 643 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 644 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 646 } 647 648 if (dmac_err & B_BE_PLRLS_ERR_INT) { 649 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 650 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 653 } 654 } 655 656 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 657 u8 band) 658 { 659 const struct rtw89_chip_info *chip = rtwdev->chip; 660 u32 offset = 0; 661 u32 cmac_err; 662 int ret; 663 664 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 665 if (ret) { 666 if (band) 667 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 668 else 669 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 670 return; 671 } 672 673 if (band) 674 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 675 676 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 677 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 678 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 679 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 680 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 681 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 682 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 683 684 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 685 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 686 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 689 } 690 691 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 692 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 693 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 694 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 695 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 696 } 697 698 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 699 if (chip->chip_id == RTL8852C) { 700 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 701 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 704 } else { 705 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 706 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 707 } 708 } 709 710 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 711 if (chip->chip_id == RTL8852C) { 712 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 713 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 716 } else { 717 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 718 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 719 } 720 } 721 722 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 723 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 724 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 725 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 726 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 727 } 728 729 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 730 if (chip->chip_id == RTL8852C) { 731 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 732 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 735 } else { 736 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 737 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 738 } 739 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 740 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 741 } 742 743 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 744 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 745 } 746 747 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 748 enum mac_ax_err_info err) 749 { 750 if (err != MAC_AX_ERR_L1_ERR_DMAC && 751 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 752 err != MAC_AX_ERR_L0_ERR_CMAC0 && 753 err != MAC_AX_ERR_L0_ERR_CMAC1 && 754 err != MAC_AX_ERR_RXI300) 755 return; 756 757 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 758 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 759 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 762 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 763 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 764 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 766 767 rtw89_mac_dump_dmac_err_status(rtwdev); 768 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 769 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 770 771 rtwdev->hci.ops->dump_err_status(rtwdev); 772 773 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 774 rtw89_mac_dump_l0_to_l1(rtwdev, err); 775 776 rtw89_info(rtwdev, "<---\n"); 777 } 778 779 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 780 { 781 struct rtw89_ser *ser = &rtwdev->ser; 782 u32 dmac_err, imr, isr; 783 int ret; 784 785 if (rtwdev->chip->chip_id == RTL8852C) { 786 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 787 if (ret) 788 return true; 789 790 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 791 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 792 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 793 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 794 795 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 796 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 797 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 798 return true; 799 } 800 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 801 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 802 return true; 803 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 804 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 805 return true; 806 } 807 } 808 809 return false; 810 } 811 812 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 813 { 814 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 815 u32 err, err_scnr; 816 int ret; 817 818 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 819 false, rtwdev, R_AX_HALT_C2H_CTRL); 820 if (ret) { 821 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 822 return ret; 823 } 824 825 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 826 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 827 828 err_scnr = RTW89_ERROR_SCENARIO(err); 829 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 830 err = MAC_AX_ERR_CPU_EXCEPTION; 831 else if (err_scnr == RTW89_WCPU_ASSERTION) 832 err = MAC_AX_ERR_ASSERTION; 833 else if (err_scnr == RTW89_RXI300_ERROR) 834 err = MAC_AX_ERR_RXI300; 835 836 if (rtw89_mac_suppress_log(rtwdev, err)) 837 return err; 838 839 rtw89_fw_st_dbg_dump(rtwdev); 840 mac->dump_err_status(rtwdev, err); 841 842 return err; 843 } 844 EXPORT_SYMBOL(rtw89_mac_get_err_status); 845 846 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 847 { 848 struct rtw89_ser *ser = &rtwdev->ser; 849 u32 halt; 850 int ret = 0; 851 852 if (err > MAC_AX_SET_ERR_MAX) { 853 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 854 return -EINVAL; 855 } 856 857 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 858 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 859 if (ret) { 860 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 861 return -EFAULT; 862 } 863 864 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 865 866 if (ser->prehandle_l1 && 867 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 868 return 0; 869 870 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 871 872 return 0; 873 } 874 EXPORT_SYMBOL(rtw89_mac_set_err_status); 875 876 static int hfc_reset_param(struct rtw89_dev *rtwdev) 877 { 878 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 879 struct rtw89_hfc_param_ini param_ini = {NULL}; 880 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 881 882 switch (rtwdev->hci.type) { 883 case RTW89_HCI_TYPE_PCIE: 884 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 885 param->en = 0; 886 break; 887 default: 888 return -EINVAL; 889 } 890 891 if (param_ini.pub_cfg) 892 param->pub_cfg = *param_ini.pub_cfg; 893 894 if (param_ini.prec_cfg) 895 param->prec_cfg = *param_ini.prec_cfg; 896 897 if (param_ini.ch_cfg) 898 param->ch_cfg = param_ini.ch_cfg; 899 900 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 901 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 902 param->mode = param_ini.mode; 903 904 return 0; 905 } 906 907 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 908 { 909 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 910 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 911 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 912 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 913 914 if (ch >= RTW89_DMA_CH_NUM) 915 return -EINVAL; 916 917 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 918 ch_cfg[ch].max > pub_cfg->pub_max) 919 return -EINVAL; 920 if (ch_cfg[ch].grp >= grp_num) 921 return -EINVAL; 922 923 return 0; 924 } 925 926 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 927 { 928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 929 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 930 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 931 932 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 933 if (rtwdev->chip->chip_id == RTL8852A) 934 return 0; 935 else 936 return -EFAULT; 937 } 938 939 return 0; 940 } 941 942 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 943 { 944 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 945 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 946 947 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 948 return -EFAULT; 949 950 return 0; 951 } 952 953 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 954 { 955 const struct rtw89_chip_info *chip = rtwdev->chip; 956 const struct rtw89_page_regs *regs = chip->page_regs; 957 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 958 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 959 int ret = 0; 960 u32 val = 0; 961 962 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 963 if (ret) 964 return ret; 965 966 ret = hfc_ch_cfg_chk(rtwdev, ch); 967 if (ret) 968 return ret; 969 970 if (ch > RTW89_DMA_B1HI) 971 return -EINVAL; 972 973 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 974 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 975 (cfg[ch].grp ? B_AX_GRP : 0); 976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 977 978 return 0; 979 } 980 981 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 982 { 983 const struct rtw89_chip_info *chip = rtwdev->chip; 984 const struct rtw89_page_regs *regs = chip->page_regs; 985 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 986 struct rtw89_hfc_ch_info *info = param->ch_info; 987 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 988 u32 val; 989 u32 ret; 990 991 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 992 if (ret) 993 return ret; 994 995 if (ch > RTW89_DMA_H2C) 996 return -EINVAL; 997 998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 999 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1000 if (ch < RTW89_DMA_H2C) 1001 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1002 else 1003 info[ch].used = cfg[ch].min - info[ch].aval; 1004 1005 return 0; 1006 } 1007 1008 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1009 { 1010 const struct rtw89_chip_info *chip = rtwdev->chip; 1011 const struct rtw89_page_regs *regs = chip->page_regs; 1012 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1013 u32 val; 1014 int ret; 1015 1016 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1017 if (ret) 1018 return ret; 1019 1020 ret = hfc_pub_cfg_chk(rtwdev); 1021 if (ret) 1022 return ret; 1023 1024 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1025 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1027 1028 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1030 1031 return 0; 1032 } 1033 1034 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1035 { 1036 const struct rtw89_chip_info *chip = rtwdev->chip; 1037 const struct rtw89_page_regs *regs = chip->page_regs; 1038 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1039 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1040 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1041 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1042 u32 val; 1043 1044 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1045 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1046 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1047 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1048 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1049 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1050 info->pub_aval = 1051 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1052 B_AX_PUB_AVAL_PG_MASK); 1053 info->wp_aval = 1054 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1055 B_AX_WP_AVAL_PG_MASK); 1056 1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1058 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1059 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1060 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1061 prec_cfg->ch011_full_cond = 1062 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1063 prec_cfg->h2c_full_cond = 1064 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1065 prec_cfg->wp_ch07_full_cond = 1066 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1067 prec_cfg->wp_ch811_full_cond = 1068 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1069 1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1071 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1072 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1073 1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1075 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1076 1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1078 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1079 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1080 1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1082 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1083 1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1085 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1086 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1087 } 1088 1089 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1090 { 1091 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1092 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1093 int ret; 1094 1095 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1096 if (ret) 1097 return ret; 1098 1099 mac->hfc_get_mix_info(rtwdev); 1100 1101 ret = hfc_pub_info_chk(rtwdev); 1102 if (param->en && ret) 1103 return ret; 1104 1105 return 0; 1106 } 1107 1108 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1109 { 1110 const struct rtw89_chip_info *chip = rtwdev->chip; 1111 const struct rtw89_page_regs *regs = chip->page_regs; 1112 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1113 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1114 u32 val; 1115 1116 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1118 1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1120 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1121 prec_cfg->h2c_full_cond); 1122 } 1123 1124 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1125 { 1126 const struct rtw89_chip_info *chip = rtwdev->chip; 1127 const struct rtw89_page_regs *regs = chip->page_regs; 1128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1129 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1130 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1131 u32 val; 1132 1133 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1134 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1136 1137 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1139 1140 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1141 B_AX_PREC_PAGE_WP_CH07_MASK) | 1142 u32_encode_bits(prec_cfg->wp_ch811_prec, 1143 B_AX_PREC_PAGE_WP_CH811_MASK); 1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1145 1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1147 param->mode, B_AX_HCI_FC_MODE_MASK); 1148 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1149 B_AX_HCI_FC_WD_FULL_COND_MASK); 1150 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1151 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1152 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1153 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1154 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1155 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1157 } 1158 1159 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1160 { 1161 const struct rtw89_chip_info *chip = rtwdev->chip; 1162 const struct rtw89_page_regs *regs = chip->page_regs; 1163 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1164 u32 val; 1165 1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1167 param->en = en; 1168 param->h2c_en = h2c_en; 1169 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1170 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1171 (val & ~B_AX_HCI_FC_CH12_EN); 1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1173 } 1174 1175 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1176 { 1177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1178 const struct rtw89_chip_info *chip = rtwdev->chip; 1179 u32 dma_ch_mask = chip->dma_ch_mask; 1180 u8 ch; 1181 u32 ret = 0; 1182 1183 if (reset) 1184 ret = hfc_reset_param(rtwdev); 1185 if (ret) 1186 return ret; 1187 1188 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1189 if (ret) 1190 return ret; 1191 1192 mac->hfc_func_en(rtwdev, false, false); 1193 1194 if (!en && h2c_en) { 1195 mac->hfc_h2c_cfg(rtwdev); 1196 mac->hfc_func_en(rtwdev, en, h2c_en); 1197 return ret; 1198 } 1199 1200 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1201 if (dma_ch_mask & BIT(ch)) 1202 continue; 1203 ret = hfc_ch_ctrl(rtwdev, ch); 1204 if (ret) 1205 return ret; 1206 } 1207 1208 ret = hfc_pub_ctrl(rtwdev); 1209 if (ret) 1210 return ret; 1211 1212 mac->hfc_mix_cfg(rtwdev); 1213 if (en || h2c_en) { 1214 mac->hfc_func_en(rtwdev, en, h2c_en); 1215 udelay(10); 1216 } 1217 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1218 if (dma_ch_mask & BIT(ch)) 1219 continue; 1220 ret = hfc_upd_ch_info(rtwdev, ch); 1221 if (ret) 1222 return ret; 1223 } 1224 ret = hfc_upd_mix_info(rtwdev); 1225 1226 return ret; 1227 } 1228 1229 #define PWR_POLL_CNT 2000 1230 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1231 const struct rtw89_pwr_cfg *cfg) 1232 { 1233 u8 val = 0; 1234 int ret; 1235 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1236 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1237 1238 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1239 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1240 1241 if (!ret) 1242 return 0; 1243 1244 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1245 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1247 1248 return -EBUSY; 1249 } 1250 1251 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1252 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1253 { 1254 const struct rtw89_pwr_cfg *cur_cfg; 1255 u32 addr; 1256 u8 val; 1257 1258 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1259 if (!(cur_cfg->intf_msk & intf_msk) || 1260 !(cur_cfg->cv_msk & cv_msk)) 1261 continue; 1262 1263 switch (cur_cfg->cmd) { 1264 case PWR_CMD_WRITE: 1265 addr = cur_cfg->addr; 1266 1267 if (cur_cfg->base == PWR_BASE_SDIO) 1268 addr |= SDIO_LOCAL_BASE_ADDR; 1269 1270 val = rtw89_read8(rtwdev, addr); 1271 val &= ~(cur_cfg->msk); 1272 val |= (cur_cfg->val & cur_cfg->msk); 1273 1274 rtw89_write8(rtwdev, addr, val); 1275 break; 1276 case PWR_CMD_POLL: 1277 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1278 return -EBUSY; 1279 break; 1280 case PWR_CMD_DELAY: 1281 if (cur_cfg->val == PWR_DELAY_US) 1282 udelay(cur_cfg->addr); 1283 else 1284 fsleep(cur_cfg->addr * 1000); 1285 break; 1286 default: 1287 return -EINVAL; 1288 } 1289 } 1290 1291 return 0; 1292 } 1293 1294 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1295 const struct rtw89_pwr_cfg * const *cfg_seq) 1296 { 1297 int ret; 1298 1299 for (; *cfg_seq; cfg_seq++) { 1300 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1301 PWR_INTF_MSK_PCIE, *cfg_seq); 1302 if (ret) 1303 return -EBUSY; 1304 } 1305 1306 return 0; 1307 } 1308 1309 static enum rtw89_rpwm_req_pwr_state 1310 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1311 { 1312 enum rtw89_rpwm_req_pwr_state state; 1313 1314 switch (rtwdev->ps_mode) { 1315 case RTW89_PS_MODE_RFOFF: 1316 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1317 break; 1318 case RTW89_PS_MODE_CLK_GATED: 1319 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1320 break; 1321 case RTW89_PS_MODE_PWR_GATED: 1322 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1323 break; 1324 default: 1325 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1326 break; 1327 } 1328 return state; 1329 } 1330 1331 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1332 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1333 bool notify_wake) 1334 { 1335 u16 request; 1336 1337 spin_lock_bh(&rtwdev->rpwm_lock); 1338 1339 request = rtw89_read16(rtwdev, R_AX_RPWM); 1340 request ^= request | PS_RPWM_TOGGLE; 1341 request |= req_pwr_state; 1342 1343 if (notify_wake) { 1344 request |= PS_RPWM_NOTIFY_WAKE; 1345 } else { 1346 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1347 RPWM_SEQ_NUM_MAX; 1348 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1349 rtwdev->mac.rpwm_seq_num); 1350 1351 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1352 request |= PS_RPWM_ACK; 1353 } 1354 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1355 1356 spin_unlock_bh(&rtwdev->rpwm_lock); 1357 } 1358 1359 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1360 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1361 { 1362 bool request_deep_mode; 1363 bool in_deep_mode; 1364 u8 rpwm_req_num; 1365 u8 cpwm_rsp_seq; 1366 u8 cpwm_seq; 1367 u8 cpwm_status; 1368 1369 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1370 request_deep_mode = true; 1371 else 1372 request_deep_mode = false; 1373 1374 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1375 in_deep_mode = true; 1376 else 1377 in_deep_mode = false; 1378 1379 if (request_deep_mode != in_deep_mode) 1380 return -EPERM; 1381 1382 if (request_deep_mode) 1383 return 0; 1384 1385 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1386 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1387 PS_CPWM_RSP_SEQ_NUM); 1388 1389 if (rpwm_req_num != cpwm_rsp_seq) 1390 return -EPERM; 1391 1392 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1393 CPWM_SEQ_NUM_MAX; 1394 1395 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1396 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1397 return -EPERM; 1398 1399 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1400 if (cpwm_status != req_pwr_state) 1401 return -EPERM; 1402 1403 return 0; 1404 } 1405 1406 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1407 { 1408 enum rtw89_rpwm_req_pwr_state state; 1409 unsigned long delay = enter ? 10 : 150; 1410 int ret; 1411 int i; 1412 1413 if (enter) 1414 state = rtw89_mac_get_req_pwr_state(rtwdev); 1415 else 1416 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1417 1418 for (i = 0; i < RPWM_TRY_CNT; i++) { 1419 rtw89_mac_send_rpwm(rtwdev, state, false); 1420 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1421 !ret, delay, 15000, false, 1422 rtwdev, state); 1423 if (!ret) 1424 break; 1425 1426 if (i == RPWM_TRY_CNT - 1) 1427 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1428 enter ? "entering" : "leaving"); 1429 else 1430 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1431 "%d time firmware failed to ack for %s ps mode\n", 1432 i + 1, enter ? "entering" : "leaving"); 1433 } 1434 } 1435 1436 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1437 { 1438 enum rtw89_rpwm_req_pwr_state state; 1439 1440 state = rtw89_mac_get_req_pwr_state(rtwdev); 1441 rtw89_mac_send_rpwm(rtwdev, state, true); 1442 } 1443 1444 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1445 { 1446 #define PWR_ACT 1 1447 const struct rtw89_chip_info *chip = rtwdev->chip; 1448 const struct rtw89_pwr_cfg * const *cfg_seq; 1449 int (*cfg_func)(struct rtw89_dev *rtwdev); 1450 int ret; 1451 u8 val; 1452 1453 if (on) { 1454 cfg_seq = chip->pwr_on_seq; 1455 cfg_func = chip->ops->pwr_on_func; 1456 } else { 1457 cfg_seq = chip->pwr_off_seq; 1458 cfg_func = chip->ops->pwr_off_func; 1459 } 1460 1461 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1462 __rtw89_leave_ps_mode(rtwdev); 1463 1464 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1465 if (on && val == PWR_ACT) { 1466 rtw89_err(rtwdev, "MAC has already powered on\n"); 1467 return -EBUSY; 1468 } 1469 1470 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1471 if (ret) 1472 return ret; 1473 1474 if (on) { 1475 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1476 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1477 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1478 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1479 } else { 1480 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1481 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1482 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1483 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1484 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1485 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1486 rtw89_set_entity_state(rtwdev, false); 1487 } 1488 1489 return 0; 1490 #undef PWR_ACT 1491 } 1492 1493 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1494 { 1495 rtw89_mac_power_switch(rtwdev, false); 1496 } 1497 1498 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1499 { 1500 u32 func_en = 0; 1501 u32 ck_en = 0; 1502 u32 c1pc_en = 0; 1503 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1504 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1505 1506 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1507 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1508 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1509 B_AX_CMAC_CRPRT; 1510 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1511 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1512 B_AX_RMAC_CKEN; 1513 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1514 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1515 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1516 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1517 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1518 1519 if (en) { 1520 if (mac_idx == RTW89_MAC_1) { 1521 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1522 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1523 B_AX_R_SYM_ISO_CMAC12PP); 1524 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1525 B_AX_CMAC1_FEN); 1526 } 1527 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1528 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1529 } else { 1530 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1531 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1532 if (mac_idx == RTW89_MAC_1) { 1533 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1534 B_AX_CMAC1_FEN); 1535 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1536 B_AX_R_SYM_ISO_CMAC12PP); 1537 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1538 } 1539 } 1540 1541 return 0; 1542 } 1543 1544 static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1545 { 1546 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1547 u32 val32; 1548 1549 if (chip_id == RTL8852C) 1550 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1551 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1552 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1553 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1554 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1555 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1556 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1557 else 1558 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1559 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1560 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1561 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1562 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1563 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1564 B_AX_DMAC_CRPRT); 1565 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1566 1567 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1568 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1569 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1570 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1571 if (chip_id == RTL8852BT) 1572 val32 |= B_AX_AXIDMA_CLK_EN; 1573 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1574 1575 return 0; 1576 } 1577 1578 static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1579 { 1580 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1581 1582 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 1583 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1584 B_AX_OCP_L1_MASK); 1585 1586 return 0; 1587 } 1588 1589 static int sys_init_ax(struct rtw89_dev *rtwdev) 1590 { 1591 int ret; 1592 1593 ret = dmac_func_en_ax(rtwdev); 1594 if (ret) 1595 return ret; 1596 1597 ret = cmac_func_en_ax(rtwdev, 0, true); 1598 if (ret) 1599 return ret; 1600 1601 ret = chip_func_en_ax(rtwdev); 1602 if (ret) 1603 return ret; 1604 1605 return ret; 1606 } 1607 1608 const struct rtw89_mac_size_set rtw89_mac_size = { 1609 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1610 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0}, 1611 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0}, 1612 /* PCIE 64 */ 1613 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1614 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1615 /* DLFW */ 1616 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1617 .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1618 /* PCIE 64 */ 1619 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1620 /* 8852B PCIE SCC */ 1621 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1622 /* DLFW */ 1623 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1624 /* 8852C DLFW */ 1625 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1626 /* 8852C PCIE SCC */ 1627 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1628 .wde_size23 = {RTW89_WDE_PG_64, 1022, 2,}, 1629 /* PCIE */ 1630 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1631 .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1632 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1633 /* DLFW */ 1634 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1635 /* PCIE 64 */ 1636 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1637 /* DLFW */ 1638 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1639 .ple_size9 = {RTW89_PLE_PG_128, 2288, 16,}, 1640 /* 8852C DLFW */ 1641 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1642 /* 8852C PCIE SCC */ 1643 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1644 /* PCIE 64 */ 1645 .wde_qt0 = {3792, 196, 0, 107,}, 1646 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1647 /* DLFW */ 1648 .wde_qt4 = {0, 0, 0, 0,}, 1649 /* PCIE 64 */ 1650 .wde_qt6 = {448, 48, 0, 16,}, 1651 /* 8852B PCIE SCC */ 1652 .wde_qt7 = {446, 48, 0, 16,}, 1653 /* 8852C DLFW */ 1654 .wde_qt17 = {0, 0, 0, 0,}, 1655 /* 8852C PCIE SCC */ 1656 .wde_qt18 = {3228, 60, 0, 40,}, 1657 .wde_qt23 = {958, 48, 0, 16,}, 1658 .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 1659 .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1660 /* PCIE SCC */ 1661 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1662 /* PCIE SCC */ 1663 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1664 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1665 /* DLFW */ 1666 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1667 /* PCIE 64 */ 1668 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1669 /* DLFW 52C */ 1670 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1671 /* DLFW 52C */ 1672 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1673 /* 8852C PCIE SCC */ 1674 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1675 /* 8852C PCIE SCC */ 1676 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1677 .ple_qt57 = {147, 0, 16, 20, 13, 13, 178, 0, 32, 14, 8, 0,}, 1678 /* PCIE 64 */ 1679 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1680 .ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,}, 1681 /* 8852A PCIE WOW */ 1682 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1683 /* 8852B PCIE WOW */ 1684 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1685 /* 8852BT PCIE WOW */ 1686 .ple_qt_52bt_wow = {147, 0, 32, 20, 1860, 13, 1929, 0, 1879, 14, 24, 0,}, 1687 /* 8851B PCIE WOW */ 1688 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1689 .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1690 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1691 .rsvd0_size0 = {212992, 0,}, 1692 .rsvd1_size0 = {587776, 2048,}, 1693 }; 1694 EXPORT_SYMBOL(rtw89_mac_size); 1695 1696 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1697 enum rtw89_qta_mode mode) 1698 { 1699 struct rtw89_mac_info *mac = &rtwdev->mac; 1700 const struct rtw89_dle_mem *cfg; 1701 1702 cfg = &rtwdev->chip->dle_mem[mode]; 1703 if (!cfg) 1704 return NULL; 1705 1706 if (cfg->mode != mode) { 1707 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1708 return NULL; 1709 } 1710 1711 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1712 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1713 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1714 mac->dle_info.qta_mode = mode; 1715 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1716 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1717 1718 return cfg; 1719 } 1720 1721 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1722 enum rtw89_mac_dle_rsvd_qt_type type, 1723 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1724 { 1725 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1726 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1727 1728 switch (type) { 1729 case DLE_RSVD_QT_MPDU_INFO: 1730 cfg->pktid = dle_info->ple_free_pg; 1731 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1732 break; 1733 case DLE_RSVD_QT_B0_CSI: 1734 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1735 cfg->pg_num = rsvd_qt->b0_csi; 1736 break; 1737 case DLE_RSVD_QT_B1_CSI: 1738 cfg->pktid = dle_info->ple_free_pg + 1739 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1740 cfg->pg_num = rsvd_qt->b1_csi; 1741 break; 1742 case DLE_RSVD_QT_B0_LMR: 1743 cfg->pktid = dle_info->ple_free_pg + 1744 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1745 cfg->pg_num = rsvd_qt->b0_lmr; 1746 break; 1747 case DLE_RSVD_QT_B1_LMR: 1748 cfg->pktid = dle_info->ple_free_pg + 1749 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1750 rsvd_qt->b0_lmr; 1751 cfg->pg_num = rsvd_qt->b1_lmr; 1752 break; 1753 case DLE_RSVD_QT_B0_FTM: 1754 cfg->pktid = dle_info->ple_free_pg + 1755 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1756 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1757 cfg->pg_num = rsvd_qt->b0_ftm; 1758 break; 1759 case DLE_RSVD_QT_B1_FTM: 1760 cfg->pktid = dle_info->ple_free_pg + 1761 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1762 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1763 cfg->pg_num = rsvd_qt->b1_ftm; 1764 break; 1765 default: 1766 return -EINVAL; 1767 } 1768 1769 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1770 1771 return 0; 1772 } 1773 1774 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1775 { 1776 struct rtw89_mac_dle_dfi_qempty qempty; 1777 u32 grpnum, qtmp, val32, msk32; 1778 int i, j, ret; 1779 1780 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1781 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1782 1783 for (i = 0; i < grpnum; i++) { 1784 qempty.grpsel = i; 1785 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1786 if (ret) { 1787 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1788 return false; 1789 } 1790 qtmp = qempty.qempty; 1791 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1792 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 1793 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1794 return false; 1795 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1796 } 1797 } 1798 1799 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1800 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1801 if (ret) { 1802 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1803 return false; 1804 } 1805 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1806 if ((qempty.qempty & msk32) != msk32) 1807 return false; 1808 1809 if (rtwdev->dbcc_en) { 1810 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1811 if ((qempty.qempty & msk32) != msk32) 1812 return false; 1813 } 1814 1815 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1816 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1817 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1818 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1819 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1820 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1821 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1822 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1823 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1824 1825 return (val32 & msk32) == msk32; 1826 } 1827 1828 static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1829 { 1830 const struct rtw89_dle_size *wde = cfg->wde_size; 1831 const struct rtw89_dle_size *ple = cfg->ple_size; 1832 u32 used; 1833 1834 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1835 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1836 1837 if (cfg->rsvd0_size && cfg->rsvd1_size) { 1838 used += cfg->rsvd0_size->size; 1839 used += cfg->rsvd1_size->size; 1840 } 1841 1842 return used; 1843 } 1844 1845 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1846 enum rtw89_qta_mode mode) 1847 { 1848 u32 size = rtwdev->chip->fifo_size; 1849 1850 if (mode == RTW89_QTA_SCC) 1851 size -= rtwdev->chip->dle_scc_rsvd_size; 1852 1853 return size; 1854 } 1855 1856 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 1857 { 1858 if (enable) 1859 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1860 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1861 else 1862 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1863 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1864 } 1865 1866 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 1867 { 1868 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1869 1870 if (enable) { 1871 if (rtwdev->chip->chip_id == RTL8851B) 1872 val |= B_AX_AXIDMA_CLK_EN; 1873 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1874 } else { 1875 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1876 } 1877 } 1878 1879 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1880 { 1881 const struct rtw89_dle_size *size_cfg; 1882 u32 val; 1883 u8 bound = 0; 1884 1885 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1886 size_cfg = cfg->wde_size; 1887 1888 switch (size_cfg->pge_size) { 1889 default: 1890 case RTW89_WDE_PG_64: 1891 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1892 B_AX_WDE_PAGE_SEL_MASK); 1893 break; 1894 case RTW89_WDE_PG_128: 1895 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1896 B_AX_WDE_PAGE_SEL_MASK); 1897 break; 1898 case RTW89_WDE_PG_256: 1899 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1900 return -EINVAL; 1901 } 1902 1903 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1904 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1905 B_AX_WDE_FREE_PAGE_NUM_MASK); 1906 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1907 1908 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1909 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1910 * size_cfg->pge_size / DLE_BOUND_UNIT; 1911 size_cfg = cfg->ple_size; 1912 1913 switch (size_cfg->pge_size) { 1914 default: 1915 case RTW89_PLE_PG_64: 1916 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1917 return -EINVAL; 1918 case RTW89_PLE_PG_128: 1919 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1920 B_AX_PLE_PAGE_SEL_MASK); 1921 break; 1922 case RTW89_PLE_PG_256: 1923 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1924 B_AX_PLE_PAGE_SEL_MASK); 1925 break; 1926 } 1927 1928 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1929 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1930 B_AX_PLE_FREE_PAGE_NUM_MASK); 1931 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1932 1933 return 0; 1934 } 1935 1936 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 1937 { 1938 u32 reg, mask; 1939 u32 ini; 1940 1941 if (wde_or_ple) { 1942 reg = R_AX_WDE_INI_STATUS; 1943 mask = WDE_MGN_INI_RDY; 1944 } else { 1945 reg = R_AX_PLE_INI_STATUS; 1946 mask = PLE_MGN_INI_RDY; 1947 } 1948 1949 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 1950 2000, false, rtwdev, reg); 1951 } 1952 1953 #define INVALID_QT_WCPU U16_MAX 1954 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1955 do { \ 1956 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1957 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1958 rtw89_write32(rtwdev, \ 1959 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1960 val); \ 1961 } while (0) 1962 #define SET_QUOTA(_x, _module, _idx) \ 1963 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1964 1965 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 1966 const struct rtw89_wde_quota *min_cfg, 1967 const struct rtw89_wde_quota *max_cfg, 1968 u16 ext_wde_min_qt_wcpu) 1969 { 1970 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1971 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1972 u32 val; 1973 1974 SET_QUOTA(hif, WDE, 0); 1975 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1976 SET_QUOTA(pkt_in, WDE, 3); 1977 SET_QUOTA(cpu_io, WDE, 4); 1978 } 1979 1980 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 1981 const struct rtw89_ple_quota *min_cfg, 1982 const struct rtw89_ple_quota *max_cfg) 1983 { 1984 u32 val; 1985 1986 SET_QUOTA(cma0_tx, PLE, 0); 1987 SET_QUOTA(cma1_tx, PLE, 1); 1988 SET_QUOTA(c2h, PLE, 2); 1989 SET_QUOTA(h2c, PLE, 3); 1990 SET_QUOTA(wcpu, PLE, 4); 1991 SET_QUOTA(mpdu_proc, PLE, 5); 1992 SET_QUOTA(cma0_dma, PLE, 6); 1993 SET_QUOTA(cma1_dma, PLE, 7); 1994 SET_QUOTA(bb_rpt, PLE, 8); 1995 SET_QUOTA(wd_rel, PLE, 9); 1996 SET_QUOTA(cpu_io, PLE, 10); 1997 if (rtwdev->chip->chip_id == RTL8852C) 1998 SET_QUOTA(tx_rpt, PLE, 11); 1999 } 2000 2001 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 2002 { 2003 const struct rtw89_ple_quota *min_cfg, *max_cfg; 2004 const struct rtw89_dle_mem *cfg; 2005 u32 val; 2006 2007 if (rtwdev->chip->chip_id == RTL8852C) 2008 return 0; 2009 2010 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2011 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2012 return -EINVAL; 2013 } 2014 2015 if (wow) 2016 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2017 else 2018 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2019 if (!cfg) { 2020 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2021 return -EINVAL; 2022 } 2023 2024 min_cfg = cfg->ple_min_qt; 2025 max_cfg = cfg->ple_max_qt; 2026 SET_QUOTA(cma0_dma, PLE, 6); 2027 SET_QUOTA(cma1_dma, PLE, 7); 2028 2029 return 0; 2030 } 2031 #undef SET_QUOTA 2032 2033 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2034 { 2035 const struct rtw89_chip_info *chip = rtwdev->chip; 2036 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2037 2038 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2039 return; 2040 2041 /* 8852C enable B_AX_UC_MGNT_DEC by default */ 2042 if (chip->chip_id == RTL8852C) 2043 msk32 = B_AX_BMC_MGNT_DEC; 2044 2045 if (enable) 2046 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2047 else 2048 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2049 } 2050 2051 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2052 const struct rtw89_dle_mem *cfg, 2053 u16 ext_wde_min_qt_wcpu) 2054 { 2055 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2056 2057 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2058 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2059 } 2060 2061 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2062 enum rtw89_qta_mode ext_mode) 2063 { 2064 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2065 const struct rtw89_dle_mem *cfg, *ext_cfg; 2066 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2067 int ret; 2068 2069 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2070 if (ret) 2071 return ret; 2072 2073 cfg = get_dle_mem_cfg(rtwdev, mode); 2074 if (!cfg) { 2075 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2076 ret = -EINVAL; 2077 goto error; 2078 } 2079 2080 if (mode == RTW89_QTA_DLFW) { 2081 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2082 if (!ext_cfg) { 2083 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2084 ext_mode); 2085 ret = -EINVAL; 2086 goto error; 2087 } 2088 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2089 } 2090 2091 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2092 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2093 ret = -EINVAL; 2094 goto error; 2095 } 2096 2097 mac->dle_func_en(rtwdev, false); 2098 mac->dle_clk_en(rtwdev, true); 2099 2100 ret = mac->dle_mix_cfg(rtwdev, cfg); 2101 if (ret) { 2102 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2103 goto error; 2104 } 2105 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2106 2107 mac->dle_func_en(rtwdev, true); 2108 2109 ret = mac->chk_dle_rdy(rtwdev, true); 2110 if (ret) { 2111 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2112 return ret; 2113 } 2114 2115 ret = mac->chk_dle_rdy(rtwdev, false); 2116 if (ret) { 2117 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2118 return ret; 2119 } 2120 2121 return 0; 2122 error: 2123 mac->dle_func_en(rtwdev, false); 2124 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2125 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2126 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2127 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2128 2129 return ret; 2130 } 2131 2132 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2133 enum rtw89_qta_mode mode) 2134 { 2135 u32 reg, max_preld_size, min_rsvd_size; 2136 2137 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2138 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2139 reg = mac_idx == RTW89_MAC_0 ? 2140 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2141 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2142 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2143 2144 min_rsvd_size = PRELD_AMSDU_SIZE; 2145 reg = mac_idx == RTW89_MAC_0 ? 2146 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2147 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2148 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2149 2150 return 0; 2151 } 2152 2153 static bool is_qta_poh(struct rtw89_dev *rtwdev) 2154 { 2155 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2156 } 2157 2158 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2159 enum rtw89_qta_mode mode) 2160 { 2161 const struct rtw89_chip_info *chip = rtwdev->chip; 2162 2163 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) || 2164 !is_qta_poh(rtwdev)) 2165 return 0; 2166 2167 return preload_init_set(rtwdev, mac_idx, mode); 2168 } 2169 2170 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2171 { 2172 u32 msk32; 2173 u32 val32; 2174 2175 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2176 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2177 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2178 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2179 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2180 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2181 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2182 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2183 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2184 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2185 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2186 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2187 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2188 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2189 2190 if ((val32 & msk32) == msk32) 2191 return true; 2192 2193 return false; 2194 } 2195 2196 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2197 { 2198 const struct rtw89_chip_info *chip = rtwdev->chip; 2199 2200 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2201 return; 2202 2203 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2204 SS2F_PATH_WLCPU); 2205 } 2206 2207 static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2208 { 2209 u32 p_val; 2210 u8 val; 2211 int ret; 2212 2213 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2214 if (ret) 2215 return ret; 2216 2217 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2218 val |= B_AX_SS_EN; 2219 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2220 2221 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2222 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2223 if (ret) { 2224 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2225 return ret; 2226 } 2227 2228 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2229 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2230 2231 _patch_ss2f_path(rtwdev); 2232 2233 return 0; 2234 } 2235 2236 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2237 { 2238 int ret; 2239 2240 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2241 if (ret) 2242 return ret; 2243 2244 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2245 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2246 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2247 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2248 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2249 2250 return 0; 2251 } 2252 2253 static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2254 { 2255 const struct rtw89_chip_info *chip = rtwdev->chip; 2256 u32 val = 0; 2257 int ret; 2258 2259 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2260 if (ret) 2261 return ret; 2262 2263 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2264 /* init clock */ 2265 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2266 /* init TX encryption */ 2267 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2268 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2269 if (chip->chip_id == RTL8852C) 2270 val |= B_AX_UC_MGNT_DEC; 2271 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2272 chip->chip_id == RTL8851B) 2273 val &= ~B_AX_TX_PARTIAL_MODE; 2274 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2275 2276 /* init MIC ICV append */ 2277 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2278 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2279 2280 /* option init */ 2281 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2282 2283 if (chip->chip_id == RTL8852C) 2284 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2285 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2286 2287 return 0; 2288 } 2289 2290 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2291 { 2292 int ret; 2293 2294 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2295 if (ret) { 2296 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2297 return ret; 2298 } 2299 2300 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2301 if (ret) { 2302 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2303 return ret; 2304 } 2305 2306 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2307 if (ret) { 2308 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2309 return ret; 2310 } 2311 2312 ret = sta_sch_init_ax(rtwdev); 2313 if (ret) { 2314 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2315 return ret; 2316 } 2317 2318 ret = mpdu_proc_init_ax(rtwdev); 2319 if (ret) { 2320 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2321 return ret; 2322 } 2323 2324 ret = sec_eng_init_ax(rtwdev); 2325 if (ret) { 2326 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2327 return ret; 2328 } 2329 2330 return ret; 2331 } 2332 2333 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2334 { 2335 u32 val, reg; 2336 u16 p_val; 2337 int ret; 2338 2339 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2340 if (ret) 2341 return ret; 2342 2343 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2344 2345 val = rtw89_read32(rtwdev, reg); 2346 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2347 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2348 rtw89_write32(rtwdev, reg, val); 2349 2350 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2351 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2352 if (ret) { 2353 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2354 return ret; 2355 } 2356 2357 return 0; 2358 } 2359 2360 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2361 { 2362 u32 ret; 2363 u32 reg; 2364 u32 val; 2365 2366 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2367 if (ret) 2368 return ret; 2369 2370 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2371 if (rtwdev->chip->chip_id == RTL8852C) 2372 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2373 SIFS_MACTXEN_T1_V1); 2374 else 2375 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2376 SIFS_MACTXEN_T1); 2377 2378 if (rtw89_is_rtl885xb(rtwdev)) { 2379 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2380 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2381 } 2382 2383 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2384 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2385 2386 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2387 if (rtwdev->chip->chip_id == RTL8852C) { 2388 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2389 B_AX_TX_PARTIAL_MODE); 2390 if (!val) 2391 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2392 SCH_PREBKF_24US); 2393 } else { 2394 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2395 SCH_PREBKF_24US); 2396 } 2397 2398 return 0; 2399 } 2400 2401 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2402 enum rtw89_machdr_frame_type type, 2403 enum rtw89_mac_fwd_target fwd_target, 2404 u8 mac_idx) 2405 { 2406 u32 reg; 2407 u32 val; 2408 2409 switch (fwd_target) { 2410 case RTW89_FWD_DONT_CARE: 2411 val = RX_FLTR_FRAME_DROP; 2412 break; 2413 case RTW89_FWD_TO_HOST: 2414 val = RX_FLTR_FRAME_TO_HOST; 2415 break; 2416 case RTW89_FWD_TO_WLAN_CPU: 2417 val = RX_FLTR_FRAME_TO_WLCPU; 2418 break; 2419 default: 2420 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2421 return -EINVAL; 2422 } 2423 2424 switch (type) { 2425 case RTW89_MGNT: 2426 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2427 break; 2428 case RTW89_CTRL: 2429 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2430 break; 2431 case RTW89_DATA: 2432 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2433 break; 2434 default: 2435 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2436 return -EINVAL; 2437 } 2438 rtw89_write32(rtwdev, reg, val); 2439 2440 return 0; 2441 } 2442 2443 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2444 { 2445 int ret, i; 2446 u32 mac_ftlr, plcp_ftlr; 2447 2448 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2449 if (ret) 2450 return ret; 2451 2452 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2453 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2454 mac_idx); 2455 if (ret) 2456 return ret; 2457 } 2458 mac_ftlr = rtwdev->hal.rx_fltr; 2459 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2460 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2461 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2462 B_AX_HE_SIGB_CRC_CHK; 2463 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2464 mac_ftlr); 2465 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2466 plcp_ftlr); 2467 2468 return 0; 2469 } 2470 2471 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2472 { 2473 u32 reg, val32; 2474 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2475 2476 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2477 B_AX_RSP_CHK_BASIC_NAV; 2478 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2479 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2480 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2481 2482 switch (rtwdev->chip->chip_id) { 2483 case RTL8852A: 2484 case RTL8852B: 2485 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2486 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2487 rtw89_write32(rtwdev, reg, val32); 2488 2489 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2490 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2491 rtw89_write32(rtwdev, reg, val32); 2492 break; 2493 default: 2494 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2495 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2496 rtw89_write32(rtwdev, reg, val32); 2497 2498 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2499 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2500 rtw89_write32(rtwdev, reg, val32); 2501 break; 2502 } 2503 } 2504 2505 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2506 { 2507 u32 val, reg; 2508 int ret; 2509 2510 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2511 if (ret) 2512 return ret; 2513 2514 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2515 val = rtw89_read32(rtwdev, reg); 2516 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2517 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2518 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2519 B_AX_CTN_CHK_INTRA_NAV | 2520 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2521 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2522 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2523 B_AX_CTN_CHK_CCA_P20); 2524 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2525 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2526 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2527 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2528 B_AX_SIFS_CHK_EDCCA); 2529 2530 rtw89_write32(rtwdev, reg, val); 2531 2532 _patch_dis_resp_chk(rtwdev, mac_idx); 2533 2534 return 0; 2535 } 2536 2537 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2538 { 2539 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2540 B_AX_WMAC_TF_UP_NAV_EN | 2541 B_AX_WMAC_NAV_UPPER_EN); 2542 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2543 2544 return 0; 2545 } 2546 2547 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2548 { 2549 u32 reg; 2550 int ret; 2551 2552 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2553 if (ret) 2554 return ret; 2555 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2556 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2557 2558 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2559 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2560 2561 return 0; 2562 } 2563 2564 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2565 { 2566 u32 reg; 2567 int ret; 2568 2569 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2570 if (ret) 2571 return ret; 2572 2573 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2574 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2575 2576 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2577 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2578 2579 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2580 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2581 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2582 2583 return 0; 2584 } 2585 2586 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2587 { 2588 const struct rtw89_chip_info *chip = rtwdev->chip; 2589 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2590 u32 reg, val, sifs; 2591 int ret; 2592 2593 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2594 if (ret) 2595 return ret; 2596 2597 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2598 val = rtw89_read32(rtwdev, reg); 2599 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2600 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2601 2602 switch (rtwdev->chip->chip_id) { 2603 case RTL8852A: 2604 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2605 break; 2606 case RTL8851B: 2607 case RTL8852B: 2608 case RTL8852BT: 2609 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2610 break; 2611 default: 2612 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2613 break; 2614 } 2615 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2616 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2617 rtw89_write32(rtwdev, reg, val); 2618 2619 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2620 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2621 2622 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2623 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2624 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2625 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2626 2627 return 0; 2628 } 2629 2630 static void rst_bacam(struct rtw89_dev *rtwdev) 2631 { 2632 u32 val32; 2633 int ret; 2634 2635 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2636 S_AX_BACAM_RST_ALL); 2637 2638 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2639 1, 1000, false, 2640 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2641 if (ret) 2642 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2643 } 2644 2645 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2646 { 2647 #define TRXCFG_RMAC_CCA_TO 32 2648 #define TRXCFG_RMAC_DATA_TO 15 2649 #define RX_MAX_LEN_UNIT 512 2650 #define PLD_RLS_MAX_PG 127 2651 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2652 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2653 int ret; 2654 u32 reg, rx_max_len, rx_qta; 2655 u16 val; 2656 2657 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2658 if (ret) 2659 return ret; 2660 2661 if (mac_idx == RTW89_MAC_0) 2662 rst_bacam(rtwdev); 2663 2664 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2665 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2666 2667 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2668 val = rtw89_read16(rtwdev, reg); 2669 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2670 B_AX_RX_DLK_DATA_TIME_MASK); 2671 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2672 B_AX_RX_DLK_CCA_TIME_MASK); 2673 if (chip_id == RTL8852BT) 2674 val |= B_AX_RX_DLK_RST_EN; 2675 rtw89_write16(rtwdev, reg, val); 2676 2677 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2678 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2679 2680 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2681 if (mac_idx == RTW89_MAC_0) 2682 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2683 else 2684 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2685 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2686 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2687 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2688 rx_max_len /= RX_MAX_LEN_UNIT; 2689 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2690 2691 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) { 2692 rtw89_write16_mask(rtwdev, 2693 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2694 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2695 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2696 BIT(12)); 2697 } 2698 2699 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2700 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2701 2702 return ret; 2703 } 2704 2705 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2706 { 2707 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2708 u32 val, reg; 2709 int ret; 2710 2711 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2712 if (ret) 2713 return ret; 2714 2715 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2716 val = rtw89_read32(rtwdev, reg); 2717 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2718 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2719 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2720 rtw89_write32(rtwdev, reg, val); 2721 2722 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2723 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2724 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2725 } 2726 2727 return 0; 2728 } 2729 2730 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2731 { 2732 const struct rtw89_dle_mem *cfg; 2733 2734 cfg = get_dle_mem_cfg(rtwdev, mode); 2735 if (!cfg) { 2736 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2737 return false; 2738 } 2739 2740 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2741 } 2742 2743 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2744 { 2745 u32 val, reg; 2746 int ret; 2747 2748 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2749 if (ret) 2750 return ret; 2751 2752 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2753 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2754 val = rtw89_read32(rtwdev, reg); 2755 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2756 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2757 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2758 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2759 val |= B_AX_HW_CTS2SELF_EN; 2760 rtw89_write32(rtwdev, reg, val); 2761 2762 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2763 val = rtw89_read32(rtwdev, reg); 2764 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2765 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2766 rtw89_write32(rtwdev, reg, val); 2767 } 2768 2769 if (mac_idx == RTW89_MAC_0) { 2770 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2771 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2772 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2773 B_AX_PTCL_TRIGGER_SS_EN_0 | 2774 B_AX_PTCL_TRIGGER_SS_EN_1 | 2775 B_AX_PTCL_TRIGGER_SS_EN_UL); 2776 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2777 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2778 } else if (mac_idx == RTW89_MAC_1) { 2779 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2780 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2781 } 2782 2783 return 0; 2784 } 2785 2786 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2787 { 2788 u32 reg; 2789 int ret; 2790 2791 if (!rtw89_is_rtl885xb(rtwdev)) 2792 return 0; 2793 2794 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2795 if (ret) 2796 return ret; 2797 2798 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2799 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2800 2801 return 0; 2802 } 2803 2804 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2805 { 2806 int ret; 2807 2808 ret = scheduler_init_ax(rtwdev, mac_idx); 2809 if (ret) { 2810 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2811 return ret; 2812 } 2813 2814 ret = addr_cam_init_ax(rtwdev, mac_idx); 2815 if (ret) { 2816 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2817 ret); 2818 return ret; 2819 } 2820 2821 ret = rx_fltr_init_ax(rtwdev, mac_idx); 2822 if (ret) { 2823 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2824 ret); 2825 return ret; 2826 } 2827 2828 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 2829 if (ret) { 2830 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2831 ret); 2832 return ret; 2833 } 2834 2835 ret = nav_ctrl_init_ax(rtwdev); 2836 if (ret) { 2837 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2838 ret); 2839 return ret; 2840 } 2841 2842 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 2843 if (ret) { 2844 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2845 mac_idx, ret); 2846 return ret; 2847 } 2848 2849 ret = tmac_init_ax(rtwdev, mac_idx); 2850 if (ret) { 2851 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2852 return ret; 2853 } 2854 2855 ret = trxptcl_init_ax(rtwdev, mac_idx); 2856 if (ret) { 2857 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2858 return ret; 2859 } 2860 2861 ret = rmac_init_ax(rtwdev, mac_idx); 2862 if (ret) { 2863 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2864 return ret; 2865 } 2866 2867 ret = cmac_com_init_ax(rtwdev, mac_idx); 2868 if (ret) { 2869 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2870 return ret; 2871 } 2872 2873 ret = ptcl_init_ax(rtwdev, mac_idx); 2874 if (ret) { 2875 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2876 return ret; 2877 } 2878 2879 ret = cmac_dma_init_ax(rtwdev, mac_idx); 2880 if (ret) { 2881 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2882 return ret; 2883 } 2884 2885 return ret; 2886 } 2887 2888 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2889 struct rtw89_mac_c2h_info *c2h_info) 2890 { 2891 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2892 struct rtw89_mac_h2c_info h2c_info = {0}; 2893 u32 ret; 2894 2895 mac->cnv_efuse_state(rtwdev, false); 2896 2897 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2898 h2c_info.content_len = 0; 2899 2900 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2901 if (ret) 2902 goto out; 2903 2904 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2905 ret = -EINVAL; 2906 2907 out: 2908 mac->cnv_efuse_state(rtwdev, true); 2909 2910 return ret; 2911 } 2912 2913 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2914 { 2915 struct rtw89_efuse *efuse = &rtwdev->efuse; 2916 struct rtw89_hal *hal = &rtwdev->hal; 2917 const struct rtw89_chip_info *chip = rtwdev->chip; 2918 struct rtw89_mac_c2h_info c2h_info = {0}; 2919 const struct rtw89_c2hreg_phycap *phycap; 2920 u8 tx_nss; 2921 u8 rx_nss; 2922 u8 tx_ant; 2923 u8 rx_ant; 2924 u32 ret; 2925 2926 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2927 if (ret) 2928 return ret; 2929 2930 phycap = &c2h_info.u.phycap; 2931 2932 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 2933 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 2934 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 2935 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2936 2937 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2938 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2939 2940 if (tx_ant == 1) 2941 hal->antenna_tx = RF_B; 2942 if (rx_ant == 1) 2943 hal->antenna_rx = RF_B; 2944 2945 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2946 hal->antenna_tx = RF_B; 2947 hal->tx_path_diversity = true; 2948 } 2949 2950 if (chip->rf_path_num == 1) { 2951 hal->antenna_tx = RF_A; 2952 hal->antenna_rx = RF_A; 2953 if ((efuse->rfe_type % 3) == 2) 2954 hal->ant_diversity = true; 2955 } 2956 2957 rtw89_debug(rtwdev, RTW89_DBG_FW, 2958 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2959 hal->tx_nss, tx_nss, chip->tx_nss, 2960 hal->rx_nss, rx_nss, chip->rx_nss); 2961 rtw89_debug(rtwdev, RTW89_DBG_FW, 2962 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2963 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2964 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2965 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2966 2967 return 0; 2968 } 2969 2970 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2971 u16 tx_en_u16, u16 mask_u16) 2972 { 2973 u32 ret; 2974 struct rtw89_mac_c2h_info c2h_info = {0}; 2975 struct rtw89_mac_h2c_info h2c_info = {0}; 2976 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 2977 2978 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2979 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 2980 2981 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 2982 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 2983 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 2984 2985 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2986 if (ret) 2987 return ret; 2988 2989 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2990 return -EINVAL; 2991 2992 return 0; 2993 } 2994 2995 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2996 u16 tx_en, u16 tx_en_mask) 2997 { 2998 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 2999 u16 val; 3000 int ret; 3001 3002 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3003 if (ret) 3004 return ret; 3005 3006 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3007 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 3008 tx_en, tx_en_mask); 3009 3010 val = rtw89_read16(rtwdev, reg); 3011 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3012 rtw89_write16(rtwdev, reg, val); 3013 3014 return 0; 3015 } 3016 3017 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3018 u32 tx_en, u32 tx_en_mask) 3019 { 3020 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3021 u32 val; 3022 int ret; 3023 3024 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3025 if (ret) 3026 return ret; 3027 3028 val = rtw89_read32(rtwdev, reg); 3029 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3030 rtw89_write32(rtwdev, reg, val); 3031 3032 return 0; 3033 } 3034 3035 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3036 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3037 { 3038 int ret; 3039 3040 *tx_en = rtw89_read16(rtwdev, 3041 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3042 3043 switch (sel) { 3044 case RTW89_SCH_TX_SEL_ALL: 3045 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3046 B_AX_CTN_TXEN_ALL_MASK); 3047 if (ret) 3048 return ret; 3049 break; 3050 case RTW89_SCH_TX_SEL_HIQ: 3051 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3052 0, B_AX_CTN_TXEN_HGQ); 3053 if (ret) 3054 return ret; 3055 break; 3056 case RTW89_SCH_TX_SEL_MG0: 3057 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3058 0, B_AX_CTN_TXEN_MGQ); 3059 if (ret) 3060 return ret; 3061 break; 3062 case RTW89_SCH_TX_SEL_MACID: 3063 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3064 B_AX_CTN_TXEN_ALL_MASK); 3065 if (ret) 3066 return ret; 3067 break; 3068 default: 3069 return 0; 3070 } 3071 3072 return 0; 3073 } 3074 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3075 3076 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3077 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3078 { 3079 int ret; 3080 3081 *tx_en = rtw89_read32(rtwdev, 3082 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3083 3084 switch (sel) { 3085 case RTW89_SCH_TX_SEL_ALL: 3086 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3087 B_AX_CTN_TXEN_ALL_MASK_V1); 3088 if (ret) 3089 return ret; 3090 break; 3091 case RTW89_SCH_TX_SEL_HIQ: 3092 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3093 0, B_AX_CTN_TXEN_HGQ); 3094 if (ret) 3095 return ret; 3096 break; 3097 case RTW89_SCH_TX_SEL_MG0: 3098 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3099 0, B_AX_CTN_TXEN_MGQ); 3100 if (ret) 3101 return ret; 3102 break; 3103 case RTW89_SCH_TX_SEL_MACID: 3104 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3105 B_AX_CTN_TXEN_ALL_MASK_V1); 3106 if (ret) 3107 return ret; 3108 break; 3109 default: 3110 return 0; 3111 } 3112 3113 return 0; 3114 } 3115 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3116 3117 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3118 { 3119 int ret; 3120 3121 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3122 if (ret) 3123 return ret; 3124 3125 return 0; 3126 } 3127 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3128 3129 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3130 { 3131 int ret; 3132 3133 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3134 B_AX_CTN_TXEN_ALL_MASK_V1); 3135 if (ret) 3136 return ret; 3137 3138 return 0; 3139 } 3140 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3141 3142 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3143 { 3144 u32 val, reg; 3145 int ret; 3146 3147 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3148 val = buf_len; 3149 val |= B_AX_WD_BUF_REQ_EXEC; 3150 rtw89_write32(rtwdev, reg, val); 3151 3152 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3153 3154 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3155 1, 2000, false, rtwdev, reg); 3156 if (ret) 3157 return ret; 3158 3159 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3160 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3161 return -ENOENT; 3162 3163 return 0; 3164 } 3165 3166 static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3167 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3168 { 3169 u32 val, cmd_type, reg; 3170 int ret; 3171 3172 cmd_type = ctrl_para->cmd_type; 3173 3174 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3175 val = 0; 3176 val = u32_replace_bits(val, ctrl_para->start_pktid, 3177 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3178 val = u32_replace_bits(val, ctrl_para->end_pktid, 3179 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3180 rtw89_write32(rtwdev, reg, val); 3181 3182 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3183 val = 0; 3184 val = u32_replace_bits(val, ctrl_para->src_pid, 3185 B_AX_CPUQ_OP_SRC_PID_MASK); 3186 val = u32_replace_bits(val, ctrl_para->src_qid, 3187 B_AX_CPUQ_OP_SRC_QID_MASK); 3188 val = u32_replace_bits(val, ctrl_para->dst_pid, 3189 B_AX_CPUQ_OP_DST_PID_MASK); 3190 val = u32_replace_bits(val, ctrl_para->dst_qid, 3191 B_AX_CPUQ_OP_DST_QID_MASK); 3192 rtw89_write32(rtwdev, reg, val); 3193 3194 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3195 val = 0; 3196 val = u32_replace_bits(val, cmd_type, 3197 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3198 val = u32_replace_bits(val, ctrl_para->macid, 3199 B_AX_CPUQ_OP_MACID_MASK); 3200 val = u32_replace_bits(val, ctrl_para->pkt_num, 3201 B_AX_CPUQ_OP_PKTNUM_MASK); 3202 val |= B_AX_WD_CPUQ_OP_EXEC; 3203 rtw89_write32(rtwdev, reg, val); 3204 3205 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3206 3207 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3208 1, 2000, false, rtwdev, reg); 3209 if (ret) 3210 return ret; 3211 3212 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3213 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3214 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3215 3216 return 0; 3217 } 3218 3219 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3220 bool band1_en) 3221 { 3222 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3223 const struct rtw89_dle_mem *cfg; 3224 3225 cfg = get_dle_mem_cfg(rtwdev, mode); 3226 if (!cfg) { 3227 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3228 return -EINVAL; 3229 } 3230 3231 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3232 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3233 return -EINVAL; 3234 } 3235 3236 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3237 3238 return mac->dle_quota_change(rtwdev, band1_en); 3239 } 3240 3241 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3242 { 3243 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3244 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3245 u16 pkt_id; 3246 int ret; 3247 3248 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3249 if (ret) { 3250 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3251 return ret; 3252 } 3253 3254 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3255 ctrl_para.start_pktid = pkt_id; 3256 ctrl_para.end_pktid = pkt_id; 3257 ctrl_para.pkt_num = 0; 3258 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3259 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3260 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3261 if (ret) { 3262 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3263 return -EFAULT; 3264 } 3265 3266 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3267 if (ret) { 3268 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3269 return ret; 3270 } 3271 3272 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3273 ctrl_para.start_pktid = pkt_id; 3274 ctrl_para.end_pktid = pkt_id; 3275 ctrl_para.pkt_num = 0; 3276 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3277 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3278 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3279 if (ret) { 3280 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3281 return -EFAULT; 3282 } 3283 3284 return 0; 3285 } 3286 3287 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3288 { 3289 int ret; 3290 u32 reg; 3291 u8 val; 3292 3293 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3294 if (ret) 3295 return ret; 3296 3297 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3298 3299 ret = read_poll_timeout(rtw89_read8, val, 3300 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3301 SW_CVR_DUR_US, 3302 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3303 false, rtwdev, reg); 3304 if (ret) 3305 return ret; 3306 3307 return 0; 3308 } 3309 3310 static int band1_enable_ax(struct rtw89_dev *rtwdev) 3311 { 3312 int ret, i; 3313 u32 sleep_bak[4] = {0}; 3314 u32 pause_bak[4] = {0}; 3315 u32 tx_en; 3316 3317 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3318 if (ret) { 3319 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3320 return ret; 3321 } 3322 3323 for (i = 0; i < 4; i++) { 3324 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3325 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3326 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3327 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3328 } 3329 3330 ret = band_idle_ck_b(rtwdev, 0); 3331 if (ret) { 3332 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3333 return ret; 3334 } 3335 3336 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3337 if (ret) { 3338 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3339 return ret; 3340 } 3341 3342 for (i = 0; i < 4; i++) { 3343 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3344 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3345 } 3346 3347 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3348 if (ret) { 3349 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3350 return ret; 3351 } 3352 3353 ret = cmac_func_en_ax(rtwdev, 1, true); 3354 if (ret) { 3355 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3356 return ret; 3357 } 3358 3359 ret = cmac_init_ax(rtwdev, 1); 3360 if (ret) { 3361 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3362 return ret; 3363 } 3364 3365 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3366 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3367 3368 return 0; 3369 } 3370 3371 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3372 { 3373 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3374 3375 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3376 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3377 } 3378 3379 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3380 { 3381 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3382 3383 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3384 } 3385 3386 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3387 { 3388 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3389 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3390 3391 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3392 B_AX_TX_GET_ERRPKTID_INT_EN | 3393 B_AX_TX_NXT_ERRPKTID_INT_EN | 3394 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3395 B_AX_TX_OFFSET_ERR_INT_EN | 3396 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3397 if (chip_id == RTL8852C) 3398 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3399 B_AX_TX_ETH_TYPE_ERR_EN | 3400 B_AX_TX_LLC_PRE_ERR_EN | 3401 B_AX_TX_NW_TYPE_ERR_EN | 3402 B_AX_TX_KSRCH_ERR_EN); 3403 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3404 imr->mpdu_tx_imr_set); 3405 3406 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3407 B_AX_GETPKTID_ERR_INT_EN | 3408 B_AX_MHDRLEN_ERR_INT_EN | 3409 B_AX_RPT_ERR_INT_EN); 3410 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3411 imr->mpdu_rx_imr_set); 3412 } 3413 3414 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3415 { 3416 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3417 3418 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3419 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3420 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3421 B_AX_PLE_B_PKTID_ERR_INT_EN); 3422 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3423 imr->sta_sch_imr_set); 3424 } 3425 3426 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3427 { 3428 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3429 3430 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3431 imr->txpktctl_imr_b0_clr); 3432 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3433 imr->txpktctl_imr_b0_set); 3434 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3435 imr->txpktctl_imr_b1_clr); 3436 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3437 imr->txpktctl_imr_b1_set); 3438 } 3439 3440 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3441 { 3442 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3443 3444 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3445 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3446 } 3447 3448 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3449 { 3450 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3451 3452 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3453 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3454 } 3455 3456 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3457 { 3458 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3459 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3460 } 3461 3462 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3463 { 3464 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3465 3466 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3467 imr->host_disp_imr_clr); 3468 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3469 imr->host_disp_imr_set); 3470 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3471 imr->cpu_disp_imr_clr); 3472 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3473 imr->cpu_disp_imr_set); 3474 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3475 imr->other_disp_imr_clr); 3476 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3477 imr->other_disp_imr_set); 3478 } 3479 3480 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3481 { 3482 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3483 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3484 } 3485 3486 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3487 { 3488 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3489 3490 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3491 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3492 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3493 B_AX_BBRPT_CHINFO_IMR_CLR); 3494 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3495 imr->bbrpt_err_imr_set); 3496 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3497 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3498 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3499 } 3500 3501 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3502 { 3503 u32 reg; 3504 3505 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3506 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3507 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3508 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3509 } 3510 3511 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3512 { 3513 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3514 u32 reg; 3515 3516 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3517 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3518 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3519 } 3520 3521 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3522 { 3523 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3524 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3525 u32 reg; 3526 3527 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3528 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3529 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3530 3531 if (chip_id == RTL8852C) { 3532 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3533 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3534 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3535 } 3536 } 3537 3538 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3539 { 3540 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3541 u32 reg; 3542 3543 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3544 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3545 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3546 } 3547 3548 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3549 { 3550 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3551 u32 reg; 3552 3553 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3554 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3555 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3556 } 3557 3558 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3559 { 3560 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3561 u32 reg; 3562 3563 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3564 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3565 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3566 } 3567 3568 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3569 enum rtw89_mac_hwmod_sel sel) 3570 { 3571 int ret; 3572 3573 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3574 if (ret) { 3575 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3576 sel, mac_idx); 3577 return ret; 3578 } 3579 3580 if (sel == RTW89_DMAC_SEL) { 3581 rtw89_wdrls_imr_enable(rtwdev); 3582 rtw89_wsec_imr_enable(rtwdev); 3583 rtw89_mpdu_trx_imr_enable(rtwdev); 3584 rtw89_sta_sch_imr_enable(rtwdev); 3585 rtw89_txpktctl_imr_enable(rtwdev); 3586 rtw89_wde_imr_enable(rtwdev); 3587 rtw89_ple_imr_enable(rtwdev); 3588 rtw89_pktin_imr_enable(rtwdev); 3589 rtw89_dispatcher_imr_enable(rtwdev); 3590 rtw89_cpuio_imr_enable(rtwdev); 3591 rtw89_bbrpt_imr_enable(rtwdev); 3592 } else if (sel == RTW89_CMAC_SEL) { 3593 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3594 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3595 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3596 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3597 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3598 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3599 } else { 3600 return -EINVAL; 3601 } 3602 3603 return 0; 3604 } 3605 3606 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3607 { 3608 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3609 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3610 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3611 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3612 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta) 3613 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3614 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3615 } 3616 3617 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3618 { 3619 int ret = 0; 3620 3621 if (enable) { 3622 ret = band1_enable_ax(rtwdev); 3623 if (ret) { 3624 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3625 return ret; 3626 } 3627 3628 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3629 if (ret) { 3630 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3631 return ret; 3632 } 3633 } else { 3634 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3635 return -EINVAL; 3636 } 3637 3638 return 0; 3639 } 3640 3641 static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3642 { 3643 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3644 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3645 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3646 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3647 B_AX_RLSRPT0_FLTR_MAP_MASK); 3648 } else { 3649 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3650 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3651 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3652 B_AX_RLSRPT0_FLTR_MAP_MASK); 3653 } 3654 3655 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3656 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3657 3658 return 0; 3659 } 3660 3661 static int trx_init_ax(struct rtw89_dev *rtwdev) 3662 { 3663 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3664 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3665 int ret; 3666 3667 ret = dmac_init_ax(rtwdev, 0); 3668 if (ret) { 3669 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3670 return ret; 3671 } 3672 3673 ret = cmac_init_ax(rtwdev, 0); 3674 if (ret) { 3675 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3676 return ret; 3677 } 3678 3679 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3680 ret = dbcc_enable_ax(rtwdev, true); 3681 if (ret) { 3682 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3683 return ret; 3684 } 3685 } 3686 3687 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3688 if (ret) { 3689 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3690 return ret; 3691 } 3692 3693 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3694 if (ret) { 3695 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3696 return ret; 3697 } 3698 3699 err_imr_ctrl_ax(rtwdev, true); 3700 3701 ret = set_host_rpr_ax(rtwdev); 3702 if (ret) { 3703 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3704 return ret; 3705 } 3706 3707 if (chip_id == RTL8852C) 3708 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG, 3709 B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN); 3710 3711 return 0; 3712 } 3713 3714 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 3715 { 3716 #define BACAM_1024BMP_OCC_ENTRY 4 3717 #define BACAM_MAX_RU_SUPPORT_B0_STA 1 3718 #define BACAM_MAX_RU_SUPPORT_B1_STA 1 3719 const struct rtw89_chip_info *chip = rtwdev->chip; 3720 u8 users, offset; 3721 3722 if (chip->bacam_ver != RTW89_BACAM_V1) 3723 return 0; 3724 3725 offset = 0; 3726 users = BACAM_MAX_RU_SUPPORT_B0_STA; 3727 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 3728 3729 offset += users * BACAM_1024BMP_OCC_ENTRY; 3730 users = BACAM_MAX_RU_SUPPORT_B1_STA; 3731 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 3732 3733 return 0; 3734 } 3735 3736 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3737 { 3738 u32 val32; 3739 3740 if (rtw89_is_rtl885xb(rtwdev)) { 3741 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3742 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3743 return; 3744 } 3745 3746 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3747 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3748 3749 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3750 val32 |= B_AX_FS_WDT_INT; 3751 val32 &= ~B_AX_FS_WDT_INT_MSK; 3752 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3753 } 3754 3755 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3756 { 3757 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3758 3759 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3760 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3761 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3762 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3763 3764 rtw89_disable_fw_watchdog(rtwdev); 3765 3766 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3767 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3768 } 3769 3770 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3771 bool dlfw, bool include_bb) 3772 { 3773 u32 val; 3774 int ret; 3775 3776 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3777 return -EFAULT; 3778 3779 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3780 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3781 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3782 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3783 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3784 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3785 3786 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3787 3788 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3789 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3790 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3791 B_AX_WCPU_FWDL_STS_MASK); 3792 3793 if (dlfw) 3794 val |= B_AX_WCPU_FWDL_EN; 3795 3796 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3797 3798 if (rtw89_is_rtl885xb(rtwdev)) 3799 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3800 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3801 3802 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3803 boot_reason); 3804 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3805 3806 if (!dlfw) { 3807 mdelay(5); 3808 3809 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3810 if (ret) 3811 return ret; 3812 } 3813 3814 return 0; 3815 } 3816 3817 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 3818 { 3819 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3820 u32 val; 3821 3822 if (chip_id == RTL8852C) 3823 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3824 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3825 else 3826 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3827 B_AX_PKT_BUF_EN; 3828 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3829 } 3830 3831 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 3832 { 3833 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3834 u32 val; 3835 3836 if (chip_id == RTL8851B || chip_id == RTL8852BT) 3837 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3838 else 3839 val = B_AX_DISPATCHER_CLK_EN; 3840 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3841 3842 if (chip_id != RTL8852C) 3843 return; 3844 3845 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3846 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3847 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3848 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3849 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3850 3851 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3852 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3853 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3854 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3855 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3856 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3857 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3858 } 3859 3860 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3861 { 3862 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3863 int ret; 3864 3865 mac->hci_func_en(rtwdev); 3866 mac->dmac_func_pre_en(rtwdev); 3867 3868 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3869 if (ret) { 3870 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3871 return ret; 3872 } 3873 3874 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 3875 if (ret) { 3876 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3877 return ret; 3878 } 3879 3880 return ret; 3881 } 3882 3883 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3884 { 3885 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3886 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3887 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3888 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3889 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3890 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3891 3892 return 0; 3893 } 3894 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3895 3896 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3897 { 3898 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3899 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3900 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3901 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3902 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3903 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3904 3905 return 0; 3906 } 3907 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3908 3909 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 3910 { 3911 int ret; 3912 3913 ret = rtw89_mac_power_switch(rtwdev, true); 3914 if (ret) { 3915 rtw89_mac_power_switch(rtwdev, false); 3916 ret = rtw89_mac_power_switch(rtwdev, true); 3917 if (ret) 3918 return ret; 3919 } 3920 3921 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3922 3923 if (include_bb) { 3924 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 3925 if (rtwdev->dbcc_en) 3926 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 3927 } 3928 3929 ret = rtw89_mac_dmac_pre_init(rtwdev); 3930 if (ret) 3931 return ret; 3932 3933 if (rtwdev->hci.ops->mac_pre_init) { 3934 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3935 if (ret) 3936 return ret; 3937 } 3938 3939 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 3940 if (ret) 3941 return ret; 3942 3943 return 0; 3944 } 3945 3946 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3947 { 3948 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3949 const struct rtw89_chip_info *chip = rtwdev->chip; 3950 bool include_bb = !!chip->bbmcu_nr; 3951 int ret; 3952 3953 ret = rtw89_mac_partial_init(rtwdev, include_bb); 3954 if (ret) 3955 goto fail; 3956 3957 ret = rtw89_chip_enable_bb_rf(rtwdev); 3958 if (ret) 3959 goto fail; 3960 3961 ret = mac->sys_init(rtwdev); 3962 if (ret) 3963 goto fail; 3964 3965 ret = mac->trx_init(rtwdev); 3966 if (ret) 3967 goto fail; 3968 3969 ret = rtw89_mac_feat_init(rtwdev); 3970 if (ret) 3971 goto fail; 3972 3973 if (rtwdev->hci.ops->mac_post_init) { 3974 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3975 if (ret) 3976 goto fail; 3977 } 3978 3979 rtw89_fw_send_all_early_h2c(rtwdev); 3980 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3981 3982 return ret; 3983 fail: 3984 rtw89_mac_power_switch(rtwdev, false); 3985 3986 return ret; 3987 } 3988 3989 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3990 { 3991 u8 i; 3992 3993 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 3994 return; 3995 3996 for (i = 0; i < 4; i++) { 3997 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3998 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3999 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 4000 } 4001 } 4002 4003 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4004 { 4005 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 4006 return; 4007 4008 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4009 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 4010 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 4011 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 4012 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 4013 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 4014 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 4015 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 4016 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 4017 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 4018 } 4019 4020 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4021 { 4022 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4023 u8 grp = macid >> 5; 4024 int ret; 4025 4026 /* If this is called by change_interface() in the case of P2P, it could 4027 * be power-off, so ignore this operation. 4028 */ 4029 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4030 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4031 return 0; 4032 4033 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4034 if (ret) 4035 return ret; 4036 4037 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4038 4039 return 0; 4040 } 4041 4042 static const struct rtw89_port_reg rtw89_port_base_ax = { 4043 .port_cfg = R_AX_PORT_CFG_P0, 4044 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4045 .bcn_area = R_AX_BCN_AREA_P0, 4046 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4047 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4048 .tbtt_agg = R_AX_TBTT_AGG_P0, 4049 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4050 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4051 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4052 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4053 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4054 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4055 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4056 .tsftr_l = R_AX_TSFTR_LOW_P0, 4057 .tsftr_h = R_AX_TSFTR_HIGH_P0, 4058 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 4059 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4060 .mbssid = R_AX_MBSSID_CTRL, 4061 .mbssid_drop = R_AX_MBSSID_DROP_0, 4062 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4063 .ptcl_dbg = R_AX_PTCL_DBG, 4064 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4065 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4066 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4067 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4068 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4069 }; 4070 4071 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4072 struct rtw89_vif *rtwvif, u8 type) 4073 { 4074 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4075 const struct rtw89_port_reg *p = mac->port_base; 4076 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif->port); 4077 u32 reg_info, reg_ctrl; 4078 u32 val; 4079 int ret; 4080 4081 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif->mac_idx); 4082 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif->mac_idx); 4083 4084 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4085 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4086 fsleep(100); 4087 4088 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4089 true, rtwdev, reg_info, mask); 4090 if (ret) 4091 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4092 } 4093 4094 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4095 { 4096 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4097 const struct rtw89_port_reg *p = mac->port_base; 4098 4099 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif->port)); 4100 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 1); 4101 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 0); 4102 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 0); 4103 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4104 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK, 1); 4105 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 1); 4106 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4107 4108 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM0); 4109 if (rtwvif->port == RTW89_PORT_0) 4110 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM1); 4111 4112 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif->port)); 4113 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4114 fsleep(2000); 4115 } 4116 4117 #define BCN_INTERVAL 100 4118 #define BCN_ERLY_DEF 160 4119 #define BCN_SETUP_DEF 2 4120 #define BCN_HOLD_DEF 200 4121 #define BCN_MASK_DEF 0 4122 #define TBTT_ERLY_DEF 5 4123 #define BCN_SET_UNIT 32 4124 #define BCN_ERLY_SET_DLY (10 * 2) 4125 4126 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4127 struct rtw89_vif *rtwvif) 4128 { 4129 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4130 const struct rtw89_port_reg *p = mac->port_base; 4131 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4132 const struct rtw89_chip_info *chip = rtwdev->chip; 4133 bool need_backup = false; 4134 u32 backup_val; 4135 4136 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 4137 return; 4138 4139 if (chip->chip_id == RTL8852A && rtwvif->port != RTW89_PORT_0) { 4140 need_backup = true; 4141 backup_val = rtw89_read32_port(rtwdev, rtwvif, p->tbtt_prohib); 4142 } 4143 4144 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4145 rtw89_mac_bcn_drop(rtwdev, rtwvif); 4146 4147 if (chip->chip_id == RTL8852A) { 4148 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 4149 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 4150 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 4151 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 4152 } 4153 4154 msleep(vif->bss_conf.beacon_int + 1); 4155 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 4156 B_AX_BRK_SETUP); 4157 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 4158 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 4159 4160 if (need_backup) 4161 rtw89_write32_port(rtwdev, rtwvif, p->tbtt_prohib, backup_val); 4162 } 4163 4164 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4165 struct rtw89_vif *rtwvif, bool en) 4166 { 4167 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4168 const struct rtw89_port_reg *p = mac->port_base; 4169 4170 if (en) 4171 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4172 else 4173 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4174 } 4175 4176 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4177 struct rtw89_vif *rtwvif, bool en) 4178 { 4179 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4180 const struct rtw89_port_reg *p = mac->port_base; 4181 4182 if (en) 4183 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4184 else 4185 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4186 } 4187 4188 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4189 struct rtw89_vif *rtwvif) 4190 { 4191 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4192 const struct rtw89_port_reg *p = mac->port_base; 4193 4194 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 4195 rtwvif->net_type); 4196 } 4197 4198 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4199 struct rtw89_vif *rtwvif) 4200 { 4201 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4202 const struct rtw89_port_reg *p = mac->port_base; 4203 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 4204 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4205 4206 if (en) 4207 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 4208 else 4209 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 4210 } 4211 4212 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4213 struct rtw89_vif *rtwvif) 4214 { 4215 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4216 const struct rtw89_port_reg *p = mac->port_base; 4217 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4218 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4219 u32 bit = B_AX_RX_BSSID_FIT_EN; 4220 4221 if (en) 4222 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 4223 else 4224 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 4225 } 4226 4227 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4228 struct rtw89_vif *rtwvif, bool en) 4229 { 4230 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4231 const struct rtw89_port_reg *p = mac->port_base; 4232 4233 if (en) 4234 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4235 else 4236 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4237 } 4238 4239 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4240 struct rtw89_vif *rtwvif) 4241 { 4242 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4243 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4244 4245 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif, en); 4246 } 4247 4248 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4249 struct rtw89_vif *rtwvif, bool en) 4250 { 4251 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4252 const struct rtw89_port_reg *p = mac->port_base; 4253 4254 if (en) 4255 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4256 else 4257 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4258 } 4259 4260 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4261 struct rtw89_vif *rtwvif) 4262 { 4263 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 4264 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4265 4266 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4267 } 4268 4269 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4270 { 4271 struct rtw89_vif *rtwvif; 4272 4273 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4274 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4275 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4276 } 4277 4278 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4279 struct rtw89_vif *rtwvif) 4280 { 4281 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4282 const struct rtw89_port_reg *p = mac->port_base; 4283 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4284 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 4285 4286 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 4287 bcn_int); 4288 } 4289 4290 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4291 struct rtw89_vif *rtwvif) 4292 { 4293 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4294 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4295 const struct rtw89_port_reg *p = mac->port_base; 4296 u8 port = rtwvif->port; 4297 u32 reg; 4298 4299 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif->mac_idx); 4300 rtw89_write8(rtwdev, reg, win); 4301 } 4302 4303 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4304 struct rtw89_vif *rtwvif) 4305 { 4306 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4307 const struct rtw89_port_reg *p = mac->port_base; 4308 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4309 u32 addr; 4310 4311 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif->mac_idx); 4312 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4313 4314 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4315 vif->bss_conf.dtim_period); 4316 } 4317 4318 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4319 struct rtw89_vif *rtwvif) 4320 { 4321 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4322 const struct rtw89_port_reg *p = mac->port_base; 4323 4324 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4325 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4326 } 4327 4328 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4329 struct rtw89_vif *rtwvif) 4330 { 4331 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4332 const struct rtw89_port_reg *p = mac->port_base; 4333 4334 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4335 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4336 } 4337 4338 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4339 struct rtw89_vif *rtwvif) 4340 { 4341 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4342 const struct rtw89_port_reg *p = mac->port_base; 4343 4344 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 4345 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4346 } 4347 4348 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4349 struct rtw89_vif *rtwvif) 4350 { 4351 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4352 const struct rtw89_port_reg *p = mac->port_base; 4353 4354 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 4355 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4356 } 4357 4358 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4359 struct rtw89_vif *rtwvif) 4360 { 4361 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4362 const struct rtw89_port_reg *p = mac->port_base; 4363 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4364 static const u32 masks[RTW89_PORT_NUM] = { 4365 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4366 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4367 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4368 }; 4369 u8 port = rtwvif->port; 4370 u32 reg_base; 4371 u32 reg; 4372 u8 bss_color; 4373 4374 bss_color = vif->bss_conf.he_bss_color.color; 4375 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4376 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx); 4377 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4378 } 4379 4380 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4381 struct rtw89_vif *rtwvif) 4382 { 4383 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4384 const struct rtw89_port_reg *p = mac->port_base; 4385 u8 port = rtwvif->port; 4386 u32 reg; 4387 4388 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4389 return; 4390 4391 if (port == 0) { 4392 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif->mac_idx); 4393 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4394 } 4395 } 4396 4397 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4398 struct rtw89_vif *rtwvif) 4399 { 4400 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4401 const struct rtw89_port_reg *p = mac->port_base; 4402 u8 port = rtwvif->port; 4403 u32 reg; 4404 u32 val; 4405 4406 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif->mac_idx); 4407 val = rtw89_read32(rtwdev, reg); 4408 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4409 if (port == 0) 4410 val &= ~BIT(0); 4411 rtw89_write32(rtwdev, reg, val); 4412 } 4413 4414 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4415 struct rtw89_vif *rtwvif, bool enable) 4416 { 4417 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4418 const struct rtw89_port_reg *p = mac->port_base; 4419 4420 if (enable) 4421 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 4422 B_AX_PORT_FUNC_EN); 4423 else 4424 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 4425 B_AX_PORT_FUNC_EN); 4426 } 4427 4428 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4429 struct rtw89_vif *rtwvif) 4430 { 4431 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4432 const struct rtw89_port_reg *p = mac->port_base; 4433 4434 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 4435 BCN_ERLY_DEF); 4436 } 4437 4438 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4439 struct rtw89_vif *rtwvif) 4440 { 4441 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4442 const struct rtw89_port_reg *p = mac->port_base; 4443 u16 val; 4444 4445 if (rtwdev->chip->chip_id != RTL8852C) 4446 return; 4447 4448 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4449 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4450 return; 4451 4452 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4453 B_AX_TBTT_SHIFT_OFST_SIGN; 4454 4455 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 4456 B_AX_TBTT_SHIFT_OFST_MASK, val); 4457 } 4458 4459 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4460 struct rtw89_vif *rtwvif, 4461 struct rtw89_vif *rtwvif_src, 4462 u16 offset_tu) 4463 { 4464 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4465 const struct rtw89_port_reg *p = mac->port_base; 4466 u32 val, reg; 4467 4468 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4469 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif->port * 4, 4470 rtwvif->mac_idx); 4471 4472 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4473 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4474 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4475 } 4476 4477 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4478 struct rtw89_vif *rtwvif, 4479 struct rtw89_vif *rtwvif_src, 4480 u8 offset, int *n_offset) 4481 { 4482 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 4483 return; 4484 4485 /* adjust offset randomly to avoid beacon conflict */ 4486 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4487 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 4488 (*n_offset) * offset); 4489 4490 (*n_offset)++; 4491 } 4492 4493 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4494 { 4495 struct rtw89_vif *src = NULL, *tmp; 4496 u8 offset = 100, vif_aps = 0; 4497 int n_offset = 1; 4498 4499 rtw89_for_each_rtwvif(rtwdev, tmp) { 4500 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4501 src = tmp; 4502 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4503 vif_aps++; 4504 } 4505 4506 if (vif_aps == 0) 4507 return; 4508 4509 offset /= (vif_aps + 1); 4510 4511 rtw89_for_each_rtwvif(rtwdev, tmp) 4512 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4513 } 4514 4515 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4516 { 4517 int ret; 4518 4519 ret = rtw89_mac_port_update(rtwdev, rtwvif); 4520 if (ret) 4521 return ret; 4522 4523 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4524 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4525 4526 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4527 if (ret) 4528 return ret; 4529 4530 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4531 if (ret) 4532 return ret; 4533 4534 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4535 if (ret) 4536 return ret; 4537 4538 ret = rtw89_cam_init(rtwdev, rtwvif); 4539 if (ret) 4540 return ret; 4541 4542 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4543 if (ret) 4544 return ret; 4545 4546 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, NULL); 4547 if (ret) 4548 return ret; 4549 4550 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, NULL); 4551 if (ret) 4552 return ret; 4553 4554 return 0; 4555 } 4556 4557 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4558 { 4559 int ret; 4560 4561 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4562 if (ret) 4563 return ret; 4564 4565 rtw89_cam_deinit(rtwdev, rtwvif); 4566 4567 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4568 if (ret) 4569 return ret; 4570 4571 return 0; 4572 } 4573 4574 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4575 { 4576 u8 port = rtwvif->port; 4577 4578 if (port >= RTW89_PORT_NUM) 4579 return -EINVAL; 4580 4581 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4582 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4583 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4584 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4585 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4586 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4587 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif); 4588 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif); 4589 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4590 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4591 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4592 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4593 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4594 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4595 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4596 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4597 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4598 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4599 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4600 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4601 rtw89_mac_port_tsf_resync_all(rtwdev); 4602 fsleep(BCN_ERLY_SET_DLY); 4603 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4604 4605 return 0; 4606 } 4607 4608 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4609 u64 *tsf) 4610 { 4611 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4612 const struct rtw89_port_reg *p = mac->port_base; 4613 u32 tsf_low, tsf_high; 4614 int ret; 4615 4616 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 4617 if (ret) 4618 return ret; 4619 4620 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 4621 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 4622 *tsf = (u64)tsf_high << 32 | tsf_low; 4623 4624 return 0; 4625 } 4626 4627 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4628 struct cfg80211_bss *bss, 4629 void *data) 4630 { 4631 const struct cfg80211_bss_ies *ies; 4632 const struct element *elem; 4633 bool *tolerated = data; 4634 4635 rcu_read_lock(); 4636 ies = rcu_dereference(bss->ies); 4637 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4638 ies->len); 4639 4640 if (!elem || elem->datalen < 10 || 4641 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4642 *tolerated = false; 4643 rcu_read_unlock(); 4644 } 4645 4646 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4647 struct ieee80211_vif *vif) 4648 { 4649 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4650 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4651 struct ieee80211_hw *hw = rtwdev->hw; 4652 bool tolerated = true; 4653 u32 reg; 4654 4655 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 4656 return; 4657 4658 if (!(vif->bss_conf.chanreq.oper.chan->flags & IEEE80211_CHAN_RADAR)) 4659 return; 4660 4661 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chanreq.oper, 4662 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4663 &tolerated); 4664 4665 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 4666 rtwvif->mac_idx); 4667 if (tolerated) 4668 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4669 else 4670 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4671 } 4672 4673 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4674 { 4675 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4676 } 4677 4678 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4679 { 4680 int ret; 4681 4682 rtwvif->mac_id = rtw89_acquire_mac_id(rtwdev); 4683 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4684 return -ENOSPC; 4685 4686 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4687 if (ret) 4688 goto release_mac_id; 4689 4690 return 0; 4691 4692 release_mac_id: 4693 rtw89_release_mac_id(rtwdev, rtwvif->mac_id); 4694 4695 return ret; 4696 } 4697 4698 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4699 { 4700 int ret; 4701 4702 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4703 rtw89_release_mac_id(rtwdev, rtwvif->mac_id); 4704 4705 return ret; 4706 } 4707 4708 static void 4709 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4710 { 4711 } 4712 4713 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4714 { 4715 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4716 4717 return band == op->band_type && channel == op->primary_channel; 4718 } 4719 4720 static void 4721 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4722 u32 len) 4723 { 4724 const struct rtw89_c2h_scanofld *c2h = 4725 (const struct rtw89_c2h_scanofld *)skb->data; 4726 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4727 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4728 struct rtw89_chan new; 4729 u8 reason, status, tx_fail, band, actual_period, expect_period; 4730 u32 last_chan = rtwdev->scan_info.last_chan_idx, report_tsf; 4731 u8 mac_idx, sw_def, fw_def; 4732 u16 chan; 4733 int ret; 4734 4735 if (!rtwvif) 4736 return; 4737 4738 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 4739 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 4740 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 4741 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 4742 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 4743 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 4744 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 4745 4746 4747 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4748 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4749 4750 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4751 "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4752 mac_idx, band, chan, reason, status, tx_fail, actual_period); 4753 4754 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4755 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 4756 expect_period = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 4757 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 4758 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 4759 4760 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4761 "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 4762 sw_def, fw_def, report_tsf, expect_period); 4763 } 4764 4765 switch (reason) { 4766 case RTW89_SCAN_LEAVE_OP_NOTIFY: 4767 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4768 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4769 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, false); 4770 ieee80211_stop_queues(rtwdev->hw); 4771 } 4772 return; 4773 case RTW89_SCAN_END_SCAN_NOTIFY: 4774 if (rtwdev->scan_info.abort) 4775 return; 4776 4777 if (rtwvif && rtwvif->scan_req && 4778 last_chan < rtwvif->scan_req->n_channels) { 4779 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4780 if (ret) { 4781 rtw89_hw_scan_abort(rtwdev, vif); 4782 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4783 } 4784 } else { 4785 rtw89_hw_scan_complete(rtwdev, vif, false); 4786 } 4787 break; 4788 case RTW89_SCAN_ENTER_OP_NOTIFY: 4789 case RTW89_SCAN_ENTER_CH_NOTIFY: 4790 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4791 rtw89_assign_entity_chan(rtwdev, rtwvif->chanctx_idx, 4792 &rtwdev->scan_info.op_chan); 4793 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, true); 4794 ieee80211_wake_queues(rtwdev->hw); 4795 } else { 4796 rtw89_chan_create(&new, chan, chan, band, 4797 RTW89_CHANNEL_WIDTH_20); 4798 rtw89_assign_entity_chan(rtwdev, rtwvif->chanctx_idx, 4799 &new); 4800 } 4801 break; 4802 default: 4803 return; 4804 } 4805 } 4806 4807 static void 4808 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4809 struct sk_buff *skb) 4810 { 4811 struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4812 enum nl80211_cqm_rssi_threshold_event nl_event; 4813 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4814 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4815 u8 type, event, mac_id; 4816 s8 sig; 4817 4818 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4819 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4820 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4821 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4822 4823 if (mac_id != rtwvif->mac_id) 4824 return; 4825 4826 rtw89_debug(rtwdev, RTW89_DBG_FW, 4827 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4828 mac_id, type, sig, event); 4829 4830 switch (type) { 4831 case RTW89_BCN_FLTR_BEACON_LOSS: 4832 if (!rtwdev->scanning && !rtwvif->offchan) 4833 ieee80211_connection_loss(vif); 4834 else 4835 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4836 return; 4837 case RTW89_BCN_FLTR_NOTIFY: 4838 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4839 break; 4840 case RTW89_BCN_FLTR_RSSI: 4841 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4842 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4843 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4844 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4845 else 4846 return; 4847 break; 4848 default: 4849 return; 4850 } 4851 4852 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4853 } 4854 4855 static void 4856 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4857 u32 len) 4858 { 4859 struct rtw89_vif *rtwvif; 4860 4861 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4862 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4863 } 4864 4865 static void 4866 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4867 { 4868 /* N.B. This will run in interrupt context. */ 4869 4870 rtw89_debug(rtwdev, RTW89_DBG_FW, 4871 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4872 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4873 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4874 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4875 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4876 } 4877 4878 static void 4879 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4880 { 4881 /* N.B. This will run in interrupt context. */ 4882 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4883 const struct rtw89_c2h_done_ack *c2h = 4884 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4885 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4886 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4887 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4888 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4889 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4890 struct rtw89_completion_data data = {}; 4891 unsigned int cond; 4892 4893 rtw89_debug(rtwdev, RTW89_DBG_FW, 4894 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4895 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4896 4897 if (h2c_cat != H2C_CAT_MAC) 4898 return; 4899 4900 switch (h2c_class) { 4901 default: 4902 return; 4903 case H2C_CL_MAC_FW_OFLD: 4904 switch (h2c_func) { 4905 default: 4906 return; 4907 case H2C_FUNC_ADD_SCANOFLD_CH: 4908 cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 4909 break; 4910 case H2C_FUNC_SCANOFLD: 4911 cond = RTW89_SCANOFLD_WAIT_COND_START; 4912 break; 4913 case H2C_FUNC_SCANOFLD_BE: 4914 cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 4915 break; 4916 } 4917 4918 data.err = !!h2c_return; 4919 rtw89_complete_cond(fw_ofld_wait, cond, &data); 4920 return; 4921 } 4922 } 4923 4924 static void 4925 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4926 { 4927 rtw89_fw_log_dump(rtwdev, c2h->data, len); 4928 } 4929 4930 static void 4931 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4932 { 4933 } 4934 4935 static void 4936 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 4937 u32 len) 4938 { 4939 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 4940 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 4941 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 4942 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 4943 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 4944 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 4945 struct rtw89_completion_data data = {}; 4946 unsigned int cond; 4947 4948 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 4949 pkt_id, pkt_op, pkt_len); 4950 4951 data.err = !pkt_len; 4952 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 4953 4954 rtw89_complete_cond(wait, cond, &data); 4955 } 4956 4957 static void 4958 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4959 u32 len) 4960 { 4961 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 4962 } 4963 4964 static void 4965 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4966 { 4967 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4968 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4969 4970 switch (func) { 4971 case H2C_FUNC_ADD_MCC: 4972 case H2C_FUNC_START_MCC: 4973 case H2C_FUNC_STOP_MCC: 4974 case H2C_FUNC_DEL_MCC_GROUP: 4975 case H2C_FUNC_RESET_MCC_GROUP: 4976 case H2C_FUNC_MCC_REQ_TSF: 4977 case H2C_FUNC_MCC_MACID_BITMAP: 4978 case H2C_FUNC_MCC_SYNC: 4979 case H2C_FUNC_MCC_SET_DURATION: 4980 break; 4981 default: 4982 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4983 "invalid MCC C2H RCV ACK: func %d\n", func); 4984 return; 4985 } 4986 4987 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4988 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4989 } 4990 4991 static void 4992 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4993 { 4994 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4995 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4996 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4997 struct rtw89_completion_data data = {}; 4998 unsigned int cond; 4999 bool next = false; 5000 5001 switch (func) { 5002 case H2C_FUNC_MCC_REQ_TSF: 5003 next = true; 5004 break; 5005 case H2C_FUNC_MCC_MACID_BITMAP: 5006 case H2C_FUNC_MCC_SYNC: 5007 case H2C_FUNC_MCC_SET_DURATION: 5008 break; 5009 case H2C_FUNC_ADD_MCC: 5010 case H2C_FUNC_START_MCC: 5011 case H2C_FUNC_STOP_MCC: 5012 case H2C_FUNC_DEL_MCC_GROUP: 5013 case H2C_FUNC_RESET_MCC_GROUP: 5014 default: 5015 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5016 "invalid MCC C2H REQ ACK: func %d\n", func); 5017 return; 5018 } 5019 5020 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5021 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5022 group, func, retcode); 5023 5024 if (!retcode && next) 5025 return; 5026 5027 data.err = !!retcode; 5028 cond = RTW89_MCC_WAIT_COND(group, func); 5029 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5030 } 5031 5032 static void 5033 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5034 { 5035 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5036 struct rtw89_completion_data data = {}; 5037 struct rtw89_mac_mcc_tsf_rpt *rpt; 5038 unsigned int cond; 5039 5040 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5041 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5042 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5043 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5044 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5045 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5046 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5047 5048 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5049 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5050 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5051 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5052 5053 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5054 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5055 } 5056 5057 static void 5058 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5059 { 5060 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5061 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5062 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5063 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5064 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5065 struct rtw89_completion_data data = {}; 5066 unsigned int cond; 5067 bool rsp = true; 5068 bool err; 5069 u8 func; 5070 5071 switch (status) { 5072 case RTW89_MAC_MCC_ADD_ROLE_OK: 5073 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5074 func = H2C_FUNC_ADD_MCC; 5075 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5076 break; 5077 case RTW89_MAC_MCC_START_GROUP_OK: 5078 case RTW89_MAC_MCC_START_GROUP_FAIL: 5079 func = H2C_FUNC_START_MCC; 5080 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5081 break; 5082 case RTW89_MAC_MCC_STOP_GROUP_OK: 5083 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5084 func = H2C_FUNC_STOP_MCC; 5085 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5086 break; 5087 case RTW89_MAC_MCC_DEL_GROUP_OK: 5088 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5089 func = H2C_FUNC_DEL_MCC_GROUP; 5090 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5091 break; 5092 case RTW89_MAC_MCC_RESET_GROUP_OK: 5093 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5094 func = H2C_FUNC_RESET_MCC_GROUP; 5095 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5096 break; 5097 case RTW89_MAC_MCC_SWITCH_CH_OK: 5098 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5099 case RTW89_MAC_MCC_TXNULL0_OK: 5100 case RTW89_MAC_MCC_TXNULL0_FAIL: 5101 case RTW89_MAC_MCC_TXNULL1_OK: 5102 case RTW89_MAC_MCC_TXNULL1_FAIL: 5103 case RTW89_MAC_MCC_SWITCH_EARLY: 5104 case RTW89_MAC_MCC_TBTT: 5105 case RTW89_MAC_MCC_DURATION_START: 5106 case RTW89_MAC_MCC_DURATION_END: 5107 rsp = false; 5108 break; 5109 default: 5110 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5111 "invalid MCC C2H STS RPT: status %d\n", status); 5112 return; 5113 } 5114 5115 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5116 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5117 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5118 5119 if (!rsp) 5120 return; 5121 5122 data.err = err; 5123 cond = RTW89_MCC_WAIT_COND(group, func); 5124 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5125 } 5126 5127 static void 5128 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5129 { 5130 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5131 const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5132 struct rtw89_completion_data data = {}; 5133 struct rtw89_mac_mrc_tsf_rpt *rpt; 5134 unsigned int i; 5135 5136 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5137 rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5138 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5139 le32_get_bits(c2h_rpt->w2, 5140 RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5141 5142 for (i = 0; i < rpt->num; i++) { 5143 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5144 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5145 5146 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5147 5148 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5149 "MRC C2H TSF RPT: index %u> %llu\n", 5150 i, rpt->tsfs[i]); 5151 } 5152 5153 rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5154 } 5155 5156 static void 5157 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5158 { 5159 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 5160 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 5161 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 5162 const struct rtw89_c2h_wow_aoac_report *c2h = 5163 (const struct rtw89_c2h_wow_aoac_report *)skb->data; 5164 struct rtw89_completion_data data = {}; 5165 unsigned int cond; 5166 5167 aoac_rpt->rpt_ver = c2h->rpt_ver; 5168 aoac_rpt->sec_type = c2h->sec_type; 5169 aoac_rpt->key_idx = c2h->key_idx; 5170 aoac_rpt->pattern_idx = c2h->pattern_idx; 5171 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok, 5172 RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX); 5173 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv)); 5174 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count, 5175 sizeof(aoac_rpt->eapol_key_replay_count)); 5176 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk)); 5177 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv)); 5178 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv)); 5179 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id); 5180 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn); 5181 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk)); 5182 5183 cond = RTW89_WOW_WAIT_COND(H2C_FUNC_AOAC_REPORT_REQ); 5184 rtw89_complete_cond(wait, cond, &data); 5185 } 5186 5187 static void 5188 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5189 { 5190 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5191 const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5192 struct rtw89_completion_data data = {}; 5193 enum rtw89_mac_mrc_status status; 5194 unsigned int cond; 5195 bool next = false; 5196 u32 tsf_high; 5197 u32 tsf_low; 5198 u8 sch_idx; 5199 u8 func; 5200 5201 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5202 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5203 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5204 tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5205 tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5206 5207 switch (status) { 5208 case RTW89_MAC_MRC_START_SCH_OK: 5209 func = H2C_FUNC_START_MRC; 5210 break; 5211 case RTW89_MAC_MRC_STOP_SCH_OK: 5212 /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5213 func = H2C_FUNC_DEL_MRC; 5214 next = true; 5215 break; 5216 case RTW89_MAC_MRC_DEL_SCH_OK: 5217 func = H2C_FUNC_DEL_MRC; 5218 break; 5219 case RTW89_MAC_MRC_EMPTY_SCH_FAIL: 5220 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5221 "MRC C2H STS RPT: empty sch fail\n"); 5222 return; 5223 case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL: 5224 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5225 "MRC C2H STS RPT: role not exist fail\n"); 5226 return; 5227 case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL: 5228 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5229 "MRC C2H STS RPT: data not found fail\n"); 5230 return; 5231 case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL: 5232 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5233 "MRC C2H STS RPT: get next slot fail\n"); 5234 return; 5235 case RTW89_MAC_MRC_ALT_ROLE_FAIL: 5236 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5237 "MRC C2H STS RPT: alt role fail\n"); 5238 return; 5239 case RTW89_MAC_MRC_ADD_PSTIMER_FAIL: 5240 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5241 "MRC C2H STS RPT: add ps timer fail\n"); 5242 return; 5243 case RTW89_MAC_MRC_MALLOC_FAIL: 5244 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5245 "MRC C2H STS RPT: malloc fail\n"); 5246 return; 5247 case RTW89_MAC_MRC_SWITCH_CH_FAIL: 5248 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5249 "MRC C2H STS RPT: switch ch fail\n"); 5250 return; 5251 case RTW89_MAC_MRC_TXNULL0_FAIL: 5252 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5253 "MRC C2H STS RPT: tx null-0 fail\n"); 5254 return; 5255 case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL: 5256 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5257 "MRC C2H STS RPT: port func en fail\n"); 5258 return; 5259 default: 5260 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5261 "invalid MRC C2H STS RPT: status %d\n", status); 5262 return; 5263 } 5264 5265 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5266 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 5267 sch_idx, status, (u64)tsf_high << 32 | tsf_low); 5268 5269 if (next) 5270 return; 5271 5272 cond = RTW89_MRC_WAIT_COND(sch_idx, func); 5273 rtw89_complete_cond(wait, cond, &data); 5274 } 5275 5276 static 5277 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5278 struct sk_buff *c2h, u32 len) = { 5279 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5280 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5281 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5282 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 5283 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5284 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5285 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5286 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5287 }; 5288 5289 static 5290 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5291 struct sk_buff *c2h, u32 len) = { 5292 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5293 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5294 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5295 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5296 }; 5297 5298 static 5299 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5300 struct sk_buff *c2h, u32 len) = { 5301 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5302 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5303 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5304 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5305 }; 5306 5307 static 5308 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 5309 struct sk_buff *c2h, u32 len) = { 5310 [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 5311 [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 5312 }; 5313 5314 static 5315 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev, 5316 struct sk_buff *c2h, u32 len) = { 5317 [RTW89_MAC_C2H_FUNC_AOAC_REPORT] = rtw89_mac_c2h_wow_aoac_rpt, 5318 }; 5319 5320 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 5321 struct sk_buff *skb) 5322 { 5323 const struct rtw89_c2h_scanofld *c2h = 5324 (const struct rtw89_c2h_scanofld *)skb->data; 5325 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5326 struct rtw89_completion_data data = {}; 5327 unsigned int cond; 5328 u8 status, reason; 5329 5330 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5331 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5332 data.err = status != RTW89_SCAN_STATUS_SUCCESS; 5333 5334 if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 5335 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 5336 cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 5337 else 5338 cond = RTW89_SCANOFLD_WAIT_COND_STOP; 5339 5340 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5341 } 5342 } 5343 5344 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5345 u8 class, u8 func) 5346 { 5347 switch (class) { 5348 default: 5349 return false; 5350 case RTW89_MAC_C2H_CLASS_INFO: 5351 switch (func) { 5352 default: 5353 return false; 5354 case RTW89_MAC_C2H_FUNC_REC_ACK: 5355 case RTW89_MAC_C2H_FUNC_DONE_ACK: 5356 return true; 5357 } 5358 case RTW89_MAC_C2H_CLASS_OFLD: 5359 switch (func) { 5360 default: 5361 return false; 5362 case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 5363 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 5364 return false; 5365 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 5366 return true; 5367 } 5368 case RTW89_MAC_C2H_CLASS_MCC: 5369 return true; 5370 case RTW89_MAC_C2H_CLASS_MRC: 5371 return true; 5372 case RTW89_MAC_C2H_CLASS_WOW: 5373 return true; 5374 } 5375 } 5376 5377 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5378 u32 len, u8 class, u8 func) 5379 { 5380 void (*handler)(struct rtw89_dev *rtwdev, 5381 struct sk_buff *c2h, u32 len) = NULL; 5382 5383 switch (class) { 5384 case RTW89_MAC_C2H_CLASS_INFO: 5385 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 5386 handler = rtw89_mac_c2h_info_handler[func]; 5387 break; 5388 case RTW89_MAC_C2H_CLASS_OFLD: 5389 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 5390 handler = rtw89_mac_c2h_ofld_handler[func]; 5391 break; 5392 case RTW89_MAC_C2H_CLASS_MCC: 5393 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 5394 handler = rtw89_mac_c2h_mcc_handler[func]; 5395 break; 5396 case RTW89_MAC_C2H_CLASS_MRC: 5397 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 5398 handler = rtw89_mac_c2h_mrc_handler[func]; 5399 break; 5400 case RTW89_MAC_C2H_CLASS_WOW: 5401 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_WOW) 5402 handler = rtw89_mac_c2h_wow_handler[func]; 5403 break; 5404 case RTW89_MAC_C2H_CLASS_FWDBG: 5405 return; 5406 default: 5407 rtw89_info(rtwdev, "c2h class %d not support\n", class); 5408 return; 5409 } 5410 if (!handler) { 5411 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 5412 func); 5413 return; 5414 } 5415 handler(rtwdev, skb, len); 5416 } 5417 5418 static 5419 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 5420 enum rtw89_phy_idx phy_idx, 5421 u32 reg_base, u32 *cr) 5422 { 5423 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 5424 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 5425 5426 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 5427 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 5428 addr); 5429 goto error; 5430 } 5431 5432 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 5433 if (mode == RTW89_QTA_SCC) { 5434 rtw89_err(rtwdev, 5435 "[TXPWR] addr=0x%x but hw not enable\n", 5436 addr); 5437 goto error; 5438 } 5439 5440 *cr = addr; 5441 return true; 5442 5443 error: 5444 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 5445 addr, phy_idx); 5446 5447 return false; 5448 } 5449 5450 static 5451 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 5452 { 5453 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 5454 int ret; 5455 5456 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5457 if (ret) 5458 return ret; 5459 5460 if (!enable) { 5461 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 5462 return 0; 5463 } 5464 5465 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 5466 B_AX_APP_MAC_INFO_RPT | 5467 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 5468 B_AX_PPDU_STAT_RPT_CRC32); 5469 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 5470 RTW89_PRPT_DEST_HOST); 5471 5472 return 0; 5473 } 5474 5475 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 5476 { 5477 #define MAC_AX_TIME_TH_SH 5 5478 #define MAC_AX_LEN_TH_SH 4 5479 #define MAC_AX_TIME_TH_MAX 255 5480 #define MAC_AX_LEN_TH_MAX 255 5481 #define MAC_AX_TIME_TH_DEF 88 5482 #define MAC_AX_LEN_TH_DEF 4080 5483 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5484 struct ieee80211_hw *hw = rtwdev->hw; 5485 u32 rts_threshold = hw->wiphy->rts_threshold; 5486 u32 time_th, len_th; 5487 u32 reg; 5488 5489 if (rts_threshold == (u32)-1) { 5490 time_th = MAC_AX_TIME_TH_DEF; 5491 len_th = MAC_AX_LEN_TH_DEF; 5492 } else { 5493 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 5494 len_th = rts_threshold; 5495 } 5496 5497 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 5498 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 5499 5500 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 5501 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 5502 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 5503 } 5504 5505 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 5506 { 5507 bool empty; 5508 int ret; 5509 5510 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5511 return; 5512 5513 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 5514 10000, 200000, false, rtwdev); 5515 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 5516 rtw89_info(rtwdev, "timed out to flush queues\n"); 5517 } 5518 5519 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 5520 { 5521 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 5522 u8 val; 5523 u16 val16; 5524 u32 val32; 5525 int ret; 5526 5527 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 5528 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5529 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 5530 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 5531 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 5532 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 5533 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5534 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 5535 5536 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 5537 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 5538 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 5539 5540 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 5541 if (ret) { 5542 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 5543 return ret; 5544 } 5545 val32 = val32 & B_AX_WL_RX_CTRL; 5546 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 5547 if (ret) { 5548 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 5549 return ret; 5550 } 5551 5552 switch (coex->pta_mode) { 5553 case RTW89_MAC_AX_COEX_RTK_MODE: 5554 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5555 val &= ~B_AX_BTMODE_MASK; 5556 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 5557 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5558 5559 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 5560 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 5561 5562 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 5563 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 5564 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 5565 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 5566 break; 5567 case RTW89_MAC_AX_COEX_CSR_MODE: 5568 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5569 val &= ~B_AX_BTMODE_MASK; 5570 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 5571 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5572 5573 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 5574 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 5575 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 5576 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 5577 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 5578 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 5579 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 5580 val16 |= B_AX_ENHANCED_BT; 5581 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 5582 5583 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 5584 break; 5585 default: 5586 return -EINVAL; 5587 } 5588 5589 switch (coex->direction) { 5590 case RTW89_MAC_AX_COEX_INNER: 5591 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5592 val = (val & ~BIT(2)) | BIT(1); 5593 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5594 break; 5595 case RTW89_MAC_AX_COEX_OUTPUT: 5596 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5597 val = val | BIT(1) | BIT(0); 5598 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5599 break; 5600 case RTW89_MAC_AX_COEX_INPUT: 5601 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5602 val = val & ~(BIT(2) | BIT(1)); 5603 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5604 break; 5605 default: 5606 return -EINVAL; 5607 } 5608 5609 return 0; 5610 } 5611 EXPORT_SYMBOL(rtw89_mac_coex_init); 5612 5613 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 5614 const struct rtw89_mac_ax_coex *coex) 5615 { 5616 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 5617 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 5618 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 5619 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 5620 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 5621 5622 switch (coex->pta_mode) { 5623 case RTW89_MAC_AX_COEX_RTK_MODE: 5624 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5625 MAC_AX_RTK_MODE); 5626 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 5627 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 5628 break; 5629 case RTW89_MAC_AX_COEX_CSR_MODE: 5630 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5631 MAC_AX_CSR_MODE); 5632 break; 5633 default: 5634 return -EINVAL; 5635 } 5636 5637 return 0; 5638 } 5639 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 5640 5641 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5642 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5643 { 5644 u32 val = 0, ret; 5645 5646 if (gnt_cfg->band[0].gnt_bt) 5647 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 5648 5649 if (gnt_cfg->band[0].gnt_bt_sw_en) 5650 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 5651 5652 if (gnt_cfg->band[0].gnt_wl) 5653 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 5654 5655 if (gnt_cfg->band[0].gnt_wl_sw_en) 5656 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 5657 5658 if (gnt_cfg->band[1].gnt_bt) 5659 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 5660 5661 if (gnt_cfg->band[1].gnt_bt_sw_en) 5662 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 5663 5664 if (gnt_cfg->band[1].gnt_wl) 5665 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 5666 5667 if (gnt_cfg->band[1].gnt_wl_sw_en) 5668 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 5669 5670 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 5671 if (ret) { 5672 rtw89_err(rtwdev, "Write LTE fail!\n"); 5673 return ret; 5674 } 5675 5676 return 0; 5677 } 5678 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 5679 5680 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 5681 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5682 { 5683 u32 val = 0; 5684 5685 if (gnt_cfg->band[0].gnt_bt) 5686 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5687 B_AX_GNT_BT_TX_VAL; 5688 else 5689 val |= B_AX_WL_ACT_VAL; 5690 5691 if (gnt_cfg->band[0].gnt_bt_sw_en) 5692 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5693 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5694 5695 if (gnt_cfg->band[0].gnt_wl) 5696 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5697 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5698 5699 if (gnt_cfg->band[0].gnt_wl_sw_en) 5700 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5701 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5702 5703 if (gnt_cfg->band[1].gnt_bt) 5704 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5705 B_AX_GNT_BT_TX_VAL; 5706 else 5707 val |= B_AX_WL_ACT_VAL; 5708 5709 if (gnt_cfg->band[1].gnt_bt_sw_en) 5710 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5711 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5712 5713 if (gnt_cfg->band[1].gnt_wl) 5714 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5715 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5716 5717 if (gnt_cfg->band[1].gnt_wl_sw_en) 5718 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5719 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5720 5721 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5722 5723 return 0; 5724 } 5725 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5726 5727 static 5728 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5729 { 5730 u32 reg; 5731 u16 val; 5732 int ret; 5733 5734 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5735 if (ret) 5736 return ret; 5737 5738 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 5739 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5740 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5741 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5742 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5743 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5744 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5745 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 5746 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 5747 B_AX_PLT_EN; 5748 rtw89_write16(rtwdev, reg, val); 5749 5750 return 0; 5751 } 5752 5753 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5754 { 5755 u32 fw_sb; 5756 5757 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5758 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5759 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5760 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5761 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5762 else 5763 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5764 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5765 val = B_AX_TOGGLE | 5766 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5767 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5768 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5769 fsleep(1000); /* avoid BT FW loss information */ 5770 } 5771 5772 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5773 { 5774 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5775 } 5776 5777 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5778 { 5779 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5780 5781 val = wl ? val | BIT(2) : val & ~BIT(2); 5782 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5783 5784 return 0; 5785 } 5786 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5787 5788 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5789 { 5790 struct rtw89_btc *btc = &rtwdev->btc; 5791 struct rtw89_btc_dm *dm = &btc->dm; 5792 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5793 int i; 5794 5795 if (wl) 5796 return 0; 5797 5798 for (i = 0; i < RTW89_PHY_MAX; i++) { 5799 g[i].gnt_bt_sw_en = 1; 5800 g[i].gnt_bt = 1; 5801 g[i].gnt_wl_sw_en = 1; 5802 g[i].gnt_wl = 0; 5803 } 5804 5805 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5806 } 5807 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5808 5809 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5810 { 5811 const struct rtw89_chip_info *chip = rtwdev->chip; 5812 u8 val = 0; 5813 5814 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) 5815 return false; 5816 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 5817 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5818 B_AX_LTE_MUX_CTRL_PATH >> 24); 5819 5820 return !!val; 5821 } 5822 5823 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 5824 { 5825 u32 reg; 5826 u16 cnt; 5827 5828 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 5829 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 5830 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 5831 5832 return cnt; 5833 } 5834 5835 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 5836 bool keep) 5837 { 5838 u32 reg; 5839 5840 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 5841 return; 5842 5843 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5844 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5845 if (keep) { 5846 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5847 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5848 BFRP_RX_STANDBY_TIMER_KEEP); 5849 } else { 5850 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5851 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5852 BFRP_RX_STANDBY_TIMER_RELEASE); 5853 } 5854 } 5855 5856 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5857 { 5858 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5859 u32 reg; 5860 u32 mask = mac->bfee_ctrl.mask; 5861 5862 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5863 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 5864 if (en) { 5865 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5866 rtw89_write32_set(rtwdev, reg, mask); 5867 } else { 5868 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5869 rtw89_write32_clr(rtwdev, reg, mask); 5870 } 5871 } 5872 5873 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 5874 { 5875 u32 reg; 5876 u32 val32; 5877 int ret; 5878 5879 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5880 if (ret) 5881 return ret; 5882 5883 /* AP mode set tx gid to 63 */ 5884 /* STA mode set tx gid to 0(default) */ 5885 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 5886 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5887 5888 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5889 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5890 5891 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5892 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5893 rtw89_write32(rtwdev, reg, val32); 5894 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5895 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5896 5897 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5898 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5899 B_AX_BFMEE_USE_NSTS | 5900 B_AX_BFMEE_CSI_GID_SEL | 5901 B_AX_BFMEE_CSI_FORCE_RETE_EN); 5902 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5903 rtw89_write32(rtwdev, reg, 5904 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5905 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5906 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5907 5908 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 5909 rtw89_write32_set(rtwdev, reg, 5910 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 5911 5912 return 0; 5913 } 5914 5915 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 5916 struct ieee80211_vif *vif, 5917 struct ieee80211_sta *sta) 5918 { 5919 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5920 u8 mac_idx = rtwvif->mac_idx; 5921 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5922 u8 port_sel = rtwvif->port; 5923 u8 sound_dim = 3, t; 5924 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5925 u32 reg; 5926 u16 val; 5927 int ret; 5928 5929 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5930 if (ret) 5931 return ret; 5932 5933 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5934 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5935 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5936 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5937 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5938 phy_cap[5]); 5939 sound_dim = min(sound_dim, t); 5940 } 5941 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5942 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5943 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5944 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5945 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5946 sta->deflink.vht_cap.cap); 5947 sound_dim = min(sound_dim, t); 5948 } 5949 nc = min(nc, sound_dim); 5950 nr = min(nr, sound_dim); 5951 5952 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5953 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5954 5955 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5956 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5957 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5958 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5959 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5960 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5961 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5962 5963 if (port_sel == 0) 5964 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5965 else 5966 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5967 5968 rtw89_write16(rtwdev, reg, val); 5969 5970 return 0; 5971 } 5972 5973 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 5974 struct ieee80211_vif *vif, 5975 struct ieee80211_sta *sta) 5976 { 5977 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5978 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5979 u32 reg; 5980 u8 mac_idx = rtwvif->mac_idx; 5981 int ret; 5982 5983 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5984 if (ret) 5985 return ret; 5986 5987 if (sta->deflink.he_cap.has_he) { 5988 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5989 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5990 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5991 } 5992 if (sta->deflink.vht_cap.vht_supported) { 5993 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5994 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5995 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5996 } 5997 if (sta->deflink.ht_cap.ht_supported) { 5998 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5999 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 6000 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 6001 } 6002 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6003 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6004 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 6005 rtw89_write32(rtwdev, 6006 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 6007 rrsc); 6008 6009 return 0; 6010 } 6011 6012 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 6013 struct ieee80211_vif *vif, 6014 struct ieee80211_sta *sta) 6015 { 6016 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6017 6018 if (rtw89_sta_has_beamformer_cap(sta)) { 6019 rtw89_debug(rtwdev, RTW89_DBG_BF, 6020 "initialize bfee for new association\n"); 6021 rtw89_mac_init_bfee_ax(rtwdev, rtwvif->mac_idx); 6022 rtw89_mac_set_csi_para_reg_ax(rtwdev, vif, sta); 6023 rtw89_mac_csi_rrsc_ax(rtwdev, vif, sta); 6024 } 6025 } 6026 6027 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6028 struct ieee80211_sta *sta) 6029 { 6030 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6031 6032 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 6033 } 6034 6035 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6036 struct ieee80211_bss_conf *conf) 6037 { 6038 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6039 u8 mac_idx = rtwvif->mac_idx; 6040 __le32 *p; 6041 6042 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 6043 6044 p = (__le32 *)conf->mu_group.membership; 6045 rtw89_write32(rtwdev, 6046 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 6047 le32_to_cpu(p[0])); 6048 rtw89_write32(rtwdev, 6049 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 6050 le32_to_cpu(p[1])); 6051 6052 p = (__le32 *)conf->mu_group.position; 6053 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 6054 le32_to_cpu(p[0])); 6055 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 6056 le32_to_cpu(p[1])); 6057 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 6058 le32_to_cpu(p[2])); 6059 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 6060 le32_to_cpu(p[3])); 6061 } 6062 6063 struct rtw89_mac_bf_monitor_iter_data { 6064 struct rtw89_dev *rtwdev; 6065 struct ieee80211_sta *down_sta; 6066 int count; 6067 }; 6068 6069 static 6070 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 6071 { 6072 struct rtw89_mac_bf_monitor_iter_data *iter_data = 6073 (struct rtw89_mac_bf_monitor_iter_data *)data; 6074 struct ieee80211_sta *down_sta = iter_data->down_sta; 6075 int *count = &iter_data->count; 6076 6077 if (down_sta == sta) 6078 return; 6079 6080 if (rtw89_sta_has_beamformer_cap(sta)) 6081 (*count)++; 6082 } 6083 6084 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 6085 struct ieee80211_sta *sta, bool disconnect) 6086 { 6087 struct rtw89_mac_bf_monitor_iter_data data; 6088 6089 data.rtwdev = rtwdev; 6090 data.down_sta = disconnect ? sta : NULL; 6091 data.count = 0; 6092 ieee80211_iterate_stations_atomic(rtwdev->hw, 6093 rtw89_mac_bf_monitor_calc_iter, 6094 &data); 6095 6096 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 6097 if (data.count) 6098 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6099 else 6100 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6101 } 6102 6103 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 6104 { 6105 struct rtw89_traffic_stats *stats = &rtwdev->stats; 6106 struct rtw89_vif *rtwvif; 6107 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 6108 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6109 bool keep_timer = true; 6110 bool old_keep_timer; 6111 6112 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6113 6114 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 6115 keep_timer = false; 6116 6117 if (keep_timer != old_keep_timer) { 6118 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6119 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 6120 keep_timer); 6121 } 6122 6123 if (en == old) 6124 return; 6125 6126 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6127 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 6128 } 6129 6130 static int 6131 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6132 u32 tx_time) 6133 { 6134 #define MAC_AX_DFLT_TX_TIME 5280 6135 u8 mac_idx = rtwsta->rtwvif->mac_idx; 6136 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 6137 u32 reg; 6138 int ret = 0; 6139 6140 if (rtwsta->cctl_tx_time) { 6141 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 6142 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6143 } else { 6144 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6145 if (ret) { 6146 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 6147 return ret; 6148 } 6149 6150 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6151 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 6152 max_tx_time >> 5); 6153 } 6154 6155 return ret; 6156 } 6157 6158 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6159 bool resume, u32 tx_time) 6160 { 6161 int ret = 0; 6162 6163 if (!resume) { 6164 rtwsta->cctl_tx_time = true; 6165 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 6166 } else { 6167 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 6168 rtwsta->cctl_tx_time = false; 6169 } 6170 6171 return ret; 6172 } 6173 6174 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6175 u32 *tx_time) 6176 { 6177 u8 mac_idx = rtwsta->rtwvif->mac_idx; 6178 u32 reg; 6179 int ret = 0; 6180 6181 if (rtwsta->cctl_tx_time) { 6182 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 6183 } else { 6184 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6185 if (ret) { 6186 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 6187 return ret; 6188 } 6189 6190 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6191 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 6192 } 6193 6194 return ret; 6195 } 6196 6197 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 6198 struct rtw89_sta *rtwsta, 6199 bool resume, u8 tx_retry) 6200 { 6201 int ret = 0; 6202 6203 rtwsta->data_tx_cnt_lmt = tx_retry; 6204 6205 if (!resume) { 6206 rtwsta->cctl_tx_retry_limit = true; 6207 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6208 } else { 6209 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6210 rtwsta->cctl_tx_retry_limit = false; 6211 } 6212 6213 return ret; 6214 } 6215 6216 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 6217 struct rtw89_sta *rtwsta, u8 *tx_retry) 6218 { 6219 u8 mac_idx = rtwsta->rtwvif->mac_idx; 6220 u32 reg; 6221 int ret = 0; 6222 6223 if (rtwsta->cctl_tx_retry_limit) { 6224 *tx_retry = rtwsta->data_tx_cnt_lmt; 6225 } else { 6226 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6227 if (ret) { 6228 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 6229 return ret; 6230 } 6231 6232 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); 6233 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 6234 } 6235 6236 return ret; 6237 } 6238 6239 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 6240 struct rtw89_vif *rtwvif, bool en) 6241 { 6242 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6243 u8 mac_idx = rtwvif->mac_idx; 6244 u16 set = mac->muedca_ctrl.mask; 6245 u32 reg; 6246 u32 ret; 6247 6248 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6249 if (ret) 6250 return ret; 6251 6252 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 6253 if (en) 6254 rtw89_write16_set(rtwdev, reg, set); 6255 else 6256 rtw89_write16_clr(rtwdev, reg, set); 6257 6258 return 0; 6259 } 6260 6261 static 6262 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 6263 { 6264 u32 val32; 6265 int ret; 6266 6267 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6268 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 6269 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 6270 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 6271 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6272 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6273 6274 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6275 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6276 if (ret) { 6277 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 6278 offset, val, mask); 6279 return ret; 6280 } 6281 6282 return 0; 6283 } 6284 6285 static 6286 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 6287 { 6288 u32 val32; 6289 int ret; 6290 6291 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6292 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 6293 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 6294 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 6295 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6296 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6297 6298 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6299 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6300 if (ret) { 6301 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 6302 return ret; 6303 } 6304 6305 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 6306 6307 return 0; 6308 } 6309 6310 static 6311 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 6312 { 6313 static const enum rtw89_pkt_drop_sel sels[] = { 6314 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 6315 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 6316 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 6317 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 6318 }; 6319 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6320 struct rtw89_pkt_drop_params params = {0}; 6321 int i; 6322 6323 params.mac_band = RTW89_MAC_0; 6324 params.macid = rtwsta->mac_id; 6325 params.port = rtwvif->port; 6326 params.mbssid = 0; 6327 params.tf_trs = rtwvif->trigger; 6328 6329 for (i = 0; i < ARRAY_SIZE(sels); i++) { 6330 params.sel = sels[i]; 6331 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6332 } 6333 } 6334 6335 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 6336 { 6337 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 6338 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6339 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 6340 struct rtw89_vif *target = data; 6341 6342 if (rtwvif != target) 6343 return; 6344 6345 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 6346 } 6347 6348 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 6349 { 6350 ieee80211_iterate_stations_atomic(rtwdev->hw, 6351 rtw89_mac_pkt_drop_vif_iter, 6352 rtwvif); 6353 } 6354 6355 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 6356 enum rtw89_mac_idx band) 6357 { 6358 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6359 struct rtw89_pkt_drop_params params = {0}; 6360 bool empty; 6361 int i, ret = 0, try_cnt = 3; 6362 6363 params.mac_band = band; 6364 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 6365 6366 for (i = 0; i < try_cnt; i++) { 6367 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 6368 50000, false, rtwdev); 6369 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 6370 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6371 else 6372 return 0; 6373 } 6374 return ret; 6375 } 6376 6377 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 6378 { 6379 struct rtw89_mac_h2c_info h2c_info = {}; 6380 struct rtw89_mac_c2h_info c2h_info = {}; 6381 u32 ret; 6382 6383 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; 6384 h2c_info.content_len = sizeof(h2c_info.u.hdr); 6385 h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); 6386 6387 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 6388 if (ret) 6389 return ret; 6390 6391 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) 6392 ret = -EINVAL; 6393 6394 return ret; 6395 } 6396 6397 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 6398 { 6399 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6400 const struct rtw89_chip_info *chip = rtwdev->chip; 6401 int ret; 6402 6403 if (enable_wow) { 6404 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 6405 if (ret) { 6406 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6407 return ret; 6408 } 6409 6410 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6411 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6412 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 6413 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 6414 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 6415 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 6416 rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 6417 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 6418 6419 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6420 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 6421 else 6422 rtw89_write32_set(rtwdev, R_AX_DBG_WOW, 6423 B_AX_DBG_WOW_CPU_IO_RX_EN); 6424 } else { 6425 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 6426 if (ret) { 6427 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6428 return ret; 6429 } 6430 6431 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6432 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6433 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 6434 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 6435 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 6436 } 6437 6438 return 0; 6439 } 6440 6441 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 6442 { 6443 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 6444 6445 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 6446 } 6447 6448 static 6449 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 6450 bool h2c_or_fwdl) 6451 { 6452 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 6453 u8 val; 6454 6455 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 6456 1, FWDL_WAIT_CNT, false, 6457 rtwdev, R_AX_WCPU_FW_CTRL); 6458 } 6459 6460 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 6461 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 6462 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 6463 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 6464 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 6465 .rx_fltr = R_AX_RX_FLTR_OPT, 6466 .port_base = &rtw89_port_base_ax, 6467 .agg_len_ht = R_AX_AGG_LEN_HT_0, 6468 .ps_status = R_AX_PPWRBIT_SETTING, 6469 6470 .muedca_ctrl = { 6471 .addr = R_AX_MUEDCA_EN, 6472 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 6473 }, 6474 .bfee_ctrl = { 6475 .addr = R_AX_BFMEE_RESP_OPTION, 6476 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 6477 B_AX_BFMEE_HE_NDPA_EN, 6478 }, 6479 .narrow_bw_ru_dis = { 6480 .addr = R_AX_RXTRIG_TEST_USER_2, 6481 .mask = B_AX_RXTRIG_RU26_DIS, 6482 }, 6483 .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 6484 6485 .check_mac_en = rtw89_mac_check_mac_en_ax, 6486 .sys_init = sys_init_ax, 6487 .trx_init = trx_init_ax, 6488 .hci_func_en = rtw89_mac_hci_func_en_ax, 6489 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 6490 .dle_func_en = dle_func_en_ax, 6491 .dle_clk_en = dle_clk_en_ax, 6492 .bf_assoc = rtw89_mac_bf_assoc_ax, 6493 6494 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 6495 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 6496 6497 .dle_mix_cfg = dle_mix_cfg_ax, 6498 .chk_dle_rdy = chk_dle_rdy_ax, 6499 .dle_buf_req = dle_buf_req_ax, 6500 .hfc_func_en = hfc_func_en_ax, 6501 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 6502 .hfc_mix_cfg = hfc_mix_cfg_ax, 6503 .hfc_get_mix_info = hfc_get_mix_info_ax, 6504 .wde_quota_cfg = wde_quota_cfg_ax, 6505 .ple_quota_cfg = ple_quota_cfg_ax, 6506 .set_cpuio = set_cpuio_ax, 6507 .dle_quota_change = dle_quota_change_ax, 6508 6509 .disable_cpu = rtw89_mac_disable_cpu_ax, 6510 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 6511 .fwdl_get_status = rtw89_fw_get_rdy_ax, 6512 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 6513 .parse_efuse_map = rtw89_parse_efuse_map_ax, 6514 .parse_phycap_map = rtw89_parse_phycap_map_ax, 6515 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 6516 6517 .cfg_plt = rtw89_mac_cfg_plt_ax, 6518 .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 6519 6520 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 6521 6522 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 6523 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 6524 6525 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 6526 .dump_err_status = rtw89_mac_dump_err_status_ax, 6527 6528 .is_txq_empty = mac_is_txq_empty_ax, 6529 6530 .add_chan_list = rtw89_hw_scan_add_chan_list_ax, 6531 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_ax, 6532 .scan_offload = rtw89_fw_h2c_scan_offload_ax, 6533 6534 .wow_config_mac = rtw89_wow_config_mac_ax, 6535 }; 6536 EXPORT_SYMBOL(rtw89_mac_gen_ax); 6537