1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "phy.h" 13 #include "ps.h" 14 #include "reg.h" 15 #include "ser.h" 16 #include "util.h" 17 18 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 19 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 20 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 21 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 22 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 23 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 24 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 26 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 28 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 29 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 30 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 31 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 35 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 36 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 37 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 38 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 39 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 40 }; 41 42 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 43 u32 val, enum rtw89_mac_mem_sel sel) 44 { 45 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 46 u32 addr = rtw89_mac_mem_base_addrs(rtwdev, sel) + offset; 47 48 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 49 rtw89_write32(rtwdev, mac->indir_access_addr, val); 50 } 51 52 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 53 enum rtw89_mac_mem_sel sel) 54 { 55 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 56 u32 addr = rtw89_mac_mem_base_addrs(rtwdev, sel) + offset; 57 58 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 59 return rtw89_read32(rtwdev, mac->indir_access_addr); 60 } 61 62 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 63 enum rtw89_mac_hwmod_sel sel) 64 { 65 u32 val, r_val; 66 67 if (sel == RTW89_DMAC_SEL) { 68 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 69 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 70 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 71 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 72 val = B_AX_CMAC_EN; 73 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 74 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 75 val = B_AX_CMAC1_FEN; 76 } else { 77 return -EINVAL; 78 } 79 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 80 (val & r_val) != val) 81 return -EFAULT; 82 83 return 0; 84 } 85 86 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 87 { 88 u8 lte_ctrl; 89 int ret; 90 91 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 92 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 93 if (ret && !test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 94 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 95 96 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 97 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 98 99 return ret; 100 } 101 102 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 103 { 104 u8 lte_ctrl; 105 int ret; 106 107 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 108 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 109 if (ret && !test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 110 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 111 112 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 113 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 114 115 return ret; 116 } 117 118 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 119 { 120 u32 ctrl_reg, data_reg, ctrl_data; 121 u32 val; 122 int ret; 123 124 switch (ctrl->type) { 125 case DLE_CTRL_TYPE_WDE: 126 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 127 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 128 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 129 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 130 B_AX_WDE_DFI_ACTIVE; 131 break; 132 case DLE_CTRL_TYPE_PLE: 133 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 134 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 135 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 136 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 137 B_AX_PLE_DFI_ACTIVE; 138 break; 139 default: 140 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 141 return -EINVAL; 142 } 143 144 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 145 146 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 147 1, 1000, false, rtwdev, ctrl_reg); 148 if (ret) { 149 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 150 ctrl_reg, ctrl_data); 151 return ret; 152 } 153 154 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 155 return 0; 156 } 157 158 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 159 struct rtw89_mac_dle_dfi_quota *quota) 160 { 161 struct rtw89_mac_dle_dfi_ctrl ctrl; 162 int ret; 163 164 ctrl.type = quota->dle_type; 165 ctrl.target = DLE_DFI_TYPE_QUOTA; 166 ctrl.addr = quota->qtaid; 167 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 168 if (ret) { 169 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 170 return ret; 171 } 172 173 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 174 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 175 return 0; 176 } 177 178 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 179 struct rtw89_mac_dle_dfi_qempty *qempty) 180 { 181 struct rtw89_mac_dle_dfi_ctrl ctrl; 182 int ret; 183 184 ctrl.type = qempty->dle_type; 185 ctrl.target = DLE_DFI_TYPE_QEMPTY; 186 ctrl.addr = qempty->grpsel; 187 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 188 if (ret) { 189 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 190 return ret; 191 } 192 193 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 194 return 0; 195 } 196 197 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 198 { 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 201 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 202 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 205 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 206 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 209 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 210 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 211 } 212 213 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 214 { 215 struct rtw89_mac_dle_dfi_qempty qempty; 216 struct rtw89_mac_dle_dfi_quota quota; 217 struct rtw89_mac_dle_dfi_ctrl ctrl; 218 u32 val, not_empty, i; 219 int ret; 220 221 qempty.dle_type = DLE_CTRL_TYPE_PLE; 222 qempty.grpsel = 0; 223 qempty.qempty = ~(u32)0; 224 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 225 if (ret) 226 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 227 else 228 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 229 230 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 231 if (!(not_empty & BIT(0))) 232 continue; 233 ctrl.type = DLE_CTRL_TYPE_PLE; 234 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 235 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 236 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 237 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 238 if (ret) 239 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 240 else 241 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 242 u32_get_bits(ctrl.out_data, 243 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 244 } 245 246 quota.dle_type = DLE_CTRL_TYPE_PLE; 247 quota.qtaid = 6; 248 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 249 if (ret) 250 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 251 else 252 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 253 quota.rsv_pgnum, quota.use_pgnum); 254 255 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 257 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 258 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 259 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 260 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 261 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 262 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 263 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 264 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 265 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 266 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 267 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 268 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 269 270 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 271 quota.dle_type = DLE_CTRL_TYPE_PLE; 272 quota.qtaid = 7; 273 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 274 if (ret) 275 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 276 else 277 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 278 quota.rsv_pgnum, quota.use_pgnum); 279 280 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 282 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 283 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 284 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 285 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 286 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 287 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 288 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 289 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 290 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 291 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 292 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 293 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 294 } 295 296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 298 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 299 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 300 301 dump_err_status_dispatcher_ax(rtwdev); 302 } 303 304 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 305 enum mac_ax_err_info err) 306 { 307 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 308 u32 dbg, event; 309 310 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 311 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 312 313 switch (event) { 314 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 315 rtw89_info(rtwdev, "quota lost!\n"); 316 mac->dump_qta_lost(rtwdev); 317 break; 318 default: 319 break; 320 } 321 } 322 323 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 324 { 325 const struct rtw89_chip_info *chip = rtwdev->chip; 326 u32 dmac_err; 327 int i, ret; 328 329 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 330 if (ret) { 331 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 332 return; 333 } 334 335 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 336 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 337 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 339 340 if (dmac_err) { 341 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 343 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 344 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 345 if (chip->chip_id == RTL8852C) { 346 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 348 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 352 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 353 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 354 } 355 } 356 357 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 360 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 361 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 362 if (chip->chip_id == RTL8852C) 363 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 364 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 365 else 366 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 367 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 368 } 369 370 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 371 if (chip->chip_id == RTL8852C) { 372 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 374 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 376 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 378 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 380 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 382 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 384 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 386 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 388 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 389 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 390 391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392 B_AX_DBG_SEL0, 0x8B); 393 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 394 B_AX_DBG_SEL1, 0x8B); 395 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 396 B_AX_SEL_0XC0_MASK, 1); 397 for (i = 0; i < 0x10; i++) { 398 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 399 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 400 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 401 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 402 } 403 } else if (chip->chip_id == RTL8922A) { 404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 406 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 407 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 408 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 409 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 410 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 411 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 412 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 413 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 414 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 415 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 416 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 417 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 418 } else { 419 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 421 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 423 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 425 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 427 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 429 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 430 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 431 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 432 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 433 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 435 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 437 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 438 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 439 } 440 } 441 442 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 445 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 449 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 450 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 451 } 452 453 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 454 if (chip->chip_id == RTL8922A) { 455 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 456 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 457 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 458 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 459 } else { 460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 462 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 463 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 464 } 465 } 466 467 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 468 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 470 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 471 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 472 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 474 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 475 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 476 } 477 478 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 479 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 486 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 487 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 488 } else { 489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 491 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 492 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 493 } 494 } 495 496 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 497 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 499 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 501 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 503 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 509 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 510 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 515 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 516 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 517 if (chip->chip_id == RTL8922A) { 518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 520 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 521 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 522 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 524 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 525 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 526 } else { 527 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 529 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 530 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 531 if (chip->chip_id == RTL8852C) { 532 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 533 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 534 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 535 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 536 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 537 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 538 } else { 539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 543 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 544 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 545 } 546 } 547 } 548 549 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 552 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 553 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 554 } 555 556 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 557 if (chip->chip_id == RTL8922A) { 558 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 559 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 560 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 561 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 562 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 563 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 564 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 565 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 566 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 567 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 568 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 569 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 570 } else { 571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 573 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 574 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 577 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 578 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 581 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 582 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 583 } 584 } 585 586 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 587 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 590 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 591 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 594 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 595 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 598 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 599 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 600 } else { 601 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 602 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 605 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 606 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 609 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 610 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 611 } 612 if (chip->chip_id == RTL8922A) { 613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 615 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 616 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 617 } 618 } 619 620 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 621 if (chip->chip_id == RTL8922A) { 622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 624 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 625 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 626 } else if (chip->chip_id == RTL8852C) { 627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 629 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 630 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 631 } 632 } 633 634 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 635 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 636 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 637 RTW89_MAC_MEM_AXIDMA)); 638 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 639 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 640 RTW89_MAC_MEM_AXIDMA)); 641 } 642 643 if (dmac_err & B_BE_MLO_ERR_INT) { 644 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 646 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 647 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 648 } 649 650 if (dmac_err & B_BE_PLRLS_ERR_INT) { 651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 653 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 654 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 655 } 656 } 657 658 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 659 u8 band) 660 { 661 const struct rtw89_chip_info *chip = rtwdev->chip; 662 u32 offset = 0; 663 u32 cmac_err; 664 int ret; 665 666 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 667 if (ret) { 668 if (band) 669 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 670 else 671 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 672 return; 673 } 674 675 if (band) 676 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 677 678 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 679 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 680 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 681 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 682 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 683 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 684 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 685 686 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 689 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 690 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 691 } 692 693 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 694 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 695 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 696 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 697 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 698 } 699 700 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 701 if (chip->chip_id == RTL8852C) { 702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 704 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 705 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 706 } else { 707 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 708 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 709 } 710 } 711 712 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 713 if (chip->chip_id == RTL8852C) { 714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 716 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 717 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 718 } else { 719 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 720 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 721 } 722 } 723 724 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 725 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 726 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 727 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 728 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 729 } 730 731 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 732 if (chip->chip_id == RTL8852C) { 733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 735 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 736 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 737 } else { 738 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 739 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 740 } 741 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 742 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 743 } 744 745 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 746 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 747 } 748 749 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 750 enum mac_ax_err_info err) 751 { 752 if (err != MAC_AX_ERR_L1_ERR_DMAC && 753 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 754 err != MAC_AX_ERR_L0_ERR_CMAC0 && 755 err != MAC_AX_ERR_L0_ERR_CMAC1 && 756 err != MAC_AX_ERR_RXI300) 757 return; 758 759 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 762 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 763 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 764 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 766 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 767 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 768 769 rtw89_mac_dump_dmac_err_status(rtwdev); 770 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 771 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 772 773 rtwdev->hci.ops->dump_err_status(rtwdev); 774 775 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 776 rtw89_mac_dump_l0_to_l1(rtwdev, err); 777 778 rtw89_info(rtwdev, "<---\n"); 779 } 780 781 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 782 { 783 struct rtw89_ser *ser = &rtwdev->ser; 784 u32 dmac_err, imr, isr; 785 int ret; 786 787 if (rtwdev->chip->chip_id == RTL8852C) { 788 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 789 if (ret) 790 return true; 791 792 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 793 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 794 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 795 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 796 797 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 798 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 799 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 800 return true; 801 } 802 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 803 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 804 return true; 805 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 806 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 807 return true; 808 } 809 } 810 811 return false; 812 } 813 814 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 815 { 816 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 817 const struct rtw89_chip_info *chip = rtwdev->chip; 818 u32 err, err_scnr; 819 int ret; 820 821 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 822 false, rtwdev, R_AX_HALT_C2H_CTRL); 823 if (ret) { 824 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 825 return ret; 826 } 827 828 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 829 830 if (!RTW89_CHK_FW_FEATURE(SER_POST_RECOVER_DMAC, &rtwdev->fw)) 831 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 832 833 err_scnr = RTW89_ERROR_SCENARIO(err); 834 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 835 err = MAC_AX_ERR_CPU_EXCEPTION; 836 else if (err_scnr == RTW89_WCPU_ASSERTION) 837 err = MAC_AX_ERR_ASSERTION; 838 else if (err_scnr == RTW89_RXI300_ERROR) 839 err = MAC_AX_ERR_RXI300; 840 841 if (rtw89_mac_suppress_log(rtwdev, err)) 842 goto bottom; 843 844 rtw89_fw_st_dbg_dump(rtwdev); 845 mac->dump_err_status(rtwdev, err); 846 847 bottom: 848 if (chip->chip_gen != RTW89_CHIP_AX) 849 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 850 851 if (RTW89_CHK_FW_FEATURE(SER_POST_RECOVER_DMAC, &rtwdev->fw)) 852 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 853 854 return err; 855 } 856 EXPORT_SYMBOL(rtw89_mac_get_err_status); 857 858 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 859 { 860 struct rtw89_ser *ser = &rtwdev->ser; 861 bool ser_l1_hdl = false; 862 u32 halt; 863 int ret = 0; 864 865 if (err > MAC_AX_SET_ERR_MAX) { 866 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 867 return -EINVAL; 868 } 869 870 if (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN) 871 ser_l1_hdl = true; 872 873 if (RTW89_CHK_FW_FEATURE(SER_L1_BY_EVENT, &rtwdev->fw) && ser_l1_hdl) 874 goto set; 875 876 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 877 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 878 if (ret) { 879 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 880 return -EFAULT; 881 } 882 883 set: 884 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 885 886 if (ser->prehandle_l1 && ser_l1_hdl) 887 return 0; 888 889 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 890 891 return 0; 892 } 893 EXPORT_SYMBOL(rtw89_mac_set_err_status); 894 895 static int hfc_reset_param(struct rtw89_dev *rtwdev) 896 { 897 const struct rtw89_hfc_param_ini *param_ini, *param_inis; 898 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 899 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 900 901 param_inis = rtwdev->chip->hfc_param_ini[rtwdev->hci.type]; 902 if (!param_inis) 903 return -EINVAL; 904 905 param_ini = ¶m_inis[qta_mode]; 906 907 param->en = 0; 908 909 if (param_ini->pub_cfg) 910 param->pub_cfg = *param_ini->pub_cfg; 911 912 if (param_ini->prec_cfg) 913 param->prec_cfg = *param_ini->prec_cfg; 914 915 if (param_ini->ch_cfg) 916 param->ch_cfg = param_ini->ch_cfg; 917 918 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 919 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 920 param->mode = param_ini->mode; 921 922 return 0; 923 } 924 925 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 926 { 927 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 928 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 929 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 930 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 931 932 if (ch >= RTW89_DMA_CH_NUM) 933 return -EINVAL; 934 935 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 936 ch_cfg[ch].max > pub_cfg->pub_max) 937 return -EINVAL; 938 if (ch_cfg[ch].grp >= grp_num) 939 return -EINVAL; 940 941 return 0; 942 } 943 944 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 945 { 946 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 947 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 948 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 949 950 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 951 if (rtwdev->chip->chip_id == RTL8852A) 952 return 0; 953 else 954 return -EFAULT; 955 } 956 957 return 0; 958 } 959 960 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 961 { 962 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 963 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 964 965 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 966 return -EFAULT; 967 968 return 0; 969 } 970 971 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 972 { 973 const struct rtw89_chip_info *chip = rtwdev->chip; 974 const struct rtw89_page_regs *regs = chip->page_regs; 975 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 976 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 977 int ret = 0; 978 u32 val = 0; 979 980 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 981 if (ret) 982 return ret; 983 984 ret = hfc_ch_cfg_chk(rtwdev, ch); 985 if (ret) 986 return ret; 987 988 if (ch > RTW89_DMA_B1HI) 989 return -EINVAL; 990 991 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 992 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 993 (cfg[ch].grp ? B_AX_GRP : 0); 994 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 995 996 return 0; 997 } 998 999 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 1000 { 1001 const struct rtw89_chip_info *chip = rtwdev->chip; 1002 const struct rtw89_page_regs *regs = chip->page_regs; 1003 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1004 struct rtw89_hfc_ch_info *info = param->ch_info; 1005 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 1006 u32 val; 1007 int ret; 1008 1009 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1010 if (ret) 1011 return ret; 1012 1013 if (ch > RTW89_DMA_H2C) 1014 return -EINVAL; 1015 1016 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 1017 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1018 if (ch < RTW89_DMA_H2C) 1019 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1020 else 1021 info[ch].used = cfg[ch].min - info[ch].aval; 1022 1023 return 0; 1024 } 1025 1026 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1027 { 1028 const struct rtw89_chip_info *chip = rtwdev->chip; 1029 const struct rtw89_page_regs *regs = chip->page_regs; 1030 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1031 u32 val; 1032 int ret; 1033 1034 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1035 if (ret) 1036 return ret; 1037 1038 ret = hfc_pub_cfg_chk(rtwdev); 1039 if (ret) 1040 return ret; 1041 1042 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1043 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1044 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1045 1046 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1047 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1048 1049 return 0; 1050 } 1051 1052 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1053 { 1054 const struct rtw89_chip_info *chip = rtwdev->chip; 1055 const struct rtw89_page_regs *regs = chip->page_regs; 1056 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1057 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1058 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1059 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1060 u32 val; 1061 1062 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1063 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1064 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1065 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1066 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1067 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1068 info->pub_aval = 1069 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1070 B_AX_PUB_AVAL_PG_MASK); 1071 info->wp_aval = 1072 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1073 B_AX_WP_AVAL_PG_MASK); 1074 1075 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1076 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1077 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1078 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1079 prec_cfg->ch011_full_cond = 1080 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1081 prec_cfg->h2c_full_cond = 1082 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1083 prec_cfg->wp_ch07_full_cond = 1084 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1085 prec_cfg->wp_ch811_full_cond = 1086 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1087 1088 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1089 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1090 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1091 1092 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1093 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1094 1095 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1096 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1097 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1098 1099 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1100 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1101 1102 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1103 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1104 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1105 } 1106 1107 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1108 { 1109 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1110 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1111 int ret; 1112 1113 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1114 if (ret) 1115 return ret; 1116 1117 mac->hfc_get_mix_info(rtwdev); 1118 1119 ret = hfc_pub_info_chk(rtwdev); 1120 if (param->en && ret) 1121 return ret; 1122 1123 return 0; 1124 } 1125 1126 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1127 { 1128 const struct rtw89_chip_info *chip = rtwdev->chip; 1129 const struct rtw89_page_regs *regs = chip->page_regs; 1130 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1131 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1132 u32 val; 1133 1134 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1136 1137 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1138 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1139 prec_cfg->h2c_full_cond); 1140 } 1141 1142 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1143 { 1144 const struct rtw89_chip_info *chip = rtwdev->chip; 1145 const struct rtw89_page_regs *regs = chip->page_regs; 1146 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1147 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1148 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1149 u32 val; 1150 1151 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1152 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1153 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1154 1155 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1156 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1157 1158 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1159 B_AX_PREC_PAGE_WP_CH07_MASK) | 1160 u32_encode_bits(prec_cfg->wp_ch811_prec, 1161 B_AX_PREC_PAGE_WP_CH811_MASK); 1162 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1163 1164 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1165 param->mode, B_AX_HCI_FC_MODE_MASK); 1166 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1167 B_AX_HCI_FC_WD_FULL_COND_MASK); 1168 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1169 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1170 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1171 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1172 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1173 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1174 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1175 } 1176 1177 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1178 { 1179 const struct rtw89_chip_info *chip = rtwdev->chip; 1180 const struct rtw89_page_regs *regs = chip->page_regs; 1181 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1182 u32 val; 1183 1184 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1185 param->en = en; 1186 param->h2c_en = h2c_en; 1187 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1188 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1189 (val & ~B_AX_HCI_FC_CH12_EN); 1190 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1191 } 1192 1193 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1194 { 1195 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1196 const struct rtw89_chip_info *chip = rtwdev->chip; 1197 u32 dma_ch_mask = chip->dma_ch_mask; 1198 int ret = 0; 1199 u8 ch; 1200 1201 if (reset) 1202 ret = hfc_reset_param(rtwdev); 1203 if (ret) 1204 return ret; 1205 1206 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1207 if (ret) 1208 return ret; 1209 1210 mac->hfc_func_en(rtwdev, false, false); 1211 1212 if (!en && h2c_en) { 1213 mac->hfc_h2c_cfg(rtwdev); 1214 mac->hfc_func_en(rtwdev, en, h2c_en); 1215 return 0; 1216 } 1217 1218 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1219 if (dma_ch_mask & BIT(ch)) 1220 continue; 1221 ret = hfc_ch_ctrl(rtwdev, ch); 1222 if (ret) 1223 return ret; 1224 } 1225 1226 ret = hfc_pub_ctrl(rtwdev); 1227 if (ret) 1228 return ret; 1229 1230 mac->hfc_mix_cfg(rtwdev); 1231 if (en || h2c_en) { 1232 mac->hfc_func_en(rtwdev, en, h2c_en); 1233 udelay(10); 1234 } 1235 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1236 if (dma_ch_mask & BIT(ch)) 1237 continue; 1238 ret = hfc_upd_ch_info(rtwdev, ch); 1239 if (ret) 1240 return ret; 1241 } 1242 ret = hfc_upd_mix_info(rtwdev); 1243 1244 return ret; 1245 } 1246 1247 #define PWR_POLL_CNT 2000 1248 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1249 const struct rtw89_pwr_cfg *cfg) 1250 { 1251 u8 val = 0; 1252 int ret; 1253 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1254 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1255 1256 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1257 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1258 1259 if (!ret) 1260 return 0; 1261 1262 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1263 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1264 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1265 1266 return -EBUSY; 1267 } 1268 1269 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1270 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1271 { 1272 const struct rtw89_pwr_cfg *cur_cfg; 1273 u32 addr; 1274 u8 val; 1275 1276 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1277 if (!(cur_cfg->intf_msk & intf_msk) || 1278 !(cur_cfg->cv_msk & cv_msk)) 1279 continue; 1280 1281 switch (cur_cfg->cmd) { 1282 case PWR_CMD_WRITE: 1283 addr = cur_cfg->addr; 1284 1285 if (cur_cfg->base == PWR_BASE_SDIO) 1286 addr |= SDIO_LOCAL_BASE_ADDR; 1287 1288 val = rtw89_read8(rtwdev, addr); 1289 val &= ~(cur_cfg->msk); 1290 val |= (cur_cfg->val & cur_cfg->msk); 1291 1292 rtw89_write8(rtwdev, addr, val); 1293 break; 1294 case PWR_CMD_POLL: 1295 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1296 return -EBUSY; 1297 break; 1298 case PWR_CMD_DELAY: 1299 if (cur_cfg->val == PWR_DELAY_US) 1300 udelay(cur_cfg->addr); 1301 else 1302 fsleep(cur_cfg->addr * 1000); 1303 break; 1304 default: 1305 return -EINVAL; 1306 } 1307 } 1308 1309 return 0; 1310 } 1311 1312 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1313 const struct rtw89_pwr_cfg * const *cfg_seq) 1314 { 1315 u8 intf_msk; 1316 int ret; 1317 1318 switch (rtwdev->hci.type) { 1319 case RTW89_HCI_TYPE_PCIE: 1320 intf_msk = PWR_INTF_MSK_PCIE; 1321 break; 1322 case RTW89_HCI_TYPE_USB: 1323 intf_msk = PWR_INTF_MSK_USB; 1324 break; 1325 case RTW89_HCI_TYPE_SDIO: 1326 intf_msk = PWR_INTF_MSK_SDIO; 1327 break; 1328 default: 1329 return -EOPNOTSUPP; 1330 } 1331 1332 for (; *cfg_seq; cfg_seq++) { 1333 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1334 intf_msk, *cfg_seq); 1335 if (ret) 1336 return -EBUSY; 1337 } 1338 1339 return 0; 1340 } 1341 1342 static enum rtw89_rpwm_req_pwr_state 1343 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1344 { 1345 enum rtw89_rpwm_req_pwr_state state; 1346 1347 switch (rtwdev->ps_mode) { 1348 case RTW89_PS_MODE_RFOFF: 1349 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1350 break; 1351 case RTW89_PS_MODE_CLK_GATED: 1352 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1353 break; 1354 case RTW89_PS_MODE_PWR_GATED: 1355 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1356 break; 1357 default: 1358 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1359 break; 1360 } 1361 return state; 1362 } 1363 1364 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1365 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1366 bool notify_wake) 1367 { 1368 u16 request; 1369 1370 spin_lock_bh(&rtwdev->rpwm_lock); 1371 1372 request = rtw89_read16(rtwdev, R_AX_RPWM); 1373 request ^= request | PS_RPWM_TOGGLE; 1374 request |= req_pwr_state; 1375 1376 if (notify_wake) { 1377 request |= PS_RPWM_NOTIFY_WAKE; 1378 } else { 1379 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1380 RPWM_SEQ_NUM_MAX; 1381 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1382 rtwdev->mac.rpwm_seq_num); 1383 1384 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1385 request |= PS_RPWM_ACK; 1386 } 1387 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1388 1389 spin_unlock_bh(&rtwdev->rpwm_lock); 1390 } 1391 1392 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1393 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1394 { 1395 bool request_deep_mode; 1396 bool in_deep_mode; 1397 u8 rpwm_req_num; 1398 u8 cpwm_rsp_seq; 1399 u8 cpwm_seq; 1400 u8 cpwm_status; 1401 1402 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1403 request_deep_mode = true; 1404 else 1405 request_deep_mode = false; 1406 1407 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1408 in_deep_mode = true; 1409 else 1410 in_deep_mode = false; 1411 1412 if (request_deep_mode != in_deep_mode) 1413 return -EPERM; 1414 1415 if (request_deep_mode) 1416 return 0; 1417 1418 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1419 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1420 PS_CPWM_RSP_SEQ_NUM); 1421 1422 if (rpwm_req_num != cpwm_rsp_seq) 1423 return -EPERM; 1424 1425 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1426 CPWM_SEQ_NUM_MAX; 1427 1428 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1429 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1430 return -EPERM; 1431 1432 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1433 if (cpwm_status != req_pwr_state) 1434 return -EPERM; 1435 1436 return 0; 1437 } 1438 1439 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1440 { 1441 enum rtw89_rpwm_req_pwr_state state; 1442 unsigned long delay = enter ? 10 : 150; 1443 int ret; 1444 int i; 1445 1446 if (enter) 1447 state = rtw89_mac_get_req_pwr_state(rtwdev); 1448 else 1449 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1450 1451 for (i = 0; i < RPWM_TRY_CNT; i++) { 1452 rtw89_mac_send_rpwm(rtwdev, state, false); 1453 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1454 !ret, delay, 15000, false, 1455 rtwdev, state); 1456 if (!ret) 1457 break; 1458 1459 if (i == RPWM_TRY_CNT - 1) { 1460 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1461 enter ? "entering" : "leaving"); 1462 rtw89_ser_notify(rtwdev, MAC_AX_ERR_ASSERTION); 1463 } else { 1464 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1465 "%d time firmware failed to ack for %s ps mode\n", 1466 i + 1, enter ? "entering" : "leaving"); 1467 } 1468 } 1469 } 1470 1471 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1472 { 1473 enum rtw89_rpwm_req_pwr_state state; 1474 1475 state = rtw89_mac_get_req_pwr_state(rtwdev); 1476 rtw89_mac_send_rpwm(rtwdev, state, true); 1477 } 1478 1479 static void rtw89_mac_power_switch_boot_mode(struct rtw89_dev *rtwdev) 1480 { 1481 u32 boot_mode; 1482 1483 if (rtwdev->hci.type != RTW89_HCI_TYPE_USB) 1484 return; 1485 1486 boot_mode = rtw89_read32_mask(rtwdev, R_AX_GPIO_MUXCFG, B_AX_BOOT_MODE); 1487 if (!boot_mode) 1488 return; 1489 1490 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 1491 rtw89_write32_clr(rtwdev, R_AX_SYS_STATUS1, B_AX_AUTO_WLPON); 1492 rtw89_write32_clr(rtwdev, R_AX_GPIO_MUXCFG, B_AX_BOOT_MODE); 1493 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); 1494 } 1495 1496 static int rtw89_mac_pwr_off_func_for_unplugged(struct rtw89_dev *rtwdev) 1497 { 1498 /* 1499 * Avoid accessing IO for unplugged power-off to prevent warnings, 1500 * especially XTAL SI. 1501 */ 1502 return 0; 1503 } 1504 1505 static void rtw89_mac_update_scoreboard(struct rtw89_dev *rtwdev, u8 val) 1506 { 1507 const struct rtw89_chip_info *chip = rtwdev->chip; 1508 u32 reg; 1509 int i; 1510 1511 for (i = 0; i < ARRAY_SIZE(chip->btc_sb.n); i++) { 1512 reg = chip->btc_sb.n[i].cfg; 1513 if (!reg) 1514 continue; 1515 1516 rtw89_write8(rtwdev, reg + 3, val); 1517 } 1518 } 1519 1520 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1521 { 1522 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1523 const struct rtw89_chip_info *chip = rtwdev->chip; 1524 const struct rtw89_pwr_cfg * const *cfg_seq; 1525 int (*cfg_func)(struct rtw89_dev *rtwdev); 1526 int ret; 1527 1528 rtw89_mac_power_switch_boot_mode(rtwdev); 1529 1530 if (on) { 1531 cfg_seq = chip->pwr_on_seq; 1532 cfg_func = chip->ops->pwr_on_func; 1533 } else { 1534 if (test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) { 1535 cfg_seq = NULL; 1536 cfg_func = rtw89_mac_pwr_off_func_for_unplugged; 1537 } else { 1538 cfg_seq = chip->pwr_off_seq; 1539 cfg_func = chip->ops->pwr_off_func; 1540 } 1541 } 1542 1543 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1544 __rtw89_leave_ps_mode(rtwdev); 1545 1546 if (on) { 1547 ret = mac->reset_pwr_state(rtwdev); 1548 if (ret) 1549 return ret; 1550 } 1551 1552 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1553 if (ret) 1554 return ret; 1555 1556 if (on) { 1557 if (!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags)) { 1558 rtw89_mac_efuse_read_ecv(rtwdev); 1559 mac->efuse_read_fw_secure(rtwdev); 1560 } 1561 1562 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1563 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1564 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1565 1566 rtw89_mac_update_scoreboard(rtwdev, MAC_AX_NOTIFY_TP_MAJOR); 1567 rtw89_mac_clr_aon_intr(rtwdev); 1568 } else { 1569 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1570 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1571 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1572 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1573 clear_bit(RTW89_FLAG_CMAC0_PWR, rtwdev->flags); 1574 clear_bit(RTW89_FLAG_CMAC1_PWR, rtwdev->flags); 1575 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1576 1577 rtw89_mac_update_scoreboard(rtwdev, MAC_AX_NOTIFY_PWR_MAJOR); 1578 rtw89_set_entity_state(rtwdev, RTW89_PHY_0, false); 1579 rtw89_set_entity_state(rtwdev, RTW89_PHY_1, false); 1580 } 1581 1582 return 0; 1583 } 1584 1585 int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev) 1586 { 1587 int ret; 1588 1589 ret = rtw89_mac_power_switch(rtwdev, true); 1590 if (ret) { 1591 rtw89_mac_power_switch(rtwdev, false); 1592 ret = rtw89_mac_power_switch(rtwdev, true); 1593 if (ret) 1594 return ret; 1595 } 1596 1597 return 0; 1598 } 1599 1600 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1601 { 1602 rtw89_mac_power_switch(rtwdev, false); 1603 } 1604 1605 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1606 { 1607 u32 func_en = 0; 1608 u32 ck_en = 0; 1609 u32 c1pc_en = 0; 1610 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1611 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1612 1613 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1614 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1615 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1616 B_AX_CMAC_CRPRT; 1617 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1618 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1619 B_AX_RMAC_CKEN; 1620 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1621 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1622 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1623 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1624 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1625 1626 if (en) { 1627 if (mac_idx == RTW89_MAC_1) { 1628 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1629 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1630 B_AX_R_SYM_ISO_CMAC12PP); 1631 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1632 B_AX_CMAC1_FEN); 1633 } 1634 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1635 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1636 } else { 1637 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1638 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1639 if (mac_idx == RTW89_MAC_1) { 1640 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1641 B_AX_CMAC1_FEN); 1642 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1643 B_AX_R_SYM_ISO_CMAC12PP); 1644 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1645 } 1646 } 1647 1648 return 0; 1649 } 1650 1651 static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1652 { 1653 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1654 u32 val32; 1655 1656 if (chip_id == RTL8852C) 1657 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1658 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1659 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1660 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1661 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1662 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1663 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1664 else 1665 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1666 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1667 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1668 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1669 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1670 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1671 B_AX_DMAC_CRPRT); 1672 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1673 1674 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1675 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1676 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1677 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1678 if (chip_id == RTL8852BT) 1679 val32 |= B_AX_AXIDMA_CLK_EN; 1680 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1681 1682 return 0; 1683 } 1684 1685 static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1686 { 1687 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1688 1689 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 1690 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1691 B_AX_OCP_L1_MASK); 1692 1693 return 0; 1694 } 1695 1696 static int sys_init_ax(struct rtw89_dev *rtwdev) 1697 { 1698 int ret; 1699 1700 ret = dmac_func_en_ax(rtwdev); 1701 if (ret) 1702 return ret; 1703 1704 ret = cmac_func_en_ax(rtwdev, 0, true); 1705 if (ret) 1706 return ret; 1707 1708 ret = chip_func_en_ax(rtwdev); 1709 if (ret) 1710 return ret; 1711 1712 return ret; 1713 } 1714 1715 const struct rtw89_mac_size_set rtw89_mac_size = { 1716 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1717 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0, 2, 32, 0, 0}, 1718 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0, 0, 256, 0, 0}, 1719 /* PCIE 64 */ 1720 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1721 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1722 /* 8852A USB */ 1723 .wde_size1 = {RTW89_WDE_PG_64, 768, 0,}, 1724 /* DLFW */ 1725 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1726 .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1727 /* PCIE 64 */ 1728 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1729 /* 8852B PCIE SCC */ 1730 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1731 /* DLFW */ 1732 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1733 .wde_size16_v1 = {RTW89_WDE_PG_64, 639, 1, 0,}, 1734 /* 8852C USB3.0 */ 1735 .wde_size17 = {RTW89_WDE_PG_64, 354, 30,}, 1736 /* 8852C DLFW */ 1737 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1738 .wde_size18_v1 = {RTW89_WDE_PG_64, 0, 640, 0,}, 1739 /* 8852C PCIE SCC */ 1740 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1741 .wde_size23 = {RTW89_WDE_PG_64, 1022, 2,}, 1742 /* 8852B USB2.0/USB3.0 SCC turbo */ 1743 .wde_size30 = {RTW89_WDE_PG_64, 220, 36,}, 1744 /* 8852C USB2.0 */ 1745 .wde_size31 = {RTW89_WDE_PG_64, 384, 0,}, 1746 /* PCIE */ 1747 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1748 .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1749 /* 8852A USB */ 1750 .ple_size1 = {RTW89_PLE_PG_128, 3184, 16,}, 1751 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1752 /* DLFW */ 1753 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1754 /* PCIE 64 */ 1755 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1756 /* DLFW */ 1757 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1758 .ple_size9 = {RTW89_PLE_PG_128, 2288, 16,}, 1759 /* 8852C USB */ 1760 .ple_size17 = {RTW89_PLE_PG_128, 3368, 24,}, 1761 /* 8852C DLFW */ 1762 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1763 /* 8852C PCIE SCC */ 1764 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1765 .ple_size20_v1 = {RTW89_PLE_PG_128, 2554, 182, 40960,}, 1766 .ple_size22_v1 = {RTW89_PLE_PG_128, 2736, 0, 40960,}, 1767 /* 8851B USB2.0 SCC turbo */ 1768 .ple_size27 = {RTW89_PLE_PG_128, 1396, 12,}, 1769 /* 8852B USB3.0 SCC turbo */ 1770 .ple_size31 = {RTW89_PLE_PG_128, 1392, 16,}, 1771 /* 8852C USB2.0 */ 1772 .ple_size34 = {RTW89_PLE_PG_128, 3374, 18,}, 1773 /* PCIE 64 */ 1774 .wde_qt0 = {3792, 196, 0, 107,}, 1775 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1776 /* 8852A USB */ 1777 .wde_qt1 = {512, 196, 0, 60,}, 1778 .wde_qt3 = {0, 0, 0, 0,}, 1779 /* DLFW */ 1780 .wde_qt4 = {0, 0, 0, 0,}, 1781 /* PCIE 64 */ 1782 .wde_qt6 = {448, 48, 0, 16,}, 1783 /* 8852B PCIE SCC */ 1784 .wde_qt7 = {446, 48, 0, 16,}, 1785 /* 8852C USB3.0 */ 1786 .wde_qt16 = {344, 2, 0, 8,}, 1787 /* 8852C DLFW */ 1788 .wde_qt17 = {0, 0, 0, 0,}, 1789 /* 8852C PCIE SCC */ 1790 .wde_qt18 = {3228, 60, 0, 40,}, 1791 .wde_qt19_v1 = {613, 6, 0, 20,}, 1792 .wde_qt23 = {958, 48, 0, 16,}, 1793 /* 8852B USB2.0/USB3.0 SCC turbo */ 1794 .wde_qt30 = {210, 2, 0, 8,}, 1795 /* 8852C USB2.0 */ 1796 .wde_qt31 = {338, 6, 0, 40,}, 1797 .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 1798 .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1799 /* PCIE SCC */ 1800 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1801 /* PCIE SCC */ 1802 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1803 .ple_qt5_v2 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,}, 1804 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1805 /* DLFW */ 1806 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1807 /* PCIE 64 */ 1808 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1809 /* 8852A USB SCC */ 1810 .ple_qt25 = {1536, 0, 16, 48, 13, 13, 360, 0, 32, 40, 8, 0,}, 1811 .ple_qt26 = {2654, 0, 1134, 48, 64, 13, 1478, 0, 64, 128, 120, 0,}, 1812 /* 8852B USB3.0 SCC turbo */ 1813 .ple_qt27 = {1040, 0, 16, 48, 13, 13, 178, 0, 32, 14, 8, 0,}, 1814 .ple_qt28 = {1040, 0, 32, 48, 43, 13, 208, 0, 62, 14, 24, 0,}, 1815 /* USB 52C USB3.0 */ 1816 .ple_qt42 = {1068, 0, 16, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,}, 1817 .ple_qt42_v2 = {91, 91, 32, 16, 19, 13, 91, 91, 44, 18, 1, 4, 0, 0,}, 1818 /* USB 52C USB3.0 */ 1819 .ple_qt43 = {3068, 0, 32, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,}, 1820 .ple_qt43_v2 = {645, 645, 32, 16, 2062, 2056, 2134, 2134, 2087, 2061, 1, 2047, 0, 0,}, 1821 /* DLFW 52C */ 1822 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1823 /* DLFW 52C */ 1824 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1825 /* 8852C PCIE SCC */ 1826 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1827 /* 8852C PCIE SCC */ 1828 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1829 .ple_qt57 = {147, 0, 16, 20, 13, 13, 178, 0, 32, 14, 8, 0,}, 1830 /* PCIE 64 */ 1831 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1832 .ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,}, 1833 /* 8851B USB2.0 SCC turbo */ 1834 .ple_qt61 = {858, 0, 16, 48, 4, 13, 370, 0, 32, 14, 8, 0, 0,}, 1835 .ple_qt62 = {858, 0, 32, 48, 37, 13, 403, 0, 65, 14, 24, 0, 0,}, 1836 /* USB2.0 52C */ 1837 .ple_qt78 = {1560, 0, 16, 48, 13, 13, 390, 0, 32, 38, 8, 16, 0,}, 1838 /* USB2.0 52C */ 1839 .ple_qt79 = {1560, 0, 32, 48, 1253, 13, 1630, 0, 1272, 38, 120, 1256, 0,}, 1840 /* 8852A PCIE WOW */ 1841 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1842 /* 8852B PCIE WOW */ 1843 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1844 /* 8852BT PCIE WOW */ 1845 .ple_qt_52bt_wow = {147, 0, 32, 20, 1860, 13, 1929, 0, 1879, 14, 24, 0,}, 1846 /* 8851B PCIE WOW */ 1847 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1848 .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1849 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1850 .ple_rsvd_qt9 = {1, 44, 44, 6, 6, 6, 6, 69, 0, 0,}, 1851 .rsvd0_size0 = {212992, 0,}, 1852 .rsvd0_size6 = {40960, 0,}, 1853 .rsvd1_size0 = {587776, 2048,}, 1854 .rsvd1_size2 = {391168, 2048,}, 1855 .dle_input3 = {0, 0, 0, 16384, 0, 2048, 0, 0,}, 1856 .dle_input18 = {128, 128, 11454, 2048, 0, 2048, 24, 24,}, 1857 }; 1858 EXPORT_SYMBOL(rtw89_mac_size); 1859 1860 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1861 enum rtw89_qta_mode mode) 1862 { 1863 struct rtw89_mac_info *mac = &rtwdev->mac; 1864 const struct rtw89_dle_mem *cfg, *cfgs; 1865 1866 cfgs = rtwdev->chip->dle_mem[rtwdev->hci.dle_type]; 1867 if (!cfgs) 1868 return NULL; 1869 1870 cfg = &cfgs[mode]; 1871 if (cfg->mode != mode) { 1872 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1873 return NULL; 1874 } 1875 1876 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1877 mac->dle_info.dle_input = cfg->dle_input; 1878 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1879 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1880 mac->dle_info.qta_mode = mode; 1881 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1882 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1883 1884 return cfg; 1885 } 1886 1887 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1888 enum rtw89_mac_dle_rsvd_qt_type type, 1889 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1890 { 1891 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1892 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1893 1894 switch (type) { 1895 case DLE_RSVD_QT_MPDU_INFO: 1896 cfg->pktid = dle_info->ple_free_pg; 1897 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1898 break; 1899 case DLE_RSVD_QT_B0_CSI: 1900 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1901 cfg->pg_num = rsvd_qt->b0_csi; 1902 break; 1903 case DLE_RSVD_QT_B1_CSI: 1904 cfg->pktid = dle_info->ple_free_pg + 1905 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1906 cfg->pg_num = rsvd_qt->b1_csi; 1907 break; 1908 case DLE_RSVD_QT_B0_LMR: 1909 cfg->pktid = dle_info->ple_free_pg + 1910 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1911 cfg->pg_num = rsvd_qt->b0_lmr; 1912 break; 1913 case DLE_RSVD_QT_B1_LMR: 1914 cfg->pktid = dle_info->ple_free_pg + 1915 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1916 rsvd_qt->b0_lmr; 1917 cfg->pg_num = rsvd_qt->b1_lmr; 1918 break; 1919 case DLE_RSVD_QT_B0_FTM: 1920 cfg->pktid = dle_info->ple_free_pg + 1921 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1922 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1923 cfg->pg_num = rsvd_qt->b0_ftm; 1924 break; 1925 case DLE_RSVD_QT_B1_FTM: 1926 cfg->pktid = dle_info->ple_free_pg + 1927 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1928 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1929 cfg->pg_num = rsvd_qt->b1_ftm; 1930 break; 1931 default: 1932 return -EINVAL; 1933 } 1934 1935 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1936 1937 return 0; 1938 } 1939 1940 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1941 { 1942 struct rtw89_mac_dle_dfi_qempty qempty; 1943 u32 grpnum, qtmp, val32, msk32; 1944 int i, j, ret; 1945 1946 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1947 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1948 1949 for (i = 0; i < grpnum; i++) { 1950 qempty.grpsel = i; 1951 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1952 if (ret) { 1953 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1954 return false; 1955 } 1956 qtmp = qempty.qempty; 1957 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1958 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 1959 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1960 return false; 1961 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1962 } 1963 } 1964 1965 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1966 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1967 if (ret) { 1968 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1969 return false; 1970 } 1971 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1972 if ((qempty.qempty & msk32) != msk32) 1973 return false; 1974 1975 if (rtwdev->dbcc_en) { 1976 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1977 if ((qempty.qempty & msk32) != msk32) 1978 return false; 1979 } 1980 1981 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1982 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1983 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1984 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1985 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1986 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1987 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1988 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1989 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1990 1991 return (val32 & msk32) == msk32; 1992 } 1993 1994 static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1995 { 1996 const struct rtw89_dle_size *wde = cfg->wde_size; 1997 const struct rtw89_dle_size *ple = cfg->ple_size; 1998 u32 used; 1999 2000 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 2001 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 2002 2003 if (cfg->rsvd0_size && cfg->rsvd1_size) { 2004 used += cfg->rsvd0_size->size; 2005 used += cfg->rsvd1_size->size; 2006 } 2007 2008 return used; 2009 } 2010 2011 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 2012 enum rtw89_qta_mode mode) 2013 { 2014 u32 size = rtwdev->chip->fifo_size; 2015 2016 if (mode == RTW89_QTA_SCC && rtwdev->hci.type != RTW89_HCI_TYPE_USB) 2017 size -= rtwdev->chip->dle_scc_rsvd_size; 2018 2019 return size; 2020 } 2021 2022 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 2023 { 2024 if (enable) 2025 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 2026 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 2027 else 2028 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 2029 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 2030 } 2031 2032 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 2033 { 2034 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 2035 2036 if (enable) { 2037 if (rtwdev->chip->chip_id == RTL8851B) 2038 val |= B_AX_AXIDMA_CLK_EN; 2039 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 2040 } else { 2041 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 2042 } 2043 } 2044 2045 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 2046 { 2047 const struct rtw89_dle_size *size_cfg; 2048 u32 val; 2049 u8 bound = 0; 2050 2051 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 2052 size_cfg = cfg->wde_size; 2053 2054 switch (size_cfg->pge_size) { 2055 default: 2056 case RTW89_WDE_PG_64: 2057 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 2058 B_AX_WDE_PAGE_SEL_MASK); 2059 break; 2060 case RTW89_WDE_PG_128: 2061 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 2062 B_AX_WDE_PAGE_SEL_MASK); 2063 break; 2064 case RTW89_WDE_PG_256: 2065 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 2066 return -EINVAL; 2067 } 2068 2069 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 2070 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 2071 B_AX_WDE_FREE_PAGE_NUM_MASK); 2072 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 2073 2074 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 2075 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 2076 * size_cfg->pge_size / DLE_BOUND_UNIT; 2077 size_cfg = cfg->ple_size; 2078 2079 switch (size_cfg->pge_size) { 2080 default: 2081 case RTW89_PLE_PG_64: 2082 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 2083 return -EINVAL; 2084 case RTW89_PLE_PG_128: 2085 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 2086 B_AX_PLE_PAGE_SEL_MASK); 2087 break; 2088 case RTW89_PLE_PG_256: 2089 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 2090 B_AX_PLE_PAGE_SEL_MASK); 2091 break; 2092 } 2093 2094 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 2095 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 2096 B_AX_PLE_FREE_PAGE_NUM_MASK); 2097 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 2098 2099 return 0; 2100 } 2101 2102 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 2103 { 2104 u32 reg, mask; 2105 u32 ini; 2106 2107 if (wde_or_ple) { 2108 reg = R_AX_WDE_INI_STATUS; 2109 mask = WDE_MGN_INI_RDY; 2110 } else { 2111 reg = R_AX_PLE_INI_STATUS; 2112 mask = PLE_MGN_INI_RDY; 2113 } 2114 2115 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 2116 2000, false, rtwdev, reg); 2117 } 2118 2119 #define INVALID_QT_WCPU U16_MAX 2120 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 2121 do { \ 2122 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 2123 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 2124 rtw89_write32(rtwdev, \ 2125 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 2126 val); \ 2127 } while (0) 2128 #define SET_QUOTA(_x, _module, _idx) \ 2129 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 2130 2131 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 2132 const struct rtw89_wde_quota *min_cfg, 2133 const struct rtw89_wde_quota *max_cfg, 2134 u16 ext_wde_min_qt_wcpu) 2135 { 2136 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 2137 ext_wde_min_qt_wcpu : min_cfg->wcpu; 2138 u32 val; 2139 2140 SET_QUOTA(hif, WDE, 0); 2141 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 2142 SET_QUOTA(pkt_in, WDE, 3); 2143 SET_QUOTA(cpu_io, WDE, 4); 2144 } 2145 2146 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 2147 const struct rtw89_ple_quota *min_cfg, 2148 const struct rtw89_ple_quota *max_cfg) 2149 { 2150 u32 val; 2151 2152 SET_QUOTA(cma0_tx, PLE, 0); 2153 SET_QUOTA(cma1_tx, PLE, 1); 2154 SET_QUOTA(c2h, PLE, 2); 2155 SET_QUOTA(h2c, PLE, 3); 2156 SET_QUOTA(wcpu, PLE, 4); 2157 SET_QUOTA(mpdu_proc, PLE, 5); 2158 SET_QUOTA(cma0_dma, PLE, 6); 2159 SET_QUOTA(cma1_dma, PLE, 7); 2160 SET_QUOTA(bb_rpt, PLE, 8); 2161 SET_QUOTA(wd_rel, PLE, 9); 2162 SET_QUOTA(cpu_io, PLE, 10); 2163 if (rtwdev->chip->chip_id == RTL8852C) 2164 SET_QUOTA(tx_rpt, PLE, 11); 2165 } 2166 2167 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 2168 { 2169 const struct rtw89_ple_quota *min_cfg, *max_cfg; 2170 const struct rtw89_dle_mem *cfg; 2171 u32 val; 2172 2173 if (rtwdev->chip->chip_id == RTL8852C) 2174 return 0; 2175 2176 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2177 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2178 return -EINVAL; 2179 } 2180 2181 if (wow) 2182 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2183 else 2184 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2185 if (!cfg) { 2186 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2187 return -EINVAL; 2188 } 2189 2190 min_cfg = cfg->ple_min_qt; 2191 max_cfg = cfg->ple_max_qt; 2192 SET_QUOTA(cma0_dma, PLE, 6); 2193 SET_QUOTA(cma1_dma, PLE, 7); 2194 2195 return 0; 2196 } 2197 #undef SET_QUOTA 2198 2199 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2200 { 2201 const struct rtw89_chip_info *chip = rtwdev->chip; 2202 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2203 2204 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2205 return; 2206 2207 /* 8852C enable B_AX_UC_MGNT_DEC by default */ 2208 if (chip->chip_id == RTL8852C) 2209 msk32 = B_AX_BMC_MGNT_DEC; 2210 2211 if (enable) 2212 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2213 else 2214 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2215 } 2216 2217 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2218 const struct rtw89_dle_mem *cfg, 2219 u16 ext_wde_min_qt_wcpu) 2220 { 2221 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2222 2223 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2224 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2225 } 2226 2227 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2228 enum rtw89_qta_mode ext_mode) 2229 { 2230 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2231 const struct rtw89_dle_mem *cfg, *ext_cfg; 2232 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2233 int ret; 2234 2235 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2236 if (ret) 2237 return ret; 2238 2239 cfg = get_dle_mem_cfg(rtwdev, mode); 2240 if (!cfg) { 2241 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2242 ret = -EINVAL; 2243 goto error; 2244 } 2245 2246 if (mode == RTW89_QTA_DLFW) { 2247 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2248 if (!ext_cfg) { 2249 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2250 ext_mode); 2251 ret = -EINVAL; 2252 goto error; 2253 } 2254 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2255 } 2256 2257 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2258 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2259 ret = -EINVAL; 2260 goto error; 2261 } 2262 2263 mac->dle_func_en(rtwdev, false); 2264 mac->dle_clk_en(rtwdev, true); 2265 2266 ret = mac->dle_mix_cfg(rtwdev, cfg); 2267 if (ret) { 2268 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2269 goto error; 2270 } 2271 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2272 2273 mac->dle_func_en(rtwdev, true); 2274 2275 ret = mac->chk_dle_rdy(rtwdev, true); 2276 if (ret) { 2277 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2278 return ret; 2279 } 2280 2281 ret = mac->chk_dle_rdy(rtwdev, false); 2282 if (ret) { 2283 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2284 return ret; 2285 } 2286 2287 return 0; 2288 error: 2289 mac->dle_func_en(rtwdev, false); 2290 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2291 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2292 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2293 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2294 2295 return ret; 2296 } 2297 2298 static int preload_init_set_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 2299 enum rtw89_qta_mode mode) 2300 { 2301 u32 reg, max_preld_size, min_rsvd_size; 2302 2303 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2304 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2305 reg = mac_idx == RTW89_MAC_0 ? 2306 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2307 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2308 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2309 2310 min_rsvd_size = PRELD_AMSDU_SIZE; 2311 reg = mac_idx == RTW89_MAC_0 ? 2312 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2313 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2314 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2315 2316 return 0; 2317 } 2318 2319 static bool is_qta_poh(struct rtw89_dev *rtwdev) 2320 { 2321 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2322 } 2323 2324 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2325 enum rtw89_qta_mode mode) 2326 { 2327 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2328 const struct rtw89_chip_info *chip = rtwdev->chip; 2329 2330 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) || 2331 !is_qta_poh(rtwdev)) 2332 return 0; 2333 2334 return mac->preload_init(rtwdev, mac_idx, mode); 2335 } 2336 2337 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2338 { 2339 u32 msk32; 2340 u32 val32; 2341 2342 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2343 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2344 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2345 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2346 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2347 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2348 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2349 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2350 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2351 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2352 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2353 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2354 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2355 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2356 2357 if ((val32 & msk32) == msk32) 2358 return true; 2359 2360 return false; 2361 } 2362 2363 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2364 { 2365 const struct rtw89_chip_info *chip = rtwdev->chip; 2366 2367 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2368 return; 2369 2370 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2371 SS2F_PATH_WLCPU); 2372 } 2373 2374 static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2375 { 2376 u32 p_val; 2377 u8 val; 2378 int ret; 2379 2380 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2381 if (ret) 2382 return ret; 2383 2384 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2385 val |= B_AX_SS_EN; 2386 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2387 2388 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2389 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2390 if (ret) { 2391 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2392 return ret; 2393 } 2394 2395 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2396 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2397 2398 _patch_ss2f_path(rtwdev); 2399 2400 return 0; 2401 } 2402 2403 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2404 { 2405 int ret; 2406 2407 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2408 if (ret) 2409 return ret; 2410 2411 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2412 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2413 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2414 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2415 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2416 2417 return 0; 2418 } 2419 2420 static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2421 { 2422 const struct rtw89_chip_info *chip = rtwdev->chip; 2423 u32 val = 0; 2424 int ret; 2425 2426 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2427 if (ret) 2428 return ret; 2429 2430 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2431 /* init clock */ 2432 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2433 /* init TX encryption */ 2434 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2435 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2436 if (chip->chip_id == RTL8852C) 2437 val |= B_AX_UC_MGNT_DEC; 2438 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2439 chip->chip_id == RTL8851B || 2440 (chip->chip_id == RTL8852C && rtwdev->hci.type == RTW89_HCI_TYPE_USB)) 2441 val &= ~B_AX_TX_PARTIAL_MODE; 2442 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2443 2444 /* init MIC ICV append */ 2445 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2446 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2447 2448 /* option init */ 2449 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2450 2451 if (chip->chip_id == RTL8852C) 2452 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2453 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2454 2455 return 0; 2456 } 2457 2458 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2459 { 2460 int ret; 2461 2462 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2463 if (ret) { 2464 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2465 return ret; 2466 } 2467 2468 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2469 if (ret) { 2470 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2471 return ret; 2472 } 2473 2474 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2475 if (ret) { 2476 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2477 return ret; 2478 } 2479 2480 ret = sta_sch_init_ax(rtwdev); 2481 if (ret) { 2482 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2483 return ret; 2484 } 2485 2486 ret = mpdu_proc_init_ax(rtwdev); 2487 if (ret) { 2488 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2489 return ret; 2490 } 2491 2492 ret = sec_eng_init_ax(rtwdev); 2493 if (ret) { 2494 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2495 return ret; 2496 } 2497 2498 return ret; 2499 } 2500 2501 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2502 { 2503 u32 val, reg; 2504 u16 p_val; 2505 int ret; 2506 2507 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2508 if (ret) 2509 return ret; 2510 2511 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2512 2513 val = rtw89_read32(rtwdev, reg); 2514 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2515 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2516 rtw89_write32(rtwdev, reg, val); 2517 2518 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2519 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2520 if (ret) { 2521 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2522 return ret; 2523 } 2524 2525 return 0; 2526 } 2527 2528 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2529 { 2530 int ret; 2531 u32 reg; 2532 u32 val; 2533 2534 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2535 if (ret) 2536 return ret; 2537 2538 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2539 if (rtwdev->chip->chip_id == RTL8852C) 2540 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2541 SIFS_MACTXEN_T1_V1); 2542 else 2543 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2544 SIFS_MACTXEN_T1); 2545 2546 if (rtw89_is_rtl885xb(rtwdev)) { 2547 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2548 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2549 } 2550 2551 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2552 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2553 2554 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2555 if (rtwdev->chip->chip_id == RTL8852C) { 2556 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2557 B_AX_TX_PARTIAL_MODE); 2558 if (!val) 2559 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2560 SCH_PREBKF_24US); 2561 } else { 2562 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2563 SCH_PREBKF_24US); 2564 } 2565 2566 return 0; 2567 } 2568 2569 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2570 enum rtw89_machdr_frame_type type, 2571 enum rtw89_mac_fwd_target fwd_target, 2572 u8 mac_idx) 2573 { 2574 u32 reg; 2575 u32 val; 2576 2577 switch (fwd_target) { 2578 case RTW89_FWD_DONT_CARE: 2579 val = RX_FLTR_FRAME_DROP; 2580 break; 2581 case RTW89_FWD_TO_HOST: 2582 val = RX_FLTR_FRAME_TO_HOST; 2583 break; 2584 case RTW89_FWD_TO_WLAN_CPU: 2585 val = RX_FLTR_FRAME_TO_WLCPU; 2586 break; 2587 default: 2588 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2589 return -EINVAL; 2590 } 2591 2592 switch (type) { 2593 case RTW89_MGNT: 2594 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2595 break; 2596 case RTW89_CTRL: 2597 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2598 break; 2599 case RTW89_DATA: 2600 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2601 break; 2602 default: 2603 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2604 return -EINVAL; 2605 } 2606 rtw89_write32(rtwdev, reg, val); 2607 2608 return 0; 2609 } 2610 2611 void rtw89_mac_set_rx_fltr(struct rtw89_dev *rtwdev, u8 mac_idx, u32 rx_fltr) 2612 { 2613 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2614 u32 reg; 2615 u32 val; 2616 2617 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, mac_idx); 2618 2619 val = rtw89_read32(rtwdev, reg); 2620 /* B_AX_RX_FLTR_CFG_MASK is not a consecutive bit mask */ 2621 val = (val & ~B_AX_RX_FLTR_CFG_MASK) | (rx_fltr & B_AX_RX_FLTR_CFG_MASK); 2622 rtw89_write32(rtwdev, reg, val); 2623 } 2624 2625 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2626 { 2627 int ret, i; 2628 u32 mac_ftlr, plcp_ftlr; 2629 2630 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2631 if (ret) 2632 return ret; 2633 2634 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2635 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2636 mac_idx); 2637 if (ret) 2638 return ret; 2639 } 2640 mac_ftlr = rtwdev->hal.rx_fltr; 2641 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2642 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2643 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2644 B_AX_HE_SIGB_CRC_CHK; 2645 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2646 mac_ftlr); 2647 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2648 plcp_ftlr); 2649 2650 return 0; 2651 } 2652 2653 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2654 { 2655 u32 reg, val32; 2656 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2657 2658 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2659 B_AX_RSP_CHK_BASIC_NAV; 2660 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2661 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2662 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2663 2664 switch (rtwdev->chip->chip_id) { 2665 case RTL8852A: 2666 case RTL8852B: 2667 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2668 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2669 rtw89_write32(rtwdev, reg, val32); 2670 2671 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2672 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2673 rtw89_write32(rtwdev, reg, val32); 2674 break; 2675 default: 2676 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2677 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2678 rtw89_write32(rtwdev, reg, val32); 2679 2680 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2681 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2682 rtw89_write32(rtwdev, reg, val32); 2683 break; 2684 } 2685 } 2686 2687 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2688 { 2689 u32 val, reg; 2690 int ret; 2691 2692 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2693 if (ret) 2694 return ret; 2695 2696 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2697 val = rtw89_read32(rtwdev, reg); 2698 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2699 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2700 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2701 B_AX_CTN_CHK_INTRA_NAV | 2702 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2703 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2704 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2705 B_AX_CTN_CHK_CCA_P20); 2706 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2707 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2708 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2709 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2710 B_AX_SIFS_CHK_EDCCA); 2711 2712 rtw89_write32(rtwdev, reg, val); 2713 2714 _patch_dis_resp_chk(rtwdev, mac_idx); 2715 2716 return 0; 2717 } 2718 2719 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2720 { 2721 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2722 B_AX_WMAC_TF_UP_NAV_EN | 2723 B_AX_WMAC_NAV_UPPER_EN); 2724 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2725 2726 return 0; 2727 } 2728 2729 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2730 { 2731 u32 reg; 2732 int ret; 2733 2734 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2735 if (ret) 2736 return ret; 2737 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2738 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2739 2740 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2741 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2742 2743 return 0; 2744 } 2745 2746 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2747 { 2748 u32 reg; 2749 int ret; 2750 2751 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2752 if (ret) 2753 return ret; 2754 2755 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2756 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2757 2758 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2759 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2760 2761 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2762 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2763 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2764 2765 return 0; 2766 } 2767 2768 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2769 { 2770 const struct rtw89_chip_info *chip = rtwdev->chip; 2771 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2772 u32 reg, val, sifs; 2773 int ret; 2774 2775 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2776 if (ret) 2777 return ret; 2778 2779 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2780 val = rtw89_read32(rtwdev, reg); 2781 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2782 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2783 2784 switch (rtwdev->chip->chip_id) { 2785 case RTL8852A: 2786 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2787 break; 2788 case RTL8851B: 2789 case RTL8852B: 2790 case RTL8852BT: 2791 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2792 break; 2793 default: 2794 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2795 break; 2796 } 2797 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2798 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2799 rtw89_write32(rtwdev, reg, val); 2800 2801 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2802 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2803 2804 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2805 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2806 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2807 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2808 2809 return 0; 2810 } 2811 2812 static void rst_bacam(struct rtw89_dev *rtwdev) 2813 { 2814 u32 val32; 2815 int ret; 2816 2817 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2818 S_AX_BACAM_RST_ALL); 2819 2820 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2821 1, 1000, false, 2822 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2823 if (ret) 2824 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2825 } 2826 2827 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2828 { 2829 #define TRXCFG_RMAC_CCA_TO 32 2830 #define TRXCFG_RMAC_DATA_TO 15 2831 #define RX_MAX_LEN_UNIT 512 2832 #define PLD_RLS_MAX_PG 127 2833 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2834 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2835 int ret; 2836 u32 reg, rx_max_len, rx_qta; 2837 u16 val; 2838 2839 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2840 if (ret) 2841 return ret; 2842 2843 if (mac_idx == RTW89_MAC_0) 2844 rst_bacam(rtwdev); 2845 2846 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2847 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2848 2849 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2850 val = rtw89_read16(rtwdev, reg); 2851 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2852 B_AX_RX_DLK_DATA_TIME_MASK); 2853 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2854 B_AX_RX_DLK_CCA_TIME_MASK); 2855 if (chip_id == RTL8852BT) 2856 val |= B_AX_RX_DLK_RST_EN; 2857 rtw89_write16(rtwdev, reg, val); 2858 2859 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2860 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2861 2862 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2863 if (mac_idx == RTW89_MAC_0) 2864 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2865 else 2866 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2867 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2868 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2869 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2870 rx_max_len /= RX_MAX_LEN_UNIT; 2871 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2872 2873 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) { 2874 rtw89_write16_mask(rtwdev, 2875 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2876 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2877 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2878 BIT(12)); 2879 } 2880 2881 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2882 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2883 2884 return ret; 2885 } 2886 2887 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2888 { 2889 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2890 u32 val, reg; 2891 int ret; 2892 2893 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2894 if (ret) 2895 return ret; 2896 2897 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2898 val = rtw89_read32(rtwdev, reg); 2899 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2900 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2901 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2902 rtw89_write32(rtwdev, reg, val); 2903 2904 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2905 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2906 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2907 } 2908 2909 return 0; 2910 } 2911 2912 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2913 { 2914 const struct rtw89_dle_mem *cfg; 2915 2916 cfg = get_dle_mem_cfg(rtwdev, mode); 2917 if (!cfg) { 2918 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2919 return false; 2920 } 2921 2922 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2923 } 2924 2925 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2926 { 2927 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2928 u32 val, reg; 2929 int ret; 2930 2931 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2932 if (ret) 2933 return ret; 2934 2935 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2936 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2937 val = rtw89_read32(rtwdev, reg); 2938 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2939 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2940 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2941 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2942 val |= B_AX_HW_CTS2SELF_EN; 2943 rtw89_write32(rtwdev, reg, val); 2944 2945 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2946 val = rtw89_read32(rtwdev, reg); 2947 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2948 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2949 rtw89_write32(rtwdev, reg, val); 2950 } 2951 2952 if (mac_idx == RTW89_MAC_0) { 2953 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2954 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2955 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2956 B_AX_PTCL_TRIGGER_SS_EN_0 | 2957 B_AX_PTCL_TRIGGER_SS_EN_1 | 2958 B_AX_PTCL_TRIGGER_SS_EN_UL); 2959 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2960 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2961 } else if (mac_idx == RTW89_MAC_1) { 2962 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2963 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2964 } 2965 2966 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2967 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_VHT_0, mac_idx); 2968 rtw89_write32_mask(rtwdev, reg, 2969 B_AX_AMPDU_MAX_LEN_VHT_MASK, 0x3FF80); 2970 } 2971 2972 return 0; 2973 } 2974 2975 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2976 { 2977 u32 reg; 2978 int ret; 2979 2980 if (!rtw89_is_rtl885xb(rtwdev)) 2981 return 0; 2982 2983 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2984 if (ret) 2985 return ret; 2986 2987 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2988 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2989 2990 return 0; 2991 } 2992 2993 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2994 { 2995 int ret; 2996 2997 ret = scheduler_init_ax(rtwdev, mac_idx); 2998 if (ret) { 2999 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 3000 return ret; 3001 } 3002 3003 ret = addr_cam_init_ax(rtwdev, mac_idx); 3004 if (ret) { 3005 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 3006 ret); 3007 return ret; 3008 } 3009 3010 ret = rx_fltr_init_ax(rtwdev, mac_idx); 3011 if (ret) { 3012 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 3013 ret); 3014 return ret; 3015 } 3016 3017 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 3018 if (ret) { 3019 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 3020 ret); 3021 return ret; 3022 } 3023 3024 ret = nav_ctrl_init_ax(rtwdev); 3025 if (ret) { 3026 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 3027 ret); 3028 return ret; 3029 } 3030 3031 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 3032 if (ret) { 3033 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 3034 mac_idx, ret); 3035 return ret; 3036 } 3037 3038 ret = tmac_init_ax(rtwdev, mac_idx); 3039 if (ret) { 3040 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 3041 return ret; 3042 } 3043 3044 ret = trxptcl_init_ax(rtwdev, mac_idx); 3045 if (ret) { 3046 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 3047 return ret; 3048 } 3049 3050 ret = rmac_init_ax(rtwdev, mac_idx); 3051 if (ret) { 3052 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 3053 return ret; 3054 } 3055 3056 ret = cmac_com_init_ax(rtwdev, mac_idx); 3057 if (ret) { 3058 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 3059 return ret; 3060 } 3061 3062 ret = ptcl_init_ax(rtwdev, mac_idx); 3063 if (ret) { 3064 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 3065 return ret; 3066 } 3067 3068 ret = cmac_dma_init_ax(rtwdev, mac_idx); 3069 if (ret) { 3070 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 3071 return ret; 3072 } 3073 3074 return ret; 3075 } 3076 3077 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 3078 struct rtw89_mac_c2h_info *c2h_info, u8 part_num) 3079 { 3080 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3081 const struct rtw89_chip_info *chip = rtwdev->chip; 3082 struct rtw89_mac_h2c_info h2c_info = {}; 3083 enum rtw89_mac_c2h_type c2h_type; 3084 u8 content_len; 3085 int ret; 3086 3087 if (chip->chip_gen == RTW89_CHIP_AX) 3088 content_len = 0; 3089 else 3090 content_len = 2; 3091 3092 switch (part_num) { 3093 case 0: 3094 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP; 3095 break; 3096 case 1: 3097 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1; 3098 break; 3099 default: 3100 return -EINVAL; 3101 } 3102 3103 mac->cnv_efuse_state(rtwdev, false); 3104 3105 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 3106 h2c_info.content_len = content_len; 3107 h2c_info.u.hdr.w0 = u32_encode_bits(part_num, RTW89_H2CREG_GET_FEATURE_PART_NUM); 3108 3109 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 3110 if (ret) 3111 goto out; 3112 3113 if (c2h_info->id != c2h_type) 3114 ret = -EINVAL; 3115 3116 out: 3117 mac->cnv_efuse_state(rtwdev, true); 3118 3119 return ret; 3120 } 3121 3122 static int rtw89_mac_setup_phycap_part0(struct rtw89_dev *rtwdev) 3123 { 3124 const struct rtw89_chip_info *chip = rtwdev->chip; 3125 const struct rtw89_c2hreg_phycap *phycap; 3126 struct rtw89_efuse *efuse = &rtwdev->efuse; 3127 struct rtw89_mac_c2h_info c2h_info = {}; 3128 struct rtw89_hal *hal = &rtwdev->hal; 3129 u8 protocol; 3130 u8 tx_nss; 3131 u8 rx_nss; 3132 u8 tx_ant; 3133 u8 rx_ant; 3134 int ret; 3135 3136 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 0); 3137 if (ret) 3138 return ret; 3139 3140 phycap = &c2h_info.u.phycap; 3141 3142 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 3143 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 3144 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 3145 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 3146 3147 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 3148 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 3149 3150 if (tx_ant == 1) 3151 hal->antenna_tx = RF_B; 3152 if (rx_ant == 1) 3153 hal->antenna_rx = RF_B; 3154 3155 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 3156 hal->antenna_tx = RF_B; 3157 hal->tx_path_diversity = true; 3158 } 3159 3160 if (chip->rf_path_num == 1) { 3161 hal->antenna_tx = RF_A; 3162 hal->antenna_rx = RF_A; 3163 if ((efuse->rfe_type % 3) == 2) 3164 hal->ant_diversity = true; 3165 } 3166 3167 rtw89_debug(rtwdev, RTW89_DBG_FW, 3168 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 3169 hal->tx_nss, tx_nss, chip->tx_nss, 3170 hal->rx_nss, rx_nss, chip->rx_nss); 3171 rtw89_debug(rtwdev, RTW89_DBG_FW, 3172 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 3173 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 3174 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 3175 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 3176 3177 protocol = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_PROT); 3178 if (protocol < RTW89_C2HREG_PHYCAP_W1_PROT_11BE) 3179 hal->no_eht = true; 3180 3181 return 0; 3182 } 3183 3184 static int rtw89_mac_setup_phycap_part1(struct rtw89_dev *rtwdev) 3185 { 3186 const struct rtw89_chip_variant *variant = rtwdev->variant; 3187 const struct rtw89_c2hreg_phycap *phycap; 3188 struct rtw89_mac_c2h_info c2h_info = {}; 3189 struct rtw89_hal *hal = &rtwdev->hal; 3190 u8 qam_raw, qam; 3191 int ret; 3192 3193 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 1); 3194 if (ret) 3195 return ret; 3196 3197 phycap = &c2h_info.u.phycap; 3198 3199 qam_raw = u32_get_bits(phycap->w2, RTW89_C2HREG_PHYCAP_P1_W2_QAM); 3200 3201 switch (qam_raw) { 3202 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_256: 3203 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024: 3204 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096: 3205 qam = qam_raw; 3206 break; 3207 default: 3208 qam = RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096; 3209 break; 3210 } 3211 3212 if ((variant && variant->no_mcs_12_13) || 3213 qam <= RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024) 3214 hal->no_mcs_12_13 = true; 3215 3216 rtw89_debug(rtwdev, RTW89_DBG_FW, "phycap qam=%d/%d no_mcs_12_13=%d\n", 3217 qam_raw, qam, hal->no_mcs_12_13); 3218 3219 return 0; 3220 } 3221 3222 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 3223 { 3224 const struct rtw89_chip_info *chip = rtwdev->chip; 3225 int ret; 3226 3227 ret = rtw89_mac_setup_phycap_part0(rtwdev); 3228 if (ret) 3229 return ret; 3230 3231 if (chip->chip_gen == RTW89_CHIP_AX || 3232 RTW89_CHK_FW_FEATURE(NO_PHYCAP_P1, &rtwdev->fw)) 3233 return 0; 3234 3235 return rtw89_mac_setup_phycap_part1(rtwdev); 3236 } 3237 3238 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 3239 u16 tx_en_u16, u16 mask_u16) 3240 { 3241 struct rtw89_mac_c2h_info c2h_info = {0}; 3242 struct rtw89_mac_h2c_info h2c_info = {0}; 3243 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 3244 int ret; 3245 3246 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 3247 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 3248 3249 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 3250 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 3251 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 3252 3253 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 3254 if (ret) 3255 return ret; 3256 3257 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 3258 return -EINVAL; 3259 3260 return 0; 3261 } 3262 3263 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 3264 u16 tx_en, u16 tx_en_mask) 3265 { 3266 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 3267 u16 val; 3268 int ret; 3269 3270 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3271 if (ret) 3272 return ret; 3273 3274 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3275 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 3276 tx_en, tx_en_mask); 3277 3278 val = rtw89_read16(rtwdev, reg); 3279 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3280 rtw89_write16(rtwdev, reg, val); 3281 3282 return 0; 3283 } 3284 3285 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3286 u32 tx_en, u32 tx_en_mask) 3287 { 3288 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3289 u32 val; 3290 int ret; 3291 3292 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3293 if (ret) 3294 return ret; 3295 3296 val = rtw89_read32(rtwdev, reg); 3297 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3298 rtw89_write32(rtwdev, reg, val); 3299 3300 return 0; 3301 } 3302 3303 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3304 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3305 { 3306 int ret; 3307 3308 *tx_en = rtw89_read16(rtwdev, 3309 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3310 3311 switch (sel) { 3312 case RTW89_SCH_TX_SEL_ALL: 3313 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3314 B_AX_CTN_TXEN_ALL_MASK); 3315 if (ret) 3316 return ret; 3317 break; 3318 case RTW89_SCH_TX_SEL_HIQ: 3319 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3320 0, B_AX_CTN_TXEN_HGQ); 3321 if (ret) 3322 return ret; 3323 break; 3324 case RTW89_SCH_TX_SEL_MG0: 3325 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3326 0, B_AX_CTN_TXEN_MGQ); 3327 if (ret) 3328 return ret; 3329 break; 3330 case RTW89_SCH_TX_SEL_MACID: 3331 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3332 B_AX_CTN_TXEN_ALL_MASK); 3333 if (ret) 3334 return ret; 3335 break; 3336 default: 3337 return 0; 3338 } 3339 3340 return 0; 3341 } 3342 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3343 3344 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3345 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3346 { 3347 int ret; 3348 3349 *tx_en = rtw89_read32(rtwdev, 3350 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3351 3352 switch (sel) { 3353 case RTW89_SCH_TX_SEL_ALL: 3354 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3355 B_AX_CTN_TXEN_ALL_MASK_V1); 3356 if (ret) 3357 return ret; 3358 break; 3359 case RTW89_SCH_TX_SEL_HIQ: 3360 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3361 0, B_AX_CTN_TXEN_HGQ); 3362 if (ret) 3363 return ret; 3364 break; 3365 case RTW89_SCH_TX_SEL_MG0: 3366 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3367 0, B_AX_CTN_TXEN_MGQ); 3368 if (ret) 3369 return ret; 3370 break; 3371 case RTW89_SCH_TX_SEL_MACID: 3372 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3373 B_AX_CTN_TXEN_ALL_MASK_V1); 3374 if (ret) 3375 return ret; 3376 break; 3377 default: 3378 return 0; 3379 } 3380 3381 return 0; 3382 } 3383 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3384 3385 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3386 { 3387 int ret; 3388 3389 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3390 if (ret) 3391 return ret; 3392 3393 return 0; 3394 } 3395 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3396 3397 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3398 { 3399 int ret; 3400 3401 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3402 B_AX_CTN_TXEN_ALL_MASK_V1); 3403 if (ret) 3404 return ret; 3405 3406 return 0; 3407 } 3408 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3409 3410 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3411 { 3412 u32 val, reg; 3413 int ret; 3414 3415 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3416 val = buf_len; 3417 val |= B_AX_WD_BUF_REQ_EXEC; 3418 rtw89_write32(rtwdev, reg, val); 3419 3420 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3421 3422 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3423 1, 2000, false, rtwdev, reg); 3424 if (ret) 3425 return ret; 3426 3427 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3428 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3429 return -ENOENT; 3430 3431 return 0; 3432 } 3433 3434 static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3435 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3436 { 3437 u32 val, cmd_type, reg; 3438 int ret; 3439 3440 cmd_type = ctrl_para->cmd_type; 3441 3442 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3443 val = 0; 3444 val = u32_replace_bits(val, ctrl_para->start_pktid, 3445 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3446 val = u32_replace_bits(val, ctrl_para->end_pktid, 3447 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3448 rtw89_write32(rtwdev, reg, val); 3449 3450 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3451 val = 0; 3452 val = u32_replace_bits(val, ctrl_para->src_pid, 3453 B_AX_CPUQ_OP_SRC_PID_MASK); 3454 val = u32_replace_bits(val, ctrl_para->src_qid, 3455 B_AX_CPUQ_OP_SRC_QID_MASK); 3456 val = u32_replace_bits(val, ctrl_para->dst_pid, 3457 B_AX_CPUQ_OP_DST_PID_MASK); 3458 val = u32_replace_bits(val, ctrl_para->dst_qid, 3459 B_AX_CPUQ_OP_DST_QID_MASK); 3460 rtw89_write32(rtwdev, reg, val); 3461 3462 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3463 val = 0; 3464 val = u32_replace_bits(val, cmd_type, 3465 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3466 val = u32_replace_bits(val, ctrl_para->macid, 3467 B_AX_CPUQ_OP_MACID_MASK); 3468 val = u32_replace_bits(val, ctrl_para->pkt_num, 3469 B_AX_CPUQ_OP_PKTNUM_MASK); 3470 val |= B_AX_WD_CPUQ_OP_EXEC; 3471 rtw89_write32(rtwdev, reg, val); 3472 3473 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3474 3475 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3476 1, 2000, false, rtwdev, reg); 3477 if (ret) 3478 return ret; 3479 3480 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3481 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3482 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3483 3484 return 0; 3485 } 3486 3487 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3488 bool band1_en) 3489 { 3490 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3491 const struct rtw89_dle_mem *cfg; 3492 3493 cfg = get_dle_mem_cfg(rtwdev, mode); 3494 if (!cfg) { 3495 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3496 return -EINVAL; 3497 } 3498 3499 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3500 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3501 return -EINVAL; 3502 } 3503 3504 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3505 3506 return mac->dle_quota_change(rtwdev, band1_en); 3507 } 3508 3509 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3510 { 3511 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3512 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3513 u16 pkt_id; 3514 int ret; 3515 3516 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3517 if (ret) { 3518 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3519 return ret; 3520 } 3521 3522 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3523 ctrl_para.start_pktid = pkt_id; 3524 ctrl_para.end_pktid = pkt_id; 3525 ctrl_para.pkt_num = 0; 3526 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3527 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3528 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3529 if (ret) { 3530 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3531 return -EFAULT; 3532 } 3533 3534 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3535 if (ret) { 3536 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3537 return ret; 3538 } 3539 3540 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3541 ctrl_para.start_pktid = pkt_id; 3542 ctrl_para.end_pktid = pkt_id; 3543 ctrl_para.pkt_num = 0; 3544 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3545 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3546 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3547 if (ret) { 3548 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3549 return -EFAULT; 3550 } 3551 3552 return 0; 3553 } 3554 3555 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3556 { 3557 int ret; 3558 u32 reg; 3559 u8 val; 3560 3561 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3562 if (ret) 3563 return ret; 3564 3565 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3566 3567 ret = read_poll_timeout(rtw89_read8, val, 3568 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3569 SW_CVR_DUR_US, 3570 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3571 false, rtwdev, reg); 3572 if (ret) 3573 return ret; 3574 3575 return 0; 3576 } 3577 3578 static int band1_enable_ax(struct rtw89_dev *rtwdev) 3579 { 3580 int ret, i; 3581 u32 sleep_bak[4] = {0}; 3582 u32 pause_bak[4] = {0}; 3583 u32 tx_en; 3584 3585 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3586 if (ret) { 3587 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3588 return ret; 3589 } 3590 3591 for (i = 0; i < 4; i++) { 3592 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3593 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3594 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3595 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3596 } 3597 3598 ret = band_idle_ck_b(rtwdev, 0); 3599 if (ret) { 3600 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3601 return ret; 3602 } 3603 3604 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3605 if (ret) { 3606 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3607 return ret; 3608 } 3609 3610 for (i = 0; i < 4; i++) { 3611 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3612 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3613 } 3614 3615 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3616 if (ret) { 3617 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3618 return ret; 3619 } 3620 3621 ret = cmac_func_en_ax(rtwdev, 1, true); 3622 if (ret) { 3623 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3624 return ret; 3625 } 3626 3627 ret = cmac_init_ax(rtwdev, 1); 3628 if (ret) { 3629 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3630 return ret; 3631 } 3632 3633 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3634 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3635 3636 return 0; 3637 } 3638 3639 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3640 { 3641 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3642 3643 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3644 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3645 } 3646 3647 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3648 { 3649 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3650 3651 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3652 } 3653 3654 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3655 { 3656 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3657 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3658 3659 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3660 B_AX_TX_GET_ERRPKTID_INT_EN | 3661 B_AX_TX_NXT_ERRPKTID_INT_EN | 3662 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3663 B_AX_TX_OFFSET_ERR_INT_EN | 3664 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3665 if (chip_id == RTL8852C) 3666 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3667 B_AX_TX_ETH_TYPE_ERR_EN | 3668 B_AX_TX_LLC_PRE_ERR_EN | 3669 B_AX_TX_NW_TYPE_ERR_EN | 3670 B_AX_TX_KSRCH_ERR_EN); 3671 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3672 imr->mpdu_tx_imr_set); 3673 3674 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3675 B_AX_GETPKTID_ERR_INT_EN | 3676 B_AX_MHDRLEN_ERR_INT_EN | 3677 B_AX_RPT_ERR_INT_EN); 3678 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3679 imr->mpdu_rx_imr_set); 3680 } 3681 3682 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3683 { 3684 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3685 3686 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3687 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3688 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3689 B_AX_PLE_B_PKTID_ERR_INT_EN); 3690 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3691 imr->sta_sch_imr_set); 3692 } 3693 3694 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3695 { 3696 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3697 3698 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3699 imr->txpktctl_imr_b0_clr); 3700 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3701 imr->txpktctl_imr_b0_set); 3702 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3703 imr->txpktctl_imr_b1_clr); 3704 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3705 imr->txpktctl_imr_b1_set); 3706 } 3707 3708 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3709 { 3710 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3711 3712 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3713 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3714 } 3715 3716 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3717 { 3718 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3719 3720 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3721 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3722 } 3723 3724 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3725 { 3726 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3727 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3728 } 3729 3730 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3731 { 3732 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3733 3734 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3735 imr->host_disp_imr_clr); 3736 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3737 imr->host_disp_imr_set); 3738 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3739 imr->cpu_disp_imr_clr); 3740 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3741 imr->cpu_disp_imr_set); 3742 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3743 imr->other_disp_imr_clr); 3744 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3745 imr->other_disp_imr_set); 3746 } 3747 3748 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3749 { 3750 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3751 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3752 } 3753 3754 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3755 { 3756 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3757 3758 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3759 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3760 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3761 B_AX_BBRPT_CHINFO_IMR_CLR); 3762 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3763 imr->bbrpt_err_imr_set); 3764 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3765 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3766 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3767 } 3768 3769 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3770 { 3771 u32 reg; 3772 3773 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3774 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3775 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3776 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3777 } 3778 3779 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3780 { 3781 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3782 u32 reg; 3783 3784 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3785 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3786 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3787 } 3788 3789 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3790 { 3791 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3792 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3793 u32 reg; 3794 3795 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3796 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3797 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3798 3799 if (chip_id == RTL8852C) { 3800 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3801 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3802 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3803 } 3804 } 3805 3806 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3807 { 3808 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3809 u32 reg; 3810 3811 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3812 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3813 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3814 } 3815 3816 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3817 { 3818 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3819 u32 reg; 3820 3821 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3822 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3823 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3824 } 3825 3826 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3827 { 3828 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3829 u32 reg; 3830 3831 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3832 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3833 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3834 } 3835 3836 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3837 enum rtw89_mac_hwmod_sel sel) 3838 { 3839 int ret; 3840 3841 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3842 if (ret) { 3843 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3844 sel, mac_idx); 3845 return ret; 3846 } 3847 3848 if (sel == RTW89_DMAC_SEL) { 3849 rtw89_wdrls_imr_enable(rtwdev); 3850 rtw89_wsec_imr_enable(rtwdev); 3851 rtw89_mpdu_trx_imr_enable(rtwdev); 3852 rtw89_sta_sch_imr_enable(rtwdev); 3853 rtw89_txpktctl_imr_enable(rtwdev); 3854 rtw89_wde_imr_enable(rtwdev); 3855 rtw89_ple_imr_enable(rtwdev); 3856 rtw89_pktin_imr_enable(rtwdev); 3857 rtw89_dispatcher_imr_enable(rtwdev); 3858 rtw89_cpuio_imr_enable(rtwdev); 3859 rtw89_bbrpt_imr_enable(rtwdev); 3860 } else if (sel == RTW89_CMAC_SEL) { 3861 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3862 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3863 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3864 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3865 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3866 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3867 } else { 3868 return -EINVAL; 3869 } 3870 3871 return 0; 3872 } 3873 3874 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3875 { 3876 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3877 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3878 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3879 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3880 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta) 3881 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3882 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3883 } 3884 3885 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3886 { 3887 int ret = 0; 3888 3889 if (enable) { 3890 ret = band1_enable_ax(rtwdev); 3891 if (ret) { 3892 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3893 return ret; 3894 } 3895 3896 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3897 if (ret) { 3898 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3899 return ret; 3900 } 3901 } else { 3902 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3903 return -EINVAL; 3904 } 3905 3906 return 0; 3907 } 3908 3909 static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3910 { 3911 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3912 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3913 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3914 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3915 B_AX_RLSRPT0_FLTR_MAP_MASK); 3916 } else { 3917 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3918 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3919 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3920 B_AX_RLSRPT0_FLTR_MAP_MASK); 3921 } 3922 3923 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3924 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3925 3926 return 0; 3927 } 3928 3929 static int trx_init_ax(struct rtw89_dev *rtwdev) 3930 { 3931 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3932 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3933 int ret; 3934 3935 ret = dmac_init_ax(rtwdev, 0); 3936 if (ret) { 3937 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3938 return ret; 3939 } 3940 3941 ret = cmac_init_ax(rtwdev, 0); 3942 if (ret) { 3943 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3944 return ret; 3945 } 3946 3947 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3948 ret = dbcc_enable_ax(rtwdev, true); 3949 if (ret) { 3950 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3951 return ret; 3952 } 3953 } 3954 3955 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3956 if (ret) { 3957 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3958 return ret; 3959 } 3960 3961 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3962 if (ret) { 3963 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3964 return ret; 3965 } 3966 3967 err_imr_ctrl_ax(rtwdev, true); 3968 3969 ret = set_host_rpr_ax(rtwdev); 3970 if (ret) { 3971 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3972 return ret; 3973 } 3974 3975 if (chip_id == RTL8852C) 3976 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG, 3977 B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN); 3978 3979 return 0; 3980 } 3981 3982 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 3983 { 3984 #define BACAM_1024BMP_OCC_ENTRY 4 3985 #define BACAM_MAX_RU_SUPPORT_B0_STA 1 3986 #define BACAM_MAX_RU_SUPPORT_B1_STA 1 3987 const struct rtw89_chip_info *chip = rtwdev->chip; 3988 u8 users, offset; 3989 3990 if (chip->bacam_ver != RTW89_BACAM_V1) 3991 return 0; 3992 3993 offset = 0; 3994 users = BACAM_MAX_RU_SUPPORT_B0_STA; 3995 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 3996 3997 offset += users * BACAM_1024BMP_OCC_ENTRY; 3998 users = BACAM_MAX_RU_SUPPORT_B1_STA; 3999 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 4000 4001 return 0; 4002 } 4003 4004 static int rtw89_mac_reset_pwr_state_ax(struct rtw89_dev *rtwdev) 4005 { 4006 u8 val; 4007 4008 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 4009 if (val == MAC_AX_MAC_ON) { 4010 /* 4011 * A USB adapter might play as USB mass storage with driver and 4012 * then switch to WiFi adapter, causing it stays on power-on 4013 * state when doing WiFi USB probe. Return EAGAIN to caller to 4014 * power-off and power-on again to reset the state. 4015 */ 4016 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB && 4017 !test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags)) 4018 return -EAGAIN; 4019 4020 rtw89_err(rtwdev, "MAC has already powered on\n"); 4021 return -EBUSY; 4022 } 4023 4024 return 0; 4025 } 4026 4027 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 4028 { 4029 u32 val32; 4030 4031 if (rtw89_is_rtl885xb(rtwdev)) { 4032 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 4033 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 4034 return; 4035 } 4036 4037 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 4038 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 4039 4040 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 4041 val32 |= B_AX_FS_WDT_INT; 4042 val32 &= ~B_AX_FS_WDT_INT_MSK; 4043 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 4044 } 4045 4046 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 4047 { 4048 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 4049 4050 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 4051 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 4052 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 4053 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 4054 4055 rtw89_disable_fw_watchdog(rtwdev); 4056 4057 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 4058 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 4059 } 4060 4061 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 4062 bool dlfw, bool include_bb) 4063 { 4064 u32 val; 4065 int ret; 4066 4067 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 4068 return -EFAULT; 4069 4070 rtw89_write32(rtwdev, R_AX_UDM1, 0); 4071 rtw89_write32(rtwdev, R_AX_UDM2, 0); 4072 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 4073 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 4074 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 4075 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 4076 4077 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 4078 4079 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 4080 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 4081 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 4082 B_AX_WCPU_FWDL_STS_MASK); 4083 4084 if (dlfw) 4085 val |= B_AX_WCPU_FWDL_EN; 4086 4087 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 4088 4089 if (rtw89_is_rtl885xb(rtwdev)) 4090 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 4091 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 4092 4093 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 4094 boot_reason); 4095 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 4096 4097 if (!dlfw) { 4098 mdelay(5); 4099 4100 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 4101 if (ret) 4102 return ret; 4103 } 4104 4105 return 0; 4106 } 4107 4108 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 4109 { 4110 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4111 u32 val; 4112 4113 if (chip_id == RTL8852C) 4114 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 4115 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 4116 else 4117 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 4118 B_AX_PKT_BUF_EN; 4119 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 4120 } 4121 4122 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 4123 { 4124 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4125 u32 val; 4126 4127 if (chip_id == RTL8851B || chip_id == RTL8852BT) 4128 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 4129 else 4130 val = B_AX_DISPATCHER_CLK_EN; 4131 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 4132 4133 if (chip_id != RTL8852C) 4134 return; 4135 4136 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 4137 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 4138 val |= B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 4139 4140 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) 4141 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B); 4142 else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 4143 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_USB); 4144 else 4145 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_SDIO); 4146 4147 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 4148 4149 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 4150 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 4151 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 4152 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 4153 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 4154 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 4155 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 4156 } 4157 4158 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 4159 { 4160 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4161 int ret; 4162 4163 mac->hci_func_en(rtwdev); 4164 mac->dmac_func_pre_en(rtwdev); 4165 4166 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 4167 if (ret) { 4168 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 4169 return ret; 4170 } 4171 4172 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 4173 if (ret) { 4174 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 4175 return ret; 4176 } 4177 4178 return ret; 4179 } 4180 4181 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 4182 { 4183 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 4184 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 4185 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 4186 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 4187 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 4188 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 4189 4190 return 0; 4191 } 4192 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 4193 4194 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 4195 { 4196 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 4197 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 4198 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 4199 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 4200 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 4201 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 4202 4203 return 0; 4204 } 4205 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 4206 4207 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 4208 { 4209 int ret; 4210 4211 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 4212 4213 if (include_bb) { 4214 /* Only call BB preinit including configuration of BB MCU for 4215 * the chips which need to download BB MCU firmware. Otherwise, 4216 * calling preinit later to prevent touching registers affecting 4217 * download firmware. 4218 */ 4219 rtw89_chip_bb_preinit(rtwdev); 4220 } 4221 4222 ret = rtw89_mac_dmac_pre_init(rtwdev); 4223 if (ret) 4224 return ret; 4225 4226 if (rtwdev->hci.ops->mac_pre_init) { 4227 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 4228 if (ret) 4229 return ret; 4230 } 4231 4232 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 4233 if (ret) 4234 return ret; 4235 4236 return 0; 4237 } 4238 4239 int rtw89_mac_preinit(struct rtw89_dev *rtwdev) 4240 { 4241 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4242 int ret; 4243 4244 ret = rtw89_mac_pwr_on(rtwdev); 4245 if (ret) 4246 return ret; 4247 4248 if (mac->mac_func_en) { 4249 ret = mac->mac_func_en(rtwdev); 4250 if (ret) 4251 return ret; 4252 } 4253 4254 return 0; 4255 } 4256 4257 int rtw89_mac_init(struct rtw89_dev *rtwdev) 4258 { 4259 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4260 const struct rtw89_chip_info *chip = rtwdev->chip; 4261 bool include_bb = !!chip->bbmcu_nr; 4262 int ret; 4263 4264 ret = rtw89_mac_partial_init(rtwdev, include_bb); 4265 if (ret) 4266 goto fail; 4267 4268 ret = rtw89_chip_enable_bb_rf(rtwdev); 4269 if (ret) 4270 goto fail; 4271 4272 ret = mac->sys_init(rtwdev); 4273 if (ret) 4274 goto fail; 4275 4276 ret = mac->trx_init(rtwdev); 4277 if (ret) 4278 goto fail; 4279 4280 ret = rtw89_mac_feat_init(rtwdev); 4281 if (ret) 4282 goto fail; 4283 4284 if (rtwdev->hci.ops->mac_post_init) { 4285 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 4286 if (ret) 4287 goto fail; 4288 } 4289 4290 rtw89_fw_send_all_early_h2c(rtwdev); 4291 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 4292 4293 return ret; 4294 fail: 4295 rtw89_mac_pwr_off(rtwdev); 4296 4297 return ret; 4298 } 4299 4300 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4301 { 4302 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4303 u8 i; 4304 4305 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4306 return; 4307 4308 for (i = 0; i < 4; i++) { 4309 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4310 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 4311 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 4312 } 4313 } 4314 4315 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4316 { 4317 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4318 4319 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4320 return; 4321 4322 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4323 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 4324 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 4325 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 4326 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 4327 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 4328 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 4329 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 4330 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 4331 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 4332 } 4333 4334 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4335 { 4336 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4337 u8 grp = macid >> 5; 4338 int ret; 4339 4340 /* If this is called by change_interface() in the case of P2P, it could 4341 * be power-off, so ignore this operation. 4342 */ 4343 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4344 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4345 return 0; 4346 4347 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4348 if (ret) 4349 return ret; 4350 4351 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4352 4353 return 0; 4354 } 4355 4356 static const struct rtw89_port_reg rtw89_port_base_ax = { 4357 .port_cfg = R_AX_PORT_CFG_P0, 4358 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4359 .bcn_area = R_AX_BCN_AREA_P0, 4360 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4361 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4362 .tbtt_agg = R_AX_TBTT_AGG_P0, 4363 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4364 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4365 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4366 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4367 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4368 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4369 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4370 .tsftr_l = R_AX_TSFTR_LOW_P0, 4371 .tsftr_h = R_AX_TSFTR_HIGH_P0, 4372 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 4373 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4374 .mbssid = R_AX_MBSSID_CTRL, 4375 .mbssid_drop = R_AX_MBSSID_DROP_0, 4376 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4377 .ptcl_dbg = R_AX_PTCL_DBG, 4378 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4379 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4380 .bcn_psr_rpt = R_AX_BCN_PSR_RPT_P0, 4381 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4382 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4383 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4384 }; 4385 4386 static const struct rtw89_mac_mu_gid_addr rtw89_mac_mu_gid_addr_ax = { 4387 .position_en = {R_AX_GID_POSITION_EN0, R_AX_GID_POSITION_EN1}, 4388 .position = {R_AX_GID_POSITION0, R_AX_GID_POSITION1, 4389 R_AX_GID_POSITION2, R_AX_GID_POSITION3}, 4390 }; 4391 4392 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4393 struct rtw89_vif_link *rtwvif_link, u8 type) 4394 { 4395 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4396 const struct rtw89_port_reg *p = mac->port_base; 4397 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif_link->port); 4398 u32 reg_info, reg_ctrl; 4399 u32 val; 4400 int ret; 4401 4402 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif_link->mac_idx); 4403 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif_link->mac_idx); 4404 4405 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4406 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4407 fsleep(100); 4408 4409 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4410 true, rtwdev, reg_info, mask); 4411 if (ret) 4412 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4413 } 4414 4415 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, 4416 struct rtw89_vif_link *rtwvif_link) 4417 { 4418 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4419 const struct rtw89_port_reg *p = mac->port_base; 4420 4421 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4422 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 4423 1); 4424 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 4425 0); 4426 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 4427 0); 4428 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4429 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4430 B_AX_TBTTERLY_MASK, 1); 4431 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, 4432 B_AX_BCN_SPACE_MASK, 1); 4433 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4434 4435 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM0); 4436 if (rtwvif_link->port == RTW89_PORT_0) 4437 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM1); 4438 4439 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4440 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4441 fsleep(2000); 4442 } 4443 4444 #define BCN_INTERVAL 100 4445 #define BCN_ERLY_DEF 160 4446 #define BCN_SETUP_DEF 2 4447 #define BCN_HOLD_DEF 200 4448 #define BCN_MASK_DEF 0 4449 #define TBTT_ERLY_DEF 5 4450 #define TBTT_AGG_DEF 1 4451 #define BCN_SET_UNIT 32 4452 #define BCN_ERLY_SET_DLY (10 * 2) 4453 4454 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4455 struct rtw89_vif_link *rtwvif_link) 4456 { 4457 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4458 const struct rtw89_port_reg *p = mac->port_base; 4459 const struct rtw89_chip_info *chip = rtwdev->chip; 4460 struct ieee80211_bss_conf *bss_conf; 4461 bool need_backup = false; 4462 u32 backup_val; 4463 u16 beacon_int; 4464 4465 if (!rtw89_read32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN)) 4466 return; 4467 4468 if (chip->chip_id == RTL8852A && rtwvif_link->port != RTW89_PORT_0) { 4469 need_backup = true; 4470 backup_val = rtw89_read32_port(rtwdev, rtwvif_link, p->tbtt_prohib); 4471 } 4472 4473 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4474 rtw89_mac_bcn_drop(rtwdev, rtwvif_link); 4475 4476 if (chip->chip_id == RTL8852A) { 4477 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->tbtt_prohib, 4478 B_AX_TBTT_SETUP_MASK); 4479 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4480 B_AX_TBTT_HOLD_MASK, 1); 4481 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->tbtt_early, 4482 B_AX_TBTTERLY_MASK); 4483 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->bcn_early, 4484 B_AX_BCNERLY_MASK); 4485 } 4486 4487 rcu_read_lock(); 4488 4489 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4490 beacon_int = bss_conf->beacon_int; 4491 4492 rcu_read_unlock(); 4493 4494 msleep(beacon_int + 1); 4495 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN | 4496 B_AX_BRK_SETUP); 4497 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSFTR_RST); 4498 rtw89_write32_port(rtwdev, rtwvif_link, p->bcn_cnt_tmr, 0); 4499 4500 if (need_backup) 4501 rtw89_write32_port(rtwdev, rtwvif_link, p->tbtt_prohib, backup_val); 4502 } 4503 4504 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4505 struct rtw89_vif_link *rtwvif_link, bool en) 4506 { 4507 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4508 const struct rtw89_port_reg *p = mac->port_base; 4509 4510 if (en) 4511 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4512 B_AX_TXBCN_RPT_EN); 4513 else 4514 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4515 B_AX_TXBCN_RPT_EN); 4516 } 4517 4518 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4519 struct rtw89_vif_link *rtwvif_link, bool en) 4520 { 4521 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4522 const struct rtw89_port_reg *p = mac->port_base; 4523 4524 if (en) 4525 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4526 B_AX_RXBCN_RPT_EN); 4527 else 4528 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4529 B_AX_RXBCN_RPT_EN); 4530 } 4531 4532 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4533 struct rtw89_vif_link *rtwvif_link) 4534 { 4535 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4536 const struct rtw89_port_reg *p = mac->port_base; 4537 4538 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_NET_TYPE_MASK, 4539 rtwvif_link->net_type); 4540 } 4541 4542 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4543 struct rtw89_vif_link *rtwvif_link) 4544 { 4545 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4546 const struct rtw89_port_reg *p = mac->port_base; 4547 bool en = rtwvif_link->net_type != RTW89_NET_TYPE_NO_LINK; 4548 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4549 4550 if (en) 4551 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bits); 4552 else 4553 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bits); 4554 } 4555 4556 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4557 struct rtw89_vif_link *rtwvif_link) 4558 { 4559 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4560 const struct rtw89_port_reg *p = mac->port_base; 4561 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4562 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4563 u32 bit = B_AX_RX_BSSID_FIT_EN; 4564 4565 if (en) 4566 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bit); 4567 else 4568 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bit); 4569 } 4570 4571 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4572 struct rtw89_vif_link *rtwvif_link, bool en) 4573 { 4574 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4575 const struct rtw89_port_reg *p = mac->port_base; 4576 4577 if (en) 4578 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4579 else 4580 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4581 } 4582 4583 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4584 struct rtw89_vif_link *rtwvif_link) 4585 { 4586 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4587 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4588 4589 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif_link, en); 4590 } 4591 4592 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4593 struct rtw89_vif_link *rtwvif_link, bool en) 4594 { 4595 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4596 const struct rtw89_port_reg *p = mac->port_base; 4597 4598 if (en) 4599 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4600 else 4601 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4602 } 4603 4604 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4605 struct rtw89_vif_link *rtwvif_link) 4606 { 4607 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || 4608 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4609 4610 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4611 } 4612 4613 static void rtw89_mac_enable_ap_bcn_by_chan(struct rtw89_dev *rtwdev, 4614 struct rtw89_vif_link *rtwvif_link, 4615 const struct rtw89_chan *to_match, 4616 bool en) 4617 { 4618 const struct rtw89_chan *chan; 4619 4620 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 4621 return; 4622 4623 if (!to_match) 4624 goto doit; 4625 4626 /* @to_match may not be in the same domain as return of calling 4627 * rtw89_chan_get(). So, cannot compare their addresses directly. 4628 */ 4629 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 4630 if (chan->channel != to_match->channel) 4631 return; 4632 4633 doit: 4634 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4635 } 4636 4637 static void rtw89_mac_enable_aps_bcn_by_chan(struct rtw89_dev *rtwdev, 4638 const struct rtw89_chan *to_match, 4639 bool en) 4640 { 4641 struct rtw89_vif_link *rtwvif_link; 4642 struct rtw89_vif *rtwvif; 4643 unsigned int link_id; 4644 4645 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4646 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4647 rtw89_mac_enable_ap_bcn_by_chan(rtwdev, rtwvif_link, 4648 to_match, en); 4649 } 4650 4651 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4652 { 4653 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, NULL, en); 4654 } 4655 4656 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4657 struct rtw89_vif_link *rtwvif_link) 4658 { 4659 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4660 const struct rtw89_port_reg *p = mac->port_base; 4661 struct ieee80211_bss_conf *bss_conf; 4662 u16 bcn_int; 4663 4664 rcu_read_lock(); 4665 4666 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4667 if (bss_conf->beacon_int) 4668 bcn_int = bss_conf->beacon_int; 4669 else 4670 bcn_int = BCN_INTERVAL; 4671 4672 rcu_read_unlock(); 4673 4674 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, B_AX_BCN_SPACE_MASK, 4675 bcn_int); 4676 } 4677 4678 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4679 struct rtw89_vif_link *rtwvif_link) 4680 { 4681 u8 win = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4682 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4683 const struct rtw89_port_reg *p = mac->port_base; 4684 u8 port = rtwvif_link->port; 4685 u32 reg; 4686 4687 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif_link->mac_idx); 4688 rtw89_write8(rtwdev, reg, win); 4689 } 4690 4691 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4692 struct rtw89_vif_link *rtwvif_link) 4693 { 4694 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4695 const struct rtw89_port_reg *p = mac->port_base; 4696 struct ieee80211_bss_conf *bss_conf; 4697 u8 dtim_period; 4698 u32 addr; 4699 4700 rcu_read_lock(); 4701 4702 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4703 dtim_period = bss_conf->dtim_period; 4704 4705 rcu_read_unlock(); 4706 4707 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif_link->mac_idx); 4708 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4709 4710 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4711 dtim_period); 4712 } 4713 4714 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4715 struct rtw89_vif_link *rtwvif_link) 4716 { 4717 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4718 const struct rtw89_port_reg *p = mac->port_base; 4719 4720 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4721 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4722 } 4723 4724 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4725 struct rtw89_vif_link *rtwvif_link) 4726 { 4727 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4728 const struct rtw89_port_reg *p = mac->port_base; 4729 4730 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4731 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4732 } 4733 4734 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4735 struct rtw89_vif_link *rtwvif_link) 4736 { 4737 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4738 const struct rtw89_port_reg *p = mac->port_base; 4739 4740 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, 4741 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4742 } 4743 4744 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4745 struct rtw89_vif_link *rtwvif_link) 4746 { 4747 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4748 const struct rtw89_port_reg *p = mac->port_base; 4749 4750 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4751 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4752 } 4753 4754 static void rtw89_mac_port_cfg_tbtt_agg(struct rtw89_dev *rtwdev, 4755 struct rtw89_vif_link *rtwvif_link) 4756 { 4757 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4758 const struct rtw89_port_reg *p = mac->port_base; 4759 4760 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_agg, 4761 B_AX_TBTT_AGG_NUM_MASK, TBTT_AGG_DEF); 4762 } 4763 4764 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4765 struct rtw89_vif_link *rtwvif_link) 4766 { 4767 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4768 const struct rtw89_port_reg *p = mac->port_base; 4769 static const u32 masks[RTW89_PORT_NUM] = { 4770 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4771 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4772 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4773 }; 4774 struct ieee80211_bss_conf *bss_conf; 4775 u8 port = rtwvif_link->port; 4776 u32 reg_base; 4777 u32 reg; 4778 u8 bss_color; 4779 4780 rcu_read_lock(); 4781 4782 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4783 bss_color = bss_conf->he_bss_color.color; 4784 4785 rcu_read_unlock(); 4786 4787 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4788 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif_link->mac_idx); 4789 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4790 } 4791 4792 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4793 struct rtw89_vif_link *rtwvif_link) 4794 { 4795 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4796 const struct rtw89_port_reg *p = mac->port_base; 4797 u8 port = rtwvif_link->port; 4798 u32 reg; 4799 4800 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4801 return; 4802 4803 if (port == 0) { 4804 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif_link->mac_idx); 4805 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4806 } 4807 } 4808 4809 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4810 struct rtw89_vif_link *rtwvif_link) 4811 { 4812 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4813 const struct rtw89_port_reg *p = mac->port_base; 4814 u8 port = rtwvif_link->port; 4815 u32 reg; 4816 u32 val; 4817 4818 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif_link->mac_idx); 4819 val = rtw89_read32(rtwdev, reg); 4820 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4821 if (port == 0) 4822 val &= ~BIT(0); 4823 rtw89_write32(rtwdev, reg, val); 4824 } 4825 4826 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4827 struct rtw89_vif_link *rtwvif_link, bool enable) 4828 { 4829 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4830 const struct rtw89_port_reg *p = mac->port_base; 4831 4832 if (enable) 4833 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4834 B_AX_PORT_FUNC_EN); 4835 else 4836 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4837 B_AX_PORT_FUNC_EN); 4838 } 4839 4840 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4841 struct rtw89_vif_link *rtwvif_link) 4842 { 4843 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4844 const struct rtw89_port_reg *p = mac->port_base; 4845 4846 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 4847 BCN_ERLY_DEF); 4848 } 4849 4850 static void rtw89_mac_port_cfg_bcn_psr_rpt(struct rtw89_dev *rtwdev, 4851 struct rtw89_vif_link *rtwvif_link) 4852 { 4853 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4854 const struct rtw89_port_reg *p = mac->port_base; 4855 struct ieee80211_bss_conf *bss_conf; 4856 u8 bssid_index; 4857 u32 reg; 4858 4859 rcu_read_lock(); 4860 4861 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4862 if (bss_conf->nontransmitted) 4863 bssid_index = bss_conf->bssid_index; 4864 else 4865 bssid_index = 0; 4866 4867 rcu_read_unlock(); 4868 4869 reg = rtw89_mac_reg_by_idx(rtwdev, p->bcn_psr_rpt + rtwvif_link->port * 4, 4870 rtwvif_link->mac_idx); 4871 rtw89_write32_mask(rtwdev, reg, B_AX_BCAID_P0_MASK, bssid_index); 4872 } 4873 4874 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4875 struct rtw89_vif_link *rtwvif_link, 4876 struct rtw89_vif_link *rtwvif_src, 4877 u16 offset_tu) 4878 { 4879 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4880 const struct rtw89_port_reg *p = mac->port_base; 4881 u32 val, reg; 4882 4883 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4884 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif_link->port * 4, 4885 rtwvif_link->mac_idx); 4886 4887 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4888 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4889 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4890 } 4891 4892 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4893 struct rtw89_vif_link *rtwvif_link, 4894 struct rtw89_vif_link *rtwvif_src, 4895 u8 offset, int *n_offset) 4896 { 4897 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif_link == rtwvif_src) 4898 return; 4899 4900 if (rtwvif_link->rand_tsf_done) 4901 goto out; 4902 4903 /* adjust offset randomly to avoid beacon conflict */ 4904 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4905 rtw89_mac_port_tsf_sync(rtwdev, rtwvif_link, rtwvif_src, 4906 (*n_offset) * offset); 4907 4908 rtwvif_link->rand_tsf_done = true; 4909 4910 out: 4911 (*n_offset)++; 4912 } 4913 4914 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4915 { 4916 struct rtw89_vif_link *src = NULL, *tmp; 4917 u8 offset = 100, vif_aps = 0; 4918 struct rtw89_vif *rtwvif; 4919 unsigned int link_id; 4920 int n_offset = 1; 4921 4922 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4923 rtw89_vif_for_each_link(rtwvif, tmp, link_id) { 4924 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4925 src = tmp; 4926 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4927 vif_aps++; 4928 } 4929 } 4930 4931 if (vif_aps == 0) 4932 return; 4933 4934 offset /= (vif_aps + 1); 4935 4936 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4937 rtw89_vif_for_each_link(rtwvif, tmp, link_id) 4938 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, 4939 &n_offset); 4940 } 4941 4942 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4943 { 4944 int ret; 4945 4946 ret = rtw89_mac_port_update(rtwdev, rtwvif_link); 4947 if (ret) 4948 return ret; 4949 4950 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4951 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4952 4953 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif_link->mac_id, false); 4954 if (ret) 4955 return ret; 4956 4957 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_CREATE); 4958 if (ret) 4959 return ret; 4960 4961 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, NULL, true); 4962 if (ret) 4963 return ret; 4964 4965 ret = rtw89_cam_init(rtwdev, rtwvif_link); 4966 if (ret) 4967 return ret; 4968 4969 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, RTW89_ROLE_CREATE); 4970 if (ret) 4971 return ret; 4972 4973 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, NULL); 4974 if (ret) 4975 return ret; 4976 4977 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, NULL); 4978 if (ret) 4979 return ret; 4980 4981 return 0; 4982 } 4983 4984 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4985 { 4986 int ret; 4987 4988 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_REMOVE); 4989 if (ret) 4990 return ret; 4991 4992 rtw89_cam_deinit(rtwdev, rtwvif_link); 4993 4994 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, RTW89_ROLE_REMOVE); 4995 if (ret) 4996 return ret; 4997 4998 return 0; 4999 } 5000 5001 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5002 { 5003 u8 port = rtwvif_link->port; 5004 5005 if (port >= RTW89_PORT_NUM) 5006 return -EINVAL; 5007 5008 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 5009 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif_link, false); 5010 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif_link, false); 5011 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif_link); 5012 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif_link); 5013 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif_link); 5014 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif_link); 5015 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif_link); 5016 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif_link); 5017 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif_link); 5018 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif_link); 5019 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif_link); 5020 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif_link); 5021 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif_link); 5022 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif_link); 5023 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif_link); 5024 rtw89_mac_port_cfg_tbtt_agg(rtwdev, rtwvif_link); 5025 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif_link); 5026 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif_link); 5027 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif_link, true); 5028 rtw89_mac_port_tsf_resync_all(rtwdev); 5029 fsleep(BCN_ERLY_SET_DLY); 5030 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif_link); 5031 rtw89_mac_port_cfg_bcn_psr_rpt(rtwdev, rtwvif_link); 5032 5033 return 0; 5034 } 5035 5036 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5037 u64 *tsf) 5038 { 5039 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5040 const struct rtw89_port_reg *p = mac->port_base; 5041 u32 tsf_low, tsf_high; 5042 int ret; 5043 5044 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif_link->mac_idx, RTW89_CMAC_SEL); 5045 if (ret) 5046 return ret; 5047 5048 tsf_low = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_l); 5049 tsf_high = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_h); 5050 *tsf = (u64)tsf_high << 32 | tsf_low; 5051 5052 return 0; 5053 } 5054 5055 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 5056 struct cfg80211_bss *bss, 5057 void *data) 5058 { 5059 const struct cfg80211_bss_ies *ies; 5060 const struct element *elem; 5061 bool *tolerated = data; 5062 5063 rcu_read_lock(); 5064 ies = rcu_dereference(bss->ies); 5065 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 5066 ies->len); 5067 5068 if (!elem || elem->datalen < 10 || 5069 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 5070 *tolerated = false; 5071 rcu_read_unlock(); 5072 } 5073 5074 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 5075 struct rtw89_vif_link *rtwvif_link) 5076 { 5077 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5078 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5079 struct ieee80211_hw *hw = rtwdev->hw; 5080 struct ieee80211_bss_conf *bss_conf; 5081 struct cfg80211_chan_def oper; 5082 bool tolerated = true; 5083 u32 reg; 5084 5085 rcu_read_lock(); 5086 5087 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5088 if (!bss_conf->he_support || vif->type != NL80211_IFTYPE_STATION) { 5089 rcu_read_unlock(); 5090 return; 5091 } 5092 5093 oper = bss_conf->chanreq.oper; 5094 if (!(oper.chan->flags & IEEE80211_CHAN_RADAR)) { 5095 rcu_read_unlock(); 5096 return; 5097 } 5098 5099 rcu_read_unlock(); 5100 5101 cfg80211_bss_iter(hw->wiphy, &oper, 5102 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 5103 &tolerated); 5104 5105 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 5106 rtwvif_link->mac_idx); 5107 if (tolerated) 5108 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 5109 else 5110 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 5111 } 5112 5113 void rtw89_mac_set_he_tb(struct rtw89_dev *rtwdev, 5114 struct rtw89_vif_link *rtwvif_link) 5115 { 5116 struct ieee80211_bss_conf *bss_conf; 5117 bool set; 5118 u32 reg; 5119 5120 if (rtwdev->chip->chip_gen != RTW89_CHIP_BE) 5121 return; 5122 5123 rcu_read_lock(); 5124 5125 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5126 set = bss_conf->he_support && !bss_conf->eht_support; 5127 5128 rcu_read_unlock(); 5129 5130 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CLIENT_OM_CTRL, 5131 rtwvif_link->mac_idx); 5132 5133 if (set) 5134 rtw89_write32_set(rtwdev, reg, B_BE_TRIG_DIS_EHTTB); 5135 else 5136 rtw89_write32_clr(rtwdev, reg, B_BE_TRIG_DIS_EHTTB); 5137 } 5138 5139 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5140 { 5141 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 5142 5143 rtwvif_link->rand_tsf_done = false; 5144 } 5145 5146 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5147 { 5148 return rtw89_mac_vif_init(rtwdev, rtwvif_link); 5149 } 5150 5151 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5152 { 5153 return rtw89_mac_vif_deinit(rtwdev, rtwvif_link); 5154 } 5155 5156 static void 5157 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5158 { 5159 } 5160 5161 static const struct rtw89_chan * 5162 rtw89_hw_scan_search_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 5163 { 5164 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 5165 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 5166 5167 if (band == op->band_type && channel == op->primary_channel) 5168 return op; 5169 5170 if (scan_info->extra_op.set) { 5171 op = &scan_info->extra_op.chan; 5172 if (band == op->band_type && channel == op->primary_channel) 5173 return op; 5174 } 5175 5176 return NULL; 5177 } 5178 5179 static void 5180 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5181 u32 len) 5182 { 5183 const struct rtw89_c2h_scanofld *c2h = 5184 (const struct rtw89_c2h_scanofld *)skb->data; 5185 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 5186 const struct rtw89_chan *op_chan; 5187 struct rtw89_vif *rtwvif; 5188 struct rtw89_chan new; 5189 u16 actual_period, expect_period; 5190 u8 reason, status, tx_fail, band; 5191 u8 mac_idx, sw_def, fw_def; 5192 u8 ver = U8_MAX; 5193 u32 report_tsf; 5194 u16 chan; 5195 int ret; 5196 5197 if (!rtwvif_link) 5198 return; 5199 5200 rtwvif = rtwvif_link->rtwvif; 5201 5202 if (RTW89_CHK_FW_FEATURE(CH_INFO_BE_V0, &rtwdev->fw)) 5203 ver = 0; 5204 5205 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 5206 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5207 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 5208 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5209 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 5210 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 5211 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 5212 5213 5214 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 5215 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 5216 5217 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 5218 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 5219 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 5220 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 5221 if (ver == 0) { 5222 expect_period = 5223 le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 5224 } else { 5225 actual_period = le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_PERIOD_V1); 5226 expect_period = 5227 le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1); 5228 } 5229 5230 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 5231 "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 5232 sw_def, fw_def, report_tsf, expect_period); 5233 } 5234 5235 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 5236 "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 5237 mac_idx, band, chan, reason, status, tx_fail, actual_period); 5238 5239 switch (reason) { 5240 case RTW89_SCAN_LEAVE_OP_NOTIFY: 5241 case RTW89_SCAN_LEAVE_CH_NOTIFY: 5242 op_chan = rtw89_hw_scan_search_op_chan(rtwdev, band, chan); 5243 if (op_chan) { 5244 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, op_chan, false); 5245 ieee80211_stop_queues(rtwdev->hw); 5246 } else { 5247 rtw89_phy_nhm_get_result(rtwdev, band, chan); 5248 } 5249 return; 5250 case RTW89_SCAN_END_SCAN_NOTIFY: 5251 if (rtwdev->scan_info.abort) 5252 return; 5253 5254 if (rtwvif_link && rtwvif->scan_req && 5255 !list_empty(&rtwdev->scan_info.chan_list)) { 5256 rtwdev->scan_info.delay = 0; 5257 ret = rtw89_hw_scan_offload(rtwdev, rtwvif_link, true); 5258 if (ret) { 5259 rtw89_hw_scan_abort(rtwdev, rtwvif_link); 5260 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 5261 } 5262 } else { 5263 rtw89_hw_scan_complete(rtwdev, rtwvif_link, false); 5264 } 5265 break; 5266 case RTW89_SCAN_ENTER_OP_NOTIFY: 5267 case RTW89_SCAN_ENTER_CH_NOTIFY: 5268 op_chan = rtw89_hw_scan_search_op_chan(rtwdev, band, chan); 5269 if (op_chan) { 5270 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, op_chan); 5271 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, op_chan, true); 5272 ieee80211_wake_queues(rtwdev->hw); 5273 } else { 5274 rtw89_chan_create(&new, chan, chan, band, 5275 RTW89_CHANNEL_WIDTH_20); 5276 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, 5277 &new); 5278 rtw89_phy_nhm_trigger(rtwdev); 5279 } 5280 break; 5281 default: 5282 return; 5283 } 5284 } 5285 5286 static void 5287 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5288 struct sk_buff *skb) 5289 { 5290 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5291 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5292 enum nl80211_cqm_rssi_threshold_event nl_event; 5293 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 5294 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 5295 u8 type, event, mac_id; 5296 bool start_detect; 5297 s8 sig; 5298 5299 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 5300 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 5301 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 5302 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 5303 5304 if (mac_id != rtwvif_link->mac_id) 5305 return; 5306 5307 rtw89_debug(rtwdev, RTW89_DBG_FW, 5308 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 5309 mac_id, type, sig, event); 5310 5311 switch (type) { 5312 case RTW89_BCN_FLTR_BEACON_LOSS: 5313 if (!rtwdev->scanning && !rtwvif->offchan && 5314 !rtwvif_link->noa_once.in_duration) { 5315 start_detect = rtw89_mcc_detect_go_bcn(rtwdev, rtwvif_link); 5316 if (start_detect) 5317 return; 5318 5319 ieee80211_beacon_loss(vif); 5320 } 5321 5322 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 5323 return; 5324 case RTW89_BCN_FLTR_NOTIFY: 5325 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 5326 break; 5327 case RTW89_BCN_FLTR_RSSI: 5328 if (event == RTW89_BCN_FLTR_RSSI_LOW) 5329 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 5330 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 5331 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 5332 else 5333 return; 5334 break; 5335 default: 5336 return; 5337 } 5338 5339 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 5340 } 5341 5342 static void 5343 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5344 u32 len) 5345 { 5346 struct rtw89_vif_link *rtwvif_link; 5347 struct rtw89_vif *rtwvif; 5348 unsigned int link_id; 5349 5350 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5351 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 5352 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif_link, c2h); 5353 } 5354 5355 static void 5356 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5357 { 5358 /* N.B. This will run in interrupt context. */ 5359 5360 rtw89_debug(rtwdev, RTW89_DBG_FW, 5361 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 5362 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 5363 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 5364 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 5365 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 5366 } 5367 5368 static void 5369 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5370 { 5371 /* N.B. This will run in interrupt context. */ 5372 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5373 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 5374 struct rtw89_wait_info *ps_wait = &rtwdev->mac.ps_wait; 5375 const struct rtw89_c2h_done_ack *c2h = 5376 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 5377 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 5378 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 5379 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 5380 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 5381 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 5382 struct rtw89_completion_data data = {}; 5383 unsigned int cond; 5384 5385 rtw89_debug(rtwdev, RTW89_DBG_FW, 5386 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 5387 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 5388 5389 if (h2c_cat != H2C_CAT_MAC) 5390 return; 5391 5392 switch (h2c_class) { 5393 default: 5394 return; 5395 case H2C_CL_MAC_PS: 5396 switch (h2c_func) { 5397 default: 5398 return; 5399 case H2C_FUNC_IPS_CFG: 5400 cond = RTW89_PS_WAIT_COND_IPS_CFG; 5401 break; 5402 } 5403 5404 data.err = !!h2c_return; 5405 rtw89_complete_cond(ps_wait, cond, &data); 5406 return; 5407 case H2C_CL_MAC_FW_OFLD: 5408 switch (h2c_func) { 5409 default: 5410 return; 5411 case H2C_FUNC_ADD_SCANOFLD_CH: 5412 cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 5413 h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN; 5414 break; 5415 case H2C_FUNC_SCANOFLD: 5416 scan_info->seq++; 5417 cond = RTW89_SCANOFLD_WAIT_COND_START; 5418 break; 5419 case H2C_FUNC_SCANOFLD_BE: 5420 scan_info->seq++; 5421 cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 5422 h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN; 5423 break; 5424 case H2C_FUNC_TRX_PROTECT: 5425 cond = RTW89_FW_OFLD_WAIT_COND_TRX_PROTECT; 5426 break; 5427 } 5428 5429 data.err = !!h2c_return; 5430 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5431 return; 5432 } 5433 } 5434 5435 static void 5436 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5437 { 5438 rtw89_fw_log_dump(rtwdev, c2h->data, len); 5439 } 5440 5441 static void 5442 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5443 { 5444 } 5445 5446 static void 5447 rtw89_mac_c2h_bcn_upd_done(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5448 { 5449 const struct rtw89_c2h_bcn_upd_done *c2h = 5450 (const struct rtw89_c2h_bcn_upd_done *)skb_c2h->data; 5451 u8 band, port, mbssid; 5452 5453 port = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_PORT); 5454 mbssid = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_MBSSID); 5455 band = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_BAND_IDX); 5456 5457 rtw89_debug(rtwdev, RTW89_DBG_FW, 5458 "BCN update done on port:%d mbssid:%d band:%d\n", 5459 port, mbssid, band); 5460 } 5461 5462 static void 5463 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 5464 u32 len) 5465 { 5466 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 5467 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 5468 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 5469 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 5470 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 5471 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 5472 struct rtw89_completion_data data = {}; 5473 unsigned int cond; 5474 5475 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 5476 pkt_id, pkt_op, pkt_len); 5477 5478 data.err = !pkt_len; 5479 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 5480 5481 rtw89_complete_cond(wait, cond, &data); 5482 } 5483 5484 static void 5485 rtw89_mac_c2h_bcn_resend(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5486 { 5487 } 5488 5489 static void 5490 rtw89_mac_c2h_tx_duty_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5491 { 5492 struct rtw89_c2h_tx_duty_rpt *c2h = 5493 (struct rtw89_c2h_tx_duty_rpt *)skb_c2h->data; 5494 u8 err; 5495 5496 err = le32_get_bits(c2h->w2, RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR); 5497 5498 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "C2H TX duty rpt with err=%d\n", err); 5499 } 5500 5501 static void 5502 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5503 u32 len) 5504 { 5505 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 5506 } 5507 5508 static void 5509 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5510 { 5511 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 5512 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 5513 5514 switch (func) { 5515 case H2C_FUNC_ADD_MCC: 5516 case H2C_FUNC_START_MCC: 5517 case H2C_FUNC_STOP_MCC: 5518 case H2C_FUNC_DEL_MCC_GROUP: 5519 case H2C_FUNC_RESET_MCC_GROUP: 5520 case H2C_FUNC_MCC_REQ_TSF: 5521 case H2C_FUNC_MCC_MACID_BITMAP: 5522 case H2C_FUNC_MCC_SYNC: 5523 case H2C_FUNC_MCC_SET_DURATION: 5524 break; 5525 default: 5526 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5527 "invalid MCC C2H RCV ACK: func %d\n", func); 5528 return; 5529 } 5530 5531 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5532 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 5533 } 5534 5535 static void 5536 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5537 { 5538 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 5539 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 5540 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 5541 struct rtw89_completion_data data = {}; 5542 unsigned int cond; 5543 bool next = false; 5544 5545 switch (func) { 5546 case H2C_FUNC_MCC_REQ_TSF: 5547 next = true; 5548 break; 5549 case H2C_FUNC_MCC_MACID_BITMAP: 5550 case H2C_FUNC_MCC_SYNC: 5551 case H2C_FUNC_MCC_SET_DURATION: 5552 break; 5553 case H2C_FUNC_ADD_MCC: 5554 case H2C_FUNC_START_MCC: 5555 case H2C_FUNC_STOP_MCC: 5556 case H2C_FUNC_DEL_MCC_GROUP: 5557 case H2C_FUNC_RESET_MCC_GROUP: 5558 default: 5559 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5560 "invalid MCC C2H REQ ACK: func %d\n", func); 5561 return; 5562 } 5563 5564 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5565 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5566 group, func, retcode); 5567 5568 if (!retcode && next) 5569 return; 5570 5571 data.err = !!retcode; 5572 cond = RTW89_MCC_WAIT_COND(group, func); 5573 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5574 } 5575 5576 static void 5577 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5578 { 5579 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5580 struct rtw89_completion_data data = {}; 5581 struct rtw89_mac_mcc_tsf_rpt *rpt; 5582 unsigned int cond; 5583 5584 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5585 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5586 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5587 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5588 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5589 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5590 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5591 5592 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5593 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5594 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5595 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5596 5597 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5598 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5599 } 5600 5601 static void 5602 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5603 { 5604 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5605 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5606 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5607 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5608 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5609 struct rtw89_completion_data data = {}; 5610 unsigned int cond; 5611 bool rsp = true; 5612 bool err; 5613 u8 func; 5614 5615 switch (status) { 5616 case RTW89_MAC_MCC_ADD_ROLE_OK: 5617 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5618 func = H2C_FUNC_ADD_MCC; 5619 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5620 break; 5621 case RTW89_MAC_MCC_START_GROUP_OK: 5622 case RTW89_MAC_MCC_START_GROUP_FAIL: 5623 func = H2C_FUNC_START_MCC; 5624 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5625 break; 5626 case RTW89_MAC_MCC_STOP_GROUP_OK: 5627 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5628 func = H2C_FUNC_STOP_MCC; 5629 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5630 break; 5631 case RTW89_MAC_MCC_DEL_GROUP_OK: 5632 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5633 func = H2C_FUNC_DEL_MCC_GROUP; 5634 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5635 break; 5636 case RTW89_MAC_MCC_RESET_GROUP_OK: 5637 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5638 func = H2C_FUNC_RESET_MCC_GROUP; 5639 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5640 break; 5641 case RTW89_MAC_MCC_SWITCH_CH_OK: 5642 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5643 case RTW89_MAC_MCC_TXNULL0_OK: 5644 case RTW89_MAC_MCC_TXNULL0_FAIL: 5645 case RTW89_MAC_MCC_TXNULL1_OK: 5646 case RTW89_MAC_MCC_TXNULL1_FAIL: 5647 case RTW89_MAC_MCC_SWITCH_EARLY: 5648 case RTW89_MAC_MCC_TBTT: 5649 case RTW89_MAC_MCC_DURATION_START: 5650 case RTW89_MAC_MCC_DURATION_END: 5651 rsp = false; 5652 break; 5653 default: 5654 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5655 "invalid MCC C2H STS RPT: status %d\n", status); 5656 return; 5657 } 5658 5659 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5660 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5661 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5662 5663 if (!rsp) 5664 return; 5665 5666 data.err = err; 5667 cond = RTW89_MCC_WAIT_COND(group, func); 5668 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5669 } 5670 5671 static void 5672 rtw89_mac_c2h_tx_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5673 { 5674 struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt; 5675 struct rtw89_tx_skb_data *skb_data; 5676 u8 sw_define, tx_status, txcnt; 5677 struct sk_buff *skb; 5678 5679 if (rtwdev->chip->chip_id == RTL8922A) { 5680 const struct rtw89_c2h_mac_tx_rpt_v2 *rpt_v2; 5681 5682 rpt_v2 = (const struct rtw89_c2h_mac_tx_rpt_v2 *)c2h->data; 5683 sw_define = le32_get_bits(rpt_v2->w12, 5684 RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2); 5685 tx_status = le32_get_bits(rpt_v2->w12, 5686 RTW89_C2H_MAC_TX_RPT_W12_TX_STATE_V2); 5687 txcnt = le32_get_bits(rpt_v2->w14, 5688 RTW89_C2H_MAC_TX_RPT_W14_DATA_TX_CNT_V2); 5689 } else { 5690 const struct rtw89_c2h_mac_tx_rpt *rpt; 5691 5692 rpt = (const struct rtw89_c2h_mac_tx_rpt *)c2h->data; 5693 sw_define = le32_get_bits(rpt->w2, RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE); 5694 tx_status = le32_get_bits(rpt->w2, RTW89_C2H_MAC_TX_RPT_W2_TX_STATE); 5695 if (rtwdev->chip->chip_id == RTL8852C) 5696 txcnt = le32_get_bits(rpt->w5, 5697 RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT_V1); 5698 else 5699 txcnt = le32_get_bits(rpt->w5, 5700 RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT); 5701 } 5702 5703 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 5704 "C2H TX RPT: sn %d, tx_status %d, txcnt %d\n", 5705 sw_define, tx_status, txcnt); 5706 5707 /* claim sw_define is not over size of tx_rpt->skbs[] */ 5708 static_assert(hweight32(RTW89_MAX_TX_RPTS_MASK) == 5709 hweight32(RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2) && 5710 hweight32(RTW89_MAX_TX_RPTS_MASK) == 5711 hweight32(RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE)); 5712 5713 scoped_guard(spinlock_irqsave, &tx_rpt->skb_lock) { 5714 skb = tx_rpt->skbs[sw_define]; 5715 5716 /* skip if no skb (normally shouldn't happen) */ 5717 if (!skb) { 5718 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 5719 "C2H TX RPT: no skb found in queue\n"); 5720 return; 5721 } 5722 5723 skb_data = RTW89_TX_SKB_CB(skb); 5724 5725 /* skip if TX attempt has failed and retry limit has not been 5726 * reached yet 5727 */ 5728 if (tx_status != RTW89_TX_DONE && 5729 txcnt != skb_data->tx_pkt_cnt_lmt) 5730 return; 5731 5732 tx_rpt->skbs[sw_define] = NULL; 5733 rtw89_tx_rpt_tx_status(rtwdev, skb, tx_status); 5734 } 5735 } 5736 5737 static void 5738 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5739 { 5740 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5741 const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5742 struct rtw89_completion_data data = {}; 5743 struct rtw89_mac_mrc_tsf_rpt *rpt; 5744 unsigned int i; 5745 5746 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5747 rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5748 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5749 le32_get_bits(c2h_rpt->w2, 5750 RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5751 5752 for (i = 0; i < rpt->num; i++) { 5753 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5754 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5755 5756 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5757 5758 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5759 "MRC C2H TSF RPT: index %u> %llu\n", 5760 i, rpt->tsfs[i]); 5761 } 5762 5763 rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5764 } 5765 5766 static void 5767 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5768 { 5769 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 5770 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 5771 struct rtw89_wait_info *wait = &rtw_wow->wait; 5772 const struct rtw89_c2h_wow_aoac_report *c2h = 5773 (const struct rtw89_c2h_wow_aoac_report *)skb->data; 5774 struct rtw89_completion_data data = {}; 5775 5776 aoac_rpt->rpt_ver = c2h->rpt_ver; 5777 aoac_rpt->sec_type = c2h->sec_type; 5778 aoac_rpt->key_idx = c2h->key_idx; 5779 aoac_rpt->pattern_idx = c2h->pattern_idx; 5780 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok, 5781 RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX); 5782 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv)); 5783 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count, 5784 sizeof(aoac_rpt->eapol_key_replay_count)); 5785 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk)); 5786 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv)); 5787 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv)); 5788 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id); 5789 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn); 5790 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk)); 5791 5792 rtw89_complete_cond(wait, RTW89_WOW_WAIT_COND_AOAC, &data); 5793 } 5794 5795 static void 5796 rtw89_mac_c2h_mlo_link_cfg_stat(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5797 { 5798 const struct rtw89_c2h_mlo_link_cfg_rpt *c2h_rpt; 5799 struct rtw89_wait_info *wait = &rtwdev->mlo.wait; 5800 struct rtw89_completion_data data = {}; 5801 unsigned int cond; 5802 u16 mac_id; 5803 u8 status; 5804 5805 c2h_rpt = (const struct rtw89_c2h_mlo_link_cfg_rpt *)c2h->data; 5806 5807 mac_id = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MLO_LINK_CFG_RPT_W2_MACID); 5808 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MLO_LINK_CFG_RPT_W2_STATUS); 5809 5810 data.err = status == RTW89_C2H_MLO_LINK_CFG_ROLE_NOT_EXIST || 5811 status == RTW89_C2H_MLO_LINK_CFG_RUNNING; 5812 cond = RTW89_MLO_WAIT_COND(mac_id, H2C_FUNC_MLO_LINK_CFG); 5813 rtw89_complete_cond(wait, cond, &data); 5814 } 5815 5816 static void 5817 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5818 { 5819 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5820 const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5821 struct rtw89_completion_data data = {}; 5822 enum rtw89_mac_mrc_status status; 5823 unsigned int cond; 5824 bool next = false; 5825 u32 tsf_high; 5826 u32 tsf_low; 5827 u8 sch_idx; 5828 u8 func; 5829 5830 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5831 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5832 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5833 tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5834 tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5835 5836 switch (status) { 5837 case RTW89_MAC_MRC_START_SCH_OK: 5838 func = H2C_FUNC_START_MRC; 5839 break; 5840 case RTW89_MAC_MRC_STOP_SCH_OK: 5841 /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5842 func = H2C_FUNC_DEL_MRC; 5843 next = true; 5844 break; 5845 case RTW89_MAC_MRC_DEL_SCH_OK: 5846 func = H2C_FUNC_DEL_MRC; 5847 break; 5848 case RTW89_MAC_MRC_EMPTY_SCH_FAIL: 5849 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5850 "MRC C2H STS RPT: empty sch fail\n"); 5851 return; 5852 case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL: 5853 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5854 "MRC C2H STS RPT: role not exist fail\n"); 5855 return; 5856 case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL: 5857 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5858 "MRC C2H STS RPT: data not found fail\n"); 5859 return; 5860 case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL: 5861 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5862 "MRC C2H STS RPT: get next slot fail\n"); 5863 return; 5864 case RTW89_MAC_MRC_ALT_ROLE_FAIL: 5865 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5866 "MRC C2H STS RPT: alt role fail\n"); 5867 return; 5868 case RTW89_MAC_MRC_ADD_PSTIMER_FAIL: 5869 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5870 "MRC C2H STS RPT: add ps timer fail\n"); 5871 return; 5872 case RTW89_MAC_MRC_MALLOC_FAIL: 5873 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5874 "MRC C2H STS RPT: malloc fail\n"); 5875 return; 5876 case RTW89_MAC_MRC_SWITCH_CH_FAIL: 5877 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5878 "MRC C2H STS RPT: switch ch fail\n"); 5879 return; 5880 case RTW89_MAC_MRC_TXNULL0_FAIL: 5881 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5882 "MRC C2H STS RPT: tx null-0 fail\n"); 5883 return; 5884 case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL: 5885 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5886 "MRC C2H STS RPT: port func en fail\n"); 5887 return; 5888 default: 5889 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5890 "invalid MRC C2H STS RPT: status %d\n", status); 5891 return; 5892 } 5893 5894 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5895 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 5896 sch_idx, status, (u64)tsf_high << 32 | tsf_low); 5897 5898 if (next) 5899 return; 5900 5901 cond = RTW89_MRC_WAIT_COND(sch_idx, func); 5902 rtw89_complete_cond(wait, cond, &data); 5903 } 5904 5905 static void 5906 rtw89_mac_c2h_pwr_int_notify(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5907 { 5908 const struct rtw89_c2h_pwr_int_notify *c2h; 5909 struct rtw89_sta_link *rtwsta_link; 5910 struct ieee80211_sta *sta; 5911 struct rtw89_sta *rtwsta; 5912 u16 macid; 5913 bool ps; 5914 5915 c2h = (const struct rtw89_c2h_pwr_int_notify *)skb->data; 5916 macid = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_MACID); 5917 ps = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS); 5918 5919 rcu_read_lock(); 5920 5921 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 5922 if (unlikely(!rtwsta_link)) 5923 goto out; 5924 5925 rtwsta = rtwsta_link->rtwsta; 5926 if (ps) 5927 set_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5928 else 5929 clear_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5930 5931 sta = rtwsta_to_sta(rtwsta); 5932 ieee80211_sta_ps_transition(sta, ps); 5933 5934 out: 5935 rcu_read_unlock(); 5936 } 5937 5938 static 5939 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5940 struct sk_buff *c2h, u32 len) = { 5941 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5942 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5943 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5944 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = rtw89_mac_c2h_bcn_resend, 5945 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5946 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5947 [RTW89_MAC_C2H_FUNC_TX_DUTY_RPT] = rtw89_mac_c2h_tx_duty_rpt, 5948 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5949 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5950 }; 5951 5952 static 5953 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5954 struct sk_buff *c2h, u32 len) = { 5955 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5956 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5957 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5958 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5959 [RTW89_MAC_C2H_FUNC_BCN_UPD_DONE] = rtw89_mac_c2h_bcn_upd_done, 5960 }; 5961 5962 static 5963 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5964 struct sk_buff *c2h, u32 len) = { 5965 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5966 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5967 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5968 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5969 }; 5970 5971 static 5972 void (* const rtw89_mac_c2h_misc_handler[])(struct rtw89_dev *rtwdev, 5973 struct sk_buff *c2h, u32 len) = { 5974 [RTW89_MAC_C2H_FUNC_TX_REPORT] = rtw89_mac_c2h_tx_rpt, 5975 }; 5976 5977 static 5978 void (* const rtw89_mac_c2h_mlo_handler[])(struct rtw89_dev *rtwdev, 5979 struct sk_buff *c2h, u32 len) = { 5980 [RTW89_MAC_C2H_FUNC_MLO_GET_TBL] = NULL, 5981 [RTW89_MAC_C2H_FUNC_MLO_EMLSR_TRANS_DONE] = NULL, 5982 [RTW89_MAC_C2H_FUNC_MLO_EMLSR_STA_CFG_DONE] = NULL, 5983 [RTW89_MAC_C2H_FUNC_MCMLO_RELINK_RPT] = NULL, 5984 [RTW89_MAC_C2H_FUNC_MCMLO_SN_SYNC_RPT] = NULL, 5985 [RTW89_MAC_C2H_FUNC_MLO_LINK_CFG_STAT] = rtw89_mac_c2h_mlo_link_cfg_stat, 5986 [RTW89_MAC_C2H_FUNC_MLO_DM_DBG_DUMP] = NULL, 5987 }; 5988 5989 static 5990 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 5991 struct sk_buff *c2h, u32 len) = { 5992 [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 5993 [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 5994 }; 5995 5996 static 5997 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev, 5998 struct sk_buff *c2h, u32 len) = { 5999 [RTW89_MAC_C2H_FUNC_AOAC_REPORT] = rtw89_mac_c2h_wow_aoac_rpt, 6000 }; 6001 6002 static 6003 void (* const rtw89_mac_c2h_ap_handler[])(struct rtw89_dev *rtwdev, 6004 struct sk_buff *c2h, u32 len) = { 6005 [RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY] = rtw89_mac_c2h_pwr_int_notify, 6006 }; 6007 6008 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 6009 struct sk_buff *skb) 6010 { 6011 const struct rtw89_c2h_scanofld *c2h = 6012 (const struct rtw89_c2h_scanofld *)skb->data; 6013 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 6014 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 6015 struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(skb); 6016 struct rtw89_completion_data data = {}; 6017 unsigned int cond; 6018 u8 status, reason; 6019 6020 attr->is_scan_event = 1; 6021 attr->scan_seq = scan_info->seq; 6022 6023 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 6024 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 6025 data.err = status != RTW89_SCAN_STATUS_SUCCESS; 6026 6027 if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 6028 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 6029 cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 6030 else 6031 cond = RTW89_SCANOFLD_WAIT_COND_STOP; 6032 6033 rtw89_complete_cond(fw_ofld_wait, cond, &data); 6034 } 6035 } 6036 6037 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 6038 u8 class, u8 func) 6039 { 6040 switch (class) { 6041 default: 6042 return false; 6043 case RTW89_MAC_C2H_CLASS_INFO: 6044 switch (func) { 6045 default: 6046 return false; 6047 case RTW89_MAC_C2H_FUNC_REC_ACK: 6048 case RTW89_MAC_C2H_FUNC_DONE_ACK: 6049 return true; 6050 } 6051 case RTW89_MAC_C2H_CLASS_OFLD: 6052 switch (func) { 6053 default: 6054 return false; 6055 case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 6056 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 6057 return false; 6058 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 6059 return true; 6060 } 6061 case RTW89_MAC_C2H_CLASS_MCC: 6062 return true; 6063 case RTW89_MAC_C2H_CLASS_MISC: 6064 return true; 6065 case RTW89_MAC_C2H_CLASS_MLO: 6066 return true; 6067 case RTW89_MAC_C2H_CLASS_MRC: 6068 return true; 6069 case RTW89_MAC_C2H_CLASS_WOW: 6070 return true; 6071 case RTW89_MAC_C2H_CLASS_AP: 6072 switch (func) { 6073 default: 6074 return false; 6075 case RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY: 6076 return true; 6077 } 6078 } 6079 } 6080 6081 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6082 u32 len, u8 class, u8 func) 6083 { 6084 void (*handler)(struct rtw89_dev *rtwdev, 6085 struct sk_buff *c2h, u32 len) = NULL; 6086 6087 switch (class) { 6088 case RTW89_MAC_C2H_CLASS_INFO: 6089 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 6090 handler = rtw89_mac_c2h_info_handler[func]; 6091 break; 6092 case RTW89_MAC_C2H_CLASS_OFLD: 6093 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 6094 handler = rtw89_mac_c2h_ofld_handler[func]; 6095 break; 6096 case RTW89_MAC_C2H_CLASS_MCC: 6097 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 6098 handler = rtw89_mac_c2h_mcc_handler[func]; 6099 break; 6100 case RTW89_MAC_C2H_CLASS_MISC: 6101 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MISC) 6102 handler = rtw89_mac_c2h_misc_handler[func]; 6103 break; 6104 case RTW89_MAC_C2H_CLASS_MLO: 6105 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MLO) 6106 handler = rtw89_mac_c2h_mlo_handler[func]; 6107 break; 6108 case RTW89_MAC_C2H_CLASS_MRC: 6109 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 6110 handler = rtw89_mac_c2h_mrc_handler[func]; 6111 break; 6112 case RTW89_MAC_C2H_CLASS_WOW: 6113 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_WOW) 6114 handler = rtw89_mac_c2h_wow_handler[func]; 6115 break; 6116 case RTW89_MAC_C2H_CLASS_AP: 6117 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_AP) 6118 handler = rtw89_mac_c2h_ap_handler[func]; 6119 break; 6120 case RTW89_MAC_C2H_CLASS_FWDBG: 6121 case RTW89_MAC_C2H_CLASS_ROLE: 6122 return; 6123 default: 6124 break; 6125 } 6126 if (!handler) { 6127 rtw89_info_once(rtwdev, "MAC c2h class %d func %d not support\n", 6128 class, func); 6129 return; 6130 } 6131 handler(rtwdev, skb, len); 6132 } 6133 6134 static 6135 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 6136 enum rtw89_phy_idx phy_idx, 6137 u32 reg_base, u32 *cr) 6138 { 6139 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 6140 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 6141 6142 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 6143 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 6144 addr); 6145 goto error; 6146 } 6147 6148 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 6149 if (mode == RTW89_QTA_SCC) { 6150 rtw89_err(rtwdev, 6151 "[TXPWR] addr=0x%x but hw not enable\n", 6152 addr); 6153 goto error; 6154 } 6155 6156 *cr = addr; 6157 return true; 6158 6159 error: 6160 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 6161 addr, phy_idx); 6162 6163 return false; 6164 } 6165 6166 static 6167 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 6168 { 6169 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 6170 int ret; 6171 6172 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6173 if (ret) 6174 return ret; 6175 6176 if (!enable) { 6177 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 6178 return 0; 6179 } 6180 6181 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 6182 B_AX_APP_MAC_INFO_RPT | 6183 B_AX_APP_PLCP_HDR_RPT | 6184 B_AX_PPDU_STAT_RPT_CRC32); 6185 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 6186 RTW89_PRPT_DEST_HOST); 6187 6188 return 0; 6189 } 6190 6191 static 6192 void __rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 6193 { 6194 #define MAC_AX_TIME_TH_SH 5 6195 #define MAC_AX_LEN_TH_SH 4 6196 #define MAC_AX_TIME_TH_MAX 255 6197 #define MAC_AX_LEN_TH_MAX 255 6198 #define MAC_AX_TIME_TH_DEF 88 6199 #define MAC_AX_LEN_TH_DEF 4080 6200 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6201 struct ieee80211_hw *hw = rtwdev->hw; 6202 u32 rts_threshold = hw->wiphy->rts_threshold; 6203 u32 time_th, len_th; 6204 u32 reg; 6205 6206 if (rts_threshold == (u32)-1) { 6207 time_th = MAC_AX_TIME_TH_DEF; 6208 len_th = MAC_AX_LEN_TH_DEF; 6209 } else { 6210 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 6211 len_th = rts_threshold; 6212 } 6213 6214 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 6215 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 6216 6217 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 6218 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 6219 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 6220 } 6221 6222 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev) 6223 { 6224 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 6225 if (rtwdev->dbcc_en) 6226 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_1); 6227 } 6228 6229 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 6230 { 6231 bool empty; 6232 int ret; 6233 6234 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6235 return; 6236 6237 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 6238 10000, 200000, false, rtwdev); 6239 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 6240 rtw89_info(rtwdev, "timed out to flush queues\n"); 6241 } 6242 6243 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 6244 { 6245 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 6246 u8 val; 6247 u16 val16; 6248 u32 val32; 6249 int ret; 6250 6251 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 6252 if (chip_id != RTL8851B && chip_id != RTL8852BT) 6253 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 6254 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 6255 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 6256 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 6257 if (chip_id != RTL8851B && chip_id != RTL8852BT) 6258 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 6259 6260 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 6261 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 6262 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 6263 6264 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 6265 if (ret) { 6266 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6267 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 6268 return ret; 6269 } 6270 val32 = val32 & B_AX_WL_RX_CTRL; 6271 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 6272 if (ret) { 6273 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6274 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 6275 return ret; 6276 } 6277 6278 switch (coex->pta_mode) { 6279 case RTW89_MAC_AX_COEX_RTK_MODE: 6280 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 6281 val &= ~B_AX_BTMODE_MASK; 6282 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 6283 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 6284 6285 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 6286 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 6287 6288 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 6289 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 6290 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 6291 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 6292 break; 6293 case RTW89_MAC_AX_COEX_CSR_MODE: 6294 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 6295 val &= ~B_AX_BTMODE_MASK; 6296 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 6297 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 6298 6299 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 6300 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 6301 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 6302 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 6303 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 6304 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 6305 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 6306 val16 |= B_AX_ENHANCED_BT; 6307 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 6308 6309 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 6310 break; 6311 default: 6312 return -EINVAL; 6313 } 6314 6315 switch (coex->direction) { 6316 case RTW89_MAC_AX_COEX_INNER: 6317 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6318 val = (val & ~BIT(2)) | BIT(1); 6319 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6320 break; 6321 case RTW89_MAC_AX_COEX_OUTPUT: 6322 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6323 val = val | BIT(1) | BIT(0); 6324 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6325 break; 6326 case RTW89_MAC_AX_COEX_INPUT: 6327 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6328 val = val & ~(BIT(2) | BIT(1)); 6329 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6330 break; 6331 default: 6332 return -EINVAL; 6333 } 6334 6335 return 0; 6336 } 6337 EXPORT_SYMBOL(rtw89_mac_coex_init); 6338 6339 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 6340 const struct rtw89_mac_ax_coex *coex) 6341 { 6342 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 6343 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 6344 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 6345 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 6346 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 6347 6348 switch (coex->pta_mode) { 6349 case RTW89_MAC_AX_COEX_RTK_MODE: 6350 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 6351 MAC_AX_RTK_MODE); 6352 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 6353 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 6354 break; 6355 case RTW89_MAC_AX_COEX_CSR_MODE: 6356 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 6357 MAC_AX_CSR_MODE); 6358 break; 6359 default: 6360 return -EINVAL; 6361 } 6362 6363 return 0; 6364 } 6365 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 6366 6367 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6368 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6369 { 6370 u32 val = 0, ret; 6371 6372 if (gnt_cfg->band[0].gnt_bt) 6373 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 6374 6375 if (gnt_cfg->band[0].gnt_bt_sw_en) 6376 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 6377 6378 if (gnt_cfg->band[0].gnt_wl) 6379 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 6380 6381 if (gnt_cfg->band[0].gnt_wl_sw_en) 6382 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 6383 6384 if (gnt_cfg->band[1].gnt_bt) 6385 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 6386 6387 if (gnt_cfg->band[1].gnt_bt_sw_en) 6388 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 6389 6390 if (gnt_cfg->band[1].gnt_wl) 6391 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 6392 6393 if (gnt_cfg->band[1].gnt_wl_sw_en) 6394 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 6395 6396 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 6397 if (ret) { 6398 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6399 rtw89_err(rtwdev, "Write LTE fail!\n"); 6400 return ret; 6401 } 6402 6403 return 0; 6404 } 6405 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 6406 6407 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 6408 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6409 { 6410 u32 val = 0; 6411 6412 if (gnt_cfg->band[0].gnt_bt) 6413 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 6414 B_AX_GNT_BT_TX_VAL; 6415 else 6416 val |= B_AX_WL_ACT_VAL; 6417 6418 if (gnt_cfg->band[0].gnt_bt_sw_en) 6419 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 6420 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 6421 6422 if (gnt_cfg->band[0].gnt_wl) 6423 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 6424 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 6425 6426 if (gnt_cfg->band[0].gnt_wl_sw_en) 6427 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 6428 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 6429 6430 if (gnt_cfg->band[1].gnt_bt) 6431 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 6432 B_AX_GNT_BT_TX_VAL; 6433 else 6434 val |= B_AX_WL_ACT_VAL; 6435 6436 if (gnt_cfg->band[1].gnt_bt_sw_en) 6437 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 6438 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 6439 6440 if (gnt_cfg->band[1].gnt_wl) 6441 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 6442 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 6443 6444 if (gnt_cfg->band[1].gnt_wl_sw_en) 6445 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 6446 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 6447 6448 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 6449 6450 return 0; 6451 } 6452 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 6453 6454 static 6455 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 6456 { 6457 u32 reg; 6458 u16 val; 6459 int ret; 6460 6461 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 6462 if (ret) 6463 return ret; 6464 6465 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 6466 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 6467 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 6468 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 6469 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 6470 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 6471 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 6472 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 6473 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 6474 B_AX_PLT_EN; 6475 rtw89_write16(rtwdev, reg, val); 6476 6477 return 0; 6478 } 6479 6480 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 6481 { 6482 const struct rtw89_chip_info *chip = rtwdev->chip; 6483 u32 reg = chip->btc_sb.n[0].cfg; 6484 u32 fw_sb; 6485 6486 fw_sb = rtw89_read32(rtwdev, reg); 6487 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 6488 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 6489 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6490 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 6491 else 6492 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 6493 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 6494 val = B_AX_TOGGLE | 6495 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 6496 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 6497 rtw89_write32(rtwdev, reg, val); 6498 fsleep(1000); /* avoid BT FW loss information */ 6499 } 6500 6501 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 6502 { 6503 const struct rtw89_chip_info *chip = rtwdev->chip; 6504 u32 reg = chip->btc_sb.n[0].get; 6505 6506 return rtw89_read32(rtwdev, reg); 6507 } 6508 6509 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6510 { 6511 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 6512 6513 val = wl ? val | BIT(2) : val & ~BIT(2); 6514 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 6515 6516 return 0; 6517 } 6518 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 6519 6520 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 6521 { 6522 struct rtw89_btc *btc = &rtwdev->btc; 6523 struct rtw89_btc_dm *dm = &btc->dm; 6524 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 6525 int i; 6526 6527 if (wl) 6528 return 0; 6529 6530 for (i = 0; i < RTW89_PHY_NUM; i++) { 6531 g[i].gnt_bt_sw_en = 1; 6532 g[i].gnt_bt = 1; 6533 g[i].gnt_wl_sw_en = 1; 6534 g[i].gnt_wl = 0; 6535 } 6536 6537 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 6538 } 6539 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 6540 6541 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 6542 { 6543 const struct rtw89_chip_info *chip = rtwdev->chip; 6544 u8 val = 0; 6545 6546 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) 6547 return false; 6548 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6549 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 6550 B_AX_LTE_MUX_CTRL_PATH >> 24); 6551 6552 return !!val; 6553 } 6554 6555 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 6556 { 6557 u32 reg; 6558 u16 cnt; 6559 6560 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 6561 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 6562 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 6563 6564 return cnt; 6565 } 6566 6567 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 6568 bool keep) 6569 { 6570 u32 reg; 6571 6572 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 6573 return; 6574 6575 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 6576 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6577 if (keep) { 6578 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6579 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6580 BFRP_RX_STANDBY_TIMER_KEEP); 6581 } else { 6582 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6583 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6584 BFRP_RX_STANDBY_TIMER_RELEASE); 6585 } 6586 } 6587 6588 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 6589 { 6590 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6591 u32 reg; 6592 u32 mask = mac->bfee_ctrl.mask; 6593 6594 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 6595 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 6596 if (en) { 6597 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6598 rtw89_write32_set(rtwdev, reg, mask); 6599 } else { 6600 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6601 rtw89_write32_clr(rtwdev, reg, mask); 6602 } 6603 } 6604 6605 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 6606 { 6607 u32 reg; 6608 u32 val32; 6609 int ret; 6610 6611 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6612 if (ret) 6613 return ret; 6614 6615 /* AP mode set tx gid to 63 */ 6616 /* STA mode set tx gid to 0(default) */ 6617 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 6618 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 6619 6620 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 6621 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 6622 6623 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6624 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 6625 rtw89_write32(rtwdev, reg, val32); 6626 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 6627 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 6628 6629 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6630 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 6631 B_AX_BFMEE_USE_NSTS | 6632 B_AX_BFMEE_CSI_GID_SEL | 6633 B_AX_BFMEE_CSI_FORCE_RETE_EN); 6634 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 6635 rtw89_write32(rtwdev, reg, 6636 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 6637 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 6638 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 6639 6640 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 6641 rtw89_write32_set(rtwdev, reg, 6642 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 6643 6644 return 0; 6645 } 6646 6647 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 6648 struct rtw89_vif_link *rtwvif_link, 6649 struct rtw89_sta_link *rtwsta_link) 6650 { 6651 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 6652 struct ieee80211_link_sta *link_sta; 6653 u8 mac_idx = rtwvif_link->mac_idx; 6654 u8 port_sel = rtwvif_link->port; 6655 u8 sound_dim = 3, t; 6656 u8 *phy_cap; 6657 u32 reg; 6658 u16 val; 6659 int ret; 6660 6661 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6662 if (ret) 6663 return ret; 6664 6665 rcu_read_lock(); 6666 6667 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6668 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; 6669 6670 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6671 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 6672 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 6673 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 6674 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 6675 phy_cap[5]); 6676 sound_dim = min(sound_dim, t); 6677 } 6678 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6679 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 6680 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 6681 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 6682 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 6683 link_sta->vht_cap.cap); 6684 sound_dim = min(sound_dim, t); 6685 } 6686 nc = min(nc, sound_dim); 6687 nr = min(nr, sound_dim); 6688 6689 rcu_read_unlock(); 6690 6691 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6692 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6693 6694 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 6695 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 6696 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 6697 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 6698 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 6699 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 6700 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 6701 6702 if (port_sel == 0) 6703 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6704 else 6705 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 6706 6707 rtw89_write16(rtwdev, reg, val); 6708 6709 return 0; 6710 } 6711 6712 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 6713 struct rtw89_vif_link *rtwvif_link, 6714 struct rtw89_sta_link *rtwsta_link) 6715 { 6716 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 6717 struct ieee80211_link_sta *link_sta; 6718 u8 mac_idx = rtwvif_link->mac_idx; 6719 u32 reg; 6720 int ret; 6721 6722 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6723 if (ret) 6724 return ret; 6725 6726 rcu_read_lock(); 6727 6728 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6729 6730 if (link_sta->he_cap.has_he) { 6731 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 6732 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 6733 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 6734 } 6735 if (link_sta->vht_cap.vht_supported) { 6736 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 6737 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 6738 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 6739 } 6740 if (link_sta->ht_cap.ht_supported) { 6741 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 6742 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 6743 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 6744 } 6745 6746 rcu_read_unlock(); 6747 6748 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6749 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6750 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 6751 rtw89_write32(rtwdev, 6752 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 6753 rrsc); 6754 6755 return 0; 6756 } 6757 6758 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 6759 struct rtw89_vif_link *rtwvif_link, 6760 struct rtw89_sta_link *rtwsta_link) 6761 { 6762 struct ieee80211_link_sta *link_sta; 6763 bool has_beamformer_cap; 6764 6765 rcu_read_lock(); 6766 6767 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6768 has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta); 6769 6770 rcu_read_unlock(); 6771 6772 if (has_beamformer_cap) { 6773 rtw89_debug(rtwdev, RTW89_DBG_BF, 6774 "initialize bfee for new association\n"); 6775 rtw89_mac_init_bfee_ax(rtwdev, rtwvif_link->mac_idx); 6776 rtw89_mac_set_csi_para_reg_ax(rtwdev, rtwvif_link, rtwsta_link); 6777 rtw89_mac_csi_rrsc_ax(rtwdev, rtwvif_link, rtwsta_link); 6778 } 6779 } 6780 6781 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, 6782 struct rtw89_vif_link *rtwvif_link, 6783 struct rtw89_sta_link *rtwsta_link) 6784 { 6785 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, false); 6786 } 6787 6788 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6789 struct ieee80211_bss_conf *conf) 6790 { 6791 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6792 const struct rtw89_mac_mu_gid_addr *addr = mac->mu_gid; 6793 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 6794 struct rtw89_vif_link *rtwvif_link; 6795 u8 mac_idx; 6796 __le32 *p; 6797 6798 rtwvif_link = rtwvif->links[conf->link_id]; 6799 if (unlikely(!rtwvif_link)) { 6800 rtw89_err(rtwdev, 6801 "%s: rtwvif link (link_id %u) is not active\n", 6802 __func__, conf->link_id); 6803 return; 6804 } 6805 6806 mac_idx = rtwvif_link->mac_idx; 6807 6808 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 6809 6810 p = (__le32 *)conf->mu_group.membership; 6811 rtw89_write32(rtwdev, 6812 rtw89_mac_reg_by_idx(rtwdev, addr->position_en[0], mac_idx), 6813 le32_to_cpu(p[0])); 6814 rtw89_write32(rtwdev, 6815 rtw89_mac_reg_by_idx(rtwdev, addr->position_en[1], mac_idx), 6816 le32_to_cpu(p[1])); 6817 6818 p = (__le32 *)conf->mu_group.position; 6819 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[0], mac_idx), 6820 le32_to_cpu(p[0])); 6821 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[1], mac_idx), 6822 le32_to_cpu(p[1])); 6823 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[2], mac_idx), 6824 le32_to_cpu(p[2])); 6825 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[3], mac_idx), 6826 le32_to_cpu(p[3])); 6827 } 6828 6829 struct rtw89_mac_bf_monitor_iter_data { 6830 struct rtw89_dev *rtwdev; 6831 struct rtw89_sta_link *down_rtwsta_link; 6832 int count; 6833 }; 6834 6835 static 6836 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 6837 { 6838 struct rtw89_mac_bf_monitor_iter_data *iter_data = 6839 (struct rtw89_mac_bf_monitor_iter_data *)data; 6840 struct rtw89_sta_link *down_rtwsta_link = iter_data->down_rtwsta_link; 6841 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6842 struct ieee80211_link_sta *link_sta; 6843 struct rtw89_sta_link *rtwsta_link; 6844 bool has_beamformer_cap = false; 6845 int *count = &iter_data->count; 6846 unsigned int link_id; 6847 6848 rcu_read_lock(); 6849 6850 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6851 if (rtwsta_link == down_rtwsta_link) 6852 continue; 6853 6854 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 6855 if (rtw89_sta_has_beamformer_cap(link_sta)) { 6856 has_beamformer_cap = true; 6857 break; 6858 } 6859 } 6860 6861 if (has_beamformer_cap) 6862 (*count)++; 6863 6864 rcu_read_unlock(); 6865 } 6866 6867 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 6868 struct rtw89_sta_link *rtwsta_link, 6869 bool disconnect) 6870 { 6871 struct rtw89_mac_bf_monitor_iter_data data; 6872 6873 data.rtwdev = rtwdev; 6874 data.down_rtwsta_link = disconnect ? rtwsta_link : NULL; 6875 data.count = 0; 6876 ieee80211_iterate_stations_atomic(rtwdev->hw, 6877 rtw89_mac_bf_monitor_calc_iter, 6878 &data); 6879 6880 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 6881 if (data.count) 6882 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6883 else 6884 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6885 } 6886 6887 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 6888 { 6889 struct rtw89_traffic_stats *stats = &rtwdev->stats; 6890 struct rtw89_vif_link *rtwvif_link; 6891 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 6892 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6893 struct rtw89_vif *rtwvif; 6894 bool keep_timer = true; 6895 unsigned int link_id; 6896 bool old_keep_timer; 6897 6898 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6899 6900 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 6901 keep_timer = false; 6902 6903 if (keep_timer != old_keep_timer) { 6904 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6905 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6906 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif_link->mac_idx, 6907 keep_timer); 6908 } 6909 6910 if (en == old) 6911 return; 6912 6913 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6914 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6915 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, en); 6916 } 6917 6918 static int 6919 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6920 u32 tx_time) 6921 { 6922 #define MAC_AX_DFLT_TX_TIME 5280 6923 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6924 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6925 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 6926 u32 reg; 6927 int ret = 0; 6928 6929 if (rtwsta_link->cctl_tx_time) { 6930 rtwsta_link->ampdu_max_time = (max_tx_time - 512) >> 9; 6931 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6932 } else { 6933 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6934 if (ret) { 6935 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 6936 return ret; 6937 } 6938 6939 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_limit.addr, mac_idx); 6940 rtw89_write32_mask(rtwdev, reg, mac->agg_limit.mask, 6941 max_tx_time >> 5); 6942 } 6943 6944 return ret; 6945 } 6946 6947 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6948 bool resume, u32 tx_time) 6949 { 6950 int ret = 0; 6951 6952 if (!resume) { 6953 rtwsta_link->cctl_tx_time = true; 6954 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6955 } else { 6956 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6957 rtwsta_link->cctl_tx_time = false; 6958 } 6959 6960 return ret; 6961 } 6962 6963 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6964 u32 *tx_time) 6965 { 6966 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6967 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6968 u32 reg; 6969 int ret = 0; 6970 6971 if (rtwsta_link->cctl_tx_time) { 6972 *tx_time = (rtwsta_link->ampdu_max_time + 1) << 9; 6973 } else { 6974 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6975 if (ret) { 6976 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 6977 return ret; 6978 } 6979 6980 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_limit.addr, mac_idx); 6981 *tx_time = rtw89_read32_mask(rtwdev, reg, mac->agg_limit.mask) << 5; 6982 } 6983 6984 return ret; 6985 } 6986 6987 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 6988 struct rtw89_sta_link *rtwsta_link, 6989 bool resume, u8 tx_retry) 6990 { 6991 int ret = 0; 6992 6993 rtwsta_link->data_tx_cnt_lmt = tx_retry; 6994 6995 if (!resume) { 6996 rtwsta_link->cctl_tx_retry_limit = true; 6997 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6998 } else { 6999 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 7000 rtwsta_link->cctl_tx_retry_limit = false; 7001 } 7002 7003 return ret; 7004 } 7005 7006 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 7007 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry) 7008 { 7009 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7010 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 7011 u32 reg; 7012 int ret = 0; 7013 7014 if (rtwsta_link->cctl_tx_retry_limit) { 7015 *tx_retry = rtwsta_link->data_tx_cnt_lmt; 7016 } else { 7017 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 7018 if (ret) { 7019 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 7020 return ret; 7021 } 7022 7023 reg = rtw89_mac_reg_by_idx(rtwdev, mac->txcnt_limit.addr, mac_idx); 7024 *tx_retry = rtw89_read32_mask(rtwdev, reg, mac->txcnt_limit.mask); 7025 } 7026 7027 return ret; 7028 } 7029 7030 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 7031 struct rtw89_vif_link *rtwvif_link, bool en) 7032 { 7033 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7034 u8 mac_idx = rtwvif_link->mac_idx; 7035 u16 set = mac->muedca_ctrl.mask; 7036 u32 reg; 7037 int ret; 7038 7039 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 7040 if (ret) 7041 return ret; 7042 7043 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 7044 if (en) 7045 rtw89_write16_set(rtwdev, reg, set); 7046 else 7047 rtw89_write16_clr(rtwdev, reg, set); 7048 7049 return 0; 7050 } 7051 7052 static 7053 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 7054 { 7055 u32 val32; 7056 int ret; 7057 7058 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 7059 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 7060 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 7061 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 7062 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 7063 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 7064 7065 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 7066 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 7067 if (ret) { 7068 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 7069 offset, val, mask); 7070 return ret; 7071 } 7072 7073 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) && 7074 (u32_get_bits(val32, B_AX_WL_XTAL_SI_ADDR_MASK) != offset || 7075 u32_get_bits(val32, B_AX_WL_XTAL_SI_DATA_MASK) != val)) 7076 rtw89_warn(rtwdev, "xtal si write: offset=%x val=%x poll=%x\n", 7077 offset, val, val32); 7078 7079 return 0; 7080 } 7081 7082 static 7083 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 7084 { 7085 u32 val32; 7086 int ret; 7087 7088 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 7089 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 7090 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 7091 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 7092 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 7093 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 7094 7095 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 7096 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 7097 if (ret) { 7098 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 7099 return ret; 7100 } 7101 7102 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) && 7103 u32_get_bits(val32, B_AX_WL_XTAL_SI_ADDR_MASK) != offset) 7104 rtw89_warn(rtwdev, "xtal si read: offset=%x poll=%x\n", 7105 offset, val32); 7106 7107 *val = u32_get_bits(val32, B_AX_WL_XTAL_SI_DATA_MASK); 7108 7109 return 0; 7110 } 7111 7112 static 7113 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, 7114 struct rtw89_vif_link *rtwvif_link, 7115 struct rtw89_sta_link *rtwsta_link) 7116 { 7117 static const enum rtw89_pkt_drop_sel sels[] = { 7118 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 7119 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 7120 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 7121 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 7122 }; 7123 struct rtw89_pkt_drop_params params = {0}; 7124 int i; 7125 7126 params.mac_band = rtwvif_link->mac_idx; 7127 params.macid = rtwsta_link->mac_id; 7128 params.port = rtwvif_link->port; 7129 params.mbssid = 0; 7130 params.tf_trs = rtwvif_link->trigger; 7131 7132 for (i = 0; i < ARRAY_SIZE(sels); i++) { 7133 params.sel = sels[i]; 7134 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 7135 } 7136 } 7137 7138 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 7139 { 7140 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 7141 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 7142 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 7143 struct rtw89_vif_link *rtwvif_link; 7144 struct rtw89_sta_link *rtwsta_link; 7145 struct rtw89_vif *target = data; 7146 unsigned int link_id; 7147 7148 if (rtwvif != target) 7149 return; 7150 7151 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 7152 rtwvif_link = rtwsta_link->rtwvif_link; 7153 rtw89_mac_pkt_drop_sta(rtwdev, rtwvif_link, rtwsta_link); 7154 } 7155 } 7156 7157 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 7158 { 7159 ieee80211_iterate_stations_atomic(rtwdev->hw, 7160 rtw89_mac_pkt_drop_vif_iter, 7161 rtwvif); 7162 } 7163 7164 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 7165 enum rtw89_mac_idx band) 7166 { 7167 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7168 struct rtw89_pkt_drop_params params = {0}; 7169 bool empty; 7170 int i, ret = 0, try_cnt = 3; 7171 7172 params.mac_band = band; 7173 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 7174 7175 for (i = 0; i < try_cnt; i++) { 7176 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 7177 50000, false, rtwdev); 7178 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 7179 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 7180 else 7181 return 0; 7182 } 7183 return ret; 7184 } 7185 7186 static int _rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 7187 { 7188 struct rtw89_mac_h2c_info h2c_info = {}; 7189 struct rtw89_mac_c2h_info c2h_info = {}; 7190 int ret; 7191 7192 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 7193 return 0; 7194 7195 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; 7196 h2c_info.content_len = sizeof(h2c_info.u.hdr); 7197 h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); 7198 7199 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 7200 if (ret) 7201 return ret; 7202 7203 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) 7204 ret = -EINVAL; 7205 7206 return ret; 7207 } 7208 7209 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 7210 { 7211 int i, ret; 7212 7213 for (i = 0; i < CPU_IO_RX_RETRY_CNT; i++) { 7214 ret = _rtw89_mac_cpu_io_rx(rtwdev, wow_enable); 7215 if (!ret) 7216 return 0; 7217 } 7218 7219 return ret; 7220 } 7221 7222 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 7223 { 7224 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7225 const struct rtw89_chip_info *chip = rtwdev->chip; 7226 int ret; 7227 7228 if (enable_wow) { 7229 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 7230 if (ret) { 7231 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 7232 return ret; 7233 } 7234 7235 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 7236 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 7237 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 7238 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 7239 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 7240 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 7241 rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 7242 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 7243 7244 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 7245 return 0; 7246 7247 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 7248 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 7249 else 7250 rtw89_write32_set(rtwdev, R_AX_DBG_WOW, 7251 B_AX_DBG_WOW_CPU_IO_RX_EN); 7252 } else { 7253 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 7254 if (ret) { 7255 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 7256 return ret; 7257 } 7258 7259 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 7260 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 7261 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 7262 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 7263 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 7264 } 7265 7266 return 0; 7267 } 7268 7269 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 7270 { 7271 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 7272 7273 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 7274 } 7275 7276 static 7277 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 7278 bool h2c_or_fwdl) 7279 { 7280 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 7281 u32 timeout; 7282 u8 val; 7283 7284 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 7285 timeout = FWDL_WAIT_CNT_USB; 7286 else 7287 timeout = FWDL_WAIT_CNT; 7288 7289 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 7290 1, timeout, false, 7291 rtwdev, R_AX_WCPU_FW_CTRL); 7292 } 7293 7294 static 7295 void rtw89_fwdl_secure_idmem_share_mode_ax(struct rtw89_dev *rtwdev, u8 mode) 7296 { 7297 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 7298 7299 if (!sec->secure_boot) 7300 return; 7301 7302 rtw89_write32_mask(rtwdev, R_AX_WCPU_FW_CTRL, 7303 B_AX_IDMEM_SHARE_MODE_RECORD_MASK, mode); 7304 rtw89_write32_set(rtwdev, R_AX_WCPU_FW_CTRL, 7305 B_AX_IDMEM_SHARE_MODE_RECORD_VALID); 7306 } 7307 7308 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 7309 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 7310 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 7311 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 7312 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 7313 .mem_page_size = MAC_MEM_DUMP_PAGE_SIZE_AX, 7314 .rx_fltr = R_AX_RX_FLTR_OPT, 7315 .port_base = &rtw89_port_base_ax, 7316 .agg_len_ht = R_AX_AGG_LEN_HT_0, 7317 .ps_status = R_AX_PPWRBIT_SETTING, 7318 .mu_gid = &rtw89_mac_mu_gid_addr_ax, 7319 7320 .muedca_ctrl = { 7321 .addr = R_AX_MUEDCA_EN, 7322 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 7323 }, 7324 .bfee_ctrl = { 7325 .addr = R_AX_BFMEE_RESP_OPTION, 7326 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 7327 B_AX_BFMEE_HE_NDPA_EN, 7328 }, 7329 .narrow_bw_ru_dis = { 7330 .addr = R_AX_RXTRIG_TEST_USER_2, 7331 .mask = B_AX_RXTRIG_RU26_DIS, 7332 }, 7333 .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 7334 .agg_limit = {.addr = R_AX_AMPDU_AGG_LIMIT, .mask = B_AX_AMPDU_MAX_TIME_MASK,}, 7335 .ra_agg_limit = {.addr = R_AX_AMPDU_AGG_LIMIT, 7336 .mask = B_AX_RA_TRY_RATE_AGG_LMT_MASK,}, 7337 .txcnt_limit = {.addr = R_AX_TXCNT, .mask = B_AX_L_TXCNT_LMT_MASK,}, 7338 7339 .check_mac_en = rtw89_mac_check_mac_en_ax, 7340 .sys_init = sys_init_ax, 7341 .trx_init = trx_init_ax, 7342 .preload_init = preload_init_set_ax, 7343 .clr_aon_intr = NULL, 7344 .err_imr_ctrl = err_imr_ctrl_ax, 7345 .mac_func_en = NULL, 7346 .hci_func_en = rtw89_mac_hci_func_en_ax, 7347 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 7348 .dle_func_en = dle_func_en_ax, 7349 .dle_clk_en = dle_clk_en_ax, 7350 .bf_assoc = rtw89_mac_bf_assoc_ax, 7351 7352 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 7353 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 7354 .cfg_phy_rpt = NULL, 7355 .set_edcca_mode = NULL, 7356 7357 .dle_mix_cfg = dle_mix_cfg_ax, 7358 .chk_dle_rdy = chk_dle_rdy_ax, 7359 .dle_buf_req = dle_buf_req_ax, 7360 .hfc_func_en = hfc_func_en_ax, 7361 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 7362 .hfc_mix_cfg = hfc_mix_cfg_ax, 7363 .hfc_get_mix_info = hfc_get_mix_info_ax, 7364 .wde_quota_cfg = wde_quota_cfg_ax, 7365 .ple_quota_cfg = ple_quota_cfg_ax, 7366 .set_cpuio = set_cpuio_ax, 7367 .dle_quota_change = dle_quota_change_ax, 7368 7369 .reset_pwr_state = rtw89_mac_reset_pwr_state_ax, 7370 .disable_cpu = rtw89_mac_disable_cpu_ax, 7371 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 7372 .fwdl_get_status = rtw89_fw_get_rdy_ax, 7373 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 7374 .fwdl_secure_idmem_share_mode = rtw89_fwdl_secure_idmem_share_mode_ax, 7375 .parse_efuse_map = rtw89_parse_efuse_map_ax, 7376 .parse_phycap_map = rtw89_parse_phycap_map_ax, 7377 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 7378 .efuse_read_fw_secure = rtw89_efuse_read_fw_secure_ax, 7379 .efuse_read_ecv = NULL, 7380 7381 .cfg_plt = rtw89_mac_cfg_plt_ax, 7382 .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 7383 7384 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 7385 7386 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 7387 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 7388 7389 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 7390 .dump_err_status = rtw89_mac_dump_err_status_ax, 7391 7392 .is_txq_empty = mac_is_txq_empty_ax, 7393 7394 .prep_chan_list = rtw89_hw_scan_prep_chan_list_ax, 7395 .free_chan_list = rtw89_hw_scan_free_chan_list_ax, 7396 .add_chan_list = rtw89_hw_scan_add_chan_list_ax, 7397 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_ax, 7398 .scan_offload = rtw89_fw_h2c_scan_offload_ax, 7399 7400 .wow_config_mac = rtw89_wow_config_mac_ax, 7401 }; 7402 EXPORT_SYMBOL(rtw89_mac_gen_ax); 7403