1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "pci.h" 11 #include "ps.h" 12 #include "reg.h" 13 #include "util.h" 14 15 const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = { 16 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 17 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 18 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 19 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 20 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 21 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 22 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 25 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 26 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 29 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 31 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 33 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 34 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 35 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 36 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 37 }; 38 39 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 40 u32 val, enum rtw89_mac_mem_sel sel) 41 { 42 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 43 44 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 45 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val); 46 } 47 48 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 49 enum rtw89_mac_mem_sel sel) 50 { 51 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 52 53 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 54 return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY); 55 } 56 57 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 58 enum rtw89_mac_hwmod_sel sel) 59 { 60 u32 val, r_val; 61 62 if (sel == RTW89_DMAC_SEL) { 63 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 64 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 65 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 66 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 67 val = B_AX_CMAC_EN; 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 69 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 70 val = B_AX_CMAC1_FEN; 71 } else { 72 return -EINVAL; 73 } 74 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 75 (val & r_val) != val) 76 return -EFAULT; 77 78 return 0; 79 } 80 81 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 82 { 83 u8 lte_ctrl; 84 int ret; 85 86 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 87 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 88 if (ret) 89 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 90 91 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 92 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 93 94 return ret; 95 } 96 97 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 98 { 99 u8 lte_ctrl; 100 int ret; 101 102 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 103 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 104 if (ret) 105 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 106 107 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 108 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 109 110 return ret; 111 } 112 113 static 114 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 115 { 116 u32 ctrl_reg, data_reg, ctrl_data; 117 u32 val; 118 int ret; 119 120 switch (ctrl->type) { 121 case DLE_CTRL_TYPE_WDE: 122 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 123 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 124 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 125 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 126 B_AX_WDE_DFI_ACTIVE; 127 break; 128 case DLE_CTRL_TYPE_PLE: 129 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 130 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 131 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 132 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 133 B_AX_PLE_DFI_ACTIVE; 134 break; 135 default: 136 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 137 return -EINVAL; 138 } 139 140 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 141 142 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 143 1, 1000, false, rtwdev, ctrl_reg); 144 if (ret) { 145 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 146 ctrl_reg, ctrl_data); 147 return ret; 148 } 149 150 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 151 return 0; 152 } 153 154 static int dle_dfi_quota(struct rtw89_dev *rtwdev, 155 struct rtw89_mac_dle_dfi_quota *quota) 156 { 157 struct rtw89_mac_dle_dfi_ctrl ctrl; 158 int ret; 159 160 ctrl.type = quota->dle_type; 161 ctrl.target = DLE_DFI_TYPE_QUOTA; 162 ctrl.addr = quota->qtaid; 163 ret = dle_dfi_ctrl(rtwdev, &ctrl); 164 if (ret) { 165 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 166 return ret; 167 } 168 169 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 170 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 171 return 0; 172 } 173 174 static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 175 struct rtw89_mac_dle_dfi_qempty *qempty) 176 { 177 struct rtw89_mac_dle_dfi_ctrl ctrl; 178 u32 ret; 179 180 ctrl.type = qempty->dle_type; 181 ctrl.target = DLE_DFI_TYPE_QEMPTY; 182 ctrl.addr = qempty->grpsel; 183 ret = dle_dfi_ctrl(rtwdev, &ctrl); 184 if (ret) { 185 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 186 return ret; 187 } 188 189 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 190 return 0; 191 } 192 193 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 194 { 195 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 196 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 199 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 200 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 203 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 204 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 207 } 208 209 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 210 { 211 struct rtw89_mac_dle_dfi_qempty qempty; 212 struct rtw89_mac_dle_dfi_quota quota; 213 struct rtw89_mac_dle_dfi_ctrl ctrl; 214 u32 val, not_empty, i; 215 int ret; 216 217 qempty.dle_type = DLE_CTRL_TYPE_PLE; 218 qempty.grpsel = 0; 219 qempty.qempty = ~(u32)0; 220 ret = dle_dfi_qempty(rtwdev, &qempty); 221 if (ret) 222 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 223 else 224 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 225 226 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 227 if (!(not_empty & BIT(0))) 228 continue; 229 ctrl.type = DLE_CTRL_TYPE_PLE; 230 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 231 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 232 FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 233 ret = dle_dfi_ctrl(rtwdev, &ctrl); 234 if (ret) 235 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 236 else 237 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 238 FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 239 ctrl.out_data)); 240 } 241 242 quota.dle_type = DLE_CTRL_TYPE_PLE; 243 quota.qtaid = 6; 244 ret = dle_dfi_quota(rtwdev, "a); 245 if (ret) 246 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 247 else 248 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 249 quota.rsv_pgnum, quota.use_pgnum); 250 251 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 252 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 253 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 255 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 256 257 dump_err_status_dispatcher(rtwdev); 258 } 259 260 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 261 enum mac_ax_err_info err) 262 { 263 u32 dbg, event; 264 265 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 266 event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 267 268 switch (event) { 269 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 270 rtw89_info(rtwdev, "quota lost!\n"); 271 rtw89_mac_dump_qta_lost(rtwdev); 272 break; 273 default: 274 break; 275 } 276 } 277 278 static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 279 { 280 const struct rtw89_chip_info *chip = rtwdev->chip; 281 u32 dmac_err; 282 int i, ret; 283 284 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 285 if (ret) { 286 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 287 return; 288 } 289 290 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 291 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 292 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 293 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 294 295 if (dmac_err) { 296 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 298 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 299 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 300 if (chip->chip_id == RTL8852C) { 301 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 302 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 303 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 304 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 305 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 306 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 307 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 308 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 309 } 310 } 311 312 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 313 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 314 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 315 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 316 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 317 if (chip->chip_id == RTL8852C) 318 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 319 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 320 else 321 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 322 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 323 } 324 325 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 326 if (chip->chip_id == RTL8852C) { 327 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 328 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 329 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 330 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 331 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 332 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 333 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 334 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 335 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 337 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 339 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 341 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 343 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 344 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 345 346 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 347 B_AX_DBG_SEL0, 0x8B); 348 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 349 B_AX_DBG_SEL1, 0x8B); 350 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 351 B_AX_SEL_0XC0_MASK, 1); 352 for (i = 0; i < 0x10; i++) { 353 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 354 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 355 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 356 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 357 } 358 } else { 359 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 360 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 361 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 363 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 364 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 365 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 366 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 367 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 368 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 369 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 370 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 371 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 372 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 373 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 374 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 375 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 376 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 377 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 378 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 379 } 380 } 381 382 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 383 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 384 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 385 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 386 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 387 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 388 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 389 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 390 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 391 } 392 393 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 394 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 395 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 396 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 397 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 398 } 399 400 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 401 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 402 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 403 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 404 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 405 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 406 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 407 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 408 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 409 } 410 411 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 412 if (chip->chip_id == RTL8852C) { 413 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 414 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 415 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 416 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 417 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 419 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 421 } else { 422 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 423 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 424 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 425 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 426 } 427 } 428 429 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 430 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 431 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 432 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 433 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 434 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 435 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 436 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 437 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 438 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 439 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 440 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 441 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 442 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 443 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 444 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 445 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 446 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 447 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 448 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 449 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 450 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 451 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 452 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 453 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 454 if (chip->chip_id == RTL8852C) { 455 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 456 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 457 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 458 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 459 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 460 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 461 } else { 462 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 463 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 464 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 465 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 466 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 468 } 469 } 470 471 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 472 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 474 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 475 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 476 } 477 478 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 479 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 480 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 481 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 482 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 483 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 484 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 485 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 486 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 487 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 489 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 491 } 492 493 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 494 if (chip->chip_id == RTL8852C) { 495 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 501 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 503 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 505 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 507 } else { 508 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 509 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 510 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 511 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 512 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 513 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 514 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 515 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 516 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 517 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 518 } 519 } 520 521 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 522 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 523 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 524 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 525 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 526 } 527 } 528 529 static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev, 530 u8 band) 531 { 532 const struct rtw89_chip_info *chip = rtwdev->chip; 533 u32 offset = 0; 534 u32 cmac_err; 535 int ret; 536 537 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 538 if (ret) { 539 if (band) 540 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 541 else 542 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 543 return; 544 } 545 546 if (band) 547 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 548 549 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 550 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 551 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 552 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 553 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 554 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 555 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 556 557 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 558 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 559 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 560 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 561 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 562 } 563 564 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 565 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 566 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 567 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 568 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 569 } 570 571 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 572 if (chip->chip_id == RTL8852C) { 573 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 574 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 575 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 576 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 577 } else { 578 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 579 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 580 } 581 } 582 583 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 584 if (chip->chip_id == RTL8852C) { 585 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 586 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 587 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 588 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 589 } else { 590 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 591 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 592 } 593 } 594 595 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 596 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 597 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 598 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 599 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 600 } 601 602 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 603 if (chip->chip_id == RTL8852C) { 604 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 605 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 606 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 607 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 608 } else { 609 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 610 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 611 } 612 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 613 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 614 } 615 616 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 617 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 618 } 619 620 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 621 enum mac_ax_err_info err) 622 { 623 if (err != MAC_AX_ERR_L1_ERR_DMAC && 624 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 625 err != MAC_AX_ERR_L0_ERR_CMAC0 && 626 err != MAC_AX_ERR_L0_ERR_CMAC1) 627 return; 628 629 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 630 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 631 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 632 633 rtw89_mac_dump_dmac_err_status(rtwdev); 634 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0); 635 if (rtwdev->dbcc_en) 636 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1); 637 638 rtwdev->hci.ops->dump_err_status(rtwdev); 639 640 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 641 rtw89_mac_dump_l0_to_l1(rtwdev, err); 642 643 rtw89_info(rtwdev, "<---\n"); 644 } 645 646 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 647 { 648 u32 err, err_scnr; 649 int ret; 650 651 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 652 false, rtwdev, R_AX_HALT_C2H_CTRL); 653 if (ret) { 654 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 655 return ret; 656 } 657 658 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 659 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 660 661 err_scnr = RTW89_ERROR_SCENARIO(err); 662 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 663 err = MAC_AX_ERR_CPU_EXCEPTION; 664 else if (err_scnr == RTW89_WCPU_ASSERTION) 665 err = MAC_AX_ERR_ASSERTION; 666 667 rtw89_fw_st_dbg_dump(rtwdev); 668 rtw89_mac_dump_err_status(rtwdev, err); 669 670 return err; 671 } 672 EXPORT_SYMBOL(rtw89_mac_get_err_status); 673 674 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 675 { 676 u32 halt; 677 int ret = 0; 678 679 if (err > MAC_AX_SET_ERR_MAX) { 680 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 681 return -EINVAL; 682 } 683 684 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 685 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 686 if (ret) { 687 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 688 return -EFAULT; 689 } 690 691 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 692 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 693 694 return 0; 695 } 696 EXPORT_SYMBOL(rtw89_mac_set_err_status); 697 698 static int hfc_reset_param(struct rtw89_dev *rtwdev) 699 { 700 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 701 struct rtw89_hfc_param_ini param_ini = {NULL}; 702 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 703 704 switch (rtwdev->hci.type) { 705 case RTW89_HCI_TYPE_PCIE: 706 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 707 param->en = 0; 708 break; 709 default: 710 return -EINVAL; 711 } 712 713 if (param_ini.pub_cfg) 714 param->pub_cfg = *param_ini.pub_cfg; 715 716 if (param_ini.prec_cfg) { 717 param->prec_cfg = *param_ini.prec_cfg; 718 rtwdev->hal.sw_amsdu_max_size = 719 param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; 720 } 721 722 if (param_ini.ch_cfg) 723 param->ch_cfg = param_ini.ch_cfg; 724 725 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 726 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 727 param->mode = param_ini.mode; 728 729 return 0; 730 } 731 732 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 733 { 734 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 735 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 736 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 737 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 738 739 if (ch >= RTW89_DMA_CH_NUM) 740 return -EINVAL; 741 742 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 743 ch_cfg[ch].max > pub_cfg->pub_max) 744 return -EINVAL; 745 if (ch_cfg[ch].grp >= grp_num) 746 return -EINVAL; 747 748 return 0; 749 } 750 751 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 752 { 753 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 754 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 755 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 756 757 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 758 if (rtwdev->chip->chip_id == RTL8852A) 759 return 0; 760 else 761 return -EFAULT; 762 } 763 764 return 0; 765 } 766 767 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 768 { 769 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 770 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 771 772 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 773 return -EFAULT; 774 775 return 0; 776 } 777 778 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 779 { 780 const struct rtw89_chip_info *chip = rtwdev->chip; 781 const struct rtw89_page_regs *regs = chip->page_regs; 782 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 783 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 784 int ret = 0; 785 u32 val = 0; 786 787 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 788 if (ret) 789 return ret; 790 791 ret = hfc_ch_cfg_chk(rtwdev, ch); 792 if (ret) 793 return ret; 794 795 if (ch > RTW89_DMA_B1HI) 796 return -EINVAL; 797 798 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 799 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 800 (cfg[ch].grp ? B_AX_GRP : 0); 801 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 802 803 return 0; 804 } 805 806 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 807 { 808 const struct rtw89_chip_info *chip = rtwdev->chip; 809 const struct rtw89_page_regs *regs = chip->page_regs; 810 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 811 struct rtw89_hfc_ch_info *info = param->ch_info; 812 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 813 u32 val; 814 u32 ret; 815 816 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 817 if (ret) 818 return ret; 819 820 if (ch > RTW89_DMA_H2C) 821 return -EINVAL; 822 823 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 824 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 825 if (ch < RTW89_DMA_H2C) 826 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 827 else 828 info[ch].used = cfg[ch].min - info[ch].aval; 829 830 return 0; 831 } 832 833 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 834 { 835 const struct rtw89_chip_info *chip = rtwdev->chip; 836 const struct rtw89_page_regs *regs = chip->page_regs; 837 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 838 u32 val; 839 int ret; 840 841 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 842 if (ret) 843 return ret; 844 845 ret = hfc_pub_cfg_chk(rtwdev); 846 if (ret) 847 return ret; 848 849 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 850 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 851 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 852 853 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 854 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 855 856 return 0; 857 } 858 859 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 860 { 861 const struct rtw89_chip_info *chip = rtwdev->chip; 862 const struct rtw89_page_regs *regs = chip->page_regs; 863 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 864 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 865 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 866 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 867 u32 val; 868 int ret; 869 870 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 871 if (ret) 872 return ret; 873 874 val = rtw89_read32(rtwdev, regs->pub_page_info1); 875 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 876 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 877 val = rtw89_read32(rtwdev, regs->pub_page_info3); 878 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 879 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 880 info->pub_aval = 881 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 882 B_AX_PUB_AVAL_PG_MASK); 883 info->wp_aval = 884 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 885 B_AX_WP_AVAL_PG_MASK); 886 887 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 888 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 889 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 890 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 891 prec_cfg->ch011_full_cond = 892 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 893 prec_cfg->h2c_full_cond = 894 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 895 prec_cfg->wp_ch07_full_cond = 896 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 897 prec_cfg->wp_ch811_full_cond = 898 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 899 900 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 901 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 902 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 903 904 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 905 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 906 907 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 908 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 909 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 910 911 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 912 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 913 914 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 915 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 916 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 917 918 ret = hfc_pub_info_chk(rtwdev); 919 if (param->en && ret) 920 return ret; 921 922 return 0; 923 } 924 925 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 926 { 927 const struct rtw89_chip_info *chip = rtwdev->chip; 928 const struct rtw89_page_regs *regs = chip->page_regs; 929 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 930 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 931 u32 val; 932 933 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 934 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 935 936 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 937 B_AX_HCI_FC_CH12_FULL_COND_MASK, 938 prec_cfg->h2c_full_cond); 939 } 940 941 static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 942 { 943 const struct rtw89_chip_info *chip = rtwdev->chip; 944 const struct rtw89_page_regs *regs = chip->page_regs; 945 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 946 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 947 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 948 u32 val; 949 950 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 951 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 952 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 953 954 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 955 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 956 957 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 958 B_AX_PREC_PAGE_WP_CH07_MASK) | 959 u32_encode_bits(prec_cfg->wp_ch811_prec, 960 B_AX_PREC_PAGE_WP_CH811_MASK); 961 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 962 963 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 964 param->mode, B_AX_HCI_FC_MODE_MASK); 965 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 966 B_AX_HCI_FC_WD_FULL_COND_MASK); 967 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 968 B_AX_HCI_FC_CH12_FULL_COND_MASK); 969 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 970 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 971 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 972 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 973 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 974 } 975 976 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 977 { 978 const struct rtw89_chip_info *chip = rtwdev->chip; 979 const struct rtw89_page_regs *regs = chip->page_regs; 980 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 981 u32 val; 982 983 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 984 param->en = en; 985 param->h2c_en = h2c_en; 986 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 987 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 988 (val & ~B_AX_HCI_FC_CH12_EN); 989 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 990 } 991 992 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 993 { 994 const struct rtw89_chip_info *chip = rtwdev->chip; 995 u32 dma_ch_mask = chip->dma_ch_mask; 996 u8 ch; 997 u32 ret = 0; 998 999 if (reset) 1000 ret = hfc_reset_param(rtwdev); 1001 if (ret) 1002 return ret; 1003 1004 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1005 if (ret) 1006 return ret; 1007 1008 hfc_func_en(rtwdev, false, false); 1009 1010 if (!en && h2c_en) { 1011 hfc_h2c_cfg(rtwdev); 1012 hfc_func_en(rtwdev, en, h2c_en); 1013 return ret; 1014 } 1015 1016 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1017 if (dma_ch_mask & BIT(ch)) 1018 continue; 1019 ret = hfc_ch_ctrl(rtwdev, ch); 1020 if (ret) 1021 return ret; 1022 } 1023 1024 ret = hfc_pub_ctrl(rtwdev); 1025 if (ret) 1026 return ret; 1027 1028 hfc_mix_cfg(rtwdev); 1029 if (en || h2c_en) { 1030 hfc_func_en(rtwdev, en, h2c_en); 1031 udelay(10); 1032 } 1033 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1034 if (dma_ch_mask & BIT(ch)) 1035 continue; 1036 ret = hfc_upd_ch_info(rtwdev, ch); 1037 if (ret) 1038 return ret; 1039 } 1040 ret = hfc_upd_mix_info(rtwdev); 1041 1042 return ret; 1043 } 1044 1045 #define PWR_POLL_CNT 2000 1046 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1047 const struct rtw89_pwr_cfg *cfg) 1048 { 1049 u8 val = 0; 1050 int ret; 1051 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1052 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1053 1054 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1055 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1056 1057 if (!ret) 1058 return 0; 1059 1060 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1061 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1062 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1063 1064 return -EBUSY; 1065 } 1066 1067 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1068 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1069 { 1070 const struct rtw89_pwr_cfg *cur_cfg; 1071 u32 addr; 1072 u8 val; 1073 1074 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1075 if (!(cur_cfg->intf_msk & intf_msk) || 1076 !(cur_cfg->cv_msk & cv_msk)) 1077 continue; 1078 1079 switch (cur_cfg->cmd) { 1080 case PWR_CMD_WRITE: 1081 addr = cur_cfg->addr; 1082 1083 if (cur_cfg->base == PWR_BASE_SDIO) 1084 addr |= SDIO_LOCAL_BASE_ADDR; 1085 1086 val = rtw89_read8(rtwdev, addr); 1087 val &= ~(cur_cfg->msk); 1088 val |= (cur_cfg->val & cur_cfg->msk); 1089 1090 rtw89_write8(rtwdev, addr, val); 1091 break; 1092 case PWR_CMD_POLL: 1093 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1094 return -EBUSY; 1095 break; 1096 case PWR_CMD_DELAY: 1097 if (cur_cfg->val == PWR_DELAY_US) 1098 udelay(cur_cfg->addr); 1099 else 1100 fsleep(cur_cfg->addr * 1000); 1101 break; 1102 default: 1103 return -EINVAL; 1104 } 1105 } 1106 1107 return 0; 1108 } 1109 1110 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1111 const struct rtw89_pwr_cfg * const *cfg_seq) 1112 { 1113 int ret; 1114 1115 for (; *cfg_seq; cfg_seq++) { 1116 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1117 PWR_INTF_MSK_PCIE, *cfg_seq); 1118 if (ret) 1119 return -EBUSY; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static enum rtw89_rpwm_req_pwr_state 1126 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1127 { 1128 enum rtw89_rpwm_req_pwr_state state; 1129 1130 switch (rtwdev->ps_mode) { 1131 case RTW89_PS_MODE_RFOFF: 1132 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1133 break; 1134 case RTW89_PS_MODE_CLK_GATED: 1135 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1136 break; 1137 case RTW89_PS_MODE_PWR_GATED: 1138 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1139 break; 1140 default: 1141 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1142 break; 1143 } 1144 return state; 1145 } 1146 1147 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1148 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1149 bool notify_wake) 1150 { 1151 u16 request; 1152 1153 spin_lock_bh(&rtwdev->rpwm_lock); 1154 1155 request = rtw89_read16(rtwdev, R_AX_RPWM); 1156 request ^= request | PS_RPWM_TOGGLE; 1157 request |= req_pwr_state; 1158 1159 if (notify_wake) { 1160 request |= PS_RPWM_NOTIFY_WAKE; 1161 } else { 1162 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1163 RPWM_SEQ_NUM_MAX; 1164 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1165 rtwdev->mac.rpwm_seq_num); 1166 1167 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1168 request |= PS_RPWM_ACK; 1169 } 1170 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1171 1172 spin_unlock_bh(&rtwdev->rpwm_lock); 1173 } 1174 1175 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1176 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1177 { 1178 bool request_deep_mode; 1179 bool in_deep_mode; 1180 u8 rpwm_req_num; 1181 u8 cpwm_rsp_seq; 1182 u8 cpwm_seq; 1183 u8 cpwm_status; 1184 1185 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1186 request_deep_mode = true; 1187 else 1188 request_deep_mode = false; 1189 1190 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1191 in_deep_mode = true; 1192 else 1193 in_deep_mode = false; 1194 1195 if (request_deep_mode != in_deep_mode) 1196 return -EPERM; 1197 1198 if (request_deep_mode) 1199 return 0; 1200 1201 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1202 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1203 PS_CPWM_RSP_SEQ_NUM); 1204 1205 if (rpwm_req_num != cpwm_rsp_seq) 1206 return -EPERM; 1207 1208 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1209 CPWM_SEQ_NUM_MAX; 1210 1211 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1212 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1213 return -EPERM; 1214 1215 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1216 if (cpwm_status != req_pwr_state) 1217 return -EPERM; 1218 1219 return 0; 1220 } 1221 1222 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1223 { 1224 enum rtw89_rpwm_req_pwr_state state; 1225 unsigned long delay = enter ? 10 : 150; 1226 int ret; 1227 int i; 1228 1229 if (enter) 1230 state = rtw89_mac_get_req_pwr_state(rtwdev); 1231 else 1232 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1233 1234 for (i = 0; i < RPWM_TRY_CNT; i++) { 1235 rtw89_mac_send_rpwm(rtwdev, state, false); 1236 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1237 !ret, delay, 15000, false, 1238 rtwdev, state); 1239 if (!ret) 1240 break; 1241 1242 if (i == RPWM_TRY_CNT - 1) 1243 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1244 enter ? "entering" : "leaving"); 1245 else 1246 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1247 "%d time firmware failed to ack for %s ps mode\n", 1248 i + 1, enter ? "entering" : "leaving"); 1249 } 1250 } 1251 1252 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1253 { 1254 enum rtw89_rpwm_req_pwr_state state; 1255 1256 state = rtw89_mac_get_req_pwr_state(rtwdev); 1257 rtw89_mac_send_rpwm(rtwdev, state, true); 1258 } 1259 1260 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1261 { 1262 #define PWR_ACT 1 1263 const struct rtw89_chip_info *chip = rtwdev->chip; 1264 const struct rtw89_pwr_cfg * const *cfg_seq; 1265 int (*cfg_func)(struct rtw89_dev *rtwdev); 1266 int ret; 1267 u8 val; 1268 1269 if (on) { 1270 cfg_seq = chip->pwr_on_seq; 1271 cfg_func = chip->ops->pwr_on_func; 1272 } else { 1273 cfg_seq = chip->pwr_off_seq; 1274 cfg_func = chip->ops->pwr_off_func; 1275 } 1276 1277 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1278 __rtw89_leave_ps_mode(rtwdev); 1279 1280 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1281 if (on && val == PWR_ACT) { 1282 rtw89_err(rtwdev, "MAC has already powered on\n"); 1283 return -EBUSY; 1284 } 1285 1286 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1287 if (ret) 1288 return ret; 1289 1290 if (on) { 1291 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1292 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1293 } else { 1294 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1295 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1296 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1297 rtw89_set_entity_state(rtwdev, false); 1298 } 1299 1300 return 0; 1301 #undef PWR_ACT 1302 } 1303 1304 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1305 { 1306 rtw89_mac_power_switch(rtwdev, false); 1307 } 1308 1309 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1310 { 1311 u32 func_en = 0; 1312 u32 ck_en = 0; 1313 u32 c1pc_en = 0; 1314 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1315 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1316 1317 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1318 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1319 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1320 B_AX_CMAC_CRPRT; 1321 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1322 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1323 B_AX_RMAC_CKEN; 1324 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1325 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1326 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1327 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1328 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1329 1330 if (en) { 1331 if (mac_idx == RTW89_MAC_1) { 1332 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1333 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1334 B_AX_R_SYM_ISO_CMAC12PP); 1335 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1336 B_AX_CMAC1_FEN); 1337 } 1338 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1339 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1340 } else { 1341 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1342 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1343 if (mac_idx == RTW89_MAC_1) { 1344 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1345 B_AX_CMAC1_FEN); 1346 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1347 B_AX_R_SYM_ISO_CMAC12PP); 1348 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1349 } 1350 } 1351 1352 return 0; 1353 } 1354 1355 static int dmac_func_en(struct rtw89_dev *rtwdev) 1356 { 1357 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1358 u32 val32; 1359 1360 if (chip_id == RTL8852C) 1361 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1362 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1363 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1364 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1365 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1366 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1367 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1368 else 1369 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1370 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1371 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1372 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1373 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1374 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1375 B_AX_DMAC_CRPRT); 1376 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1377 1378 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1379 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1380 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1381 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1382 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1383 1384 return 0; 1385 } 1386 1387 static int chip_func_en(struct rtw89_dev *rtwdev) 1388 { 1389 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1390 1391 if (chip_id == RTL8852A || chip_id == RTL8852B) 1392 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1393 B_AX_OCP_L1_MASK); 1394 1395 return 0; 1396 } 1397 1398 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1399 { 1400 int ret; 1401 1402 ret = dmac_func_en(rtwdev); 1403 if (ret) 1404 return ret; 1405 1406 ret = cmac_func_en(rtwdev, 0, true); 1407 if (ret) 1408 return ret; 1409 1410 ret = chip_func_en(rtwdev); 1411 if (ret) 1412 return ret; 1413 1414 return ret; 1415 } 1416 1417 const struct rtw89_mac_size_set rtw89_mac_size = { 1418 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1419 /* PCIE 64 */ 1420 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1421 /* DLFW */ 1422 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1423 /* PCIE 64 */ 1424 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1425 /* DLFW */ 1426 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1427 /* 8852C DLFW */ 1428 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1429 /* 8852C PCIE SCC */ 1430 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1431 /* PCIE */ 1432 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1433 /* DLFW */ 1434 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1435 /* PCIE 64 */ 1436 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1437 /* DLFW */ 1438 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1439 /* 8852C DLFW */ 1440 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1441 /* 8852C PCIE SCC */ 1442 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1443 /* PCIE 64 */ 1444 .wde_qt0 = {3792, 196, 0, 107,}, 1445 /* DLFW */ 1446 .wde_qt4 = {0, 0, 0, 0,}, 1447 /* PCIE 64 */ 1448 .wde_qt6 = {448, 48, 0, 16,}, 1449 /* 8852C DLFW */ 1450 .wde_qt17 = {0, 0, 0, 0,}, 1451 /* 8852C PCIE SCC */ 1452 .wde_qt18 = {3228, 60, 0, 40,}, 1453 /* PCIE SCC */ 1454 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1455 /* PCIE SCC */ 1456 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1457 /* DLFW */ 1458 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1459 /* PCIE 64 */ 1460 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1461 /* DLFW 52C */ 1462 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1463 /* DLFW 52C */ 1464 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1465 /* 8852C PCIE SCC */ 1466 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1467 /* 8852C PCIE SCC */ 1468 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1469 /* PCIE 64 */ 1470 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1471 /* 8852A PCIE WOW */ 1472 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1473 }; 1474 EXPORT_SYMBOL(rtw89_mac_size); 1475 1476 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1477 enum rtw89_qta_mode mode) 1478 { 1479 struct rtw89_mac_info *mac = &rtwdev->mac; 1480 const struct rtw89_dle_mem *cfg; 1481 1482 cfg = &rtwdev->chip->dle_mem[mode]; 1483 if (!cfg) 1484 return NULL; 1485 1486 if (cfg->mode != mode) { 1487 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1488 return NULL; 1489 } 1490 1491 mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; 1492 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1493 mac->dle_info.qta_mode = mode; 1494 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1495 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1496 1497 return cfg; 1498 } 1499 1500 static bool mac_is_txq_empty(struct rtw89_dev *rtwdev) 1501 { 1502 struct rtw89_mac_dle_dfi_qempty qempty; 1503 u32 qnum, qtmp, val32, msk32; 1504 int i, j, ret; 1505 1506 qnum = rtwdev->chip->wde_qempty_acq_num; 1507 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1508 1509 for (i = 0; i < qnum; i++) { 1510 qempty.grpsel = i; 1511 ret = dle_dfi_qempty(rtwdev, &qempty); 1512 if (ret) { 1513 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1514 return false; 1515 } 1516 qtmp = qempty.qempty; 1517 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1518 val32 = FIELD_GET(QEMP_ACQ_GRP_QSEL_MASK, qtmp); 1519 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1520 return false; 1521 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1522 } 1523 } 1524 1525 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel; 1526 ret = dle_dfi_qempty(rtwdev, &qempty); 1527 if (ret) { 1528 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1529 return false; 1530 } 1531 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1532 if ((qempty.qempty & msk32) != msk32) 1533 return false; 1534 1535 if (rtwdev->dbcc_en) { 1536 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1537 if ((qempty.qempty & msk32) != msk32) 1538 return false; 1539 } 1540 1541 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1542 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1543 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1544 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1545 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1546 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1547 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1548 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1549 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1550 1551 return (val32 & msk32) == msk32; 1552 } 1553 1554 static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1555 const struct rtw89_dle_size *ple) 1556 { 1557 return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1558 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1559 } 1560 1561 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1562 enum rtw89_qta_mode mode) 1563 { 1564 u32 size = rtwdev->chip->fifo_size; 1565 1566 if (mode == RTW89_QTA_SCC) 1567 size -= rtwdev->chip->dle_scc_rsvd_size; 1568 1569 return size; 1570 } 1571 1572 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1573 { 1574 if (enable) 1575 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1576 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1577 else 1578 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1579 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1580 } 1581 1582 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1583 { 1584 if (enable) 1585 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, 1586 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1587 else 1588 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, 1589 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1590 } 1591 1592 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1593 { 1594 const struct rtw89_dle_size *size_cfg; 1595 u32 val; 1596 u8 bound = 0; 1597 1598 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1599 size_cfg = cfg->wde_size; 1600 1601 switch (size_cfg->pge_size) { 1602 default: 1603 case RTW89_WDE_PG_64: 1604 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1605 B_AX_WDE_PAGE_SEL_MASK); 1606 break; 1607 case RTW89_WDE_PG_128: 1608 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1609 B_AX_WDE_PAGE_SEL_MASK); 1610 break; 1611 case RTW89_WDE_PG_256: 1612 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1613 return -EINVAL; 1614 } 1615 1616 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1617 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1618 B_AX_WDE_FREE_PAGE_NUM_MASK); 1619 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1620 1621 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1622 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1623 * size_cfg->pge_size / DLE_BOUND_UNIT; 1624 size_cfg = cfg->ple_size; 1625 1626 switch (size_cfg->pge_size) { 1627 default: 1628 case RTW89_PLE_PG_64: 1629 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1630 return -EINVAL; 1631 case RTW89_PLE_PG_128: 1632 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1633 B_AX_PLE_PAGE_SEL_MASK); 1634 break; 1635 case RTW89_PLE_PG_256: 1636 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1637 B_AX_PLE_PAGE_SEL_MASK); 1638 break; 1639 } 1640 1641 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1642 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1643 B_AX_PLE_FREE_PAGE_NUM_MASK); 1644 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1645 1646 return 0; 1647 } 1648 1649 #define INVALID_QT_WCPU U16_MAX 1650 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1651 do { \ 1652 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1653 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1654 rtw89_write32(rtwdev, \ 1655 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1656 val); \ 1657 } while (0) 1658 #define SET_QUOTA(_x, _module, _idx) \ 1659 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1660 1661 static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1662 const struct rtw89_wde_quota *min_cfg, 1663 const struct rtw89_wde_quota *max_cfg, 1664 u16 ext_wde_min_qt_wcpu) 1665 { 1666 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1667 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1668 u32 val; 1669 1670 SET_QUOTA(hif, WDE, 0); 1671 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1672 SET_QUOTA(pkt_in, WDE, 3); 1673 SET_QUOTA(cpu_io, WDE, 4); 1674 } 1675 1676 static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1677 const struct rtw89_ple_quota *min_cfg, 1678 const struct rtw89_ple_quota *max_cfg) 1679 { 1680 u32 val; 1681 1682 SET_QUOTA(cma0_tx, PLE, 0); 1683 SET_QUOTA(cma1_tx, PLE, 1); 1684 SET_QUOTA(c2h, PLE, 2); 1685 SET_QUOTA(h2c, PLE, 3); 1686 SET_QUOTA(wcpu, PLE, 4); 1687 SET_QUOTA(mpdu_proc, PLE, 5); 1688 SET_QUOTA(cma0_dma, PLE, 6); 1689 SET_QUOTA(cma1_dma, PLE, 7); 1690 SET_QUOTA(bb_rpt, PLE, 8); 1691 SET_QUOTA(wd_rel, PLE, 9); 1692 SET_QUOTA(cpu_io, PLE, 10); 1693 if (rtwdev->chip->chip_id == RTL8852C) 1694 SET_QUOTA(tx_rpt, PLE, 11); 1695 } 1696 1697 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 1698 { 1699 const struct rtw89_ple_quota *min_cfg, *max_cfg; 1700 const struct rtw89_dle_mem *cfg; 1701 u32 val; 1702 1703 if (rtwdev->chip->chip_id == RTL8852C) 1704 return 0; 1705 1706 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 1707 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 1708 return -EINVAL; 1709 } 1710 1711 if (wow) 1712 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 1713 else 1714 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 1715 if (!cfg) { 1716 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1717 return -EINVAL; 1718 } 1719 1720 min_cfg = cfg->ple_min_qt; 1721 max_cfg = cfg->ple_max_qt; 1722 SET_QUOTA(cma0_dma, PLE, 6); 1723 SET_QUOTA(cma1_dma, PLE, 7); 1724 1725 return 0; 1726 } 1727 #undef SET_QUOTA 1728 1729 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 1730 { 1731 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 1732 1733 if (enable) 1734 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1735 else 1736 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1737 } 1738 1739 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1740 const struct rtw89_dle_mem *cfg, 1741 u16 ext_wde_min_qt_wcpu) 1742 { 1743 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1744 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1745 } 1746 1747 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1748 enum rtw89_qta_mode ext_mode) 1749 { 1750 const struct rtw89_dle_mem *cfg, *ext_cfg; 1751 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1752 int ret = 0; 1753 u32 ini; 1754 1755 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1756 if (ret) 1757 return ret; 1758 1759 cfg = get_dle_mem_cfg(rtwdev, mode); 1760 if (!cfg) { 1761 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1762 ret = -EINVAL; 1763 goto error; 1764 } 1765 1766 if (mode == RTW89_QTA_DLFW) { 1767 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1768 if (!ext_cfg) { 1769 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1770 ext_mode); 1771 ret = -EINVAL; 1772 goto error; 1773 } 1774 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1775 } 1776 1777 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 1778 dle_expected_used_size(rtwdev, mode)) { 1779 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1780 ret = -EINVAL; 1781 goto error; 1782 } 1783 1784 dle_func_en(rtwdev, false); 1785 dle_clk_en(rtwdev, true); 1786 1787 ret = dle_mix_cfg(rtwdev, cfg); 1788 if (ret) { 1789 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1790 goto error; 1791 } 1792 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1793 1794 dle_func_en(rtwdev, true); 1795 1796 ret = read_poll_timeout(rtw89_read32, ini, 1797 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1798 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1799 if (ret) { 1800 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1801 return ret; 1802 } 1803 1804 ret = read_poll_timeout(rtw89_read32, ini, 1805 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1806 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1807 if (ret) { 1808 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1809 return ret; 1810 } 1811 1812 return 0; 1813 error: 1814 dle_func_en(rtwdev, false); 1815 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1816 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1817 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1818 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1819 1820 return ret; 1821 } 1822 1823 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1824 enum rtw89_qta_mode mode) 1825 { 1826 u32 reg, max_preld_size, min_rsvd_size; 1827 1828 max_preld_size = (mac_idx == RTW89_MAC_0 ? 1829 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1830 reg = mac_idx == RTW89_MAC_0 ? 1831 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1832 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1833 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1834 1835 min_rsvd_size = PRELD_AMSDU_SIZE; 1836 reg = mac_idx == RTW89_MAC_0 ? 1837 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1838 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1839 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1840 1841 return 0; 1842 } 1843 1844 static bool is_qta_poh(struct rtw89_dev *rtwdev) 1845 { 1846 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1847 } 1848 1849 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1850 enum rtw89_qta_mode mode) 1851 { 1852 const struct rtw89_chip_info *chip = rtwdev->chip; 1853 1854 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || !is_qta_poh(rtwdev)) 1855 return 0; 1856 1857 return preload_init_set(rtwdev, mac_idx, mode); 1858 } 1859 1860 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1861 { 1862 u32 msk32; 1863 u32 val32; 1864 1865 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1866 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1867 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1868 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1869 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1870 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1871 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1872 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1873 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1874 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1875 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1876 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1877 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1878 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1879 1880 if ((val32 & msk32) == msk32) 1881 return true; 1882 1883 return false; 1884 } 1885 1886 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 1887 { 1888 const struct rtw89_chip_info *chip = rtwdev->chip; 1889 1890 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 1891 return; 1892 1893 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 1894 SS2F_PATH_WLCPU); 1895 } 1896 1897 static int sta_sch_init(struct rtw89_dev *rtwdev) 1898 { 1899 u32 p_val; 1900 u8 val; 1901 int ret; 1902 1903 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1904 if (ret) 1905 return ret; 1906 1907 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1908 val |= B_AX_SS_EN; 1909 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1910 1911 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1912 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1913 if (ret) { 1914 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1915 return ret; 1916 } 1917 1918 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 1919 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 1920 1921 _patch_ss2f_path(rtwdev); 1922 1923 return 0; 1924 } 1925 1926 static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1927 { 1928 int ret; 1929 1930 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1931 if (ret) 1932 return ret; 1933 1934 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1935 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1936 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1937 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1938 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1939 1940 return 0; 1941 } 1942 1943 static int sec_eng_init(struct rtw89_dev *rtwdev) 1944 { 1945 const struct rtw89_chip_info *chip = rtwdev->chip; 1946 u32 val = 0; 1947 int ret; 1948 1949 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1950 if (ret) 1951 return ret; 1952 1953 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 1954 /* init clock */ 1955 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 1956 /* init TX encryption */ 1957 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 1958 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 1959 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 1960 val &= ~B_AX_TX_PARTIAL_MODE; 1961 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 1962 1963 /* init MIC ICV append */ 1964 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 1965 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 1966 1967 /* option init */ 1968 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 1969 1970 if (chip->chip_id == RTL8852C) 1971 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 1972 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 1973 1974 return 0; 1975 } 1976 1977 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1978 { 1979 int ret; 1980 1981 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 1982 if (ret) { 1983 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 1984 return ret; 1985 } 1986 1987 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 1988 if (ret) { 1989 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 1990 return ret; 1991 } 1992 1993 ret = hfc_init(rtwdev, true, true, true); 1994 if (ret) { 1995 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 1996 return ret; 1997 } 1998 1999 ret = sta_sch_init(rtwdev); 2000 if (ret) { 2001 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2002 return ret; 2003 } 2004 2005 ret = mpdu_proc_init(rtwdev); 2006 if (ret) { 2007 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2008 return ret; 2009 } 2010 2011 ret = sec_eng_init(rtwdev); 2012 if (ret) { 2013 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2014 return ret; 2015 } 2016 2017 return ret; 2018 } 2019 2020 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2021 { 2022 u32 val, reg; 2023 u16 p_val; 2024 int ret; 2025 2026 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2027 if (ret) 2028 return ret; 2029 2030 reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); 2031 2032 val = rtw89_read32(rtwdev, reg); 2033 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2034 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2035 rtw89_write32(rtwdev, reg, val); 2036 2037 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2038 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2039 if (ret) { 2040 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2041 return ret; 2042 } 2043 2044 return 0; 2045 } 2046 2047 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2048 { 2049 u32 ret; 2050 u32 reg; 2051 u32 val; 2052 2053 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2054 if (ret) 2055 return ret; 2056 2057 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx); 2058 if (rtwdev->chip->chip_id == RTL8852C) 2059 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2060 SIFS_MACTXEN_T1_V1); 2061 else 2062 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2063 SIFS_MACTXEN_T1); 2064 2065 if (rtwdev->chip->chip_id == RTL8852B) { 2066 reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx); 2067 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2068 } 2069 2070 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx); 2071 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2072 2073 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); 2074 if (rtwdev->chip->chip_id == RTL8852C) { 2075 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2076 B_AX_TX_PARTIAL_MODE); 2077 if (!val) 2078 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2079 SCH_PREBKF_24US); 2080 } else { 2081 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2082 SCH_PREBKF_24US); 2083 } 2084 2085 return 0; 2086 } 2087 2088 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 2089 enum rtw89_machdr_frame_type type, 2090 enum rtw89_mac_fwd_target fwd_target, 2091 u8 mac_idx) 2092 { 2093 u32 reg; 2094 u32 val; 2095 2096 switch (fwd_target) { 2097 case RTW89_FWD_DONT_CARE: 2098 val = RX_FLTR_FRAME_DROP; 2099 break; 2100 case RTW89_FWD_TO_HOST: 2101 val = RX_FLTR_FRAME_TO_HOST; 2102 break; 2103 case RTW89_FWD_TO_WLAN_CPU: 2104 val = RX_FLTR_FRAME_TO_WLCPU; 2105 break; 2106 default: 2107 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2108 return -EINVAL; 2109 } 2110 2111 switch (type) { 2112 case RTW89_MGNT: 2113 reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); 2114 break; 2115 case RTW89_CTRL: 2116 reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); 2117 break; 2118 case RTW89_DATA: 2119 reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); 2120 break; 2121 default: 2122 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2123 return -EINVAL; 2124 } 2125 rtw89_write32(rtwdev, reg, val); 2126 2127 return 0; 2128 } 2129 2130 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2131 { 2132 int ret, i; 2133 u32 mac_ftlr, plcp_ftlr; 2134 2135 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2136 if (ret) 2137 return ret; 2138 2139 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2140 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 2141 mac_idx); 2142 if (ret) 2143 return ret; 2144 } 2145 mac_ftlr = rtwdev->hal.rx_fltr; 2146 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2147 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2148 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2149 B_AX_HE_SIGB_CRC_CHK; 2150 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), 2151 mac_ftlr); 2152 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), 2153 plcp_ftlr); 2154 2155 return 0; 2156 } 2157 2158 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2159 { 2160 u32 reg, val32; 2161 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2162 2163 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2164 B_AX_RSP_CHK_BASIC_NAV; 2165 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2166 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2167 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2168 2169 switch (rtwdev->chip->chip_id) { 2170 case RTL8852A: 2171 case RTL8852B: 2172 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2173 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2174 rtw89_write32(rtwdev, reg, val32); 2175 2176 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2177 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2178 rtw89_write32(rtwdev, reg, val32); 2179 break; 2180 default: 2181 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2182 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2183 rtw89_write32(rtwdev, reg, val32); 2184 2185 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2186 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2187 rtw89_write32(rtwdev, reg, val32); 2188 break; 2189 } 2190 } 2191 2192 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2193 { 2194 u32 val, reg; 2195 int ret; 2196 2197 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2198 if (ret) 2199 return ret; 2200 2201 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); 2202 val = rtw89_read32(rtwdev, reg); 2203 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2204 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2205 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2206 B_AX_CTN_CHK_INTRA_NAV | 2207 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2208 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2209 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2210 B_AX_CTN_CHK_CCA_P20); 2211 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2212 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2213 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2214 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2215 B_AX_SIFS_CHK_EDCCA); 2216 2217 rtw89_write32(rtwdev, reg, val); 2218 2219 _patch_dis_resp_chk(rtwdev, mac_idx); 2220 2221 return 0; 2222 } 2223 2224 static int nav_ctrl_init(struct rtw89_dev *rtwdev) 2225 { 2226 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2227 B_AX_WMAC_TF_UP_NAV_EN | 2228 B_AX_WMAC_NAV_UPPER_EN); 2229 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2230 2231 return 0; 2232 } 2233 2234 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2235 { 2236 u32 reg; 2237 int ret; 2238 2239 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2240 if (ret) 2241 return ret; 2242 reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); 2243 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2244 2245 return 0; 2246 } 2247 2248 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2249 { 2250 u32 reg; 2251 int ret; 2252 2253 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2254 if (ret) 2255 return ret; 2256 2257 reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); 2258 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2259 2260 reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx); 2261 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2262 2263 reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx); 2264 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2265 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2266 2267 return 0; 2268 } 2269 2270 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2271 { 2272 const struct rtw89_chip_info *chip = rtwdev->chip; 2273 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2274 u32 reg, val, sifs; 2275 int ret; 2276 2277 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2278 if (ret) 2279 return ret; 2280 2281 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2282 val = rtw89_read32(rtwdev, reg); 2283 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2284 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2285 2286 switch (rtwdev->chip->chip_id) { 2287 case RTL8852A: 2288 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2289 break; 2290 case RTL8852B: 2291 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2292 break; 2293 default: 2294 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2295 break; 2296 } 2297 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2298 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2299 rtw89_write32(rtwdev, reg, val); 2300 2301 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); 2302 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2303 2304 reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx); 2305 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2306 reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx); 2307 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2308 2309 return 0; 2310 } 2311 2312 static void rst_bacam(struct rtw89_dev *rtwdev) 2313 { 2314 u32 val32; 2315 int ret; 2316 2317 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2318 S_AX_BACAM_RST_ALL); 2319 2320 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2321 1, 1000, false, 2322 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2323 if (ret) 2324 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2325 } 2326 2327 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2328 { 2329 #define TRXCFG_RMAC_CCA_TO 32 2330 #define TRXCFG_RMAC_DATA_TO 15 2331 #define RX_MAX_LEN_UNIT 512 2332 #define PLD_RLS_MAX_PG 127 2333 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2334 int ret; 2335 u32 reg, rx_max_len, rx_qta; 2336 u16 val; 2337 2338 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2339 if (ret) 2340 return ret; 2341 2342 if (mac_idx == RTW89_MAC_0) 2343 rst_bacam(rtwdev); 2344 2345 reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); 2346 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2347 2348 reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); 2349 val = rtw89_read16(rtwdev, reg); 2350 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2351 B_AX_RX_DLK_DATA_TIME_MASK); 2352 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2353 B_AX_RX_DLK_CCA_TIME_MASK); 2354 rtw89_write16(rtwdev, reg, val); 2355 2356 reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); 2357 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2358 2359 reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); 2360 if (mac_idx == RTW89_MAC_0) 2361 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2362 else 2363 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2364 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2365 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2366 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2367 rx_max_len /= RX_MAX_LEN_UNIT; 2368 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2369 2370 if (rtwdev->chip->chip_id == RTL8852A && 2371 rtwdev->hal.cv == CHIP_CBV) { 2372 rtw89_write16_mask(rtwdev, 2373 rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), 2374 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2375 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), 2376 BIT(12)); 2377 } 2378 2379 reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); 2380 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2381 2382 return ret; 2383 } 2384 2385 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2386 { 2387 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2388 u32 val, reg; 2389 int ret; 2390 2391 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2392 if (ret) 2393 return ret; 2394 2395 reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2396 val = rtw89_read32(rtwdev, reg); 2397 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2398 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2399 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2400 rtw89_write32(rtwdev, reg, val); 2401 2402 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2403 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx); 2404 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2405 } 2406 2407 return 0; 2408 } 2409 2410 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2411 { 2412 const struct rtw89_dle_mem *cfg; 2413 2414 cfg = get_dle_mem_cfg(rtwdev, mode); 2415 if (!cfg) { 2416 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2417 return false; 2418 } 2419 2420 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2421 } 2422 2423 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2424 { 2425 u32 val, reg; 2426 int ret; 2427 2428 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2429 if (ret) 2430 return ret; 2431 2432 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2433 reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2434 val = rtw89_read32(rtwdev, reg); 2435 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2436 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2437 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2438 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2439 val |= B_AX_HW_CTS2SELF_EN; 2440 rtw89_write32(rtwdev, reg, val); 2441 2442 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); 2443 val = rtw89_read32(rtwdev, reg); 2444 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2445 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2446 rtw89_write32(rtwdev, reg, val); 2447 } 2448 2449 if (mac_idx == RTW89_MAC_0) { 2450 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2451 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2452 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2453 B_AX_PTCL_TRIGGER_SS_EN_0 | 2454 B_AX_PTCL_TRIGGER_SS_EN_1 | 2455 B_AX_PTCL_TRIGGER_SS_EN_UL); 2456 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2457 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2458 } else if (mac_idx == RTW89_MAC_1) { 2459 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2460 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2461 } 2462 2463 return 0; 2464 } 2465 2466 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2467 { 2468 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2469 u32 reg; 2470 int ret; 2471 2472 if (chip_id != RTL8852A && chip_id != RTL8852B) 2473 return 0; 2474 2475 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2476 if (ret) 2477 return ret; 2478 2479 reg = rtw89_mac_reg_by_idx(R_AX_RXDMA_CTRL_0, mac_idx); 2480 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2481 2482 return 0; 2483 } 2484 2485 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2486 { 2487 int ret; 2488 2489 ret = scheduler_init(rtwdev, mac_idx); 2490 if (ret) { 2491 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2492 return ret; 2493 } 2494 2495 ret = addr_cam_init(rtwdev, mac_idx); 2496 if (ret) { 2497 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2498 ret); 2499 return ret; 2500 } 2501 2502 ret = rx_fltr_init(rtwdev, mac_idx); 2503 if (ret) { 2504 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2505 ret); 2506 return ret; 2507 } 2508 2509 ret = cca_ctrl_init(rtwdev, mac_idx); 2510 if (ret) { 2511 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2512 ret); 2513 return ret; 2514 } 2515 2516 ret = nav_ctrl_init(rtwdev); 2517 if (ret) { 2518 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2519 ret); 2520 return ret; 2521 } 2522 2523 ret = spatial_reuse_init(rtwdev, mac_idx); 2524 if (ret) { 2525 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2526 mac_idx, ret); 2527 return ret; 2528 } 2529 2530 ret = tmac_init(rtwdev, mac_idx); 2531 if (ret) { 2532 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2533 return ret; 2534 } 2535 2536 ret = trxptcl_init(rtwdev, mac_idx); 2537 if (ret) { 2538 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2539 return ret; 2540 } 2541 2542 ret = rmac_init(rtwdev, mac_idx); 2543 if (ret) { 2544 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2545 return ret; 2546 } 2547 2548 ret = cmac_com_init(rtwdev, mac_idx); 2549 if (ret) { 2550 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2551 return ret; 2552 } 2553 2554 ret = ptcl_init(rtwdev, mac_idx); 2555 if (ret) { 2556 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2557 return ret; 2558 } 2559 2560 ret = cmac_dma_init(rtwdev, mac_idx); 2561 if (ret) { 2562 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2563 return ret; 2564 } 2565 2566 return ret; 2567 } 2568 2569 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2570 struct rtw89_mac_c2h_info *c2h_info) 2571 { 2572 struct rtw89_mac_h2c_info h2c_info = {0}; 2573 u32 ret; 2574 2575 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2576 h2c_info.content_len = 0; 2577 2578 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2579 if (ret) 2580 return ret; 2581 2582 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2583 return -EINVAL; 2584 2585 return 0; 2586 } 2587 2588 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2589 { 2590 struct rtw89_hal *hal = &rtwdev->hal; 2591 const struct rtw89_chip_info *chip = rtwdev->chip; 2592 struct rtw89_mac_c2h_info c2h_info = {0}; 2593 u8 tx_nss; 2594 u8 rx_nss; 2595 u8 tx_ant; 2596 u8 rx_ant; 2597 u32 ret; 2598 2599 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2600 if (ret) 2601 return ret; 2602 2603 tx_nss = RTW89_GET_C2H_PHYCAP_TX_NSS(c2h_info.c2hreg); 2604 rx_nss = RTW89_GET_C2H_PHYCAP_RX_NSS(c2h_info.c2hreg); 2605 tx_ant = RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(c2h_info.c2hreg); 2606 rx_ant = RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(c2h_info.c2hreg); 2607 2608 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2609 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2610 2611 if (tx_ant == 1) 2612 hal->antenna_tx = RF_B; 2613 if (rx_ant == 1) 2614 hal->antenna_rx = RF_B; 2615 2616 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2617 hal->antenna_tx = RF_B; 2618 hal->tx_path_diversity = true; 2619 } 2620 2621 rtw89_debug(rtwdev, RTW89_DBG_FW, 2622 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2623 hal->tx_nss, tx_nss, chip->tx_nss, 2624 hal->rx_nss, rx_nss, chip->rx_nss); 2625 rtw89_debug(rtwdev, RTW89_DBG_FW, 2626 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2627 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2628 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2629 2630 return 0; 2631 } 2632 2633 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2634 u16 tx_en_u16, u16 mask_u16) 2635 { 2636 u32 ret; 2637 struct rtw89_mac_c2h_info c2h_info = {0}; 2638 struct rtw89_mac_h2c_info h2c_info = {0}; 2639 struct rtw89_h2creg_sch_tx_en *h2creg = 2640 (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; 2641 2642 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2643 h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; 2644 h2creg->tx_en = tx_en_u16; 2645 h2creg->mask = mask_u16; 2646 h2creg->band = band; 2647 2648 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2649 if (ret) 2650 return ret; 2651 2652 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2653 return -EINVAL; 2654 2655 return 0; 2656 } 2657 2658 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2659 u16 tx_en, u16 tx_en_mask) 2660 { 2661 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); 2662 u16 val; 2663 int ret; 2664 2665 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2666 if (ret) 2667 return ret; 2668 2669 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2670 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2671 tx_en, tx_en_mask); 2672 2673 val = rtw89_read16(rtwdev, reg); 2674 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2675 rtw89_write16(rtwdev, reg, val); 2676 2677 return 0; 2678 } 2679 2680 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2681 u32 tx_en, u32 tx_en_mask) 2682 { 2683 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx); 2684 u32 val; 2685 int ret; 2686 2687 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2688 if (ret) 2689 return ret; 2690 2691 val = rtw89_read32(rtwdev, reg); 2692 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2693 rtw89_write32(rtwdev, reg, val); 2694 2695 return 0; 2696 } 2697 2698 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2699 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2700 { 2701 int ret; 2702 2703 *tx_en = rtw89_read16(rtwdev, 2704 rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); 2705 2706 switch (sel) { 2707 case RTW89_SCH_TX_SEL_ALL: 2708 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2709 B_AX_CTN_TXEN_ALL_MASK); 2710 if (ret) 2711 return ret; 2712 break; 2713 case RTW89_SCH_TX_SEL_HIQ: 2714 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2715 0, B_AX_CTN_TXEN_HGQ); 2716 if (ret) 2717 return ret; 2718 break; 2719 case RTW89_SCH_TX_SEL_MG0: 2720 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2721 0, B_AX_CTN_TXEN_MGQ); 2722 if (ret) 2723 return ret; 2724 break; 2725 case RTW89_SCH_TX_SEL_MACID: 2726 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2727 B_AX_CTN_TXEN_ALL_MASK); 2728 if (ret) 2729 return ret; 2730 break; 2731 default: 2732 return 0; 2733 } 2734 2735 return 0; 2736 } 2737 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2738 2739 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2740 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2741 { 2742 int ret; 2743 2744 *tx_en = rtw89_read32(rtwdev, 2745 rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx)); 2746 2747 switch (sel) { 2748 case RTW89_SCH_TX_SEL_ALL: 2749 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2750 B_AX_CTN_TXEN_ALL_MASK_V1); 2751 if (ret) 2752 return ret; 2753 break; 2754 case RTW89_SCH_TX_SEL_HIQ: 2755 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2756 0, B_AX_CTN_TXEN_HGQ); 2757 if (ret) 2758 return ret; 2759 break; 2760 case RTW89_SCH_TX_SEL_MG0: 2761 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2762 0, B_AX_CTN_TXEN_MGQ); 2763 if (ret) 2764 return ret; 2765 break; 2766 case RTW89_SCH_TX_SEL_MACID: 2767 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2768 B_AX_CTN_TXEN_ALL_MASK_V1); 2769 if (ret) 2770 return ret; 2771 break; 2772 default: 2773 return 0; 2774 } 2775 2776 return 0; 2777 } 2778 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2779 2780 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2781 { 2782 int ret; 2783 2784 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2785 if (ret) 2786 return ret; 2787 2788 return 0; 2789 } 2790 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2791 2792 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2793 { 2794 int ret; 2795 2796 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2797 B_AX_CTN_TXEN_ALL_MASK_V1); 2798 if (ret) 2799 return ret; 2800 2801 return 0; 2802 } 2803 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2804 2805 u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd) 2806 { 2807 u32 val, reg; 2808 int ret; 2809 2810 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2811 val = buf_len; 2812 val |= B_AX_WD_BUF_REQ_EXEC; 2813 rtw89_write32(rtwdev, reg, val); 2814 2815 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2816 2817 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2818 1, 2000, false, rtwdev, reg); 2819 if (ret) 2820 return 0xffff; 2821 2822 return FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2823 } 2824 2825 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2826 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 2827 { 2828 u32 val, cmd_type, reg; 2829 int ret; 2830 2831 cmd_type = ctrl_para->cmd_type; 2832 2833 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2834 val = 0; 2835 val = u32_replace_bits(val, ctrl_para->start_pktid, 2836 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2837 val = u32_replace_bits(val, ctrl_para->end_pktid, 2838 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2839 rtw89_write32(rtwdev, reg, val); 2840 2841 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2842 val = 0; 2843 val = u32_replace_bits(val, ctrl_para->src_pid, 2844 B_AX_CPUQ_OP_SRC_PID_MASK); 2845 val = u32_replace_bits(val, ctrl_para->src_qid, 2846 B_AX_CPUQ_OP_SRC_QID_MASK); 2847 val = u32_replace_bits(val, ctrl_para->dst_pid, 2848 B_AX_CPUQ_OP_DST_PID_MASK); 2849 val = u32_replace_bits(val, ctrl_para->dst_qid, 2850 B_AX_CPUQ_OP_DST_QID_MASK); 2851 rtw89_write32(rtwdev, reg, val); 2852 2853 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2854 val = 0; 2855 val = u32_replace_bits(val, cmd_type, 2856 B_AX_CPUQ_OP_CMD_TYPE_MASK); 2857 val = u32_replace_bits(val, ctrl_para->macid, 2858 B_AX_CPUQ_OP_MACID_MASK); 2859 val = u32_replace_bits(val, ctrl_para->pkt_num, 2860 B_AX_CPUQ_OP_PKTNUM_MASK); 2861 val |= B_AX_WD_CPUQ_OP_EXEC; 2862 rtw89_write32(rtwdev, reg, val); 2863 2864 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2865 2866 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2867 1, 2000, false, rtwdev, reg); 2868 if (ret) 2869 return ret; 2870 2871 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2872 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2873 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2874 2875 return 0; 2876 } 2877 2878 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2879 { 2880 const struct rtw89_dle_mem *cfg; 2881 struct rtw89_cpuio_ctrl ctrl_para = {0}; 2882 u16 pkt_id; 2883 int ret; 2884 2885 cfg = get_dle_mem_cfg(rtwdev, mode); 2886 if (!cfg) { 2887 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2888 return -EINVAL; 2889 } 2890 2891 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 2892 dle_expected_used_size(rtwdev, mode)) { 2893 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2894 return -EINVAL; 2895 } 2896 2897 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2898 2899 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true); 2900 if (pkt_id == 0xffff) { 2901 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2902 return -ENOMEM; 2903 } 2904 2905 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2906 ctrl_para.start_pktid = pkt_id; 2907 ctrl_para.end_pktid = pkt_id; 2908 ctrl_para.pkt_num = 0; 2909 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2910 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2911 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2912 if (ret) { 2913 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2914 return -EFAULT; 2915 } 2916 2917 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, false); 2918 if (pkt_id == 0xffff) { 2919 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2920 return -ENOMEM; 2921 } 2922 2923 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2924 ctrl_para.start_pktid = pkt_id; 2925 ctrl_para.end_pktid = pkt_id; 2926 ctrl_para.pkt_num = 0; 2927 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 2928 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 2929 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 2930 if (ret) { 2931 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 2932 return -EFAULT; 2933 } 2934 2935 return 0; 2936 } 2937 2938 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 2939 { 2940 int ret; 2941 u32 reg; 2942 u8 val; 2943 2944 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2945 if (ret) 2946 return ret; 2947 2948 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); 2949 2950 ret = read_poll_timeout(rtw89_read8, val, 2951 (val & B_AX_PTCL_TX_ON_STAT) == 0, 2952 SW_CVR_DUR_US, 2953 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 2954 false, rtwdev, reg); 2955 if (ret) 2956 return ret; 2957 2958 return 0; 2959 } 2960 2961 static int band1_enable(struct rtw89_dev *rtwdev) 2962 { 2963 int ret, i; 2964 u32 sleep_bak[4] = {0}; 2965 u32 pause_bak[4] = {0}; 2966 u32 tx_en; 2967 2968 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 2969 if (ret) { 2970 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 2971 return ret; 2972 } 2973 2974 for (i = 0; i < 4; i++) { 2975 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 2976 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 2977 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 2978 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 2979 } 2980 2981 ret = band_idle_ck_b(rtwdev, 0); 2982 if (ret) { 2983 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 2984 return ret; 2985 } 2986 2987 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 2988 if (ret) { 2989 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 2990 return ret; 2991 } 2992 2993 for (i = 0; i < 4; i++) { 2994 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 2995 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 2996 } 2997 2998 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 2999 if (ret) { 3000 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3001 return ret; 3002 } 3003 3004 ret = cmac_func_en(rtwdev, 1, true); 3005 if (ret) { 3006 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3007 return ret; 3008 } 3009 3010 ret = cmac_init(rtwdev, 1); 3011 if (ret) { 3012 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3013 return ret; 3014 } 3015 3016 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3017 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3018 3019 return 0; 3020 } 3021 3022 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3023 { 3024 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3025 3026 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3027 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3028 } 3029 3030 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3031 { 3032 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3033 3034 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3035 } 3036 3037 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3038 { 3039 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3040 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3041 3042 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3043 B_AX_TX_GET_ERRPKTID_INT_EN | 3044 B_AX_TX_NXT_ERRPKTID_INT_EN | 3045 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3046 B_AX_TX_OFFSET_ERR_INT_EN | 3047 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3048 if (chip_id == RTL8852C) 3049 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3050 B_AX_TX_ETH_TYPE_ERR_EN | 3051 B_AX_TX_LLC_PRE_ERR_EN | 3052 B_AX_TX_NW_TYPE_ERR_EN | 3053 B_AX_TX_KSRCH_ERR_EN); 3054 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3055 imr->mpdu_tx_imr_set); 3056 3057 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3058 B_AX_GETPKTID_ERR_INT_EN | 3059 B_AX_MHDRLEN_ERR_INT_EN | 3060 B_AX_RPT_ERR_INT_EN); 3061 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3062 imr->mpdu_rx_imr_set); 3063 } 3064 3065 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3066 { 3067 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3068 3069 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3070 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3071 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3072 B_AX_PLE_B_PKTID_ERR_INT_EN); 3073 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3074 imr->sta_sch_imr_set); 3075 } 3076 3077 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3078 { 3079 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3080 3081 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3082 imr->txpktctl_imr_b0_clr); 3083 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3084 imr->txpktctl_imr_b0_set); 3085 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3086 imr->txpktctl_imr_b1_clr); 3087 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3088 imr->txpktctl_imr_b1_set); 3089 } 3090 3091 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3092 { 3093 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3094 3095 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3096 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3097 } 3098 3099 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3100 { 3101 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3102 3103 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3104 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3105 } 3106 3107 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3108 { 3109 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3110 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3111 } 3112 3113 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3114 { 3115 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3116 3117 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3118 imr->host_disp_imr_clr); 3119 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3120 imr->host_disp_imr_set); 3121 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3122 imr->cpu_disp_imr_clr); 3123 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3124 imr->cpu_disp_imr_set); 3125 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3126 imr->other_disp_imr_clr); 3127 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3128 imr->other_disp_imr_set); 3129 } 3130 3131 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3132 { 3133 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3134 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3135 } 3136 3137 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3138 { 3139 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3140 3141 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3142 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3143 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3144 B_AX_BBRPT_CHINFO_IMR_CLR); 3145 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3146 imr->bbrpt_err_imr_set); 3147 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3148 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3149 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3150 } 3151 3152 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3153 { 3154 u32 reg; 3155 3156 reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); 3157 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3158 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3159 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3160 } 3161 3162 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3163 { 3164 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3165 u32 reg; 3166 3167 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); 3168 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3169 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3170 } 3171 3172 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3173 { 3174 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3175 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3176 u32 reg; 3177 3178 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx); 3179 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3180 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3181 3182 if (chip_id == RTL8852C) { 3183 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx); 3184 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3185 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3186 } 3187 } 3188 3189 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3190 { 3191 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3192 u32 reg; 3193 3194 reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx); 3195 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3196 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3197 } 3198 3199 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3200 { 3201 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3202 u32 reg; 3203 3204 reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx); 3205 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3206 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3207 } 3208 3209 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3210 { 3211 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3212 u32 reg; 3213 3214 reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx); 3215 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3216 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3217 } 3218 3219 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 3220 enum rtw89_mac_hwmod_sel sel) 3221 { 3222 int ret; 3223 3224 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3225 if (ret) { 3226 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3227 sel, mac_idx); 3228 return ret; 3229 } 3230 3231 if (sel == RTW89_DMAC_SEL) { 3232 rtw89_wdrls_imr_enable(rtwdev); 3233 rtw89_wsec_imr_enable(rtwdev); 3234 rtw89_mpdu_trx_imr_enable(rtwdev); 3235 rtw89_sta_sch_imr_enable(rtwdev); 3236 rtw89_txpktctl_imr_enable(rtwdev); 3237 rtw89_wde_imr_enable(rtwdev); 3238 rtw89_ple_imr_enable(rtwdev); 3239 rtw89_pktin_imr_enable(rtwdev); 3240 rtw89_dispatcher_imr_enable(rtwdev); 3241 rtw89_cpuio_imr_enable(rtwdev); 3242 rtw89_bbrpt_imr_enable(rtwdev); 3243 } else if (sel == RTW89_CMAC_SEL) { 3244 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3245 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3246 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3247 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3248 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3249 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3250 } else { 3251 return -EINVAL; 3252 } 3253 3254 return 0; 3255 } 3256 3257 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) 3258 { 3259 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3260 3261 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3262 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3263 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3264 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3265 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 3266 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3267 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3268 } 3269 3270 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 3271 { 3272 int ret = 0; 3273 3274 if (enable) { 3275 ret = band1_enable(rtwdev); 3276 if (ret) { 3277 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3278 return ret; 3279 } 3280 3281 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3282 if (ret) { 3283 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3284 return ret; 3285 } 3286 } else { 3287 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3288 return -EINVAL; 3289 } 3290 3291 return 0; 3292 } 3293 3294 static int set_host_rpr(struct rtw89_dev *rtwdev) 3295 { 3296 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3297 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3298 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3299 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3300 B_AX_RLSRPT0_FLTR_MAP_MASK); 3301 } else { 3302 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3303 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3304 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3305 B_AX_RLSRPT0_FLTR_MAP_MASK); 3306 } 3307 3308 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3309 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3310 3311 return 0; 3312 } 3313 3314 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 3315 { 3316 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3317 int ret; 3318 3319 ret = dmac_init(rtwdev, 0); 3320 if (ret) { 3321 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3322 return ret; 3323 } 3324 3325 ret = cmac_init(rtwdev, 0); 3326 if (ret) { 3327 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3328 return ret; 3329 } 3330 3331 if (is_qta_dbcc(rtwdev, qta_mode)) { 3332 ret = rtw89_mac_dbcc_enable(rtwdev, true); 3333 if (ret) { 3334 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3335 return ret; 3336 } 3337 } 3338 3339 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3340 if (ret) { 3341 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3342 return ret; 3343 } 3344 3345 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3346 if (ret) { 3347 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3348 return ret; 3349 } 3350 3351 rtw89_mac_err_imr_ctrl(rtwdev, true); 3352 3353 ret = set_host_rpr(rtwdev); 3354 if (ret) { 3355 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3356 return ret; 3357 } 3358 3359 return 0; 3360 } 3361 3362 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3363 { 3364 u32 val32; 3365 3366 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3367 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3368 3369 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3370 val32 |= B_AX_FS_WDT_INT; 3371 val32 &= ~B_AX_FS_WDT_INT_MSK; 3372 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3373 } 3374 3375 void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) 3376 { 3377 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3378 3379 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3380 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3381 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3382 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3383 3384 rtw89_disable_fw_watchdog(rtwdev); 3385 3386 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3387 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3388 } 3389 3390 int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw) 3391 { 3392 u32 val; 3393 int ret; 3394 3395 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3396 return -EFAULT; 3397 3398 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3399 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3400 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3401 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3402 3403 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3404 3405 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3406 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3407 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3408 B_AX_WCPU_FWDL_STS_MASK); 3409 3410 if (dlfw) 3411 val |= B_AX_WCPU_FWDL_EN; 3412 3413 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3414 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3415 boot_reason); 3416 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3417 3418 if (!dlfw) { 3419 mdelay(5); 3420 3421 ret = rtw89_fw_check_rdy(rtwdev); 3422 if (ret) 3423 return ret; 3424 } 3425 3426 return 0; 3427 } 3428 3429 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3430 { 3431 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3432 u32 val; 3433 int ret; 3434 3435 if (chip_id == RTL8852C) 3436 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3437 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3438 else 3439 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3440 B_AX_PKT_BUF_EN; 3441 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3442 3443 val = B_AX_DISPATCHER_CLK_EN; 3444 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3445 3446 if (chip_id != RTL8852C) 3447 goto dle; 3448 3449 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3450 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3451 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3452 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3453 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3454 3455 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3456 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3457 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3458 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3459 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3460 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3461 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3462 3463 dle: 3464 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3465 if (ret) { 3466 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3467 return ret; 3468 } 3469 3470 ret = hfc_init(rtwdev, true, false, true); 3471 if (ret) { 3472 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3473 return ret; 3474 } 3475 3476 return ret; 3477 } 3478 3479 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3480 { 3481 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3482 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3483 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3484 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3485 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3486 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3487 3488 return 0; 3489 } 3490 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3491 3492 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3493 { 3494 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3495 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3496 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3497 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3498 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3499 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3500 3501 return 0; 3502 } 3503 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3504 3505 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) 3506 { 3507 int ret; 3508 3509 ret = rtw89_mac_power_switch(rtwdev, true); 3510 if (ret) { 3511 rtw89_mac_power_switch(rtwdev, false); 3512 ret = rtw89_mac_power_switch(rtwdev, true); 3513 if (ret) 3514 return ret; 3515 } 3516 3517 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3518 3519 ret = rtw89_mac_dmac_pre_init(rtwdev); 3520 if (ret) 3521 return ret; 3522 3523 if (rtwdev->hci.ops->mac_pre_init) { 3524 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3525 if (ret) 3526 return ret; 3527 } 3528 3529 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); 3530 if (ret) 3531 return ret; 3532 3533 return 0; 3534 } 3535 3536 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3537 { 3538 int ret; 3539 3540 ret = rtw89_mac_partial_init(rtwdev); 3541 if (ret) 3542 goto fail; 3543 3544 ret = rtw89_chip_enable_bb_rf(rtwdev); 3545 if (ret) 3546 goto fail; 3547 3548 ret = rtw89_mac_sys_init(rtwdev); 3549 if (ret) 3550 goto fail; 3551 3552 ret = rtw89_mac_trx_init(rtwdev); 3553 if (ret) 3554 goto fail; 3555 3556 if (rtwdev->hci.ops->mac_post_init) { 3557 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3558 if (ret) 3559 goto fail; 3560 } 3561 3562 rtw89_fw_send_all_early_h2c(rtwdev); 3563 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3564 3565 return ret; 3566 fail: 3567 rtw89_mac_power_switch(rtwdev, false); 3568 3569 return ret; 3570 } 3571 3572 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3573 { 3574 u8 i; 3575 3576 for (i = 0; i < 4; i++) { 3577 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3578 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3579 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3580 } 3581 } 3582 3583 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3584 { 3585 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3586 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3587 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3588 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3589 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3590 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3591 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3592 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3593 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3594 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3595 } 3596 3597 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3598 { 3599 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3600 u8 grp = macid >> 5; 3601 int ret; 3602 3603 /* If this is called by change_interface() in the case of P2P, it could 3604 * be power-off, so ignore this operation. 3605 */ 3606 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 3607 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3608 return 0; 3609 3610 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3611 if (ret) 3612 return ret; 3613 3614 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3615 3616 return 0; 3617 } 3618 3619 static const struct rtw89_port_reg rtw_port_base = { 3620 .port_cfg = R_AX_PORT_CFG_P0, 3621 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3622 .bcn_area = R_AX_BCN_AREA_P0, 3623 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3624 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3625 .tbtt_agg = R_AX_TBTT_AGG_P0, 3626 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3627 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3628 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3629 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3630 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3631 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3632 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3633 .tsftr_l = R_AX_TSFTR_LOW_P0, 3634 .tsftr_h = R_AX_TSFTR_HIGH_P0 3635 }; 3636 3637 #define BCN_INTERVAL 100 3638 #define BCN_ERLY_DEF 160 3639 #define BCN_SETUP_DEF 2 3640 #define BCN_HOLD_DEF 200 3641 #define BCN_MASK_DEF 0 3642 #define TBTT_ERLY_DEF 5 3643 #define BCN_SET_UNIT 32 3644 #define BCN_ERLY_SET_DLY (10 * 2) 3645 3646 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3647 struct rtw89_vif *rtwvif) 3648 { 3649 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3650 const struct rtw89_port_reg *p = &rtw_port_base; 3651 3652 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3653 return; 3654 3655 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3656 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3657 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3658 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3659 3660 msleep(vif->bss_conf.beacon_int + 1); 3661 3662 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3663 B_AX_BRK_SETUP); 3664 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3665 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3666 } 3667 3668 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3669 struct rtw89_vif *rtwvif, bool en) 3670 { 3671 const struct rtw89_port_reg *p = &rtw_port_base; 3672 3673 if (en) 3674 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3675 else 3676 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3677 } 3678 3679 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3680 struct rtw89_vif *rtwvif, bool en) 3681 { 3682 const struct rtw89_port_reg *p = &rtw_port_base; 3683 3684 if (en) 3685 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3686 else 3687 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3688 } 3689 3690 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3691 struct rtw89_vif *rtwvif) 3692 { 3693 const struct rtw89_port_reg *p = &rtw_port_base; 3694 3695 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3696 rtwvif->net_type); 3697 } 3698 3699 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3700 struct rtw89_vif *rtwvif) 3701 { 3702 const struct rtw89_port_reg *p = &rtw_port_base; 3703 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3704 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3705 3706 if (en) 3707 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3708 else 3709 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3710 } 3711 3712 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3713 struct rtw89_vif *rtwvif) 3714 { 3715 const struct rtw89_port_reg *p = &rtw_port_base; 3716 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3717 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3718 u32 bit = B_AX_RX_BSSID_FIT_EN; 3719 3720 if (en) 3721 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3722 else 3723 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3724 } 3725 3726 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3727 struct rtw89_vif *rtwvif) 3728 { 3729 const struct rtw89_port_reg *p = &rtw_port_base; 3730 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3731 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3732 3733 if (en) 3734 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3735 else 3736 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3737 } 3738 3739 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3740 struct rtw89_vif *rtwvif) 3741 { 3742 const struct rtw89_port_reg *p = &rtw_port_base; 3743 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3744 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3745 3746 if (en) 3747 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3748 else 3749 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3750 } 3751 3752 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3753 struct rtw89_vif *rtwvif) 3754 { 3755 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3756 const struct rtw89_port_reg *p = &rtw_port_base; 3757 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3758 3759 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3760 bcn_int); 3761 } 3762 3763 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3764 struct rtw89_vif *rtwvif) 3765 { 3766 static const u32 hiq_win_addr[RTW89_PORT_NUM] = { 3767 R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3768 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3769 R_AX_PORT_HGQ_WINDOW_CFG + 3, 3770 }; 3771 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3772 u8 port = rtwvif->port; 3773 u32 reg; 3774 3775 reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx); 3776 rtw89_write8(rtwdev, reg, win); 3777 } 3778 3779 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3780 struct rtw89_vif *rtwvif) 3781 { 3782 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3783 const struct rtw89_port_reg *p = &rtw_port_base; 3784 u32 addr; 3785 3786 addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); 3787 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3788 3789 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3790 vif->bss_conf.dtim_period); 3791 } 3792 3793 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3794 struct rtw89_vif *rtwvif) 3795 { 3796 const struct rtw89_port_reg *p = &rtw_port_base; 3797 3798 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3799 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3800 } 3801 3802 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3803 struct rtw89_vif *rtwvif) 3804 { 3805 const struct rtw89_port_reg *p = &rtw_port_base; 3806 3807 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3808 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3809 } 3810 3811 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3812 struct rtw89_vif *rtwvif) 3813 { 3814 const struct rtw89_port_reg *p = &rtw_port_base; 3815 3816 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3817 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3818 } 3819 3820 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3821 struct rtw89_vif *rtwvif) 3822 { 3823 const struct rtw89_port_reg *p = &rtw_port_base; 3824 3825 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3826 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3827 } 3828 3829 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3830 struct rtw89_vif *rtwvif) 3831 { 3832 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3833 static const u32 masks[RTW89_PORT_NUM] = { 3834 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3835 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3836 B_AX_BSS_COLOB_AX_PORT_4_MASK, 3837 }; 3838 u8 port = rtwvif->port; 3839 u32 reg_base; 3840 u32 reg; 3841 u8 bss_color; 3842 3843 bss_color = vif->bss_conf.he_bss_color.color; 3844 reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; 3845 reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); 3846 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3847 } 3848 3849 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3850 struct rtw89_vif *rtwvif) 3851 { 3852 u8 port = rtwvif->port; 3853 u32 reg; 3854 3855 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3856 return; 3857 3858 if (port == 0) { 3859 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); 3860 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3861 } 3862 } 3863 3864 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3865 struct rtw89_vif *rtwvif) 3866 { 3867 u8 port = rtwvif->port; 3868 u32 reg; 3869 u32 val; 3870 3871 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); 3872 val = rtw89_read32(rtwdev, reg); 3873 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 3874 if (port == 0) 3875 val &= ~BIT(0); 3876 rtw89_write32(rtwdev, reg, val); 3877 } 3878 3879 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 3880 struct rtw89_vif *rtwvif, bool enable) 3881 { 3882 const struct rtw89_port_reg *p = &rtw_port_base; 3883 3884 if (enable) 3885 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 3886 B_AX_PORT_FUNC_EN); 3887 else 3888 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 3889 B_AX_PORT_FUNC_EN); 3890 } 3891 3892 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 3893 struct rtw89_vif *rtwvif) 3894 { 3895 const struct rtw89_port_reg *p = &rtw_port_base; 3896 3897 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 3898 BCN_ERLY_DEF); 3899 } 3900 3901 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 3902 struct rtw89_vif *rtwvif) 3903 { 3904 const struct rtw89_port_reg *p = &rtw_port_base; 3905 u16 val; 3906 3907 if (rtwdev->chip->chip_id != RTL8852C) 3908 return; 3909 3910 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 3911 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 3912 return; 3913 3914 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 3915 B_AX_TBTT_SHIFT_OFST_SIGN; 3916 3917 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 3918 B_AX_TBTT_SHIFT_OFST_MASK, val); 3919 } 3920 3921 static void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 3922 struct rtw89_vif *rtwvif, 3923 struct rtw89_vif *rtwvif_src, u8 offset, 3924 int *n_offset) 3925 { 3926 u32 val, reg; 3927 3928 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 3929 return; 3930 3931 /* adjust offset randomly to avoid beacon conflict */ 3932 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 3933 val = RTW89_PORT_OFFSET_MS_TO_32US((*n_offset)++, offset); 3934 reg = rtw89_mac_reg_by_idx(R_AX_PORT0_TSF_SYNC + rtwvif->port * 4, 3935 rtwvif->mac_idx); 3936 3937 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 3938 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 3939 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 3940 } 3941 3942 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 3943 { 3944 struct rtw89_vif *src = NULL, *tmp; 3945 u8 offset = 100, vif_aps = 0; 3946 int n_offset = 1; 3947 3948 rtw89_for_each_rtwvif(rtwdev, tmp) { 3949 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 3950 src = tmp; 3951 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 3952 vif_aps++; 3953 } 3954 3955 if (vif_aps == 0) 3956 return; 3957 3958 offset /= (vif_aps + 1); 3959 3960 rtw89_for_each_rtwvif(rtwdev, tmp) 3961 rtw89_mac_port_tsf_sync(rtwdev, tmp, src, offset, &n_offset); 3962 } 3963 3964 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3965 { 3966 int ret; 3967 3968 ret = rtw89_mac_port_update(rtwdev, rtwvif); 3969 if (ret) 3970 return ret; 3971 3972 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 3973 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 3974 3975 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 3976 if (ret) 3977 return ret; 3978 3979 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 3980 if (ret) 3981 return ret; 3982 3983 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 3984 if (ret) 3985 return ret; 3986 3987 ret = rtw89_cam_init(rtwdev, rtwvif); 3988 if (ret) 3989 return ret; 3990 3991 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3992 if (ret) 3993 return ret; 3994 3995 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 3996 if (ret) 3997 return ret; 3998 3999 return 0; 4000 } 4001 4002 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4003 { 4004 int ret; 4005 4006 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4007 if (ret) 4008 return ret; 4009 4010 rtw89_cam_deinit(rtwdev, rtwvif); 4011 4012 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4013 if (ret) 4014 return ret; 4015 4016 return 0; 4017 } 4018 4019 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4020 { 4021 u8 port = rtwvif->port; 4022 4023 if (port >= RTW89_PORT_NUM) 4024 return -EINVAL; 4025 4026 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4027 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4028 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4029 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4030 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4031 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4032 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 4033 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 4034 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4035 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4036 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4037 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4038 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4039 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4040 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4041 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4042 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4043 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4044 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4045 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4046 rtw89_mac_port_tsf_resync_all(rtwdev); 4047 fsleep(BCN_ERLY_SET_DLY); 4048 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4049 4050 return 0; 4051 } 4052 4053 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4054 struct cfg80211_bss *bss, 4055 void *data) 4056 { 4057 const struct cfg80211_bss_ies *ies; 4058 const struct element *elem; 4059 bool *tolerated = data; 4060 4061 rcu_read_lock(); 4062 ies = rcu_dereference(bss->ies); 4063 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4064 ies->len); 4065 4066 if (!elem || elem->datalen < 10 || 4067 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4068 *tolerated = false; 4069 rcu_read_unlock(); 4070 } 4071 4072 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4073 struct ieee80211_vif *vif) 4074 { 4075 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4076 struct ieee80211_hw *hw = rtwdev->hw; 4077 bool tolerated = true; 4078 u32 reg; 4079 4080 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 4081 return; 4082 4083 if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR)) 4084 return; 4085 4086 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef, 4087 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4088 &tolerated); 4089 4090 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); 4091 if (tolerated) 4092 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4093 else 4094 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4095 } 4096 4097 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4098 { 4099 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false); 4100 } 4101 4102 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4103 { 4104 int ret; 4105 4106 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 4107 RTW89_MAX_MAC_ID_NUM); 4108 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4109 return -ENOSPC; 4110 4111 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4112 if (ret) 4113 goto release_mac_id; 4114 4115 return 0; 4116 4117 release_mac_id: 4118 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4119 4120 return ret; 4121 } 4122 4123 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4124 { 4125 int ret; 4126 4127 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4128 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4129 4130 return ret; 4131 } 4132 4133 static void 4134 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4135 { 4136 } 4137 4138 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4139 { 4140 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 4141 4142 return band == scan_info->op_band && channel == scan_info->op_pri_ch; 4143 } 4144 4145 static void 4146 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4147 u32 len) 4148 { 4149 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4150 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4151 struct rtw89_chan new; 4152 u8 reason, status, tx_fail, band, actual_period; 4153 u32 last_chan = rtwdev->scan_info.last_chan_idx; 4154 u16 chan; 4155 int ret; 4156 4157 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 4158 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 4159 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 4160 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 4161 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 4162 actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data); 4163 4164 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4165 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4166 4167 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4168 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4169 band, chan, reason, status, tx_fail, actual_period); 4170 4171 switch (reason) { 4172 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4173 if (rtw89_is_op_chan(rtwdev, band, chan)) 4174 ieee80211_stop_queues(rtwdev->hw); 4175 return; 4176 case RTW89_SCAN_END_SCAN_NOTIFY: 4177 if (rtwvif && rtwvif->scan_req && 4178 last_chan < rtwvif->scan_req->n_channels) { 4179 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4180 if (ret) { 4181 rtw89_hw_scan_abort(rtwdev, vif); 4182 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4183 } 4184 } else { 4185 rtw89_hw_scan_complete(rtwdev, vif, false); 4186 } 4187 break; 4188 case RTW89_SCAN_ENTER_CH_NOTIFY: 4189 rtw89_chan_create(&new, chan, chan, band, RTW89_CHANNEL_WIDTH_20); 4190 rtw89_assign_entity_chan(rtwdev, RTW89_SUB_ENTITY_0, &new); 4191 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4192 rtw89_store_op_chan(rtwdev, false); 4193 ieee80211_wake_queues(rtwdev->hw); 4194 } 4195 break; 4196 default: 4197 return; 4198 } 4199 } 4200 4201 static void 4202 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4203 { 4204 rtw89_debug(rtwdev, RTW89_DBG_FW, 4205 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4206 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4207 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4208 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4209 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4210 } 4211 4212 static void 4213 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4214 { 4215 rtw89_debug(rtwdev, RTW89_DBG_FW, 4216 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4217 RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data), 4218 RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data), 4219 RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data), 4220 RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data), 4221 RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data)); 4222 } 4223 4224 static void 4225 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4226 { 4227 rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), 4228 RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); 4229 } 4230 4231 static void 4232 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4233 { 4234 } 4235 4236 static void 4237 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4238 u32 len) 4239 { 4240 } 4241 4242 static void 4243 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4244 u32 len) 4245 { 4246 } 4247 4248 static void 4249 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4250 { 4251 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4252 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4253 4254 switch (func) { 4255 case H2C_FUNC_ADD_MCC: 4256 case H2C_FUNC_START_MCC: 4257 case H2C_FUNC_STOP_MCC: 4258 case H2C_FUNC_DEL_MCC_GROUP: 4259 case H2C_FUNC_RESET_MCC_GROUP: 4260 case H2C_FUNC_MCC_REQ_TSF: 4261 case H2C_FUNC_MCC_MACID_BITMAP: 4262 case H2C_FUNC_MCC_SYNC: 4263 case H2C_FUNC_MCC_SET_DURATION: 4264 break; 4265 default: 4266 rtw89_debug(rtwdev, RTW89_DBG_FW, 4267 "invalid MCC C2H RCV ACK: func %d\n", func); 4268 return; 4269 } 4270 4271 rtw89_debug(rtwdev, RTW89_DBG_FW, 4272 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4273 } 4274 4275 static void 4276 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4277 { 4278 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4279 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4280 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4281 struct rtw89_completion_data data = {}; 4282 unsigned int cond; 4283 bool next = false; 4284 4285 switch (func) { 4286 case H2C_FUNC_MCC_REQ_TSF: 4287 next = true; 4288 break; 4289 case H2C_FUNC_MCC_MACID_BITMAP: 4290 case H2C_FUNC_MCC_SYNC: 4291 case H2C_FUNC_MCC_SET_DURATION: 4292 break; 4293 case H2C_FUNC_ADD_MCC: 4294 case H2C_FUNC_START_MCC: 4295 case H2C_FUNC_STOP_MCC: 4296 case H2C_FUNC_DEL_MCC_GROUP: 4297 case H2C_FUNC_RESET_MCC_GROUP: 4298 default: 4299 rtw89_debug(rtwdev, RTW89_DBG_FW, 4300 "invalid MCC C2H REQ ACK: func %d\n", func); 4301 return; 4302 } 4303 4304 rtw89_debug(rtwdev, RTW89_DBG_FW, 4305 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 4306 group, func, retcode); 4307 4308 if (!retcode && next) 4309 return; 4310 4311 data.err = !!retcode; 4312 cond = RTW89_MCC_WAIT_COND(group, func); 4313 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4314 } 4315 4316 static void 4317 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4318 { 4319 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 4320 struct rtw89_completion_data data = {}; 4321 struct rtw89_mac_mcc_tsf_rpt *rpt; 4322 unsigned int cond; 4323 4324 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 4325 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 4326 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 4327 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 4328 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 4329 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 4330 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 4331 4332 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 4333 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4334 } 4335 4336 static void 4337 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4338 { 4339 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 4340 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 4341 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 4342 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 4343 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 4344 struct rtw89_completion_data data = {}; 4345 unsigned int cond; 4346 bool rsp = true; 4347 bool err; 4348 u8 func; 4349 4350 switch (status) { 4351 case RTW89_MAC_MCC_ADD_ROLE_OK: 4352 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 4353 func = H2C_FUNC_ADD_MCC; 4354 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 4355 break; 4356 case RTW89_MAC_MCC_START_GROUP_OK: 4357 case RTW89_MAC_MCC_START_GROUP_FAIL: 4358 func = H2C_FUNC_START_MCC; 4359 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 4360 break; 4361 case RTW89_MAC_MCC_STOP_GROUP_OK: 4362 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 4363 func = H2C_FUNC_STOP_MCC; 4364 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 4365 break; 4366 case RTW89_MAC_MCC_DEL_GROUP_OK: 4367 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 4368 func = H2C_FUNC_DEL_MCC_GROUP; 4369 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 4370 break; 4371 case RTW89_MAC_MCC_RESET_GROUP_OK: 4372 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 4373 func = H2C_FUNC_RESET_MCC_GROUP; 4374 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 4375 break; 4376 case RTW89_MAC_MCC_SWITCH_CH_OK: 4377 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 4378 case RTW89_MAC_MCC_TXNULL0_OK: 4379 case RTW89_MAC_MCC_TXNULL0_FAIL: 4380 case RTW89_MAC_MCC_TXNULL1_OK: 4381 case RTW89_MAC_MCC_TXNULL1_FAIL: 4382 case RTW89_MAC_MCC_SWITCH_EARLY: 4383 case RTW89_MAC_MCC_TBTT: 4384 case RTW89_MAC_MCC_DURATION_START: 4385 case RTW89_MAC_MCC_DURATION_END: 4386 rsp = false; 4387 break; 4388 default: 4389 rtw89_debug(rtwdev, RTW89_DBG_FW, 4390 "invalid MCC C2H STS RPT: status %d\n", status); 4391 return; 4392 } 4393 4394 rtw89_debug(rtwdev, RTW89_DBG_FW, 4395 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf {%d, %d}\n", 4396 group, macid, status, tsf_low, tsf_high); 4397 4398 if (!rsp) 4399 return; 4400 4401 data.err = err; 4402 cond = RTW89_MCC_WAIT_COND(group, func); 4403 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4404 } 4405 4406 static 4407 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 4408 struct sk_buff *c2h, u32 len) = { 4409 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 4410 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 4411 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 4412 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 4413 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 4414 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 4415 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 4416 }; 4417 4418 static 4419 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 4420 struct sk_buff *c2h, u32 len) = { 4421 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 4422 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 4423 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 4424 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 4425 }; 4426 4427 static 4428 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 4429 struct sk_buff *c2h, u32 len) = { 4430 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 4431 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 4432 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 4433 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 4434 }; 4435 4436 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 4437 { 4438 switch (class) { 4439 default: 4440 return false; 4441 case RTW89_MAC_C2H_CLASS_MCC: 4442 return true; 4443 } 4444 } 4445 4446 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4447 u32 len, u8 class, u8 func) 4448 { 4449 void (*handler)(struct rtw89_dev *rtwdev, 4450 struct sk_buff *c2h, u32 len) = NULL; 4451 4452 switch (class) { 4453 case RTW89_MAC_C2H_CLASS_INFO: 4454 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 4455 handler = rtw89_mac_c2h_info_handler[func]; 4456 break; 4457 case RTW89_MAC_C2H_CLASS_OFLD: 4458 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 4459 handler = rtw89_mac_c2h_ofld_handler[func]; 4460 break; 4461 case RTW89_MAC_C2H_CLASS_MCC: 4462 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 4463 handler = rtw89_mac_c2h_mcc_handler[func]; 4464 break; 4465 case RTW89_MAC_C2H_CLASS_FWDBG: 4466 return; 4467 default: 4468 rtw89_info(rtwdev, "c2h class %d not support\n", class); 4469 return; 4470 } 4471 if (!handler) { 4472 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 4473 func); 4474 return; 4475 } 4476 handler(rtwdev, skb, len); 4477 } 4478 4479 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 4480 enum rtw89_phy_idx phy_idx, 4481 u32 reg_base, u32 *cr) 4482 { 4483 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 4484 enum rtw89_qta_mode mode = dle_mem->mode; 4485 u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); 4486 4487 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { 4488 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 4489 addr); 4490 goto error; 4491 } 4492 4493 if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) 4494 if (mode == RTW89_QTA_SCC) { 4495 rtw89_err(rtwdev, 4496 "[TXPWR] addr=0x%x but hw not enable\n", 4497 addr); 4498 goto error; 4499 } 4500 4501 *cr = addr; 4502 return true; 4503 4504 error: 4505 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 4506 addr, phy_idx); 4507 4508 return false; 4509 } 4510 EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); 4511 4512 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 4513 { 4514 u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); 4515 int ret = 0; 4516 4517 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4518 if (ret) 4519 return ret; 4520 4521 if (!enable) { 4522 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 4523 return ret; 4524 } 4525 4526 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 4527 B_AX_APP_MAC_INFO_RPT | 4528 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 4529 B_AX_PPDU_STAT_RPT_CRC32); 4530 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 4531 RTW89_PRPT_DEST_HOST); 4532 4533 return ret; 4534 } 4535 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 4536 4537 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 4538 { 4539 #define MAC_AX_TIME_TH_SH 5 4540 #define MAC_AX_LEN_TH_SH 4 4541 #define MAC_AX_TIME_TH_MAX 255 4542 #define MAC_AX_LEN_TH_MAX 255 4543 #define MAC_AX_TIME_TH_DEF 88 4544 #define MAC_AX_LEN_TH_DEF 4080 4545 struct ieee80211_hw *hw = rtwdev->hw; 4546 u32 rts_threshold = hw->wiphy->rts_threshold; 4547 u32 time_th, len_th; 4548 u32 reg; 4549 4550 if (rts_threshold == (u32)-1) { 4551 time_th = MAC_AX_TIME_TH_DEF; 4552 len_th = MAC_AX_LEN_TH_DEF; 4553 } else { 4554 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 4555 len_th = rts_threshold; 4556 } 4557 4558 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 4559 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 4560 4561 reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); 4562 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 4563 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 4564 } 4565 4566 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 4567 { 4568 bool empty; 4569 int ret; 4570 4571 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4572 return; 4573 4574 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 4575 10000, 200000, false, rtwdev); 4576 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 4577 rtw89_info(rtwdev, "timed out to flush queues\n"); 4578 } 4579 4580 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 4581 { 4582 u8 val; 4583 u16 val16; 4584 u32 val32; 4585 int ret; 4586 4587 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 4588 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 4589 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 4590 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 4591 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 4592 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 4593 4594 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 4595 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 4596 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 4597 4598 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 4599 if (ret) { 4600 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 4601 return ret; 4602 } 4603 val32 = val32 & B_AX_WL_RX_CTRL; 4604 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 4605 if (ret) { 4606 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 4607 return ret; 4608 } 4609 4610 switch (coex->pta_mode) { 4611 case RTW89_MAC_AX_COEX_RTK_MODE: 4612 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4613 val &= ~B_AX_BTMODE_MASK; 4614 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 4615 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4616 4617 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 4618 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 4619 4620 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 4621 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 4622 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 4623 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 4624 break; 4625 case RTW89_MAC_AX_COEX_CSR_MODE: 4626 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4627 val &= ~B_AX_BTMODE_MASK; 4628 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 4629 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4630 4631 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 4632 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 4633 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 4634 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 4635 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 4636 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 4637 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 4638 val16 |= B_AX_ENHANCED_BT; 4639 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 4640 4641 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 4642 break; 4643 default: 4644 return -EINVAL; 4645 } 4646 4647 switch (coex->direction) { 4648 case RTW89_MAC_AX_COEX_INNER: 4649 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4650 val = (val & ~BIT(2)) | BIT(1); 4651 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4652 break; 4653 case RTW89_MAC_AX_COEX_OUTPUT: 4654 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4655 val = val | BIT(1) | BIT(0); 4656 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4657 break; 4658 case RTW89_MAC_AX_COEX_INPUT: 4659 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4660 val = val & ~(BIT(2) | BIT(1)); 4661 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4662 break; 4663 default: 4664 return -EINVAL; 4665 } 4666 4667 return 0; 4668 } 4669 EXPORT_SYMBOL(rtw89_mac_coex_init); 4670 4671 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 4672 const struct rtw89_mac_ax_coex *coex) 4673 { 4674 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 4675 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 4676 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 4677 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 4678 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 4679 4680 switch (coex->pta_mode) { 4681 case RTW89_MAC_AX_COEX_RTK_MODE: 4682 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4683 MAC_AX_RTK_MODE); 4684 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 4685 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 4686 break; 4687 case RTW89_MAC_AX_COEX_CSR_MODE: 4688 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4689 MAC_AX_CSR_MODE); 4690 break; 4691 default: 4692 return -EINVAL; 4693 } 4694 4695 return 0; 4696 } 4697 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 4698 4699 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4700 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4701 { 4702 u32 val = 0, ret; 4703 4704 if (gnt_cfg->band[0].gnt_bt) 4705 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 4706 4707 if (gnt_cfg->band[0].gnt_bt_sw_en) 4708 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 4709 4710 if (gnt_cfg->band[0].gnt_wl) 4711 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 4712 4713 if (gnt_cfg->band[0].gnt_wl_sw_en) 4714 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 4715 4716 if (gnt_cfg->band[1].gnt_bt) 4717 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 4718 4719 if (gnt_cfg->band[1].gnt_bt_sw_en) 4720 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 4721 4722 if (gnt_cfg->band[1].gnt_wl) 4723 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 4724 4725 if (gnt_cfg->band[1].gnt_wl_sw_en) 4726 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 4727 4728 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 4729 if (ret) { 4730 rtw89_err(rtwdev, "Write LTE fail!\n"); 4731 return ret; 4732 } 4733 4734 return 0; 4735 } 4736 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 4737 4738 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 4739 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4740 { 4741 u32 val = 0; 4742 4743 if (gnt_cfg->band[0].gnt_bt) 4744 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 4745 B_AX_GNT_BT_TX_VAL; 4746 else 4747 val |= B_AX_WL_ACT_VAL; 4748 4749 if (gnt_cfg->band[0].gnt_bt_sw_en) 4750 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4751 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4752 4753 if (gnt_cfg->band[0].gnt_wl) 4754 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 4755 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4756 4757 if (gnt_cfg->band[0].gnt_wl_sw_en) 4758 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4759 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4760 4761 if (gnt_cfg->band[1].gnt_bt) 4762 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 4763 B_AX_GNT_BT_TX_VAL; 4764 else 4765 val |= B_AX_WL_ACT_VAL; 4766 4767 if (gnt_cfg->band[1].gnt_bt_sw_en) 4768 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4769 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4770 4771 if (gnt_cfg->band[1].gnt_wl) 4772 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 4773 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4774 4775 if (gnt_cfg->band[1].gnt_wl_sw_en) 4776 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4777 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4778 4779 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 4780 4781 return 0; 4782 } 4783 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 4784 4785 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 4786 { 4787 u32 reg; 4788 u16 val; 4789 int ret; 4790 4791 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 4792 if (ret) 4793 return ret; 4794 4795 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); 4796 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 4797 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 4798 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 4799 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 4800 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 4801 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 4802 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 4803 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 4804 B_AX_PLT_EN; 4805 rtw89_write16(rtwdev, reg, val); 4806 4807 return 0; 4808 } 4809 4810 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 4811 { 4812 u32 fw_sb; 4813 4814 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4815 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 4816 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 4817 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4818 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 4819 else 4820 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 4821 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 4822 val = B_AX_TOGGLE | 4823 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 4824 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 4825 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 4826 fsleep(1000); /* avoid BT FW loss information */ 4827 } 4828 4829 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 4830 { 4831 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4832 } 4833 4834 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4835 { 4836 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 4837 4838 val = wl ? val | BIT(2) : val & ~BIT(2); 4839 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 4840 4841 return 0; 4842 } 4843 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 4844 4845 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 4846 { 4847 struct rtw89_btc *btc = &rtwdev->btc; 4848 struct rtw89_btc_dm *dm = &btc->dm; 4849 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 4850 int i; 4851 4852 if (wl) 4853 return 0; 4854 4855 for (i = 0; i < RTW89_PHY_MAX; i++) { 4856 g[i].gnt_bt_sw_en = 1; 4857 g[i].gnt_bt = 1; 4858 g[i].gnt_wl_sw_en = 1; 4859 g[i].gnt_wl = 0; 4860 } 4861 4862 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 4863 } 4864 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 4865 4866 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 4867 { 4868 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 4869 4870 return FIELD_GET(B_AX_LTE_MUX_CTRL_PATH >> 24, val); 4871 } 4872 4873 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 4874 { 4875 u32 reg; 4876 u16 cnt; 4877 4878 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); 4879 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 4880 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 4881 4882 return cnt; 4883 } 4884 4885 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 4886 { 4887 u32 reg; 4888 u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 4889 B_AX_BFMEE_HE_NDPA_EN; 4890 4891 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 4892 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 4893 if (en) { 4894 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4895 rtw89_write32_set(rtwdev, reg, mask); 4896 } else { 4897 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4898 rtw89_write32_clr(rtwdev, reg, mask); 4899 } 4900 } 4901 4902 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 4903 { 4904 u32 reg; 4905 u32 val32; 4906 int ret; 4907 4908 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4909 if (ret) 4910 return ret; 4911 4912 /* AP mode set tx gid to 63 */ 4913 /* STA mode set tx gid to 0(default) */ 4914 reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); 4915 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 4916 4917 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 4918 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 4919 4920 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 4921 val32 = FIELD_PREP(B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, BFRP_RX_STANDBY_TIMER); 4922 val32 |= FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 4923 rtw89_write32(rtwdev, reg, val32); 4924 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 4925 4926 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4927 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 4928 B_AX_BFMEE_USE_NSTS | 4929 B_AX_BFMEE_CSI_GID_SEL | 4930 B_AX_BFMEE_CSI_FORCE_RETE_EN); 4931 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 4932 rtw89_write32(rtwdev, reg, 4933 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 4934 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 4935 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 4936 4937 reg = rtw89_mac_reg_by_idx(R_AX_CSIRPT_OPTION, mac_idx); 4938 rtw89_write32_set(rtwdev, reg, 4939 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 4940 4941 return 0; 4942 } 4943 4944 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 4945 struct ieee80211_vif *vif, 4946 struct ieee80211_sta *sta) 4947 { 4948 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4949 u8 mac_idx = rtwvif->mac_idx; 4950 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 4951 u8 port_sel = rtwvif->port; 4952 u8 sound_dim = 3, t; 4953 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 4954 u32 reg; 4955 u16 val; 4956 int ret; 4957 4958 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4959 if (ret) 4960 return ret; 4961 4962 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4963 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 4964 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 4965 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 4966 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 4967 phy_cap[5]); 4968 sound_dim = min(sound_dim, t); 4969 } 4970 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4971 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 4972 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 4973 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 4974 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 4975 sta->deflink.vht_cap.cap); 4976 sound_dim = min(sound_dim, t); 4977 } 4978 nc = min(nc, sound_dim); 4979 nr = min(nr, sound_dim); 4980 4981 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4982 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 4983 4984 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 4985 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 4986 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 4987 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 4988 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 4989 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 4990 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 4991 4992 if (port_sel == 0) 4993 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4994 else 4995 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 4996 4997 rtw89_write16(rtwdev, reg, val); 4998 4999 return 0; 5000 } 5001 5002 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 5003 struct ieee80211_vif *vif, 5004 struct ieee80211_sta *sta) 5005 { 5006 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5007 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5008 u32 reg; 5009 u8 mac_idx = rtwvif->mac_idx; 5010 int ret; 5011 5012 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5013 if (ret) 5014 return ret; 5015 5016 if (sta->deflink.he_cap.has_he) { 5017 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5018 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5019 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5020 } 5021 if (sta->deflink.vht_cap.vht_supported) { 5022 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5023 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5024 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5025 } 5026 if (sta->deflink.ht_cap.ht_supported) { 5027 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5028 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5029 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5030 } 5031 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5032 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5033 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5034 rtw89_write32(rtwdev, 5035 rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5036 rrsc); 5037 5038 return 0; 5039 } 5040 5041 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5042 struct ieee80211_sta *sta) 5043 { 5044 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5045 5046 if (rtw89_sta_has_beamformer_cap(sta)) { 5047 rtw89_debug(rtwdev, RTW89_DBG_BF, 5048 "initialize bfee for new association\n"); 5049 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 5050 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 5051 rtw89_mac_csi_rrsc(rtwdev, vif, sta); 5052 } 5053 } 5054 5055 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5056 struct ieee80211_sta *sta) 5057 { 5058 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5059 5060 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 5061 } 5062 5063 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5064 struct ieee80211_bss_conf *conf) 5065 { 5066 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5067 u8 mac_idx = rtwvif->mac_idx; 5068 __le32 *p; 5069 5070 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 5071 5072 p = (__le32 *)conf->mu_group.membership; 5073 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), 5074 le32_to_cpu(p[0])); 5075 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), 5076 le32_to_cpu(p[1])); 5077 5078 p = (__le32 *)conf->mu_group.position; 5079 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), 5080 le32_to_cpu(p[0])); 5081 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), 5082 le32_to_cpu(p[1])); 5083 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), 5084 le32_to_cpu(p[2])); 5085 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), 5086 le32_to_cpu(p[3])); 5087 } 5088 5089 struct rtw89_mac_bf_monitor_iter_data { 5090 struct rtw89_dev *rtwdev; 5091 struct ieee80211_sta *down_sta; 5092 int count; 5093 }; 5094 5095 static 5096 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 5097 { 5098 struct rtw89_mac_bf_monitor_iter_data *iter_data = 5099 (struct rtw89_mac_bf_monitor_iter_data *)data; 5100 struct ieee80211_sta *down_sta = iter_data->down_sta; 5101 int *count = &iter_data->count; 5102 5103 if (down_sta == sta) 5104 return; 5105 5106 if (rtw89_sta_has_beamformer_cap(sta)) 5107 (*count)++; 5108 } 5109 5110 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 5111 struct ieee80211_sta *sta, bool disconnect) 5112 { 5113 struct rtw89_mac_bf_monitor_iter_data data; 5114 5115 data.rtwdev = rtwdev; 5116 data.down_sta = disconnect ? sta : NULL; 5117 data.count = 0; 5118 ieee80211_iterate_stations_atomic(rtwdev->hw, 5119 rtw89_mac_bf_monitor_calc_iter, 5120 &data); 5121 5122 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 5123 if (data.count) 5124 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5125 else 5126 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5127 } 5128 5129 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 5130 { 5131 struct rtw89_traffic_stats *stats = &rtwdev->stats; 5132 struct rtw89_vif *rtwvif; 5133 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 5134 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5135 5136 if (en == old) 5137 return; 5138 5139 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5140 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 5141 } 5142 5143 static int 5144 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5145 u32 tx_time) 5146 { 5147 #define MAC_AX_DFLT_TX_TIME 5280 5148 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5149 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 5150 u32 reg; 5151 int ret = 0; 5152 5153 if (rtwsta->cctl_tx_time) { 5154 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 5155 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5156 } else { 5157 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5158 if (ret) { 5159 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 5160 return ret; 5161 } 5162 5163 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5164 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 5165 max_tx_time >> 5); 5166 } 5167 5168 return ret; 5169 } 5170 5171 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5172 bool resume, u32 tx_time) 5173 { 5174 int ret = 0; 5175 5176 if (!resume) { 5177 rtwsta->cctl_tx_time = true; 5178 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5179 } else { 5180 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5181 rtwsta->cctl_tx_time = false; 5182 } 5183 5184 return ret; 5185 } 5186 5187 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5188 u32 *tx_time) 5189 { 5190 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5191 u32 reg; 5192 int ret = 0; 5193 5194 if (rtwsta->cctl_tx_time) { 5195 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 5196 } else { 5197 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5198 if (ret) { 5199 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 5200 return ret; 5201 } 5202 5203 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5204 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 5205 } 5206 5207 return ret; 5208 } 5209 5210 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 5211 struct rtw89_sta *rtwsta, 5212 bool resume, u8 tx_retry) 5213 { 5214 int ret = 0; 5215 5216 rtwsta->data_tx_cnt_lmt = tx_retry; 5217 5218 if (!resume) { 5219 rtwsta->cctl_tx_retry_limit = true; 5220 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5221 } else { 5222 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5223 rtwsta->cctl_tx_retry_limit = false; 5224 } 5225 5226 return ret; 5227 } 5228 5229 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 5230 struct rtw89_sta *rtwsta, u8 *tx_retry) 5231 { 5232 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5233 u32 reg; 5234 int ret = 0; 5235 5236 if (rtwsta->cctl_tx_retry_limit) { 5237 *tx_retry = rtwsta->data_tx_cnt_lmt; 5238 } else { 5239 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5240 if (ret) { 5241 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 5242 return ret; 5243 } 5244 5245 reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); 5246 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 5247 } 5248 5249 return ret; 5250 } 5251 5252 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 5253 struct rtw89_vif *rtwvif, bool en) 5254 { 5255 u8 mac_idx = rtwvif->mac_idx; 5256 u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; 5257 u32 reg; 5258 u32 ret; 5259 5260 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5261 if (ret) 5262 return ret; 5263 5264 reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); 5265 if (en) 5266 rtw89_write16_set(rtwdev, reg, set); 5267 else 5268 rtw89_write16_clr(rtwdev, reg, set); 5269 5270 return 0; 5271 } 5272 5273 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 5274 { 5275 u32 val32; 5276 int ret; 5277 5278 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5279 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 5280 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 5281 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 5282 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5283 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5284 5285 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5286 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5287 if (ret) { 5288 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 5289 offset, val, mask); 5290 return ret; 5291 } 5292 5293 return 0; 5294 } 5295 EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 5296 5297 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 5298 { 5299 u32 val32; 5300 int ret; 5301 5302 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5303 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 5304 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 5305 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 5306 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5307 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5308 5309 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5310 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5311 if (ret) { 5312 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 5313 return ret; 5314 } 5315 5316 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 5317 5318 return 0; 5319 } 5320 EXPORT_SYMBOL(rtw89_mac_read_xtal_si); 5321 5322 static 5323 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 5324 { 5325 static const enum rtw89_pkt_drop_sel sels[] = { 5326 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5327 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5328 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5329 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5330 }; 5331 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5332 struct rtw89_pkt_drop_params params = {0}; 5333 int i; 5334 5335 params.mac_band = RTW89_MAC_0; 5336 params.macid = rtwsta->mac_id; 5337 params.port = rtwvif->port; 5338 params.mbssid = 0; 5339 params.tf_trs = rtwvif->trigger; 5340 5341 for (i = 0; i < ARRAY_SIZE(sels); i++) { 5342 params.sel = sels[i]; 5343 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5344 } 5345 } 5346 5347 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 5348 { 5349 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 5350 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5351 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 5352 struct rtw89_vif *target = data; 5353 5354 if (rtwvif != target) 5355 return; 5356 5357 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 5358 } 5359 5360 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 5361 { 5362 ieee80211_iterate_stations_atomic(rtwdev->hw, 5363 rtw89_mac_pkt_drop_vif_iter, 5364 rtwvif); 5365 } 5366 5367 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 5368 enum rtw89_mac_idx band) 5369 { 5370 struct rtw89_pkt_drop_params params = {0}; 5371 bool empty; 5372 int i, ret = 0, try_cnt = 3; 5373 5374 params.mac_band = band; 5375 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 5376 5377 for (i = 0; i < try_cnt; i++) { 5378 ret = read_poll_timeout(mac_is_txq_empty, empty, empty, 50, 5379 50000, false, rtwdev); 5380 if (ret) 5381 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5382 else 5383 return 0; 5384 } 5385 return ret; 5386 } 5387