1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "util.h" 15 16 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 17 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 18 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 19 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 20 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 21 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 22 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 26 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 29 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 31 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 35 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 36 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 37 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 38 }; 39 40 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 41 u32 val, enum rtw89_mac_mem_sel sel) 42 { 43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44 u32 addr = mac->mem_base_addrs[sel] + offset; 45 46 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 47 rtw89_write32(rtwdev, mac->indir_access_addr, val); 48 } 49 50 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 51 enum rtw89_mac_mem_sel sel) 52 { 53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 54 u32 addr = mac->mem_base_addrs[sel] + offset; 55 56 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 57 return rtw89_read32(rtwdev, mac->indir_access_addr); 58 } 59 60 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 61 enum rtw89_mac_hwmod_sel sel) 62 { 63 u32 val, r_val; 64 65 if (sel == RTW89_DMAC_SEL) { 66 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 67 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 69 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 70 val = B_AX_CMAC_EN; 71 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 72 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 73 val = B_AX_CMAC1_FEN; 74 } else { 75 return -EINVAL; 76 } 77 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 78 (val & r_val) != val) 79 return -EFAULT; 80 81 return 0; 82 } 83 84 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 85 { 86 u8 lte_ctrl; 87 int ret; 88 89 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 90 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 91 if (ret) 92 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 93 94 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 95 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 96 97 return ret; 98 } 99 100 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 101 { 102 u8 lte_ctrl; 103 int ret; 104 105 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 106 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 107 if (ret) 108 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 109 110 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 111 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 112 113 return ret; 114 } 115 116 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 117 { 118 u32 ctrl_reg, data_reg, ctrl_data; 119 u32 val; 120 int ret; 121 122 switch (ctrl->type) { 123 case DLE_CTRL_TYPE_WDE: 124 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 125 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 126 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 127 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 128 B_AX_WDE_DFI_ACTIVE; 129 break; 130 case DLE_CTRL_TYPE_PLE: 131 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 132 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 133 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 134 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 135 B_AX_PLE_DFI_ACTIVE; 136 break; 137 default: 138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 139 return -EINVAL; 140 } 141 142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 143 144 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 145 1, 1000, false, rtwdev, ctrl_reg); 146 if (ret) { 147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 148 ctrl_reg, ctrl_data); 149 return ret; 150 } 151 152 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 153 return 0; 154 } 155 156 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 157 struct rtw89_mac_dle_dfi_quota *quota) 158 { 159 struct rtw89_mac_dle_dfi_ctrl ctrl; 160 int ret; 161 162 ctrl.type = quota->dle_type; 163 ctrl.target = DLE_DFI_TYPE_QUOTA; 164 ctrl.addr = quota->qtaid; 165 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 166 if (ret) { 167 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 168 return ret; 169 } 170 171 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 172 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 173 return 0; 174 } 175 176 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 177 struct rtw89_mac_dle_dfi_qempty *qempty) 178 { 179 struct rtw89_mac_dle_dfi_ctrl ctrl; 180 u32 ret; 181 182 ctrl.type = qempty->dle_type; 183 ctrl.target = DLE_DFI_TYPE_QEMPTY; 184 ctrl.addr = qempty->grpsel; 185 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 186 if (ret) { 187 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 188 return ret; 189 } 190 191 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 192 return 0; 193 } 194 195 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 196 { 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 209 } 210 211 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 212 { 213 struct rtw89_mac_dle_dfi_qempty qempty; 214 struct rtw89_mac_dle_dfi_quota quota; 215 struct rtw89_mac_dle_dfi_ctrl ctrl; 216 u32 val, not_empty, i; 217 int ret; 218 219 qempty.dle_type = DLE_CTRL_TYPE_PLE; 220 qempty.grpsel = 0; 221 qempty.qempty = ~(u32)0; 222 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 223 if (ret) 224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 225 else 226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 227 228 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 229 if (!(not_empty & BIT(0))) 230 continue; 231 ctrl.type = DLE_CTRL_TYPE_PLE; 232 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 233 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 234 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 235 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 236 if (ret) 237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 238 else 239 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 240 u32_get_bits(ctrl.out_data, 241 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 242 } 243 244 quota.dle_type = DLE_CTRL_TYPE_PLE; 245 quota.qtaid = 6; 246 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 247 if (ret) 248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 249 else 250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 251 quota.rsv_pgnum, quota.use_pgnum); 252 253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 255 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 257 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 258 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 259 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 260 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 261 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 262 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 263 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 264 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 265 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 266 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 267 268 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 269 quota.dle_type = DLE_CTRL_TYPE_PLE; 270 quota.qtaid = 7; 271 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 272 if (ret) 273 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 274 else 275 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 276 quota.rsv_pgnum, quota.use_pgnum); 277 278 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 279 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 280 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 282 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 283 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 284 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 285 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 286 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 287 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 288 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 289 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 290 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 291 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 292 } 293 294 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 295 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 298 299 dump_err_status_dispatcher_ax(rtwdev); 300 } 301 302 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 303 enum mac_ax_err_info err) 304 { 305 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 306 u32 dbg, event; 307 308 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 309 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 310 311 switch (event) { 312 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 313 rtw89_info(rtwdev, "quota lost!\n"); 314 mac->dump_qta_lost(rtwdev); 315 break; 316 default: 317 break; 318 } 319 } 320 321 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 322 { 323 const struct rtw89_chip_info *chip = rtwdev->chip; 324 u32 dmac_err; 325 int i, ret; 326 327 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 328 if (ret) { 329 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 330 return; 331 } 332 333 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 334 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 335 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 337 338 if (dmac_err) { 339 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 341 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 343 if (chip->chip_id == RTL8852C) { 344 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 345 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 346 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 348 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 352 } 353 } 354 355 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 356 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 357 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 360 if (chip->chip_id == RTL8852C) 361 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 363 else 364 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 365 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 366 } 367 368 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 369 if (chip->chip_id == RTL8852C) { 370 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 371 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 372 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 374 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 376 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 378 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 380 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 382 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 384 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 386 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 388 389 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 390 B_AX_DBG_SEL0, 0x8B); 391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392 B_AX_DBG_SEL1, 0x8B); 393 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 394 B_AX_SEL_0XC0_MASK, 1); 395 for (i = 0; i < 0x10; i++) { 396 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 397 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 398 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 399 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 400 } 401 } else if (chip->chip_id == RTL8922A) { 402 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 403 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 406 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 407 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 408 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 409 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 410 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 411 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 412 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 413 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 414 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 415 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 416 } else { 417 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 419 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 421 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 423 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 425 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 427 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 429 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 430 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 431 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 432 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 433 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 435 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 437 } 438 } 439 440 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 441 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 442 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 445 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 449 } 450 451 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 452 if (chip->chip_id == RTL8922A) { 453 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 454 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 455 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 456 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 457 } else { 458 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 459 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 462 } 463 } 464 465 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 466 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 468 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 470 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 471 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 472 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 474 } 475 476 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 477 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 478 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 479 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 486 } else { 487 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 491 } 492 } 493 494 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 495 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 501 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 503 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 509 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 510 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 515 if (chip->chip_id == RTL8922A) { 516 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 517 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 520 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 521 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 522 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 524 } else { 525 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 526 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 527 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 529 if (chip->chip_id == RTL8852C) { 530 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 531 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 532 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 533 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 534 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 535 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 536 } else { 537 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 538 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 543 } 544 } 545 } 546 547 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 548 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 549 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 552 } 553 554 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 555 if (chip->chip_id == RTL8922A) { 556 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 557 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 558 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 559 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 560 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 561 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 562 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 563 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 564 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 565 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 566 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 567 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 568 } else { 569 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 570 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 573 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 574 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 577 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 578 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 581 } 582 } 583 584 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 585 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 586 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 587 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 590 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 591 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 594 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 595 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 598 } else { 599 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 600 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 601 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 602 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 605 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 606 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 609 } 610 if (chip->chip_id == RTL8922A) { 611 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 612 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 615 } 616 } 617 618 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 619 if (chip->chip_id == RTL8922A) { 620 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 621 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 624 } else if (chip->chip_id == RTL8852C) { 625 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 626 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 629 } 630 } 631 632 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 633 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 634 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 635 RTW89_MAC_MEM_AXIDMA)); 636 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 637 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 638 RTW89_MAC_MEM_AXIDMA)); 639 } 640 641 if (dmac_err & B_BE_MLO_ERR_INT) { 642 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 643 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 644 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 646 } 647 648 if (dmac_err & B_BE_PLRLS_ERR_INT) { 649 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 650 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 653 } 654 } 655 656 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 657 u8 band) 658 { 659 const struct rtw89_chip_info *chip = rtwdev->chip; 660 u32 offset = 0; 661 u32 cmac_err; 662 int ret; 663 664 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 665 if (ret) { 666 if (band) 667 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 668 else 669 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 670 return; 671 } 672 673 if (band) 674 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 675 676 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 677 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 678 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 679 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 680 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 681 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 682 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 683 684 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 685 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 686 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 689 } 690 691 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 692 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 693 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 694 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 695 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 696 } 697 698 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 699 if (chip->chip_id == RTL8852C) { 700 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 701 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 704 } else { 705 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 706 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 707 } 708 } 709 710 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 711 if (chip->chip_id == RTL8852C) { 712 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 713 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 716 } else { 717 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 718 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 719 } 720 } 721 722 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 723 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 724 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 725 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 726 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 727 } 728 729 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 730 if (chip->chip_id == RTL8852C) { 731 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 732 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 735 } else { 736 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 737 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 738 } 739 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 740 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 741 } 742 743 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 744 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 745 } 746 747 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 748 enum mac_ax_err_info err) 749 { 750 if (err != MAC_AX_ERR_L1_ERR_DMAC && 751 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 752 err != MAC_AX_ERR_L0_ERR_CMAC0 && 753 err != MAC_AX_ERR_L0_ERR_CMAC1 && 754 err != MAC_AX_ERR_RXI300) 755 return; 756 757 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 758 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 759 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 762 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 763 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 764 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 766 767 rtw89_mac_dump_dmac_err_status(rtwdev); 768 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 769 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 770 771 rtwdev->hci.ops->dump_err_status(rtwdev); 772 773 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 774 rtw89_mac_dump_l0_to_l1(rtwdev, err); 775 776 rtw89_info(rtwdev, "<---\n"); 777 } 778 779 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 780 { 781 struct rtw89_ser *ser = &rtwdev->ser; 782 u32 dmac_err, imr, isr; 783 int ret; 784 785 if (rtwdev->chip->chip_id == RTL8852C) { 786 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 787 if (ret) 788 return true; 789 790 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 791 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 792 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 793 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 794 795 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 796 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 797 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 798 return true; 799 } 800 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 801 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 802 return true; 803 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 804 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 805 return true; 806 } 807 } 808 809 return false; 810 } 811 812 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 813 { 814 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 815 u32 err, err_scnr; 816 int ret; 817 818 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 819 false, rtwdev, R_AX_HALT_C2H_CTRL); 820 if (ret) { 821 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 822 return ret; 823 } 824 825 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 826 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 827 828 err_scnr = RTW89_ERROR_SCENARIO(err); 829 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 830 err = MAC_AX_ERR_CPU_EXCEPTION; 831 else if (err_scnr == RTW89_WCPU_ASSERTION) 832 err = MAC_AX_ERR_ASSERTION; 833 else if (err_scnr == RTW89_RXI300_ERROR) 834 err = MAC_AX_ERR_RXI300; 835 836 if (rtw89_mac_suppress_log(rtwdev, err)) 837 return err; 838 839 rtw89_fw_st_dbg_dump(rtwdev); 840 mac->dump_err_status(rtwdev, err); 841 842 return err; 843 } 844 EXPORT_SYMBOL(rtw89_mac_get_err_status); 845 846 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 847 { 848 struct rtw89_ser *ser = &rtwdev->ser; 849 u32 halt; 850 int ret = 0; 851 852 if (err > MAC_AX_SET_ERR_MAX) { 853 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 854 return -EINVAL; 855 } 856 857 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 858 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 859 if (ret) { 860 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 861 return -EFAULT; 862 } 863 864 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 865 866 if (ser->prehandle_l1 && 867 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 868 return 0; 869 870 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 871 872 return 0; 873 } 874 EXPORT_SYMBOL(rtw89_mac_set_err_status); 875 876 static int hfc_reset_param(struct rtw89_dev *rtwdev) 877 { 878 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 879 struct rtw89_hfc_param_ini param_ini = {NULL}; 880 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 881 882 switch (rtwdev->hci.type) { 883 case RTW89_HCI_TYPE_PCIE: 884 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 885 param->en = 0; 886 break; 887 default: 888 return -EINVAL; 889 } 890 891 if (param_ini.pub_cfg) 892 param->pub_cfg = *param_ini.pub_cfg; 893 894 if (param_ini.prec_cfg) 895 param->prec_cfg = *param_ini.prec_cfg; 896 897 if (param_ini.ch_cfg) 898 param->ch_cfg = param_ini.ch_cfg; 899 900 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 901 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 902 param->mode = param_ini.mode; 903 904 return 0; 905 } 906 907 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 908 { 909 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 910 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 911 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 912 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 913 914 if (ch >= RTW89_DMA_CH_NUM) 915 return -EINVAL; 916 917 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 918 ch_cfg[ch].max > pub_cfg->pub_max) 919 return -EINVAL; 920 if (ch_cfg[ch].grp >= grp_num) 921 return -EINVAL; 922 923 return 0; 924 } 925 926 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 927 { 928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 929 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 930 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 931 932 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 933 if (rtwdev->chip->chip_id == RTL8852A) 934 return 0; 935 else 936 return -EFAULT; 937 } 938 939 return 0; 940 } 941 942 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 943 { 944 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 945 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 946 947 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 948 return -EFAULT; 949 950 return 0; 951 } 952 953 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 954 { 955 const struct rtw89_chip_info *chip = rtwdev->chip; 956 const struct rtw89_page_regs *regs = chip->page_regs; 957 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 958 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 959 int ret = 0; 960 u32 val = 0; 961 962 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 963 if (ret) 964 return ret; 965 966 ret = hfc_ch_cfg_chk(rtwdev, ch); 967 if (ret) 968 return ret; 969 970 if (ch > RTW89_DMA_B1HI) 971 return -EINVAL; 972 973 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 974 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 975 (cfg[ch].grp ? B_AX_GRP : 0); 976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 977 978 return 0; 979 } 980 981 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 982 { 983 const struct rtw89_chip_info *chip = rtwdev->chip; 984 const struct rtw89_page_regs *regs = chip->page_regs; 985 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 986 struct rtw89_hfc_ch_info *info = param->ch_info; 987 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 988 u32 val; 989 u32 ret; 990 991 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 992 if (ret) 993 return ret; 994 995 if (ch > RTW89_DMA_H2C) 996 return -EINVAL; 997 998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 999 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1000 if (ch < RTW89_DMA_H2C) 1001 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1002 else 1003 info[ch].used = cfg[ch].min - info[ch].aval; 1004 1005 return 0; 1006 } 1007 1008 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1009 { 1010 const struct rtw89_chip_info *chip = rtwdev->chip; 1011 const struct rtw89_page_regs *regs = chip->page_regs; 1012 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1013 u32 val; 1014 int ret; 1015 1016 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1017 if (ret) 1018 return ret; 1019 1020 ret = hfc_pub_cfg_chk(rtwdev); 1021 if (ret) 1022 return ret; 1023 1024 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1025 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1027 1028 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1030 1031 return 0; 1032 } 1033 1034 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1035 { 1036 const struct rtw89_chip_info *chip = rtwdev->chip; 1037 const struct rtw89_page_regs *regs = chip->page_regs; 1038 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1039 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1040 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1041 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1042 u32 val; 1043 1044 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1045 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1046 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1047 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1048 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1049 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1050 info->pub_aval = 1051 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1052 B_AX_PUB_AVAL_PG_MASK); 1053 info->wp_aval = 1054 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1055 B_AX_WP_AVAL_PG_MASK); 1056 1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1058 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1059 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1060 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1061 prec_cfg->ch011_full_cond = 1062 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1063 prec_cfg->h2c_full_cond = 1064 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1065 prec_cfg->wp_ch07_full_cond = 1066 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1067 prec_cfg->wp_ch811_full_cond = 1068 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1069 1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1071 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1072 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1073 1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1075 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1076 1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1078 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1079 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1080 1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1082 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1083 1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1085 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1086 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1087 } 1088 1089 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1090 { 1091 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1092 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1093 int ret; 1094 1095 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1096 if (ret) 1097 return ret; 1098 1099 mac->hfc_get_mix_info(rtwdev); 1100 1101 ret = hfc_pub_info_chk(rtwdev); 1102 if (param->en && ret) 1103 return ret; 1104 1105 return 0; 1106 } 1107 1108 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1109 { 1110 const struct rtw89_chip_info *chip = rtwdev->chip; 1111 const struct rtw89_page_regs *regs = chip->page_regs; 1112 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1113 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1114 u32 val; 1115 1116 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1118 1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1120 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1121 prec_cfg->h2c_full_cond); 1122 } 1123 1124 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1125 { 1126 const struct rtw89_chip_info *chip = rtwdev->chip; 1127 const struct rtw89_page_regs *regs = chip->page_regs; 1128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1129 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1130 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1131 u32 val; 1132 1133 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1134 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1136 1137 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1139 1140 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1141 B_AX_PREC_PAGE_WP_CH07_MASK) | 1142 u32_encode_bits(prec_cfg->wp_ch811_prec, 1143 B_AX_PREC_PAGE_WP_CH811_MASK); 1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1145 1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1147 param->mode, B_AX_HCI_FC_MODE_MASK); 1148 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1149 B_AX_HCI_FC_WD_FULL_COND_MASK); 1150 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1151 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1152 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1153 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1154 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1155 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1157 } 1158 1159 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1160 { 1161 const struct rtw89_chip_info *chip = rtwdev->chip; 1162 const struct rtw89_page_regs *regs = chip->page_regs; 1163 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1164 u32 val; 1165 1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1167 param->en = en; 1168 param->h2c_en = h2c_en; 1169 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1170 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1171 (val & ~B_AX_HCI_FC_CH12_EN); 1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1173 } 1174 1175 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1176 { 1177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1178 const struct rtw89_chip_info *chip = rtwdev->chip; 1179 u32 dma_ch_mask = chip->dma_ch_mask; 1180 u8 ch; 1181 u32 ret = 0; 1182 1183 if (reset) 1184 ret = hfc_reset_param(rtwdev); 1185 if (ret) 1186 return ret; 1187 1188 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1189 if (ret) 1190 return ret; 1191 1192 mac->hfc_func_en(rtwdev, false, false); 1193 1194 if (!en && h2c_en) { 1195 mac->hfc_h2c_cfg(rtwdev); 1196 mac->hfc_func_en(rtwdev, en, h2c_en); 1197 return ret; 1198 } 1199 1200 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1201 if (dma_ch_mask & BIT(ch)) 1202 continue; 1203 ret = hfc_ch_ctrl(rtwdev, ch); 1204 if (ret) 1205 return ret; 1206 } 1207 1208 ret = hfc_pub_ctrl(rtwdev); 1209 if (ret) 1210 return ret; 1211 1212 mac->hfc_mix_cfg(rtwdev); 1213 if (en || h2c_en) { 1214 mac->hfc_func_en(rtwdev, en, h2c_en); 1215 udelay(10); 1216 } 1217 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1218 if (dma_ch_mask & BIT(ch)) 1219 continue; 1220 ret = hfc_upd_ch_info(rtwdev, ch); 1221 if (ret) 1222 return ret; 1223 } 1224 ret = hfc_upd_mix_info(rtwdev); 1225 1226 return ret; 1227 } 1228 1229 #define PWR_POLL_CNT 2000 1230 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1231 const struct rtw89_pwr_cfg *cfg) 1232 { 1233 u8 val = 0; 1234 int ret; 1235 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1236 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1237 1238 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1239 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1240 1241 if (!ret) 1242 return 0; 1243 1244 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1245 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1247 1248 return -EBUSY; 1249 } 1250 1251 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1252 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1253 { 1254 const struct rtw89_pwr_cfg *cur_cfg; 1255 u32 addr; 1256 u8 val; 1257 1258 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1259 if (!(cur_cfg->intf_msk & intf_msk) || 1260 !(cur_cfg->cv_msk & cv_msk)) 1261 continue; 1262 1263 switch (cur_cfg->cmd) { 1264 case PWR_CMD_WRITE: 1265 addr = cur_cfg->addr; 1266 1267 if (cur_cfg->base == PWR_BASE_SDIO) 1268 addr |= SDIO_LOCAL_BASE_ADDR; 1269 1270 val = rtw89_read8(rtwdev, addr); 1271 val &= ~(cur_cfg->msk); 1272 val |= (cur_cfg->val & cur_cfg->msk); 1273 1274 rtw89_write8(rtwdev, addr, val); 1275 break; 1276 case PWR_CMD_POLL: 1277 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1278 return -EBUSY; 1279 break; 1280 case PWR_CMD_DELAY: 1281 if (cur_cfg->val == PWR_DELAY_US) 1282 udelay(cur_cfg->addr); 1283 else 1284 fsleep(cur_cfg->addr * 1000); 1285 break; 1286 default: 1287 return -EINVAL; 1288 } 1289 } 1290 1291 return 0; 1292 } 1293 1294 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1295 const struct rtw89_pwr_cfg * const *cfg_seq) 1296 { 1297 int ret; 1298 1299 for (; *cfg_seq; cfg_seq++) { 1300 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1301 PWR_INTF_MSK_PCIE, *cfg_seq); 1302 if (ret) 1303 return -EBUSY; 1304 } 1305 1306 return 0; 1307 } 1308 1309 static enum rtw89_rpwm_req_pwr_state 1310 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1311 { 1312 enum rtw89_rpwm_req_pwr_state state; 1313 1314 switch (rtwdev->ps_mode) { 1315 case RTW89_PS_MODE_RFOFF: 1316 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1317 break; 1318 case RTW89_PS_MODE_CLK_GATED: 1319 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1320 break; 1321 case RTW89_PS_MODE_PWR_GATED: 1322 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1323 break; 1324 default: 1325 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1326 break; 1327 } 1328 return state; 1329 } 1330 1331 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1332 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1333 bool notify_wake) 1334 { 1335 u16 request; 1336 1337 spin_lock_bh(&rtwdev->rpwm_lock); 1338 1339 request = rtw89_read16(rtwdev, R_AX_RPWM); 1340 request ^= request | PS_RPWM_TOGGLE; 1341 request |= req_pwr_state; 1342 1343 if (notify_wake) { 1344 request |= PS_RPWM_NOTIFY_WAKE; 1345 } else { 1346 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1347 RPWM_SEQ_NUM_MAX; 1348 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1349 rtwdev->mac.rpwm_seq_num); 1350 1351 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1352 request |= PS_RPWM_ACK; 1353 } 1354 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1355 1356 spin_unlock_bh(&rtwdev->rpwm_lock); 1357 } 1358 1359 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1360 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1361 { 1362 bool request_deep_mode; 1363 bool in_deep_mode; 1364 u8 rpwm_req_num; 1365 u8 cpwm_rsp_seq; 1366 u8 cpwm_seq; 1367 u8 cpwm_status; 1368 1369 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1370 request_deep_mode = true; 1371 else 1372 request_deep_mode = false; 1373 1374 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1375 in_deep_mode = true; 1376 else 1377 in_deep_mode = false; 1378 1379 if (request_deep_mode != in_deep_mode) 1380 return -EPERM; 1381 1382 if (request_deep_mode) 1383 return 0; 1384 1385 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1386 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1387 PS_CPWM_RSP_SEQ_NUM); 1388 1389 if (rpwm_req_num != cpwm_rsp_seq) 1390 return -EPERM; 1391 1392 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1393 CPWM_SEQ_NUM_MAX; 1394 1395 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1396 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1397 return -EPERM; 1398 1399 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1400 if (cpwm_status != req_pwr_state) 1401 return -EPERM; 1402 1403 return 0; 1404 } 1405 1406 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1407 { 1408 enum rtw89_rpwm_req_pwr_state state; 1409 unsigned long delay = enter ? 10 : 150; 1410 int ret; 1411 int i; 1412 1413 if (enter) 1414 state = rtw89_mac_get_req_pwr_state(rtwdev); 1415 else 1416 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1417 1418 for (i = 0; i < RPWM_TRY_CNT; i++) { 1419 rtw89_mac_send_rpwm(rtwdev, state, false); 1420 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1421 !ret, delay, 15000, false, 1422 rtwdev, state); 1423 if (!ret) 1424 break; 1425 1426 if (i == RPWM_TRY_CNT - 1) 1427 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1428 enter ? "entering" : "leaving"); 1429 else 1430 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1431 "%d time firmware failed to ack for %s ps mode\n", 1432 i + 1, enter ? "entering" : "leaving"); 1433 } 1434 } 1435 1436 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1437 { 1438 enum rtw89_rpwm_req_pwr_state state; 1439 1440 state = rtw89_mac_get_req_pwr_state(rtwdev); 1441 rtw89_mac_send_rpwm(rtwdev, state, true); 1442 } 1443 1444 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1445 { 1446 #define PWR_ACT 1 1447 const struct rtw89_chip_info *chip = rtwdev->chip; 1448 const struct rtw89_pwr_cfg * const *cfg_seq; 1449 int (*cfg_func)(struct rtw89_dev *rtwdev); 1450 int ret; 1451 u8 val; 1452 1453 if (on) { 1454 cfg_seq = chip->pwr_on_seq; 1455 cfg_func = chip->ops->pwr_on_func; 1456 } else { 1457 cfg_seq = chip->pwr_off_seq; 1458 cfg_func = chip->ops->pwr_off_func; 1459 } 1460 1461 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1462 __rtw89_leave_ps_mode(rtwdev); 1463 1464 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1465 if (on && val == PWR_ACT) { 1466 rtw89_err(rtwdev, "MAC has already powered on\n"); 1467 return -EBUSY; 1468 } 1469 1470 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1471 if (ret) 1472 return ret; 1473 1474 if (on) { 1475 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1476 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1477 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1478 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1479 } else { 1480 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1481 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1482 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1483 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1484 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1485 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1486 rtw89_set_entity_state(rtwdev, false); 1487 } 1488 1489 return 0; 1490 #undef PWR_ACT 1491 } 1492 1493 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1494 { 1495 rtw89_mac_power_switch(rtwdev, false); 1496 } 1497 1498 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1499 { 1500 u32 func_en = 0; 1501 u32 ck_en = 0; 1502 u32 c1pc_en = 0; 1503 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1504 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1505 1506 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1507 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1508 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1509 B_AX_CMAC_CRPRT; 1510 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1511 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1512 B_AX_RMAC_CKEN; 1513 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1514 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1515 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1516 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1517 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1518 1519 if (en) { 1520 if (mac_idx == RTW89_MAC_1) { 1521 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1522 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1523 B_AX_R_SYM_ISO_CMAC12PP); 1524 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1525 B_AX_CMAC1_FEN); 1526 } 1527 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1528 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1529 } else { 1530 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1531 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1532 if (mac_idx == RTW89_MAC_1) { 1533 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1534 B_AX_CMAC1_FEN); 1535 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1536 B_AX_R_SYM_ISO_CMAC12PP); 1537 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1538 } 1539 } 1540 1541 return 0; 1542 } 1543 1544 static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1545 { 1546 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1547 u32 val32; 1548 1549 if (chip_id == RTL8852C) 1550 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1551 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1552 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1553 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1554 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1555 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1556 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1557 else 1558 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1559 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1560 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1561 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1562 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1563 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1564 B_AX_DMAC_CRPRT); 1565 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1566 1567 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1568 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1569 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1570 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1571 if (chip_id == RTL8852BT) 1572 val32 |= B_AX_AXIDMA_CLK_EN; 1573 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1574 1575 return 0; 1576 } 1577 1578 static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1579 { 1580 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1581 1582 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 1583 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1584 B_AX_OCP_L1_MASK); 1585 1586 return 0; 1587 } 1588 1589 static int sys_init_ax(struct rtw89_dev *rtwdev) 1590 { 1591 int ret; 1592 1593 ret = dmac_func_en_ax(rtwdev); 1594 if (ret) 1595 return ret; 1596 1597 ret = cmac_func_en_ax(rtwdev, 0, true); 1598 if (ret) 1599 return ret; 1600 1601 ret = chip_func_en_ax(rtwdev); 1602 if (ret) 1603 return ret; 1604 1605 return ret; 1606 } 1607 1608 const struct rtw89_mac_size_set rtw89_mac_size = { 1609 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1610 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0}, 1611 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0}, 1612 /* PCIE 64 */ 1613 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1614 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1615 /* DLFW */ 1616 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1617 .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1618 /* PCIE 64 */ 1619 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1620 /* 8852B PCIE SCC */ 1621 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1622 /* DLFW */ 1623 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1624 /* 8852C DLFW */ 1625 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1626 /* 8852C PCIE SCC */ 1627 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1628 /* PCIE */ 1629 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1630 .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1631 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1632 /* DLFW */ 1633 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1634 /* PCIE 64 */ 1635 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1636 /* DLFW */ 1637 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1638 /* 8852C DLFW */ 1639 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1640 /* 8852C PCIE SCC */ 1641 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1642 /* PCIE 64 */ 1643 .wde_qt0 = {3792, 196, 0, 107,}, 1644 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1645 /* DLFW */ 1646 .wde_qt4 = {0, 0, 0, 0,}, 1647 /* PCIE 64 */ 1648 .wde_qt6 = {448, 48, 0, 16,}, 1649 /* 8852B PCIE SCC */ 1650 .wde_qt7 = {446, 48, 0, 16,}, 1651 /* 8852C DLFW */ 1652 .wde_qt17 = {0, 0, 0, 0,}, 1653 /* 8852C PCIE SCC */ 1654 .wde_qt18 = {3228, 60, 0, 40,}, 1655 .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 1656 .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1657 /* PCIE SCC */ 1658 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1659 /* PCIE SCC */ 1660 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1661 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1662 /* DLFW */ 1663 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1664 /* PCIE 64 */ 1665 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1666 /* DLFW 52C */ 1667 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1668 /* DLFW 52C */ 1669 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1670 /* 8852C PCIE SCC */ 1671 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1672 /* 8852C PCIE SCC */ 1673 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1674 /* PCIE 64 */ 1675 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1676 /* 8852A PCIE WOW */ 1677 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1678 /* 8852B PCIE WOW */ 1679 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1680 /* 8851B PCIE WOW */ 1681 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1682 .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1683 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1684 .rsvd0_size0 = {212992, 0,}, 1685 .rsvd1_size0 = {587776, 2048,}, 1686 }; 1687 EXPORT_SYMBOL(rtw89_mac_size); 1688 1689 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1690 enum rtw89_qta_mode mode) 1691 { 1692 struct rtw89_mac_info *mac = &rtwdev->mac; 1693 const struct rtw89_dle_mem *cfg; 1694 1695 cfg = &rtwdev->chip->dle_mem[mode]; 1696 if (!cfg) 1697 return NULL; 1698 1699 if (cfg->mode != mode) { 1700 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1701 return NULL; 1702 } 1703 1704 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1705 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1706 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1707 mac->dle_info.qta_mode = mode; 1708 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1709 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1710 1711 return cfg; 1712 } 1713 1714 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1715 enum rtw89_mac_dle_rsvd_qt_type type, 1716 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1717 { 1718 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1719 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1720 1721 switch (type) { 1722 case DLE_RSVD_QT_MPDU_INFO: 1723 cfg->pktid = dle_info->ple_free_pg; 1724 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1725 break; 1726 case DLE_RSVD_QT_B0_CSI: 1727 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1728 cfg->pg_num = rsvd_qt->b0_csi; 1729 break; 1730 case DLE_RSVD_QT_B1_CSI: 1731 cfg->pktid = dle_info->ple_free_pg + 1732 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1733 cfg->pg_num = rsvd_qt->b1_csi; 1734 break; 1735 case DLE_RSVD_QT_B0_LMR: 1736 cfg->pktid = dle_info->ple_free_pg + 1737 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1738 cfg->pg_num = rsvd_qt->b0_lmr; 1739 break; 1740 case DLE_RSVD_QT_B1_LMR: 1741 cfg->pktid = dle_info->ple_free_pg + 1742 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1743 rsvd_qt->b0_lmr; 1744 cfg->pg_num = rsvd_qt->b1_lmr; 1745 break; 1746 case DLE_RSVD_QT_B0_FTM: 1747 cfg->pktid = dle_info->ple_free_pg + 1748 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1749 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1750 cfg->pg_num = rsvd_qt->b0_ftm; 1751 break; 1752 case DLE_RSVD_QT_B1_FTM: 1753 cfg->pktid = dle_info->ple_free_pg + 1754 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1755 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1756 cfg->pg_num = rsvd_qt->b1_ftm; 1757 break; 1758 default: 1759 return -EINVAL; 1760 } 1761 1762 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1763 1764 return 0; 1765 } 1766 1767 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1768 { 1769 struct rtw89_mac_dle_dfi_qempty qempty; 1770 u32 grpnum, qtmp, val32, msk32; 1771 int i, j, ret; 1772 1773 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1774 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1775 1776 for (i = 0; i < grpnum; i++) { 1777 qempty.grpsel = i; 1778 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1779 if (ret) { 1780 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1781 return false; 1782 } 1783 qtmp = qempty.qempty; 1784 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1785 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 1786 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1787 return false; 1788 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1789 } 1790 } 1791 1792 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1793 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1794 if (ret) { 1795 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1796 return false; 1797 } 1798 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1799 if ((qempty.qempty & msk32) != msk32) 1800 return false; 1801 1802 if (rtwdev->dbcc_en) { 1803 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1804 if ((qempty.qempty & msk32) != msk32) 1805 return false; 1806 } 1807 1808 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1809 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1810 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1811 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1812 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1813 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1814 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1815 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1816 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1817 1818 return (val32 & msk32) == msk32; 1819 } 1820 1821 static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1822 { 1823 const struct rtw89_dle_size *wde = cfg->wde_size; 1824 const struct rtw89_dle_size *ple = cfg->ple_size; 1825 u32 used; 1826 1827 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1828 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1829 1830 if (cfg->rsvd0_size && cfg->rsvd1_size) { 1831 used += cfg->rsvd0_size->size; 1832 used += cfg->rsvd1_size->size; 1833 } 1834 1835 return used; 1836 } 1837 1838 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1839 enum rtw89_qta_mode mode) 1840 { 1841 u32 size = rtwdev->chip->fifo_size; 1842 1843 if (mode == RTW89_QTA_SCC) 1844 size -= rtwdev->chip->dle_scc_rsvd_size; 1845 1846 return size; 1847 } 1848 1849 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 1850 { 1851 if (enable) 1852 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1853 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1854 else 1855 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1856 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1857 } 1858 1859 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 1860 { 1861 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1862 1863 if (enable) { 1864 if (rtwdev->chip->chip_id == RTL8851B) 1865 val |= B_AX_AXIDMA_CLK_EN; 1866 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1867 } else { 1868 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1869 } 1870 } 1871 1872 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1873 { 1874 const struct rtw89_dle_size *size_cfg; 1875 u32 val; 1876 u8 bound = 0; 1877 1878 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1879 size_cfg = cfg->wde_size; 1880 1881 switch (size_cfg->pge_size) { 1882 default: 1883 case RTW89_WDE_PG_64: 1884 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1885 B_AX_WDE_PAGE_SEL_MASK); 1886 break; 1887 case RTW89_WDE_PG_128: 1888 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1889 B_AX_WDE_PAGE_SEL_MASK); 1890 break; 1891 case RTW89_WDE_PG_256: 1892 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1893 return -EINVAL; 1894 } 1895 1896 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1897 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1898 B_AX_WDE_FREE_PAGE_NUM_MASK); 1899 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1900 1901 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1902 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1903 * size_cfg->pge_size / DLE_BOUND_UNIT; 1904 size_cfg = cfg->ple_size; 1905 1906 switch (size_cfg->pge_size) { 1907 default: 1908 case RTW89_PLE_PG_64: 1909 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1910 return -EINVAL; 1911 case RTW89_PLE_PG_128: 1912 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1913 B_AX_PLE_PAGE_SEL_MASK); 1914 break; 1915 case RTW89_PLE_PG_256: 1916 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1917 B_AX_PLE_PAGE_SEL_MASK); 1918 break; 1919 } 1920 1921 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1922 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1923 B_AX_PLE_FREE_PAGE_NUM_MASK); 1924 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1925 1926 return 0; 1927 } 1928 1929 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 1930 { 1931 u32 reg, mask; 1932 u32 ini; 1933 1934 if (wde_or_ple) { 1935 reg = R_AX_WDE_INI_STATUS; 1936 mask = WDE_MGN_INI_RDY; 1937 } else { 1938 reg = R_AX_PLE_INI_STATUS; 1939 mask = PLE_MGN_INI_RDY; 1940 } 1941 1942 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 1943 2000, false, rtwdev, reg); 1944 } 1945 1946 #define INVALID_QT_WCPU U16_MAX 1947 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1948 do { \ 1949 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1950 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1951 rtw89_write32(rtwdev, \ 1952 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1953 val); \ 1954 } while (0) 1955 #define SET_QUOTA(_x, _module, _idx) \ 1956 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1957 1958 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 1959 const struct rtw89_wde_quota *min_cfg, 1960 const struct rtw89_wde_quota *max_cfg, 1961 u16 ext_wde_min_qt_wcpu) 1962 { 1963 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1964 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1965 u32 val; 1966 1967 SET_QUOTA(hif, WDE, 0); 1968 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1969 SET_QUOTA(pkt_in, WDE, 3); 1970 SET_QUOTA(cpu_io, WDE, 4); 1971 } 1972 1973 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 1974 const struct rtw89_ple_quota *min_cfg, 1975 const struct rtw89_ple_quota *max_cfg) 1976 { 1977 u32 val; 1978 1979 SET_QUOTA(cma0_tx, PLE, 0); 1980 SET_QUOTA(cma1_tx, PLE, 1); 1981 SET_QUOTA(c2h, PLE, 2); 1982 SET_QUOTA(h2c, PLE, 3); 1983 SET_QUOTA(wcpu, PLE, 4); 1984 SET_QUOTA(mpdu_proc, PLE, 5); 1985 SET_QUOTA(cma0_dma, PLE, 6); 1986 SET_QUOTA(cma1_dma, PLE, 7); 1987 SET_QUOTA(bb_rpt, PLE, 8); 1988 SET_QUOTA(wd_rel, PLE, 9); 1989 SET_QUOTA(cpu_io, PLE, 10); 1990 if (rtwdev->chip->chip_id == RTL8852C) 1991 SET_QUOTA(tx_rpt, PLE, 11); 1992 } 1993 1994 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 1995 { 1996 const struct rtw89_ple_quota *min_cfg, *max_cfg; 1997 const struct rtw89_dle_mem *cfg; 1998 u32 val; 1999 2000 if (rtwdev->chip->chip_id == RTL8852C) 2001 return 0; 2002 2003 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2004 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2005 return -EINVAL; 2006 } 2007 2008 if (wow) 2009 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2010 else 2011 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2012 if (!cfg) { 2013 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2014 return -EINVAL; 2015 } 2016 2017 min_cfg = cfg->ple_min_qt; 2018 max_cfg = cfg->ple_max_qt; 2019 SET_QUOTA(cma0_dma, PLE, 6); 2020 SET_QUOTA(cma1_dma, PLE, 7); 2021 2022 return 0; 2023 } 2024 #undef SET_QUOTA 2025 2026 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2027 { 2028 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2029 2030 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2031 return; 2032 2033 if (enable) 2034 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2035 else 2036 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2037 } 2038 2039 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2040 const struct rtw89_dle_mem *cfg, 2041 u16 ext_wde_min_qt_wcpu) 2042 { 2043 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2044 2045 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2046 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2047 } 2048 2049 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2050 enum rtw89_qta_mode ext_mode) 2051 { 2052 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2053 const struct rtw89_dle_mem *cfg, *ext_cfg; 2054 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2055 int ret; 2056 2057 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2058 if (ret) 2059 return ret; 2060 2061 cfg = get_dle_mem_cfg(rtwdev, mode); 2062 if (!cfg) { 2063 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2064 ret = -EINVAL; 2065 goto error; 2066 } 2067 2068 if (mode == RTW89_QTA_DLFW) { 2069 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2070 if (!ext_cfg) { 2071 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2072 ext_mode); 2073 ret = -EINVAL; 2074 goto error; 2075 } 2076 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2077 } 2078 2079 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2080 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2081 ret = -EINVAL; 2082 goto error; 2083 } 2084 2085 mac->dle_func_en(rtwdev, false); 2086 mac->dle_clk_en(rtwdev, true); 2087 2088 ret = mac->dle_mix_cfg(rtwdev, cfg); 2089 if (ret) { 2090 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2091 goto error; 2092 } 2093 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2094 2095 mac->dle_func_en(rtwdev, true); 2096 2097 ret = mac->chk_dle_rdy(rtwdev, true); 2098 if (ret) { 2099 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2100 return ret; 2101 } 2102 2103 ret = mac->chk_dle_rdy(rtwdev, false); 2104 if (ret) { 2105 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2106 return ret; 2107 } 2108 2109 return 0; 2110 error: 2111 mac->dle_func_en(rtwdev, false); 2112 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2113 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2114 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2115 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2116 2117 return ret; 2118 } 2119 2120 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2121 enum rtw89_qta_mode mode) 2122 { 2123 u32 reg, max_preld_size, min_rsvd_size; 2124 2125 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2126 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2127 reg = mac_idx == RTW89_MAC_0 ? 2128 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2129 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2130 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2131 2132 min_rsvd_size = PRELD_AMSDU_SIZE; 2133 reg = mac_idx == RTW89_MAC_0 ? 2134 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2135 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2136 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2137 2138 return 0; 2139 } 2140 2141 static bool is_qta_poh(struct rtw89_dev *rtwdev) 2142 { 2143 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2144 } 2145 2146 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2147 enum rtw89_qta_mode mode) 2148 { 2149 const struct rtw89_chip_info *chip = rtwdev->chip; 2150 2151 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) || 2152 !is_qta_poh(rtwdev)) 2153 return 0; 2154 2155 return preload_init_set(rtwdev, mac_idx, mode); 2156 } 2157 2158 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2159 { 2160 u32 msk32; 2161 u32 val32; 2162 2163 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2164 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2165 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2166 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2167 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2168 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2169 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2170 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2171 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2172 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2173 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2174 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2175 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2176 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2177 2178 if ((val32 & msk32) == msk32) 2179 return true; 2180 2181 return false; 2182 } 2183 2184 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2185 { 2186 const struct rtw89_chip_info *chip = rtwdev->chip; 2187 2188 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2189 return; 2190 2191 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2192 SS2F_PATH_WLCPU); 2193 } 2194 2195 static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2196 { 2197 u32 p_val; 2198 u8 val; 2199 int ret; 2200 2201 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2202 if (ret) 2203 return ret; 2204 2205 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2206 val |= B_AX_SS_EN; 2207 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2208 2209 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2210 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2211 if (ret) { 2212 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2213 return ret; 2214 } 2215 2216 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2217 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2218 2219 _patch_ss2f_path(rtwdev); 2220 2221 return 0; 2222 } 2223 2224 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2225 { 2226 int ret; 2227 2228 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2229 if (ret) 2230 return ret; 2231 2232 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2233 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2234 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2235 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2236 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2237 2238 return 0; 2239 } 2240 2241 static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2242 { 2243 const struct rtw89_chip_info *chip = rtwdev->chip; 2244 u32 val = 0; 2245 int ret; 2246 2247 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2248 if (ret) 2249 return ret; 2250 2251 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2252 /* init clock */ 2253 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2254 /* init TX encryption */ 2255 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2256 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2257 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2258 chip->chip_id == RTL8851B) 2259 val &= ~B_AX_TX_PARTIAL_MODE; 2260 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2261 2262 /* init MIC ICV append */ 2263 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2264 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2265 2266 /* option init */ 2267 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2268 2269 if (chip->chip_id == RTL8852C) 2270 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2271 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2272 2273 return 0; 2274 } 2275 2276 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2277 { 2278 int ret; 2279 2280 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2281 if (ret) { 2282 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2283 return ret; 2284 } 2285 2286 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2287 if (ret) { 2288 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2289 return ret; 2290 } 2291 2292 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2293 if (ret) { 2294 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2295 return ret; 2296 } 2297 2298 ret = sta_sch_init_ax(rtwdev); 2299 if (ret) { 2300 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2301 return ret; 2302 } 2303 2304 ret = mpdu_proc_init_ax(rtwdev); 2305 if (ret) { 2306 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2307 return ret; 2308 } 2309 2310 ret = sec_eng_init_ax(rtwdev); 2311 if (ret) { 2312 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2313 return ret; 2314 } 2315 2316 return ret; 2317 } 2318 2319 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2320 { 2321 u32 val, reg; 2322 u16 p_val; 2323 int ret; 2324 2325 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2326 if (ret) 2327 return ret; 2328 2329 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2330 2331 val = rtw89_read32(rtwdev, reg); 2332 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2333 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2334 rtw89_write32(rtwdev, reg, val); 2335 2336 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2337 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2338 if (ret) { 2339 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2340 return ret; 2341 } 2342 2343 return 0; 2344 } 2345 2346 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2347 { 2348 u32 ret; 2349 u32 reg; 2350 u32 val; 2351 2352 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2353 if (ret) 2354 return ret; 2355 2356 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2357 if (rtwdev->chip->chip_id == RTL8852C) 2358 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2359 SIFS_MACTXEN_T1_V1); 2360 else 2361 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2362 SIFS_MACTXEN_T1); 2363 2364 if (rtw89_is_rtl885xb(rtwdev)) { 2365 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2366 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2367 } 2368 2369 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2370 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2371 2372 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2373 if (rtwdev->chip->chip_id == RTL8852C) { 2374 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2375 B_AX_TX_PARTIAL_MODE); 2376 if (!val) 2377 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2378 SCH_PREBKF_24US); 2379 } else { 2380 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2381 SCH_PREBKF_24US); 2382 } 2383 2384 return 0; 2385 } 2386 2387 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2388 enum rtw89_machdr_frame_type type, 2389 enum rtw89_mac_fwd_target fwd_target, 2390 u8 mac_idx) 2391 { 2392 u32 reg; 2393 u32 val; 2394 2395 switch (fwd_target) { 2396 case RTW89_FWD_DONT_CARE: 2397 val = RX_FLTR_FRAME_DROP; 2398 break; 2399 case RTW89_FWD_TO_HOST: 2400 val = RX_FLTR_FRAME_TO_HOST; 2401 break; 2402 case RTW89_FWD_TO_WLAN_CPU: 2403 val = RX_FLTR_FRAME_TO_WLCPU; 2404 break; 2405 default: 2406 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2407 return -EINVAL; 2408 } 2409 2410 switch (type) { 2411 case RTW89_MGNT: 2412 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2413 break; 2414 case RTW89_CTRL: 2415 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2416 break; 2417 case RTW89_DATA: 2418 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2419 break; 2420 default: 2421 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2422 return -EINVAL; 2423 } 2424 rtw89_write32(rtwdev, reg, val); 2425 2426 return 0; 2427 } 2428 2429 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2430 { 2431 int ret, i; 2432 u32 mac_ftlr, plcp_ftlr; 2433 2434 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2435 if (ret) 2436 return ret; 2437 2438 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2439 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2440 mac_idx); 2441 if (ret) 2442 return ret; 2443 } 2444 mac_ftlr = rtwdev->hal.rx_fltr; 2445 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2446 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2447 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2448 B_AX_HE_SIGB_CRC_CHK; 2449 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2450 mac_ftlr); 2451 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2452 plcp_ftlr); 2453 2454 return 0; 2455 } 2456 2457 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2458 { 2459 u32 reg, val32; 2460 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2461 2462 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2463 B_AX_RSP_CHK_BASIC_NAV; 2464 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2465 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2466 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2467 2468 switch (rtwdev->chip->chip_id) { 2469 case RTL8852A: 2470 case RTL8852B: 2471 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2472 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2473 rtw89_write32(rtwdev, reg, val32); 2474 2475 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2476 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2477 rtw89_write32(rtwdev, reg, val32); 2478 break; 2479 default: 2480 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2481 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2482 rtw89_write32(rtwdev, reg, val32); 2483 2484 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2485 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2486 rtw89_write32(rtwdev, reg, val32); 2487 break; 2488 } 2489 } 2490 2491 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2492 { 2493 u32 val, reg; 2494 int ret; 2495 2496 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2497 if (ret) 2498 return ret; 2499 2500 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2501 val = rtw89_read32(rtwdev, reg); 2502 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2503 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2504 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2505 B_AX_CTN_CHK_INTRA_NAV | 2506 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2507 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2508 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2509 B_AX_CTN_CHK_CCA_P20); 2510 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2511 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2512 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2513 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2514 B_AX_SIFS_CHK_EDCCA); 2515 2516 rtw89_write32(rtwdev, reg, val); 2517 2518 _patch_dis_resp_chk(rtwdev, mac_idx); 2519 2520 return 0; 2521 } 2522 2523 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2524 { 2525 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2526 B_AX_WMAC_TF_UP_NAV_EN | 2527 B_AX_WMAC_NAV_UPPER_EN); 2528 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2529 2530 return 0; 2531 } 2532 2533 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2534 { 2535 u32 reg; 2536 int ret; 2537 2538 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2539 if (ret) 2540 return ret; 2541 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2542 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2543 2544 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2545 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2546 2547 return 0; 2548 } 2549 2550 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2551 { 2552 u32 reg; 2553 int ret; 2554 2555 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2556 if (ret) 2557 return ret; 2558 2559 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2560 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2561 2562 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2563 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2564 2565 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2566 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2567 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2568 2569 return 0; 2570 } 2571 2572 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2573 { 2574 const struct rtw89_chip_info *chip = rtwdev->chip; 2575 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2576 u32 reg, val, sifs; 2577 int ret; 2578 2579 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2580 if (ret) 2581 return ret; 2582 2583 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2584 val = rtw89_read32(rtwdev, reg); 2585 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2586 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2587 2588 switch (rtwdev->chip->chip_id) { 2589 case RTL8852A: 2590 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2591 break; 2592 case RTL8851B: 2593 case RTL8852B: 2594 case RTL8852BT: 2595 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2596 break; 2597 default: 2598 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2599 break; 2600 } 2601 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2602 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2603 rtw89_write32(rtwdev, reg, val); 2604 2605 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2606 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2607 2608 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2609 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2610 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2611 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2612 2613 return 0; 2614 } 2615 2616 static void rst_bacam(struct rtw89_dev *rtwdev) 2617 { 2618 u32 val32; 2619 int ret; 2620 2621 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2622 S_AX_BACAM_RST_ALL); 2623 2624 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2625 1, 1000, false, 2626 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2627 if (ret) 2628 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2629 } 2630 2631 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2632 { 2633 #define TRXCFG_RMAC_CCA_TO 32 2634 #define TRXCFG_RMAC_DATA_TO 15 2635 #define RX_MAX_LEN_UNIT 512 2636 #define PLD_RLS_MAX_PG 127 2637 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2638 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2639 int ret; 2640 u32 reg, rx_max_len, rx_qta; 2641 u16 val; 2642 2643 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2644 if (ret) 2645 return ret; 2646 2647 if (mac_idx == RTW89_MAC_0) 2648 rst_bacam(rtwdev); 2649 2650 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2651 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2652 2653 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2654 val = rtw89_read16(rtwdev, reg); 2655 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2656 B_AX_RX_DLK_DATA_TIME_MASK); 2657 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2658 B_AX_RX_DLK_CCA_TIME_MASK); 2659 if (chip_id == RTL8852BT) 2660 val |= B_AX_RX_DLK_RST_EN; 2661 rtw89_write16(rtwdev, reg, val); 2662 2663 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2664 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2665 2666 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2667 if (mac_idx == RTW89_MAC_0) 2668 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2669 else 2670 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2671 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2672 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2673 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2674 rx_max_len /= RX_MAX_LEN_UNIT; 2675 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2676 2677 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) { 2678 rtw89_write16_mask(rtwdev, 2679 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2680 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2681 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2682 BIT(12)); 2683 } 2684 2685 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2686 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2687 2688 return ret; 2689 } 2690 2691 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2692 { 2693 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2694 u32 val, reg; 2695 int ret; 2696 2697 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2698 if (ret) 2699 return ret; 2700 2701 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2702 val = rtw89_read32(rtwdev, reg); 2703 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2704 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2705 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2706 rtw89_write32(rtwdev, reg, val); 2707 2708 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2709 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2710 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2711 } 2712 2713 return 0; 2714 } 2715 2716 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2717 { 2718 const struct rtw89_dle_mem *cfg; 2719 2720 cfg = get_dle_mem_cfg(rtwdev, mode); 2721 if (!cfg) { 2722 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2723 return false; 2724 } 2725 2726 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2727 } 2728 2729 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2730 { 2731 u32 val, reg; 2732 int ret; 2733 2734 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2735 if (ret) 2736 return ret; 2737 2738 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2739 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2740 val = rtw89_read32(rtwdev, reg); 2741 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2742 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2743 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2744 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2745 val |= B_AX_HW_CTS2SELF_EN; 2746 rtw89_write32(rtwdev, reg, val); 2747 2748 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2749 val = rtw89_read32(rtwdev, reg); 2750 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2751 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2752 rtw89_write32(rtwdev, reg, val); 2753 } 2754 2755 if (mac_idx == RTW89_MAC_0) { 2756 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2757 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2758 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2759 B_AX_PTCL_TRIGGER_SS_EN_0 | 2760 B_AX_PTCL_TRIGGER_SS_EN_1 | 2761 B_AX_PTCL_TRIGGER_SS_EN_UL); 2762 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2763 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2764 } else if (mac_idx == RTW89_MAC_1) { 2765 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2766 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2767 } 2768 2769 return 0; 2770 } 2771 2772 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2773 { 2774 u32 reg; 2775 int ret; 2776 2777 if (!rtw89_is_rtl885xb(rtwdev)) 2778 return 0; 2779 2780 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2781 if (ret) 2782 return ret; 2783 2784 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2785 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2786 2787 return 0; 2788 } 2789 2790 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2791 { 2792 int ret; 2793 2794 ret = scheduler_init_ax(rtwdev, mac_idx); 2795 if (ret) { 2796 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2797 return ret; 2798 } 2799 2800 ret = addr_cam_init_ax(rtwdev, mac_idx); 2801 if (ret) { 2802 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2803 ret); 2804 return ret; 2805 } 2806 2807 ret = rx_fltr_init_ax(rtwdev, mac_idx); 2808 if (ret) { 2809 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2810 ret); 2811 return ret; 2812 } 2813 2814 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 2815 if (ret) { 2816 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2817 ret); 2818 return ret; 2819 } 2820 2821 ret = nav_ctrl_init_ax(rtwdev); 2822 if (ret) { 2823 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2824 ret); 2825 return ret; 2826 } 2827 2828 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 2829 if (ret) { 2830 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2831 mac_idx, ret); 2832 return ret; 2833 } 2834 2835 ret = tmac_init_ax(rtwdev, mac_idx); 2836 if (ret) { 2837 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2838 return ret; 2839 } 2840 2841 ret = trxptcl_init_ax(rtwdev, mac_idx); 2842 if (ret) { 2843 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2844 return ret; 2845 } 2846 2847 ret = rmac_init_ax(rtwdev, mac_idx); 2848 if (ret) { 2849 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2850 return ret; 2851 } 2852 2853 ret = cmac_com_init_ax(rtwdev, mac_idx); 2854 if (ret) { 2855 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2856 return ret; 2857 } 2858 2859 ret = ptcl_init_ax(rtwdev, mac_idx); 2860 if (ret) { 2861 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2862 return ret; 2863 } 2864 2865 ret = cmac_dma_init_ax(rtwdev, mac_idx); 2866 if (ret) { 2867 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2868 return ret; 2869 } 2870 2871 return ret; 2872 } 2873 2874 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2875 struct rtw89_mac_c2h_info *c2h_info) 2876 { 2877 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2878 struct rtw89_mac_h2c_info h2c_info = {0}; 2879 u32 ret; 2880 2881 mac->cnv_efuse_state(rtwdev, false); 2882 2883 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2884 h2c_info.content_len = 0; 2885 2886 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2887 if (ret) 2888 goto out; 2889 2890 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2891 ret = -EINVAL; 2892 2893 out: 2894 mac->cnv_efuse_state(rtwdev, true); 2895 2896 return ret; 2897 } 2898 2899 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2900 { 2901 struct rtw89_efuse *efuse = &rtwdev->efuse; 2902 struct rtw89_hal *hal = &rtwdev->hal; 2903 const struct rtw89_chip_info *chip = rtwdev->chip; 2904 struct rtw89_mac_c2h_info c2h_info = {0}; 2905 const struct rtw89_c2hreg_phycap *phycap; 2906 u8 tx_nss; 2907 u8 rx_nss; 2908 u8 tx_ant; 2909 u8 rx_ant; 2910 u32 ret; 2911 2912 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2913 if (ret) 2914 return ret; 2915 2916 phycap = &c2h_info.u.phycap; 2917 2918 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 2919 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 2920 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 2921 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2922 2923 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2924 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2925 2926 if (tx_ant == 1) 2927 hal->antenna_tx = RF_B; 2928 if (rx_ant == 1) 2929 hal->antenna_rx = RF_B; 2930 2931 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2932 hal->antenna_tx = RF_B; 2933 hal->tx_path_diversity = true; 2934 } 2935 2936 if (chip->rf_path_num == 1) { 2937 hal->antenna_tx = RF_A; 2938 hal->antenna_rx = RF_A; 2939 if ((efuse->rfe_type % 3) == 2) 2940 hal->ant_diversity = true; 2941 } 2942 2943 rtw89_debug(rtwdev, RTW89_DBG_FW, 2944 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2945 hal->tx_nss, tx_nss, chip->tx_nss, 2946 hal->rx_nss, rx_nss, chip->rx_nss); 2947 rtw89_debug(rtwdev, RTW89_DBG_FW, 2948 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2949 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2950 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2951 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2952 2953 return 0; 2954 } 2955 2956 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2957 u16 tx_en_u16, u16 mask_u16) 2958 { 2959 u32 ret; 2960 struct rtw89_mac_c2h_info c2h_info = {0}; 2961 struct rtw89_mac_h2c_info h2c_info = {0}; 2962 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 2963 2964 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2965 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 2966 2967 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 2968 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 2969 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 2970 2971 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2972 if (ret) 2973 return ret; 2974 2975 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2976 return -EINVAL; 2977 2978 return 0; 2979 } 2980 2981 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2982 u16 tx_en, u16 tx_en_mask) 2983 { 2984 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 2985 u16 val; 2986 int ret; 2987 2988 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2989 if (ret) 2990 return ret; 2991 2992 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2993 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2994 tx_en, tx_en_mask); 2995 2996 val = rtw89_read16(rtwdev, reg); 2997 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2998 rtw89_write16(rtwdev, reg, val); 2999 3000 return 0; 3001 } 3002 3003 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3004 u32 tx_en, u32 tx_en_mask) 3005 { 3006 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3007 u32 val; 3008 int ret; 3009 3010 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3011 if (ret) 3012 return ret; 3013 3014 val = rtw89_read32(rtwdev, reg); 3015 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3016 rtw89_write32(rtwdev, reg, val); 3017 3018 return 0; 3019 } 3020 3021 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3022 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3023 { 3024 int ret; 3025 3026 *tx_en = rtw89_read16(rtwdev, 3027 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3028 3029 switch (sel) { 3030 case RTW89_SCH_TX_SEL_ALL: 3031 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3032 B_AX_CTN_TXEN_ALL_MASK); 3033 if (ret) 3034 return ret; 3035 break; 3036 case RTW89_SCH_TX_SEL_HIQ: 3037 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3038 0, B_AX_CTN_TXEN_HGQ); 3039 if (ret) 3040 return ret; 3041 break; 3042 case RTW89_SCH_TX_SEL_MG0: 3043 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3044 0, B_AX_CTN_TXEN_MGQ); 3045 if (ret) 3046 return ret; 3047 break; 3048 case RTW89_SCH_TX_SEL_MACID: 3049 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3050 B_AX_CTN_TXEN_ALL_MASK); 3051 if (ret) 3052 return ret; 3053 break; 3054 default: 3055 return 0; 3056 } 3057 3058 return 0; 3059 } 3060 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3061 3062 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3063 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3064 { 3065 int ret; 3066 3067 *tx_en = rtw89_read32(rtwdev, 3068 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3069 3070 switch (sel) { 3071 case RTW89_SCH_TX_SEL_ALL: 3072 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3073 B_AX_CTN_TXEN_ALL_MASK_V1); 3074 if (ret) 3075 return ret; 3076 break; 3077 case RTW89_SCH_TX_SEL_HIQ: 3078 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3079 0, B_AX_CTN_TXEN_HGQ); 3080 if (ret) 3081 return ret; 3082 break; 3083 case RTW89_SCH_TX_SEL_MG0: 3084 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3085 0, B_AX_CTN_TXEN_MGQ); 3086 if (ret) 3087 return ret; 3088 break; 3089 case RTW89_SCH_TX_SEL_MACID: 3090 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3091 B_AX_CTN_TXEN_ALL_MASK_V1); 3092 if (ret) 3093 return ret; 3094 break; 3095 default: 3096 return 0; 3097 } 3098 3099 return 0; 3100 } 3101 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3102 3103 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3104 { 3105 int ret; 3106 3107 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3108 if (ret) 3109 return ret; 3110 3111 return 0; 3112 } 3113 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3114 3115 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3116 { 3117 int ret; 3118 3119 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3120 B_AX_CTN_TXEN_ALL_MASK_V1); 3121 if (ret) 3122 return ret; 3123 3124 return 0; 3125 } 3126 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3127 3128 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3129 { 3130 u32 val, reg; 3131 int ret; 3132 3133 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3134 val = buf_len; 3135 val |= B_AX_WD_BUF_REQ_EXEC; 3136 rtw89_write32(rtwdev, reg, val); 3137 3138 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3139 3140 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3141 1, 2000, false, rtwdev, reg); 3142 if (ret) 3143 return ret; 3144 3145 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3146 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3147 return -ENOENT; 3148 3149 return 0; 3150 } 3151 3152 static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3153 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3154 { 3155 u32 val, cmd_type, reg; 3156 int ret; 3157 3158 cmd_type = ctrl_para->cmd_type; 3159 3160 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3161 val = 0; 3162 val = u32_replace_bits(val, ctrl_para->start_pktid, 3163 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3164 val = u32_replace_bits(val, ctrl_para->end_pktid, 3165 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3166 rtw89_write32(rtwdev, reg, val); 3167 3168 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3169 val = 0; 3170 val = u32_replace_bits(val, ctrl_para->src_pid, 3171 B_AX_CPUQ_OP_SRC_PID_MASK); 3172 val = u32_replace_bits(val, ctrl_para->src_qid, 3173 B_AX_CPUQ_OP_SRC_QID_MASK); 3174 val = u32_replace_bits(val, ctrl_para->dst_pid, 3175 B_AX_CPUQ_OP_DST_PID_MASK); 3176 val = u32_replace_bits(val, ctrl_para->dst_qid, 3177 B_AX_CPUQ_OP_DST_QID_MASK); 3178 rtw89_write32(rtwdev, reg, val); 3179 3180 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3181 val = 0; 3182 val = u32_replace_bits(val, cmd_type, 3183 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3184 val = u32_replace_bits(val, ctrl_para->macid, 3185 B_AX_CPUQ_OP_MACID_MASK); 3186 val = u32_replace_bits(val, ctrl_para->pkt_num, 3187 B_AX_CPUQ_OP_PKTNUM_MASK); 3188 val |= B_AX_WD_CPUQ_OP_EXEC; 3189 rtw89_write32(rtwdev, reg, val); 3190 3191 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3192 3193 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3194 1, 2000, false, rtwdev, reg); 3195 if (ret) 3196 return ret; 3197 3198 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3199 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3200 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3201 3202 return 0; 3203 } 3204 3205 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3206 bool band1_en) 3207 { 3208 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3209 const struct rtw89_dle_mem *cfg; 3210 3211 cfg = get_dle_mem_cfg(rtwdev, mode); 3212 if (!cfg) { 3213 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3214 return -EINVAL; 3215 } 3216 3217 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3218 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3219 return -EINVAL; 3220 } 3221 3222 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3223 3224 return mac->dle_quota_change(rtwdev, band1_en); 3225 } 3226 3227 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3228 { 3229 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3230 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3231 u16 pkt_id; 3232 int ret; 3233 3234 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3235 if (ret) { 3236 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3237 return ret; 3238 } 3239 3240 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3241 ctrl_para.start_pktid = pkt_id; 3242 ctrl_para.end_pktid = pkt_id; 3243 ctrl_para.pkt_num = 0; 3244 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3245 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3246 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3247 if (ret) { 3248 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3249 return -EFAULT; 3250 } 3251 3252 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3253 if (ret) { 3254 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3255 return ret; 3256 } 3257 3258 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3259 ctrl_para.start_pktid = pkt_id; 3260 ctrl_para.end_pktid = pkt_id; 3261 ctrl_para.pkt_num = 0; 3262 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3263 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3264 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3265 if (ret) { 3266 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3267 return -EFAULT; 3268 } 3269 3270 return 0; 3271 } 3272 3273 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3274 { 3275 int ret; 3276 u32 reg; 3277 u8 val; 3278 3279 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3280 if (ret) 3281 return ret; 3282 3283 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3284 3285 ret = read_poll_timeout(rtw89_read8, val, 3286 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3287 SW_CVR_DUR_US, 3288 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3289 false, rtwdev, reg); 3290 if (ret) 3291 return ret; 3292 3293 return 0; 3294 } 3295 3296 static int band1_enable_ax(struct rtw89_dev *rtwdev) 3297 { 3298 int ret, i; 3299 u32 sleep_bak[4] = {0}; 3300 u32 pause_bak[4] = {0}; 3301 u32 tx_en; 3302 3303 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3304 if (ret) { 3305 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3306 return ret; 3307 } 3308 3309 for (i = 0; i < 4; i++) { 3310 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3311 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3312 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3313 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3314 } 3315 3316 ret = band_idle_ck_b(rtwdev, 0); 3317 if (ret) { 3318 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3319 return ret; 3320 } 3321 3322 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3323 if (ret) { 3324 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3325 return ret; 3326 } 3327 3328 for (i = 0; i < 4; i++) { 3329 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3330 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3331 } 3332 3333 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3334 if (ret) { 3335 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3336 return ret; 3337 } 3338 3339 ret = cmac_func_en_ax(rtwdev, 1, true); 3340 if (ret) { 3341 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3342 return ret; 3343 } 3344 3345 ret = cmac_init_ax(rtwdev, 1); 3346 if (ret) { 3347 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3348 return ret; 3349 } 3350 3351 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3352 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3353 3354 return 0; 3355 } 3356 3357 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3358 { 3359 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3360 3361 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3362 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3363 } 3364 3365 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3366 { 3367 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3368 3369 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3370 } 3371 3372 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3373 { 3374 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3375 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3376 3377 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3378 B_AX_TX_GET_ERRPKTID_INT_EN | 3379 B_AX_TX_NXT_ERRPKTID_INT_EN | 3380 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3381 B_AX_TX_OFFSET_ERR_INT_EN | 3382 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3383 if (chip_id == RTL8852C) 3384 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3385 B_AX_TX_ETH_TYPE_ERR_EN | 3386 B_AX_TX_LLC_PRE_ERR_EN | 3387 B_AX_TX_NW_TYPE_ERR_EN | 3388 B_AX_TX_KSRCH_ERR_EN); 3389 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3390 imr->mpdu_tx_imr_set); 3391 3392 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3393 B_AX_GETPKTID_ERR_INT_EN | 3394 B_AX_MHDRLEN_ERR_INT_EN | 3395 B_AX_RPT_ERR_INT_EN); 3396 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3397 imr->mpdu_rx_imr_set); 3398 } 3399 3400 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3401 { 3402 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3403 3404 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3405 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3406 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3407 B_AX_PLE_B_PKTID_ERR_INT_EN); 3408 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3409 imr->sta_sch_imr_set); 3410 } 3411 3412 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3413 { 3414 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3415 3416 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3417 imr->txpktctl_imr_b0_clr); 3418 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3419 imr->txpktctl_imr_b0_set); 3420 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3421 imr->txpktctl_imr_b1_clr); 3422 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3423 imr->txpktctl_imr_b1_set); 3424 } 3425 3426 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3427 { 3428 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3429 3430 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3431 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3432 } 3433 3434 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3435 { 3436 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3437 3438 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3439 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3440 } 3441 3442 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3443 { 3444 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3445 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3446 } 3447 3448 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3449 { 3450 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3451 3452 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3453 imr->host_disp_imr_clr); 3454 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3455 imr->host_disp_imr_set); 3456 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3457 imr->cpu_disp_imr_clr); 3458 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3459 imr->cpu_disp_imr_set); 3460 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3461 imr->other_disp_imr_clr); 3462 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3463 imr->other_disp_imr_set); 3464 } 3465 3466 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3467 { 3468 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3469 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3470 } 3471 3472 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3473 { 3474 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3475 3476 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3477 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3478 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3479 B_AX_BBRPT_CHINFO_IMR_CLR); 3480 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3481 imr->bbrpt_err_imr_set); 3482 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3483 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3484 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3485 } 3486 3487 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3488 { 3489 u32 reg; 3490 3491 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3492 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3493 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3494 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3495 } 3496 3497 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3498 { 3499 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3500 u32 reg; 3501 3502 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3503 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3504 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3505 } 3506 3507 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3508 { 3509 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3510 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3511 u32 reg; 3512 3513 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3514 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3515 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3516 3517 if (chip_id == RTL8852C) { 3518 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3519 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3520 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3521 } 3522 } 3523 3524 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3525 { 3526 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3527 u32 reg; 3528 3529 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3530 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3531 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3532 } 3533 3534 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3535 { 3536 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3537 u32 reg; 3538 3539 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3540 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3541 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3542 } 3543 3544 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3545 { 3546 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3547 u32 reg; 3548 3549 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3550 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3551 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3552 } 3553 3554 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3555 enum rtw89_mac_hwmod_sel sel) 3556 { 3557 int ret; 3558 3559 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3560 if (ret) { 3561 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3562 sel, mac_idx); 3563 return ret; 3564 } 3565 3566 if (sel == RTW89_DMAC_SEL) { 3567 rtw89_wdrls_imr_enable(rtwdev); 3568 rtw89_wsec_imr_enable(rtwdev); 3569 rtw89_mpdu_trx_imr_enable(rtwdev); 3570 rtw89_sta_sch_imr_enable(rtwdev); 3571 rtw89_txpktctl_imr_enable(rtwdev); 3572 rtw89_wde_imr_enable(rtwdev); 3573 rtw89_ple_imr_enable(rtwdev); 3574 rtw89_pktin_imr_enable(rtwdev); 3575 rtw89_dispatcher_imr_enable(rtwdev); 3576 rtw89_cpuio_imr_enable(rtwdev); 3577 rtw89_bbrpt_imr_enable(rtwdev); 3578 } else if (sel == RTW89_CMAC_SEL) { 3579 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3580 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3581 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3582 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3583 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3584 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3585 } else { 3586 return -EINVAL; 3587 } 3588 3589 return 0; 3590 } 3591 3592 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3593 { 3594 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3595 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3596 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3597 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3598 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta) 3599 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3600 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3601 } 3602 3603 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3604 { 3605 int ret = 0; 3606 3607 if (enable) { 3608 ret = band1_enable_ax(rtwdev); 3609 if (ret) { 3610 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3611 return ret; 3612 } 3613 3614 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3615 if (ret) { 3616 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3617 return ret; 3618 } 3619 } else { 3620 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3621 return -EINVAL; 3622 } 3623 3624 return 0; 3625 } 3626 3627 static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3628 { 3629 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3630 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3631 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3632 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3633 B_AX_RLSRPT0_FLTR_MAP_MASK); 3634 } else { 3635 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3636 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3637 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3638 B_AX_RLSRPT0_FLTR_MAP_MASK); 3639 } 3640 3641 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3642 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3643 3644 return 0; 3645 } 3646 3647 static int trx_init_ax(struct rtw89_dev *rtwdev) 3648 { 3649 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3650 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3651 int ret; 3652 3653 ret = dmac_init_ax(rtwdev, 0); 3654 if (ret) { 3655 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3656 return ret; 3657 } 3658 3659 ret = cmac_init_ax(rtwdev, 0); 3660 if (ret) { 3661 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3662 return ret; 3663 } 3664 3665 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3666 ret = dbcc_enable_ax(rtwdev, true); 3667 if (ret) { 3668 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3669 return ret; 3670 } 3671 } 3672 3673 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3674 if (ret) { 3675 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3676 return ret; 3677 } 3678 3679 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3680 if (ret) { 3681 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3682 return ret; 3683 } 3684 3685 err_imr_ctrl_ax(rtwdev, true); 3686 3687 ret = set_host_rpr_ax(rtwdev); 3688 if (ret) { 3689 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3690 return ret; 3691 } 3692 3693 if (chip_id == RTL8852C) 3694 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG, 3695 B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN); 3696 3697 return 0; 3698 } 3699 3700 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 3701 { 3702 #define BACAM_1024BMP_OCC_ENTRY 4 3703 #define BACAM_MAX_RU_SUPPORT_B0_STA 1 3704 #define BACAM_MAX_RU_SUPPORT_B1_STA 1 3705 const struct rtw89_chip_info *chip = rtwdev->chip; 3706 u8 users, offset; 3707 3708 if (chip->bacam_ver != RTW89_BACAM_V1) 3709 return 0; 3710 3711 offset = 0; 3712 users = BACAM_MAX_RU_SUPPORT_B0_STA; 3713 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 3714 3715 offset += users * BACAM_1024BMP_OCC_ENTRY; 3716 users = BACAM_MAX_RU_SUPPORT_B1_STA; 3717 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 3718 3719 return 0; 3720 } 3721 3722 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3723 { 3724 u32 val32; 3725 3726 if (rtw89_is_rtl885xb(rtwdev)) { 3727 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3728 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3729 return; 3730 } 3731 3732 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3733 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3734 3735 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3736 val32 |= B_AX_FS_WDT_INT; 3737 val32 &= ~B_AX_FS_WDT_INT_MSK; 3738 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3739 } 3740 3741 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3742 { 3743 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3744 3745 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3746 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3747 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3748 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3749 3750 rtw89_disable_fw_watchdog(rtwdev); 3751 3752 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3753 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3754 } 3755 3756 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3757 bool dlfw, bool include_bb) 3758 { 3759 u32 val; 3760 int ret; 3761 3762 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3763 return -EFAULT; 3764 3765 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3766 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3767 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3768 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3769 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3770 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3771 3772 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3773 3774 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3775 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3776 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3777 B_AX_WCPU_FWDL_STS_MASK); 3778 3779 if (dlfw) 3780 val |= B_AX_WCPU_FWDL_EN; 3781 3782 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3783 3784 if (rtwdev->chip->chip_id == RTL8852B) 3785 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3786 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3787 3788 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3789 boot_reason); 3790 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3791 3792 if (!dlfw) { 3793 mdelay(5); 3794 3795 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3796 if (ret) 3797 return ret; 3798 } 3799 3800 return 0; 3801 } 3802 3803 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 3804 { 3805 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3806 u32 val; 3807 3808 if (chip_id == RTL8852C) 3809 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3810 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3811 else 3812 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3813 B_AX_PKT_BUF_EN; 3814 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3815 } 3816 3817 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 3818 { 3819 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3820 u32 val; 3821 3822 if (chip_id == RTL8851B || chip_id == RTL8852BT) 3823 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3824 else 3825 val = B_AX_DISPATCHER_CLK_EN; 3826 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3827 3828 if (chip_id != RTL8852C) 3829 return; 3830 3831 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3832 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3833 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3834 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3835 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3836 3837 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3838 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3839 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3840 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3841 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3842 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3843 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3844 } 3845 3846 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3847 { 3848 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3849 int ret; 3850 3851 mac->hci_func_en(rtwdev); 3852 mac->dmac_func_pre_en(rtwdev); 3853 3854 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3855 if (ret) { 3856 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3857 return ret; 3858 } 3859 3860 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 3861 if (ret) { 3862 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3863 return ret; 3864 } 3865 3866 return ret; 3867 } 3868 3869 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3870 { 3871 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3872 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3873 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3874 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3875 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3876 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3877 3878 return 0; 3879 } 3880 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3881 3882 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3883 { 3884 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3885 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3886 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3887 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3888 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3889 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3890 3891 return 0; 3892 } 3893 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3894 3895 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 3896 { 3897 int ret; 3898 3899 ret = rtw89_mac_power_switch(rtwdev, true); 3900 if (ret) { 3901 rtw89_mac_power_switch(rtwdev, false); 3902 ret = rtw89_mac_power_switch(rtwdev, true); 3903 if (ret) 3904 return ret; 3905 } 3906 3907 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3908 3909 if (include_bb) { 3910 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 3911 if (rtwdev->dbcc_en) 3912 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 3913 } 3914 3915 ret = rtw89_mac_dmac_pre_init(rtwdev); 3916 if (ret) 3917 return ret; 3918 3919 if (rtwdev->hci.ops->mac_pre_init) { 3920 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3921 if (ret) 3922 return ret; 3923 } 3924 3925 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 3926 if (ret) 3927 return ret; 3928 3929 return 0; 3930 } 3931 3932 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3933 { 3934 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3935 const struct rtw89_chip_info *chip = rtwdev->chip; 3936 bool include_bb = !!chip->bbmcu_nr; 3937 int ret; 3938 3939 ret = rtw89_mac_partial_init(rtwdev, include_bb); 3940 if (ret) 3941 goto fail; 3942 3943 ret = rtw89_chip_enable_bb_rf(rtwdev); 3944 if (ret) 3945 goto fail; 3946 3947 ret = mac->sys_init(rtwdev); 3948 if (ret) 3949 goto fail; 3950 3951 ret = mac->trx_init(rtwdev); 3952 if (ret) 3953 goto fail; 3954 3955 ret = rtw89_mac_feat_init(rtwdev); 3956 if (ret) 3957 goto fail; 3958 3959 if (rtwdev->hci.ops->mac_post_init) { 3960 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3961 if (ret) 3962 goto fail; 3963 } 3964 3965 rtw89_fw_send_all_early_h2c(rtwdev); 3966 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3967 3968 return ret; 3969 fail: 3970 rtw89_mac_power_switch(rtwdev, false); 3971 3972 return ret; 3973 } 3974 3975 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3976 { 3977 u8 i; 3978 3979 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 3980 return; 3981 3982 for (i = 0; i < 4; i++) { 3983 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3984 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3985 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3986 } 3987 } 3988 3989 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3990 { 3991 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 3992 return; 3993 3994 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3995 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3996 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3997 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3998 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3999 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 4000 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 4001 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 4002 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 4003 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 4004 } 4005 4006 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4007 { 4008 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4009 u8 grp = macid >> 5; 4010 int ret; 4011 4012 /* If this is called by change_interface() in the case of P2P, it could 4013 * be power-off, so ignore this operation. 4014 */ 4015 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4016 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4017 return 0; 4018 4019 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4020 if (ret) 4021 return ret; 4022 4023 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4024 4025 return 0; 4026 } 4027 4028 static const struct rtw89_port_reg rtw89_port_base_ax = { 4029 .port_cfg = R_AX_PORT_CFG_P0, 4030 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4031 .bcn_area = R_AX_BCN_AREA_P0, 4032 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4033 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4034 .tbtt_agg = R_AX_TBTT_AGG_P0, 4035 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4036 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4037 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4038 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4039 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4040 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4041 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4042 .tsftr_l = R_AX_TSFTR_LOW_P0, 4043 .tsftr_h = R_AX_TSFTR_HIGH_P0, 4044 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 4045 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4046 .mbssid = R_AX_MBSSID_CTRL, 4047 .mbssid_drop = R_AX_MBSSID_DROP_0, 4048 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4049 .ptcl_dbg = R_AX_PTCL_DBG, 4050 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4051 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4052 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4053 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4054 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4055 }; 4056 4057 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4058 struct rtw89_vif *rtwvif, u8 type) 4059 { 4060 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4061 const struct rtw89_port_reg *p = mac->port_base; 4062 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif->port); 4063 u32 reg_info, reg_ctrl; 4064 u32 val; 4065 int ret; 4066 4067 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif->mac_idx); 4068 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif->mac_idx); 4069 4070 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4071 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4072 fsleep(100); 4073 4074 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4075 true, rtwdev, reg_info, mask); 4076 if (ret) 4077 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4078 } 4079 4080 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4081 { 4082 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4083 const struct rtw89_port_reg *p = mac->port_base; 4084 4085 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif->port)); 4086 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 1); 4087 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 0); 4088 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 0); 4089 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4090 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK, 1); 4091 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 1); 4092 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4093 4094 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM0); 4095 if (rtwvif->port == RTW89_PORT_0) 4096 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM1); 4097 4098 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif->port)); 4099 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4100 fsleep(2000); 4101 } 4102 4103 #define BCN_INTERVAL 100 4104 #define BCN_ERLY_DEF 160 4105 #define BCN_SETUP_DEF 2 4106 #define BCN_HOLD_DEF 200 4107 #define BCN_MASK_DEF 0 4108 #define TBTT_ERLY_DEF 5 4109 #define BCN_SET_UNIT 32 4110 #define BCN_ERLY_SET_DLY (10 * 2) 4111 4112 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4113 struct rtw89_vif *rtwvif) 4114 { 4115 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4116 const struct rtw89_port_reg *p = mac->port_base; 4117 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4118 const struct rtw89_chip_info *chip = rtwdev->chip; 4119 bool need_backup = false; 4120 u32 backup_val; 4121 4122 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 4123 return; 4124 4125 if (chip->chip_id == RTL8852A && rtwvif->port != RTW89_PORT_0) { 4126 need_backup = true; 4127 backup_val = rtw89_read32_port(rtwdev, rtwvif, p->tbtt_prohib); 4128 } 4129 4130 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4131 rtw89_mac_bcn_drop(rtwdev, rtwvif); 4132 4133 if (chip->chip_id == RTL8852A) { 4134 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 4135 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 4136 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 4137 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 4138 } 4139 4140 msleep(vif->bss_conf.beacon_int + 1); 4141 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 4142 B_AX_BRK_SETUP); 4143 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 4144 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 4145 4146 if (need_backup) 4147 rtw89_write32_port(rtwdev, rtwvif, p->tbtt_prohib, backup_val); 4148 } 4149 4150 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4151 struct rtw89_vif *rtwvif, bool en) 4152 { 4153 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4154 const struct rtw89_port_reg *p = mac->port_base; 4155 4156 if (en) 4157 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4158 else 4159 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4160 } 4161 4162 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4163 struct rtw89_vif *rtwvif, bool en) 4164 { 4165 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4166 const struct rtw89_port_reg *p = mac->port_base; 4167 4168 if (en) 4169 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4170 else 4171 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4172 } 4173 4174 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4175 struct rtw89_vif *rtwvif) 4176 { 4177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4178 const struct rtw89_port_reg *p = mac->port_base; 4179 4180 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 4181 rtwvif->net_type); 4182 } 4183 4184 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4185 struct rtw89_vif *rtwvif) 4186 { 4187 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4188 const struct rtw89_port_reg *p = mac->port_base; 4189 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 4190 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4191 4192 if (en) 4193 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 4194 else 4195 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 4196 } 4197 4198 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4199 struct rtw89_vif *rtwvif) 4200 { 4201 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4202 const struct rtw89_port_reg *p = mac->port_base; 4203 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4204 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4205 u32 bit = B_AX_RX_BSSID_FIT_EN; 4206 4207 if (en) 4208 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 4209 else 4210 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 4211 } 4212 4213 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4214 struct rtw89_vif *rtwvif, bool en) 4215 { 4216 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4217 const struct rtw89_port_reg *p = mac->port_base; 4218 4219 if (en) 4220 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4221 else 4222 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4223 } 4224 4225 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4226 struct rtw89_vif *rtwvif) 4227 { 4228 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4229 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4230 4231 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif, en); 4232 } 4233 4234 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4235 struct rtw89_vif *rtwvif, bool en) 4236 { 4237 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4238 const struct rtw89_port_reg *p = mac->port_base; 4239 4240 if (en) 4241 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4242 else 4243 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4244 } 4245 4246 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4247 struct rtw89_vif *rtwvif) 4248 { 4249 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 4250 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4251 4252 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4253 } 4254 4255 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4256 { 4257 struct rtw89_vif *rtwvif; 4258 4259 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4260 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4261 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4262 } 4263 4264 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4265 struct rtw89_vif *rtwvif) 4266 { 4267 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4268 const struct rtw89_port_reg *p = mac->port_base; 4269 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4270 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 4271 4272 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 4273 bcn_int); 4274 } 4275 4276 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4277 struct rtw89_vif *rtwvif) 4278 { 4279 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4280 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4281 const struct rtw89_port_reg *p = mac->port_base; 4282 u8 port = rtwvif->port; 4283 u32 reg; 4284 4285 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif->mac_idx); 4286 rtw89_write8(rtwdev, reg, win); 4287 } 4288 4289 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4290 struct rtw89_vif *rtwvif) 4291 { 4292 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4293 const struct rtw89_port_reg *p = mac->port_base; 4294 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4295 u32 addr; 4296 4297 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif->mac_idx); 4298 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4299 4300 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4301 vif->bss_conf.dtim_period); 4302 } 4303 4304 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4305 struct rtw89_vif *rtwvif) 4306 { 4307 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4308 const struct rtw89_port_reg *p = mac->port_base; 4309 4310 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4311 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4312 } 4313 4314 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4315 struct rtw89_vif *rtwvif) 4316 { 4317 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4318 const struct rtw89_port_reg *p = mac->port_base; 4319 4320 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4321 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4322 } 4323 4324 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4325 struct rtw89_vif *rtwvif) 4326 { 4327 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4328 const struct rtw89_port_reg *p = mac->port_base; 4329 4330 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 4331 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4332 } 4333 4334 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4335 struct rtw89_vif *rtwvif) 4336 { 4337 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4338 const struct rtw89_port_reg *p = mac->port_base; 4339 4340 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 4341 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4342 } 4343 4344 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4345 struct rtw89_vif *rtwvif) 4346 { 4347 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4348 const struct rtw89_port_reg *p = mac->port_base; 4349 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4350 static const u32 masks[RTW89_PORT_NUM] = { 4351 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4352 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4353 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4354 }; 4355 u8 port = rtwvif->port; 4356 u32 reg_base; 4357 u32 reg; 4358 u8 bss_color; 4359 4360 bss_color = vif->bss_conf.he_bss_color.color; 4361 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4362 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx); 4363 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4364 } 4365 4366 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4367 struct rtw89_vif *rtwvif) 4368 { 4369 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4370 const struct rtw89_port_reg *p = mac->port_base; 4371 u8 port = rtwvif->port; 4372 u32 reg; 4373 4374 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4375 return; 4376 4377 if (port == 0) { 4378 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif->mac_idx); 4379 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4380 } 4381 } 4382 4383 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4384 struct rtw89_vif *rtwvif) 4385 { 4386 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4387 const struct rtw89_port_reg *p = mac->port_base; 4388 u8 port = rtwvif->port; 4389 u32 reg; 4390 u32 val; 4391 4392 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif->mac_idx); 4393 val = rtw89_read32(rtwdev, reg); 4394 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4395 if (port == 0) 4396 val &= ~BIT(0); 4397 rtw89_write32(rtwdev, reg, val); 4398 } 4399 4400 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4401 struct rtw89_vif *rtwvif, bool enable) 4402 { 4403 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4404 const struct rtw89_port_reg *p = mac->port_base; 4405 4406 if (enable) 4407 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 4408 B_AX_PORT_FUNC_EN); 4409 else 4410 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 4411 B_AX_PORT_FUNC_EN); 4412 } 4413 4414 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4415 struct rtw89_vif *rtwvif) 4416 { 4417 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4418 const struct rtw89_port_reg *p = mac->port_base; 4419 4420 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 4421 BCN_ERLY_DEF); 4422 } 4423 4424 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4425 struct rtw89_vif *rtwvif) 4426 { 4427 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4428 const struct rtw89_port_reg *p = mac->port_base; 4429 u16 val; 4430 4431 if (rtwdev->chip->chip_id != RTL8852C) 4432 return; 4433 4434 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4435 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4436 return; 4437 4438 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4439 B_AX_TBTT_SHIFT_OFST_SIGN; 4440 4441 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 4442 B_AX_TBTT_SHIFT_OFST_MASK, val); 4443 } 4444 4445 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4446 struct rtw89_vif *rtwvif, 4447 struct rtw89_vif *rtwvif_src, 4448 u16 offset_tu) 4449 { 4450 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4451 const struct rtw89_port_reg *p = mac->port_base; 4452 u32 val, reg; 4453 4454 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4455 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif->port * 4, 4456 rtwvif->mac_idx); 4457 4458 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4459 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4460 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4461 } 4462 4463 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4464 struct rtw89_vif *rtwvif, 4465 struct rtw89_vif *rtwvif_src, 4466 u8 offset, int *n_offset) 4467 { 4468 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 4469 return; 4470 4471 /* adjust offset randomly to avoid beacon conflict */ 4472 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4473 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 4474 (*n_offset) * offset); 4475 4476 (*n_offset)++; 4477 } 4478 4479 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4480 { 4481 struct rtw89_vif *src = NULL, *tmp; 4482 u8 offset = 100, vif_aps = 0; 4483 int n_offset = 1; 4484 4485 rtw89_for_each_rtwvif(rtwdev, tmp) { 4486 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4487 src = tmp; 4488 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4489 vif_aps++; 4490 } 4491 4492 if (vif_aps == 0) 4493 return; 4494 4495 offset /= (vif_aps + 1); 4496 4497 rtw89_for_each_rtwvif(rtwdev, tmp) 4498 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4499 } 4500 4501 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4502 { 4503 int ret; 4504 4505 ret = rtw89_mac_port_update(rtwdev, rtwvif); 4506 if (ret) 4507 return ret; 4508 4509 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4510 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4511 4512 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4513 if (ret) 4514 return ret; 4515 4516 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4517 if (ret) 4518 return ret; 4519 4520 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4521 if (ret) 4522 return ret; 4523 4524 ret = rtw89_cam_init(rtwdev, rtwvif); 4525 if (ret) 4526 return ret; 4527 4528 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4529 if (ret) 4530 return ret; 4531 4532 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, NULL); 4533 if (ret) 4534 return ret; 4535 4536 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, NULL); 4537 if (ret) 4538 return ret; 4539 4540 return 0; 4541 } 4542 4543 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4544 { 4545 int ret; 4546 4547 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4548 if (ret) 4549 return ret; 4550 4551 rtw89_cam_deinit(rtwdev, rtwvif); 4552 4553 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4554 if (ret) 4555 return ret; 4556 4557 return 0; 4558 } 4559 4560 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4561 { 4562 u8 port = rtwvif->port; 4563 4564 if (port >= RTW89_PORT_NUM) 4565 return -EINVAL; 4566 4567 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4568 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4569 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4570 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4571 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4572 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4573 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif); 4574 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif); 4575 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4576 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4577 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4578 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4579 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4580 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4581 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4582 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4583 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4584 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4585 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4586 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4587 rtw89_mac_port_tsf_resync_all(rtwdev); 4588 fsleep(BCN_ERLY_SET_DLY); 4589 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4590 4591 return 0; 4592 } 4593 4594 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4595 u64 *tsf) 4596 { 4597 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4598 const struct rtw89_port_reg *p = mac->port_base; 4599 u32 tsf_low, tsf_high; 4600 int ret; 4601 4602 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 4603 if (ret) 4604 return ret; 4605 4606 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 4607 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 4608 *tsf = (u64)tsf_high << 32 | tsf_low; 4609 4610 return 0; 4611 } 4612 4613 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4614 struct cfg80211_bss *bss, 4615 void *data) 4616 { 4617 const struct cfg80211_bss_ies *ies; 4618 const struct element *elem; 4619 bool *tolerated = data; 4620 4621 rcu_read_lock(); 4622 ies = rcu_dereference(bss->ies); 4623 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4624 ies->len); 4625 4626 if (!elem || elem->datalen < 10 || 4627 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4628 *tolerated = false; 4629 rcu_read_unlock(); 4630 } 4631 4632 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4633 struct ieee80211_vif *vif) 4634 { 4635 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4636 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4637 struct ieee80211_hw *hw = rtwdev->hw; 4638 bool tolerated = true; 4639 u32 reg; 4640 4641 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 4642 return; 4643 4644 if (!(vif->bss_conf.chanreq.oper.chan->flags & IEEE80211_CHAN_RADAR)) 4645 return; 4646 4647 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chanreq.oper, 4648 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4649 &tolerated); 4650 4651 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 4652 rtwvif->mac_idx); 4653 if (tolerated) 4654 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4655 else 4656 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4657 } 4658 4659 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4660 { 4661 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4662 } 4663 4664 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4665 { 4666 int ret; 4667 4668 rtwvif->mac_id = rtw89_acquire_mac_id(rtwdev); 4669 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4670 return -ENOSPC; 4671 4672 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4673 if (ret) 4674 goto release_mac_id; 4675 4676 return 0; 4677 4678 release_mac_id: 4679 rtw89_release_mac_id(rtwdev, rtwvif->mac_id); 4680 4681 return ret; 4682 } 4683 4684 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4685 { 4686 int ret; 4687 4688 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4689 rtw89_release_mac_id(rtwdev, rtwvif->mac_id); 4690 4691 return ret; 4692 } 4693 4694 static void 4695 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4696 { 4697 } 4698 4699 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4700 { 4701 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4702 4703 return band == op->band_type && channel == op->primary_channel; 4704 } 4705 4706 static void 4707 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4708 u32 len) 4709 { 4710 const struct rtw89_c2h_scanofld *c2h = 4711 (const struct rtw89_c2h_scanofld *)skb->data; 4712 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4713 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4714 struct rtw89_chan new; 4715 u8 reason, status, tx_fail, band, actual_period, expect_period; 4716 u32 last_chan = rtwdev->scan_info.last_chan_idx, report_tsf; 4717 u8 mac_idx, sw_def, fw_def; 4718 u16 chan; 4719 int ret; 4720 4721 if (!rtwvif) 4722 return; 4723 4724 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 4725 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 4726 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 4727 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 4728 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 4729 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 4730 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 4731 4732 4733 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4734 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4735 4736 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4737 "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4738 mac_idx, band, chan, reason, status, tx_fail, actual_period); 4739 4740 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4741 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 4742 expect_period = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 4743 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 4744 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 4745 4746 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4747 "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 4748 sw_def, fw_def, report_tsf, expect_period); 4749 } 4750 4751 switch (reason) { 4752 case RTW89_SCAN_LEAVE_OP_NOTIFY: 4753 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4754 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4755 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, false); 4756 ieee80211_stop_queues(rtwdev->hw); 4757 } 4758 return; 4759 case RTW89_SCAN_END_SCAN_NOTIFY: 4760 if (rtwdev->scan_info.abort) 4761 return; 4762 4763 if (rtwvif && rtwvif->scan_req && 4764 last_chan < rtwvif->scan_req->n_channels) { 4765 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4766 if (ret) { 4767 rtw89_hw_scan_abort(rtwdev, vif); 4768 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4769 } 4770 } else { 4771 rtw89_hw_scan_complete(rtwdev, vif, false); 4772 } 4773 break; 4774 case RTW89_SCAN_ENTER_OP_NOTIFY: 4775 case RTW89_SCAN_ENTER_CH_NOTIFY: 4776 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4777 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4778 &rtwdev->scan_info.op_chan); 4779 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, true); 4780 ieee80211_wake_queues(rtwdev->hw); 4781 } else { 4782 rtw89_chan_create(&new, chan, chan, band, 4783 RTW89_CHANNEL_WIDTH_20); 4784 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4785 &new); 4786 } 4787 break; 4788 default: 4789 return; 4790 } 4791 } 4792 4793 static void 4794 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4795 struct sk_buff *skb) 4796 { 4797 struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4798 enum nl80211_cqm_rssi_threshold_event nl_event; 4799 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4800 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4801 u8 type, event, mac_id; 4802 s8 sig; 4803 4804 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4805 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4806 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4807 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4808 4809 if (mac_id != rtwvif->mac_id) 4810 return; 4811 4812 rtw89_debug(rtwdev, RTW89_DBG_FW, 4813 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4814 mac_id, type, sig, event); 4815 4816 switch (type) { 4817 case RTW89_BCN_FLTR_BEACON_LOSS: 4818 if (!rtwdev->scanning && !rtwvif->offchan) 4819 ieee80211_connection_loss(vif); 4820 else 4821 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4822 return; 4823 case RTW89_BCN_FLTR_NOTIFY: 4824 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4825 break; 4826 case RTW89_BCN_FLTR_RSSI: 4827 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4828 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4829 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4830 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4831 else 4832 return; 4833 break; 4834 default: 4835 return; 4836 } 4837 4838 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4839 } 4840 4841 static void 4842 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4843 u32 len) 4844 { 4845 struct rtw89_vif *rtwvif; 4846 4847 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4848 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4849 } 4850 4851 static void 4852 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4853 { 4854 /* N.B. This will run in interrupt context. */ 4855 4856 rtw89_debug(rtwdev, RTW89_DBG_FW, 4857 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4858 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4859 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4860 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4861 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4862 } 4863 4864 static void 4865 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4866 { 4867 /* N.B. This will run in interrupt context. */ 4868 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4869 const struct rtw89_c2h_done_ack *c2h = 4870 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4871 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4872 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4873 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4874 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4875 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4876 struct rtw89_completion_data data = {}; 4877 unsigned int cond; 4878 4879 rtw89_debug(rtwdev, RTW89_DBG_FW, 4880 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4881 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4882 4883 if (h2c_cat != H2C_CAT_MAC) 4884 return; 4885 4886 switch (h2c_class) { 4887 default: 4888 return; 4889 case H2C_CL_MAC_FW_OFLD: 4890 switch (h2c_func) { 4891 default: 4892 return; 4893 case H2C_FUNC_ADD_SCANOFLD_CH: 4894 cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 4895 break; 4896 case H2C_FUNC_SCANOFLD: 4897 cond = RTW89_SCANOFLD_WAIT_COND_START; 4898 break; 4899 case H2C_FUNC_SCANOFLD_BE: 4900 cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 4901 break; 4902 } 4903 4904 data.err = !!h2c_return; 4905 rtw89_complete_cond(fw_ofld_wait, cond, &data); 4906 return; 4907 } 4908 } 4909 4910 static void 4911 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4912 { 4913 rtw89_fw_log_dump(rtwdev, c2h->data, len); 4914 } 4915 4916 static void 4917 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4918 { 4919 } 4920 4921 static void 4922 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 4923 u32 len) 4924 { 4925 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 4926 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 4927 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 4928 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 4929 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 4930 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 4931 struct rtw89_completion_data data = {}; 4932 unsigned int cond; 4933 4934 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 4935 pkt_id, pkt_op, pkt_len); 4936 4937 data.err = !pkt_len; 4938 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 4939 4940 rtw89_complete_cond(wait, cond, &data); 4941 } 4942 4943 static void 4944 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4945 u32 len) 4946 { 4947 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 4948 } 4949 4950 static void 4951 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4952 { 4953 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4954 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4955 4956 switch (func) { 4957 case H2C_FUNC_ADD_MCC: 4958 case H2C_FUNC_START_MCC: 4959 case H2C_FUNC_STOP_MCC: 4960 case H2C_FUNC_DEL_MCC_GROUP: 4961 case H2C_FUNC_RESET_MCC_GROUP: 4962 case H2C_FUNC_MCC_REQ_TSF: 4963 case H2C_FUNC_MCC_MACID_BITMAP: 4964 case H2C_FUNC_MCC_SYNC: 4965 case H2C_FUNC_MCC_SET_DURATION: 4966 break; 4967 default: 4968 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4969 "invalid MCC C2H RCV ACK: func %d\n", func); 4970 return; 4971 } 4972 4973 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4974 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4975 } 4976 4977 static void 4978 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4979 { 4980 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4981 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4982 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4983 struct rtw89_completion_data data = {}; 4984 unsigned int cond; 4985 bool next = false; 4986 4987 switch (func) { 4988 case H2C_FUNC_MCC_REQ_TSF: 4989 next = true; 4990 break; 4991 case H2C_FUNC_MCC_MACID_BITMAP: 4992 case H2C_FUNC_MCC_SYNC: 4993 case H2C_FUNC_MCC_SET_DURATION: 4994 break; 4995 case H2C_FUNC_ADD_MCC: 4996 case H2C_FUNC_START_MCC: 4997 case H2C_FUNC_STOP_MCC: 4998 case H2C_FUNC_DEL_MCC_GROUP: 4999 case H2C_FUNC_RESET_MCC_GROUP: 5000 default: 5001 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5002 "invalid MCC C2H REQ ACK: func %d\n", func); 5003 return; 5004 } 5005 5006 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5007 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5008 group, func, retcode); 5009 5010 if (!retcode && next) 5011 return; 5012 5013 data.err = !!retcode; 5014 cond = RTW89_MCC_WAIT_COND(group, func); 5015 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5016 } 5017 5018 static void 5019 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5020 { 5021 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5022 struct rtw89_completion_data data = {}; 5023 struct rtw89_mac_mcc_tsf_rpt *rpt; 5024 unsigned int cond; 5025 5026 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5027 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5028 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5029 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5030 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5031 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5032 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5033 5034 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5035 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5036 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5037 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5038 5039 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5040 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5041 } 5042 5043 static void 5044 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5045 { 5046 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5047 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5048 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5049 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5050 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5051 struct rtw89_completion_data data = {}; 5052 unsigned int cond; 5053 bool rsp = true; 5054 bool err; 5055 u8 func; 5056 5057 switch (status) { 5058 case RTW89_MAC_MCC_ADD_ROLE_OK: 5059 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5060 func = H2C_FUNC_ADD_MCC; 5061 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5062 break; 5063 case RTW89_MAC_MCC_START_GROUP_OK: 5064 case RTW89_MAC_MCC_START_GROUP_FAIL: 5065 func = H2C_FUNC_START_MCC; 5066 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5067 break; 5068 case RTW89_MAC_MCC_STOP_GROUP_OK: 5069 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5070 func = H2C_FUNC_STOP_MCC; 5071 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5072 break; 5073 case RTW89_MAC_MCC_DEL_GROUP_OK: 5074 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5075 func = H2C_FUNC_DEL_MCC_GROUP; 5076 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5077 break; 5078 case RTW89_MAC_MCC_RESET_GROUP_OK: 5079 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5080 func = H2C_FUNC_RESET_MCC_GROUP; 5081 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5082 break; 5083 case RTW89_MAC_MCC_SWITCH_CH_OK: 5084 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5085 case RTW89_MAC_MCC_TXNULL0_OK: 5086 case RTW89_MAC_MCC_TXNULL0_FAIL: 5087 case RTW89_MAC_MCC_TXNULL1_OK: 5088 case RTW89_MAC_MCC_TXNULL1_FAIL: 5089 case RTW89_MAC_MCC_SWITCH_EARLY: 5090 case RTW89_MAC_MCC_TBTT: 5091 case RTW89_MAC_MCC_DURATION_START: 5092 case RTW89_MAC_MCC_DURATION_END: 5093 rsp = false; 5094 break; 5095 default: 5096 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5097 "invalid MCC C2H STS RPT: status %d\n", status); 5098 return; 5099 } 5100 5101 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5102 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5103 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5104 5105 if (!rsp) 5106 return; 5107 5108 data.err = err; 5109 cond = RTW89_MCC_WAIT_COND(group, func); 5110 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5111 } 5112 5113 static void 5114 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5115 { 5116 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5117 const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5118 struct rtw89_completion_data data = {}; 5119 struct rtw89_mac_mrc_tsf_rpt *rpt; 5120 unsigned int i; 5121 5122 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5123 rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5124 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5125 le32_get_bits(c2h_rpt->w2, 5126 RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5127 5128 for (i = 0; i < rpt->num; i++) { 5129 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5130 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5131 5132 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5133 5134 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5135 "MRC C2H TSF RPT: index %u> %llu\n", 5136 i, rpt->tsfs[i]); 5137 } 5138 5139 rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5140 } 5141 5142 static void 5143 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5144 { 5145 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 5146 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 5147 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 5148 const struct rtw89_c2h_wow_aoac_report *c2h = 5149 (const struct rtw89_c2h_wow_aoac_report *)skb->data; 5150 struct rtw89_completion_data data = {}; 5151 unsigned int cond; 5152 5153 aoac_rpt->rpt_ver = c2h->rpt_ver; 5154 aoac_rpt->sec_type = c2h->sec_type; 5155 aoac_rpt->key_idx = c2h->key_idx; 5156 aoac_rpt->pattern_idx = c2h->pattern_idx; 5157 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok, 5158 RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX); 5159 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv)); 5160 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count, 5161 sizeof(aoac_rpt->eapol_key_replay_count)); 5162 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk)); 5163 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv)); 5164 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv)); 5165 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id); 5166 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn); 5167 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk)); 5168 5169 cond = RTW89_WOW_WAIT_COND(H2C_FUNC_AOAC_REPORT_REQ); 5170 rtw89_complete_cond(wait, cond, &data); 5171 } 5172 5173 static void 5174 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5175 { 5176 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5177 const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5178 struct rtw89_completion_data data = {}; 5179 enum rtw89_mac_mrc_status status; 5180 unsigned int cond; 5181 bool next = false; 5182 u32 tsf_high; 5183 u32 tsf_low; 5184 u8 sch_idx; 5185 u8 func; 5186 5187 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5188 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5189 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5190 tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5191 tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5192 5193 switch (status) { 5194 case RTW89_MAC_MRC_START_SCH_OK: 5195 func = H2C_FUNC_START_MRC; 5196 break; 5197 case RTW89_MAC_MRC_STOP_SCH_OK: 5198 /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5199 func = H2C_FUNC_DEL_MRC; 5200 next = true; 5201 break; 5202 case RTW89_MAC_MRC_DEL_SCH_OK: 5203 func = H2C_FUNC_DEL_MRC; 5204 break; 5205 case RTW89_MAC_MRC_EMPTY_SCH_FAIL: 5206 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5207 "MRC C2H STS RPT: empty sch fail\n"); 5208 return; 5209 case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL: 5210 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5211 "MRC C2H STS RPT: role not exist fail\n"); 5212 return; 5213 case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL: 5214 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5215 "MRC C2H STS RPT: data not found fail\n"); 5216 return; 5217 case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL: 5218 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5219 "MRC C2H STS RPT: get next slot fail\n"); 5220 return; 5221 case RTW89_MAC_MRC_ALT_ROLE_FAIL: 5222 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5223 "MRC C2H STS RPT: alt role fail\n"); 5224 return; 5225 case RTW89_MAC_MRC_ADD_PSTIMER_FAIL: 5226 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5227 "MRC C2H STS RPT: add ps timer fail\n"); 5228 return; 5229 case RTW89_MAC_MRC_MALLOC_FAIL: 5230 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5231 "MRC C2H STS RPT: malloc fail\n"); 5232 return; 5233 case RTW89_MAC_MRC_SWITCH_CH_FAIL: 5234 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5235 "MRC C2H STS RPT: switch ch fail\n"); 5236 return; 5237 case RTW89_MAC_MRC_TXNULL0_FAIL: 5238 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5239 "MRC C2H STS RPT: tx null-0 fail\n"); 5240 return; 5241 case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL: 5242 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5243 "MRC C2H STS RPT: port func en fail\n"); 5244 return; 5245 default: 5246 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5247 "invalid MRC C2H STS RPT: status %d\n", status); 5248 return; 5249 } 5250 5251 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5252 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 5253 sch_idx, status, (u64)tsf_high << 32 | tsf_low); 5254 5255 if (next) 5256 return; 5257 5258 cond = RTW89_MRC_WAIT_COND(sch_idx, func); 5259 rtw89_complete_cond(wait, cond, &data); 5260 } 5261 5262 static 5263 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5264 struct sk_buff *c2h, u32 len) = { 5265 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5266 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5267 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5268 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 5269 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5270 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5271 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5272 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5273 }; 5274 5275 static 5276 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5277 struct sk_buff *c2h, u32 len) = { 5278 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5279 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5280 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5281 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5282 }; 5283 5284 static 5285 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5286 struct sk_buff *c2h, u32 len) = { 5287 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5288 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5289 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5290 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5291 }; 5292 5293 static 5294 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 5295 struct sk_buff *c2h, u32 len) = { 5296 [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 5297 [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 5298 }; 5299 5300 static 5301 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev, 5302 struct sk_buff *c2h, u32 len) = { 5303 [RTW89_MAC_C2H_FUNC_AOAC_REPORT] = rtw89_mac_c2h_wow_aoac_rpt, 5304 }; 5305 5306 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 5307 struct sk_buff *skb) 5308 { 5309 const struct rtw89_c2h_scanofld *c2h = 5310 (const struct rtw89_c2h_scanofld *)skb->data; 5311 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5312 struct rtw89_completion_data data = {}; 5313 unsigned int cond; 5314 u8 status, reason; 5315 5316 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5317 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5318 data.err = status != RTW89_SCAN_STATUS_SUCCESS; 5319 5320 if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 5321 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 5322 cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 5323 else 5324 cond = RTW89_SCANOFLD_WAIT_COND_STOP; 5325 5326 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5327 } 5328 } 5329 5330 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5331 u8 class, u8 func) 5332 { 5333 switch (class) { 5334 default: 5335 return false; 5336 case RTW89_MAC_C2H_CLASS_INFO: 5337 switch (func) { 5338 default: 5339 return false; 5340 case RTW89_MAC_C2H_FUNC_REC_ACK: 5341 case RTW89_MAC_C2H_FUNC_DONE_ACK: 5342 return true; 5343 } 5344 case RTW89_MAC_C2H_CLASS_OFLD: 5345 switch (func) { 5346 default: 5347 return false; 5348 case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 5349 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 5350 return false; 5351 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 5352 return true; 5353 } 5354 case RTW89_MAC_C2H_CLASS_MCC: 5355 return true; 5356 case RTW89_MAC_C2H_CLASS_MRC: 5357 return true; 5358 case RTW89_MAC_C2H_CLASS_WOW: 5359 return true; 5360 } 5361 } 5362 5363 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5364 u32 len, u8 class, u8 func) 5365 { 5366 void (*handler)(struct rtw89_dev *rtwdev, 5367 struct sk_buff *c2h, u32 len) = NULL; 5368 5369 switch (class) { 5370 case RTW89_MAC_C2H_CLASS_INFO: 5371 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 5372 handler = rtw89_mac_c2h_info_handler[func]; 5373 break; 5374 case RTW89_MAC_C2H_CLASS_OFLD: 5375 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 5376 handler = rtw89_mac_c2h_ofld_handler[func]; 5377 break; 5378 case RTW89_MAC_C2H_CLASS_MCC: 5379 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 5380 handler = rtw89_mac_c2h_mcc_handler[func]; 5381 break; 5382 case RTW89_MAC_C2H_CLASS_MRC: 5383 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 5384 handler = rtw89_mac_c2h_mrc_handler[func]; 5385 break; 5386 case RTW89_MAC_C2H_CLASS_WOW: 5387 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_WOW) 5388 handler = rtw89_mac_c2h_wow_handler[func]; 5389 break; 5390 case RTW89_MAC_C2H_CLASS_FWDBG: 5391 return; 5392 default: 5393 rtw89_info(rtwdev, "c2h class %d not support\n", class); 5394 return; 5395 } 5396 if (!handler) { 5397 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 5398 func); 5399 return; 5400 } 5401 handler(rtwdev, skb, len); 5402 } 5403 5404 static 5405 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 5406 enum rtw89_phy_idx phy_idx, 5407 u32 reg_base, u32 *cr) 5408 { 5409 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 5410 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 5411 5412 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 5413 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 5414 addr); 5415 goto error; 5416 } 5417 5418 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 5419 if (mode == RTW89_QTA_SCC) { 5420 rtw89_err(rtwdev, 5421 "[TXPWR] addr=0x%x but hw not enable\n", 5422 addr); 5423 goto error; 5424 } 5425 5426 *cr = addr; 5427 return true; 5428 5429 error: 5430 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 5431 addr, phy_idx); 5432 5433 return false; 5434 } 5435 5436 static 5437 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 5438 { 5439 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 5440 int ret; 5441 5442 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5443 if (ret) 5444 return ret; 5445 5446 if (!enable) { 5447 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 5448 return 0; 5449 } 5450 5451 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 5452 B_AX_APP_MAC_INFO_RPT | 5453 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 5454 B_AX_PPDU_STAT_RPT_CRC32); 5455 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 5456 RTW89_PRPT_DEST_HOST); 5457 5458 return 0; 5459 } 5460 5461 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 5462 { 5463 #define MAC_AX_TIME_TH_SH 5 5464 #define MAC_AX_LEN_TH_SH 4 5465 #define MAC_AX_TIME_TH_MAX 255 5466 #define MAC_AX_LEN_TH_MAX 255 5467 #define MAC_AX_TIME_TH_DEF 88 5468 #define MAC_AX_LEN_TH_DEF 4080 5469 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5470 struct ieee80211_hw *hw = rtwdev->hw; 5471 u32 rts_threshold = hw->wiphy->rts_threshold; 5472 u32 time_th, len_th; 5473 u32 reg; 5474 5475 if (rts_threshold == (u32)-1) { 5476 time_th = MAC_AX_TIME_TH_DEF; 5477 len_th = MAC_AX_LEN_TH_DEF; 5478 } else { 5479 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 5480 len_th = rts_threshold; 5481 } 5482 5483 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 5484 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 5485 5486 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 5487 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 5488 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 5489 } 5490 5491 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 5492 { 5493 bool empty; 5494 int ret; 5495 5496 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5497 return; 5498 5499 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 5500 10000, 200000, false, rtwdev); 5501 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 5502 rtw89_info(rtwdev, "timed out to flush queues\n"); 5503 } 5504 5505 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 5506 { 5507 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 5508 u8 val; 5509 u16 val16; 5510 u32 val32; 5511 int ret; 5512 5513 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 5514 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5515 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 5516 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 5517 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 5518 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 5519 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5520 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 5521 5522 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 5523 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 5524 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 5525 5526 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 5527 if (ret) { 5528 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 5529 return ret; 5530 } 5531 val32 = val32 & B_AX_WL_RX_CTRL; 5532 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 5533 if (ret) { 5534 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 5535 return ret; 5536 } 5537 5538 switch (coex->pta_mode) { 5539 case RTW89_MAC_AX_COEX_RTK_MODE: 5540 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5541 val &= ~B_AX_BTMODE_MASK; 5542 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 5543 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5544 5545 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 5546 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 5547 5548 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 5549 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 5550 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 5551 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 5552 break; 5553 case RTW89_MAC_AX_COEX_CSR_MODE: 5554 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5555 val &= ~B_AX_BTMODE_MASK; 5556 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 5557 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5558 5559 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 5560 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 5561 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 5562 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 5563 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 5564 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 5565 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 5566 val16 |= B_AX_ENHANCED_BT; 5567 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 5568 5569 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 5570 break; 5571 default: 5572 return -EINVAL; 5573 } 5574 5575 switch (coex->direction) { 5576 case RTW89_MAC_AX_COEX_INNER: 5577 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5578 val = (val & ~BIT(2)) | BIT(1); 5579 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5580 break; 5581 case RTW89_MAC_AX_COEX_OUTPUT: 5582 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5583 val = val | BIT(1) | BIT(0); 5584 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5585 break; 5586 case RTW89_MAC_AX_COEX_INPUT: 5587 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5588 val = val & ~(BIT(2) | BIT(1)); 5589 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5590 break; 5591 default: 5592 return -EINVAL; 5593 } 5594 5595 return 0; 5596 } 5597 EXPORT_SYMBOL(rtw89_mac_coex_init); 5598 5599 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 5600 const struct rtw89_mac_ax_coex *coex) 5601 { 5602 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 5603 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 5604 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 5605 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 5606 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 5607 5608 switch (coex->pta_mode) { 5609 case RTW89_MAC_AX_COEX_RTK_MODE: 5610 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5611 MAC_AX_RTK_MODE); 5612 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 5613 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 5614 break; 5615 case RTW89_MAC_AX_COEX_CSR_MODE: 5616 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5617 MAC_AX_CSR_MODE); 5618 break; 5619 default: 5620 return -EINVAL; 5621 } 5622 5623 return 0; 5624 } 5625 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 5626 5627 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5628 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5629 { 5630 u32 val = 0, ret; 5631 5632 if (gnt_cfg->band[0].gnt_bt) 5633 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 5634 5635 if (gnt_cfg->band[0].gnt_bt_sw_en) 5636 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 5637 5638 if (gnt_cfg->band[0].gnt_wl) 5639 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 5640 5641 if (gnt_cfg->band[0].gnt_wl_sw_en) 5642 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 5643 5644 if (gnt_cfg->band[1].gnt_bt) 5645 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 5646 5647 if (gnt_cfg->band[1].gnt_bt_sw_en) 5648 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 5649 5650 if (gnt_cfg->band[1].gnt_wl) 5651 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 5652 5653 if (gnt_cfg->band[1].gnt_wl_sw_en) 5654 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 5655 5656 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 5657 if (ret) { 5658 rtw89_err(rtwdev, "Write LTE fail!\n"); 5659 return ret; 5660 } 5661 5662 return 0; 5663 } 5664 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 5665 5666 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 5667 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5668 { 5669 u32 val = 0; 5670 5671 if (gnt_cfg->band[0].gnt_bt) 5672 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5673 B_AX_GNT_BT_TX_VAL; 5674 else 5675 val |= B_AX_WL_ACT_VAL; 5676 5677 if (gnt_cfg->band[0].gnt_bt_sw_en) 5678 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5679 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5680 5681 if (gnt_cfg->band[0].gnt_wl) 5682 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5683 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5684 5685 if (gnt_cfg->band[0].gnt_wl_sw_en) 5686 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5687 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5688 5689 if (gnt_cfg->band[1].gnt_bt) 5690 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5691 B_AX_GNT_BT_TX_VAL; 5692 else 5693 val |= B_AX_WL_ACT_VAL; 5694 5695 if (gnt_cfg->band[1].gnt_bt_sw_en) 5696 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5697 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5698 5699 if (gnt_cfg->band[1].gnt_wl) 5700 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5701 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5702 5703 if (gnt_cfg->band[1].gnt_wl_sw_en) 5704 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5705 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5706 5707 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5708 5709 return 0; 5710 } 5711 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5712 5713 static 5714 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5715 { 5716 u32 reg; 5717 u16 val; 5718 int ret; 5719 5720 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5721 if (ret) 5722 return ret; 5723 5724 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 5725 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5726 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5727 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5728 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5729 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5730 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5731 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 5732 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 5733 B_AX_PLT_EN; 5734 rtw89_write16(rtwdev, reg, val); 5735 5736 return 0; 5737 } 5738 5739 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5740 { 5741 u32 fw_sb; 5742 5743 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5744 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5745 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5746 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5747 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5748 else 5749 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5750 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5751 val = B_AX_TOGGLE | 5752 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5753 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5754 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5755 fsleep(1000); /* avoid BT FW loss information */ 5756 } 5757 5758 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5759 { 5760 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5761 } 5762 5763 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5764 { 5765 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5766 5767 val = wl ? val | BIT(2) : val & ~BIT(2); 5768 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5769 5770 return 0; 5771 } 5772 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5773 5774 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5775 { 5776 struct rtw89_btc *btc = &rtwdev->btc; 5777 struct rtw89_btc_dm *dm = &btc->dm; 5778 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5779 int i; 5780 5781 if (wl) 5782 return 0; 5783 5784 for (i = 0; i < RTW89_PHY_MAX; i++) { 5785 g[i].gnt_bt_sw_en = 1; 5786 g[i].gnt_bt = 1; 5787 g[i].gnt_wl_sw_en = 1; 5788 g[i].gnt_wl = 0; 5789 } 5790 5791 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5792 } 5793 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5794 5795 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5796 { 5797 const struct rtw89_chip_info *chip = rtwdev->chip; 5798 u8 val = 0; 5799 5800 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) 5801 return false; 5802 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 5803 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5804 B_AX_LTE_MUX_CTRL_PATH >> 24); 5805 5806 return !!val; 5807 } 5808 5809 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 5810 { 5811 u32 reg; 5812 u16 cnt; 5813 5814 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 5815 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 5816 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 5817 5818 return cnt; 5819 } 5820 5821 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 5822 bool keep) 5823 { 5824 u32 reg; 5825 5826 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 5827 return; 5828 5829 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5830 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5831 if (keep) { 5832 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5833 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5834 BFRP_RX_STANDBY_TIMER_KEEP); 5835 } else { 5836 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5837 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5838 BFRP_RX_STANDBY_TIMER_RELEASE); 5839 } 5840 } 5841 5842 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5843 { 5844 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5845 u32 reg; 5846 u32 mask = mac->bfee_ctrl.mask; 5847 5848 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5849 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 5850 if (en) { 5851 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5852 rtw89_write32_set(rtwdev, reg, mask); 5853 } else { 5854 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5855 rtw89_write32_clr(rtwdev, reg, mask); 5856 } 5857 } 5858 5859 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 5860 { 5861 u32 reg; 5862 u32 val32; 5863 int ret; 5864 5865 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5866 if (ret) 5867 return ret; 5868 5869 /* AP mode set tx gid to 63 */ 5870 /* STA mode set tx gid to 0(default) */ 5871 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 5872 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5873 5874 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5875 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5876 5877 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5878 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5879 rtw89_write32(rtwdev, reg, val32); 5880 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5881 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5882 5883 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5884 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5885 B_AX_BFMEE_USE_NSTS | 5886 B_AX_BFMEE_CSI_GID_SEL | 5887 B_AX_BFMEE_CSI_FORCE_RETE_EN); 5888 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5889 rtw89_write32(rtwdev, reg, 5890 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5891 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5892 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5893 5894 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 5895 rtw89_write32_set(rtwdev, reg, 5896 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 5897 5898 return 0; 5899 } 5900 5901 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 5902 struct ieee80211_vif *vif, 5903 struct ieee80211_sta *sta) 5904 { 5905 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5906 u8 mac_idx = rtwvif->mac_idx; 5907 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5908 u8 port_sel = rtwvif->port; 5909 u8 sound_dim = 3, t; 5910 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5911 u32 reg; 5912 u16 val; 5913 int ret; 5914 5915 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5916 if (ret) 5917 return ret; 5918 5919 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5920 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5921 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5922 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5923 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5924 phy_cap[5]); 5925 sound_dim = min(sound_dim, t); 5926 } 5927 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5928 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5929 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5930 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5931 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5932 sta->deflink.vht_cap.cap); 5933 sound_dim = min(sound_dim, t); 5934 } 5935 nc = min(nc, sound_dim); 5936 nr = min(nr, sound_dim); 5937 5938 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5939 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5940 5941 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5942 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5943 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5944 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5945 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5946 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5947 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5948 5949 if (port_sel == 0) 5950 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5951 else 5952 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5953 5954 rtw89_write16(rtwdev, reg, val); 5955 5956 return 0; 5957 } 5958 5959 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 5960 struct ieee80211_vif *vif, 5961 struct ieee80211_sta *sta) 5962 { 5963 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5964 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5965 u32 reg; 5966 u8 mac_idx = rtwvif->mac_idx; 5967 int ret; 5968 5969 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5970 if (ret) 5971 return ret; 5972 5973 if (sta->deflink.he_cap.has_he) { 5974 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5975 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5976 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5977 } 5978 if (sta->deflink.vht_cap.vht_supported) { 5979 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5980 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5981 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5982 } 5983 if (sta->deflink.ht_cap.ht_supported) { 5984 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5985 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5986 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5987 } 5988 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5989 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5990 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5991 rtw89_write32(rtwdev, 5992 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5993 rrsc); 5994 5995 return 0; 5996 } 5997 5998 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 5999 struct ieee80211_vif *vif, 6000 struct ieee80211_sta *sta) 6001 { 6002 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6003 6004 if (rtw89_sta_has_beamformer_cap(sta)) { 6005 rtw89_debug(rtwdev, RTW89_DBG_BF, 6006 "initialize bfee for new association\n"); 6007 rtw89_mac_init_bfee_ax(rtwdev, rtwvif->mac_idx); 6008 rtw89_mac_set_csi_para_reg_ax(rtwdev, vif, sta); 6009 rtw89_mac_csi_rrsc_ax(rtwdev, vif, sta); 6010 } 6011 } 6012 6013 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6014 struct ieee80211_sta *sta) 6015 { 6016 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6017 6018 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 6019 } 6020 6021 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6022 struct ieee80211_bss_conf *conf) 6023 { 6024 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6025 u8 mac_idx = rtwvif->mac_idx; 6026 __le32 *p; 6027 6028 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 6029 6030 p = (__le32 *)conf->mu_group.membership; 6031 rtw89_write32(rtwdev, 6032 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 6033 le32_to_cpu(p[0])); 6034 rtw89_write32(rtwdev, 6035 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 6036 le32_to_cpu(p[1])); 6037 6038 p = (__le32 *)conf->mu_group.position; 6039 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 6040 le32_to_cpu(p[0])); 6041 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 6042 le32_to_cpu(p[1])); 6043 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 6044 le32_to_cpu(p[2])); 6045 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 6046 le32_to_cpu(p[3])); 6047 } 6048 6049 struct rtw89_mac_bf_monitor_iter_data { 6050 struct rtw89_dev *rtwdev; 6051 struct ieee80211_sta *down_sta; 6052 int count; 6053 }; 6054 6055 static 6056 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 6057 { 6058 struct rtw89_mac_bf_monitor_iter_data *iter_data = 6059 (struct rtw89_mac_bf_monitor_iter_data *)data; 6060 struct ieee80211_sta *down_sta = iter_data->down_sta; 6061 int *count = &iter_data->count; 6062 6063 if (down_sta == sta) 6064 return; 6065 6066 if (rtw89_sta_has_beamformer_cap(sta)) 6067 (*count)++; 6068 } 6069 6070 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 6071 struct ieee80211_sta *sta, bool disconnect) 6072 { 6073 struct rtw89_mac_bf_monitor_iter_data data; 6074 6075 data.rtwdev = rtwdev; 6076 data.down_sta = disconnect ? sta : NULL; 6077 data.count = 0; 6078 ieee80211_iterate_stations_atomic(rtwdev->hw, 6079 rtw89_mac_bf_monitor_calc_iter, 6080 &data); 6081 6082 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 6083 if (data.count) 6084 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6085 else 6086 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6087 } 6088 6089 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 6090 { 6091 struct rtw89_traffic_stats *stats = &rtwdev->stats; 6092 struct rtw89_vif *rtwvif; 6093 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 6094 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6095 bool keep_timer = true; 6096 bool old_keep_timer; 6097 6098 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6099 6100 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 6101 keep_timer = false; 6102 6103 if (keep_timer != old_keep_timer) { 6104 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6105 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 6106 keep_timer); 6107 } 6108 6109 if (en == old) 6110 return; 6111 6112 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6113 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 6114 } 6115 6116 static int 6117 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6118 u32 tx_time) 6119 { 6120 #define MAC_AX_DFLT_TX_TIME 5280 6121 u8 mac_idx = rtwsta->rtwvif->mac_idx; 6122 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 6123 u32 reg; 6124 int ret = 0; 6125 6126 if (rtwsta->cctl_tx_time) { 6127 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 6128 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6129 } else { 6130 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6131 if (ret) { 6132 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 6133 return ret; 6134 } 6135 6136 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6137 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 6138 max_tx_time >> 5); 6139 } 6140 6141 return ret; 6142 } 6143 6144 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6145 bool resume, u32 tx_time) 6146 { 6147 int ret = 0; 6148 6149 if (!resume) { 6150 rtwsta->cctl_tx_time = true; 6151 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 6152 } else { 6153 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 6154 rtwsta->cctl_tx_time = false; 6155 } 6156 6157 return ret; 6158 } 6159 6160 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6161 u32 *tx_time) 6162 { 6163 u8 mac_idx = rtwsta->rtwvif->mac_idx; 6164 u32 reg; 6165 int ret = 0; 6166 6167 if (rtwsta->cctl_tx_time) { 6168 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 6169 } else { 6170 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6171 if (ret) { 6172 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 6173 return ret; 6174 } 6175 6176 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6177 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 6178 } 6179 6180 return ret; 6181 } 6182 6183 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 6184 struct rtw89_sta *rtwsta, 6185 bool resume, u8 tx_retry) 6186 { 6187 int ret = 0; 6188 6189 rtwsta->data_tx_cnt_lmt = tx_retry; 6190 6191 if (!resume) { 6192 rtwsta->cctl_tx_retry_limit = true; 6193 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6194 } else { 6195 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6196 rtwsta->cctl_tx_retry_limit = false; 6197 } 6198 6199 return ret; 6200 } 6201 6202 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 6203 struct rtw89_sta *rtwsta, u8 *tx_retry) 6204 { 6205 u8 mac_idx = rtwsta->rtwvif->mac_idx; 6206 u32 reg; 6207 int ret = 0; 6208 6209 if (rtwsta->cctl_tx_retry_limit) { 6210 *tx_retry = rtwsta->data_tx_cnt_lmt; 6211 } else { 6212 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6213 if (ret) { 6214 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 6215 return ret; 6216 } 6217 6218 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); 6219 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 6220 } 6221 6222 return ret; 6223 } 6224 6225 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 6226 struct rtw89_vif *rtwvif, bool en) 6227 { 6228 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6229 u8 mac_idx = rtwvif->mac_idx; 6230 u16 set = mac->muedca_ctrl.mask; 6231 u32 reg; 6232 u32 ret; 6233 6234 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6235 if (ret) 6236 return ret; 6237 6238 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 6239 if (en) 6240 rtw89_write16_set(rtwdev, reg, set); 6241 else 6242 rtw89_write16_clr(rtwdev, reg, set); 6243 6244 return 0; 6245 } 6246 6247 static 6248 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 6249 { 6250 u32 val32; 6251 int ret; 6252 6253 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6254 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 6255 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 6256 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 6257 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6258 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6259 6260 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6261 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6262 if (ret) { 6263 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 6264 offset, val, mask); 6265 return ret; 6266 } 6267 6268 return 0; 6269 } 6270 6271 static 6272 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 6273 { 6274 u32 val32; 6275 int ret; 6276 6277 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6278 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 6279 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 6280 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 6281 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6282 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6283 6284 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6285 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6286 if (ret) { 6287 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 6288 return ret; 6289 } 6290 6291 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 6292 6293 return 0; 6294 } 6295 6296 static 6297 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 6298 { 6299 static const enum rtw89_pkt_drop_sel sels[] = { 6300 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 6301 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 6302 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 6303 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 6304 }; 6305 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6306 struct rtw89_pkt_drop_params params = {0}; 6307 int i; 6308 6309 params.mac_band = RTW89_MAC_0; 6310 params.macid = rtwsta->mac_id; 6311 params.port = rtwvif->port; 6312 params.mbssid = 0; 6313 params.tf_trs = rtwvif->trigger; 6314 6315 for (i = 0; i < ARRAY_SIZE(sels); i++) { 6316 params.sel = sels[i]; 6317 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6318 } 6319 } 6320 6321 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 6322 { 6323 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 6324 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6325 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 6326 struct rtw89_vif *target = data; 6327 6328 if (rtwvif != target) 6329 return; 6330 6331 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 6332 } 6333 6334 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 6335 { 6336 ieee80211_iterate_stations_atomic(rtwdev->hw, 6337 rtw89_mac_pkt_drop_vif_iter, 6338 rtwvif); 6339 } 6340 6341 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 6342 enum rtw89_mac_idx band) 6343 { 6344 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6345 struct rtw89_pkt_drop_params params = {0}; 6346 bool empty; 6347 int i, ret = 0, try_cnt = 3; 6348 6349 params.mac_band = band; 6350 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 6351 6352 for (i = 0; i < try_cnt; i++) { 6353 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 6354 50000, false, rtwdev); 6355 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 6356 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6357 else 6358 return 0; 6359 } 6360 return ret; 6361 } 6362 6363 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 6364 { 6365 struct rtw89_mac_h2c_info h2c_info = {}; 6366 struct rtw89_mac_c2h_info c2h_info = {}; 6367 u32 ret; 6368 6369 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; 6370 h2c_info.content_len = sizeof(h2c_info.u.hdr); 6371 h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); 6372 6373 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 6374 if (ret) 6375 return ret; 6376 6377 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) 6378 ret = -EINVAL; 6379 6380 return ret; 6381 } 6382 6383 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 6384 { 6385 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6386 const struct rtw89_chip_info *chip = rtwdev->chip; 6387 int ret; 6388 6389 if (enable_wow) { 6390 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 6391 if (ret) { 6392 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6393 return ret; 6394 } 6395 6396 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6397 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6398 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 6399 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 6400 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 6401 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 6402 rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 6403 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 6404 6405 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6406 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 6407 else 6408 rtw89_write32_set(rtwdev, R_AX_DBG_WOW, 6409 B_AX_DBG_WOW_CPU_IO_RX_EN); 6410 } else { 6411 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 6412 if (ret) { 6413 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6414 return ret; 6415 } 6416 6417 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6418 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6419 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 6420 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 6421 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 6422 } 6423 6424 return 0; 6425 } 6426 6427 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 6428 { 6429 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 6430 6431 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 6432 } 6433 6434 static 6435 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 6436 bool h2c_or_fwdl) 6437 { 6438 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 6439 u8 val; 6440 6441 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 6442 1, FWDL_WAIT_CNT, false, 6443 rtwdev, R_AX_WCPU_FW_CTRL); 6444 } 6445 6446 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 6447 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 6448 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 6449 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 6450 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 6451 .rx_fltr = R_AX_RX_FLTR_OPT, 6452 .port_base = &rtw89_port_base_ax, 6453 .agg_len_ht = R_AX_AGG_LEN_HT_0, 6454 .ps_status = R_AX_PPWRBIT_SETTING, 6455 6456 .muedca_ctrl = { 6457 .addr = R_AX_MUEDCA_EN, 6458 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 6459 }, 6460 .bfee_ctrl = { 6461 .addr = R_AX_BFMEE_RESP_OPTION, 6462 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 6463 B_AX_BFMEE_HE_NDPA_EN, 6464 }, 6465 .narrow_bw_ru_dis = { 6466 .addr = R_AX_RXTRIG_TEST_USER_2, 6467 .mask = B_AX_RXTRIG_RU26_DIS, 6468 }, 6469 .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 6470 6471 .check_mac_en = rtw89_mac_check_mac_en_ax, 6472 .sys_init = sys_init_ax, 6473 .trx_init = trx_init_ax, 6474 .hci_func_en = rtw89_mac_hci_func_en_ax, 6475 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 6476 .dle_func_en = dle_func_en_ax, 6477 .dle_clk_en = dle_clk_en_ax, 6478 .bf_assoc = rtw89_mac_bf_assoc_ax, 6479 6480 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 6481 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 6482 6483 .dle_mix_cfg = dle_mix_cfg_ax, 6484 .chk_dle_rdy = chk_dle_rdy_ax, 6485 .dle_buf_req = dle_buf_req_ax, 6486 .hfc_func_en = hfc_func_en_ax, 6487 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 6488 .hfc_mix_cfg = hfc_mix_cfg_ax, 6489 .hfc_get_mix_info = hfc_get_mix_info_ax, 6490 .wde_quota_cfg = wde_quota_cfg_ax, 6491 .ple_quota_cfg = ple_quota_cfg_ax, 6492 .set_cpuio = set_cpuio_ax, 6493 .dle_quota_change = dle_quota_change_ax, 6494 6495 .disable_cpu = rtw89_mac_disable_cpu_ax, 6496 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 6497 .fwdl_get_status = rtw89_fw_get_rdy_ax, 6498 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 6499 .parse_efuse_map = rtw89_parse_efuse_map_ax, 6500 .parse_phycap_map = rtw89_parse_phycap_map_ax, 6501 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 6502 6503 .cfg_plt = rtw89_mac_cfg_plt_ax, 6504 .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 6505 6506 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 6507 6508 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 6509 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 6510 6511 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 6512 .dump_err_status = rtw89_mac_dump_err_status_ax, 6513 6514 .is_txq_empty = mac_is_txq_empty_ax, 6515 6516 .add_chan_list = rtw89_hw_scan_add_chan_list, 6517 .scan_offload = rtw89_fw_h2c_scan_offload, 6518 6519 .wow_config_mac = rtw89_wow_config_mac_ax, 6520 }; 6521 EXPORT_SYMBOL(rtw89_mac_gen_ax); 6522