1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "phy.h" 13 #include "ps.h" 14 #include "reg.h" 15 #include "util.h" 16 17 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 18 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 19 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 20 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 21 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 22 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 23 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 26 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 27 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 28 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 29 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 30 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 31 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 32 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 33 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 34 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 35 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 36 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 37 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 38 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 39 }; 40 41 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 42 u32 val, enum rtw89_mac_mem_sel sel) 43 { 44 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 45 u32 addr = mac->mem_base_addrs[sel] + offset; 46 47 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 48 rtw89_write32(rtwdev, mac->indir_access_addr, val); 49 } 50 51 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 52 enum rtw89_mac_mem_sel sel) 53 { 54 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 55 u32 addr = mac->mem_base_addrs[sel] + offset; 56 57 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 58 return rtw89_read32(rtwdev, mac->indir_access_addr); 59 } 60 61 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 62 enum rtw89_mac_hwmod_sel sel) 63 { 64 u32 val, r_val; 65 66 if (sel == RTW89_DMAC_SEL) { 67 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 68 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 69 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 70 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 71 val = B_AX_CMAC_EN; 72 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 73 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 74 val = B_AX_CMAC1_FEN; 75 } else { 76 return -EINVAL; 77 } 78 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 79 (val & r_val) != val) 80 return -EFAULT; 81 82 return 0; 83 } 84 85 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 86 { 87 u8 lte_ctrl; 88 int ret; 89 90 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 91 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 92 if (ret && !test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 93 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 94 95 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 96 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 97 98 return ret; 99 } 100 101 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 102 { 103 u8 lte_ctrl; 104 int ret; 105 106 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 107 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 108 if (ret && !test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 109 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 110 111 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 112 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 113 114 return ret; 115 } 116 117 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 118 { 119 u32 ctrl_reg, data_reg, ctrl_data; 120 u32 val; 121 int ret; 122 123 switch (ctrl->type) { 124 case DLE_CTRL_TYPE_WDE: 125 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 126 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 127 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 128 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 129 B_AX_WDE_DFI_ACTIVE; 130 break; 131 case DLE_CTRL_TYPE_PLE: 132 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 133 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 134 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 135 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 136 B_AX_PLE_DFI_ACTIVE; 137 break; 138 default: 139 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 140 return -EINVAL; 141 } 142 143 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 144 145 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 146 1, 1000, false, rtwdev, ctrl_reg); 147 if (ret) { 148 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 149 ctrl_reg, ctrl_data); 150 return ret; 151 } 152 153 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 154 return 0; 155 } 156 157 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 158 struct rtw89_mac_dle_dfi_quota *quota) 159 { 160 struct rtw89_mac_dle_dfi_ctrl ctrl; 161 int ret; 162 163 ctrl.type = quota->dle_type; 164 ctrl.target = DLE_DFI_TYPE_QUOTA; 165 ctrl.addr = quota->qtaid; 166 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 167 if (ret) { 168 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 169 return ret; 170 } 171 172 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 173 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 174 return 0; 175 } 176 177 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 178 struct rtw89_mac_dle_dfi_qempty *qempty) 179 { 180 struct rtw89_mac_dle_dfi_ctrl ctrl; 181 int ret; 182 183 ctrl.type = qempty->dle_type; 184 ctrl.target = DLE_DFI_TYPE_QEMPTY; 185 ctrl.addr = qempty->grpsel; 186 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 187 if (ret) { 188 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 189 return ret; 190 } 191 192 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 193 return 0; 194 } 195 196 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 197 { 198 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 199 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 200 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 201 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 202 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 203 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 204 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 205 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 206 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 207 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 208 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 209 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 210 } 211 212 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 213 { 214 struct rtw89_mac_dle_dfi_qempty qempty; 215 struct rtw89_mac_dle_dfi_quota quota; 216 struct rtw89_mac_dle_dfi_ctrl ctrl; 217 u32 val, not_empty, i; 218 int ret; 219 220 qempty.dle_type = DLE_CTRL_TYPE_PLE; 221 qempty.grpsel = 0; 222 qempty.qempty = ~(u32)0; 223 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 224 if (ret) 225 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 226 else 227 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 228 229 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 230 if (!(not_empty & BIT(0))) 231 continue; 232 ctrl.type = DLE_CTRL_TYPE_PLE; 233 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 234 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 235 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 236 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 237 if (ret) 238 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 239 else 240 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 241 u32_get_bits(ctrl.out_data, 242 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 243 } 244 245 quota.dle_type = DLE_CTRL_TYPE_PLE; 246 quota.qtaid = 6; 247 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 248 if (ret) 249 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 250 else 251 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 252 quota.rsv_pgnum, quota.use_pgnum); 253 254 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 255 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 256 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 257 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 258 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 259 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 260 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 261 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 262 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 263 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 264 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 265 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 266 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 267 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 268 269 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 270 quota.dle_type = DLE_CTRL_TYPE_PLE; 271 quota.qtaid = 7; 272 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 273 if (ret) 274 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 275 else 276 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 277 quota.rsv_pgnum, quota.use_pgnum); 278 279 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 280 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 281 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 282 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 283 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 284 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 285 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 286 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 287 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 288 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 289 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 290 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 291 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 292 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 293 } 294 295 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 296 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 297 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 298 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 299 300 dump_err_status_dispatcher_ax(rtwdev); 301 } 302 303 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 304 enum mac_ax_err_info err) 305 { 306 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 307 u32 dbg, event; 308 309 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 310 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 311 312 switch (event) { 313 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 314 rtw89_info(rtwdev, "quota lost!\n"); 315 mac->dump_qta_lost(rtwdev); 316 break; 317 default: 318 break; 319 } 320 } 321 322 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 323 { 324 const struct rtw89_chip_info *chip = rtwdev->chip; 325 u32 dmac_err; 326 int i, ret; 327 328 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 329 if (ret) { 330 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 331 return; 332 } 333 334 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 335 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 336 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 337 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 338 339 if (dmac_err) { 340 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 341 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 342 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 343 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 344 if (chip->chip_id == RTL8852C) { 345 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 346 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 347 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 348 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 349 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 350 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 351 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 352 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 353 } 354 } 355 356 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 357 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 358 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 359 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 360 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 361 if (chip->chip_id == RTL8852C) 362 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 363 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 364 else 365 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 366 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 367 } 368 369 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 370 if (chip->chip_id == RTL8852C) { 371 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 372 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 373 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 374 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 375 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 376 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 377 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 378 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 379 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 380 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 381 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 382 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 383 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 384 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 385 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 386 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 387 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 388 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 389 390 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 391 B_AX_DBG_SEL0, 0x8B); 392 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 393 B_AX_DBG_SEL1, 0x8B); 394 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 395 B_AX_SEL_0XC0_MASK, 1); 396 for (i = 0; i < 0x10; i++) { 397 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 398 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 399 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 400 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 401 } 402 } else if (chip->chip_id == RTL8922A) { 403 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 404 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 405 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 406 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 407 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 408 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 409 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 410 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 411 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 412 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 413 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 414 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 415 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 416 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 417 } else { 418 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 419 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 420 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 421 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 422 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 423 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 424 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 425 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 426 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 427 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 428 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 429 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 430 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 431 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 432 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 433 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 434 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 435 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 436 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 437 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 438 } 439 } 440 441 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 442 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 443 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 444 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 445 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 446 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 447 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 448 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 449 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 450 } 451 452 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 453 if (chip->chip_id == RTL8922A) { 454 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 455 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 456 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 457 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 458 } else { 459 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 460 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 461 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 462 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 463 } 464 } 465 466 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 467 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 468 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 469 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 470 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 471 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 472 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 473 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 474 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 475 } 476 477 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 478 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 479 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 480 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 481 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 482 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 483 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 484 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 485 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 486 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 487 } else { 488 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 489 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 490 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 491 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 492 } 493 } 494 495 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 496 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 497 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 498 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 499 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 500 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 501 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 502 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 503 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 504 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 505 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 506 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 507 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 508 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 509 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 510 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 511 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 512 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 513 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 514 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 515 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 516 if (chip->chip_id == RTL8922A) { 517 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 518 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 519 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 520 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 521 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 522 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 523 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 524 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 525 } else { 526 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 527 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 528 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 529 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 530 if (chip->chip_id == RTL8852C) { 531 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 532 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 533 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 534 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 535 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 536 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 537 } else { 538 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 539 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 540 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 541 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 542 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 543 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 544 } 545 } 546 } 547 548 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 549 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 550 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 551 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 552 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 553 } 554 555 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 556 if (chip->chip_id == RTL8922A) { 557 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 558 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 559 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 560 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 561 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 562 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 563 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 564 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 565 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 566 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 567 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 568 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 569 } else { 570 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 571 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 572 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 573 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 574 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 575 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 576 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 577 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 578 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 579 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 580 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 581 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 582 } 583 } 584 585 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 586 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 587 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 588 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 589 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 590 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 591 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 592 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 593 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 594 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 595 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 596 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 597 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 598 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 599 } else { 600 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 601 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 602 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 603 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 604 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 605 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 606 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 607 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 608 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 609 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 610 } 611 if (chip->chip_id == RTL8922A) { 612 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 613 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 614 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 615 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 616 } 617 } 618 619 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 620 if (chip->chip_id == RTL8922A) { 621 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 622 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 623 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 624 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 625 } else if (chip->chip_id == RTL8852C) { 626 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 627 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 628 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 629 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 630 } 631 } 632 633 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 634 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 635 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 636 RTW89_MAC_MEM_AXIDMA)); 637 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 638 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 639 RTW89_MAC_MEM_AXIDMA)); 640 } 641 642 if (dmac_err & B_BE_MLO_ERR_INT) { 643 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 644 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 645 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 646 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 647 } 648 649 if (dmac_err & B_BE_PLRLS_ERR_INT) { 650 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 651 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 652 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 653 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 654 } 655 } 656 657 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 658 u8 band) 659 { 660 const struct rtw89_chip_info *chip = rtwdev->chip; 661 u32 offset = 0; 662 u32 cmac_err; 663 int ret; 664 665 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 666 if (ret) { 667 if (band) 668 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 669 else 670 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 671 return; 672 } 673 674 if (band) 675 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 676 677 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 678 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 679 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 680 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 681 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 682 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 683 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 684 685 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 686 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 687 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 688 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 689 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 690 } 691 692 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 693 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 694 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 695 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 696 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 697 } 698 699 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 700 if (chip->chip_id == RTL8852C) { 701 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 702 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 703 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 704 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 705 } else { 706 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 707 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 708 } 709 } 710 711 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 712 if (chip->chip_id == RTL8852C) { 713 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 714 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 715 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 716 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 717 } else { 718 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 719 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 720 } 721 } 722 723 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 724 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 725 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 726 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 727 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 728 } 729 730 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 731 if (chip->chip_id == RTL8852C) { 732 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 733 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 734 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 735 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 736 } else { 737 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 738 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 739 } 740 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 741 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 742 } 743 744 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 745 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 746 } 747 748 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 749 enum mac_ax_err_info err) 750 { 751 if (err != MAC_AX_ERR_L1_ERR_DMAC && 752 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 753 err != MAC_AX_ERR_L0_ERR_CMAC0 && 754 err != MAC_AX_ERR_L0_ERR_CMAC1 && 755 err != MAC_AX_ERR_RXI300) 756 return; 757 758 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 759 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 760 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 761 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 762 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 763 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 764 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 765 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 766 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 767 768 rtw89_mac_dump_dmac_err_status(rtwdev); 769 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 770 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 771 772 rtwdev->hci.ops->dump_err_status(rtwdev); 773 774 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 775 rtw89_mac_dump_l0_to_l1(rtwdev, err); 776 777 rtw89_info(rtwdev, "<---\n"); 778 } 779 780 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 781 { 782 struct rtw89_ser *ser = &rtwdev->ser; 783 u32 dmac_err, imr, isr; 784 int ret; 785 786 if (rtwdev->chip->chip_id == RTL8852C) { 787 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 788 if (ret) 789 return true; 790 791 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 792 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 793 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 794 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 795 796 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 797 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 798 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 799 return true; 800 } 801 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 802 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 803 return true; 804 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 805 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 806 return true; 807 } 808 } 809 810 return false; 811 } 812 813 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 814 { 815 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 816 u32 err, err_scnr; 817 int ret; 818 819 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 820 false, rtwdev, R_AX_HALT_C2H_CTRL); 821 if (ret) { 822 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 823 return ret; 824 } 825 826 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 827 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 828 829 err_scnr = RTW89_ERROR_SCENARIO(err); 830 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 831 err = MAC_AX_ERR_CPU_EXCEPTION; 832 else if (err_scnr == RTW89_WCPU_ASSERTION) 833 err = MAC_AX_ERR_ASSERTION; 834 else if (err_scnr == RTW89_RXI300_ERROR) 835 err = MAC_AX_ERR_RXI300; 836 837 if (rtw89_mac_suppress_log(rtwdev, err)) 838 return err; 839 840 rtw89_fw_st_dbg_dump(rtwdev); 841 mac->dump_err_status(rtwdev, err); 842 843 return err; 844 } 845 EXPORT_SYMBOL(rtw89_mac_get_err_status); 846 847 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 848 { 849 struct rtw89_ser *ser = &rtwdev->ser; 850 u32 halt; 851 int ret = 0; 852 853 if (err > MAC_AX_SET_ERR_MAX) { 854 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 855 return -EINVAL; 856 } 857 858 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 859 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 860 if (ret) { 861 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 862 return -EFAULT; 863 } 864 865 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 866 867 if (ser->prehandle_l1 && 868 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 869 return 0; 870 871 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 872 873 return 0; 874 } 875 EXPORT_SYMBOL(rtw89_mac_set_err_status); 876 877 static int hfc_reset_param(struct rtw89_dev *rtwdev) 878 { 879 const struct rtw89_hfc_param_ini *param_ini, *param_inis; 880 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 881 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 882 883 param_inis = rtwdev->chip->hfc_param_ini[rtwdev->hci.type]; 884 if (!param_inis) 885 return -EINVAL; 886 887 param_ini = ¶m_inis[qta_mode]; 888 889 param->en = 0; 890 891 if (param_ini->pub_cfg) 892 param->pub_cfg = *param_ini->pub_cfg; 893 894 if (param_ini->prec_cfg) 895 param->prec_cfg = *param_ini->prec_cfg; 896 897 if (param_ini->ch_cfg) 898 param->ch_cfg = param_ini->ch_cfg; 899 900 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 901 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 902 param->mode = param_ini->mode; 903 904 return 0; 905 } 906 907 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 908 { 909 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 910 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 911 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 912 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 913 914 if (ch >= RTW89_DMA_CH_NUM) 915 return -EINVAL; 916 917 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 918 ch_cfg[ch].max > pub_cfg->pub_max) 919 return -EINVAL; 920 if (ch_cfg[ch].grp >= grp_num) 921 return -EINVAL; 922 923 return 0; 924 } 925 926 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 927 { 928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 929 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 930 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 931 932 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 933 if (rtwdev->chip->chip_id == RTL8852A) 934 return 0; 935 else 936 return -EFAULT; 937 } 938 939 return 0; 940 } 941 942 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 943 { 944 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 945 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 946 947 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 948 return -EFAULT; 949 950 return 0; 951 } 952 953 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 954 { 955 const struct rtw89_chip_info *chip = rtwdev->chip; 956 const struct rtw89_page_regs *regs = chip->page_regs; 957 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 958 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 959 int ret = 0; 960 u32 val = 0; 961 962 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 963 if (ret) 964 return ret; 965 966 ret = hfc_ch_cfg_chk(rtwdev, ch); 967 if (ret) 968 return ret; 969 970 if (ch > RTW89_DMA_B1HI) 971 return -EINVAL; 972 973 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 974 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 975 (cfg[ch].grp ? B_AX_GRP : 0); 976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 977 978 return 0; 979 } 980 981 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 982 { 983 const struct rtw89_chip_info *chip = rtwdev->chip; 984 const struct rtw89_page_regs *regs = chip->page_regs; 985 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 986 struct rtw89_hfc_ch_info *info = param->ch_info; 987 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 988 u32 val; 989 int ret; 990 991 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 992 if (ret) 993 return ret; 994 995 if (ch > RTW89_DMA_H2C) 996 return -EINVAL; 997 998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 999 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1000 if (ch < RTW89_DMA_H2C) 1001 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1002 else 1003 info[ch].used = cfg[ch].min - info[ch].aval; 1004 1005 return 0; 1006 } 1007 1008 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1009 { 1010 const struct rtw89_chip_info *chip = rtwdev->chip; 1011 const struct rtw89_page_regs *regs = chip->page_regs; 1012 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1013 u32 val; 1014 int ret; 1015 1016 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1017 if (ret) 1018 return ret; 1019 1020 ret = hfc_pub_cfg_chk(rtwdev); 1021 if (ret) 1022 return ret; 1023 1024 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1025 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1027 1028 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1030 1031 return 0; 1032 } 1033 1034 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1035 { 1036 const struct rtw89_chip_info *chip = rtwdev->chip; 1037 const struct rtw89_page_regs *regs = chip->page_regs; 1038 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1039 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1040 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1041 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1042 u32 val; 1043 1044 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1045 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1046 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1047 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1048 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1049 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1050 info->pub_aval = 1051 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1052 B_AX_PUB_AVAL_PG_MASK); 1053 info->wp_aval = 1054 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1055 B_AX_WP_AVAL_PG_MASK); 1056 1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1058 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1059 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1060 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1061 prec_cfg->ch011_full_cond = 1062 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1063 prec_cfg->h2c_full_cond = 1064 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1065 prec_cfg->wp_ch07_full_cond = 1066 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1067 prec_cfg->wp_ch811_full_cond = 1068 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1069 1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1071 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1072 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1073 1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1075 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1076 1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1078 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1079 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1080 1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1082 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1083 1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1085 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1086 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1087 } 1088 1089 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1090 { 1091 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1092 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1093 int ret; 1094 1095 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1096 if (ret) 1097 return ret; 1098 1099 mac->hfc_get_mix_info(rtwdev); 1100 1101 ret = hfc_pub_info_chk(rtwdev); 1102 if (param->en && ret) 1103 return ret; 1104 1105 return 0; 1106 } 1107 1108 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1109 { 1110 const struct rtw89_chip_info *chip = rtwdev->chip; 1111 const struct rtw89_page_regs *regs = chip->page_regs; 1112 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1113 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1114 u32 val; 1115 1116 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1118 1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1120 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1121 prec_cfg->h2c_full_cond); 1122 } 1123 1124 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1125 { 1126 const struct rtw89_chip_info *chip = rtwdev->chip; 1127 const struct rtw89_page_regs *regs = chip->page_regs; 1128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1129 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1130 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1131 u32 val; 1132 1133 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1134 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1136 1137 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1139 1140 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1141 B_AX_PREC_PAGE_WP_CH07_MASK) | 1142 u32_encode_bits(prec_cfg->wp_ch811_prec, 1143 B_AX_PREC_PAGE_WP_CH811_MASK); 1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1145 1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1147 param->mode, B_AX_HCI_FC_MODE_MASK); 1148 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1149 B_AX_HCI_FC_WD_FULL_COND_MASK); 1150 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1151 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1152 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1153 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1154 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1155 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1157 } 1158 1159 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1160 { 1161 const struct rtw89_chip_info *chip = rtwdev->chip; 1162 const struct rtw89_page_regs *regs = chip->page_regs; 1163 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1164 u32 val; 1165 1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1167 param->en = en; 1168 param->h2c_en = h2c_en; 1169 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1170 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1171 (val & ~B_AX_HCI_FC_CH12_EN); 1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1173 } 1174 1175 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1176 { 1177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1178 const struct rtw89_chip_info *chip = rtwdev->chip; 1179 u32 dma_ch_mask = chip->dma_ch_mask; 1180 int ret = 0; 1181 u8 ch; 1182 1183 if (reset) 1184 ret = hfc_reset_param(rtwdev); 1185 if (ret) 1186 return ret; 1187 1188 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1189 if (ret) 1190 return ret; 1191 1192 mac->hfc_func_en(rtwdev, false, false); 1193 1194 if (!en && h2c_en) { 1195 mac->hfc_h2c_cfg(rtwdev); 1196 mac->hfc_func_en(rtwdev, en, h2c_en); 1197 return 0; 1198 } 1199 1200 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1201 if (dma_ch_mask & BIT(ch)) 1202 continue; 1203 ret = hfc_ch_ctrl(rtwdev, ch); 1204 if (ret) 1205 return ret; 1206 } 1207 1208 ret = hfc_pub_ctrl(rtwdev); 1209 if (ret) 1210 return ret; 1211 1212 mac->hfc_mix_cfg(rtwdev); 1213 if (en || h2c_en) { 1214 mac->hfc_func_en(rtwdev, en, h2c_en); 1215 udelay(10); 1216 } 1217 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1218 if (dma_ch_mask & BIT(ch)) 1219 continue; 1220 ret = hfc_upd_ch_info(rtwdev, ch); 1221 if (ret) 1222 return ret; 1223 } 1224 ret = hfc_upd_mix_info(rtwdev); 1225 1226 return ret; 1227 } 1228 1229 #define PWR_POLL_CNT 2000 1230 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1231 const struct rtw89_pwr_cfg *cfg) 1232 { 1233 u8 val = 0; 1234 int ret; 1235 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1236 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1237 1238 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1239 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1240 1241 if (!ret) 1242 return 0; 1243 1244 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1245 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1247 1248 return -EBUSY; 1249 } 1250 1251 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1252 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1253 { 1254 const struct rtw89_pwr_cfg *cur_cfg; 1255 u32 addr; 1256 u8 val; 1257 1258 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1259 if (!(cur_cfg->intf_msk & intf_msk) || 1260 !(cur_cfg->cv_msk & cv_msk)) 1261 continue; 1262 1263 switch (cur_cfg->cmd) { 1264 case PWR_CMD_WRITE: 1265 addr = cur_cfg->addr; 1266 1267 if (cur_cfg->base == PWR_BASE_SDIO) 1268 addr |= SDIO_LOCAL_BASE_ADDR; 1269 1270 val = rtw89_read8(rtwdev, addr); 1271 val &= ~(cur_cfg->msk); 1272 val |= (cur_cfg->val & cur_cfg->msk); 1273 1274 rtw89_write8(rtwdev, addr, val); 1275 break; 1276 case PWR_CMD_POLL: 1277 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1278 return -EBUSY; 1279 break; 1280 case PWR_CMD_DELAY: 1281 if (cur_cfg->val == PWR_DELAY_US) 1282 udelay(cur_cfg->addr); 1283 else 1284 fsleep(cur_cfg->addr * 1000); 1285 break; 1286 default: 1287 return -EINVAL; 1288 } 1289 } 1290 1291 return 0; 1292 } 1293 1294 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1295 const struct rtw89_pwr_cfg * const *cfg_seq) 1296 { 1297 int ret; 1298 1299 for (; *cfg_seq; cfg_seq++) { 1300 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1301 PWR_INTF_MSK_PCIE, *cfg_seq); 1302 if (ret) 1303 return -EBUSY; 1304 } 1305 1306 return 0; 1307 } 1308 1309 static enum rtw89_rpwm_req_pwr_state 1310 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1311 { 1312 enum rtw89_rpwm_req_pwr_state state; 1313 1314 switch (rtwdev->ps_mode) { 1315 case RTW89_PS_MODE_RFOFF: 1316 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1317 break; 1318 case RTW89_PS_MODE_CLK_GATED: 1319 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1320 break; 1321 case RTW89_PS_MODE_PWR_GATED: 1322 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1323 break; 1324 default: 1325 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1326 break; 1327 } 1328 return state; 1329 } 1330 1331 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1332 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1333 bool notify_wake) 1334 { 1335 u16 request; 1336 1337 spin_lock_bh(&rtwdev->rpwm_lock); 1338 1339 request = rtw89_read16(rtwdev, R_AX_RPWM); 1340 request ^= request | PS_RPWM_TOGGLE; 1341 request |= req_pwr_state; 1342 1343 if (notify_wake) { 1344 request |= PS_RPWM_NOTIFY_WAKE; 1345 } else { 1346 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1347 RPWM_SEQ_NUM_MAX; 1348 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1349 rtwdev->mac.rpwm_seq_num); 1350 1351 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1352 request |= PS_RPWM_ACK; 1353 } 1354 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1355 1356 spin_unlock_bh(&rtwdev->rpwm_lock); 1357 } 1358 1359 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1360 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1361 { 1362 bool request_deep_mode; 1363 bool in_deep_mode; 1364 u8 rpwm_req_num; 1365 u8 cpwm_rsp_seq; 1366 u8 cpwm_seq; 1367 u8 cpwm_status; 1368 1369 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1370 request_deep_mode = true; 1371 else 1372 request_deep_mode = false; 1373 1374 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1375 in_deep_mode = true; 1376 else 1377 in_deep_mode = false; 1378 1379 if (request_deep_mode != in_deep_mode) 1380 return -EPERM; 1381 1382 if (request_deep_mode) 1383 return 0; 1384 1385 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1386 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1387 PS_CPWM_RSP_SEQ_NUM); 1388 1389 if (rpwm_req_num != cpwm_rsp_seq) 1390 return -EPERM; 1391 1392 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1393 CPWM_SEQ_NUM_MAX; 1394 1395 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1396 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1397 return -EPERM; 1398 1399 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1400 if (cpwm_status != req_pwr_state) 1401 return -EPERM; 1402 1403 return 0; 1404 } 1405 1406 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1407 { 1408 enum rtw89_rpwm_req_pwr_state state; 1409 unsigned long delay = enter ? 10 : 150; 1410 int ret; 1411 int i; 1412 1413 if (enter) 1414 state = rtw89_mac_get_req_pwr_state(rtwdev); 1415 else 1416 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1417 1418 for (i = 0; i < RPWM_TRY_CNT; i++) { 1419 rtw89_mac_send_rpwm(rtwdev, state, false); 1420 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1421 !ret, delay, 15000, false, 1422 rtwdev, state); 1423 if (!ret) 1424 break; 1425 1426 if (i == RPWM_TRY_CNT - 1) 1427 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1428 enter ? "entering" : "leaving"); 1429 else 1430 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1431 "%d time firmware failed to ack for %s ps mode\n", 1432 i + 1, enter ? "entering" : "leaving"); 1433 } 1434 } 1435 1436 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1437 { 1438 enum rtw89_rpwm_req_pwr_state state; 1439 1440 state = rtw89_mac_get_req_pwr_state(rtwdev); 1441 rtw89_mac_send_rpwm(rtwdev, state, true); 1442 } 1443 1444 static void rtw89_mac_power_switch_boot_mode(struct rtw89_dev *rtwdev) 1445 { 1446 u32 boot_mode; 1447 1448 if (rtwdev->hci.type != RTW89_HCI_TYPE_USB) 1449 return; 1450 1451 boot_mode = rtw89_read32_mask(rtwdev, R_AX_GPIO_MUXCFG, B_AX_BOOT_MODE); 1452 if (!boot_mode) 1453 return; 1454 1455 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 1456 rtw89_write32_clr(rtwdev, R_AX_SYS_STATUS1, B_AX_AUTO_WLPON); 1457 rtw89_write32_clr(rtwdev, R_AX_GPIO_MUXCFG, B_AX_BOOT_MODE); 1458 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); 1459 } 1460 1461 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1462 { 1463 #define PWR_ACT 1 1464 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1465 const struct rtw89_chip_info *chip = rtwdev->chip; 1466 const struct rtw89_pwr_cfg * const *cfg_seq; 1467 int (*cfg_func)(struct rtw89_dev *rtwdev); 1468 int ret; 1469 u8 val; 1470 1471 rtw89_mac_power_switch_boot_mode(rtwdev); 1472 1473 if (on) { 1474 cfg_seq = chip->pwr_on_seq; 1475 cfg_func = chip->ops->pwr_on_func; 1476 } else { 1477 cfg_seq = chip->pwr_off_seq; 1478 cfg_func = chip->ops->pwr_off_func; 1479 } 1480 1481 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1482 __rtw89_leave_ps_mode(rtwdev); 1483 1484 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1485 if (on && val == PWR_ACT) { 1486 rtw89_err(rtwdev, "MAC has already powered on\n"); 1487 return -EBUSY; 1488 } 1489 1490 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1491 if (ret) 1492 return ret; 1493 1494 if (on) { 1495 if (!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags)) 1496 mac->efuse_read_fw_secure(rtwdev); 1497 1498 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1499 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1500 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1501 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1502 } else { 1503 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1504 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1505 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1506 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1507 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1508 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1509 rtw89_set_entity_state(rtwdev, RTW89_PHY_0, false); 1510 rtw89_set_entity_state(rtwdev, RTW89_PHY_1, false); 1511 } 1512 1513 return 0; 1514 #undef PWR_ACT 1515 } 1516 1517 int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev) 1518 { 1519 int ret; 1520 1521 ret = rtw89_mac_power_switch(rtwdev, true); 1522 if (ret) { 1523 rtw89_mac_power_switch(rtwdev, false); 1524 ret = rtw89_mac_power_switch(rtwdev, true); 1525 if (ret) 1526 return ret; 1527 } 1528 1529 return 0; 1530 } 1531 1532 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1533 { 1534 rtw89_mac_power_switch(rtwdev, false); 1535 } 1536 1537 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1538 { 1539 u32 func_en = 0; 1540 u32 ck_en = 0; 1541 u32 c1pc_en = 0; 1542 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1543 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1544 1545 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1546 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1547 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1548 B_AX_CMAC_CRPRT; 1549 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1550 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1551 B_AX_RMAC_CKEN; 1552 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1553 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1554 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1555 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1556 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1557 1558 if (en) { 1559 if (mac_idx == RTW89_MAC_1) { 1560 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1561 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1562 B_AX_R_SYM_ISO_CMAC12PP); 1563 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1564 B_AX_CMAC1_FEN); 1565 } 1566 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1567 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1568 } else { 1569 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1570 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1571 if (mac_idx == RTW89_MAC_1) { 1572 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1573 B_AX_CMAC1_FEN); 1574 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1575 B_AX_R_SYM_ISO_CMAC12PP); 1576 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1577 } 1578 } 1579 1580 return 0; 1581 } 1582 1583 static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1584 { 1585 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1586 u32 val32; 1587 1588 if (chip_id == RTL8852C) 1589 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1590 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1591 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1592 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1593 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1594 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1595 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1596 else 1597 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1598 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1599 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1600 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1601 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1602 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1603 B_AX_DMAC_CRPRT); 1604 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1605 1606 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1607 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1608 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1609 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1610 if (chip_id == RTL8852BT) 1611 val32 |= B_AX_AXIDMA_CLK_EN; 1612 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1613 1614 return 0; 1615 } 1616 1617 static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1618 { 1619 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1620 1621 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 1622 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1623 B_AX_OCP_L1_MASK); 1624 1625 return 0; 1626 } 1627 1628 static int sys_init_ax(struct rtw89_dev *rtwdev) 1629 { 1630 int ret; 1631 1632 ret = dmac_func_en_ax(rtwdev); 1633 if (ret) 1634 return ret; 1635 1636 ret = cmac_func_en_ax(rtwdev, 0, true); 1637 if (ret) 1638 return ret; 1639 1640 ret = chip_func_en_ax(rtwdev); 1641 if (ret) 1642 return ret; 1643 1644 return ret; 1645 } 1646 1647 const struct rtw89_mac_size_set rtw89_mac_size = { 1648 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1649 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0}, 1650 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0}, 1651 /* PCIE 64 */ 1652 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1653 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1654 /* DLFW */ 1655 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1656 .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1657 /* PCIE 64 */ 1658 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1659 /* 8852B PCIE SCC */ 1660 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1661 /* DLFW */ 1662 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1663 /* 8852C DLFW */ 1664 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1665 /* 8852C PCIE SCC */ 1666 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1667 .wde_size23 = {RTW89_WDE_PG_64, 1022, 2,}, 1668 /* 8852B USB2.0/USB3.0 SCC */ 1669 .wde_size25 = {RTW89_WDE_PG_64, 162, 94,}, 1670 /* PCIE */ 1671 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1672 .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1673 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1674 /* DLFW */ 1675 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1676 /* PCIE 64 */ 1677 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1678 /* DLFW */ 1679 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1680 .ple_size9 = {RTW89_PLE_PG_128, 2288, 16,}, 1681 /* 8852C DLFW */ 1682 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1683 /* 8852C PCIE SCC */ 1684 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1685 /* 8852B USB2.0 SCC */ 1686 .ple_size32 = {RTW89_PLE_PG_128, 620, 20,}, 1687 /* 8852B USB3.0 SCC */ 1688 .ple_size33 = {RTW89_PLE_PG_128, 632, 8,}, 1689 /* PCIE 64 */ 1690 .wde_qt0 = {3792, 196, 0, 107,}, 1691 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1692 /* DLFW */ 1693 .wde_qt4 = {0, 0, 0, 0,}, 1694 /* PCIE 64 */ 1695 .wde_qt6 = {448, 48, 0, 16,}, 1696 /* 8852B PCIE SCC */ 1697 .wde_qt7 = {446, 48, 0, 16,}, 1698 /* 8852C DLFW */ 1699 .wde_qt17 = {0, 0, 0, 0,}, 1700 /* 8852C PCIE SCC */ 1701 .wde_qt18 = {3228, 60, 0, 40,}, 1702 .wde_qt23 = {958, 48, 0, 16,}, 1703 /* 8852B USB2.0/USB3.0 SCC */ 1704 .wde_qt25 = {152, 2, 0, 8,}, 1705 .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 1706 .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1707 /* PCIE SCC */ 1708 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1709 /* PCIE SCC */ 1710 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1711 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1712 /* DLFW */ 1713 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1714 /* PCIE 64 */ 1715 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1716 /* DLFW 52C */ 1717 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1718 /* DLFW 52C */ 1719 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1720 /* 8852C PCIE SCC */ 1721 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1722 /* 8852C PCIE SCC */ 1723 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1724 .ple_qt57 = {147, 0, 16, 20, 13, 13, 178, 0, 32, 14, 8, 0,}, 1725 /* PCIE 64 */ 1726 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1727 .ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,}, 1728 /* USB2.0 52B SCC */ 1729 .ple_qt72 = {130, 0, 16, 48, 4, 13, 322, 0, 32, 14, 8, 0, 0,}, 1730 /* USB2.0 52B 92K */ 1731 .ple_qt73 = {130, 0, 32, 48, 37, 13, 355, 0, 65, 14, 24, 0, 0,}, 1732 /* USB3.0 52B 92K */ 1733 .ple_qt74 = {286, 0, 16, 48, 4, 13, 178, 0, 32, 14, 8, 0, 0,}, 1734 .ple_qt75 = {286, 0, 32, 48, 37, 13, 211, 0, 65, 14, 24, 0, 0,}, 1735 /* 8852A PCIE WOW */ 1736 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1737 /* 8852B PCIE WOW */ 1738 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1739 /* 8852BT PCIE WOW */ 1740 .ple_qt_52bt_wow = {147, 0, 32, 20, 1860, 13, 1929, 0, 1879, 14, 24, 0,}, 1741 /* 8851B PCIE WOW */ 1742 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1743 .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1744 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1745 .rsvd0_size0 = {212992, 0,}, 1746 .rsvd1_size0 = {587776, 2048,}, 1747 }; 1748 EXPORT_SYMBOL(rtw89_mac_size); 1749 1750 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1751 enum rtw89_qta_mode mode) 1752 { 1753 struct rtw89_mac_info *mac = &rtwdev->mac; 1754 const struct rtw89_dle_mem *cfg, *cfgs; 1755 1756 cfgs = rtwdev->chip->dle_mem[rtwdev->hci.dle_type]; 1757 if (!cfgs) 1758 return NULL; 1759 1760 cfg = &cfgs[mode]; 1761 if (cfg->mode != mode) { 1762 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1763 return NULL; 1764 } 1765 1766 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1767 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1768 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1769 mac->dle_info.qta_mode = mode; 1770 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1771 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1772 1773 return cfg; 1774 } 1775 1776 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1777 enum rtw89_mac_dle_rsvd_qt_type type, 1778 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1779 { 1780 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1781 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1782 1783 switch (type) { 1784 case DLE_RSVD_QT_MPDU_INFO: 1785 cfg->pktid = dle_info->ple_free_pg; 1786 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1787 break; 1788 case DLE_RSVD_QT_B0_CSI: 1789 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1790 cfg->pg_num = rsvd_qt->b0_csi; 1791 break; 1792 case DLE_RSVD_QT_B1_CSI: 1793 cfg->pktid = dle_info->ple_free_pg + 1794 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1795 cfg->pg_num = rsvd_qt->b1_csi; 1796 break; 1797 case DLE_RSVD_QT_B0_LMR: 1798 cfg->pktid = dle_info->ple_free_pg + 1799 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1800 cfg->pg_num = rsvd_qt->b0_lmr; 1801 break; 1802 case DLE_RSVD_QT_B1_LMR: 1803 cfg->pktid = dle_info->ple_free_pg + 1804 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1805 rsvd_qt->b0_lmr; 1806 cfg->pg_num = rsvd_qt->b1_lmr; 1807 break; 1808 case DLE_RSVD_QT_B0_FTM: 1809 cfg->pktid = dle_info->ple_free_pg + 1810 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1811 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1812 cfg->pg_num = rsvd_qt->b0_ftm; 1813 break; 1814 case DLE_RSVD_QT_B1_FTM: 1815 cfg->pktid = dle_info->ple_free_pg + 1816 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1817 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1818 cfg->pg_num = rsvd_qt->b1_ftm; 1819 break; 1820 default: 1821 return -EINVAL; 1822 } 1823 1824 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1825 1826 return 0; 1827 } 1828 1829 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1830 { 1831 struct rtw89_mac_dle_dfi_qempty qempty; 1832 u32 grpnum, qtmp, val32, msk32; 1833 int i, j, ret; 1834 1835 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1836 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1837 1838 for (i = 0; i < grpnum; i++) { 1839 qempty.grpsel = i; 1840 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1841 if (ret) { 1842 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1843 return false; 1844 } 1845 qtmp = qempty.qempty; 1846 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1847 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 1848 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1849 return false; 1850 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1851 } 1852 } 1853 1854 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1855 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1856 if (ret) { 1857 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1858 return false; 1859 } 1860 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1861 if ((qempty.qempty & msk32) != msk32) 1862 return false; 1863 1864 if (rtwdev->dbcc_en) { 1865 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1866 if ((qempty.qempty & msk32) != msk32) 1867 return false; 1868 } 1869 1870 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1871 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1872 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1873 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1874 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1875 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1876 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1877 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1878 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1879 1880 return (val32 & msk32) == msk32; 1881 } 1882 1883 static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1884 { 1885 const struct rtw89_dle_size *wde = cfg->wde_size; 1886 const struct rtw89_dle_size *ple = cfg->ple_size; 1887 u32 used; 1888 1889 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1890 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1891 1892 if (cfg->rsvd0_size && cfg->rsvd1_size) { 1893 used += cfg->rsvd0_size->size; 1894 used += cfg->rsvd1_size->size; 1895 } 1896 1897 return used; 1898 } 1899 1900 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1901 enum rtw89_qta_mode mode) 1902 { 1903 u32 size = rtwdev->chip->fifo_size; 1904 1905 if (mode == RTW89_QTA_SCC) 1906 size -= rtwdev->chip->dle_scc_rsvd_size; 1907 1908 return size; 1909 } 1910 1911 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 1912 { 1913 if (enable) 1914 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1915 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1916 else 1917 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1918 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1919 } 1920 1921 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 1922 { 1923 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1924 1925 if (enable) { 1926 if (rtwdev->chip->chip_id == RTL8851B) 1927 val |= B_AX_AXIDMA_CLK_EN; 1928 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1929 } else { 1930 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1931 } 1932 } 1933 1934 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1935 { 1936 const struct rtw89_dle_size *size_cfg; 1937 u32 val; 1938 u8 bound = 0; 1939 1940 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1941 size_cfg = cfg->wde_size; 1942 1943 switch (size_cfg->pge_size) { 1944 default: 1945 case RTW89_WDE_PG_64: 1946 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1947 B_AX_WDE_PAGE_SEL_MASK); 1948 break; 1949 case RTW89_WDE_PG_128: 1950 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1951 B_AX_WDE_PAGE_SEL_MASK); 1952 break; 1953 case RTW89_WDE_PG_256: 1954 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1955 return -EINVAL; 1956 } 1957 1958 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1959 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1960 B_AX_WDE_FREE_PAGE_NUM_MASK); 1961 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1962 1963 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1964 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1965 * size_cfg->pge_size / DLE_BOUND_UNIT; 1966 size_cfg = cfg->ple_size; 1967 1968 switch (size_cfg->pge_size) { 1969 default: 1970 case RTW89_PLE_PG_64: 1971 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1972 return -EINVAL; 1973 case RTW89_PLE_PG_128: 1974 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1975 B_AX_PLE_PAGE_SEL_MASK); 1976 break; 1977 case RTW89_PLE_PG_256: 1978 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1979 B_AX_PLE_PAGE_SEL_MASK); 1980 break; 1981 } 1982 1983 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1984 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1985 B_AX_PLE_FREE_PAGE_NUM_MASK); 1986 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1987 1988 return 0; 1989 } 1990 1991 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 1992 { 1993 u32 reg, mask; 1994 u32 ini; 1995 1996 if (wde_or_ple) { 1997 reg = R_AX_WDE_INI_STATUS; 1998 mask = WDE_MGN_INI_RDY; 1999 } else { 2000 reg = R_AX_PLE_INI_STATUS; 2001 mask = PLE_MGN_INI_RDY; 2002 } 2003 2004 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 2005 2000, false, rtwdev, reg); 2006 } 2007 2008 #define INVALID_QT_WCPU U16_MAX 2009 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 2010 do { \ 2011 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 2012 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 2013 rtw89_write32(rtwdev, \ 2014 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 2015 val); \ 2016 } while (0) 2017 #define SET_QUOTA(_x, _module, _idx) \ 2018 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 2019 2020 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 2021 const struct rtw89_wde_quota *min_cfg, 2022 const struct rtw89_wde_quota *max_cfg, 2023 u16 ext_wde_min_qt_wcpu) 2024 { 2025 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 2026 ext_wde_min_qt_wcpu : min_cfg->wcpu; 2027 u32 val; 2028 2029 SET_QUOTA(hif, WDE, 0); 2030 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 2031 SET_QUOTA(pkt_in, WDE, 3); 2032 SET_QUOTA(cpu_io, WDE, 4); 2033 } 2034 2035 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 2036 const struct rtw89_ple_quota *min_cfg, 2037 const struct rtw89_ple_quota *max_cfg) 2038 { 2039 u32 val; 2040 2041 SET_QUOTA(cma0_tx, PLE, 0); 2042 SET_QUOTA(cma1_tx, PLE, 1); 2043 SET_QUOTA(c2h, PLE, 2); 2044 SET_QUOTA(h2c, PLE, 3); 2045 SET_QUOTA(wcpu, PLE, 4); 2046 SET_QUOTA(mpdu_proc, PLE, 5); 2047 SET_QUOTA(cma0_dma, PLE, 6); 2048 SET_QUOTA(cma1_dma, PLE, 7); 2049 SET_QUOTA(bb_rpt, PLE, 8); 2050 SET_QUOTA(wd_rel, PLE, 9); 2051 SET_QUOTA(cpu_io, PLE, 10); 2052 if (rtwdev->chip->chip_id == RTL8852C) 2053 SET_QUOTA(tx_rpt, PLE, 11); 2054 } 2055 2056 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 2057 { 2058 const struct rtw89_ple_quota *min_cfg, *max_cfg; 2059 const struct rtw89_dle_mem *cfg; 2060 u32 val; 2061 2062 if (rtwdev->chip->chip_id == RTL8852C) 2063 return 0; 2064 2065 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2066 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2067 return -EINVAL; 2068 } 2069 2070 if (wow) 2071 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2072 else 2073 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2074 if (!cfg) { 2075 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2076 return -EINVAL; 2077 } 2078 2079 min_cfg = cfg->ple_min_qt; 2080 max_cfg = cfg->ple_max_qt; 2081 SET_QUOTA(cma0_dma, PLE, 6); 2082 SET_QUOTA(cma1_dma, PLE, 7); 2083 2084 return 0; 2085 } 2086 #undef SET_QUOTA 2087 2088 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2089 { 2090 const struct rtw89_chip_info *chip = rtwdev->chip; 2091 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2092 2093 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2094 return; 2095 2096 /* 8852C enable B_AX_UC_MGNT_DEC by default */ 2097 if (chip->chip_id == RTL8852C) 2098 msk32 = B_AX_BMC_MGNT_DEC; 2099 2100 if (enable) 2101 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2102 else 2103 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2104 } 2105 2106 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2107 const struct rtw89_dle_mem *cfg, 2108 u16 ext_wde_min_qt_wcpu) 2109 { 2110 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2111 2112 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2113 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2114 } 2115 2116 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2117 enum rtw89_qta_mode ext_mode) 2118 { 2119 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2120 const struct rtw89_dle_mem *cfg, *ext_cfg; 2121 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2122 int ret; 2123 2124 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2125 if (ret) 2126 return ret; 2127 2128 cfg = get_dle_mem_cfg(rtwdev, mode); 2129 if (!cfg) { 2130 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2131 ret = -EINVAL; 2132 goto error; 2133 } 2134 2135 if (mode == RTW89_QTA_DLFW) { 2136 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2137 if (!ext_cfg) { 2138 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2139 ext_mode); 2140 ret = -EINVAL; 2141 goto error; 2142 } 2143 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2144 } 2145 2146 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2147 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2148 ret = -EINVAL; 2149 goto error; 2150 } 2151 2152 mac->dle_func_en(rtwdev, false); 2153 mac->dle_clk_en(rtwdev, true); 2154 2155 ret = mac->dle_mix_cfg(rtwdev, cfg); 2156 if (ret) { 2157 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2158 goto error; 2159 } 2160 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2161 2162 mac->dle_func_en(rtwdev, true); 2163 2164 ret = mac->chk_dle_rdy(rtwdev, true); 2165 if (ret) { 2166 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2167 return ret; 2168 } 2169 2170 ret = mac->chk_dle_rdy(rtwdev, false); 2171 if (ret) { 2172 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2173 return ret; 2174 } 2175 2176 return 0; 2177 error: 2178 mac->dle_func_en(rtwdev, false); 2179 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2180 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2181 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2182 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2183 2184 return ret; 2185 } 2186 2187 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2188 enum rtw89_qta_mode mode) 2189 { 2190 u32 reg, max_preld_size, min_rsvd_size; 2191 2192 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2193 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2194 reg = mac_idx == RTW89_MAC_0 ? 2195 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2196 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2197 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2198 2199 min_rsvd_size = PRELD_AMSDU_SIZE; 2200 reg = mac_idx == RTW89_MAC_0 ? 2201 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2202 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2203 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2204 2205 return 0; 2206 } 2207 2208 static bool is_qta_poh(struct rtw89_dev *rtwdev) 2209 { 2210 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2211 } 2212 2213 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2214 enum rtw89_qta_mode mode) 2215 { 2216 const struct rtw89_chip_info *chip = rtwdev->chip; 2217 2218 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) || 2219 !is_qta_poh(rtwdev)) 2220 return 0; 2221 2222 return preload_init_set(rtwdev, mac_idx, mode); 2223 } 2224 2225 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2226 { 2227 u32 msk32; 2228 u32 val32; 2229 2230 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2231 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2232 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2233 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2234 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2235 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2236 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2237 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2238 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2239 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2240 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2241 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2242 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2243 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2244 2245 if ((val32 & msk32) == msk32) 2246 return true; 2247 2248 return false; 2249 } 2250 2251 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2252 { 2253 const struct rtw89_chip_info *chip = rtwdev->chip; 2254 2255 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2256 return; 2257 2258 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2259 SS2F_PATH_WLCPU); 2260 } 2261 2262 static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2263 { 2264 u32 p_val; 2265 u8 val; 2266 int ret; 2267 2268 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2269 if (ret) 2270 return ret; 2271 2272 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2273 val |= B_AX_SS_EN; 2274 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2275 2276 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2277 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2278 if (ret) { 2279 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2280 return ret; 2281 } 2282 2283 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2284 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2285 2286 _patch_ss2f_path(rtwdev); 2287 2288 return 0; 2289 } 2290 2291 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2292 { 2293 int ret; 2294 2295 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2296 if (ret) 2297 return ret; 2298 2299 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2300 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2301 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2302 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2303 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2304 2305 return 0; 2306 } 2307 2308 static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2309 { 2310 const struct rtw89_chip_info *chip = rtwdev->chip; 2311 u32 val = 0; 2312 int ret; 2313 2314 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2315 if (ret) 2316 return ret; 2317 2318 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2319 /* init clock */ 2320 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2321 /* init TX encryption */ 2322 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2323 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2324 if (chip->chip_id == RTL8852C) 2325 val |= B_AX_UC_MGNT_DEC; 2326 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2327 chip->chip_id == RTL8851B) 2328 val &= ~B_AX_TX_PARTIAL_MODE; 2329 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2330 2331 /* init MIC ICV append */ 2332 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2333 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2334 2335 /* option init */ 2336 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2337 2338 if (chip->chip_id == RTL8852C) 2339 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2340 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2341 2342 return 0; 2343 } 2344 2345 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2346 { 2347 int ret; 2348 2349 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2350 if (ret) { 2351 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2352 return ret; 2353 } 2354 2355 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2356 if (ret) { 2357 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2358 return ret; 2359 } 2360 2361 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2362 if (ret) { 2363 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2364 return ret; 2365 } 2366 2367 ret = sta_sch_init_ax(rtwdev); 2368 if (ret) { 2369 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2370 return ret; 2371 } 2372 2373 ret = mpdu_proc_init_ax(rtwdev); 2374 if (ret) { 2375 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2376 return ret; 2377 } 2378 2379 ret = sec_eng_init_ax(rtwdev); 2380 if (ret) { 2381 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2382 return ret; 2383 } 2384 2385 return ret; 2386 } 2387 2388 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2389 { 2390 u32 val, reg; 2391 u16 p_val; 2392 int ret; 2393 2394 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2395 if (ret) 2396 return ret; 2397 2398 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2399 2400 val = rtw89_read32(rtwdev, reg); 2401 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2402 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2403 rtw89_write32(rtwdev, reg, val); 2404 2405 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2406 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2407 if (ret) { 2408 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2409 return ret; 2410 } 2411 2412 return 0; 2413 } 2414 2415 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2416 { 2417 int ret; 2418 u32 reg; 2419 u32 val; 2420 2421 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2422 if (ret) 2423 return ret; 2424 2425 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2426 if (rtwdev->chip->chip_id == RTL8852C) 2427 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2428 SIFS_MACTXEN_T1_V1); 2429 else 2430 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2431 SIFS_MACTXEN_T1); 2432 2433 if (rtw89_is_rtl885xb(rtwdev)) { 2434 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2435 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2436 } 2437 2438 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2439 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2440 2441 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2442 if (rtwdev->chip->chip_id == RTL8852C) { 2443 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2444 B_AX_TX_PARTIAL_MODE); 2445 if (!val) 2446 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2447 SCH_PREBKF_24US); 2448 } else { 2449 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2450 SCH_PREBKF_24US); 2451 } 2452 2453 return 0; 2454 } 2455 2456 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2457 enum rtw89_machdr_frame_type type, 2458 enum rtw89_mac_fwd_target fwd_target, 2459 u8 mac_idx) 2460 { 2461 u32 reg; 2462 u32 val; 2463 2464 switch (fwd_target) { 2465 case RTW89_FWD_DONT_CARE: 2466 val = RX_FLTR_FRAME_DROP; 2467 break; 2468 case RTW89_FWD_TO_HOST: 2469 val = RX_FLTR_FRAME_TO_HOST; 2470 break; 2471 case RTW89_FWD_TO_WLAN_CPU: 2472 val = RX_FLTR_FRAME_TO_WLCPU; 2473 break; 2474 default: 2475 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2476 return -EINVAL; 2477 } 2478 2479 switch (type) { 2480 case RTW89_MGNT: 2481 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2482 break; 2483 case RTW89_CTRL: 2484 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2485 break; 2486 case RTW89_DATA: 2487 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2488 break; 2489 default: 2490 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2491 return -EINVAL; 2492 } 2493 rtw89_write32(rtwdev, reg, val); 2494 2495 return 0; 2496 } 2497 2498 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2499 { 2500 int ret, i; 2501 u32 mac_ftlr, plcp_ftlr; 2502 2503 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2504 if (ret) 2505 return ret; 2506 2507 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2508 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2509 mac_idx); 2510 if (ret) 2511 return ret; 2512 } 2513 mac_ftlr = rtwdev->hal.rx_fltr; 2514 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2515 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2516 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2517 B_AX_HE_SIGB_CRC_CHK; 2518 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2519 mac_ftlr); 2520 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2521 plcp_ftlr); 2522 2523 return 0; 2524 } 2525 2526 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2527 { 2528 u32 reg, val32; 2529 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2530 2531 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2532 B_AX_RSP_CHK_BASIC_NAV; 2533 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2534 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2535 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2536 2537 switch (rtwdev->chip->chip_id) { 2538 case RTL8852A: 2539 case RTL8852B: 2540 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2541 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2542 rtw89_write32(rtwdev, reg, val32); 2543 2544 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2545 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2546 rtw89_write32(rtwdev, reg, val32); 2547 break; 2548 default: 2549 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2550 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2551 rtw89_write32(rtwdev, reg, val32); 2552 2553 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2554 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2555 rtw89_write32(rtwdev, reg, val32); 2556 break; 2557 } 2558 } 2559 2560 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2561 { 2562 u32 val, reg; 2563 int ret; 2564 2565 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2566 if (ret) 2567 return ret; 2568 2569 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2570 val = rtw89_read32(rtwdev, reg); 2571 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2572 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2573 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2574 B_AX_CTN_CHK_INTRA_NAV | 2575 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2576 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2577 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2578 B_AX_CTN_CHK_CCA_P20); 2579 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2580 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2581 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2582 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2583 B_AX_SIFS_CHK_EDCCA); 2584 2585 rtw89_write32(rtwdev, reg, val); 2586 2587 _patch_dis_resp_chk(rtwdev, mac_idx); 2588 2589 return 0; 2590 } 2591 2592 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2593 { 2594 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2595 B_AX_WMAC_TF_UP_NAV_EN | 2596 B_AX_WMAC_NAV_UPPER_EN); 2597 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2598 2599 return 0; 2600 } 2601 2602 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2603 { 2604 u32 reg; 2605 int ret; 2606 2607 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2608 if (ret) 2609 return ret; 2610 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2611 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2612 2613 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2614 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2615 2616 return 0; 2617 } 2618 2619 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2620 { 2621 u32 reg; 2622 int ret; 2623 2624 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2625 if (ret) 2626 return ret; 2627 2628 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2629 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2630 2631 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2632 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2633 2634 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2635 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2636 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2637 2638 return 0; 2639 } 2640 2641 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2642 { 2643 const struct rtw89_chip_info *chip = rtwdev->chip; 2644 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2645 u32 reg, val, sifs; 2646 int ret; 2647 2648 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2649 if (ret) 2650 return ret; 2651 2652 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2653 val = rtw89_read32(rtwdev, reg); 2654 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2655 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2656 2657 switch (rtwdev->chip->chip_id) { 2658 case RTL8852A: 2659 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2660 break; 2661 case RTL8851B: 2662 case RTL8852B: 2663 case RTL8852BT: 2664 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2665 break; 2666 default: 2667 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2668 break; 2669 } 2670 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2671 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2672 rtw89_write32(rtwdev, reg, val); 2673 2674 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2675 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2676 2677 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2678 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2679 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2680 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2681 2682 return 0; 2683 } 2684 2685 static void rst_bacam(struct rtw89_dev *rtwdev) 2686 { 2687 u32 val32; 2688 int ret; 2689 2690 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2691 S_AX_BACAM_RST_ALL); 2692 2693 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2694 1, 1000, false, 2695 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2696 if (ret) 2697 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2698 } 2699 2700 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2701 { 2702 #define TRXCFG_RMAC_CCA_TO 32 2703 #define TRXCFG_RMAC_DATA_TO 15 2704 #define RX_MAX_LEN_UNIT 512 2705 #define PLD_RLS_MAX_PG 127 2706 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2707 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2708 int ret; 2709 u32 reg, rx_max_len, rx_qta; 2710 u16 val; 2711 2712 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2713 if (ret) 2714 return ret; 2715 2716 if (mac_idx == RTW89_MAC_0) 2717 rst_bacam(rtwdev); 2718 2719 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2720 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2721 2722 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2723 val = rtw89_read16(rtwdev, reg); 2724 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2725 B_AX_RX_DLK_DATA_TIME_MASK); 2726 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2727 B_AX_RX_DLK_CCA_TIME_MASK); 2728 if (chip_id == RTL8852BT) 2729 val |= B_AX_RX_DLK_RST_EN; 2730 rtw89_write16(rtwdev, reg, val); 2731 2732 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2733 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2734 2735 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2736 if (mac_idx == RTW89_MAC_0) 2737 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2738 else 2739 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2740 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2741 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2742 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2743 rx_max_len /= RX_MAX_LEN_UNIT; 2744 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2745 2746 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) { 2747 rtw89_write16_mask(rtwdev, 2748 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2749 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2750 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2751 BIT(12)); 2752 } 2753 2754 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2755 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2756 2757 return ret; 2758 } 2759 2760 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2761 { 2762 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2763 u32 val, reg; 2764 int ret; 2765 2766 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2767 if (ret) 2768 return ret; 2769 2770 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2771 val = rtw89_read32(rtwdev, reg); 2772 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2773 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2774 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2775 rtw89_write32(rtwdev, reg, val); 2776 2777 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2778 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2779 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2780 } 2781 2782 return 0; 2783 } 2784 2785 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2786 { 2787 const struct rtw89_dle_mem *cfg; 2788 2789 cfg = get_dle_mem_cfg(rtwdev, mode); 2790 if (!cfg) { 2791 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2792 return false; 2793 } 2794 2795 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2796 } 2797 2798 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2799 { 2800 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2801 u32 val, reg; 2802 int ret; 2803 2804 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2805 if (ret) 2806 return ret; 2807 2808 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2809 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2810 val = rtw89_read32(rtwdev, reg); 2811 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2812 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2813 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2814 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2815 val |= B_AX_HW_CTS2SELF_EN; 2816 rtw89_write32(rtwdev, reg, val); 2817 2818 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2819 val = rtw89_read32(rtwdev, reg); 2820 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2821 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2822 rtw89_write32(rtwdev, reg, val); 2823 } 2824 2825 if (mac_idx == RTW89_MAC_0) { 2826 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2827 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2828 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2829 B_AX_PTCL_TRIGGER_SS_EN_0 | 2830 B_AX_PTCL_TRIGGER_SS_EN_1 | 2831 B_AX_PTCL_TRIGGER_SS_EN_UL); 2832 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2833 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2834 } else if (mac_idx == RTW89_MAC_1) { 2835 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2836 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2837 } 2838 2839 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2840 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_VHT_0, mac_idx); 2841 rtw89_write32_mask(rtwdev, reg, 2842 B_AX_AMPDU_MAX_LEN_VHT_MASK, 0x3FF80); 2843 } 2844 2845 return 0; 2846 } 2847 2848 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2849 { 2850 u32 reg; 2851 int ret; 2852 2853 if (!rtw89_is_rtl885xb(rtwdev)) 2854 return 0; 2855 2856 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2857 if (ret) 2858 return ret; 2859 2860 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2861 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2862 2863 return 0; 2864 } 2865 2866 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2867 { 2868 int ret; 2869 2870 ret = scheduler_init_ax(rtwdev, mac_idx); 2871 if (ret) { 2872 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2873 return ret; 2874 } 2875 2876 ret = addr_cam_init_ax(rtwdev, mac_idx); 2877 if (ret) { 2878 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2879 ret); 2880 return ret; 2881 } 2882 2883 ret = rx_fltr_init_ax(rtwdev, mac_idx); 2884 if (ret) { 2885 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2886 ret); 2887 return ret; 2888 } 2889 2890 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 2891 if (ret) { 2892 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2893 ret); 2894 return ret; 2895 } 2896 2897 ret = nav_ctrl_init_ax(rtwdev); 2898 if (ret) { 2899 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2900 ret); 2901 return ret; 2902 } 2903 2904 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 2905 if (ret) { 2906 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2907 mac_idx, ret); 2908 return ret; 2909 } 2910 2911 ret = tmac_init_ax(rtwdev, mac_idx); 2912 if (ret) { 2913 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2914 return ret; 2915 } 2916 2917 ret = trxptcl_init_ax(rtwdev, mac_idx); 2918 if (ret) { 2919 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2920 return ret; 2921 } 2922 2923 ret = rmac_init_ax(rtwdev, mac_idx); 2924 if (ret) { 2925 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2926 return ret; 2927 } 2928 2929 ret = cmac_com_init_ax(rtwdev, mac_idx); 2930 if (ret) { 2931 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2932 return ret; 2933 } 2934 2935 ret = ptcl_init_ax(rtwdev, mac_idx); 2936 if (ret) { 2937 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2938 return ret; 2939 } 2940 2941 ret = cmac_dma_init_ax(rtwdev, mac_idx); 2942 if (ret) { 2943 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2944 return ret; 2945 } 2946 2947 return ret; 2948 } 2949 2950 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2951 struct rtw89_mac_c2h_info *c2h_info, u8 part_num) 2952 { 2953 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2954 const struct rtw89_chip_info *chip = rtwdev->chip; 2955 struct rtw89_mac_h2c_info h2c_info = {}; 2956 enum rtw89_mac_c2h_type c2h_type; 2957 u8 content_len; 2958 int ret; 2959 2960 if (chip->chip_gen == RTW89_CHIP_AX) 2961 content_len = 0; 2962 else 2963 content_len = 2; 2964 2965 switch (part_num) { 2966 case 0: 2967 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP; 2968 break; 2969 case 1: 2970 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1; 2971 break; 2972 default: 2973 return -EINVAL; 2974 } 2975 2976 mac->cnv_efuse_state(rtwdev, false); 2977 2978 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2979 h2c_info.content_len = content_len; 2980 h2c_info.u.hdr.w0 = u32_encode_bits(part_num, RTW89_H2CREG_GET_FEATURE_PART_NUM); 2981 2982 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2983 if (ret) 2984 goto out; 2985 2986 if (c2h_info->id != c2h_type) 2987 ret = -EINVAL; 2988 2989 out: 2990 mac->cnv_efuse_state(rtwdev, true); 2991 2992 return ret; 2993 } 2994 2995 static int rtw89_mac_setup_phycap_part0(struct rtw89_dev *rtwdev) 2996 { 2997 const struct rtw89_chip_info *chip = rtwdev->chip; 2998 const struct rtw89_c2hreg_phycap *phycap; 2999 struct rtw89_efuse *efuse = &rtwdev->efuse; 3000 struct rtw89_mac_c2h_info c2h_info = {}; 3001 struct rtw89_hal *hal = &rtwdev->hal; 3002 u8 tx_nss; 3003 u8 rx_nss; 3004 u8 tx_ant; 3005 u8 rx_ant; 3006 int ret; 3007 3008 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 0); 3009 if (ret) 3010 return ret; 3011 3012 phycap = &c2h_info.u.phycap; 3013 3014 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 3015 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 3016 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 3017 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 3018 3019 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 3020 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 3021 3022 if (tx_ant == 1) 3023 hal->antenna_tx = RF_B; 3024 if (rx_ant == 1) 3025 hal->antenna_rx = RF_B; 3026 3027 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 3028 hal->antenna_tx = RF_B; 3029 hal->tx_path_diversity = true; 3030 } 3031 3032 if (chip->rf_path_num == 1) { 3033 hal->antenna_tx = RF_A; 3034 hal->antenna_rx = RF_A; 3035 if ((efuse->rfe_type % 3) == 2) 3036 hal->ant_diversity = true; 3037 } 3038 3039 rtw89_debug(rtwdev, RTW89_DBG_FW, 3040 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 3041 hal->tx_nss, tx_nss, chip->tx_nss, 3042 hal->rx_nss, rx_nss, chip->rx_nss); 3043 rtw89_debug(rtwdev, RTW89_DBG_FW, 3044 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 3045 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 3046 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 3047 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 3048 3049 return 0; 3050 } 3051 3052 static int rtw89_mac_setup_phycap_part1(struct rtw89_dev *rtwdev) 3053 { 3054 const struct rtw89_chip_variant *variant = rtwdev->variant; 3055 const struct rtw89_c2hreg_phycap *phycap; 3056 struct rtw89_mac_c2h_info c2h_info = {}; 3057 struct rtw89_hal *hal = &rtwdev->hal; 3058 u8 qam_raw, qam; 3059 int ret; 3060 3061 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 1); 3062 if (ret) 3063 return ret; 3064 3065 phycap = &c2h_info.u.phycap; 3066 3067 qam_raw = u32_get_bits(phycap->w2, RTW89_C2HREG_PHYCAP_P1_W2_QAM); 3068 3069 switch (qam_raw) { 3070 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_256: 3071 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024: 3072 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096: 3073 qam = qam_raw; 3074 break; 3075 default: 3076 qam = RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096; 3077 break; 3078 } 3079 3080 if ((variant && variant->no_mcs_12_13) || 3081 qam <= RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024) 3082 hal->no_mcs_12_13 = true; 3083 3084 rtw89_debug(rtwdev, RTW89_DBG_FW, "phycap qam=%d/%d no_mcs_12_13=%d\n", 3085 qam_raw, qam, hal->no_mcs_12_13); 3086 3087 return 0; 3088 } 3089 3090 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 3091 { 3092 const struct rtw89_chip_info *chip = rtwdev->chip; 3093 int ret; 3094 3095 ret = rtw89_mac_setup_phycap_part0(rtwdev); 3096 if (ret) 3097 return ret; 3098 3099 if (chip->chip_gen == RTW89_CHIP_AX || 3100 RTW89_CHK_FW_FEATURE(NO_PHYCAP_P1, &rtwdev->fw)) 3101 return 0; 3102 3103 return rtw89_mac_setup_phycap_part1(rtwdev); 3104 } 3105 3106 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 3107 u16 tx_en_u16, u16 mask_u16) 3108 { 3109 struct rtw89_mac_c2h_info c2h_info = {0}; 3110 struct rtw89_mac_h2c_info h2c_info = {0}; 3111 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 3112 int ret; 3113 3114 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 3115 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 3116 3117 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 3118 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 3119 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 3120 3121 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 3122 if (ret) 3123 return ret; 3124 3125 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 3126 return -EINVAL; 3127 3128 return 0; 3129 } 3130 3131 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 3132 u16 tx_en, u16 tx_en_mask) 3133 { 3134 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 3135 u16 val; 3136 int ret; 3137 3138 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3139 if (ret) 3140 return ret; 3141 3142 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3143 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 3144 tx_en, tx_en_mask); 3145 3146 val = rtw89_read16(rtwdev, reg); 3147 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3148 rtw89_write16(rtwdev, reg, val); 3149 3150 return 0; 3151 } 3152 3153 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3154 u32 tx_en, u32 tx_en_mask) 3155 { 3156 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3157 u32 val; 3158 int ret; 3159 3160 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3161 if (ret) 3162 return ret; 3163 3164 val = rtw89_read32(rtwdev, reg); 3165 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3166 rtw89_write32(rtwdev, reg, val); 3167 3168 return 0; 3169 } 3170 3171 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3172 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3173 { 3174 int ret; 3175 3176 *tx_en = rtw89_read16(rtwdev, 3177 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3178 3179 switch (sel) { 3180 case RTW89_SCH_TX_SEL_ALL: 3181 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3182 B_AX_CTN_TXEN_ALL_MASK); 3183 if (ret) 3184 return ret; 3185 break; 3186 case RTW89_SCH_TX_SEL_HIQ: 3187 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3188 0, B_AX_CTN_TXEN_HGQ); 3189 if (ret) 3190 return ret; 3191 break; 3192 case RTW89_SCH_TX_SEL_MG0: 3193 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3194 0, B_AX_CTN_TXEN_MGQ); 3195 if (ret) 3196 return ret; 3197 break; 3198 case RTW89_SCH_TX_SEL_MACID: 3199 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3200 B_AX_CTN_TXEN_ALL_MASK); 3201 if (ret) 3202 return ret; 3203 break; 3204 default: 3205 return 0; 3206 } 3207 3208 return 0; 3209 } 3210 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3211 3212 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3213 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3214 { 3215 int ret; 3216 3217 *tx_en = rtw89_read32(rtwdev, 3218 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3219 3220 switch (sel) { 3221 case RTW89_SCH_TX_SEL_ALL: 3222 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3223 B_AX_CTN_TXEN_ALL_MASK_V1); 3224 if (ret) 3225 return ret; 3226 break; 3227 case RTW89_SCH_TX_SEL_HIQ: 3228 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3229 0, B_AX_CTN_TXEN_HGQ); 3230 if (ret) 3231 return ret; 3232 break; 3233 case RTW89_SCH_TX_SEL_MG0: 3234 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3235 0, B_AX_CTN_TXEN_MGQ); 3236 if (ret) 3237 return ret; 3238 break; 3239 case RTW89_SCH_TX_SEL_MACID: 3240 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3241 B_AX_CTN_TXEN_ALL_MASK_V1); 3242 if (ret) 3243 return ret; 3244 break; 3245 default: 3246 return 0; 3247 } 3248 3249 return 0; 3250 } 3251 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3252 3253 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3254 { 3255 int ret; 3256 3257 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3258 if (ret) 3259 return ret; 3260 3261 return 0; 3262 } 3263 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3264 3265 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3266 { 3267 int ret; 3268 3269 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3270 B_AX_CTN_TXEN_ALL_MASK_V1); 3271 if (ret) 3272 return ret; 3273 3274 return 0; 3275 } 3276 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3277 3278 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3279 { 3280 u32 val, reg; 3281 int ret; 3282 3283 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3284 val = buf_len; 3285 val |= B_AX_WD_BUF_REQ_EXEC; 3286 rtw89_write32(rtwdev, reg, val); 3287 3288 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3289 3290 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3291 1, 2000, false, rtwdev, reg); 3292 if (ret) 3293 return ret; 3294 3295 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3296 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3297 return -ENOENT; 3298 3299 return 0; 3300 } 3301 3302 static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3303 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3304 { 3305 u32 val, cmd_type, reg; 3306 int ret; 3307 3308 cmd_type = ctrl_para->cmd_type; 3309 3310 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3311 val = 0; 3312 val = u32_replace_bits(val, ctrl_para->start_pktid, 3313 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3314 val = u32_replace_bits(val, ctrl_para->end_pktid, 3315 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3316 rtw89_write32(rtwdev, reg, val); 3317 3318 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3319 val = 0; 3320 val = u32_replace_bits(val, ctrl_para->src_pid, 3321 B_AX_CPUQ_OP_SRC_PID_MASK); 3322 val = u32_replace_bits(val, ctrl_para->src_qid, 3323 B_AX_CPUQ_OP_SRC_QID_MASK); 3324 val = u32_replace_bits(val, ctrl_para->dst_pid, 3325 B_AX_CPUQ_OP_DST_PID_MASK); 3326 val = u32_replace_bits(val, ctrl_para->dst_qid, 3327 B_AX_CPUQ_OP_DST_QID_MASK); 3328 rtw89_write32(rtwdev, reg, val); 3329 3330 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3331 val = 0; 3332 val = u32_replace_bits(val, cmd_type, 3333 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3334 val = u32_replace_bits(val, ctrl_para->macid, 3335 B_AX_CPUQ_OP_MACID_MASK); 3336 val = u32_replace_bits(val, ctrl_para->pkt_num, 3337 B_AX_CPUQ_OP_PKTNUM_MASK); 3338 val |= B_AX_WD_CPUQ_OP_EXEC; 3339 rtw89_write32(rtwdev, reg, val); 3340 3341 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3342 3343 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3344 1, 2000, false, rtwdev, reg); 3345 if (ret) 3346 return ret; 3347 3348 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3349 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3350 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3351 3352 return 0; 3353 } 3354 3355 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3356 bool band1_en) 3357 { 3358 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3359 const struct rtw89_dle_mem *cfg; 3360 3361 cfg = get_dle_mem_cfg(rtwdev, mode); 3362 if (!cfg) { 3363 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3364 return -EINVAL; 3365 } 3366 3367 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3368 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3369 return -EINVAL; 3370 } 3371 3372 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3373 3374 return mac->dle_quota_change(rtwdev, band1_en); 3375 } 3376 3377 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3378 { 3379 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3380 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3381 u16 pkt_id; 3382 int ret; 3383 3384 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3385 if (ret) { 3386 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3387 return ret; 3388 } 3389 3390 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3391 ctrl_para.start_pktid = pkt_id; 3392 ctrl_para.end_pktid = pkt_id; 3393 ctrl_para.pkt_num = 0; 3394 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3395 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3396 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3397 if (ret) { 3398 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3399 return -EFAULT; 3400 } 3401 3402 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3403 if (ret) { 3404 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3405 return ret; 3406 } 3407 3408 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3409 ctrl_para.start_pktid = pkt_id; 3410 ctrl_para.end_pktid = pkt_id; 3411 ctrl_para.pkt_num = 0; 3412 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3413 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3414 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3415 if (ret) { 3416 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3417 return -EFAULT; 3418 } 3419 3420 return 0; 3421 } 3422 3423 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3424 { 3425 int ret; 3426 u32 reg; 3427 u8 val; 3428 3429 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3430 if (ret) 3431 return ret; 3432 3433 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3434 3435 ret = read_poll_timeout(rtw89_read8, val, 3436 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3437 SW_CVR_DUR_US, 3438 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3439 false, rtwdev, reg); 3440 if (ret) 3441 return ret; 3442 3443 return 0; 3444 } 3445 3446 static int band1_enable_ax(struct rtw89_dev *rtwdev) 3447 { 3448 int ret, i; 3449 u32 sleep_bak[4] = {0}; 3450 u32 pause_bak[4] = {0}; 3451 u32 tx_en; 3452 3453 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3454 if (ret) { 3455 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3456 return ret; 3457 } 3458 3459 for (i = 0; i < 4; i++) { 3460 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3461 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3462 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3463 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3464 } 3465 3466 ret = band_idle_ck_b(rtwdev, 0); 3467 if (ret) { 3468 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3469 return ret; 3470 } 3471 3472 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3473 if (ret) { 3474 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3475 return ret; 3476 } 3477 3478 for (i = 0; i < 4; i++) { 3479 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3480 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3481 } 3482 3483 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3484 if (ret) { 3485 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3486 return ret; 3487 } 3488 3489 ret = cmac_func_en_ax(rtwdev, 1, true); 3490 if (ret) { 3491 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3492 return ret; 3493 } 3494 3495 ret = cmac_init_ax(rtwdev, 1); 3496 if (ret) { 3497 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3498 return ret; 3499 } 3500 3501 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3502 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3503 3504 return 0; 3505 } 3506 3507 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3508 { 3509 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3510 3511 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3512 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3513 } 3514 3515 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3516 { 3517 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3518 3519 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3520 } 3521 3522 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3523 { 3524 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3525 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3526 3527 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3528 B_AX_TX_GET_ERRPKTID_INT_EN | 3529 B_AX_TX_NXT_ERRPKTID_INT_EN | 3530 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3531 B_AX_TX_OFFSET_ERR_INT_EN | 3532 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3533 if (chip_id == RTL8852C) 3534 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3535 B_AX_TX_ETH_TYPE_ERR_EN | 3536 B_AX_TX_LLC_PRE_ERR_EN | 3537 B_AX_TX_NW_TYPE_ERR_EN | 3538 B_AX_TX_KSRCH_ERR_EN); 3539 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3540 imr->mpdu_tx_imr_set); 3541 3542 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3543 B_AX_GETPKTID_ERR_INT_EN | 3544 B_AX_MHDRLEN_ERR_INT_EN | 3545 B_AX_RPT_ERR_INT_EN); 3546 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3547 imr->mpdu_rx_imr_set); 3548 } 3549 3550 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3551 { 3552 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3553 3554 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3555 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3556 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3557 B_AX_PLE_B_PKTID_ERR_INT_EN); 3558 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3559 imr->sta_sch_imr_set); 3560 } 3561 3562 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3563 { 3564 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3565 3566 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3567 imr->txpktctl_imr_b0_clr); 3568 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3569 imr->txpktctl_imr_b0_set); 3570 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3571 imr->txpktctl_imr_b1_clr); 3572 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3573 imr->txpktctl_imr_b1_set); 3574 } 3575 3576 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3577 { 3578 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3579 3580 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3581 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3582 } 3583 3584 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3585 { 3586 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3587 3588 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3589 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3590 } 3591 3592 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3593 { 3594 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3595 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3596 } 3597 3598 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3599 { 3600 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3601 3602 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3603 imr->host_disp_imr_clr); 3604 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3605 imr->host_disp_imr_set); 3606 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3607 imr->cpu_disp_imr_clr); 3608 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3609 imr->cpu_disp_imr_set); 3610 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3611 imr->other_disp_imr_clr); 3612 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3613 imr->other_disp_imr_set); 3614 } 3615 3616 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3617 { 3618 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3619 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3620 } 3621 3622 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3623 { 3624 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3625 3626 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3627 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3628 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3629 B_AX_BBRPT_CHINFO_IMR_CLR); 3630 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3631 imr->bbrpt_err_imr_set); 3632 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3633 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3634 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3635 } 3636 3637 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3638 { 3639 u32 reg; 3640 3641 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3642 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3643 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3644 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3645 } 3646 3647 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3648 { 3649 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3650 u32 reg; 3651 3652 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3653 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3654 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3655 } 3656 3657 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3658 { 3659 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3660 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3661 u32 reg; 3662 3663 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3664 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3665 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3666 3667 if (chip_id == RTL8852C) { 3668 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3669 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3670 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3671 } 3672 } 3673 3674 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3675 { 3676 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3677 u32 reg; 3678 3679 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3680 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3681 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3682 } 3683 3684 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3685 { 3686 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3687 u32 reg; 3688 3689 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3690 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3691 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3692 } 3693 3694 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3695 { 3696 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3697 u32 reg; 3698 3699 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3700 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3701 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3702 } 3703 3704 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3705 enum rtw89_mac_hwmod_sel sel) 3706 { 3707 int ret; 3708 3709 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3710 if (ret) { 3711 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3712 sel, mac_idx); 3713 return ret; 3714 } 3715 3716 if (sel == RTW89_DMAC_SEL) { 3717 rtw89_wdrls_imr_enable(rtwdev); 3718 rtw89_wsec_imr_enable(rtwdev); 3719 rtw89_mpdu_trx_imr_enable(rtwdev); 3720 rtw89_sta_sch_imr_enable(rtwdev); 3721 rtw89_txpktctl_imr_enable(rtwdev); 3722 rtw89_wde_imr_enable(rtwdev); 3723 rtw89_ple_imr_enable(rtwdev); 3724 rtw89_pktin_imr_enable(rtwdev); 3725 rtw89_dispatcher_imr_enable(rtwdev); 3726 rtw89_cpuio_imr_enable(rtwdev); 3727 rtw89_bbrpt_imr_enable(rtwdev); 3728 } else if (sel == RTW89_CMAC_SEL) { 3729 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3730 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3731 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3732 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3733 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3734 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3735 } else { 3736 return -EINVAL; 3737 } 3738 3739 return 0; 3740 } 3741 3742 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3743 { 3744 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3745 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3746 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3747 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3748 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta) 3749 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3750 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3751 } 3752 3753 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3754 { 3755 int ret = 0; 3756 3757 if (enable) { 3758 ret = band1_enable_ax(rtwdev); 3759 if (ret) { 3760 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3761 return ret; 3762 } 3763 3764 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3765 if (ret) { 3766 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3767 return ret; 3768 } 3769 } else { 3770 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3771 return -EINVAL; 3772 } 3773 3774 return 0; 3775 } 3776 3777 static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3778 { 3779 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3780 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3781 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3782 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3783 B_AX_RLSRPT0_FLTR_MAP_MASK); 3784 } else { 3785 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3786 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3787 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3788 B_AX_RLSRPT0_FLTR_MAP_MASK); 3789 } 3790 3791 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3792 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3793 3794 return 0; 3795 } 3796 3797 static int trx_init_ax(struct rtw89_dev *rtwdev) 3798 { 3799 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3800 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3801 int ret; 3802 3803 ret = dmac_init_ax(rtwdev, 0); 3804 if (ret) { 3805 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3806 return ret; 3807 } 3808 3809 ret = cmac_init_ax(rtwdev, 0); 3810 if (ret) { 3811 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3812 return ret; 3813 } 3814 3815 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3816 ret = dbcc_enable_ax(rtwdev, true); 3817 if (ret) { 3818 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3819 return ret; 3820 } 3821 } 3822 3823 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3824 if (ret) { 3825 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3826 return ret; 3827 } 3828 3829 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3830 if (ret) { 3831 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3832 return ret; 3833 } 3834 3835 err_imr_ctrl_ax(rtwdev, true); 3836 3837 ret = set_host_rpr_ax(rtwdev); 3838 if (ret) { 3839 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3840 return ret; 3841 } 3842 3843 if (chip_id == RTL8852C) 3844 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG, 3845 B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN); 3846 3847 return 0; 3848 } 3849 3850 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 3851 { 3852 #define BACAM_1024BMP_OCC_ENTRY 4 3853 #define BACAM_MAX_RU_SUPPORT_B0_STA 1 3854 #define BACAM_MAX_RU_SUPPORT_B1_STA 1 3855 const struct rtw89_chip_info *chip = rtwdev->chip; 3856 u8 users, offset; 3857 3858 if (chip->bacam_ver != RTW89_BACAM_V1) 3859 return 0; 3860 3861 offset = 0; 3862 users = BACAM_MAX_RU_SUPPORT_B0_STA; 3863 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 3864 3865 offset += users * BACAM_1024BMP_OCC_ENTRY; 3866 users = BACAM_MAX_RU_SUPPORT_B1_STA; 3867 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 3868 3869 return 0; 3870 } 3871 3872 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3873 { 3874 u32 val32; 3875 3876 if (rtw89_is_rtl885xb(rtwdev)) { 3877 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3878 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3879 return; 3880 } 3881 3882 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3883 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3884 3885 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3886 val32 |= B_AX_FS_WDT_INT; 3887 val32 &= ~B_AX_FS_WDT_INT_MSK; 3888 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3889 } 3890 3891 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3892 { 3893 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3894 3895 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3896 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3897 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3898 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3899 3900 rtw89_disable_fw_watchdog(rtwdev); 3901 3902 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3903 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3904 } 3905 3906 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3907 bool dlfw, bool include_bb) 3908 { 3909 u32 val; 3910 int ret; 3911 3912 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3913 return -EFAULT; 3914 3915 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3916 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3917 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3918 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3919 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3920 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3921 3922 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3923 3924 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3925 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3926 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3927 B_AX_WCPU_FWDL_STS_MASK); 3928 3929 if (dlfw) 3930 val |= B_AX_WCPU_FWDL_EN; 3931 3932 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3933 3934 if (rtw89_is_rtl885xb(rtwdev)) 3935 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3936 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3937 3938 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3939 boot_reason); 3940 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3941 3942 if (!dlfw) { 3943 mdelay(5); 3944 3945 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3946 if (ret) 3947 return ret; 3948 } 3949 3950 return 0; 3951 } 3952 3953 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 3954 { 3955 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3956 u32 val; 3957 3958 if (chip_id == RTL8852C) 3959 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3960 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3961 else 3962 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3963 B_AX_PKT_BUF_EN; 3964 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3965 } 3966 3967 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 3968 { 3969 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3970 u32 val; 3971 3972 if (chip_id == RTL8851B || chip_id == RTL8852BT) 3973 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3974 else 3975 val = B_AX_DISPATCHER_CLK_EN; 3976 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3977 3978 if (chip_id != RTL8852C) 3979 return; 3980 3981 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3982 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3983 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3984 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3985 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3986 3987 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3988 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3989 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3990 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3991 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3992 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3993 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3994 } 3995 3996 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3997 { 3998 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3999 int ret; 4000 4001 mac->hci_func_en(rtwdev); 4002 mac->dmac_func_pre_en(rtwdev); 4003 4004 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 4005 if (ret) { 4006 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 4007 return ret; 4008 } 4009 4010 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 4011 if (ret) { 4012 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 4013 return ret; 4014 } 4015 4016 return ret; 4017 } 4018 4019 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 4020 { 4021 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 4022 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 4023 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 4024 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 4025 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 4026 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 4027 4028 return 0; 4029 } 4030 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 4031 4032 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 4033 { 4034 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 4035 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 4036 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 4037 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 4038 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 4039 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 4040 4041 return 0; 4042 } 4043 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 4044 4045 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 4046 { 4047 int ret; 4048 4049 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 4050 4051 if (include_bb) { 4052 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 4053 if (rtwdev->dbcc_en) 4054 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 4055 } 4056 4057 ret = rtw89_mac_dmac_pre_init(rtwdev); 4058 if (ret) 4059 return ret; 4060 4061 if (rtwdev->hci.ops->mac_pre_init) { 4062 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 4063 if (ret) 4064 return ret; 4065 } 4066 4067 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 4068 if (ret) 4069 return ret; 4070 4071 return 0; 4072 } 4073 4074 int rtw89_mac_init(struct rtw89_dev *rtwdev) 4075 { 4076 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4077 const struct rtw89_chip_info *chip = rtwdev->chip; 4078 bool include_bb = !!chip->bbmcu_nr; 4079 int ret; 4080 4081 ret = rtw89_mac_pwr_on(rtwdev); 4082 if (ret) 4083 return ret; 4084 4085 ret = rtw89_mac_partial_init(rtwdev, include_bb); 4086 if (ret) 4087 goto fail; 4088 4089 ret = rtw89_chip_enable_bb_rf(rtwdev); 4090 if (ret) 4091 goto fail; 4092 4093 ret = mac->sys_init(rtwdev); 4094 if (ret) 4095 goto fail; 4096 4097 ret = mac->trx_init(rtwdev); 4098 if (ret) 4099 goto fail; 4100 4101 ret = rtw89_mac_feat_init(rtwdev); 4102 if (ret) 4103 goto fail; 4104 4105 if (rtwdev->hci.ops->mac_post_init) { 4106 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 4107 if (ret) 4108 goto fail; 4109 } 4110 4111 rtw89_fw_send_all_early_h2c(rtwdev); 4112 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 4113 4114 return ret; 4115 fail: 4116 rtw89_mac_pwr_off(rtwdev); 4117 4118 return ret; 4119 } 4120 4121 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4122 { 4123 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4124 u8 i; 4125 4126 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4127 return; 4128 4129 for (i = 0; i < 4; i++) { 4130 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4131 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 4132 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 4133 } 4134 } 4135 4136 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4137 { 4138 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4139 4140 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4141 return; 4142 4143 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4144 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 4145 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 4146 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 4147 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 4148 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 4149 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 4150 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 4151 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 4152 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 4153 } 4154 4155 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4156 { 4157 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4158 u8 grp = macid >> 5; 4159 int ret; 4160 4161 /* If this is called by change_interface() in the case of P2P, it could 4162 * be power-off, so ignore this operation. 4163 */ 4164 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4165 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4166 return 0; 4167 4168 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4169 if (ret) 4170 return ret; 4171 4172 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4173 4174 return 0; 4175 } 4176 4177 static const struct rtw89_port_reg rtw89_port_base_ax = { 4178 .port_cfg = R_AX_PORT_CFG_P0, 4179 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4180 .bcn_area = R_AX_BCN_AREA_P0, 4181 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4182 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4183 .tbtt_agg = R_AX_TBTT_AGG_P0, 4184 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4185 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4186 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4187 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4188 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4189 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4190 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4191 .tsftr_l = R_AX_TSFTR_LOW_P0, 4192 .tsftr_h = R_AX_TSFTR_HIGH_P0, 4193 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 4194 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4195 .mbssid = R_AX_MBSSID_CTRL, 4196 .mbssid_drop = R_AX_MBSSID_DROP_0, 4197 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4198 .ptcl_dbg = R_AX_PTCL_DBG, 4199 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4200 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4201 .bcn_psr_rpt = R_AX_BCN_PSR_RPT_P0, 4202 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4203 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4204 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4205 }; 4206 4207 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4208 struct rtw89_vif_link *rtwvif_link, u8 type) 4209 { 4210 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4211 const struct rtw89_port_reg *p = mac->port_base; 4212 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif_link->port); 4213 u32 reg_info, reg_ctrl; 4214 u32 val; 4215 int ret; 4216 4217 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif_link->mac_idx); 4218 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif_link->mac_idx); 4219 4220 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4221 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4222 fsleep(100); 4223 4224 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4225 true, rtwdev, reg_info, mask); 4226 if (ret) 4227 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4228 } 4229 4230 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, 4231 struct rtw89_vif_link *rtwvif_link) 4232 { 4233 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4234 const struct rtw89_port_reg *p = mac->port_base; 4235 4236 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4237 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 4238 1); 4239 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 4240 0); 4241 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 4242 0); 4243 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4244 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4245 B_AX_TBTTERLY_MASK, 1); 4246 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, 4247 B_AX_BCN_SPACE_MASK, 1); 4248 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4249 4250 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM0); 4251 if (rtwvif_link->port == RTW89_PORT_0) 4252 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM1); 4253 4254 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4255 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4256 fsleep(2000); 4257 } 4258 4259 #define BCN_INTERVAL 100 4260 #define BCN_ERLY_DEF 160 4261 #define BCN_SETUP_DEF 2 4262 #define BCN_HOLD_DEF 200 4263 #define BCN_MASK_DEF 0 4264 #define TBTT_ERLY_DEF 5 4265 #define BCN_SET_UNIT 32 4266 #define BCN_ERLY_SET_DLY (10 * 2) 4267 4268 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4269 struct rtw89_vif_link *rtwvif_link) 4270 { 4271 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4272 const struct rtw89_port_reg *p = mac->port_base; 4273 const struct rtw89_chip_info *chip = rtwdev->chip; 4274 struct ieee80211_bss_conf *bss_conf; 4275 bool need_backup = false; 4276 u32 backup_val; 4277 u16 beacon_int; 4278 4279 if (!rtw89_read32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN)) 4280 return; 4281 4282 if (chip->chip_id == RTL8852A && rtwvif_link->port != RTW89_PORT_0) { 4283 need_backup = true; 4284 backup_val = rtw89_read32_port(rtwdev, rtwvif_link, p->tbtt_prohib); 4285 } 4286 4287 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4288 rtw89_mac_bcn_drop(rtwdev, rtwvif_link); 4289 4290 if (chip->chip_id == RTL8852A) { 4291 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->tbtt_prohib, 4292 B_AX_TBTT_SETUP_MASK); 4293 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4294 B_AX_TBTT_HOLD_MASK, 1); 4295 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->tbtt_early, 4296 B_AX_TBTTERLY_MASK); 4297 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->bcn_early, 4298 B_AX_BCNERLY_MASK); 4299 } 4300 4301 rcu_read_lock(); 4302 4303 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4304 beacon_int = bss_conf->beacon_int; 4305 4306 rcu_read_unlock(); 4307 4308 msleep(beacon_int + 1); 4309 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN | 4310 B_AX_BRK_SETUP); 4311 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSFTR_RST); 4312 rtw89_write32_port(rtwdev, rtwvif_link, p->bcn_cnt_tmr, 0); 4313 4314 if (need_backup) 4315 rtw89_write32_port(rtwdev, rtwvif_link, p->tbtt_prohib, backup_val); 4316 } 4317 4318 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4319 struct rtw89_vif_link *rtwvif_link, bool en) 4320 { 4321 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4322 const struct rtw89_port_reg *p = mac->port_base; 4323 4324 if (en) 4325 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4326 B_AX_TXBCN_RPT_EN); 4327 else 4328 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4329 B_AX_TXBCN_RPT_EN); 4330 } 4331 4332 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4333 struct rtw89_vif_link *rtwvif_link, bool en) 4334 { 4335 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4336 const struct rtw89_port_reg *p = mac->port_base; 4337 4338 if (en) 4339 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4340 B_AX_RXBCN_RPT_EN); 4341 else 4342 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4343 B_AX_RXBCN_RPT_EN); 4344 } 4345 4346 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4347 struct rtw89_vif_link *rtwvif_link) 4348 { 4349 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4350 const struct rtw89_port_reg *p = mac->port_base; 4351 4352 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_NET_TYPE_MASK, 4353 rtwvif_link->net_type); 4354 } 4355 4356 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4357 struct rtw89_vif_link *rtwvif_link) 4358 { 4359 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4360 const struct rtw89_port_reg *p = mac->port_base; 4361 bool en = rtwvif_link->net_type != RTW89_NET_TYPE_NO_LINK; 4362 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4363 4364 if (en) 4365 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bits); 4366 else 4367 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bits); 4368 } 4369 4370 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4371 struct rtw89_vif_link *rtwvif_link) 4372 { 4373 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4374 const struct rtw89_port_reg *p = mac->port_base; 4375 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4376 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4377 u32 bit = B_AX_RX_BSSID_FIT_EN; 4378 4379 if (en) 4380 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bit); 4381 else 4382 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bit); 4383 } 4384 4385 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4386 struct rtw89_vif_link *rtwvif_link, bool en) 4387 { 4388 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4389 const struct rtw89_port_reg *p = mac->port_base; 4390 4391 if (en) 4392 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4393 else 4394 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4395 } 4396 4397 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4398 struct rtw89_vif_link *rtwvif_link) 4399 { 4400 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4401 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4402 4403 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif_link, en); 4404 } 4405 4406 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4407 struct rtw89_vif_link *rtwvif_link, bool en) 4408 { 4409 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4410 const struct rtw89_port_reg *p = mac->port_base; 4411 4412 if (en) 4413 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4414 else 4415 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4416 } 4417 4418 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4419 struct rtw89_vif_link *rtwvif_link) 4420 { 4421 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || 4422 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4423 4424 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4425 } 4426 4427 static void rtw89_mac_enable_ap_bcn_by_chan(struct rtw89_dev *rtwdev, 4428 struct rtw89_vif_link *rtwvif_link, 4429 const struct rtw89_chan *to_match, 4430 bool en) 4431 { 4432 const struct rtw89_chan *chan; 4433 4434 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 4435 return; 4436 4437 if (!to_match) 4438 goto doit; 4439 4440 /* @to_match may not be in the same domain as return of calling 4441 * rtw89_chan_get(). So, cannot compare their addresses directly. 4442 */ 4443 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 4444 if (chan->channel != to_match->channel) 4445 return; 4446 4447 doit: 4448 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4449 } 4450 4451 static void rtw89_mac_enable_aps_bcn_by_chan(struct rtw89_dev *rtwdev, 4452 const struct rtw89_chan *to_match, 4453 bool en) 4454 { 4455 struct rtw89_vif_link *rtwvif_link; 4456 struct rtw89_vif *rtwvif; 4457 unsigned int link_id; 4458 4459 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4460 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4461 rtw89_mac_enable_ap_bcn_by_chan(rtwdev, rtwvif_link, 4462 to_match, en); 4463 } 4464 4465 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4466 { 4467 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, NULL, en); 4468 } 4469 4470 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4471 struct rtw89_vif_link *rtwvif_link) 4472 { 4473 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4474 const struct rtw89_port_reg *p = mac->port_base; 4475 struct ieee80211_bss_conf *bss_conf; 4476 u16 bcn_int; 4477 4478 rcu_read_lock(); 4479 4480 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4481 if (bss_conf->beacon_int) 4482 bcn_int = bss_conf->beacon_int; 4483 else 4484 bcn_int = BCN_INTERVAL; 4485 4486 rcu_read_unlock(); 4487 4488 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, B_AX_BCN_SPACE_MASK, 4489 bcn_int); 4490 } 4491 4492 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4493 struct rtw89_vif_link *rtwvif_link) 4494 { 4495 u8 win = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4496 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4497 const struct rtw89_port_reg *p = mac->port_base; 4498 u8 port = rtwvif_link->port; 4499 u32 reg; 4500 4501 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif_link->mac_idx); 4502 rtw89_write8(rtwdev, reg, win); 4503 } 4504 4505 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4506 struct rtw89_vif_link *rtwvif_link) 4507 { 4508 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4509 const struct rtw89_port_reg *p = mac->port_base; 4510 struct ieee80211_bss_conf *bss_conf; 4511 u8 dtim_period; 4512 u32 addr; 4513 4514 rcu_read_lock(); 4515 4516 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4517 dtim_period = bss_conf->dtim_period; 4518 4519 rcu_read_unlock(); 4520 4521 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif_link->mac_idx); 4522 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4523 4524 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4525 dtim_period); 4526 } 4527 4528 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4529 struct rtw89_vif_link *rtwvif_link) 4530 { 4531 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4532 const struct rtw89_port_reg *p = mac->port_base; 4533 4534 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4535 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4536 } 4537 4538 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4539 struct rtw89_vif_link *rtwvif_link) 4540 { 4541 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4542 const struct rtw89_port_reg *p = mac->port_base; 4543 4544 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4545 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4546 } 4547 4548 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4549 struct rtw89_vif_link *rtwvif_link) 4550 { 4551 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4552 const struct rtw89_port_reg *p = mac->port_base; 4553 4554 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, 4555 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4556 } 4557 4558 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4559 struct rtw89_vif_link *rtwvif_link) 4560 { 4561 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4562 const struct rtw89_port_reg *p = mac->port_base; 4563 4564 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4565 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4566 } 4567 4568 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4569 struct rtw89_vif_link *rtwvif_link) 4570 { 4571 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4572 const struct rtw89_port_reg *p = mac->port_base; 4573 static const u32 masks[RTW89_PORT_NUM] = { 4574 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4575 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4576 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4577 }; 4578 struct ieee80211_bss_conf *bss_conf; 4579 u8 port = rtwvif_link->port; 4580 u32 reg_base; 4581 u32 reg; 4582 u8 bss_color; 4583 4584 rcu_read_lock(); 4585 4586 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4587 bss_color = bss_conf->he_bss_color.color; 4588 4589 rcu_read_unlock(); 4590 4591 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4592 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif_link->mac_idx); 4593 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4594 } 4595 4596 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4597 struct rtw89_vif_link *rtwvif_link) 4598 { 4599 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4600 const struct rtw89_port_reg *p = mac->port_base; 4601 u8 port = rtwvif_link->port; 4602 u32 reg; 4603 4604 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4605 return; 4606 4607 if (port == 0) { 4608 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif_link->mac_idx); 4609 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4610 } 4611 } 4612 4613 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4614 struct rtw89_vif_link *rtwvif_link) 4615 { 4616 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4617 const struct rtw89_port_reg *p = mac->port_base; 4618 u8 port = rtwvif_link->port; 4619 u32 reg; 4620 u32 val; 4621 4622 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif_link->mac_idx); 4623 val = rtw89_read32(rtwdev, reg); 4624 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4625 if (port == 0) 4626 val &= ~BIT(0); 4627 rtw89_write32(rtwdev, reg, val); 4628 } 4629 4630 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4631 struct rtw89_vif_link *rtwvif_link, bool enable) 4632 { 4633 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4634 const struct rtw89_port_reg *p = mac->port_base; 4635 4636 if (enable) 4637 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4638 B_AX_PORT_FUNC_EN); 4639 else 4640 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4641 B_AX_PORT_FUNC_EN); 4642 } 4643 4644 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4645 struct rtw89_vif_link *rtwvif_link) 4646 { 4647 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4648 const struct rtw89_port_reg *p = mac->port_base; 4649 4650 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 4651 BCN_ERLY_DEF); 4652 } 4653 4654 static void rtw89_mac_port_cfg_bcn_psr_rpt(struct rtw89_dev *rtwdev, 4655 struct rtw89_vif_link *rtwvif_link) 4656 { 4657 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4658 const struct rtw89_port_reg *p = mac->port_base; 4659 struct ieee80211_bss_conf *bss_conf; 4660 u8 bssid_index; 4661 u32 reg; 4662 4663 rcu_read_lock(); 4664 4665 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4666 if (bss_conf->nontransmitted) 4667 bssid_index = bss_conf->bssid_index; 4668 else 4669 bssid_index = 0; 4670 4671 rcu_read_unlock(); 4672 4673 reg = rtw89_mac_reg_by_idx(rtwdev, p->bcn_psr_rpt + rtwvif_link->port * 4, 4674 rtwvif_link->mac_idx); 4675 rtw89_write32_mask(rtwdev, reg, B_AX_BCAID_P0_MASK, bssid_index); 4676 } 4677 4678 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4679 struct rtw89_vif_link *rtwvif_link, 4680 struct rtw89_vif_link *rtwvif_src, 4681 u16 offset_tu) 4682 { 4683 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4684 const struct rtw89_port_reg *p = mac->port_base; 4685 u32 val, reg; 4686 4687 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4688 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif_link->port * 4, 4689 rtwvif_link->mac_idx); 4690 4691 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4692 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4693 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4694 } 4695 4696 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4697 struct rtw89_vif_link *rtwvif_link, 4698 struct rtw89_vif_link *rtwvif_src, 4699 u8 offset, int *n_offset) 4700 { 4701 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif_link == rtwvif_src) 4702 return; 4703 4704 if (rtwvif_link->rand_tsf_done) 4705 goto out; 4706 4707 /* adjust offset randomly to avoid beacon conflict */ 4708 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4709 rtw89_mac_port_tsf_sync(rtwdev, rtwvif_link, rtwvif_src, 4710 (*n_offset) * offset); 4711 4712 rtwvif_link->rand_tsf_done = true; 4713 4714 out: 4715 (*n_offset)++; 4716 } 4717 4718 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4719 { 4720 struct rtw89_vif_link *src = NULL, *tmp; 4721 u8 offset = 100, vif_aps = 0; 4722 struct rtw89_vif *rtwvif; 4723 unsigned int link_id; 4724 int n_offset = 1; 4725 4726 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4727 rtw89_vif_for_each_link(rtwvif, tmp, link_id) { 4728 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4729 src = tmp; 4730 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4731 vif_aps++; 4732 } 4733 } 4734 4735 if (vif_aps == 0) 4736 return; 4737 4738 offset /= (vif_aps + 1); 4739 4740 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4741 rtw89_vif_for_each_link(rtwvif, tmp, link_id) 4742 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, 4743 &n_offset); 4744 } 4745 4746 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4747 { 4748 int ret; 4749 4750 ret = rtw89_mac_port_update(rtwdev, rtwvif_link); 4751 if (ret) 4752 return ret; 4753 4754 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4755 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4756 4757 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif_link->mac_id, false); 4758 if (ret) 4759 return ret; 4760 4761 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_CREATE); 4762 if (ret) 4763 return ret; 4764 4765 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, NULL, true); 4766 if (ret) 4767 return ret; 4768 4769 ret = rtw89_cam_init(rtwdev, rtwvif_link); 4770 if (ret) 4771 return ret; 4772 4773 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 4774 if (ret) 4775 return ret; 4776 4777 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, NULL); 4778 if (ret) 4779 return ret; 4780 4781 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, NULL); 4782 if (ret) 4783 return ret; 4784 4785 return 0; 4786 } 4787 4788 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4789 { 4790 int ret; 4791 4792 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_REMOVE); 4793 if (ret) 4794 return ret; 4795 4796 rtw89_cam_deinit(rtwdev, rtwvif_link); 4797 4798 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 4799 if (ret) 4800 return ret; 4801 4802 return 0; 4803 } 4804 4805 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4806 { 4807 u8 port = rtwvif_link->port; 4808 4809 if (port >= RTW89_PORT_NUM) 4810 return -EINVAL; 4811 4812 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 4813 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif_link, false); 4814 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif_link, false); 4815 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif_link); 4816 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif_link); 4817 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif_link); 4818 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif_link); 4819 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif_link); 4820 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif_link); 4821 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif_link); 4822 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif_link); 4823 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif_link); 4824 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif_link); 4825 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif_link); 4826 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif_link); 4827 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif_link); 4828 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif_link); 4829 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif_link); 4830 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif_link, true); 4831 rtw89_mac_port_tsf_resync_all(rtwdev); 4832 fsleep(BCN_ERLY_SET_DLY); 4833 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif_link); 4834 rtw89_mac_port_cfg_bcn_psr_rpt(rtwdev, rtwvif_link); 4835 4836 return 0; 4837 } 4838 4839 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4840 u64 *tsf) 4841 { 4842 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4843 const struct rtw89_port_reg *p = mac->port_base; 4844 u32 tsf_low, tsf_high; 4845 int ret; 4846 4847 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif_link->mac_idx, RTW89_CMAC_SEL); 4848 if (ret) 4849 return ret; 4850 4851 tsf_low = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_l); 4852 tsf_high = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_h); 4853 *tsf = (u64)tsf_high << 32 | tsf_low; 4854 4855 return 0; 4856 } 4857 4858 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4859 struct cfg80211_bss *bss, 4860 void *data) 4861 { 4862 const struct cfg80211_bss_ies *ies; 4863 const struct element *elem; 4864 bool *tolerated = data; 4865 4866 rcu_read_lock(); 4867 ies = rcu_dereference(bss->ies); 4868 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4869 ies->len); 4870 4871 if (!elem || elem->datalen < 10 || 4872 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4873 *tolerated = false; 4874 rcu_read_unlock(); 4875 } 4876 4877 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4878 struct rtw89_vif_link *rtwvif_link) 4879 { 4880 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4881 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4882 struct ieee80211_hw *hw = rtwdev->hw; 4883 struct ieee80211_bss_conf *bss_conf; 4884 struct cfg80211_chan_def oper; 4885 bool tolerated = true; 4886 u32 reg; 4887 4888 rcu_read_lock(); 4889 4890 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4891 if (!bss_conf->he_support || vif->type != NL80211_IFTYPE_STATION) { 4892 rcu_read_unlock(); 4893 return; 4894 } 4895 4896 oper = bss_conf->chanreq.oper; 4897 if (!(oper.chan->flags & IEEE80211_CHAN_RADAR)) { 4898 rcu_read_unlock(); 4899 return; 4900 } 4901 4902 rcu_read_unlock(); 4903 4904 cfg80211_bss_iter(hw->wiphy, &oper, 4905 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4906 &tolerated); 4907 4908 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 4909 rtwvif_link->mac_idx); 4910 if (tolerated) 4911 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4912 else 4913 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4914 } 4915 4916 void rtw89_mac_set_he_tb(struct rtw89_dev *rtwdev, 4917 struct rtw89_vif_link *rtwvif_link) 4918 { 4919 struct ieee80211_bss_conf *bss_conf; 4920 bool set; 4921 u32 reg; 4922 4923 if (rtwdev->chip->chip_gen != RTW89_CHIP_BE) 4924 return; 4925 4926 rcu_read_lock(); 4927 4928 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4929 set = bss_conf->he_support && !bss_conf->eht_support; 4930 4931 rcu_read_unlock(); 4932 4933 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CLIENT_OM_CTRL, 4934 rtwvif_link->mac_idx); 4935 4936 if (set) 4937 rtw89_write32_set(rtwdev, reg, B_BE_TRIG_DIS_EHTTB); 4938 else 4939 rtw89_write32_clr(rtwdev, reg, B_BE_TRIG_DIS_EHTTB); 4940 } 4941 4942 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4943 { 4944 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 4945 4946 rtwvif_link->rand_tsf_done = false; 4947 } 4948 4949 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4950 { 4951 return rtw89_mac_vif_init(rtwdev, rtwvif_link); 4952 } 4953 4954 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4955 { 4956 return rtw89_mac_vif_deinit(rtwdev, rtwvif_link); 4957 } 4958 4959 static void 4960 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4961 { 4962 } 4963 4964 static const struct rtw89_chan * 4965 rtw89_hw_scan_search_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4966 { 4967 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 4968 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4969 4970 if (band == op->band_type && channel == op->primary_channel) 4971 return op; 4972 4973 if (scan_info->extra_op.set) { 4974 op = &scan_info->extra_op.chan; 4975 if (band == op->band_type && channel == op->primary_channel) 4976 return op; 4977 } 4978 4979 return NULL; 4980 } 4981 4982 static void 4983 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4984 u32 len) 4985 { 4986 const struct rtw89_c2h_scanofld *c2h = 4987 (const struct rtw89_c2h_scanofld *)skb->data; 4988 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 4989 const struct rtw89_chan *op_chan; 4990 struct rtw89_vif *rtwvif; 4991 struct rtw89_chan new; 4992 u16 actual_period, expect_period; 4993 u8 reason, status, tx_fail, band; 4994 u8 mac_idx, sw_def, fw_def; 4995 u8 ver = U8_MAX; 4996 u32 report_tsf; 4997 u16 chan; 4998 int ret; 4999 5000 if (!rtwvif_link) 5001 return; 5002 5003 rtwvif = rtwvif_link->rtwvif; 5004 5005 if (RTW89_CHK_FW_FEATURE(CH_INFO_BE_V0, &rtwdev->fw)) 5006 ver = 0; 5007 5008 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 5009 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5010 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 5011 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5012 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 5013 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 5014 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 5015 5016 5017 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 5018 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 5019 5020 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 5021 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 5022 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 5023 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 5024 if (ver == 0) { 5025 expect_period = 5026 le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 5027 } else { 5028 actual_period = le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_PERIOD_V1); 5029 expect_period = 5030 le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1); 5031 } 5032 5033 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 5034 "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 5035 sw_def, fw_def, report_tsf, expect_period); 5036 } 5037 5038 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 5039 "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 5040 mac_idx, band, chan, reason, status, tx_fail, actual_period); 5041 5042 switch (reason) { 5043 case RTW89_SCAN_LEAVE_OP_NOTIFY: 5044 case RTW89_SCAN_LEAVE_CH_NOTIFY: 5045 op_chan = rtw89_hw_scan_search_op_chan(rtwdev, band, chan); 5046 if (op_chan) { 5047 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, op_chan, false); 5048 ieee80211_stop_queues(rtwdev->hw); 5049 } else { 5050 rtw89_phy_nhm_get_result(rtwdev, band, chan); 5051 } 5052 return; 5053 case RTW89_SCAN_END_SCAN_NOTIFY: 5054 if (rtwdev->scan_info.abort) 5055 return; 5056 5057 if (rtwvif_link && rtwvif->scan_req && 5058 !list_empty(&rtwdev->scan_info.chan_list)) { 5059 rtwdev->scan_info.delay = 0; 5060 ret = rtw89_hw_scan_offload(rtwdev, rtwvif_link, true); 5061 if (ret) { 5062 rtw89_hw_scan_abort(rtwdev, rtwvif_link); 5063 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 5064 } 5065 } else { 5066 rtw89_hw_scan_complete(rtwdev, rtwvif_link, false); 5067 } 5068 break; 5069 case RTW89_SCAN_ENTER_OP_NOTIFY: 5070 case RTW89_SCAN_ENTER_CH_NOTIFY: 5071 op_chan = rtw89_hw_scan_search_op_chan(rtwdev, band, chan); 5072 if (op_chan) { 5073 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, op_chan); 5074 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, op_chan, true); 5075 ieee80211_wake_queues(rtwdev->hw); 5076 } else { 5077 rtw89_chan_create(&new, chan, chan, band, 5078 RTW89_CHANNEL_WIDTH_20); 5079 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, 5080 &new); 5081 rtw89_phy_nhm_trigger(rtwdev); 5082 } 5083 break; 5084 default: 5085 return; 5086 } 5087 } 5088 5089 static void 5090 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5091 struct sk_buff *skb) 5092 { 5093 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5094 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5095 enum nl80211_cqm_rssi_threshold_event nl_event; 5096 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 5097 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 5098 u8 type, event, mac_id; 5099 bool start_detect; 5100 s8 sig; 5101 5102 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 5103 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 5104 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 5105 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 5106 5107 if (mac_id != rtwvif_link->mac_id) 5108 return; 5109 5110 rtw89_debug(rtwdev, RTW89_DBG_FW, 5111 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 5112 mac_id, type, sig, event); 5113 5114 switch (type) { 5115 case RTW89_BCN_FLTR_BEACON_LOSS: 5116 if (!rtwdev->scanning && !rtwvif->offchan && 5117 !rtwvif_link->noa_once.in_duration) { 5118 start_detect = rtw89_mcc_detect_go_bcn(rtwdev, rtwvif_link); 5119 if (start_detect) 5120 return; 5121 5122 ieee80211_connection_loss(vif); 5123 } else { 5124 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 5125 } 5126 return; 5127 case RTW89_BCN_FLTR_NOTIFY: 5128 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 5129 break; 5130 case RTW89_BCN_FLTR_RSSI: 5131 if (event == RTW89_BCN_FLTR_RSSI_LOW) 5132 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 5133 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 5134 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 5135 else 5136 return; 5137 break; 5138 default: 5139 return; 5140 } 5141 5142 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 5143 } 5144 5145 static void 5146 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5147 u32 len) 5148 { 5149 struct rtw89_vif_link *rtwvif_link; 5150 struct rtw89_vif *rtwvif; 5151 unsigned int link_id; 5152 5153 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5154 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 5155 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif_link, c2h); 5156 } 5157 5158 static void 5159 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5160 { 5161 /* N.B. This will run in interrupt context. */ 5162 5163 rtw89_debug(rtwdev, RTW89_DBG_FW, 5164 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 5165 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 5166 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 5167 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 5168 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 5169 } 5170 5171 static void 5172 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5173 { 5174 /* N.B. This will run in interrupt context. */ 5175 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5176 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 5177 struct rtw89_wait_info *ps_wait = &rtwdev->mac.ps_wait; 5178 const struct rtw89_c2h_done_ack *c2h = 5179 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 5180 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 5181 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 5182 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 5183 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 5184 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 5185 struct rtw89_completion_data data = {}; 5186 unsigned int cond; 5187 5188 rtw89_debug(rtwdev, RTW89_DBG_FW, 5189 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 5190 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 5191 5192 if (h2c_cat != H2C_CAT_MAC) 5193 return; 5194 5195 switch (h2c_class) { 5196 default: 5197 return; 5198 case H2C_CL_MAC_PS: 5199 switch (h2c_func) { 5200 default: 5201 return; 5202 case H2C_FUNC_IPS_CFG: 5203 cond = RTW89_PS_WAIT_COND_IPS_CFG; 5204 break; 5205 } 5206 5207 data.err = !!h2c_return; 5208 rtw89_complete_cond(ps_wait, cond, &data); 5209 return; 5210 case H2C_CL_MAC_FW_OFLD: 5211 switch (h2c_func) { 5212 default: 5213 return; 5214 case H2C_FUNC_ADD_SCANOFLD_CH: 5215 cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 5216 h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN; 5217 break; 5218 case H2C_FUNC_SCANOFLD: 5219 scan_info->seq++; 5220 cond = RTW89_SCANOFLD_WAIT_COND_START; 5221 break; 5222 case H2C_FUNC_SCANOFLD_BE: 5223 scan_info->seq++; 5224 cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 5225 h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN; 5226 break; 5227 } 5228 5229 data.err = !!h2c_return; 5230 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5231 return; 5232 } 5233 } 5234 5235 static void 5236 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5237 { 5238 rtw89_fw_log_dump(rtwdev, c2h->data, len); 5239 } 5240 5241 static void 5242 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5243 { 5244 } 5245 5246 static void 5247 rtw89_mac_c2h_bcn_upd_done(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5248 { 5249 } 5250 5251 static void 5252 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 5253 u32 len) 5254 { 5255 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 5256 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 5257 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 5258 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 5259 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 5260 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 5261 struct rtw89_completion_data data = {}; 5262 unsigned int cond; 5263 5264 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 5265 pkt_id, pkt_op, pkt_len); 5266 5267 data.err = !pkt_len; 5268 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 5269 5270 rtw89_complete_cond(wait, cond, &data); 5271 } 5272 5273 static void 5274 rtw89_mac_c2h_bcn_resend(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5275 { 5276 } 5277 5278 static void 5279 rtw89_mac_c2h_tx_duty_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5280 { 5281 struct rtw89_c2h_tx_duty_rpt *c2h = 5282 (struct rtw89_c2h_tx_duty_rpt *)skb_c2h->data; 5283 u8 err; 5284 5285 err = le32_get_bits(c2h->w2, RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR); 5286 5287 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "C2H TX duty rpt with err=%d\n", err); 5288 } 5289 5290 static void 5291 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5292 u32 len) 5293 { 5294 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 5295 } 5296 5297 static void 5298 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5299 { 5300 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 5301 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 5302 5303 switch (func) { 5304 case H2C_FUNC_ADD_MCC: 5305 case H2C_FUNC_START_MCC: 5306 case H2C_FUNC_STOP_MCC: 5307 case H2C_FUNC_DEL_MCC_GROUP: 5308 case H2C_FUNC_RESET_MCC_GROUP: 5309 case H2C_FUNC_MCC_REQ_TSF: 5310 case H2C_FUNC_MCC_MACID_BITMAP: 5311 case H2C_FUNC_MCC_SYNC: 5312 case H2C_FUNC_MCC_SET_DURATION: 5313 break; 5314 default: 5315 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5316 "invalid MCC C2H RCV ACK: func %d\n", func); 5317 return; 5318 } 5319 5320 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5321 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 5322 } 5323 5324 static void 5325 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5326 { 5327 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 5328 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 5329 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 5330 struct rtw89_completion_data data = {}; 5331 unsigned int cond; 5332 bool next = false; 5333 5334 switch (func) { 5335 case H2C_FUNC_MCC_REQ_TSF: 5336 next = true; 5337 break; 5338 case H2C_FUNC_MCC_MACID_BITMAP: 5339 case H2C_FUNC_MCC_SYNC: 5340 case H2C_FUNC_MCC_SET_DURATION: 5341 break; 5342 case H2C_FUNC_ADD_MCC: 5343 case H2C_FUNC_START_MCC: 5344 case H2C_FUNC_STOP_MCC: 5345 case H2C_FUNC_DEL_MCC_GROUP: 5346 case H2C_FUNC_RESET_MCC_GROUP: 5347 default: 5348 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5349 "invalid MCC C2H REQ ACK: func %d\n", func); 5350 return; 5351 } 5352 5353 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5354 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5355 group, func, retcode); 5356 5357 if (!retcode && next) 5358 return; 5359 5360 data.err = !!retcode; 5361 cond = RTW89_MCC_WAIT_COND(group, func); 5362 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5363 } 5364 5365 static void 5366 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5367 { 5368 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5369 struct rtw89_completion_data data = {}; 5370 struct rtw89_mac_mcc_tsf_rpt *rpt; 5371 unsigned int cond; 5372 5373 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5374 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5375 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5376 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5377 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5378 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5379 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5380 5381 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5382 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5383 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5384 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5385 5386 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5387 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5388 } 5389 5390 static void 5391 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5392 { 5393 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5394 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5395 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5396 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5397 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5398 struct rtw89_completion_data data = {}; 5399 unsigned int cond; 5400 bool rsp = true; 5401 bool err; 5402 u8 func; 5403 5404 switch (status) { 5405 case RTW89_MAC_MCC_ADD_ROLE_OK: 5406 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5407 func = H2C_FUNC_ADD_MCC; 5408 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5409 break; 5410 case RTW89_MAC_MCC_START_GROUP_OK: 5411 case RTW89_MAC_MCC_START_GROUP_FAIL: 5412 func = H2C_FUNC_START_MCC; 5413 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5414 break; 5415 case RTW89_MAC_MCC_STOP_GROUP_OK: 5416 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5417 func = H2C_FUNC_STOP_MCC; 5418 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5419 break; 5420 case RTW89_MAC_MCC_DEL_GROUP_OK: 5421 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5422 func = H2C_FUNC_DEL_MCC_GROUP; 5423 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5424 break; 5425 case RTW89_MAC_MCC_RESET_GROUP_OK: 5426 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5427 func = H2C_FUNC_RESET_MCC_GROUP; 5428 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5429 break; 5430 case RTW89_MAC_MCC_SWITCH_CH_OK: 5431 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5432 case RTW89_MAC_MCC_TXNULL0_OK: 5433 case RTW89_MAC_MCC_TXNULL0_FAIL: 5434 case RTW89_MAC_MCC_TXNULL1_OK: 5435 case RTW89_MAC_MCC_TXNULL1_FAIL: 5436 case RTW89_MAC_MCC_SWITCH_EARLY: 5437 case RTW89_MAC_MCC_TBTT: 5438 case RTW89_MAC_MCC_DURATION_START: 5439 case RTW89_MAC_MCC_DURATION_END: 5440 rsp = false; 5441 break; 5442 default: 5443 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5444 "invalid MCC C2H STS RPT: status %d\n", status); 5445 return; 5446 } 5447 5448 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5449 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5450 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5451 5452 if (!rsp) 5453 return; 5454 5455 data.err = err; 5456 cond = RTW89_MCC_WAIT_COND(group, func); 5457 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5458 } 5459 5460 static void 5461 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5462 { 5463 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5464 const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5465 struct rtw89_completion_data data = {}; 5466 struct rtw89_mac_mrc_tsf_rpt *rpt; 5467 unsigned int i; 5468 5469 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5470 rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5471 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5472 le32_get_bits(c2h_rpt->w2, 5473 RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5474 5475 for (i = 0; i < rpt->num; i++) { 5476 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5477 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5478 5479 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5480 5481 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5482 "MRC C2H TSF RPT: index %u> %llu\n", 5483 i, rpt->tsfs[i]); 5484 } 5485 5486 rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5487 } 5488 5489 static void 5490 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5491 { 5492 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 5493 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 5494 struct rtw89_wait_info *wait = &rtw_wow->wait; 5495 const struct rtw89_c2h_wow_aoac_report *c2h = 5496 (const struct rtw89_c2h_wow_aoac_report *)skb->data; 5497 struct rtw89_completion_data data = {}; 5498 5499 aoac_rpt->rpt_ver = c2h->rpt_ver; 5500 aoac_rpt->sec_type = c2h->sec_type; 5501 aoac_rpt->key_idx = c2h->key_idx; 5502 aoac_rpt->pattern_idx = c2h->pattern_idx; 5503 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok, 5504 RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX); 5505 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv)); 5506 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count, 5507 sizeof(aoac_rpt->eapol_key_replay_count)); 5508 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk)); 5509 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv)); 5510 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv)); 5511 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id); 5512 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn); 5513 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk)); 5514 5515 rtw89_complete_cond(wait, RTW89_WOW_WAIT_COND_AOAC, &data); 5516 } 5517 5518 static void 5519 rtw89_mac_c2h_mlo_link_cfg_stat(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5520 { 5521 const struct rtw89_c2h_mlo_link_cfg_rpt *c2h_rpt; 5522 struct rtw89_wait_info *wait = &rtwdev->mlo.wait; 5523 struct rtw89_completion_data data = {}; 5524 unsigned int cond; 5525 u16 mac_id; 5526 u8 status; 5527 5528 c2h_rpt = (const struct rtw89_c2h_mlo_link_cfg_rpt *)c2h->data; 5529 5530 mac_id = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MLO_LINK_CFG_RPT_W2_MACID); 5531 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MLO_LINK_CFG_RPT_W2_STATUS); 5532 5533 data.err = status == RTW89_C2H_MLO_LINK_CFG_ROLE_NOT_EXIST || 5534 status == RTW89_C2H_MLO_LINK_CFG_RUNNING; 5535 cond = RTW89_MLO_WAIT_COND(mac_id, H2C_FUNC_MLO_LINK_CFG); 5536 rtw89_complete_cond(wait, cond, &data); 5537 } 5538 5539 static void 5540 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5541 { 5542 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5543 const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5544 struct rtw89_completion_data data = {}; 5545 enum rtw89_mac_mrc_status status; 5546 unsigned int cond; 5547 bool next = false; 5548 u32 tsf_high; 5549 u32 tsf_low; 5550 u8 sch_idx; 5551 u8 func; 5552 5553 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5554 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5555 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5556 tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5557 tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5558 5559 switch (status) { 5560 case RTW89_MAC_MRC_START_SCH_OK: 5561 func = H2C_FUNC_START_MRC; 5562 break; 5563 case RTW89_MAC_MRC_STOP_SCH_OK: 5564 /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5565 func = H2C_FUNC_DEL_MRC; 5566 next = true; 5567 break; 5568 case RTW89_MAC_MRC_DEL_SCH_OK: 5569 func = H2C_FUNC_DEL_MRC; 5570 break; 5571 case RTW89_MAC_MRC_EMPTY_SCH_FAIL: 5572 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5573 "MRC C2H STS RPT: empty sch fail\n"); 5574 return; 5575 case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL: 5576 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5577 "MRC C2H STS RPT: role not exist fail\n"); 5578 return; 5579 case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL: 5580 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5581 "MRC C2H STS RPT: data not found fail\n"); 5582 return; 5583 case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL: 5584 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5585 "MRC C2H STS RPT: get next slot fail\n"); 5586 return; 5587 case RTW89_MAC_MRC_ALT_ROLE_FAIL: 5588 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5589 "MRC C2H STS RPT: alt role fail\n"); 5590 return; 5591 case RTW89_MAC_MRC_ADD_PSTIMER_FAIL: 5592 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5593 "MRC C2H STS RPT: add ps timer fail\n"); 5594 return; 5595 case RTW89_MAC_MRC_MALLOC_FAIL: 5596 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5597 "MRC C2H STS RPT: malloc fail\n"); 5598 return; 5599 case RTW89_MAC_MRC_SWITCH_CH_FAIL: 5600 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5601 "MRC C2H STS RPT: switch ch fail\n"); 5602 return; 5603 case RTW89_MAC_MRC_TXNULL0_FAIL: 5604 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5605 "MRC C2H STS RPT: tx null-0 fail\n"); 5606 return; 5607 case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL: 5608 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5609 "MRC C2H STS RPT: port func en fail\n"); 5610 return; 5611 default: 5612 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5613 "invalid MRC C2H STS RPT: status %d\n", status); 5614 return; 5615 } 5616 5617 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5618 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 5619 sch_idx, status, (u64)tsf_high << 32 | tsf_low); 5620 5621 if (next) 5622 return; 5623 5624 cond = RTW89_MRC_WAIT_COND(sch_idx, func); 5625 rtw89_complete_cond(wait, cond, &data); 5626 } 5627 5628 static void 5629 rtw89_mac_c2h_pwr_int_notify(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5630 { 5631 const struct rtw89_c2h_pwr_int_notify *c2h; 5632 struct rtw89_sta_link *rtwsta_link; 5633 struct ieee80211_sta *sta; 5634 struct rtw89_sta *rtwsta; 5635 u16 macid; 5636 bool ps; 5637 5638 c2h = (const struct rtw89_c2h_pwr_int_notify *)skb->data; 5639 macid = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_MACID); 5640 ps = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS); 5641 5642 rcu_read_lock(); 5643 5644 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 5645 if (unlikely(!rtwsta_link)) 5646 goto out; 5647 5648 rtwsta = rtwsta_link->rtwsta; 5649 if (ps) 5650 set_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5651 else 5652 clear_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5653 5654 sta = rtwsta_to_sta(rtwsta); 5655 ieee80211_sta_ps_transition(sta, ps); 5656 5657 out: 5658 rcu_read_unlock(); 5659 } 5660 5661 static 5662 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5663 struct sk_buff *c2h, u32 len) = { 5664 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5665 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5666 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5667 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = rtw89_mac_c2h_bcn_resend, 5668 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5669 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5670 [RTW89_MAC_C2H_FUNC_TX_DUTY_RPT] = rtw89_mac_c2h_tx_duty_rpt, 5671 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5672 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5673 }; 5674 5675 static 5676 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5677 struct sk_buff *c2h, u32 len) = { 5678 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5679 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5680 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5681 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5682 [RTW89_MAC_C2H_FUNC_BCN_UPD_DONE] = rtw89_mac_c2h_bcn_upd_done, 5683 }; 5684 5685 static 5686 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5687 struct sk_buff *c2h, u32 len) = { 5688 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5689 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5690 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5691 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5692 }; 5693 5694 static 5695 void (* const rtw89_mac_c2h_mlo_handler[])(struct rtw89_dev *rtwdev, 5696 struct sk_buff *c2h, u32 len) = { 5697 [RTW89_MAC_C2H_FUNC_MLO_GET_TBL] = NULL, 5698 [RTW89_MAC_C2H_FUNC_MLO_EMLSR_TRANS_DONE] = NULL, 5699 [RTW89_MAC_C2H_FUNC_MLO_EMLSR_STA_CFG_DONE] = NULL, 5700 [RTW89_MAC_C2H_FUNC_MCMLO_RELINK_RPT] = NULL, 5701 [RTW89_MAC_C2H_FUNC_MCMLO_SN_SYNC_RPT] = NULL, 5702 [RTW89_MAC_C2H_FUNC_MLO_LINK_CFG_STAT] = rtw89_mac_c2h_mlo_link_cfg_stat, 5703 [RTW89_MAC_C2H_FUNC_MLO_DM_DBG_DUMP] = NULL, 5704 }; 5705 5706 static 5707 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 5708 struct sk_buff *c2h, u32 len) = { 5709 [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 5710 [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 5711 }; 5712 5713 static 5714 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev, 5715 struct sk_buff *c2h, u32 len) = { 5716 [RTW89_MAC_C2H_FUNC_AOAC_REPORT] = rtw89_mac_c2h_wow_aoac_rpt, 5717 }; 5718 5719 static 5720 void (* const rtw89_mac_c2h_ap_handler[])(struct rtw89_dev *rtwdev, 5721 struct sk_buff *c2h, u32 len) = { 5722 [RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY] = rtw89_mac_c2h_pwr_int_notify, 5723 }; 5724 5725 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 5726 struct sk_buff *skb) 5727 { 5728 const struct rtw89_c2h_scanofld *c2h = 5729 (const struct rtw89_c2h_scanofld *)skb->data; 5730 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5731 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 5732 struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(skb); 5733 struct rtw89_completion_data data = {}; 5734 unsigned int cond; 5735 u8 status, reason; 5736 5737 attr->is_scan_event = 1; 5738 attr->scan_seq = scan_info->seq; 5739 5740 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5741 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5742 data.err = status != RTW89_SCAN_STATUS_SUCCESS; 5743 5744 if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 5745 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 5746 cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 5747 else 5748 cond = RTW89_SCANOFLD_WAIT_COND_STOP; 5749 5750 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5751 } 5752 } 5753 5754 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5755 u8 class, u8 func) 5756 { 5757 switch (class) { 5758 default: 5759 return false; 5760 case RTW89_MAC_C2H_CLASS_INFO: 5761 switch (func) { 5762 default: 5763 return false; 5764 case RTW89_MAC_C2H_FUNC_REC_ACK: 5765 case RTW89_MAC_C2H_FUNC_DONE_ACK: 5766 return true; 5767 } 5768 case RTW89_MAC_C2H_CLASS_OFLD: 5769 switch (func) { 5770 default: 5771 return false; 5772 case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 5773 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 5774 return false; 5775 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 5776 return true; 5777 } 5778 case RTW89_MAC_C2H_CLASS_MCC: 5779 return true; 5780 case RTW89_MAC_C2H_CLASS_MLO: 5781 return true; 5782 case RTW89_MAC_C2H_CLASS_MRC: 5783 return true; 5784 case RTW89_MAC_C2H_CLASS_WOW: 5785 return true; 5786 case RTW89_MAC_C2H_CLASS_AP: 5787 switch (func) { 5788 default: 5789 return false; 5790 case RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY: 5791 return true; 5792 } 5793 } 5794 } 5795 5796 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5797 u32 len, u8 class, u8 func) 5798 { 5799 void (*handler)(struct rtw89_dev *rtwdev, 5800 struct sk_buff *c2h, u32 len) = NULL; 5801 5802 switch (class) { 5803 case RTW89_MAC_C2H_CLASS_INFO: 5804 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 5805 handler = rtw89_mac_c2h_info_handler[func]; 5806 break; 5807 case RTW89_MAC_C2H_CLASS_OFLD: 5808 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 5809 handler = rtw89_mac_c2h_ofld_handler[func]; 5810 break; 5811 case RTW89_MAC_C2H_CLASS_MCC: 5812 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 5813 handler = rtw89_mac_c2h_mcc_handler[func]; 5814 break; 5815 case RTW89_MAC_C2H_CLASS_MLO: 5816 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MLO) 5817 handler = rtw89_mac_c2h_mlo_handler[func]; 5818 break; 5819 case RTW89_MAC_C2H_CLASS_MRC: 5820 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 5821 handler = rtw89_mac_c2h_mrc_handler[func]; 5822 break; 5823 case RTW89_MAC_C2H_CLASS_WOW: 5824 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_WOW) 5825 handler = rtw89_mac_c2h_wow_handler[func]; 5826 break; 5827 case RTW89_MAC_C2H_CLASS_AP: 5828 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_AP) 5829 handler = rtw89_mac_c2h_ap_handler[func]; 5830 break; 5831 case RTW89_MAC_C2H_CLASS_FWDBG: 5832 case RTW89_MAC_C2H_CLASS_ROLE: 5833 return; 5834 default: 5835 break; 5836 } 5837 if (!handler) { 5838 rtw89_info_once(rtwdev, "MAC c2h class %d func %d not support\n", 5839 class, func); 5840 return; 5841 } 5842 handler(rtwdev, skb, len); 5843 } 5844 5845 static 5846 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 5847 enum rtw89_phy_idx phy_idx, 5848 u32 reg_base, u32 *cr) 5849 { 5850 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 5851 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 5852 5853 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 5854 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 5855 addr); 5856 goto error; 5857 } 5858 5859 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 5860 if (mode == RTW89_QTA_SCC) { 5861 rtw89_err(rtwdev, 5862 "[TXPWR] addr=0x%x but hw not enable\n", 5863 addr); 5864 goto error; 5865 } 5866 5867 *cr = addr; 5868 return true; 5869 5870 error: 5871 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 5872 addr, phy_idx); 5873 5874 return false; 5875 } 5876 5877 static 5878 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 5879 { 5880 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 5881 int ret; 5882 5883 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5884 if (ret) 5885 return ret; 5886 5887 if (!enable) { 5888 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 5889 return 0; 5890 } 5891 5892 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 5893 B_AX_APP_MAC_INFO_RPT | 5894 B_AX_APP_PLCP_HDR_RPT | 5895 B_AX_PPDU_STAT_RPT_CRC32); 5896 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 5897 RTW89_PRPT_DEST_HOST); 5898 5899 return 0; 5900 } 5901 5902 static 5903 void __rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 5904 { 5905 #define MAC_AX_TIME_TH_SH 5 5906 #define MAC_AX_LEN_TH_SH 4 5907 #define MAC_AX_TIME_TH_MAX 255 5908 #define MAC_AX_LEN_TH_MAX 255 5909 #define MAC_AX_TIME_TH_DEF 88 5910 #define MAC_AX_LEN_TH_DEF 4080 5911 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5912 struct ieee80211_hw *hw = rtwdev->hw; 5913 u32 rts_threshold = hw->wiphy->rts_threshold; 5914 u32 time_th, len_th; 5915 u32 reg; 5916 5917 if (rts_threshold == (u32)-1) { 5918 time_th = MAC_AX_TIME_TH_DEF; 5919 len_th = MAC_AX_LEN_TH_DEF; 5920 } else { 5921 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 5922 len_th = rts_threshold; 5923 } 5924 5925 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 5926 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 5927 5928 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 5929 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 5930 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 5931 } 5932 5933 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev) 5934 { 5935 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 5936 if (rtwdev->dbcc_en) 5937 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_1); 5938 } 5939 5940 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 5941 { 5942 bool empty; 5943 int ret; 5944 5945 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5946 return; 5947 5948 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 5949 10000, 200000, false, rtwdev); 5950 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 5951 rtw89_info(rtwdev, "timed out to flush queues\n"); 5952 } 5953 5954 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 5955 { 5956 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 5957 u8 val; 5958 u16 val16; 5959 u32 val32; 5960 int ret; 5961 5962 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 5963 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5964 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 5965 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 5966 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 5967 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 5968 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5969 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 5970 5971 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 5972 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 5973 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 5974 5975 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 5976 if (ret) { 5977 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 5978 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 5979 return ret; 5980 } 5981 val32 = val32 & B_AX_WL_RX_CTRL; 5982 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 5983 if (ret) { 5984 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 5985 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 5986 return ret; 5987 } 5988 5989 switch (coex->pta_mode) { 5990 case RTW89_MAC_AX_COEX_RTK_MODE: 5991 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5992 val &= ~B_AX_BTMODE_MASK; 5993 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 5994 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5995 5996 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 5997 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 5998 5999 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 6000 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 6001 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 6002 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 6003 break; 6004 case RTW89_MAC_AX_COEX_CSR_MODE: 6005 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 6006 val &= ~B_AX_BTMODE_MASK; 6007 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 6008 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 6009 6010 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 6011 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 6012 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 6013 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 6014 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 6015 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 6016 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 6017 val16 |= B_AX_ENHANCED_BT; 6018 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 6019 6020 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 6021 break; 6022 default: 6023 return -EINVAL; 6024 } 6025 6026 switch (coex->direction) { 6027 case RTW89_MAC_AX_COEX_INNER: 6028 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6029 val = (val & ~BIT(2)) | BIT(1); 6030 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6031 break; 6032 case RTW89_MAC_AX_COEX_OUTPUT: 6033 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6034 val = val | BIT(1) | BIT(0); 6035 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6036 break; 6037 case RTW89_MAC_AX_COEX_INPUT: 6038 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6039 val = val & ~(BIT(2) | BIT(1)); 6040 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6041 break; 6042 default: 6043 return -EINVAL; 6044 } 6045 6046 return 0; 6047 } 6048 EXPORT_SYMBOL(rtw89_mac_coex_init); 6049 6050 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 6051 const struct rtw89_mac_ax_coex *coex) 6052 { 6053 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 6054 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 6055 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 6056 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 6057 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 6058 6059 switch (coex->pta_mode) { 6060 case RTW89_MAC_AX_COEX_RTK_MODE: 6061 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 6062 MAC_AX_RTK_MODE); 6063 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 6064 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 6065 break; 6066 case RTW89_MAC_AX_COEX_CSR_MODE: 6067 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 6068 MAC_AX_CSR_MODE); 6069 break; 6070 default: 6071 return -EINVAL; 6072 } 6073 6074 return 0; 6075 } 6076 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 6077 6078 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6079 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6080 { 6081 u32 val = 0, ret; 6082 6083 if (gnt_cfg->band[0].gnt_bt) 6084 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 6085 6086 if (gnt_cfg->band[0].gnt_bt_sw_en) 6087 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 6088 6089 if (gnt_cfg->band[0].gnt_wl) 6090 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 6091 6092 if (gnt_cfg->band[0].gnt_wl_sw_en) 6093 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 6094 6095 if (gnt_cfg->band[1].gnt_bt) 6096 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 6097 6098 if (gnt_cfg->band[1].gnt_bt_sw_en) 6099 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 6100 6101 if (gnt_cfg->band[1].gnt_wl) 6102 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 6103 6104 if (gnt_cfg->band[1].gnt_wl_sw_en) 6105 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 6106 6107 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 6108 if (ret) { 6109 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6110 rtw89_err(rtwdev, "Write LTE fail!\n"); 6111 return ret; 6112 } 6113 6114 return 0; 6115 } 6116 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 6117 6118 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 6119 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6120 { 6121 u32 val = 0; 6122 6123 if (gnt_cfg->band[0].gnt_bt) 6124 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 6125 B_AX_GNT_BT_TX_VAL; 6126 else 6127 val |= B_AX_WL_ACT_VAL; 6128 6129 if (gnt_cfg->band[0].gnt_bt_sw_en) 6130 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 6131 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 6132 6133 if (gnt_cfg->band[0].gnt_wl) 6134 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 6135 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 6136 6137 if (gnt_cfg->band[0].gnt_wl_sw_en) 6138 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 6139 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 6140 6141 if (gnt_cfg->band[1].gnt_bt) 6142 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 6143 B_AX_GNT_BT_TX_VAL; 6144 else 6145 val |= B_AX_WL_ACT_VAL; 6146 6147 if (gnt_cfg->band[1].gnt_bt_sw_en) 6148 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 6149 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 6150 6151 if (gnt_cfg->band[1].gnt_wl) 6152 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 6153 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 6154 6155 if (gnt_cfg->band[1].gnt_wl_sw_en) 6156 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 6157 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 6158 6159 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 6160 6161 return 0; 6162 } 6163 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 6164 6165 static 6166 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 6167 { 6168 u32 reg; 6169 u16 val; 6170 int ret; 6171 6172 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 6173 if (ret) 6174 return ret; 6175 6176 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 6177 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 6178 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 6179 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 6180 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 6181 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 6182 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 6183 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 6184 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 6185 B_AX_PLT_EN; 6186 rtw89_write16(rtwdev, reg, val); 6187 6188 return 0; 6189 } 6190 6191 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 6192 { 6193 u32 fw_sb; 6194 6195 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 6196 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 6197 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 6198 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6199 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 6200 else 6201 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 6202 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 6203 val = B_AX_TOGGLE | 6204 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 6205 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 6206 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 6207 fsleep(1000); /* avoid BT FW loss information */ 6208 } 6209 6210 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 6211 { 6212 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 6213 } 6214 6215 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6216 { 6217 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 6218 6219 val = wl ? val | BIT(2) : val & ~BIT(2); 6220 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 6221 6222 return 0; 6223 } 6224 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 6225 6226 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 6227 { 6228 struct rtw89_btc *btc = &rtwdev->btc; 6229 struct rtw89_btc_dm *dm = &btc->dm; 6230 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 6231 int i; 6232 6233 if (wl) 6234 return 0; 6235 6236 for (i = 0; i < RTW89_PHY_NUM; i++) { 6237 g[i].gnt_bt_sw_en = 1; 6238 g[i].gnt_bt = 1; 6239 g[i].gnt_wl_sw_en = 1; 6240 g[i].gnt_wl = 0; 6241 } 6242 6243 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 6244 } 6245 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 6246 6247 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 6248 { 6249 const struct rtw89_chip_info *chip = rtwdev->chip; 6250 u8 val = 0; 6251 6252 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) 6253 return false; 6254 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6255 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 6256 B_AX_LTE_MUX_CTRL_PATH >> 24); 6257 6258 return !!val; 6259 } 6260 6261 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 6262 { 6263 u32 reg; 6264 u16 cnt; 6265 6266 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 6267 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 6268 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 6269 6270 return cnt; 6271 } 6272 6273 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 6274 bool keep) 6275 { 6276 u32 reg; 6277 6278 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 6279 return; 6280 6281 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 6282 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6283 if (keep) { 6284 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6285 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6286 BFRP_RX_STANDBY_TIMER_KEEP); 6287 } else { 6288 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6289 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6290 BFRP_RX_STANDBY_TIMER_RELEASE); 6291 } 6292 } 6293 6294 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 6295 { 6296 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6297 u32 reg; 6298 u32 mask = mac->bfee_ctrl.mask; 6299 6300 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 6301 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 6302 if (en) { 6303 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6304 rtw89_write32_set(rtwdev, reg, mask); 6305 } else { 6306 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6307 rtw89_write32_clr(rtwdev, reg, mask); 6308 } 6309 } 6310 6311 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 6312 { 6313 u32 reg; 6314 u32 val32; 6315 int ret; 6316 6317 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6318 if (ret) 6319 return ret; 6320 6321 /* AP mode set tx gid to 63 */ 6322 /* STA mode set tx gid to 0(default) */ 6323 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 6324 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 6325 6326 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 6327 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 6328 6329 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6330 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 6331 rtw89_write32(rtwdev, reg, val32); 6332 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 6333 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 6334 6335 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6336 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 6337 B_AX_BFMEE_USE_NSTS | 6338 B_AX_BFMEE_CSI_GID_SEL | 6339 B_AX_BFMEE_CSI_FORCE_RETE_EN); 6340 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 6341 rtw89_write32(rtwdev, reg, 6342 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 6343 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 6344 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 6345 6346 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 6347 rtw89_write32_set(rtwdev, reg, 6348 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 6349 6350 return 0; 6351 } 6352 6353 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 6354 struct rtw89_vif_link *rtwvif_link, 6355 struct rtw89_sta_link *rtwsta_link) 6356 { 6357 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 6358 struct ieee80211_link_sta *link_sta; 6359 u8 mac_idx = rtwvif_link->mac_idx; 6360 u8 port_sel = rtwvif_link->port; 6361 u8 sound_dim = 3, t; 6362 u8 *phy_cap; 6363 u32 reg; 6364 u16 val; 6365 int ret; 6366 6367 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6368 if (ret) 6369 return ret; 6370 6371 rcu_read_lock(); 6372 6373 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6374 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; 6375 6376 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6377 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 6378 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 6379 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 6380 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 6381 phy_cap[5]); 6382 sound_dim = min(sound_dim, t); 6383 } 6384 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6385 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 6386 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 6387 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 6388 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 6389 link_sta->vht_cap.cap); 6390 sound_dim = min(sound_dim, t); 6391 } 6392 nc = min(nc, sound_dim); 6393 nr = min(nr, sound_dim); 6394 6395 rcu_read_unlock(); 6396 6397 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6398 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6399 6400 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 6401 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 6402 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 6403 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 6404 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 6405 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 6406 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 6407 6408 if (port_sel == 0) 6409 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6410 else 6411 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 6412 6413 rtw89_write16(rtwdev, reg, val); 6414 6415 return 0; 6416 } 6417 6418 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 6419 struct rtw89_vif_link *rtwvif_link, 6420 struct rtw89_sta_link *rtwsta_link) 6421 { 6422 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 6423 struct ieee80211_link_sta *link_sta; 6424 u8 mac_idx = rtwvif_link->mac_idx; 6425 u32 reg; 6426 int ret; 6427 6428 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6429 if (ret) 6430 return ret; 6431 6432 rcu_read_lock(); 6433 6434 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6435 6436 if (link_sta->he_cap.has_he) { 6437 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 6438 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 6439 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 6440 } 6441 if (link_sta->vht_cap.vht_supported) { 6442 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 6443 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 6444 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 6445 } 6446 if (link_sta->ht_cap.ht_supported) { 6447 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 6448 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 6449 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 6450 } 6451 6452 rcu_read_unlock(); 6453 6454 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6455 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6456 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 6457 rtw89_write32(rtwdev, 6458 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 6459 rrsc); 6460 6461 return 0; 6462 } 6463 6464 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 6465 struct rtw89_vif_link *rtwvif_link, 6466 struct rtw89_sta_link *rtwsta_link) 6467 { 6468 struct ieee80211_link_sta *link_sta; 6469 bool has_beamformer_cap; 6470 6471 rcu_read_lock(); 6472 6473 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6474 has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta); 6475 6476 rcu_read_unlock(); 6477 6478 if (has_beamformer_cap) { 6479 rtw89_debug(rtwdev, RTW89_DBG_BF, 6480 "initialize bfee for new association\n"); 6481 rtw89_mac_init_bfee_ax(rtwdev, rtwvif_link->mac_idx); 6482 rtw89_mac_set_csi_para_reg_ax(rtwdev, rtwvif_link, rtwsta_link); 6483 rtw89_mac_csi_rrsc_ax(rtwdev, rtwvif_link, rtwsta_link); 6484 } 6485 } 6486 6487 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, 6488 struct rtw89_vif_link *rtwvif_link, 6489 struct rtw89_sta_link *rtwsta_link) 6490 { 6491 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, false); 6492 } 6493 6494 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6495 struct ieee80211_bss_conf *conf) 6496 { 6497 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 6498 struct rtw89_vif_link *rtwvif_link; 6499 u8 mac_idx; 6500 __le32 *p; 6501 6502 rtwvif_link = rtwvif->links[conf->link_id]; 6503 if (unlikely(!rtwvif_link)) { 6504 rtw89_err(rtwdev, 6505 "%s: rtwvif link (link_id %u) is not active\n", 6506 __func__, conf->link_id); 6507 return; 6508 } 6509 6510 mac_idx = rtwvif_link->mac_idx; 6511 6512 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 6513 6514 p = (__le32 *)conf->mu_group.membership; 6515 rtw89_write32(rtwdev, 6516 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 6517 le32_to_cpu(p[0])); 6518 rtw89_write32(rtwdev, 6519 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 6520 le32_to_cpu(p[1])); 6521 6522 p = (__le32 *)conf->mu_group.position; 6523 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 6524 le32_to_cpu(p[0])); 6525 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 6526 le32_to_cpu(p[1])); 6527 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 6528 le32_to_cpu(p[2])); 6529 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 6530 le32_to_cpu(p[3])); 6531 } 6532 6533 struct rtw89_mac_bf_monitor_iter_data { 6534 struct rtw89_dev *rtwdev; 6535 struct rtw89_sta_link *down_rtwsta_link; 6536 int count; 6537 }; 6538 6539 static 6540 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 6541 { 6542 struct rtw89_mac_bf_monitor_iter_data *iter_data = 6543 (struct rtw89_mac_bf_monitor_iter_data *)data; 6544 struct rtw89_sta_link *down_rtwsta_link = iter_data->down_rtwsta_link; 6545 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6546 struct ieee80211_link_sta *link_sta; 6547 struct rtw89_sta_link *rtwsta_link; 6548 bool has_beamformer_cap = false; 6549 int *count = &iter_data->count; 6550 unsigned int link_id; 6551 6552 rcu_read_lock(); 6553 6554 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6555 if (rtwsta_link == down_rtwsta_link) 6556 continue; 6557 6558 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 6559 if (rtw89_sta_has_beamformer_cap(link_sta)) { 6560 has_beamformer_cap = true; 6561 break; 6562 } 6563 } 6564 6565 if (has_beamformer_cap) 6566 (*count)++; 6567 6568 rcu_read_unlock(); 6569 } 6570 6571 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 6572 struct rtw89_sta_link *rtwsta_link, 6573 bool disconnect) 6574 { 6575 struct rtw89_mac_bf_monitor_iter_data data; 6576 6577 data.rtwdev = rtwdev; 6578 data.down_rtwsta_link = disconnect ? rtwsta_link : NULL; 6579 data.count = 0; 6580 ieee80211_iterate_stations_atomic(rtwdev->hw, 6581 rtw89_mac_bf_monitor_calc_iter, 6582 &data); 6583 6584 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 6585 if (data.count) 6586 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6587 else 6588 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6589 } 6590 6591 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 6592 { 6593 struct rtw89_traffic_stats *stats = &rtwdev->stats; 6594 struct rtw89_vif_link *rtwvif_link; 6595 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 6596 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6597 struct rtw89_vif *rtwvif; 6598 bool keep_timer = true; 6599 unsigned int link_id; 6600 bool old_keep_timer; 6601 6602 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6603 6604 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 6605 keep_timer = false; 6606 6607 if (keep_timer != old_keep_timer) { 6608 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6609 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6610 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif_link->mac_idx, 6611 keep_timer); 6612 } 6613 6614 if (en == old) 6615 return; 6616 6617 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6618 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6619 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, en); 6620 } 6621 6622 static int 6623 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6624 u32 tx_time) 6625 { 6626 #define MAC_AX_DFLT_TX_TIME 5280 6627 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6628 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6629 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 6630 u32 reg; 6631 int ret = 0; 6632 6633 if (rtwsta_link->cctl_tx_time) { 6634 rtwsta_link->ampdu_max_time = (max_tx_time - 512) >> 9; 6635 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6636 } else { 6637 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6638 if (ret) { 6639 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 6640 return ret; 6641 } 6642 6643 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_limit.addr, mac_idx); 6644 rtw89_write32_mask(rtwdev, reg, mac->agg_limit.mask, 6645 max_tx_time >> 5); 6646 } 6647 6648 return ret; 6649 } 6650 6651 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6652 bool resume, u32 tx_time) 6653 { 6654 int ret = 0; 6655 6656 if (!resume) { 6657 rtwsta_link->cctl_tx_time = true; 6658 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6659 } else { 6660 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6661 rtwsta_link->cctl_tx_time = false; 6662 } 6663 6664 return ret; 6665 } 6666 6667 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6668 u32 *tx_time) 6669 { 6670 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6671 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6672 u32 reg; 6673 int ret = 0; 6674 6675 if (rtwsta_link->cctl_tx_time) { 6676 *tx_time = (rtwsta_link->ampdu_max_time + 1) << 9; 6677 } else { 6678 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6679 if (ret) { 6680 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 6681 return ret; 6682 } 6683 6684 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_limit.addr, mac_idx); 6685 *tx_time = rtw89_read32_mask(rtwdev, reg, mac->agg_limit.mask) << 5; 6686 } 6687 6688 return ret; 6689 } 6690 6691 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 6692 struct rtw89_sta_link *rtwsta_link, 6693 bool resume, u8 tx_retry) 6694 { 6695 int ret = 0; 6696 6697 rtwsta_link->data_tx_cnt_lmt = tx_retry; 6698 6699 if (!resume) { 6700 rtwsta_link->cctl_tx_retry_limit = true; 6701 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6702 } else { 6703 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6704 rtwsta_link->cctl_tx_retry_limit = false; 6705 } 6706 6707 return ret; 6708 } 6709 6710 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 6711 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry) 6712 { 6713 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6714 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6715 u32 reg; 6716 int ret = 0; 6717 6718 if (rtwsta_link->cctl_tx_retry_limit) { 6719 *tx_retry = rtwsta_link->data_tx_cnt_lmt; 6720 } else { 6721 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6722 if (ret) { 6723 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 6724 return ret; 6725 } 6726 6727 reg = rtw89_mac_reg_by_idx(rtwdev, mac->txcnt_limit.addr, mac_idx); 6728 *tx_retry = rtw89_read32_mask(rtwdev, reg, mac->txcnt_limit.mask); 6729 } 6730 6731 return ret; 6732 } 6733 6734 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 6735 struct rtw89_vif_link *rtwvif_link, bool en) 6736 { 6737 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6738 u8 mac_idx = rtwvif_link->mac_idx; 6739 u16 set = mac->muedca_ctrl.mask; 6740 u32 reg; 6741 int ret; 6742 6743 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6744 if (ret) 6745 return ret; 6746 6747 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 6748 if (en) 6749 rtw89_write16_set(rtwdev, reg, set); 6750 else 6751 rtw89_write16_clr(rtwdev, reg, set); 6752 6753 return 0; 6754 } 6755 6756 static 6757 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 6758 { 6759 u32 val32; 6760 int ret; 6761 6762 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6763 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 6764 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 6765 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 6766 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6767 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6768 6769 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6770 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6771 if (ret) { 6772 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 6773 offset, val, mask); 6774 return ret; 6775 } 6776 6777 return 0; 6778 } 6779 6780 static 6781 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 6782 { 6783 u32 val32; 6784 int ret; 6785 6786 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6787 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 6788 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 6789 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 6790 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6791 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6792 6793 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6794 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6795 if (ret) { 6796 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 6797 return ret; 6798 } 6799 6800 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 6801 6802 return 0; 6803 } 6804 6805 static 6806 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, 6807 struct rtw89_vif_link *rtwvif_link, 6808 struct rtw89_sta_link *rtwsta_link) 6809 { 6810 static const enum rtw89_pkt_drop_sel sels[] = { 6811 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 6812 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 6813 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 6814 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 6815 }; 6816 struct rtw89_pkt_drop_params params = {0}; 6817 int i; 6818 6819 params.mac_band = rtwvif_link->mac_idx; 6820 params.macid = rtwsta_link->mac_id; 6821 params.port = rtwvif_link->port; 6822 params.mbssid = 0; 6823 params.tf_trs = rtwvif_link->trigger; 6824 6825 for (i = 0; i < ARRAY_SIZE(sels); i++) { 6826 params.sel = sels[i]; 6827 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6828 } 6829 } 6830 6831 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 6832 { 6833 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6834 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6835 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6836 struct rtw89_vif_link *rtwvif_link; 6837 struct rtw89_sta_link *rtwsta_link; 6838 struct rtw89_vif *target = data; 6839 unsigned int link_id; 6840 6841 if (rtwvif != target) 6842 return; 6843 6844 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6845 rtwvif_link = rtwsta_link->rtwvif_link; 6846 rtw89_mac_pkt_drop_sta(rtwdev, rtwvif_link, rtwsta_link); 6847 } 6848 } 6849 6850 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 6851 { 6852 ieee80211_iterate_stations_atomic(rtwdev->hw, 6853 rtw89_mac_pkt_drop_vif_iter, 6854 rtwvif); 6855 } 6856 6857 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 6858 enum rtw89_mac_idx band) 6859 { 6860 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6861 struct rtw89_pkt_drop_params params = {0}; 6862 bool empty; 6863 int i, ret = 0, try_cnt = 3; 6864 6865 params.mac_band = band; 6866 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 6867 6868 for (i = 0; i < try_cnt; i++) { 6869 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 6870 50000, false, rtwdev); 6871 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 6872 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6873 else 6874 return 0; 6875 } 6876 return ret; 6877 } 6878 6879 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 6880 { 6881 struct rtw89_mac_h2c_info h2c_info = {}; 6882 struct rtw89_mac_c2h_info c2h_info = {}; 6883 int ret; 6884 6885 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 6886 return 0; 6887 6888 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; 6889 h2c_info.content_len = sizeof(h2c_info.u.hdr); 6890 h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); 6891 6892 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 6893 if (ret) 6894 return ret; 6895 6896 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) 6897 ret = -EINVAL; 6898 6899 return ret; 6900 } 6901 6902 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 6903 { 6904 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6905 const struct rtw89_chip_info *chip = rtwdev->chip; 6906 int ret; 6907 6908 if (enable_wow) { 6909 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 6910 if (ret) { 6911 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6912 return ret; 6913 } 6914 6915 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6916 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6917 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 6918 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 6919 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 6920 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 6921 rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 6922 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 6923 6924 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 6925 return 0; 6926 6927 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6928 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 6929 else 6930 rtw89_write32_set(rtwdev, R_AX_DBG_WOW, 6931 B_AX_DBG_WOW_CPU_IO_RX_EN); 6932 } else { 6933 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 6934 if (ret) { 6935 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6936 return ret; 6937 } 6938 6939 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6940 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6941 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 6942 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 6943 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 6944 } 6945 6946 return 0; 6947 } 6948 6949 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 6950 { 6951 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 6952 6953 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 6954 } 6955 6956 static 6957 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 6958 bool h2c_or_fwdl) 6959 { 6960 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 6961 u32 timeout; 6962 u8 val; 6963 6964 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 6965 timeout = FWDL_WAIT_CNT_USB; 6966 else 6967 timeout = FWDL_WAIT_CNT; 6968 6969 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 6970 1, timeout, false, 6971 rtwdev, R_AX_WCPU_FW_CTRL); 6972 } 6973 6974 static 6975 void rtw89_fwdl_secure_idmem_share_mode_ax(struct rtw89_dev *rtwdev, u8 mode) 6976 { 6977 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 6978 6979 if (!sec->secure_boot) 6980 return; 6981 6982 rtw89_write32_mask(rtwdev, R_AX_WCPU_FW_CTRL, 6983 B_AX_IDMEM_SHARE_MODE_RECORD_MASK, mode); 6984 rtw89_write32_set(rtwdev, R_AX_WCPU_FW_CTRL, 6985 B_AX_IDMEM_SHARE_MODE_RECORD_VALID); 6986 } 6987 6988 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 6989 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 6990 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 6991 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 6992 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 6993 .mem_page_size = MAC_MEM_DUMP_PAGE_SIZE_AX, 6994 .rx_fltr = R_AX_RX_FLTR_OPT, 6995 .port_base = &rtw89_port_base_ax, 6996 .agg_len_ht = R_AX_AGG_LEN_HT_0, 6997 .ps_status = R_AX_PPWRBIT_SETTING, 6998 6999 .muedca_ctrl = { 7000 .addr = R_AX_MUEDCA_EN, 7001 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 7002 }, 7003 .bfee_ctrl = { 7004 .addr = R_AX_BFMEE_RESP_OPTION, 7005 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 7006 B_AX_BFMEE_HE_NDPA_EN, 7007 }, 7008 .narrow_bw_ru_dis = { 7009 .addr = R_AX_RXTRIG_TEST_USER_2, 7010 .mask = B_AX_RXTRIG_RU26_DIS, 7011 }, 7012 .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 7013 .agg_limit = {.addr = R_AX_AMPDU_AGG_LIMIT, .mask = B_AX_AMPDU_MAX_TIME_MASK,}, 7014 .txcnt_limit = {.addr = R_AX_TXCNT, .mask = B_AX_L_TXCNT_LMT_MASK,}, 7015 7016 .check_mac_en = rtw89_mac_check_mac_en_ax, 7017 .sys_init = sys_init_ax, 7018 .trx_init = trx_init_ax, 7019 .hci_func_en = rtw89_mac_hci_func_en_ax, 7020 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 7021 .dle_func_en = dle_func_en_ax, 7022 .dle_clk_en = dle_clk_en_ax, 7023 .bf_assoc = rtw89_mac_bf_assoc_ax, 7024 7025 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 7026 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 7027 .cfg_phy_rpt = NULL, 7028 7029 .dle_mix_cfg = dle_mix_cfg_ax, 7030 .chk_dle_rdy = chk_dle_rdy_ax, 7031 .dle_buf_req = dle_buf_req_ax, 7032 .hfc_func_en = hfc_func_en_ax, 7033 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 7034 .hfc_mix_cfg = hfc_mix_cfg_ax, 7035 .hfc_get_mix_info = hfc_get_mix_info_ax, 7036 .wde_quota_cfg = wde_quota_cfg_ax, 7037 .ple_quota_cfg = ple_quota_cfg_ax, 7038 .set_cpuio = set_cpuio_ax, 7039 .dle_quota_change = dle_quota_change_ax, 7040 7041 .disable_cpu = rtw89_mac_disable_cpu_ax, 7042 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 7043 .fwdl_get_status = rtw89_fw_get_rdy_ax, 7044 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 7045 .fwdl_secure_idmem_share_mode = rtw89_fwdl_secure_idmem_share_mode_ax, 7046 .parse_efuse_map = rtw89_parse_efuse_map_ax, 7047 .parse_phycap_map = rtw89_parse_phycap_map_ax, 7048 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 7049 .efuse_read_fw_secure = rtw89_efuse_read_fw_secure_ax, 7050 7051 .cfg_plt = rtw89_mac_cfg_plt_ax, 7052 .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 7053 7054 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 7055 7056 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 7057 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 7058 7059 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 7060 .dump_err_status = rtw89_mac_dump_err_status_ax, 7061 7062 .is_txq_empty = mac_is_txq_empty_ax, 7063 7064 .prep_chan_list = rtw89_hw_scan_prep_chan_list_ax, 7065 .free_chan_list = rtw89_hw_scan_free_chan_list_ax, 7066 .add_chan_list = rtw89_hw_scan_add_chan_list_ax, 7067 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_ax, 7068 .scan_offload = rtw89_fw_h2c_scan_offload_ax, 7069 7070 .wow_config_mac = rtw89_wow_config_mac_ax, 7071 }; 7072 EXPORT_SYMBOL(rtw89_mac_gen_ax); 7073