1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "util.h" 15 16 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 17 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 18 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 19 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 20 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 21 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 22 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 26 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 29 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 31 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 35 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 36 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 37 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 38 }; 39 40 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 41 u32 val, enum rtw89_mac_mem_sel sel) 42 { 43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44 u32 addr = mac->mem_base_addrs[sel] + offset; 45 46 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 47 rtw89_write32(rtwdev, mac->indir_access_addr, val); 48 } 49 50 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 51 enum rtw89_mac_mem_sel sel) 52 { 53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 54 u32 addr = mac->mem_base_addrs[sel] + offset; 55 56 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 57 return rtw89_read32(rtwdev, mac->indir_access_addr); 58 } 59 60 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 61 enum rtw89_mac_hwmod_sel sel) 62 { 63 u32 val, r_val; 64 65 if (sel == RTW89_DMAC_SEL) { 66 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 67 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 69 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 70 val = B_AX_CMAC_EN; 71 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 72 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 73 val = B_AX_CMAC1_FEN; 74 } else { 75 return -EINVAL; 76 } 77 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 78 (val & r_val) != val) 79 return -EFAULT; 80 81 return 0; 82 } 83 84 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 85 { 86 u8 lte_ctrl; 87 int ret; 88 89 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 90 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 91 if (ret) 92 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 93 94 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 95 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 96 97 return ret; 98 } 99 100 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 101 { 102 u8 lte_ctrl; 103 int ret; 104 105 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 106 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 107 if (ret) 108 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 109 110 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 111 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 112 113 return ret; 114 } 115 116 static 117 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 118 { 119 u32 ctrl_reg, data_reg, ctrl_data; 120 u32 val; 121 int ret; 122 123 switch (ctrl->type) { 124 case DLE_CTRL_TYPE_WDE: 125 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 126 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 127 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 128 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 129 B_AX_WDE_DFI_ACTIVE; 130 break; 131 case DLE_CTRL_TYPE_PLE: 132 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 133 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 134 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 135 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 136 B_AX_PLE_DFI_ACTIVE; 137 break; 138 default: 139 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 140 return -EINVAL; 141 } 142 143 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 144 145 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 146 1, 1000, false, rtwdev, ctrl_reg); 147 if (ret) { 148 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 149 ctrl_reg, ctrl_data); 150 return ret; 151 } 152 153 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 154 return 0; 155 } 156 157 static int dle_dfi_quota(struct rtw89_dev *rtwdev, 158 struct rtw89_mac_dle_dfi_quota *quota) 159 { 160 struct rtw89_mac_dle_dfi_ctrl ctrl; 161 int ret; 162 163 ctrl.type = quota->dle_type; 164 ctrl.target = DLE_DFI_TYPE_QUOTA; 165 ctrl.addr = quota->qtaid; 166 ret = dle_dfi_ctrl(rtwdev, &ctrl); 167 if (ret) { 168 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 169 return ret; 170 } 171 172 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 173 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 174 return 0; 175 } 176 177 static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 178 struct rtw89_mac_dle_dfi_qempty *qempty) 179 { 180 struct rtw89_mac_dle_dfi_ctrl ctrl; 181 u32 ret; 182 183 ctrl.type = qempty->dle_type; 184 ctrl.target = DLE_DFI_TYPE_QEMPTY; 185 ctrl.addr = qempty->grpsel; 186 ret = dle_dfi_ctrl(rtwdev, &ctrl); 187 if (ret) { 188 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 189 return ret; 190 } 191 192 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 193 return 0; 194 } 195 196 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 197 { 198 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 199 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 200 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 201 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 202 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 203 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 204 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 205 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 206 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 207 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 208 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 209 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 210 } 211 212 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 213 { 214 struct rtw89_mac_dle_dfi_qempty qempty; 215 struct rtw89_mac_dle_dfi_quota quota; 216 struct rtw89_mac_dle_dfi_ctrl ctrl; 217 u32 val, not_empty, i; 218 int ret; 219 220 qempty.dle_type = DLE_CTRL_TYPE_PLE; 221 qempty.grpsel = 0; 222 qempty.qempty = ~(u32)0; 223 ret = dle_dfi_qempty(rtwdev, &qempty); 224 if (ret) 225 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 226 else 227 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 228 229 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 230 if (!(not_empty & BIT(0))) 231 continue; 232 ctrl.type = DLE_CTRL_TYPE_PLE; 233 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 234 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 235 FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 236 ret = dle_dfi_ctrl(rtwdev, &ctrl); 237 if (ret) 238 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 239 else 240 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 241 FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 242 ctrl.out_data)); 243 } 244 245 quota.dle_type = DLE_CTRL_TYPE_PLE; 246 quota.qtaid = 6; 247 ret = dle_dfi_quota(rtwdev, "a); 248 if (ret) 249 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 250 else 251 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 252 quota.rsv_pgnum, quota.use_pgnum); 253 254 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 255 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 256 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 257 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 258 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 259 260 dump_err_status_dispatcher(rtwdev); 261 } 262 263 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 264 enum mac_ax_err_info err) 265 { 266 u32 dbg, event; 267 268 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 269 event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 270 271 switch (event) { 272 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 273 rtw89_info(rtwdev, "quota lost!\n"); 274 rtw89_mac_dump_qta_lost(rtwdev); 275 break; 276 default: 277 break; 278 } 279 } 280 281 static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 282 { 283 const struct rtw89_chip_info *chip = rtwdev->chip; 284 u32 dmac_err; 285 int i, ret; 286 287 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 288 if (ret) { 289 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 290 return; 291 } 292 293 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 294 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 295 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 296 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 297 298 if (dmac_err) { 299 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 300 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 301 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 302 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 303 if (chip->chip_id == RTL8852C) { 304 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 305 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 306 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 307 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 308 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 309 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 310 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 311 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 312 } 313 } 314 315 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 316 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 317 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 318 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 319 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 320 if (chip->chip_id == RTL8852C) 321 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 322 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 323 else 324 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 325 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 326 } 327 328 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 329 if (chip->chip_id == RTL8852C) { 330 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 331 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 332 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 333 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 334 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 335 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 336 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 337 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 338 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 339 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 340 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 341 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 342 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 343 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 344 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 345 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 346 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 348 349 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 350 B_AX_DBG_SEL0, 0x8B); 351 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 352 B_AX_DBG_SEL1, 0x8B); 353 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 354 B_AX_SEL_0XC0_MASK, 1); 355 for (i = 0; i < 0x10; i++) { 356 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 357 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 358 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 359 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 360 } 361 } else { 362 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 363 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 364 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 365 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 366 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 367 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 368 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 369 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 370 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 371 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 372 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 374 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 376 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 378 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 380 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 382 } 383 } 384 385 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 386 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 388 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 389 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 390 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 391 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 392 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 393 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 394 } 395 396 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 397 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 398 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 399 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 400 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 401 } 402 403 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 404 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 405 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 406 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 407 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 408 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 409 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 410 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 411 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 412 } 413 414 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 415 if (chip->chip_id == RTL8852C) { 416 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 417 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 418 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 419 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 420 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 421 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 422 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 423 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 424 } else { 425 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 427 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 429 } 430 } 431 432 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 433 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 435 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 437 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 438 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 439 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 440 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 441 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 442 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 443 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 445 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 447 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 449 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 450 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 451 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 452 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 453 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 454 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 455 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 456 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 457 if (chip->chip_id == RTL8852C) { 458 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 459 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 460 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 462 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 463 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 464 } else { 465 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 466 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 467 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 468 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 469 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 470 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 471 } 472 } 473 474 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 475 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 476 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 477 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 478 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 479 } 480 481 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 482 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 484 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 486 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 487 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 488 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 489 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 490 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 491 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 492 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 493 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 494 } 495 496 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 497 if (chip->chip_id == RTL8852C) { 498 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 499 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 500 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 501 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 502 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 503 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 504 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 505 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 506 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 507 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 508 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 509 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 510 } else { 511 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 513 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 515 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 516 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 517 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 518 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 519 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 520 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 521 } 522 } 523 524 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 525 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 526 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 527 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 529 } 530 } 531 532 static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev, 533 u8 band) 534 { 535 const struct rtw89_chip_info *chip = rtwdev->chip; 536 u32 offset = 0; 537 u32 cmac_err; 538 int ret; 539 540 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 541 if (ret) { 542 if (band) 543 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 544 else 545 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 546 return; 547 } 548 549 if (band) 550 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 551 552 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 553 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 554 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 555 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 556 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 557 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 558 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 559 560 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 561 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 562 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 563 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 564 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 565 } 566 567 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 568 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 569 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 570 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 571 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 572 } 573 574 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 575 if (chip->chip_id == RTL8852C) { 576 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 577 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 578 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 579 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 580 } else { 581 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 582 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 583 } 584 } 585 586 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 587 if (chip->chip_id == RTL8852C) { 588 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 589 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 590 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 591 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 592 } else { 593 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 594 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 595 } 596 } 597 598 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 599 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 600 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 601 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 602 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 603 } 604 605 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 606 if (chip->chip_id == RTL8852C) { 607 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 608 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 609 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 610 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 611 } else { 612 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 613 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 614 } 615 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 616 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 617 } 618 619 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 620 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 621 } 622 623 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 624 enum mac_ax_err_info err) 625 { 626 if (err != MAC_AX_ERR_L1_ERR_DMAC && 627 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 628 err != MAC_AX_ERR_L0_ERR_CMAC0 && 629 err != MAC_AX_ERR_L0_ERR_CMAC1 && 630 err != MAC_AX_ERR_RXI300) 631 return; 632 633 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 634 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 635 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 636 637 rtw89_mac_dump_dmac_err_status(rtwdev); 638 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0); 639 if (rtwdev->dbcc_en) 640 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1); 641 642 rtwdev->hci.ops->dump_err_status(rtwdev); 643 644 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 645 rtw89_mac_dump_l0_to_l1(rtwdev, err); 646 647 rtw89_info(rtwdev, "<---\n"); 648 } 649 650 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 651 { 652 struct rtw89_ser *ser = &rtwdev->ser; 653 u32 dmac_err, imr, isr; 654 int ret; 655 656 if (rtwdev->chip->chip_id == RTL8852C) { 657 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 658 if (ret) 659 return true; 660 661 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 662 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 663 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 664 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 665 666 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 667 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 668 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 669 return true; 670 } 671 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 672 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 673 return true; 674 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 675 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 676 return true; 677 } 678 } 679 680 return false; 681 } 682 683 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 684 { 685 u32 err, err_scnr; 686 int ret; 687 688 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 689 false, rtwdev, R_AX_HALT_C2H_CTRL); 690 if (ret) { 691 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 692 return ret; 693 } 694 695 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 696 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 697 698 err_scnr = RTW89_ERROR_SCENARIO(err); 699 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 700 err = MAC_AX_ERR_CPU_EXCEPTION; 701 else if (err_scnr == RTW89_WCPU_ASSERTION) 702 err = MAC_AX_ERR_ASSERTION; 703 else if (err_scnr == RTW89_RXI300_ERROR) 704 err = MAC_AX_ERR_RXI300; 705 706 if (rtw89_mac_suppress_log(rtwdev, err)) 707 return err; 708 709 rtw89_fw_st_dbg_dump(rtwdev); 710 rtw89_mac_dump_err_status(rtwdev, err); 711 712 return err; 713 } 714 EXPORT_SYMBOL(rtw89_mac_get_err_status); 715 716 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 717 { 718 struct rtw89_ser *ser = &rtwdev->ser; 719 u32 halt; 720 int ret = 0; 721 722 if (err > MAC_AX_SET_ERR_MAX) { 723 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 724 return -EINVAL; 725 } 726 727 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 728 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 729 if (ret) { 730 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 731 return -EFAULT; 732 } 733 734 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 735 736 if (ser->prehandle_l1 && 737 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 738 return 0; 739 740 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 741 742 return 0; 743 } 744 EXPORT_SYMBOL(rtw89_mac_set_err_status); 745 746 static int hfc_reset_param(struct rtw89_dev *rtwdev) 747 { 748 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 749 struct rtw89_hfc_param_ini param_ini = {NULL}; 750 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 751 752 switch (rtwdev->hci.type) { 753 case RTW89_HCI_TYPE_PCIE: 754 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 755 param->en = 0; 756 break; 757 default: 758 return -EINVAL; 759 } 760 761 if (param_ini.pub_cfg) 762 param->pub_cfg = *param_ini.pub_cfg; 763 764 if (param_ini.prec_cfg) 765 param->prec_cfg = *param_ini.prec_cfg; 766 767 if (param_ini.ch_cfg) 768 param->ch_cfg = param_ini.ch_cfg; 769 770 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 771 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 772 param->mode = param_ini.mode; 773 774 return 0; 775 } 776 777 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 778 { 779 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 780 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 781 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 782 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 783 784 if (ch >= RTW89_DMA_CH_NUM) 785 return -EINVAL; 786 787 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 788 ch_cfg[ch].max > pub_cfg->pub_max) 789 return -EINVAL; 790 if (ch_cfg[ch].grp >= grp_num) 791 return -EINVAL; 792 793 return 0; 794 } 795 796 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 797 { 798 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 799 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 800 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 801 802 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 803 if (rtwdev->chip->chip_id == RTL8852A) 804 return 0; 805 else 806 return -EFAULT; 807 } 808 809 return 0; 810 } 811 812 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 813 { 814 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 815 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 816 817 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 818 return -EFAULT; 819 820 return 0; 821 } 822 823 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 824 { 825 const struct rtw89_chip_info *chip = rtwdev->chip; 826 const struct rtw89_page_regs *regs = chip->page_regs; 827 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 828 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 829 int ret = 0; 830 u32 val = 0; 831 832 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 833 if (ret) 834 return ret; 835 836 ret = hfc_ch_cfg_chk(rtwdev, ch); 837 if (ret) 838 return ret; 839 840 if (ch > RTW89_DMA_B1HI) 841 return -EINVAL; 842 843 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 844 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 845 (cfg[ch].grp ? B_AX_GRP : 0); 846 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 847 848 return 0; 849 } 850 851 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 852 { 853 const struct rtw89_chip_info *chip = rtwdev->chip; 854 const struct rtw89_page_regs *regs = chip->page_regs; 855 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 856 struct rtw89_hfc_ch_info *info = param->ch_info; 857 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 858 u32 val; 859 u32 ret; 860 861 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 862 if (ret) 863 return ret; 864 865 if (ch > RTW89_DMA_H2C) 866 return -EINVAL; 867 868 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 869 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 870 if (ch < RTW89_DMA_H2C) 871 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 872 else 873 info[ch].used = cfg[ch].min - info[ch].aval; 874 875 return 0; 876 } 877 878 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 879 { 880 const struct rtw89_chip_info *chip = rtwdev->chip; 881 const struct rtw89_page_regs *regs = chip->page_regs; 882 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 883 u32 val; 884 int ret; 885 886 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 887 if (ret) 888 return ret; 889 890 ret = hfc_pub_cfg_chk(rtwdev); 891 if (ret) 892 return ret; 893 894 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 895 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 896 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 897 898 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 899 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 900 901 return 0; 902 } 903 904 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 905 { 906 const struct rtw89_chip_info *chip = rtwdev->chip; 907 const struct rtw89_page_regs *regs = chip->page_regs; 908 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 909 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 910 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 911 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 912 u32 val; 913 int ret; 914 915 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 916 if (ret) 917 return ret; 918 919 val = rtw89_read32(rtwdev, regs->pub_page_info1); 920 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 921 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 922 val = rtw89_read32(rtwdev, regs->pub_page_info3); 923 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 924 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 925 info->pub_aval = 926 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 927 B_AX_PUB_AVAL_PG_MASK); 928 info->wp_aval = 929 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 930 B_AX_WP_AVAL_PG_MASK); 931 932 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 933 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 934 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 935 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 936 prec_cfg->ch011_full_cond = 937 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 938 prec_cfg->h2c_full_cond = 939 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 940 prec_cfg->wp_ch07_full_cond = 941 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 942 prec_cfg->wp_ch811_full_cond = 943 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 944 945 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 946 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 947 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 948 949 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 950 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 951 952 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 953 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 954 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 955 956 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 957 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 958 959 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 960 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 961 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 962 963 ret = hfc_pub_info_chk(rtwdev); 964 if (param->en && ret) 965 return ret; 966 967 return 0; 968 } 969 970 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 971 { 972 const struct rtw89_chip_info *chip = rtwdev->chip; 973 const struct rtw89_page_regs *regs = chip->page_regs; 974 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 975 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 976 u32 val; 977 978 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 979 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 980 981 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 982 B_AX_HCI_FC_CH12_FULL_COND_MASK, 983 prec_cfg->h2c_full_cond); 984 } 985 986 static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 987 { 988 const struct rtw89_chip_info *chip = rtwdev->chip; 989 const struct rtw89_page_regs *regs = chip->page_regs; 990 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 991 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 992 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 993 u32 val; 994 995 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 996 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 997 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 998 999 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1000 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1001 1002 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1003 B_AX_PREC_PAGE_WP_CH07_MASK) | 1004 u32_encode_bits(prec_cfg->wp_ch811_prec, 1005 B_AX_PREC_PAGE_WP_CH811_MASK); 1006 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1007 1008 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1009 param->mode, B_AX_HCI_FC_MODE_MASK); 1010 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1011 B_AX_HCI_FC_WD_FULL_COND_MASK); 1012 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1013 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1014 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1015 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1016 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1017 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1018 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1019 } 1020 1021 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1022 { 1023 const struct rtw89_chip_info *chip = rtwdev->chip; 1024 const struct rtw89_page_regs *regs = chip->page_regs; 1025 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1026 u32 val; 1027 1028 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1029 param->en = en; 1030 param->h2c_en = h2c_en; 1031 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1032 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1033 (val & ~B_AX_HCI_FC_CH12_EN); 1034 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1035 } 1036 1037 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1038 { 1039 const struct rtw89_chip_info *chip = rtwdev->chip; 1040 u32 dma_ch_mask = chip->dma_ch_mask; 1041 u8 ch; 1042 u32 ret = 0; 1043 1044 if (reset) 1045 ret = hfc_reset_param(rtwdev); 1046 if (ret) 1047 return ret; 1048 1049 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1050 if (ret) 1051 return ret; 1052 1053 hfc_func_en(rtwdev, false, false); 1054 1055 if (!en && h2c_en) { 1056 hfc_h2c_cfg(rtwdev); 1057 hfc_func_en(rtwdev, en, h2c_en); 1058 return ret; 1059 } 1060 1061 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1062 if (dma_ch_mask & BIT(ch)) 1063 continue; 1064 ret = hfc_ch_ctrl(rtwdev, ch); 1065 if (ret) 1066 return ret; 1067 } 1068 1069 ret = hfc_pub_ctrl(rtwdev); 1070 if (ret) 1071 return ret; 1072 1073 hfc_mix_cfg(rtwdev); 1074 if (en || h2c_en) { 1075 hfc_func_en(rtwdev, en, h2c_en); 1076 udelay(10); 1077 } 1078 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1079 if (dma_ch_mask & BIT(ch)) 1080 continue; 1081 ret = hfc_upd_ch_info(rtwdev, ch); 1082 if (ret) 1083 return ret; 1084 } 1085 ret = hfc_upd_mix_info(rtwdev); 1086 1087 return ret; 1088 } 1089 1090 #define PWR_POLL_CNT 2000 1091 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1092 const struct rtw89_pwr_cfg *cfg) 1093 { 1094 u8 val = 0; 1095 int ret; 1096 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1097 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1098 1099 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1100 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1101 1102 if (!ret) 1103 return 0; 1104 1105 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1106 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1107 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1108 1109 return -EBUSY; 1110 } 1111 1112 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1113 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1114 { 1115 const struct rtw89_pwr_cfg *cur_cfg; 1116 u32 addr; 1117 u8 val; 1118 1119 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1120 if (!(cur_cfg->intf_msk & intf_msk) || 1121 !(cur_cfg->cv_msk & cv_msk)) 1122 continue; 1123 1124 switch (cur_cfg->cmd) { 1125 case PWR_CMD_WRITE: 1126 addr = cur_cfg->addr; 1127 1128 if (cur_cfg->base == PWR_BASE_SDIO) 1129 addr |= SDIO_LOCAL_BASE_ADDR; 1130 1131 val = rtw89_read8(rtwdev, addr); 1132 val &= ~(cur_cfg->msk); 1133 val |= (cur_cfg->val & cur_cfg->msk); 1134 1135 rtw89_write8(rtwdev, addr, val); 1136 break; 1137 case PWR_CMD_POLL: 1138 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1139 return -EBUSY; 1140 break; 1141 case PWR_CMD_DELAY: 1142 if (cur_cfg->val == PWR_DELAY_US) 1143 udelay(cur_cfg->addr); 1144 else 1145 fsleep(cur_cfg->addr * 1000); 1146 break; 1147 default: 1148 return -EINVAL; 1149 } 1150 } 1151 1152 return 0; 1153 } 1154 1155 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1156 const struct rtw89_pwr_cfg * const *cfg_seq) 1157 { 1158 int ret; 1159 1160 for (; *cfg_seq; cfg_seq++) { 1161 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1162 PWR_INTF_MSK_PCIE, *cfg_seq); 1163 if (ret) 1164 return -EBUSY; 1165 } 1166 1167 return 0; 1168 } 1169 1170 static enum rtw89_rpwm_req_pwr_state 1171 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1172 { 1173 enum rtw89_rpwm_req_pwr_state state; 1174 1175 switch (rtwdev->ps_mode) { 1176 case RTW89_PS_MODE_RFOFF: 1177 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1178 break; 1179 case RTW89_PS_MODE_CLK_GATED: 1180 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1181 break; 1182 case RTW89_PS_MODE_PWR_GATED: 1183 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1184 break; 1185 default: 1186 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1187 break; 1188 } 1189 return state; 1190 } 1191 1192 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1193 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1194 bool notify_wake) 1195 { 1196 u16 request; 1197 1198 spin_lock_bh(&rtwdev->rpwm_lock); 1199 1200 request = rtw89_read16(rtwdev, R_AX_RPWM); 1201 request ^= request | PS_RPWM_TOGGLE; 1202 request |= req_pwr_state; 1203 1204 if (notify_wake) { 1205 request |= PS_RPWM_NOTIFY_WAKE; 1206 } else { 1207 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1208 RPWM_SEQ_NUM_MAX; 1209 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1210 rtwdev->mac.rpwm_seq_num); 1211 1212 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1213 request |= PS_RPWM_ACK; 1214 } 1215 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1216 1217 spin_unlock_bh(&rtwdev->rpwm_lock); 1218 } 1219 1220 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1221 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1222 { 1223 bool request_deep_mode; 1224 bool in_deep_mode; 1225 u8 rpwm_req_num; 1226 u8 cpwm_rsp_seq; 1227 u8 cpwm_seq; 1228 u8 cpwm_status; 1229 1230 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1231 request_deep_mode = true; 1232 else 1233 request_deep_mode = false; 1234 1235 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1236 in_deep_mode = true; 1237 else 1238 in_deep_mode = false; 1239 1240 if (request_deep_mode != in_deep_mode) 1241 return -EPERM; 1242 1243 if (request_deep_mode) 1244 return 0; 1245 1246 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1247 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1248 PS_CPWM_RSP_SEQ_NUM); 1249 1250 if (rpwm_req_num != cpwm_rsp_seq) 1251 return -EPERM; 1252 1253 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1254 CPWM_SEQ_NUM_MAX; 1255 1256 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1257 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1258 return -EPERM; 1259 1260 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1261 if (cpwm_status != req_pwr_state) 1262 return -EPERM; 1263 1264 return 0; 1265 } 1266 1267 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1268 { 1269 enum rtw89_rpwm_req_pwr_state state; 1270 unsigned long delay = enter ? 10 : 150; 1271 int ret; 1272 int i; 1273 1274 if (enter) 1275 state = rtw89_mac_get_req_pwr_state(rtwdev); 1276 else 1277 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1278 1279 for (i = 0; i < RPWM_TRY_CNT; i++) { 1280 rtw89_mac_send_rpwm(rtwdev, state, false); 1281 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1282 !ret, delay, 15000, false, 1283 rtwdev, state); 1284 if (!ret) 1285 break; 1286 1287 if (i == RPWM_TRY_CNT - 1) 1288 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1289 enter ? "entering" : "leaving"); 1290 else 1291 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1292 "%d time firmware failed to ack for %s ps mode\n", 1293 i + 1, enter ? "entering" : "leaving"); 1294 } 1295 } 1296 1297 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1298 { 1299 enum rtw89_rpwm_req_pwr_state state; 1300 1301 state = rtw89_mac_get_req_pwr_state(rtwdev); 1302 rtw89_mac_send_rpwm(rtwdev, state, true); 1303 } 1304 1305 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1306 { 1307 #define PWR_ACT 1 1308 const struct rtw89_chip_info *chip = rtwdev->chip; 1309 const struct rtw89_pwr_cfg * const *cfg_seq; 1310 int (*cfg_func)(struct rtw89_dev *rtwdev); 1311 int ret; 1312 u8 val; 1313 1314 if (on) { 1315 cfg_seq = chip->pwr_on_seq; 1316 cfg_func = chip->ops->pwr_on_func; 1317 } else { 1318 cfg_seq = chip->pwr_off_seq; 1319 cfg_func = chip->ops->pwr_off_func; 1320 } 1321 1322 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1323 __rtw89_leave_ps_mode(rtwdev); 1324 1325 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1326 if (on && val == PWR_ACT) { 1327 rtw89_err(rtwdev, "MAC has already powered on\n"); 1328 return -EBUSY; 1329 } 1330 1331 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1332 if (ret) 1333 return ret; 1334 1335 if (on) { 1336 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1337 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1338 } else { 1339 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1340 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1341 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1342 rtw89_set_entity_state(rtwdev, false); 1343 } 1344 1345 return 0; 1346 #undef PWR_ACT 1347 } 1348 1349 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1350 { 1351 rtw89_mac_power_switch(rtwdev, false); 1352 } 1353 1354 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1355 { 1356 u32 func_en = 0; 1357 u32 ck_en = 0; 1358 u32 c1pc_en = 0; 1359 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1360 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1361 1362 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1363 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1364 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1365 B_AX_CMAC_CRPRT; 1366 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1367 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1368 B_AX_RMAC_CKEN; 1369 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1370 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1371 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1372 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1373 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1374 1375 if (en) { 1376 if (mac_idx == RTW89_MAC_1) { 1377 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1378 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1379 B_AX_R_SYM_ISO_CMAC12PP); 1380 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1381 B_AX_CMAC1_FEN); 1382 } 1383 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1384 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1385 } else { 1386 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1387 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1388 if (mac_idx == RTW89_MAC_1) { 1389 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1390 B_AX_CMAC1_FEN); 1391 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1392 B_AX_R_SYM_ISO_CMAC12PP); 1393 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1394 } 1395 } 1396 1397 return 0; 1398 } 1399 1400 static int dmac_func_en(struct rtw89_dev *rtwdev) 1401 { 1402 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1403 u32 val32; 1404 1405 if (chip_id == RTL8852C) 1406 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1407 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1408 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1409 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1410 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1411 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1412 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1413 else 1414 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1415 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1416 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1417 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1418 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1419 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1420 B_AX_DMAC_CRPRT); 1421 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1422 1423 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1424 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1425 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1426 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1427 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1428 1429 return 0; 1430 } 1431 1432 static int chip_func_en(struct rtw89_dev *rtwdev) 1433 { 1434 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1435 1436 if (chip_id == RTL8852A || chip_id == RTL8852B) 1437 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1438 B_AX_OCP_L1_MASK); 1439 1440 return 0; 1441 } 1442 1443 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1444 { 1445 int ret; 1446 1447 ret = dmac_func_en(rtwdev); 1448 if (ret) 1449 return ret; 1450 1451 ret = cmac_func_en(rtwdev, 0, true); 1452 if (ret) 1453 return ret; 1454 1455 ret = chip_func_en(rtwdev); 1456 if (ret) 1457 return ret; 1458 1459 return ret; 1460 } 1461 1462 const struct rtw89_mac_size_set rtw89_mac_size = { 1463 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1464 /* PCIE 64 */ 1465 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1466 /* DLFW */ 1467 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1468 /* PCIE 64 */ 1469 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1470 /* 8852B PCIE SCC */ 1471 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1472 /* DLFW */ 1473 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1474 /* 8852C DLFW */ 1475 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1476 /* 8852C PCIE SCC */ 1477 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1478 /* PCIE */ 1479 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1480 /* DLFW */ 1481 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1482 /* PCIE 64 */ 1483 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1484 /* DLFW */ 1485 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1486 /* 8852C DLFW */ 1487 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1488 /* 8852C PCIE SCC */ 1489 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1490 /* PCIE 64 */ 1491 .wde_qt0 = {3792, 196, 0, 107,}, 1492 /* DLFW */ 1493 .wde_qt4 = {0, 0, 0, 0,}, 1494 /* PCIE 64 */ 1495 .wde_qt6 = {448, 48, 0, 16,}, 1496 /* 8852B PCIE SCC */ 1497 .wde_qt7 = {446, 48, 0, 16,}, 1498 /* 8852C DLFW */ 1499 .wde_qt17 = {0, 0, 0, 0,}, 1500 /* 8852C PCIE SCC */ 1501 .wde_qt18 = {3228, 60, 0, 40,}, 1502 /* PCIE SCC */ 1503 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1504 /* PCIE SCC */ 1505 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1506 /* DLFW */ 1507 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1508 /* PCIE 64 */ 1509 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1510 /* DLFW 52C */ 1511 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1512 /* DLFW 52C */ 1513 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1514 /* 8852C PCIE SCC */ 1515 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1516 /* 8852C PCIE SCC */ 1517 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1518 /* PCIE 64 */ 1519 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1520 /* 8852A PCIE WOW */ 1521 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1522 /* 8852B PCIE WOW */ 1523 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1524 /* 8851B PCIE WOW */ 1525 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1526 }; 1527 EXPORT_SYMBOL(rtw89_mac_size); 1528 1529 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1530 enum rtw89_qta_mode mode) 1531 { 1532 struct rtw89_mac_info *mac = &rtwdev->mac; 1533 const struct rtw89_dle_mem *cfg; 1534 1535 cfg = &rtwdev->chip->dle_mem[mode]; 1536 if (!cfg) 1537 return NULL; 1538 1539 if (cfg->mode != mode) { 1540 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1541 return NULL; 1542 } 1543 1544 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1545 mac->dle_info.qta_mode = mode; 1546 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1547 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1548 1549 return cfg; 1550 } 1551 1552 static bool mac_is_txq_empty(struct rtw89_dev *rtwdev) 1553 { 1554 struct rtw89_mac_dle_dfi_qempty qempty; 1555 u32 qnum, qtmp, val32, msk32; 1556 int i, j, ret; 1557 1558 qnum = rtwdev->chip->wde_qempty_acq_num; 1559 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1560 1561 for (i = 0; i < qnum; i++) { 1562 qempty.grpsel = i; 1563 ret = dle_dfi_qempty(rtwdev, &qempty); 1564 if (ret) { 1565 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1566 return false; 1567 } 1568 qtmp = qempty.qempty; 1569 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1570 val32 = FIELD_GET(QEMP_ACQ_GRP_QSEL_MASK, qtmp); 1571 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1572 return false; 1573 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1574 } 1575 } 1576 1577 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel; 1578 ret = dle_dfi_qempty(rtwdev, &qempty); 1579 if (ret) { 1580 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1581 return false; 1582 } 1583 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1584 if ((qempty.qempty & msk32) != msk32) 1585 return false; 1586 1587 if (rtwdev->dbcc_en) { 1588 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1589 if ((qempty.qempty & msk32) != msk32) 1590 return false; 1591 } 1592 1593 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1594 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1595 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1596 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1597 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1598 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1599 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1600 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1601 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1602 1603 return (val32 & msk32) == msk32; 1604 } 1605 1606 static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1607 const struct rtw89_dle_size *ple) 1608 { 1609 return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1610 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1611 } 1612 1613 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1614 enum rtw89_qta_mode mode) 1615 { 1616 u32 size = rtwdev->chip->fifo_size; 1617 1618 if (mode == RTW89_QTA_SCC) 1619 size -= rtwdev->chip->dle_scc_rsvd_size; 1620 1621 return size; 1622 } 1623 1624 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1625 { 1626 if (enable) 1627 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1628 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1629 else 1630 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1631 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1632 } 1633 1634 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1635 { 1636 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1637 1638 if (enable) { 1639 if (rtwdev->chip->chip_id == RTL8851B) 1640 val |= B_AX_AXIDMA_CLK_EN; 1641 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1642 } else { 1643 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1644 } 1645 } 1646 1647 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1648 { 1649 const struct rtw89_dle_size *size_cfg; 1650 u32 val; 1651 u8 bound = 0; 1652 1653 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1654 size_cfg = cfg->wde_size; 1655 1656 switch (size_cfg->pge_size) { 1657 default: 1658 case RTW89_WDE_PG_64: 1659 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1660 B_AX_WDE_PAGE_SEL_MASK); 1661 break; 1662 case RTW89_WDE_PG_128: 1663 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1664 B_AX_WDE_PAGE_SEL_MASK); 1665 break; 1666 case RTW89_WDE_PG_256: 1667 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1668 return -EINVAL; 1669 } 1670 1671 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1672 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1673 B_AX_WDE_FREE_PAGE_NUM_MASK); 1674 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1675 1676 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1677 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1678 * size_cfg->pge_size / DLE_BOUND_UNIT; 1679 size_cfg = cfg->ple_size; 1680 1681 switch (size_cfg->pge_size) { 1682 default: 1683 case RTW89_PLE_PG_64: 1684 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1685 return -EINVAL; 1686 case RTW89_PLE_PG_128: 1687 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1688 B_AX_PLE_PAGE_SEL_MASK); 1689 break; 1690 case RTW89_PLE_PG_256: 1691 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1692 B_AX_PLE_PAGE_SEL_MASK); 1693 break; 1694 } 1695 1696 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1697 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1698 B_AX_PLE_FREE_PAGE_NUM_MASK); 1699 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1700 1701 return 0; 1702 } 1703 1704 #define INVALID_QT_WCPU U16_MAX 1705 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1706 do { \ 1707 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1708 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1709 rtw89_write32(rtwdev, \ 1710 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1711 val); \ 1712 } while (0) 1713 #define SET_QUOTA(_x, _module, _idx) \ 1714 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1715 1716 static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1717 const struct rtw89_wde_quota *min_cfg, 1718 const struct rtw89_wde_quota *max_cfg, 1719 u16 ext_wde_min_qt_wcpu) 1720 { 1721 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1722 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1723 u32 val; 1724 1725 SET_QUOTA(hif, WDE, 0); 1726 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1727 SET_QUOTA(pkt_in, WDE, 3); 1728 SET_QUOTA(cpu_io, WDE, 4); 1729 } 1730 1731 static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1732 const struct rtw89_ple_quota *min_cfg, 1733 const struct rtw89_ple_quota *max_cfg) 1734 { 1735 u32 val; 1736 1737 SET_QUOTA(cma0_tx, PLE, 0); 1738 SET_QUOTA(cma1_tx, PLE, 1); 1739 SET_QUOTA(c2h, PLE, 2); 1740 SET_QUOTA(h2c, PLE, 3); 1741 SET_QUOTA(wcpu, PLE, 4); 1742 SET_QUOTA(mpdu_proc, PLE, 5); 1743 SET_QUOTA(cma0_dma, PLE, 6); 1744 SET_QUOTA(cma1_dma, PLE, 7); 1745 SET_QUOTA(bb_rpt, PLE, 8); 1746 SET_QUOTA(wd_rel, PLE, 9); 1747 SET_QUOTA(cpu_io, PLE, 10); 1748 if (rtwdev->chip->chip_id == RTL8852C) 1749 SET_QUOTA(tx_rpt, PLE, 11); 1750 } 1751 1752 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 1753 { 1754 const struct rtw89_ple_quota *min_cfg, *max_cfg; 1755 const struct rtw89_dle_mem *cfg; 1756 u32 val; 1757 1758 if (rtwdev->chip->chip_id == RTL8852C) 1759 return 0; 1760 1761 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 1762 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 1763 return -EINVAL; 1764 } 1765 1766 if (wow) 1767 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 1768 else 1769 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 1770 if (!cfg) { 1771 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1772 return -EINVAL; 1773 } 1774 1775 min_cfg = cfg->ple_min_qt; 1776 max_cfg = cfg->ple_max_qt; 1777 SET_QUOTA(cma0_dma, PLE, 6); 1778 SET_QUOTA(cma1_dma, PLE, 7); 1779 1780 return 0; 1781 } 1782 #undef SET_QUOTA 1783 1784 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 1785 { 1786 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 1787 1788 if (enable) 1789 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1790 else 1791 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1792 } 1793 1794 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1795 const struct rtw89_dle_mem *cfg, 1796 u16 ext_wde_min_qt_wcpu) 1797 { 1798 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1799 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1800 } 1801 1802 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1803 enum rtw89_qta_mode ext_mode) 1804 { 1805 const struct rtw89_dle_mem *cfg, *ext_cfg; 1806 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1807 int ret = 0; 1808 u32 ini; 1809 1810 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1811 if (ret) 1812 return ret; 1813 1814 cfg = get_dle_mem_cfg(rtwdev, mode); 1815 if (!cfg) { 1816 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1817 ret = -EINVAL; 1818 goto error; 1819 } 1820 1821 if (mode == RTW89_QTA_DLFW) { 1822 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1823 if (!ext_cfg) { 1824 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1825 ext_mode); 1826 ret = -EINVAL; 1827 goto error; 1828 } 1829 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1830 } 1831 1832 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 1833 dle_expected_used_size(rtwdev, mode)) { 1834 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1835 ret = -EINVAL; 1836 goto error; 1837 } 1838 1839 dle_func_en(rtwdev, false); 1840 dle_clk_en(rtwdev, true); 1841 1842 ret = dle_mix_cfg(rtwdev, cfg); 1843 if (ret) { 1844 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1845 goto error; 1846 } 1847 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1848 1849 dle_func_en(rtwdev, true); 1850 1851 ret = read_poll_timeout(rtw89_read32, ini, 1852 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1853 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1854 if (ret) { 1855 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1856 return ret; 1857 } 1858 1859 ret = read_poll_timeout(rtw89_read32, ini, 1860 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1861 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1862 if (ret) { 1863 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1864 return ret; 1865 } 1866 1867 return 0; 1868 error: 1869 dle_func_en(rtwdev, false); 1870 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1871 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1872 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1873 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1874 1875 return ret; 1876 } 1877 1878 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1879 enum rtw89_qta_mode mode) 1880 { 1881 u32 reg, max_preld_size, min_rsvd_size; 1882 1883 max_preld_size = (mac_idx == RTW89_MAC_0 ? 1884 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1885 reg = mac_idx == RTW89_MAC_0 ? 1886 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1887 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1888 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1889 1890 min_rsvd_size = PRELD_AMSDU_SIZE; 1891 reg = mac_idx == RTW89_MAC_0 ? 1892 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1893 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1894 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1895 1896 return 0; 1897 } 1898 1899 static bool is_qta_poh(struct rtw89_dev *rtwdev) 1900 { 1901 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1902 } 1903 1904 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1905 enum rtw89_qta_mode mode) 1906 { 1907 const struct rtw89_chip_info *chip = rtwdev->chip; 1908 1909 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1910 chip->chip_id == RTL8851B || !is_qta_poh(rtwdev)) 1911 return 0; 1912 1913 return preload_init_set(rtwdev, mac_idx, mode); 1914 } 1915 1916 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1917 { 1918 u32 msk32; 1919 u32 val32; 1920 1921 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1922 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1923 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1924 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1925 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1926 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1927 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1928 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1929 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1930 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1931 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1932 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1933 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1934 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1935 1936 if ((val32 & msk32) == msk32) 1937 return true; 1938 1939 return false; 1940 } 1941 1942 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 1943 { 1944 const struct rtw89_chip_info *chip = rtwdev->chip; 1945 1946 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1947 chip->chip_id == RTL8851B) 1948 return; 1949 1950 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 1951 SS2F_PATH_WLCPU); 1952 } 1953 1954 static int sta_sch_init(struct rtw89_dev *rtwdev) 1955 { 1956 u32 p_val; 1957 u8 val; 1958 int ret; 1959 1960 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1961 if (ret) 1962 return ret; 1963 1964 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1965 val |= B_AX_SS_EN; 1966 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1967 1968 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1969 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1970 if (ret) { 1971 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1972 return ret; 1973 } 1974 1975 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 1976 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 1977 1978 _patch_ss2f_path(rtwdev); 1979 1980 return 0; 1981 } 1982 1983 static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1984 { 1985 int ret; 1986 1987 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1988 if (ret) 1989 return ret; 1990 1991 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1992 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1993 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1994 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1995 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1996 1997 return 0; 1998 } 1999 2000 static int sec_eng_init(struct rtw89_dev *rtwdev) 2001 { 2002 const struct rtw89_chip_info *chip = rtwdev->chip; 2003 u32 val = 0; 2004 int ret; 2005 2006 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2007 if (ret) 2008 return ret; 2009 2010 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2011 /* init clock */ 2012 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2013 /* init TX encryption */ 2014 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2015 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2016 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2017 chip->chip_id == RTL8851B) 2018 val &= ~B_AX_TX_PARTIAL_MODE; 2019 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2020 2021 /* init MIC ICV append */ 2022 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2023 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2024 2025 /* option init */ 2026 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2027 2028 if (chip->chip_id == RTL8852C) 2029 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2030 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2031 2032 return 0; 2033 } 2034 2035 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2036 { 2037 int ret; 2038 2039 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2040 if (ret) { 2041 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2042 return ret; 2043 } 2044 2045 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2046 if (ret) { 2047 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2048 return ret; 2049 } 2050 2051 ret = hfc_init(rtwdev, true, true, true); 2052 if (ret) { 2053 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2054 return ret; 2055 } 2056 2057 ret = sta_sch_init(rtwdev); 2058 if (ret) { 2059 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2060 return ret; 2061 } 2062 2063 ret = mpdu_proc_init(rtwdev); 2064 if (ret) { 2065 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2066 return ret; 2067 } 2068 2069 ret = sec_eng_init(rtwdev); 2070 if (ret) { 2071 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2072 return ret; 2073 } 2074 2075 return ret; 2076 } 2077 2078 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2079 { 2080 u32 val, reg; 2081 u16 p_val; 2082 int ret; 2083 2084 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2085 if (ret) 2086 return ret; 2087 2088 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2089 2090 val = rtw89_read32(rtwdev, reg); 2091 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2092 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2093 rtw89_write32(rtwdev, reg, val); 2094 2095 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2096 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2097 if (ret) { 2098 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2099 return ret; 2100 } 2101 2102 return 0; 2103 } 2104 2105 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2106 { 2107 u32 ret; 2108 u32 reg; 2109 u32 val; 2110 2111 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2112 if (ret) 2113 return ret; 2114 2115 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2116 if (rtwdev->chip->chip_id == RTL8852C) 2117 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2118 SIFS_MACTXEN_T1_V1); 2119 else 2120 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2121 SIFS_MACTXEN_T1); 2122 2123 if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) { 2124 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2125 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2126 } 2127 2128 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2129 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2130 2131 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2132 if (rtwdev->chip->chip_id == RTL8852C) { 2133 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2134 B_AX_TX_PARTIAL_MODE); 2135 if (!val) 2136 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2137 SCH_PREBKF_24US); 2138 } else { 2139 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2140 SCH_PREBKF_24US); 2141 } 2142 2143 return 0; 2144 } 2145 2146 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 2147 enum rtw89_machdr_frame_type type, 2148 enum rtw89_mac_fwd_target fwd_target, 2149 u8 mac_idx) 2150 { 2151 u32 reg; 2152 u32 val; 2153 2154 switch (fwd_target) { 2155 case RTW89_FWD_DONT_CARE: 2156 val = RX_FLTR_FRAME_DROP; 2157 break; 2158 case RTW89_FWD_TO_HOST: 2159 val = RX_FLTR_FRAME_TO_HOST; 2160 break; 2161 case RTW89_FWD_TO_WLAN_CPU: 2162 val = RX_FLTR_FRAME_TO_WLCPU; 2163 break; 2164 default: 2165 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2166 return -EINVAL; 2167 } 2168 2169 switch (type) { 2170 case RTW89_MGNT: 2171 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2172 break; 2173 case RTW89_CTRL: 2174 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2175 break; 2176 case RTW89_DATA: 2177 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2178 break; 2179 default: 2180 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2181 return -EINVAL; 2182 } 2183 rtw89_write32(rtwdev, reg, val); 2184 2185 return 0; 2186 } 2187 2188 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2189 { 2190 int ret, i; 2191 u32 mac_ftlr, plcp_ftlr; 2192 2193 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2194 if (ret) 2195 return ret; 2196 2197 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2198 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 2199 mac_idx); 2200 if (ret) 2201 return ret; 2202 } 2203 mac_ftlr = rtwdev->hal.rx_fltr; 2204 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2205 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2206 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2207 B_AX_HE_SIGB_CRC_CHK; 2208 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2209 mac_ftlr); 2210 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2211 plcp_ftlr); 2212 2213 return 0; 2214 } 2215 2216 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2217 { 2218 u32 reg, val32; 2219 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2220 2221 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2222 B_AX_RSP_CHK_BASIC_NAV; 2223 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2224 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2225 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2226 2227 switch (rtwdev->chip->chip_id) { 2228 case RTL8852A: 2229 case RTL8852B: 2230 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2231 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2232 rtw89_write32(rtwdev, reg, val32); 2233 2234 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2235 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2236 rtw89_write32(rtwdev, reg, val32); 2237 break; 2238 default: 2239 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2240 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2241 rtw89_write32(rtwdev, reg, val32); 2242 2243 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2244 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2245 rtw89_write32(rtwdev, reg, val32); 2246 break; 2247 } 2248 } 2249 2250 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2251 { 2252 u32 val, reg; 2253 int ret; 2254 2255 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2256 if (ret) 2257 return ret; 2258 2259 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2260 val = rtw89_read32(rtwdev, reg); 2261 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2262 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2263 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2264 B_AX_CTN_CHK_INTRA_NAV | 2265 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2266 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2267 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2268 B_AX_CTN_CHK_CCA_P20); 2269 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2270 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2271 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2272 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2273 B_AX_SIFS_CHK_EDCCA); 2274 2275 rtw89_write32(rtwdev, reg, val); 2276 2277 _patch_dis_resp_chk(rtwdev, mac_idx); 2278 2279 return 0; 2280 } 2281 2282 static int nav_ctrl_init(struct rtw89_dev *rtwdev) 2283 { 2284 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2285 B_AX_WMAC_TF_UP_NAV_EN | 2286 B_AX_WMAC_NAV_UPPER_EN); 2287 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2288 2289 return 0; 2290 } 2291 2292 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2293 { 2294 u32 reg; 2295 int ret; 2296 2297 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2298 if (ret) 2299 return ret; 2300 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2301 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2302 2303 return 0; 2304 } 2305 2306 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2307 { 2308 u32 reg; 2309 int ret; 2310 2311 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2312 if (ret) 2313 return ret; 2314 2315 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2316 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2317 2318 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2319 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2320 2321 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2322 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2323 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2324 2325 return 0; 2326 } 2327 2328 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2329 { 2330 const struct rtw89_chip_info *chip = rtwdev->chip; 2331 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2332 u32 reg, val, sifs; 2333 int ret; 2334 2335 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2336 if (ret) 2337 return ret; 2338 2339 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2340 val = rtw89_read32(rtwdev, reg); 2341 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2342 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2343 2344 switch (rtwdev->chip->chip_id) { 2345 case RTL8852A: 2346 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2347 break; 2348 case RTL8852B: 2349 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2350 break; 2351 default: 2352 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2353 break; 2354 } 2355 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2356 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2357 rtw89_write32(rtwdev, reg, val); 2358 2359 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2360 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2361 2362 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2363 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2364 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2365 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2366 2367 return 0; 2368 } 2369 2370 static void rst_bacam(struct rtw89_dev *rtwdev) 2371 { 2372 u32 val32; 2373 int ret; 2374 2375 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2376 S_AX_BACAM_RST_ALL); 2377 2378 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2379 1, 1000, false, 2380 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2381 if (ret) 2382 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2383 } 2384 2385 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2386 { 2387 #define TRXCFG_RMAC_CCA_TO 32 2388 #define TRXCFG_RMAC_DATA_TO 15 2389 #define RX_MAX_LEN_UNIT 512 2390 #define PLD_RLS_MAX_PG 127 2391 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2392 int ret; 2393 u32 reg, rx_max_len, rx_qta; 2394 u16 val; 2395 2396 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2397 if (ret) 2398 return ret; 2399 2400 if (mac_idx == RTW89_MAC_0) 2401 rst_bacam(rtwdev); 2402 2403 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2404 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2405 2406 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2407 val = rtw89_read16(rtwdev, reg); 2408 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2409 B_AX_RX_DLK_DATA_TIME_MASK); 2410 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2411 B_AX_RX_DLK_CCA_TIME_MASK); 2412 rtw89_write16(rtwdev, reg, val); 2413 2414 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2415 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2416 2417 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2418 if (mac_idx == RTW89_MAC_0) 2419 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2420 else 2421 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2422 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2423 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2424 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2425 rx_max_len /= RX_MAX_LEN_UNIT; 2426 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2427 2428 if (rtwdev->chip->chip_id == RTL8852A && 2429 rtwdev->hal.cv == CHIP_CBV) { 2430 rtw89_write16_mask(rtwdev, 2431 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2432 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2433 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2434 BIT(12)); 2435 } 2436 2437 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2438 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2439 2440 return ret; 2441 } 2442 2443 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2444 { 2445 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2446 u32 val, reg; 2447 int ret; 2448 2449 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2450 if (ret) 2451 return ret; 2452 2453 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2454 val = rtw89_read32(rtwdev, reg); 2455 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2456 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2457 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2458 rtw89_write32(rtwdev, reg, val); 2459 2460 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2461 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2462 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2463 } 2464 2465 return 0; 2466 } 2467 2468 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2469 { 2470 const struct rtw89_dle_mem *cfg; 2471 2472 cfg = get_dle_mem_cfg(rtwdev, mode); 2473 if (!cfg) { 2474 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2475 return false; 2476 } 2477 2478 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2479 } 2480 2481 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2482 { 2483 u32 val, reg; 2484 int ret; 2485 2486 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2487 if (ret) 2488 return ret; 2489 2490 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2491 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2492 val = rtw89_read32(rtwdev, reg); 2493 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2494 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2495 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2496 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2497 val |= B_AX_HW_CTS2SELF_EN; 2498 rtw89_write32(rtwdev, reg, val); 2499 2500 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2501 val = rtw89_read32(rtwdev, reg); 2502 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2503 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2504 rtw89_write32(rtwdev, reg, val); 2505 } 2506 2507 if (mac_idx == RTW89_MAC_0) { 2508 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2509 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2510 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2511 B_AX_PTCL_TRIGGER_SS_EN_0 | 2512 B_AX_PTCL_TRIGGER_SS_EN_1 | 2513 B_AX_PTCL_TRIGGER_SS_EN_UL); 2514 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2515 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2516 } else if (mac_idx == RTW89_MAC_1) { 2517 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2518 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2519 } 2520 2521 return 0; 2522 } 2523 2524 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2525 { 2526 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2527 u32 reg; 2528 int ret; 2529 2530 if (chip_id != RTL8852B) 2531 return 0; 2532 2533 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2534 if (ret) 2535 return ret; 2536 2537 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2538 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2539 2540 return 0; 2541 } 2542 2543 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2544 { 2545 int ret; 2546 2547 ret = scheduler_init(rtwdev, mac_idx); 2548 if (ret) { 2549 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2550 return ret; 2551 } 2552 2553 ret = addr_cam_init(rtwdev, mac_idx); 2554 if (ret) { 2555 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2556 ret); 2557 return ret; 2558 } 2559 2560 ret = rx_fltr_init(rtwdev, mac_idx); 2561 if (ret) { 2562 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2563 ret); 2564 return ret; 2565 } 2566 2567 ret = cca_ctrl_init(rtwdev, mac_idx); 2568 if (ret) { 2569 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2570 ret); 2571 return ret; 2572 } 2573 2574 ret = nav_ctrl_init(rtwdev); 2575 if (ret) { 2576 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2577 ret); 2578 return ret; 2579 } 2580 2581 ret = spatial_reuse_init(rtwdev, mac_idx); 2582 if (ret) { 2583 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2584 mac_idx, ret); 2585 return ret; 2586 } 2587 2588 ret = tmac_init(rtwdev, mac_idx); 2589 if (ret) { 2590 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2591 return ret; 2592 } 2593 2594 ret = trxptcl_init(rtwdev, mac_idx); 2595 if (ret) { 2596 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2597 return ret; 2598 } 2599 2600 ret = rmac_init(rtwdev, mac_idx); 2601 if (ret) { 2602 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2603 return ret; 2604 } 2605 2606 ret = cmac_com_init(rtwdev, mac_idx); 2607 if (ret) { 2608 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2609 return ret; 2610 } 2611 2612 ret = ptcl_init(rtwdev, mac_idx); 2613 if (ret) { 2614 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2615 return ret; 2616 } 2617 2618 ret = cmac_dma_init(rtwdev, mac_idx); 2619 if (ret) { 2620 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2621 return ret; 2622 } 2623 2624 return ret; 2625 } 2626 2627 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2628 struct rtw89_mac_c2h_info *c2h_info) 2629 { 2630 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2631 struct rtw89_mac_h2c_info h2c_info = {0}; 2632 u32 ret; 2633 2634 mac->cnv_efuse_state(rtwdev, false); 2635 2636 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2637 h2c_info.content_len = 0; 2638 2639 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2640 if (ret) 2641 goto out; 2642 2643 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2644 ret = -EINVAL; 2645 2646 out: 2647 mac->cnv_efuse_state(rtwdev, true); 2648 2649 return ret; 2650 } 2651 2652 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2653 { 2654 struct rtw89_efuse *efuse = &rtwdev->efuse; 2655 struct rtw89_hal *hal = &rtwdev->hal; 2656 const struct rtw89_chip_info *chip = rtwdev->chip; 2657 struct rtw89_mac_c2h_info c2h_info = {0}; 2658 const struct rtw89_c2hreg_phycap *phycap; 2659 u8 tx_nss; 2660 u8 rx_nss; 2661 u8 tx_ant; 2662 u8 rx_ant; 2663 u32 ret; 2664 2665 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2666 if (ret) 2667 return ret; 2668 2669 phycap = &c2h_info.u.phycap; 2670 2671 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 2672 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 2673 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 2674 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2675 2676 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2677 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2678 2679 if (tx_ant == 1) 2680 hal->antenna_tx = RF_B; 2681 if (rx_ant == 1) 2682 hal->antenna_rx = RF_B; 2683 2684 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2685 hal->antenna_tx = RF_B; 2686 hal->tx_path_diversity = true; 2687 } 2688 2689 if (chip->rf_path_num == 1) { 2690 hal->antenna_tx = RF_A; 2691 hal->antenna_rx = RF_A; 2692 if ((efuse->rfe_type % 3) == 2) 2693 hal->ant_diversity = true; 2694 } 2695 2696 rtw89_debug(rtwdev, RTW89_DBG_FW, 2697 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2698 hal->tx_nss, tx_nss, chip->tx_nss, 2699 hal->rx_nss, rx_nss, chip->rx_nss); 2700 rtw89_debug(rtwdev, RTW89_DBG_FW, 2701 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2702 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2703 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2704 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2705 2706 return 0; 2707 } 2708 2709 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2710 u16 tx_en_u16, u16 mask_u16) 2711 { 2712 u32 ret; 2713 struct rtw89_mac_c2h_info c2h_info = {0}; 2714 struct rtw89_mac_h2c_info h2c_info = {0}; 2715 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 2716 2717 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2718 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 2719 2720 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 2721 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 2722 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 2723 2724 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2725 if (ret) 2726 return ret; 2727 2728 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2729 return -EINVAL; 2730 2731 return 0; 2732 } 2733 2734 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2735 u16 tx_en, u16 tx_en_mask) 2736 { 2737 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 2738 u16 val; 2739 int ret; 2740 2741 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2742 if (ret) 2743 return ret; 2744 2745 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2746 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2747 tx_en, tx_en_mask); 2748 2749 val = rtw89_read16(rtwdev, reg); 2750 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2751 rtw89_write16(rtwdev, reg, val); 2752 2753 return 0; 2754 } 2755 2756 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2757 u32 tx_en, u32 tx_en_mask) 2758 { 2759 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 2760 u32 val; 2761 int ret; 2762 2763 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2764 if (ret) 2765 return ret; 2766 2767 val = rtw89_read32(rtwdev, reg); 2768 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2769 rtw89_write32(rtwdev, reg, val); 2770 2771 return 0; 2772 } 2773 2774 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2775 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2776 { 2777 int ret; 2778 2779 *tx_en = rtw89_read16(rtwdev, 2780 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 2781 2782 switch (sel) { 2783 case RTW89_SCH_TX_SEL_ALL: 2784 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2785 B_AX_CTN_TXEN_ALL_MASK); 2786 if (ret) 2787 return ret; 2788 break; 2789 case RTW89_SCH_TX_SEL_HIQ: 2790 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2791 0, B_AX_CTN_TXEN_HGQ); 2792 if (ret) 2793 return ret; 2794 break; 2795 case RTW89_SCH_TX_SEL_MG0: 2796 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2797 0, B_AX_CTN_TXEN_MGQ); 2798 if (ret) 2799 return ret; 2800 break; 2801 case RTW89_SCH_TX_SEL_MACID: 2802 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2803 B_AX_CTN_TXEN_ALL_MASK); 2804 if (ret) 2805 return ret; 2806 break; 2807 default: 2808 return 0; 2809 } 2810 2811 return 0; 2812 } 2813 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2814 2815 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2816 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2817 { 2818 int ret; 2819 2820 *tx_en = rtw89_read32(rtwdev, 2821 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 2822 2823 switch (sel) { 2824 case RTW89_SCH_TX_SEL_ALL: 2825 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2826 B_AX_CTN_TXEN_ALL_MASK_V1); 2827 if (ret) 2828 return ret; 2829 break; 2830 case RTW89_SCH_TX_SEL_HIQ: 2831 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2832 0, B_AX_CTN_TXEN_HGQ); 2833 if (ret) 2834 return ret; 2835 break; 2836 case RTW89_SCH_TX_SEL_MG0: 2837 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2838 0, B_AX_CTN_TXEN_MGQ); 2839 if (ret) 2840 return ret; 2841 break; 2842 case RTW89_SCH_TX_SEL_MACID: 2843 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2844 B_AX_CTN_TXEN_ALL_MASK_V1); 2845 if (ret) 2846 return ret; 2847 break; 2848 default: 2849 return 0; 2850 } 2851 2852 return 0; 2853 } 2854 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2855 2856 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2857 { 2858 int ret; 2859 2860 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2861 if (ret) 2862 return ret; 2863 2864 return 0; 2865 } 2866 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2867 2868 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2869 { 2870 int ret; 2871 2872 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2873 B_AX_CTN_TXEN_ALL_MASK_V1); 2874 if (ret) 2875 return ret; 2876 2877 return 0; 2878 } 2879 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2880 2881 int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 2882 { 2883 u32 val, reg; 2884 int ret; 2885 2886 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2887 val = buf_len; 2888 val |= B_AX_WD_BUF_REQ_EXEC; 2889 rtw89_write32(rtwdev, reg, val); 2890 2891 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2892 2893 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2894 1, 2000, false, rtwdev, reg); 2895 if (ret) 2896 return ret; 2897 2898 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2899 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 2900 return -ENOENT; 2901 2902 return 0; 2903 } 2904 2905 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2906 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 2907 { 2908 u32 val, cmd_type, reg; 2909 int ret; 2910 2911 cmd_type = ctrl_para->cmd_type; 2912 2913 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2914 val = 0; 2915 val = u32_replace_bits(val, ctrl_para->start_pktid, 2916 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2917 val = u32_replace_bits(val, ctrl_para->end_pktid, 2918 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2919 rtw89_write32(rtwdev, reg, val); 2920 2921 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2922 val = 0; 2923 val = u32_replace_bits(val, ctrl_para->src_pid, 2924 B_AX_CPUQ_OP_SRC_PID_MASK); 2925 val = u32_replace_bits(val, ctrl_para->src_qid, 2926 B_AX_CPUQ_OP_SRC_QID_MASK); 2927 val = u32_replace_bits(val, ctrl_para->dst_pid, 2928 B_AX_CPUQ_OP_DST_PID_MASK); 2929 val = u32_replace_bits(val, ctrl_para->dst_qid, 2930 B_AX_CPUQ_OP_DST_QID_MASK); 2931 rtw89_write32(rtwdev, reg, val); 2932 2933 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2934 val = 0; 2935 val = u32_replace_bits(val, cmd_type, 2936 B_AX_CPUQ_OP_CMD_TYPE_MASK); 2937 val = u32_replace_bits(val, ctrl_para->macid, 2938 B_AX_CPUQ_OP_MACID_MASK); 2939 val = u32_replace_bits(val, ctrl_para->pkt_num, 2940 B_AX_CPUQ_OP_PKTNUM_MASK); 2941 val |= B_AX_WD_CPUQ_OP_EXEC; 2942 rtw89_write32(rtwdev, reg, val); 2943 2944 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2945 2946 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2947 1, 2000, false, rtwdev, reg); 2948 if (ret) 2949 return ret; 2950 2951 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2952 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2953 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2954 2955 return 0; 2956 } 2957 2958 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2959 { 2960 const struct rtw89_dle_mem *cfg; 2961 struct rtw89_cpuio_ctrl ctrl_para = {0}; 2962 u16 pkt_id; 2963 int ret; 2964 2965 cfg = get_dle_mem_cfg(rtwdev, mode); 2966 if (!cfg) { 2967 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2968 return -EINVAL; 2969 } 2970 2971 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 2972 dle_expected_used_size(rtwdev, mode)) { 2973 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2974 return -EINVAL; 2975 } 2976 2977 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2978 2979 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id); 2980 if (ret) { 2981 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2982 return ret; 2983 } 2984 2985 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2986 ctrl_para.start_pktid = pkt_id; 2987 ctrl_para.end_pktid = pkt_id; 2988 ctrl_para.pkt_num = 0; 2989 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2990 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2991 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2992 if (ret) { 2993 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2994 return -EFAULT; 2995 } 2996 2997 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, false, &pkt_id); 2998 if (ret) { 2999 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3000 return ret; 3001 } 3002 3003 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3004 ctrl_para.start_pktid = pkt_id; 3005 ctrl_para.end_pktid = pkt_id; 3006 ctrl_para.pkt_num = 0; 3007 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3008 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3009 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 3010 if (ret) { 3011 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3012 return -EFAULT; 3013 } 3014 3015 return 0; 3016 } 3017 3018 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3019 { 3020 int ret; 3021 u32 reg; 3022 u8 val; 3023 3024 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3025 if (ret) 3026 return ret; 3027 3028 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3029 3030 ret = read_poll_timeout(rtw89_read8, val, 3031 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3032 SW_CVR_DUR_US, 3033 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3034 false, rtwdev, reg); 3035 if (ret) 3036 return ret; 3037 3038 return 0; 3039 } 3040 3041 static int band1_enable(struct rtw89_dev *rtwdev) 3042 { 3043 int ret, i; 3044 u32 sleep_bak[4] = {0}; 3045 u32 pause_bak[4] = {0}; 3046 u32 tx_en; 3047 3048 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3049 if (ret) { 3050 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3051 return ret; 3052 } 3053 3054 for (i = 0; i < 4; i++) { 3055 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3056 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3057 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3058 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3059 } 3060 3061 ret = band_idle_ck_b(rtwdev, 0); 3062 if (ret) { 3063 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3064 return ret; 3065 } 3066 3067 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 3068 if (ret) { 3069 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3070 return ret; 3071 } 3072 3073 for (i = 0; i < 4; i++) { 3074 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3075 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3076 } 3077 3078 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3079 if (ret) { 3080 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3081 return ret; 3082 } 3083 3084 ret = cmac_func_en(rtwdev, 1, true); 3085 if (ret) { 3086 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3087 return ret; 3088 } 3089 3090 ret = cmac_init(rtwdev, 1); 3091 if (ret) { 3092 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3093 return ret; 3094 } 3095 3096 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3097 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3098 3099 return 0; 3100 } 3101 3102 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3103 { 3104 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3105 3106 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3107 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3108 } 3109 3110 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3111 { 3112 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3113 3114 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3115 } 3116 3117 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3118 { 3119 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3120 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3121 3122 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3123 B_AX_TX_GET_ERRPKTID_INT_EN | 3124 B_AX_TX_NXT_ERRPKTID_INT_EN | 3125 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3126 B_AX_TX_OFFSET_ERR_INT_EN | 3127 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3128 if (chip_id == RTL8852C) 3129 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3130 B_AX_TX_ETH_TYPE_ERR_EN | 3131 B_AX_TX_LLC_PRE_ERR_EN | 3132 B_AX_TX_NW_TYPE_ERR_EN | 3133 B_AX_TX_KSRCH_ERR_EN); 3134 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3135 imr->mpdu_tx_imr_set); 3136 3137 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3138 B_AX_GETPKTID_ERR_INT_EN | 3139 B_AX_MHDRLEN_ERR_INT_EN | 3140 B_AX_RPT_ERR_INT_EN); 3141 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3142 imr->mpdu_rx_imr_set); 3143 } 3144 3145 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3146 { 3147 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3148 3149 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3150 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3151 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3152 B_AX_PLE_B_PKTID_ERR_INT_EN); 3153 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3154 imr->sta_sch_imr_set); 3155 } 3156 3157 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3158 { 3159 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3160 3161 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3162 imr->txpktctl_imr_b0_clr); 3163 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3164 imr->txpktctl_imr_b0_set); 3165 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3166 imr->txpktctl_imr_b1_clr); 3167 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3168 imr->txpktctl_imr_b1_set); 3169 } 3170 3171 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3172 { 3173 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3174 3175 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3176 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3177 } 3178 3179 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3180 { 3181 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3182 3183 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3184 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3185 } 3186 3187 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3188 { 3189 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3190 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3191 } 3192 3193 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3194 { 3195 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3196 3197 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3198 imr->host_disp_imr_clr); 3199 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3200 imr->host_disp_imr_set); 3201 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3202 imr->cpu_disp_imr_clr); 3203 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3204 imr->cpu_disp_imr_set); 3205 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3206 imr->other_disp_imr_clr); 3207 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3208 imr->other_disp_imr_set); 3209 } 3210 3211 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3212 { 3213 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3214 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3215 } 3216 3217 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3218 { 3219 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3220 3221 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3222 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3223 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3224 B_AX_BBRPT_CHINFO_IMR_CLR); 3225 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3226 imr->bbrpt_err_imr_set); 3227 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3228 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3229 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3230 } 3231 3232 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3233 { 3234 u32 reg; 3235 3236 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3237 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3238 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3239 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3240 } 3241 3242 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3243 { 3244 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3245 u32 reg; 3246 3247 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3248 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3249 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3250 } 3251 3252 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3253 { 3254 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3255 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3256 u32 reg; 3257 3258 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3259 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3260 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3261 3262 if (chip_id == RTL8852C) { 3263 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3264 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3265 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3266 } 3267 } 3268 3269 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3270 { 3271 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3272 u32 reg; 3273 3274 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3275 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3276 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3277 } 3278 3279 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3280 { 3281 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3282 u32 reg; 3283 3284 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3285 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3286 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3287 } 3288 3289 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3290 { 3291 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3292 u32 reg; 3293 3294 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3295 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3296 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3297 } 3298 3299 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 3300 enum rtw89_mac_hwmod_sel sel) 3301 { 3302 int ret; 3303 3304 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3305 if (ret) { 3306 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3307 sel, mac_idx); 3308 return ret; 3309 } 3310 3311 if (sel == RTW89_DMAC_SEL) { 3312 rtw89_wdrls_imr_enable(rtwdev); 3313 rtw89_wsec_imr_enable(rtwdev); 3314 rtw89_mpdu_trx_imr_enable(rtwdev); 3315 rtw89_sta_sch_imr_enable(rtwdev); 3316 rtw89_txpktctl_imr_enable(rtwdev); 3317 rtw89_wde_imr_enable(rtwdev); 3318 rtw89_ple_imr_enable(rtwdev); 3319 rtw89_pktin_imr_enable(rtwdev); 3320 rtw89_dispatcher_imr_enable(rtwdev); 3321 rtw89_cpuio_imr_enable(rtwdev); 3322 rtw89_bbrpt_imr_enable(rtwdev); 3323 } else if (sel == RTW89_CMAC_SEL) { 3324 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3325 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3326 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3327 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3328 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3329 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3330 } else { 3331 return -EINVAL; 3332 } 3333 3334 return 0; 3335 } 3336 3337 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) 3338 { 3339 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3340 3341 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3342 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3343 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3344 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3345 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 3346 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3347 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3348 } 3349 3350 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 3351 { 3352 int ret = 0; 3353 3354 if (enable) { 3355 ret = band1_enable(rtwdev); 3356 if (ret) { 3357 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3358 return ret; 3359 } 3360 3361 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3362 if (ret) { 3363 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3364 return ret; 3365 } 3366 } else { 3367 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3368 return -EINVAL; 3369 } 3370 3371 return 0; 3372 } 3373 3374 static int set_host_rpr(struct rtw89_dev *rtwdev) 3375 { 3376 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3377 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3378 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3379 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3380 B_AX_RLSRPT0_FLTR_MAP_MASK); 3381 } else { 3382 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3383 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3384 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3385 B_AX_RLSRPT0_FLTR_MAP_MASK); 3386 } 3387 3388 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3389 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3390 3391 return 0; 3392 } 3393 3394 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 3395 { 3396 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3397 int ret; 3398 3399 ret = dmac_init(rtwdev, 0); 3400 if (ret) { 3401 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3402 return ret; 3403 } 3404 3405 ret = cmac_init(rtwdev, 0); 3406 if (ret) { 3407 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3408 return ret; 3409 } 3410 3411 if (is_qta_dbcc(rtwdev, qta_mode)) { 3412 ret = rtw89_mac_dbcc_enable(rtwdev, true); 3413 if (ret) { 3414 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3415 return ret; 3416 } 3417 } 3418 3419 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3420 if (ret) { 3421 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3422 return ret; 3423 } 3424 3425 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3426 if (ret) { 3427 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3428 return ret; 3429 } 3430 3431 rtw89_mac_err_imr_ctrl(rtwdev, true); 3432 3433 ret = set_host_rpr(rtwdev); 3434 if (ret) { 3435 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3436 return ret; 3437 } 3438 3439 return 0; 3440 } 3441 3442 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3443 { 3444 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3445 u32 val32; 3446 3447 if (chip_id == RTL8852B || chip_id == RTL8851B) { 3448 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3449 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3450 return; 3451 } 3452 3453 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3454 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3455 3456 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3457 val32 |= B_AX_FS_WDT_INT; 3458 val32 &= ~B_AX_FS_WDT_INT_MSK; 3459 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3460 } 3461 3462 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3463 { 3464 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3465 3466 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3467 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3468 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3469 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3470 3471 rtw89_disable_fw_watchdog(rtwdev); 3472 3473 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3474 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3475 } 3476 3477 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3478 bool dlfw, bool include_bb) 3479 { 3480 u32 val; 3481 int ret; 3482 3483 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3484 return -EFAULT; 3485 3486 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3487 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3488 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3489 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3490 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3491 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3492 3493 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3494 3495 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3496 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3497 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3498 B_AX_WCPU_FWDL_STS_MASK); 3499 3500 if (dlfw) 3501 val |= B_AX_WCPU_FWDL_EN; 3502 3503 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3504 3505 if (rtwdev->chip->chip_id == RTL8852B) 3506 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3507 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3508 3509 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3510 boot_reason); 3511 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3512 3513 if (!dlfw) { 3514 mdelay(5); 3515 3516 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3517 if (ret) 3518 return ret; 3519 } 3520 3521 return 0; 3522 } 3523 3524 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3525 { 3526 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3527 u32 val; 3528 int ret; 3529 3530 if (chip_id == RTL8852C) 3531 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3532 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3533 else 3534 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3535 B_AX_PKT_BUF_EN; 3536 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3537 3538 if (chip_id == RTL8851B) 3539 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3540 else 3541 val = B_AX_DISPATCHER_CLK_EN; 3542 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3543 3544 if (chip_id != RTL8852C) 3545 goto dle; 3546 3547 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3548 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3549 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3550 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3551 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3552 3553 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3554 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3555 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3556 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3557 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3558 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3559 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3560 3561 dle: 3562 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3563 if (ret) { 3564 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3565 return ret; 3566 } 3567 3568 ret = hfc_init(rtwdev, true, false, true); 3569 if (ret) { 3570 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3571 return ret; 3572 } 3573 3574 return ret; 3575 } 3576 3577 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3578 { 3579 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3580 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3581 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3582 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3583 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3584 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3585 3586 return 0; 3587 } 3588 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3589 3590 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3591 { 3592 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3593 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3594 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3595 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3596 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3597 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3598 3599 return 0; 3600 } 3601 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3602 3603 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 3604 { 3605 int ret; 3606 3607 ret = rtw89_mac_power_switch(rtwdev, true); 3608 if (ret) { 3609 rtw89_mac_power_switch(rtwdev, false); 3610 ret = rtw89_mac_power_switch(rtwdev, true); 3611 if (ret) 3612 return ret; 3613 } 3614 3615 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3616 3617 if (include_bb) { 3618 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 3619 if (rtwdev->dbcc_en) 3620 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 3621 } 3622 3623 ret = rtw89_mac_dmac_pre_init(rtwdev); 3624 if (ret) 3625 return ret; 3626 3627 if (rtwdev->hci.ops->mac_pre_init) { 3628 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3629 if (ret) 3630 return ret; 3631 } 3632 3633 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 3634 if (ret) 3635 return ret; 3636 3637 return 0; 3638 } 3639 3640 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3641 { 3642 const struct rtw89_chip_info *chip = rtwdev->chip; 3643 bool include_bb = !!chip->bbmcu_nr; 3644 int ret; 3645 3646 ret = rtw89_mac_partial_init(rtwdev, include_bb); 3647 if (ret) 3648 goto fail; 3649 3650 ret = rtw89_chip_enable_bb_rf(rtwdev); 3651 if (ret) 3652 goto fail; 3653 3654 ret = rtw89_mac_sys_init(rtwdev); 3655 if (ret) 3656 goto fail; 3657 3658 ret = rtw89_mac_trx_init(rtwdev); 3659 if (ret) 3660 goto fail; 3661 3662 if (rtwdev->hci.ops->mac_post_init) { 3663 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3664 if (ret) 3665 goto fail; 3666 } 3667 3668 rtw89_fw_send_all_early_h2c(rtwdev); 3669 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3670 3671 return ret; 3672 fail: 3673 rtw89_mac_power_switch(rtwdev, false); 3674 3675 return ret; 3676 } 3677 3678 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3679 { 3680 u8 i; 3681 3682 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 3683 return; 3684 3685 for (i = 0; i < 4; i++) { 3686 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3687 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3688 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3689 } 3690 } 3691 3692 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3693 { 3694 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 3695 return; 3696 3697 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3698 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3699 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3700 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3701 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3702 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3703 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3704 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3705 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3706 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3707 } 3708 3709 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3710 { 3711 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3712 u8 grp = macid >> 5; 3713 int ret; 3714 3715 /* If this is called by change_interface() in the case of P2P, it could 3716 * be power-off, so ignore this operation. 3717 */ 3718 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 3719 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3720 return 0; 3721 3722 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3723 if (ret) 3724 return ret; 3725 3726 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3727 3728 return 0; 3729 } 3730 3731 static const struct rtw89_port_reg rtw89_port_base_ax = { 3732 .port_cfg = R_AX_PORT_CFG_P0, 3733 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3734 .bcn_area = R_AX_BCN_AREA_P0, 3735 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3736 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3737 .tbtt_agg = R_AX_TBTT_AGG_P0, 3738 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3739 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3740 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3741 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3742 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3743 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3744 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3745 .tsftr_l = R_AX_TSFTR_LOW_P0, 3746 .tsftr_h = R_AX_TSFTR_HIGH_P0, 3747 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 3748 .bss_color = R_AX_PTCL_BSS_COLOR_0, 3749 .mbssid = R_AX_MBSSID_CTRL, 3750 .mbssid_drop = R_AX_MBSSID_DROP_0, 3751 .tsf_sync = R_AX_PORT0_TSF_SYNC, 3752 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3753 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3754 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 3755 }; 3756 3757 #define BCN_INTERVAL 100 3758 #define BCN_ERLY_DEF 160 3759 #define BCN_SETUP_DEF 2 3760 #define BCN_HOLD_DEF 200 3761 #define BCN_MASK_DEF 0 3762 #define TBTT_ERLY_DEF 5 3763 #define BCN_SET_UNIT 32 3764 #define BCN_ERLY_SET_DLY (10 * 2) 3765 3766 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3767 struct rtw89_vif *rtwvif) 3768 { 3769 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3770 const struct rtw89_port_reg *p = mac->port_base; 3771 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3772 3773 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3774 return; 3775 3776 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3777 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3778 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3779 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3780 3781 msleep(vif->bss_conf.beacon_int + 1); 3782 3783 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3784 B_AX_BRK_SETUP); 3785 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3786 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3787 } 3788 3789 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3790 struct rtw89_vif *rtwvif, bool en) 3791 { 3792 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3793 const struct rtw89_port_reg *p = mac->port_base; 3794 3795 if (en) 3796 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3797 else 3798 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3799 } 3800 3801 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3802 struct rtw89_vif *rtwvif, bool en) 3803 { 3804 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3805 const struct rtw89_port_reg *p = mac->port_base; 3806 3807 if (en) 3808 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3809 else 3810 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3811 } 3812 3813 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3814 struct rtw89_vif *rtwvif) 3815 { 3816 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3817 const struct rtw89_port_reg *p = mac->port_base; 3818 3819 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3820 rtwvif->net_type); 3821 } 3822 3823 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3824 struct rtw89_vif *rtwvif) 3825 { 3826 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3827 const struct rtw89_port_reg *p = mac->port_base; 3828 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3829 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3830 3831 if (en) 3832 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3833 else 3834 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3835 } 3836 3837 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3838 struct rtw89_vif *rtwvif) 3839 { 3840 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3841 const struct rtw89_port_reg *p = mac->port_base; 3842 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3843 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3844 u32 bit = B_AX_RX_BSSID_FIT_EN; 3845 3846 if (en) 3847 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3848 else 3849 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3850 } 3851 3852 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3853 struct rtw89_vif *rtwvif) 3854 { 3855 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3856 const struct rtw89_port_reg *p = mac->port_base; 3857 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3858 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3859 3860 if (en) 3861 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3862 else 3863 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3864 } 3865 3866 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3867 struct rtw89_vif *rtwvif) 3868 { 3869 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3870 const struct rtw89_port_reg *p = mac->port_base; 3871 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3872 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3873 3874 if (en) 3875 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3876 else 3877 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3878 } 3879 3880 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3881 struct rtw89_vif *rtwvif) 3882 { 3883 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3884 const struct rtw89_port_reg *p = mac->port_base; 3885 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3886 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3887 3888 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3889 bcn_int); 3890 } 3891 3892 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3893 struct rtw89_vif *rtwvif) 3894 { 3895 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3896 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3897 const struct rtw89_port_reg *p = mac->port_base; 3898 u8 port = rtwvif->port; 3899 u32 reg; 3900 3901 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif->mac_idx); 3902 rtw89_write8(rtwdev, reg, win); 3903 } 3904 3905 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3906 struct rtw89_vif *rtwvif) 3907 { 3908 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3909 const struct rtw89_port_reg *p = mac->port_base; 3910 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3911 u32 addr; 3912 3913 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif->mac_idx); 3914 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3915 3916 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3917 vif->bss_conf.dtim_period); 3918 } 3919 3920 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3921 struct rtw89_vif *rtwvif) 3922 { 3923 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3924 const struct rtw89_port_reg *p = mac->port_base; 3925 3926 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3927 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3928 } 3929 3930 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3931 struct rtw89_vif *rtwvif) 3932 { 3933 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3934 const struct rtw89_port_reg *p = mac->port_base; 3935 3936 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3937 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3938 } 3939 3940 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3941 struct rtw89_vif *rtwvif) 3942 { 3943 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3944 const struct rtw89_port_reg *p = mac->port_base; 3945 3946 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3947 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3948 } 3949 3950 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3951 struct rtw89_vif *rtwvif) 3952 { 3953 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3954 const struct rtw89_port_reg *p = mac->port_base; 3955 3956 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3957 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3958 } 3959 3960 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3961 struct rtw89_vif *rtwvif) 3962 { 3963 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3964 const struct rtw89_port_reg *p = mac->port_base; 3965 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3966 static const u32 masks[RTW89_PORT_NUM] = { 3967 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3968 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3969 B_AX_BSS_COLOB_AX_PORT_4_MASK, 3970 }; 3971 u8 port = rtwvif->port; 3972 u32 reg_base; 3973 u32 reg; 3974 u8 bss_color; 3975 3976 bss_color = vif->bss_conf.he_bss_color.color; 3977 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 3978 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx); 3979 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3980 } 3981 3982 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3983 struct rtw89_vif *rtwvif) 3984 { 3985 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3986 const struct rtw89_port_reg *p = mac->port_base; 3987 u8 port = rtwvif->port; 3988 u32 reg; 3989 3990 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3991 return; 3992 3993 if (port == 0) { 3994 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif->mac_idx); 3995 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3996 } 3997 } 3998 3999 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4000 struct rtw89_vif *rtwvif) 4001 { 4002 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4003 const struct rtw89_port_reg *p = mac->port_base; 4004 u8 port = rtwvif->port; 4005 u32 reg; 4006 u32 val; 4007 4008 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif->mac_idx); 4009 val = rtw89_read32(rtwdev, reg); 4010 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4011 if (port == 0) 4012 val &= ~BIT(0); 4013 rtw89_write32(rtwdev, reg, val); 4014 } 4015 4016 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4017 struct rtw89_vif *rtwvif, bool enable) 4018 { 4019 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4020 const struct rtw89_port_reg *p = mac->port_base; 4021 4022 if (enable) 4023 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 4024 B_AX_PORT_FUNC_EN); 4025 else 4026 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 4027 B_AX_PORT_FUNC_EN); 4028 } 4029 4030 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4031 struct rtw89_vif *rtwvif) 4032 { 4033 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4034 const struct rtw89_port_reg *p = mac->port_base; 4035 4036 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 4037 BCN_ERLY_DEF); 4038 } 4039 4040 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4041 struct rtw89_vif *rtwvif) 4042 { 4043 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4044 const struct rtw89_port_reg *p = mac->port_base; 4045 u16 val; 4046 4047 if (rtwdev->chip->chip_id != RTL8852C) 4048 return; 4049 4050 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4051 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4052 return; 4053 4054 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4055 B_AX_TBTT_SHIFT_OFST_SIGN; 4056 4057 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 4058 B_AX_TBTT_SHIFT_OFST_MASK, val); 4059 } 4060 4061 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4062 struct rtw89_vif *rtwvif, 4063 struct rtw89_vif *rtwvif_src, 4064 u16 offset_tu) 4065 { 4066 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4067 const struct rtw89_port_reg *p = mac->port_base; 4068 u32 val, reg; 4069 4070 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4071 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif->port * 4, 4072 rtwvif->mac_idx); 4073 4074 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4075 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4076 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4077 } 4078 4079 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4080 struct rtw89_vif *rtwvif, 4081 struct rtw89_vif *rtwvif_src, 4082 u8 offset, int *n_offset) 4083 { 4084 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 4085 return; 4086 4087 /* adjust offset randomly to avoid beacon conflict */ 4088 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4089 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 4090 (*n_offset) * offset); 4091 4092 (*n_offset)++; 4093 } 4094 4095 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4096 { 4097 struct rtw89_vif *src = NULL, *tmp; 4098 u8 offset = 100, vif_aps = 0; 4099 int n_offset = 1; 4100 4101 rtw89_for_each_rtwvif(rtwdev, tmp) { 4102 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4103 src = tmp; 4104 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4105 vif_aps++; 4106 } 4107 4108 if (vif_aps == 0) 4109 return; 4110 4111 offset /= (vif_aps + 1); 4112 4113 rtw89_for_each_rtwvif(rtwdev, tmp) 4114 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4115 } 4116 4117 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4118 { 4119 int ret; 4120 4121 ret = rtw89_mac_port_update(rtwdev, rtwvif); 4122 if (ret) 4123 return ret; 4124 4125 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4126 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4127 4128 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4129 if (ret) 4130 return ret; 4131 4132 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4133 if (ret) 4134 return ret; 4135 4136 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4137 if (ret) 4138 return ret; 4139 4140 ret = rtw89_cam_init(rtwdev, rtwvif); 4141 if (ret) 4142 return ret; 4143 4144 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4145 if (ret) 4146 return ret; 4147 4148 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 4149 if (ret) 4150 return ret; 4151 4152 return 0; 4153 } 4154 4155 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4156 { 4157 int ret; 4158 4159 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4160 if (ret) 4161 return ret; 4162 4163 rtw89_cam_deinit(rtwdev, rtwvif); 4164 4165 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4166 if (ret) 4167 return ret; 4168 4169 return 0; 4170 } 4171 4172 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4173 { 4174 u8 port = rtwvif->port; 4175 4176 if (port >= RTW89_PORT_NUM) 4177 return -EINVAL; 4178 4179 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4180 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4181 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4182 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4183 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4184 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4185 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 4186 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 4187 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4188 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4189 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4190 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4191 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4192 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4193 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4194 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4195 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4196 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4197 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4198 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4199 rtw89_mac_port_tsf_resync_all(rtwdev); 4200 fsleep(BCN_ERLY_SET_DLY); 4201 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4202 4203 return 0; 4204 } 4205 4206 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4207 u64 *tsf) 4208 { 4209 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4210 const struct rtw89_port_reg *p = mac->port_base; 4211 u32 tsf_low, tsf_high; 4212 int ret; 4213 4214 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 4215 if (ret) 4216 return ret; 4217 4218 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 4219 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 4220 *tsf = (u64)tsf_high << 32 | tsf_low; 4221 4222 return 0; 4223 } 4224 4225 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4226 struct cfg80211_bss *bss, 4227 void *data) 4228 { 4229 const struct cfg80211_bss_ies *ies; 4230 const struct element *elem; 4231 bool *tolerated = data; 4232 4233 rcu_read_lock(); 4234 ies = rcu_dereference(bss->ies); 4235 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4236 ies->len); 4237 4238 if (!elem || elem->datalen < 10 || 4239 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4240 *tolerated = false; 4241 rcu_read_unlock(); 4242 } 4243 4244 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4245 struct ieee80211_vif *vif) 4246 { 4247 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4248 struct ieee80211_hw *hw = rtwdev->hw; 4249 bool tolerated = true; 4250 u32 reg; 4251 4252 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 4253 return; 4254 4255 if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR)) 4256 return; 4257 4258 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef, 4259 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4260 &tolerated); 4261 4262 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); 4263 if (tolerated) 4264 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4265 else 4266 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4267 } 4268 4269 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4270 { 4271 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false); 4272 } 4273 4274 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4275 { 4276 int ret; 4277 4278 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 4279 RTW89_MAX_MAC_ID_NUM); 4280 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4281 return -ENOSPC; 4282 4283 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4284 if (ret) 4285 goto release_mac_id; 4286 4287 return 0; 4288 4289 release_mac_id: 4290 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4291 4292 return ret; 4293 } 4294 4295 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4296 { 4297 int ret; 4298 4299 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4300 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4301 4302 return ret; 4303 } 4304 4305 static void 4306 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4307 { 4308 } 4309 4310 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4311 { 4312 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4313 4314 return band == op->band_type && channel == op->primary_channel; 4315 } 4316 4317 static void 4318 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4319 u32 len) 4320 { 4321 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4322 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4323 struct rtw89_chan new; 4324 u8 reason, status, tx_fail, band, actual_period; 4325 u32 last_chan = rtwdev->scan_info.last_chan_idx; 4326 u16 chan; 4327 int ret; 4328 4329 if (!rtwvif) 4330 return; 4331 4332 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 4333 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 4334 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 4335 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 4336 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 4337 actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data); 4338 4339 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4340 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4341 4342 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4343 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4344 band, chan, reason, status, tx_fail, actual_period); 4345 4346 switch (reason) { 4347 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4348 if (rtw89_is_op_chan(rtwdev, band, chan)) 4349 ieee80211_stop_queues(rtwdev->hw); 4350 return; 4351 case RTW89_SCAN_END_SCAN_NOTIFY: 4352 if (rtwvif && rtwvif->scan_req && 4353 last_chan < rtwvif->scan_req->n_channels) { 4354 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4355 if (ret) { 4356 rtw89_hw_scan_abort(rtwdev, vif); 4357 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4358 } 4359 } else { 4360 rtw89_hw_scan_complete(rtwdev, vif, false); 4361 } 4362 break; 4363 case RTW89_SCAN_ENTER_CH_NOTIFY: 4364 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4365 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4366 &rtwdev->scan_info.op_chan); 4367 ieee80211_wake_queues(rtwdev->hw); 4368 } else { 4369 rtw89_chan_create(&new, chan, chan, band, 4370 RTW89_CHANNEL_WIDTH_20); 4371 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4372 &new); 4373 } 4374 break; 4375 default: 4376 return; 4377 } 4378 } 4379 4380 static void 4381 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4382 struct sk_buff *skb) 4383 { 4384 struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4385 enum nl80211_cqm_rssi_threshold_event nl_event; 4386 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4387 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4388 u8 type, event, mac_id; 4389 s8 sig; 4390 4391 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4392 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4393 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4394 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4395 4396 if (mac_id != rtwvif->mac_id) 4397 return; 4398 4399 rtw89_debug(rtwdev, RTW89_DBG_FW, 4400 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4401 mac_id, type, sig, event); 4402 4403 switch (type) { 4404 case RTW89_BCN_FLTR_BEACON_LOSS: 4405 if (!rtwdev->scanning && !rtwvif->offchan) 4406 ieee80211_connection_loss(vif); 4407 else 4408 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4409 return; 4410 case RTW89_BCN_FLTR_NOTIFY: 4411 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4412 break; 4413 case RTW89_BCN_FLTR_RSSI: 4414 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4415 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4416 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4417 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4418 else 4419 return; 4420 break; 4421 default: 4422 return; 4423 } 4424 4425 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4426 } 4427 4428 static void 4429 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4430 u32 len) 4431 { 4432 struct rtw89_vif *rtwvif; 4433 4434 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4435 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4436 } 4437 4438 static void 4439 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4440 { 4441 /* N.B. This will run in interrupt context. */ 4442 4443 rtw89_debug(rtwdev, RTW89_DBG_FW, 4444 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4445 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4446 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4447 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4448 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4449 } 4450 4451 static void 4452 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4453 { 4454 /* N.B. This will run in interrupt context. */ 4455 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4456 const struct rtw89_c2h_done_ack *c2h = 4457 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4458 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4459 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4460 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4461 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4462 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4463 struct rtw89_completion_data data = {}; 4464 unsigned int cond; 4465 4466 rtw89_debug(rtwdev, RTW89_DBG_FW, 4467 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4468 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4469 4470 if (h2c_cat != H2C_CAT_MAC) 4471 return; 4472 4473 switch (h2c_class) { 4474 default: 4475 return; 4476 case H2C_CL_MAC_FW_OFLD: 4477 switch (h2c_func) { 4478 default: 4479 return; 4480 case H2C_FUNC_ADD_SCANOFLD_CH: 4481 case H2C_FUNC_SCANOFLD: 4482 cond = RTW89_FW_OFLD_WAIT_COND(0, h2c_func); 4483 break; 4484 } 4485 4486 data.err = !!h2c_return; 4487 rtw89_complete_cond(fw_ofld_wait, cond, &data); 4488 return; 4489 } 4490 } 4491 4492 static void 4493 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4494 { 4495 rtw89_fw_log_dump(rtwdev, c2h->data, len); 4496 } 4497 4498 static void 4499 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4500 { 4501 } 4502 4503 static void 4504 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 4505 u32 len) 4506 { 4507 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 4508 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 4509 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 4510 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 4511 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 4512 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 4513 struct rtw89_completion_data data = {}; 4514 unsigned int cond; 4515 4516 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 4517 pkt_id, pkt_op, pkt_len); 4518 4519 data.err = !pkt_len; 4520 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 4521 4522 rtw89_complete_cond(wait, cond, &data); 4523 } 4524 4525 static void 4526 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4527 u32 len) 4528 { 4529 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 4530 } 4531 4532 static void 4533 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4534 { 4535 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4536 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4537 4538 switch (func) { 4539 case H2C_FUNC_ADD_MCC: 4540 case H2C_FUNC_START_MCC: 4541 case H2C_FUNC_STOP_MCC: 4542 case H2C_FUNC_DEL_MCC_GROUP: 4543 case H2C_FUNC_RESET_MCC_GROUP: 4544 case H2C_FUNC_MCC_REQ_TSF: 4545 case H2C_FUNC_MCC_MACID_BITMAP: 4546 case H2C_FUNC_MCC_SYNC: 4547 case H2C_FUNC_MCC_SET_DURATION: 4548 break; 4549 default: 4550 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4551 "invalid MCC C2H RCV ACK: func %d\n", func); 4552 return; 4553 } 4554 4555 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4556 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4557 } 4558 4559 static void 4560 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4561 { 4562 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4563 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4564 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4565 struct rtw89_completion_data data = {}; 4566 unsigned int cond; 4567 bool next = false; 4568 4569 switch (func) { 4570 case H2C_FUNC_MCC_REQ_TSF: 4571 next = true; 4572 break; 4573 case H2C_FUNC_MCC_MACID_BITMAP: 4574 case H2C_FUNC_MCC_SYNC: 4575 case H2C_FUNC_MCC_SET_DURATION: 4576 break; 4577 case H2C_FUNC_ADD_MCC: 4578 case H2C_FUNC_START_MCC: 4579 case H2C_FUNC_STOP_MCC: 4580 case H2C_FUNC_DEL_MCC_GROUP: 4581 case H2C_FUNC_RESET_MCC_GROUP: 4582 default: 4583 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4584 "invalid MCC C2H REQ ACK: func %d\n", func); 4585 return; 4586 } 4587 4588 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4589 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 4590 group, func, retcode); 4591 4592 if (!retcode && next) 4593 return; 4594 4595 data.err = !!retcode; 4596 cond = RTW89_MCC_WAIT_COND(group, func); 4597 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4598 } 4599 4600 static void 4601 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4602 { 4603 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 4604 struct rtw89_completion_data data = {}; 4605 struct rtw89_mac_mcc_tsf_rpt *rpt; 4606 unsigned int cond; 4607 4608 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 4609 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 4610 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 4611 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 4612 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 4613 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 4614 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 4615 4616 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4617 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 4618 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 4619 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 4620 4621 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 4622 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4623 } 4624 4625 static void 4626 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4627 { 4628 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 4629 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 4630 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 4631 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 4632 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 4633 struct rtw89_completion_data data = {}; 4634 unsigned int cond; 4635 bool rsp = true; 4636 bool err; 4637 u8 func; 4638 4639 switch (status) { 4640 case RTW89_MAC_MCC_ADD_ROLE_OK: 4641 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 4642 func = H2C_FUNC_ADD_MCC; 4643 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 4644 break; 4645 case RTW89_MAC_MCC_START_GROUP_OK: 4646 case RTW89_MAC_MCC_START_GROUP_FAIL: 4647 func = H2C_FUNC_START_MCC; 4648 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 4649 break; 4650 case RTW89_MAC_MCC_STOP_GROUP_OK: 4651 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 4652 func = H2C_FUNC_STOP_MCC; 4653 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 4654 break; 4655 case RTW89_MAC_MCC_DEL_GROUP_OK: 4656 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 4657 func = H2C_FUNC_DEL_MCC_GROUP; 4658 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 4659 break; 4660 case RTW89_MAC_MCC_RESET_GROUP_OK: 4661 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 4662 func = H2C_FUNC_RESET_MCC_GROUP; 4663 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 4664 break; 4665 case RTW89_MAC_MCC_SWITCH_CH_OK: 4666 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 4667 case RTW89_MAC_MCC_TXNULL0_OK: 4668 case RTW89_MAC_MCC_TXNULL0_FAIL: 4669 case RTW89_MAC_MCC_TXNULL1_OK: 4670 case RTW89_MAC_MCC_TXNULL1_FAIL: 4671 case RTW89_MAC_MCC_SWITCH_EARLY: 4672 case RTW89_MAC_MCC_TBTT: 4673 case RTW89_MAC_MCC_DURATION_START: 4674 case RTW89_MAC_MCC_DURATION_END: 4675 rsp = false; 4676 break; 4677 default: 4678 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4679 "invalid MCC C2H STS RPT: status %d\n", status); 4680 return; 4681 } 4682 4683 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4684 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 4685 group, macid, status, (u64)tsf_high << 32 | tsf_low); 4686 4687 if (!rsp) 4688 return; 4689 4690 data.err = err; 4691 cond = RTW89_MCC_WAIT_COND(group, func); 4692 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4693 } 4694 4695 static 4696 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 4697 struct sk_buff *c2h, u32 len) = { 4698 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 4699 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 4700 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 4701 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 4702 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 4703 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 4704 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 4705 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 4706 }; 4707 4708 static 4709 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 4710 struct sk_buff *c2h, u32 len) = { 4711 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 4712 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 4713 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 4714 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 4715 }; 4716 4717 static 4718 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 4719 struct sk_buff *c2h, u32 len) = { 4720 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 4721 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 4722 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 4723 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 4724 }; 4725 4726 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 4727 { 4728 switch (class) { 4729 default: 4730 return false; 4731 case RTW89_MAC_C2H_CLASS_INFO: 4732 switch (func) { 4733 default: 4734 return false; 4735 case RTW89_MAC_C2H_FUNC_REC_ACK: 4736 case RTW89_MAC_C2H_FUNC_DONE_ACK: 4737 return true; 4738 } 4739 case RTW89_MAC_C2H_CLASS_OFLD: 4740 switch (func) { 4741 default: 4742 return false; 4743 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 4744 return true; 4745 } 4746 case RTW89_MAC_C2H_CLASS_MCC: 4747 return true; 4748 } 4749 } 4750 4751 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4752 u32 len, u8 class, u8 func) 4753 { 4754 void (*handler)(struct rtw89_dev *rtwdev, 4755 struct sk_buff *c2h, u32 len) = NULL; 4756 4757 switch (class) { 4758 case RTW89_MAC_C2H_CLASS_INFO: 4759 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 4760 handler = rtw89_mac_c2h_info_handler[func]; 4761 break; 4762 case RTW89_MAC_C2H_CLASS_OFLD: 4763 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 4764 handler = rtw89_mac_c2h_ofld_handler[func]; 4765 break; 4766 case RTW89_MAC_C2H_CLASS_MCC: 4767 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 4768 handler = rtw89_mac_c2h_mcc_handler[func]; 4769 break; 4770 case RTW89_MAC_C2H_CLASS_FWDBG: 4771 return; 4772 default: 4773 rtw89_info(rtwdev, "c2h class %d not support\n", class); 4774 return; 4775 } 4776 if (!handler) { 4777 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 4778 func); 4779 return; 4780 } 4781 handler(rtwdev, skb, len); 4782 } 4783 4784 static 4785 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 4786 enum rtw89_phy_idx phy_idx, 4787 u32 reg_base, u32 *cr) 4788 { 4789 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 4790 enum rtw89_qta_mode mode = dle_mem->mode; 4791 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 4792 4793 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 4794 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 4795 addr); 4796 goto error; 4797 } 4798 4799 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 4800 if (mode == RTW89_QTA_SCC) { 4801 rtw89_err(rtwdev, 4802 "[TXPWR] addr=0x%x but hw not enable\n", 4803 addr); 4804 goto error; 4805 } 4806 4807 *cr = addr; 4808 return true; 4809 4810 error: 4811 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 4812 addr, phy_idx); 4813 4814 return false; 4815 } 4816 4817 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 4818 { 4819 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 4820 int ret; 4821 4822 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4823 if (ret) 4824 return ret; 4825 4826 if (!enable) { 4827 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 4828 return 0; 4829 } 4830 4831 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 4832 B_AX_APP_MAC_INFO_RPT | 4833 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 4834 B_AX_PPDU_STAT_RPT_CRC32); 4835 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 4836 RTW89_PRPT_DEST_HOST); 4837 4838 return 0; 4839 } 4840 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 4841 4842 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 4843 { 4844 #define MAC_AX_TIME_TH_SH 5 4845 #define MAC_AX_LEN_TH_SH 4 4846 #define MAC_AX_TIME_TH_MAX 255 4847 #define MAC_AX_LEN_TH_MAX 255 4848 #define MAC_AX_TIME_TH_DEF 88 4849 #define MAC_AX_LEN_TH_DEF 4080 4850 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4851 struct ieee80211_hw *hw = rtwdev->hw; 4852 u32 rts_threshold = hw->wiphy->rts_threshold; 4853 u32 time_th, len_th; 4854 u32 reg; 4855 4856 if (rts_threshold == (u32)-1) { 4857 time_th = MAC_AX_TIME_TH_DEF; 4858 len_th = MAC_AX_LEN_TH_DEF; 4859 } else { 4860 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 4861 len_th = rts_threshold; 4862 } 4863 4864 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 4865 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 4866 4867 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 4868 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 4869 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 4870 } 4871 4872 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 4873 { 4874 bool empty; 4875 int ret; 4876 4877 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4878 return; 4879 4880 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 4881 10000, 200000, false, rtwdev); 4882 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 4883 rtw89_info(rtwdev, "timed out to flush queues\n"); 4884 } 4885 4886 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 4887 { 4888 u8 val; 4889 u16 val16; 4890 u32 val32; 4891 int ret; 4892 4893 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 4894 if (rtwdev->chip->chip_id != RTL8851B) 4895 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 4896 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 4897 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 4898 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 4899 if (rtwdev->chip->chip_id != RTL8851B) 4900 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 4901 4902 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 4903 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 4904 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 4905 4906 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 4907 if (ret) { 4908 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 4909 return ret; 4910 } 4911 val32 = val32 & B_AX_WL_RX_CTRL; 4912 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 4913 if (ret) { 4914 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 4915 return ret; 4916 } 4917 4918 switch (coex->pta_mode) { 4919 case RTW89_MAC_AX_COEX_RTK_MODE: 4920 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4921 val &= ~B_AX_BTMODE_MASK; 4922 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 4923 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4924 4925 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 4926 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 4927 4928 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 4929 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 4930 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 4931 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 4932 break; 4933 case RTW89_MAC_AX_COEX_CSR_MODE: 4934 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4935 val &= ~B_AX_BTMODE_MASK; 4936 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 4937 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4938 4939 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 4940 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 4941 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 4942 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 4943 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 4944 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 4945 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 4946 val16 |= B_AX_ENHANCED_BT; 4947 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 4948 4949 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 4950 break; 4951 default: 4952 return -EINVAL; 4953 } 4954 4955 switch (coex->direction) { 4956 case RTW89_MAC_AX_COEX_INNER: 4957 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4958 val = (val & ~BIT(2)) | BIT(1); 4959 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4960 break; 4961 case RTW89_MAC_AX_COEX_OUTPUT: 4962 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4963 val = val | BIT(1) | BIT(0); 4964 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4965 break; 4966 case RTW89_MAC_AX_COEX_INPUT: 4967 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4968 val = val & ~(BIT(2) | BIT(1)); 4969 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4970 break; 4971 default: 4972 return -EINVAL; 4973 } 4974 4975 return 0; 4976 } 4977 EXPORT_SYMBOL(rtw89_mac_coex_init); 4978 4979 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 4980 const struct rtw89_mac_ax_coex *coex) 4981 { 4982 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 4983 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 4984 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 4985 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 4986 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 4987 4988 switch (coex->pta_mode) { 4989 case RTW89_MAC_AX_COEX_RTK_MODE: 4990 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4991 MAC_AX_RTK_MODE); 4992 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 4993 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 4994 break; 4995 case RTW89_MAC_AX_COEX_CSR_MODE: 4996 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4997 MAC_AX_CSR_MODE); 4998 break; 4999 default: 5000 return -EINVAL; 5001 } 5002 5003 return 0; 5004 } 5005 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 5006 5007 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5008 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5009 { 5010 u32 val = 0, ret; 5011 5012 if (gnt_cfg->band[0].gnt_bt) 5013 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 5014 5015 if (gnt_cfg->band[0].gnt_bt_sw_en) 5016 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 5017 5018 if (gnt_cfg->band[0].gnt_wl) 5019 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 5020 5021 if (gnt_cfg->band[0].gnt_wl_sw_en) 5022 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 5023 5024 if (gnt_cfg->band[1].gnt_bt) 5025 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 5026 5027 if (gnt_cfg->band[1].gnt_bt_sw_en) 5028 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 5029 5030 if (gnt_cfg->band[1].gnt_wl) 5031 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 5032 5033 if (gnt_cfg->band[1].gnt_wl_sw_en) 5034 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 5035 5036 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 5037 if (ret) { 5038 rtw89_err(rtwdev, "Write LTE fail!\n"); 5039 return ret; 5040 } 5041 5042 return 0; 5043 } 5044 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 5045 5046 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 5047 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5048 { 5049 u32 val = 0; 5050 5051 if (gnt_cfg->band[0].gnt_bt) 5052 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5053 B_AX_GNT_BT_TX_VAL; 5054 else 5055 val |= B_AX_WL_ACT_VAL; 5056 5057 if (gnt_cfg->band[0].gnt_bt_sw_en) 5058 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5059 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5060 5061 if (gnt_cfg->band[0].gnt_wl) 5062 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5063 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5064 5065 if (gnt_cfg->band[0].gnt_wl_sw_en) 5066 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5067 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5068 5069 if (gnt_cfg->band[1].gnt_bt) 5070 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5071 B_AX_GNT_BT_TX_VAL; 5072 else 5073 val |= B_AX_WL_ACT_VAL; 5074 5075 if (gnt_cfg->band[1].gnt_bt_sw_en) 5076 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5077 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5078 5079 if (gnt_cfg->band[1].gnt_wl) 5080 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5081 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5082 5083 if (gnt_cfg->band[1].gnt_wl_sw_en) 5084 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5085 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5086 5087 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5088 5089 return 0; 5090 } 5091 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5092 5093 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5094 { 5095 u32 reg; 5096 u16 val; 5097 int ret; 5098 5099 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5100 if (ret) 5101 return ret; 5102 5103 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 5104 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5105 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5106 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5107 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5108 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5109 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5110 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 5111 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 5112 B_AX_PLT_EN; 5113 rtw89_write16(rtwdev, reg, val); 5114 5115 return 0; 5116 } 5117 5118 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5119 { 5120 u32 fw_sb; 5121 5122 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5123 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5124 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5125 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5126 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5127 else 5128 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5129 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5130 val = B_AX_TOGGLE | 5131 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5132 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5133 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5134 fsleep(1000); /* avoid BT FW loss information */ 5135 } 5136 5137 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5138 { 5139 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5140 } 5141 5142 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5143 { 5144 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5145 5146 val = wl ? val | BIT(2) : val & ~BIT(2); 5147 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5148 5149 return 0; 5150 } 5151 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5152 5153 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5154 { 5155 struct rtw89_btc *btc = &rtwdev->btc; 5156 struct rtw89_btc_dm *dm = &btc->dm; 5157 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5158 int i; 5159 5160 if (wl) 5161 return 0; 5162 5163 for (i = 0; i < RTW89_PHY_MAX; i++) { 5164 g[i].gnt_bt_sw_en = 1; 5165 g[i].gnt_bt = 1; 5166 g[i].gnt_wl_sw_en = 1; 5167 g[i].gnt_wl = 0; 5168 } 5169 5170 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5171 } 5172 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5173 5174 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5175 { 5176 const struct rtw89_chip_info *chip = rtwdev->chip; 5177 u8 val = 0; 5178 5179 if (chip->chip_id == RTL8852C) 5180 return false; 5181 else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 5182 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5183 B_AX_LTE_MUX_CTRL_PATH >> 24); 5184 5185 return !!val; 5186 } 5187 5188 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 5189 { 5190 u32 reg; 5191 u16 cnt; 5192 5193 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 5194 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 5195 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 5196 5197 return cnt; 5198 } 5199 5200 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 5201 bool keep) 5202 { 5203 u32 reg; 5204 5205 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 5206 return; 5207 5208 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5209 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5210 if (keep) { 5211 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5212 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5213 BFRP_RX_STANDBY_TIMER_KEEP); 5214 } else { 5215 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5216 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5217 BFRP_RX_STANDBY_TIMER_RELEASE); 5218 } 5219 } 5220 5221 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5222 { 5223 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5224 u32 reg; 5225 u32 mask = mac->bfee_ctrl.mask; 5226 5227 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5228 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 5229 if (en) { 5230 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5231 rtw89_write32_set(rtwdev, reg, mask); 5232 } else { 5233 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5234 rtw89_write32_clr(rtwdev, reg, mask); 5235 } 5236 } 5237 5238 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 5239 { 5240 u32 reg; 5241 u32 val32; 5242 int ret; 5243 5244 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5245 if (ret) 5246 return ret; 5247 5248 /* AP mode set tx gid to 63 */ 5249 /* STA mode set tx gid to 0(default) */ 5250 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 5251 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5252 5253 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5254 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5255 5256 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5257 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5258 rtw89_write32(rtwdev, reg, val32); 5259 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5260 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5261 5262 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5263 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5264 B_AX_BFMEE_USE_NSTS | 5265 B_AX_BFMEE_CSI_GID_SEL | 5266 B_AX_BFMEE_CSI_FORCE_RETE_EN); 5267 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5268 rtw89_write32(rtwdev, reg, 5269 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5270 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5271 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5272 5273 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 5274 rtw89_write32_set(rtwdev, reg, 5275 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 5276 5277 return 0; 5278 } 5279 5280 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 5281 struct ieee80211_vif *vif, 5282 struct ieee80211_sta *sta) 5283 { 5284 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5285 u8 mac_idx = rtwvif->mac_idx; 5286 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5287 u8 port_sel = rtwvif->port; 5288 u8 sound_dim = 3, t; 5289 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5290 u32 reg; 5291 u16 val; 5292 int ret; 5293 5294 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5295 if (ret) 5296 return ret; 5297 5298 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5299 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5300 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5301 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5302 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5303 phy_cap[5]); 5304 sound_dim = min(sound_dim, t); 5305 } 5306 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5307 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5308 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5309 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5310 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5311 sta->deflink.vht_cap.cap); 5312 sound_dim = min(sound_dim, t); 5313 } 5314 nc = min(nc, sound_dim); 5315 nr = min(nr, sound_dim); 5316 5317 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5318 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5319 5320 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5321 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5322 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5323 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5324 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5325 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5326 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5327 5328 if (port_sel == 0) 5329 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5330 else 5331 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5332 5333 rtw89_write16(rtwdev, reg, val); 5334 5335 return 0; 5336 } 5337 5338 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 5339 struct ieee80211_vif *vif, 5340 struct ieee80211_sta *sta) 5341 { 5342 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5343 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5344 u32 reg; 5345 u8 mac_idx = rtwvif->mac_idx; 5346 int ret; 5347 5348 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5349 if (ret) 5350 return ret; 5351 5352 if (sta->deflink.he_cap.has_he) { 5353 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5354 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5355 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5356 } 5357 if (sta->deflink.vht_cap.vht_supported) { 5358 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5359 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5360 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5361 } 5362 if (sta->deflink.ht_cap.ht_supported) { 5363 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5364 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5365 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5366 } 5367 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5368 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5369 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5370 rtw89_write32(rtwdev, 5371 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5372 rrsc); 5373 5374 return 0; 5375 } 5376 5377 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 5378 struct ieee80211_vif *vif, 5379 struct ieee80211_sta *sta) 5380 { 5381 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5382 5383 if (rtw89_sta_has_beamformer_cap(sta)) { 5384 rtw89_debug(rtwdev, RTW89_DBG_BF, 5385 "initialize bfee for new association\n"); 5386 rtw89_mac_init_bfee_ax(rtwdev, rtwvif->mac_idx); 5387 rtw89_mac_set_csi_para_reg_ax(rtwdev, vif, sta); 5388 rtw89_mac_csi_rrsc_ax(rtwdev, vif, sta); 5389 } 5390 } 5391 5392 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5393 struct ieee80211_sta *sta) 5394 { 5395 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5396 5397 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 5398 } 5399 5400 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5401 struct ieee80211_bss_conf *conf) 5402 { 5403 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5404 u8 mac_idx = rtwvif->mac_idx; 5405 __le32 *p; 5406 5407 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 5408 5409 p = (__le32 *)conf->mu_group.membership; 5410 rtw89_write32(rtwdev, 5411 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 5412 le32_to_cpu(p[0])); 5413 rtw89_write32(rtwdev, 5414 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 5415 le32_to_cpu(p[1])); 5416 5417 p = (__le32 *)conf->mu_group.position; 5418 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 5419 le32_to_cpu(p[0])); 5420 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 5421 le32_to_cpu(p[1])); 5422 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 5423 le32_to_cpu(p[2])); 5424 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 5425 le32_to_cpu(p[3])); 5426 } 5427 5428 struct rtw89_mac_bf_monitor_iter_data { 5429 struct rtw89_dev *rtwdev; 5430 struct ieee80211_sta *down_sta; 5431 int count; 5432 }; 5433 5434 static 5435 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 5436 { 5437 struct rtw89_mac_bf_monitor_iter_data *iter_data = 5438 (struct rtw89_mac_bf_monitor_iter_data *)data; 5439 struct ieee80211_sta *down_sta = iter_data->down_sta; 5440 int *count = &iter_data->count; 5441 5442 if (down_sta == sta) 5443 return; 5444 5445 if (rtw89_sta_has_beamformer_cap(sta)) 5446 (*count)++; 5447 } 5448 5449 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 5450 struct ieee80211_sta *sta, bool disconnect) 5451 { 5452 struct rtw89_mac_bf_monitor_iter_data data; 5453 5454 data.rtwdev = rtwdev; 5455 data.down_sta = disconnect ? sta : NULL; 5456 data.count = 0; 5457 ieee80211_iterate_stations_atomic(rtwdev->hw, 5458 rtw89_mac_bf_monitor_calc_iter, 5459 &data); 5460 5461 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 5462 if (data.count) 5463 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5464 else 5465 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5466 } 5467 5468 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 5469 { 5470 struct rtw89_traffic_stats *stats = &rtwdev->stats; 5471 struct rtw89_vif *rtwvif; 5472 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 5473 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5474 bool keep_timer = true; 5475 bool old_keep_timer; 5476 5477 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5478 5479 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 5480 keep_timer = false; 5481 5482 if (keep_timer != old_keep_timer) { 5483 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5484 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 5485 keep_timer); 5486 } 5487 5488 if (en == old) 5489 return; 5490 5491 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5492 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 5493 } 5494 5495 static int 5496 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5497 u32 tx_time) 5498 { 5499 #define MAC_AX_DFLT_TX_TIME 5280 5500 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5501 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 5502 u32 reg; 5503 int ret = 0; 5504 5505 if (rtwsta->cctl_tx_time) { 5506 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 5507 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5508 } else { 5509 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5510 if (ret) { 5511 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 5512 return ret; 5513 } 5514 5515 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 5516 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 5517 max_tx_time >> 5); 5518 } 5519 5520 return ret; 5521 } 5522 5523 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5524 bool resume, u32 tx_time) 5525 { 5526 int ret = 0; 5527 5528 if (!resume) { 5529 rtwsta->cctl_tx_time = true; 5530 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5531 } else { 5532 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5533 rtwsta->cctl_tx_time = false; 5534 } 5535 5536 return ret; 5537 } 5538 5539 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5540 u32 *tx_time) 5541 { 5542 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5543 u32 reg; 5544 int ret = 0; 5545 5546 if (rtwsta->cctl_tx_time) { 5547 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 5548 } else { 5549 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5550 if (ret) { 5551 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 5552 return ret; 5553 } 5554 5555 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 5556 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 5557 } 5558 5559 return ret; 5560 } 5561 5562 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 5563 struct rtw89_sta *rtwsta, 5564 bool resume, u8 tx_retry) 5565 { 5566 int ret = 0; 5567 5568 rtwsta->data_tx_cnt_lmt = tx_retry; 5569 5570 if (!resume) { 5571 rtwsta->cctl_tx_retry_limit = true; 5572 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5573 } else { 5574 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5575 rtwsta->cctl_tx_retry_limit = false; 5576 } 5577 5578 return ret; 5579 } 5580 5581 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 5582 struct rtw89_sta *rtwsta, u8 *tx_retry) 5583 { 5584 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5585 u32 reg; 5586 int ret = 0; 5587 5588 if (rtwsta->cctl_tx_retry_limit) { 5589 *tx_retry = rtwsta->data_tx_cnt_lmt; 5590 } else { 5591 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5592 if (ret) { 5593 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 5594 return ret; 5595 } 5596 5597 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); 5598 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 5599 } 5600 5601 return ret; 5602 } 5603 5604 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 5605 struct rtw89_vif *rtwvif, bool en) 5606 { 5607 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5608 u8 mac_idx = rtwvif->mac_idx; 5609 u16 set = mac->muedca_ctrl.mask; 5610 u32 reg; 5611 u32 ret; 5612 5613 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5614 if (ret) 5615 return ret; 5616 5617 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 5618 if (en) 5619 rtw89_write16_set(rtwdev, reg, set); 5620 else 5621 rtw89_write16_clr(rtwdev, reg, set); 5622 5623 return 0; 5624 } 5625 5626 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 5627 { 5628 u32 val32; 5629 int ret; 5630 5631 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5632 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 5633 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 5634 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 5635 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5636 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5637 5638 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5639 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5640 if (ret) { 5641 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 5642 offset, val, mask); 5643 return ret; 5644 } 5645 5646 return 0; 5647 } 5648 EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 5649 5650 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 5651 { 5652 u32 val32; 5653 int ret; 5654 5655 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5656 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 5657 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 5658 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 5659 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5660 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5661 5662 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5663 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5664 if (ret) { 5665 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 5666 return ret; 5667 } 5668 5669 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 5670 5671 return 0; 5672 } 5673 EXPORT_SYMBOL(rtw89_mac_read_xtal_si); 5674 5675 static 5676 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 5677 { 5678 static const enum rtw89_pkt_drop_sel sels[] = { 5679 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5680 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5681 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5682 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5683 }; 5684 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5685 struct rtw89_pkt_drop_params params = {0}; 5686 int i; 5687 5688 params.mac_band = RTW89_MAC_0; 5689 params.macid = rtwsta->mac_id; 5690 params.port = rtwvif->port; 5691 params.mbssid = 0; 5692 params.tf_trs = rtwvif->trigger; 5693 5694 for (i = 0; i < ARRAY_SIZE(sels); i++) { 5695 params.sel = sels[i]; 5696 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5697 } 5698 } 5699 5700 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 5701 { 5702 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 5703 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5704 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 5705 struct rtw89_vif *target = data; 5706 5707 if (rtwvif != target) 5708 return; 5709 5710 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 5711 } 5712 5713 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 5714 { 5715 ieee80211_iterate_stations_atomic(rtwdev->hw, 5716 rtw89_mac_pkt_drop_vif_iter, 5717 rtwvif); 5718 } 5719 5720 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 5721 enum rtw89_mac_idx band) 5722 { 5723 struct rtw89_pkt_drop_params params = {0}; 5724 bool empty; 5725 int i, ret = 0, try_cnt = 3; 5726 5727 params.mac_band = band; 5728 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 5729 5730 for (i = 0; i < try_cnt; i++) { 5731 ret = read_poll_timeout(mac_is_txq_empty, empty, empty, 50, 5732 50000, false, rtwdev); 5733 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 5734 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5735 else 5736 return 0; 5737 } 5738 return ret; 5739 } 5740 5741 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 5742 { 5743 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 5744 5745 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 5746 } 5747 5748 static 5749 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 5750 bool h2c_or_fwdl) 5751 { 5752 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 5753 u8 val; 5754 5755 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 5756 1, FWDL_WAIT_CNT, false, 5757 rtwdev, R_AX_WCPU_FW_CTRL); 5758 } 5759 5760 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 5761 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 5762 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 5763 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 5764 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 5765 .rx_fltr = R_AX_RX_FLTR_OPT, 5766 .port_base = &rtw89_port_base_ax, 5767 .agg_len_ht = R_AX_AGG_LEN_HT_0, 5768 5769 .muedca_ctrl = { 5770 .addr = R_AX_MUEDCA_EN, 5771 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 5772 }, 5773 .bfee_ctrl = { 5774 .addr = R_AX_BFMEE_RESP_OPTION, 5775 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 5776 B_AX_BFMEE_HE_NDPA_EN, 5777 }, 5778 5779 .bf_assoc = rtw89_mac_bf_assoc_ax, 5780 5781 .disable_cpu = rtw89_mac_disable_cpu_ax, 5782 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 5783 .fwdl_get_status = rtw89_fw_get_rdy_ax, 5784 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 5785 .parse_efuse_map = rtw89_parse_efuse_map_ax, 5786 .parse_phycap_map = rtw89_parse_phycap_map_ax, 5787 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 5788 5789 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 5790 }; 5791 EXPORT_SYMBOL(rtw89_mac_gen_ax); 5792