1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "util.h" 15 16 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 17 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 18 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 19 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 20 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 21 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 22 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 26 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 29 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 31 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 35 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 36 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 37 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 38 }; 39 40 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 41 u32 val, enum rtw89_mac_mem_sel sel) 42 { 43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44 u32 addr = mac->mem_base_addrs[sel] + offset; 45 46 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 47 rtw89_write32(rtwdev, mac->indir_access_addr, val); 48 } 49 50 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 51 enum rtw89_mac_mem_sel sel) 52 { 53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 54 u32 addr = mac->mem_base_addrs[sel] + offset; 55 56 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 57 return rtw89_read32(rtwdev, mac->indir_access_addr); 58 } 59 60 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 61 enum rtw89_mac_hwmod_sel sel) 62 { 63 u32 val, r_val; 64 65 if (sel == RTW89_DMAC_SEL) { 66 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 67 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 69 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 70 val = B_AX_CMAC_EN; 71 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 72 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 73 val = B_AX_CMAC1_FEN; 74 } else { 75 return -EINVAL; 76 } 77 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 78 (val & r_val) != val) 79 return -EFAULT; 80 81 return 0; 82 } 83 84 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 85 { 86 u8 lte_ctrl; 87 int ret; 88 89 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 90 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 91 if (ret && !test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 92 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 93 94 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 95 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 96 97 return ret; 98 } 99 100 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 101 { 102 u8 lte_ctrl; 103 int ret; 104 105 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 106 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 107 if (ret && !test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 108 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 109 110 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 111 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 112 113 return ret; 114 } 115 116 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 117 { 118 u32 ctrl_reg, data_reg, ctrl_data; 119 u32 val; 120 int ret; 121 122 switch (ctrl->type) { 123 case DLE_CTRL_TYPE_WDE: 124 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 125 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 126 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 127 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 128 B_AX_WDE_DFI_ACTIVE; 129 break; 130 case DLE_CTRL_TYPE_PLE: 131 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 132 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 133 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 134 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 135 B_AX_PLE_DFI_ACTIVE; 136 break; 137 default: 138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 139 return -EINVAL; 140 } 141 142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 143 144 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 145 1, 1000, false, rtwdev, ctrl_reg); 146 if (ret) { 147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 148 ctrl_reg, ctrl_data); 149 return ret; 150 } 151 152 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 153 return 0; 154 } 155 156 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 157 struct rtw89_mac_dle_dfi_quota *quota) 158 { 159 struct rtw89_mac_dle_dfi_ctrl ctrl; 160 int ret; 161 162 ctrl.type = quota->dle_type; 163 ctrl.target = DLE_DFI_TYPE_QUOTA; 164 ctrl.addr = quota->qtaid; 165 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 166 if (ret) { 167 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 168 return ret; 169 } 170 171 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 172 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 173 return 0; 174 } 175 176 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 177 struct rtw89_mac_dle_dfi_qempty *qempty) 178 { 179 struct rtw89_mac_dle_dfi_ctrl ctrl; 180 u32 ret; 181 182 ctrl.type = qempty->dle_type; 183 ctrl.target = DLE_DFI_TYPE_QEMPTY; 184 ctrl.addr = qempty->grpsel; 185 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 186 if (ret) { 187 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 188 return ret; 189 } 190 191 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 192 return 0; 193 } 194 195 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 196 { 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 209 } 210 211 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 212 { 213 struct rtw89_mac_dle_dfi_qempty qempty; 214 struct rtw89_mac_dle_dfi_quota quota; 215 struct rtw89_mac_dle_dfi_ctrl ctrl; 216 u32 val, not_empty, i; 217 int ret; 218 219 qempty.dle_type = DLE_CTRL_TYPE_PLE; 220 qempty.grpsel = 0; 221 qempty.qempty = ~(u32)0; 222 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 223 if (ret) 224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 225 else 226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 227 228 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 229 if (!(not_empty & BIT(0))) 230 continue; 231 ctrl.type = DLE_CTRL_TYPE_PLE; 232 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 233 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 234 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 235 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 236 if (ret) 237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 238 else 239 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 240 u32_get_bits(ctrl.out_data, 241 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 242 } 243 244 quota.dle_type = DLE_CTRL_TYPE_PLE; 245 quota.qtaid = 6; 246 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 247 if (ret) 248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 249 else 250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 251 quota.rsv_pgnum, quota.use_pgnum); 252 253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 255 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 257 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 258 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 259 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 260 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 261 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 262 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 263 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 264 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 265 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 266 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 267 268 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 269 quota.dle_type = DLE_CTRL_TYPE_PLE; 270 quota.qtaid = 7; 271 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 272 if (ret) 273 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 274 else 275 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 276 quota.rsv_pgnum, quota.use_pgnum); 277 278 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 279 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 280 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 282 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 283 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 284 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 285 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 286 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 287 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 288 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 289 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 290 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 291 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 292 } 293 294 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 295 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 298 299 dump_err_status_dispatcher_ax(rtwdev); 300 } 301 302 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 303 enum mac_ax_err_info err) 304 { 305 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 306 u32 dbg, event; 307 308 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 309 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 310 311 switch (event) { 312 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 313 rtw89_info(rtwdev, "quota lost!\n"); 314 mac->dump_qta_lost(rtwdev); 315 break; 316 default: 317 break; 318 } 319 } 320 321 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 322 { 323 const struct rtw89_chip_info *chip = rtwdev->chip; 324 u32 dmac_err; 325 int i, ret; 326 327 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 328 if (ret) { 329 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 330 return; 331 } 332 333 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 334 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 335 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 337 338 if (dmac_err) { 339 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 341 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 343 if (chip->chip_id == RTL8852C) { 344 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 345 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 346 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 348 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 352 } 353 } 354 355 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 356 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 357 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 360 if (chip->chip_id == RTL8852C) 361 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 363 else 364 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 365 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 366 } 367 368 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 369 if (chip->chip_id == RTL8852C) { 370 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 371 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 372 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 374 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 376 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 378 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 380 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 382 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 384 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 386 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 388 389 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 390 B_AX_DBG_SEL0, 0x8B); 391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392 B_AX_DBG_SEL1, 0x8B); 393 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 394 B_AX_SEL_0XC0_MASK, 1); 395 for (i = 0; i < 0x10; i++) { 396 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 397 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 398 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 399 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 400 } 401 } else if (chip->chip_id == RTL8922A) { 402 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 403 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 406 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 407 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 408 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 409 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 410 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 411 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 412 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 413 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 414 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 415 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 416 } else { 417 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 419 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 421 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 423 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 425 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 427 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 429 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 430 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 431 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 432 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 433 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 435 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 437 } 438 } 439 440 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 441 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 442 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 445 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 449 } 450 451 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 452 if (chip->chip_id == RTL8922A) { 453 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 454 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 455 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 456 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 457 } else { 458 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 459 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 462 } 463 } 464 465 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 466 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 468 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 470 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 471 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 472 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 474 } 475 476 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 477 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 478 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 479 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 486 } else { 487 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 491 } 492 } 493 494 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 495 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 501 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 503 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 509 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 510 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 515 if (chip->chip_id == RTL8922A) { 516 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 517 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 520 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 521 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 522 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 524 } else { 525 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 526 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 527 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 529 if (chip->chip_id == RTL8852C) { 530 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 531 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 532 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 533 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 534 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 535 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 536 } else { 537 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 538 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 543 } 544 } 545 } 546 547 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 548 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 549 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 552 } 553 554 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 555 if (chip->chip_id == RTL8922A) { 556 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 557 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 558 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 559 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 560 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 561 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 562 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 563 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 564 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 565 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 566 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 567 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 568 } else { 569 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 570 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 573 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 574 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 577 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 578 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 581 } 582 } 583 584 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 585 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 586 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 587 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 590 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 591 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 594 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 595 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 598 } else { 599 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 600 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 601 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 602 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 605 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 606 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 609 } 610 if (chip->chip_id == RTL8922A) { 611 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 612 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 615 } 616 } 617 618 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 619 if (chip->chip_id == RTL8922A) { 620 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 621 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 624 } else if (chip->chip_id == RTL8852C) { 625 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 626 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 629 } 630 } 631 632 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 633 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 634 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 635 RTW89_MAC_MEM_AXIDMA)); 636 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 637 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 638 RTW89_MAC_MEM_AXIDMA)); 639 } 640 641 if (dmac_err & B_BE_MLO_ERR_INT) { 642 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 643 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 644 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 646 } 647 648 if (dmac_err & B_BE_PLRLS_ERR_INT) { 649 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 650 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 653 } 654 } 655 656 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 657 u8 band) 658 { 659 const struct rtw89_chip_info *chip = rtwdev->chip; 660 u32 offset = 0; 661 u32 cmac_err; 662 int ret; 663 664 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 665 if (ret) { 666 if (band) 667 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 668 else 669 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 670 return; 671 } 672 673 if (band) 674 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 675 676 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 677 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 678 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 679 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 680 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 681 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 682 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 683 684 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 685 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 686 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 689 } 690 691 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 692 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 693 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 694 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 695 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 696 } 697 698 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 699 if (chip->chip_id == RTL8852C) { 700 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 701 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 704 } else { 705 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 706 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 707 } 708 } 709 710 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 711 if (chip->chip_id == RTL8852C) { 712 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 713 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 716 } else { 717 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 718 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 719 } 720 } 721 722 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 723 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 724 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 725 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 726 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 727 } 728 729 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 730 if (chip->chip_id == RTL8852C) { 731 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 732 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 735 } else { 736 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 737 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 738 } 739 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 740 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 741 } 742 743 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 744 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 745 } 746 747 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 748 enum mac_ax_err_info err) 749 { 750 if (err != MAC_AX_ERR_L1_ERR_DMAC && 751 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 752 err != MAC_AX_ERR_L0_ERR_CMAC0 && 753 err != MAC_AX_ERR_L0_ERR_CMAC1 && 754 err != MAC_AX_ERR_RXI300) 755 return; 756 757 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 758 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 759 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 762 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 763 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 764 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 766 767 rtw89_mac_dump_dmac_err_status(rtwdev); 768 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 769 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 770 771 rtwdev->hci.ops->dump_err_status(rtwdev); 772 773 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 774 rtw89_mac_dump_l0_to_l1(rtwdev, err); 775 776 rtw89_info(rtwdev, "<---\n"); 777 } 778 779 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 780 { 781 struct rtw89_ser *ser = &rtwdev->ser; 782 u32 dmac_err, imr, isr; 783 int ret; 784 785 if (rtwdev->chip->chip_id == RTL8852C) { 786 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 787 if (ret) 788 return true; 789 790 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 791 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 792 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 793 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 794 795 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 796 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 797 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 798 return true; 799 } 800 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 801 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 802 return true; 803 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 804 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 805 return true; 806 } 807 } 808 809 return false; 810 } 811 812 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 813 { 814 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 815 u32 err, err_scnr; 816 int ret; 817 818 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 819 false, rtwdev, R_AX_HALT_C2H_CTRL); 820 if (ret) { 821 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 822 return ret; 823 } 824 825 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 826 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 827 828 err_scnr = RTW89_ERROR_SCENARIO(err); 829 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 830 err = MAC_AX_ERR_CPU_EXCEPTION; 831 else if (err_scnr == RTW89_WCPU_ASSERTION) 832 err = MAC_AX_ERR_ASSERTION; 833 else if (err_scnr == RTW89_RXI300_ERROR) 834 err = MAC_AX_ERR_RXI300; 835 836 if (rtw89_mac_suppress_log(rtwdev, err)) 837 return err; 838 839 rtw89_fw_st_dbg_dump(rtwdev); 840 mac->dump_err_status(rtwdev, err); 841 842 return err; 843 } 844 EXPORT_SYMBOL(rtw89_mac_get_err_status); 845 846 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 847 { 848 struct rtw89_ser *ser = &rtwdev->ser; 849 u32 halt; 850 int ret = 0; 851 852 if (err > MAC_AX_SET_ERR_MAX) { 853 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 854 return -EINVAL; 855 } 856 857 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 858 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 859 if (ret) { 860 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 861 return -EFAULT; 862 } 863 864 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 865 866 if (ser->prehandle_l1 && 867 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 868 return 0; 869 870 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 871 872 return 0; 873 } 874 EXPORT_SYMBOL(rtw89_mac_set_err_status); 875 876 static int hfc_reset_param(struct rtw89_dev *rtwdev) 877 { 878 const struct rtw89_hfc_param_ini *param_ini, *param_inis; 879 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 880 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 881 882 param_inis = rtwdev->chip->hfc_param_ini[rtwdev->hci.type]; 883 if (!param_inis) 884 return -EINVAL; 885 886 param_ini = ¶m_inis[qta_mode]; 887 888 param->en = 0; 889 890 if (param_ini->pub_cfg) 891 param->pub_cfg = *param_ini->pub_cfg; 892 893 if (param_ini->prec_cfg) 894 param->prec_cfg = *param_ini->prec_cfg; 895 896 if (param_ini->ch_cfg) 897 param->ch_cfg = param_ini->ch_cfg; 898 899 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 900 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 901 param->mode = param_ini->mode; 902 903 return 0; 904 } 905 906 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 907 { 908 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 909 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 910 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 911 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 912 913 if (ch >= RTW89_DMA_CH_NUM) 914 return -EINVAL; 915 916 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 917 ch_cfg[ch].max > pub_cfg->pub_max) 918 return -EINVAL; 919 if (ch_cfg[ch].grp >= grp_num) 920 return -EINVAL; 921 922 return 0; 923 } 924 925 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 926 { 927 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 928 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 929 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 930 931 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 932 if (rtwdev->chip->chip_id == RTL8852A) 933 return 0; 934 else 935 return -EFAULT; 936 } 937 938 return 0; 939 } 940 941 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 942 { 943 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 944 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 945 946 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 947 return -EFAULT; 948 949 return 0; 950 } 951 952 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 953 { 954 const struct rtw89_chip_info *chip = rtwdev->chip; 955 const struct rtw89_page_regs *regs = chip->page_regs; 956 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 957 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 958 int ret = 0; 959 u32 val = 0; 960 961 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 962 if (ret) 963 return ret; 964 965 ret = hfc_ch_cfg_chk(rtwdev, ch); 966 if (ret) 967 return ret; 968 969 if (ch > RTW89_DMA_B1HI) 970 return -EINVAL; 971 972 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 973 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 974 (cfg[ch].grp ? B_AX_GRP : 0); 975 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 976 977 return 0; 978 } 979 980 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 981 { 982 const struct rtw89_chip_info *chip = rtwdev->chip; 983 const struct rtw89_page_regs *regs = chip->page_regs; 984 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 985 struct rtw89_hfc_ch_info *info = param->ch_info; 986 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 987 u32 val; 988 u32 ret; 989 990 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 991 if (ret) 992 return ret; 993 994 if (ch > RTW89_DMA_H2C) 995 return -EINVAL; 996 997 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 998 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 999 if (ch < RTW89_DMA_H2C) 1000 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1001 else 1002 info[ch].used = cfg[ch].min - info[ch].aval; 1003 1004 return 0; 1005 } 1006 1007 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1008 { 1009 const struct rtw89_chip_info *chip = rtwdev->chip; 1010 const struct rtw89_page_regs *regs = chip->page_regs; 1011 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1012 u32 val; 1013 int ret; 1014 1015 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1016 if (ret) 1017 return ret; 1018 1019 ret = hfc_pub_cfg_chk(rtwdev); 1020 if (ret) 1021 return ret; 1022 1023 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1024 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1025 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1026 1027 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1028 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1029 1030 return 0; 1031 } 1032 1033 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1034 { 1035 const struct rtw89_chip_info *chip = rtwdev->chip; 1036 const struct rtw89_page_regs *regs = chip->page_regs; 1037 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1038 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1039 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1040 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1041 u32 val; 1042 1043 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1044 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1045 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1046 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1047 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1048 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1049 info->pub_aval = 1050 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1051 B_AX_PUB_AVAL_PG_MASK); 1052 info->wp_aval = 1053 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1054 B_AX_WP_AVAL_PG_MASK); 1055 1056 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1057 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1058 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1059 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1060 prec_cfg->ch011_full_cond = 1061 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1062 prec_cfg->h2c_full_cond = 1063 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1064 prec_cfg->wp_ch07_full_cond = 1065 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1066 prec_cfg->wp_ch811_full_cond = 1067 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1068 1069 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1070 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1071 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1072 1073 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1074 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1075 1076 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1077 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1078 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1079 1080 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1081 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1082 1083 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1084 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1085 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1086 } 1087 1088 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1089 { 1090 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1091 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1092 int ret; 1093 1094 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1095 if (ret) 1096 return ret; 1097 1098 mac->hfc_get_mix_info(rtwdev); 1099 1100 ret = hfc_pub_info_chk(rtwdev); 1101 if (param->en && ret) 1102 return ret; 1103 1104 return 0; 1105 } 1106 1107 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1108 { 1109 const struct rtw89_chip_info *chip = rtwdev->chip; 1110 const struct rtw89_page_regs *regs = chip->page_regs; 1111 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1112 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1113 u32 val; 1114 1115 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1116 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1117 1118 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1119 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1120 prec_cfg->h2c_full_cond); 1121 } 1122 1123 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1124 { 1125 const struct rtw89_chip_info *chip = rtwdev->chip; 1126 const struct rtw89_page_regs *regs = chip->page_regs; 1127 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1128 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1129 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1130 u32 val; 1131 1132 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1133 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1134 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1135 1136 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1137 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1138 1139 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1140 B_AX_PREC_PAGE_WP_CH07_MASK) | 1141 u32_encode_bits(prec_cfg->wp_ch811_prec, 1142 B_AX_PREC_PAGE_WP_CH811_MASK); 1143 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1144 1145 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1146 param->mode, B_AX_HCI_FC_MODE_MASK); 1147 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1148 B_AX_HCI_FC_WD_FULL_COND_MASK); 1149 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1150 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1151 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1152 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1153 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1154 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1155 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1156 } 1157 1158 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1159 { 1160 const struct rtw89_chip_info *chip = rtwdev->chip; 1161 const struct rtw89_page_regs *regs = chip->page_regs; 1162 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1163 u32 val; 1164 1165 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1166 param->en = en; 1167 param->h2c_en = h2c_en; 1168 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1169 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1170 (val & ~B_AX_HCI_FC_CH12_EN); 1171 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1172 } 1173 1174 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1175 { 1176 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1177 const struct rtw89_chip_info *chip = rtwdev->chip; 1178 u32 dma_ch_mask = chip->dma_ch_mask; 1179 u8 ch; 1180 u32 ret = 0; 1181 1182 if (reset) 1183 ret = hfc_reset_param(rtwdev); 1184 if (ret) 1185 return ret; 1186 1187 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1188 if (ret) 1189 return ret; 1190 1191 mac->hfc_func_en(rtwdev, false, false); 1192 1193 if (!en && h2c_en) { 1194 mac->hfc_h2c_cfg(rtwdev); 1195 mac->hfc_func_en(rtwdev, en, h2c_en); 1196 return ret; 1197 } 1198 1199 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1200 if (dma_ch_mask & BIT(ch)) 1201 continue; 1202 ret = hfc_ch_ctrl(rtwdev, ch); 1203 if (ret) 1204 return ret; 1205 } 1206 1207 ret = hfc_pub_ctrl(rtwdev); 1208 if (ret) 1209 return ret; 1210 1211 mac->hfc_mix_cfg(rtwdev); 1212 if (en || h2c_en) { 1213 mac->hfc_func_en(rtwdev, en, h2c_en); 1214 udelay(10); 1215 } 1216 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1217 if (dma_ch_mask & BIT(ch)) 1218 continue; 1219 ret = hfc_upd_ch_info(rtwdev, ch); 1220 if (ret) 1221 return ret; 1222 } 1223 ret = hfc_upd_mix_info(rtwdev); 1224 1225 return ret; 1226 } 1227 1228 #define PWR_POLL_CNT 2000 1229 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1230 const struct rtw89_pwr_cfg *cfg) 1231 { 1232 u8 val = 0; 1233 int ret; 1234 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1235 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1236 1237 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1238 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1239 1240 if (!ret) 1241 return 0; 1242 1243 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1244 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1245 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1246 1247 return -EBUSY; 1248 } 1249 1250 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1251 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1252 { 1253 const struct rtw89_pwr_cfg *cur_cfg; 1254 u32 addr; 1255 u8 val; 1256 1257 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1258 if (!(cur_cfg->intf_msk & intf_msk) || 1259 !(cur_cfg->cv_msk & cv_msk)) 1260 continue; 1261 1262 switch (cur_cfg->cmd) { 1263 case PWR_CMD_WRITE: 1264 addr = cur_cfg->addr; 1265 1266 if (cur_cfg->base == PWR_BASE_SDIO) 1267 addr |= SDIO_LOCAL_BASE_ADDR; 1268 1269 val = rtw89_read8(rtwdev, addr); 1270 val &= ~(cur_cfg->msk); 1271 val |= (cur_cfg->val & cur_cfg->msk); 1272 1273 rtw89_write8(rtwdev, addr, val); 1274 break; 1275 case PWR_CMD_POLL: 1276 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1277 return -EBUSY; 1278 break; 1279 case PWR_CMD_DELAY: 1280 if (cur_cfg->val == PWR_DELAY_US) 1281 udelay(cur_cfg->addr); 1282 else 1283 fsleep(cur_cfg->addr * 1000); 1284 break; 1285 default: 1286 return -EINVAL; 1287 } 1288 } 1289 1290 return 0; 1291 } 1292 1293 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1294 const struct rtw89_pwr_cfg * const *cfg_seq) 1295 { 1296 int ret; 1297 1298 for (; *cfg_seq; cfg_seq++) { 1299 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1300 PWR_INTF_MSK_PCIE, *cfg_seq); 1301 if (ret) 1302 return -EBUSY; 1303 } 1304 1305 return 0; 1306 } 1307 1308 static enum rtw89_rpwm_req_pwr_state 1309 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1310 { 1311 enum rtw89_rpwm_req_pwr_state state; 1312 1313 switch (rtwdev->ps_mode) { 1314 case RTW89_PS_MODE_RFOFF: 1315 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1316 break; 1317 case RTW89_PS_MODE_CLK_GATED: 1318 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1319 break; 1320 case RTW89_PS_MODE_PWR_GATED: 1321 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1322 break; 1323 default: 1324 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1325 break; 1326 } 1327 return state; 1328 } 1329 1330 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1331 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1332 bool notify_wake) 1333 { 1334 u16 request; 1335 1336 spin_lock_bh(&rtwdev->rpwm_lock); 1337 1338 request = rtw89_read16(rtwdev, R_AX_RPWM); 1339 request ^= request | PS_RPWM_TOGGLE; 1340 request |= req_pwr_state; 1341 1342 if (notify_wake) { 1343 request |= PS_RPWM_NOTIFY_WAKE; 1344 } else { 1345 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1346 RPWM_SEQ_NUM_MAX; 1347 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1348 rtwdev->mac.rpwm_seq_num); 1349 1350 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1351 request |= PS_RPWM_ACK; 1352 } 1353 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1354 1355 spin_unlock_bh(&rtwdev->rpwm_lock); 1356 } 1357 1358 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1359 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1360 { 1361 bool request_deep_mode; 1362 bool in_deep_mode; 1363 u8 rpwm_req_num; 1364 u8 cpwm_rsp_seq; 1365 u8 cpwm_seq; 1366 u8 cpwm_status; 1367 1368 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1369 request_deep_mode = true; 1370 else 1371 request_deep_mode = false; 1372 1373 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1374 in_deep_mode = true; 1375 else 1376 in_deep_mode = false; 1377 1378 if (request_deep_mode != in_deep_mode) 1379 return -EPERM; 1380 1381 if (request_deep_mode) 1382 return 0; 1383 1384 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1385 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1386 PS_CPWM_RSP_SEQ_NUM); 1387 1388 if (rpwm_req_num != cpwm_rsp_seq) 1389 return -EPERM; 1390 1391 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1392 CPWM_SEQ_NUM_MAX; 1393 1394 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1395 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1396 return -EPERM; 1397 1398 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1399 if (cpwm_status != req_pwr_state) 1400 return -EPERM; 1401 1402 return 0; 1403 } 1404 1405 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1406 { 1407 enum rtw89_rpwm_req_pwr_state state; 1408 unsigned long delay = enter ? 10 : 150; 1409 int ret; 1410 int i; 1411 1412 if (enter) 1413 state = rtw89_mac_get_req_pwr_state(rtwdev); 1414 else 1415 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1416 1417 for (i = 0; i < RPWM_TRY_CNT; i++) { 1418 rtw89_mac_send_rpwm(rtwdev, state, false); 1419 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1420 !ret, delay, 15000, false, 1421 rtwdev, state); 1422 if (!ret) 1423 break; 1424 1425 if (i == RPWM_TRY_CNT - 1) 1426 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1427 enter ? "entering" : "leaving"); 1428 else 1429 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1430 "%d time firmware failed to ack for %s ps mode\n", 1431 i + 1, enter ? "entering" : "leaving"); 1432 } 1433 } 1434 1435 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1436 { 1437 enum rtw89_rpwm_req_pwr_state state; 1438 1439 state = rtw89_mac_get_req_pwr_state(rtwdev); 1440 rtw89_mac_send_rpwm(rtwdev, state, true); 1441 } 1442 1443 static void rtw89_mac_power_switch_boot_mode(struct rtw89_dev *rtwdev) 1444 { 1445 u32 boot_mode; 1446 1447 if (rtwdev->hci.type != RTW89_HCI_TYPE_USB) 1448 return; 1449 1450 boot_mode = rtw89_read32_mask(rtwdev, R_AX_GPIO_MUXCFG, B_AX_BOOT_MODE); 1451 if (!boot_mode) 1452 return; 1453 1454 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 1455 rtw89_write32_clr(rtwdev, R_AX_SYS_STATUS1, B_AX_AUTO_WLPON); 1456 rtw89_write32_clr(rtwdev, R_AX_GPIO_MUXCFG, B_AX_BOOT_MODE); 1457 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); 1458 } 1459 1460 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1461 { 1462 #define PWR_ACT 1 1463 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1464 const struct rtw89_chip_info *chip = rtwdev->chip; 1465 const struct rtw89_pwr_cfg * const *cfg_seq; 1466 int (*cfg_func)(struct rtw89_dev *rtwdev); 1467 int ret; 1468 u8 val; 1469 1470 rtw89_mac_power_switch_boot_mode(rtwdev); 1471 1472 if (on) { 1473 cfg_seq = chip->pwr_on_seq; 1474 cfg_func = chip->ops->pwr_on_func; 1475 } else { 1476 cfg_seq = chip->pwr_off_seq; 1477 cfg_func = chip->ops->pwr_off_func; 1478 } 1479 1480 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1481 __rtw89_leave_ps_mode(rtwdev); 1482 1483 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1484 if (on && val == PWR_ACT) { 1485 rtw89_err(rtwdev, "MAC has already powered on\n"); 1486 return -EBUSY; 1487 } 1488 1489 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1490 if (ret) 1491 return ret; 1492 1493 if (on) { 1494 if (!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags)) 1495 mac->efuse_read_fw_secure(rtwdev); 1496 1497 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1498 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1499 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1500 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1501 } else { 1502 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1503 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1504 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1505 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1506 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1507 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1508 rtw89_set_entity_state(rtwdev, RTW89_PHY_0, false); 1509 rtw89_set_entity_state(rtwdev, RTW89_PHY_1, false); 1510 } 1511 1512 return 0; 1513 #undef PWR_ACT 1514 } 1515 1516 int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev) 1517 { 1518 int ret; 1519 1520 ret = rtw89_mac_power_switch(rtwdev, true); 1521 if (ret) { 1522 rtw89_mac_power_switch(rtwdev, false); 1523 ret = rtw89_mac_power_switch(rtwdev, true); 1524 if (ret) 1525 return ret; 1526 } 1527 1528 return 0; 1529 } 1530 1531 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1532 { 1533 rtw89_mac_power_switch(rtwdev, false); 1534 } 1535 1536 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1537 { 1538 u32 func_en = 0; 1539 u32 ck_en = 0; 1540 u32 c1pc_en = 0; 1541 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1542 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1543 1544 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1545 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1546 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1547 B_AX_CMAC_CRPRT; 1548 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1549 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1550 B_AX_RMAC_CKEN; 1551 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1552 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1553 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1554 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1555 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1556 1557 if (en) { 1558 if (mac_idx == RTW89_MAC_1) { 1559 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1560 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1561 B_AX_R_SYM_ISO_CMAC12PP); 1562 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1563 B_AX_CMAC1_FEN); 1564 } 1565 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1566 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1567 } else { 1568 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1569 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1570 if (mac_idx == RTW89_MAC_1) { 1571 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1572 B_AX_CMAC1_FEN); 1573 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1574 B_AX_R_SYM_ISO_CMAC12PP); 1575 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1576 } 1577 } 1578 1579 return 0; 1580 } 1581 1582 static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1583 { 1584 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1585 u32 val32; 1586 1587 if (chip_id == RTL8852C) 1588 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1589 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1590 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1591 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1592 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1593 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1594 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1595 else 1596 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1597 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1598 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1599 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1600 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1601 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1602 B_AX_DMAC_CRPRT); 1603 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1604 1605 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1606 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1607 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1608 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1609 if (chip_id == RTL8852BT) 1610 val32 |= B_AX_AXIDMA_CLK_EN; 1611 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1612 1613 return 0; 1614 } 1615 1616 static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1617 { 1618 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1619 1620 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 1621 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1622 B_AX_OCP_L1_MASK); 1623 1624 return 0; 1625 } 1626 1627 static int sys_init_ax(struct rtw89_dev *rtwdev) 1628 { 1629 int ret; 1630 1631 ret = dmac_func_en_ax(rtwdev); 1632 if (ret) 1633 return ret; 1634 1635 ret = cmac_func_en_ax(rtwdev, 0, true); 1636 if (ret) 1637 return ret; 1638 1639 ret = chip_func_en_ax(rtwdev); 1640 if (ret) 1641 return ret; 1642 1643 return ret; 1644 } 1645 1646 const struct rtw89_mac_size_set rtw89_mac_size = { 1647 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1648 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0}, 1649 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0}, 1650 /* PCIE 64 */ 1651 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1652 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1653 /* DLFW */ 1654 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1655 .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1656 /* PCIE 64 */ 1657 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1658 /* 8852B PCIE SCC */ 1659 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1660 /* DLFW */ 1661 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1662 /* 8852C DLFW */ 1663 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1664 /* 8852C PCIE SCC */ 1665 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1666 .wde_size23 = {RTW89_WDE_PG_64, 1022, 2,}, 1667 /* 8852B USB2.0/USB3.0 SCC */ 1668 .wde_size25 = {RTW89_WDE_PG_64, 162, 94,}, 1669 /* PCIE */ 1670 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1671 .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1672 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1673 /* DLFW */ 1674 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1675 /* PCIE 64 */ 1676 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1677 /* DLFW */ 1678 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1679 .ple_size9 = {RTW89_PLE_PG_128, 2288, 16,}, 1680 /* 8852C DLFW */ 1681 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1682 /* 8852C PCIE SCC */ 1683 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1684 /* 8852B USB2.0 SCC */ 1685 .ple_size32 = {RTW89_PLE_PG_128, 620, 20,}, 1686 /* 8852B USB3.0 SCC */ 1687 .ple_size33 = {RTW89_PLE_PG_128, 632, 8,}, 1688 /* PCIE 64 */ 1689 .wde_qt0 = {3792, 196, 0, 107,}, 1690 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1691 /* DLFW */ 1692 .wde_qt4 = {0, 0, 0, 0,}, 1693 /* PCIE 64 */ 1694 .wde_qt6 = {448, 48, 0, 16,}, 1695 /* 8852B PCIE SCC */ 1696 .wde_qt7 = {446, 48, 0, 16,}, 1697 /* 8852C DLFW */ 1698 .wde_qt17 = {0, 0, 0, 0,}, 1699 /* 8852C PCIE SCC */ 1700 .wde_qt18 = {3228, 60, 0, 40,}, 1701 .wde_qt23 = {958, 48, 0, 16,}, 1702 /* 8852B USB2.0/USB3.0 SCC */ 1703 .wde_qt25 = {152, 2, 0, 8,}, 1704 .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 1705 .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1706 /* PCIE SCC */ 1707 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1708 /* PCIE SCC */ 1709 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1710 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1711 /* DLFW */ 1712 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1713 /* PCIE 64 */ 1714 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1715 /* DLFW 52C */ 1716 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1717 /* DLFW 52C */ 1718 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1719 /* 8852C PCIE SCC */ 1720 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1721 /* 8852C PCIE SCC */ 1722 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1723 .ple_qt57 = {147, 0, 16, 20, 13, 13, 178, 0, 32, 14, 8, 0,}, 1724 /* PCIE 64 */ 1725 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1726 .ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,}, 1727 /* USB2.0 52B SCC */ 1728 .ple_qt72 = {130, 0, 16, 48, 4, 13, 322, 0, 32, 14, 8, 0, 0,}, 1729 /* USB2.0 52B 92K */ 1730 .ple_qt73 = {130, 0, 32, 48, 37, 13, 355, 0, 65, 14, 24, 0, 0,}, 1731 /* USB3.0 52B 92K */ 1732 .ple_qt74 = {286, 0, 16, 48, 4, 13, 178, 0, 32, 14, 8, 0, 0,}, 1733 .ple_qt75 = {286, 0, 32, 48, 37, 13, 211, 0, 65, 14, 24, 0, 0,}, 1734 /* 8852A PCIE WOW */ 1735 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1736 /* 8852B PCIE WOW */ 1737 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1738 /* 8852BT PCIE WOW */ 1739 .ple_qt_52bt_wow = {147, 0, 32, 20, 1860, 13, 1929, 0, 1879, 14, 24, 0,}, 1740 /* 8851B PCIE WOW */ 1741 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1742 .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1743 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1744 .rsvd0_size0 = {212992, 0,}, 1745 .rsvd1_size0 = {587776, 2048,}, 1746 }; 1747 EXPORT_SYMBOL(rtw89_mac_size); 1748 1749 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1750 enum rtw89_qta_mode mode) 1751 { 1752 struct rtw89_mac_info *mac = &rtwdev->mac; 1753 const struct rtw89_dle_mem *cfg, *cfgs; 1754 1755 cfgs = rtwdev->chip->dle_mem[rtwdev->hci.dle_type]; 1756 if (!cfgs) 1757 return NULL; 1758 1759 cfg = &cfgs[mode]; 1760 if (cfg->mode != mode) { 1761 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1762 return NULL; 1763 } 1764 1765 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1766 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1767 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1768 mac->dle_info.qta_mode = mode; 1769 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1770 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1771 1772 return cfg; 1773 } 1774 1775 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1776 enum rtw89_mac_dle_rsvd_qt_type type, 1777 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1778 { 1779 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1780 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1781 1782 switch (type) { 1783 case DLE_RSVD_QT_MPDU_INFO: 1784 cfg->pktid = dle_info->ple_free_pg; 1785 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1786 break; 1787 case DLE_RSVD_QT_B0_CSI: 1788 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1789 cfg->pg_num = rsvd_qt->b0_csi; 1790 break; 1791 case DLE_RSVD_QT_B1_CSI: 1792 cfg->pktid = dle_info->ple_free_pg + 1793 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1794 cfg->pg_num = rsvd_qt->b1_csi; 1795 break; 1796 case DLE_RSVD_QT_B0_LMR: 1797 cfg->pktid = dle_info->ple_free_pg + 1798 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1799 cfg->pg_num = rsvd_qt->b0_lmr; 1800 break; 1801 case DLE_RSVD_QT_B1_LMR: 1802 cfg->pktid = dle_info->ple_free_pg + 1803 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1804 rsvd_qt->b0_lmr; 1805 cfg->pg_num = rsvd_qt->b1_lmr; 1806 break; 1807 case DLE_RSVD_QT_B0_FTM: 1808 cfg->pktid = dle_info->ple_free_pg + 1809 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1810 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1811 cfg->pg_num = rsvd_qt->b0_ftm; 1812 break; 1813 case DLE_RSVD_QT_B1_FTM: 1814 cfg->pktid = dle_info->ple_free_pg + 1815 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1816 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1817 cfg->pg_num = rsvd_qt->b1_ftm; 1818 break; 1819 default: 1820 return -EINVAL; 1821 } 1822 1823 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1824 1825 return 0; 1826 } 1827 1828 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1829 { 1830 struct rtw89_mac_dle_dfi_qempty qempty; 1831 u32 grpnum, qtmp, val32, msk32; 1832 int i, j, ret; 1833 1834 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1835 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1836 1837 for (i = 0; i < grpnum; i++) { 1838 qempty.grpsel = i; 1839 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1840 if (ret) { 1841 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1842 return false; 1843 } 1844 qtmp = qempty.qempty; 1845 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1846 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 1847 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1848 return false; 1849 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1850 } 1851 } 1852 1853 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1854 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1855 if (ret) { 1856 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1857 return false; 1858 } 1859 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1860 if ((qempty.qempty & msk32) != msk32) 1861 return false; 1862 1863 if (rtwdev->dbcc_en) { 1864 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1865 if ((qempty.qempty & msk32) != msk32) 1866 return false; 1867 } 1868 1869 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1870 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1871 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1872 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1873 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1874 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1875 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1876 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1877 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1878 1879 return (val32 & msk32) == msk32; 1880 } 1881 1882 static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1883 { 1884 const struct rtw89_dle_size *wde = cfg->wde_size; 1885 const struct rtw89_dle_size *ple = cfg->ple_size; 1886 u32 used; 1887 1888 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1889 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1890 1891 if (cfg->rsvd0_size && cfg->rsvd1_size) { 1892 used += cfg->rsvd0_size->size; 1893 used += cfg->rsvd1_size->size; 1894 } 1895 1896 return used; 1897 } 1898 1899 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1900 enum rtw89_qta_mode mode) 1901 { 1902 u32 size = rtwdev->chip->fifo_size; 1903 1904 if (mode == RTW89_QTA_SCC) 1905 size -= rtwdev->chip->dle_scc_rsvd_size; 1906 1907 return size; 1908 } 1909 1910 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 1911 { 1912 if (enable) 1913 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1914 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1915 else 1916 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1917 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1918 } 1919 1920 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 1921 { 1922 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1923 1924 if (enable) { 1925 if (rtwdev->chip->chip_id == RTL8851B) 1926 val |= B_AX_AXIDMA_CLK_EN; 1927 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1928 } else { 1929 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1930 } 1931 } 1932 1933 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1934 { 1935 const struct rtw89_dle_size *size_cfg; 1936 u32 val; 1937 u8 bound = 0; 1938 1939 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1940 size_cfg = cfg->wde_size; 1941 1942 switch (size_cfg->pge_size) { 1943 default: 1944 case RTW89_WDE_PG_64: 1945 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1946 B_AX_WDE_PAGE_SEL_MASK); 1947 break; 1948 case RTW89_WDE_PG_128: 1949 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1950 B_AX_WDE_PAGE_SEL_MASK); 1951 break; 1952 case RTW89_WDE_PG_256: 1953 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1954 return -EINVAL; 1955 } 1956 1957 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1958 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1959 B_AX_WDE_FREE_PAGE_NUM_MASK); 1960 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1961 1962 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1963 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1964 * size_cfg->pge_size / DLE_BOUND_UNIT; 1965 size_cfg = cfg->ple_size; 1966 1967 switch (size_cfg->pge_size) { 1968 default: 1969 case RTW89_PLE_PG_64: 1970 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1971 return -EINVAL; 1972 case RTW89_PLE_PG_128: 1973 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1974 B_AX_PLE_PAGE_SEL_MASK); 1975 break; 1976 case RTW89_PLE_PG_256: 1977 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1978 B_AX_PLE_PAGE_SEL_MASK); 1979 break; 1980 } 1981 1982 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1983 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1984 B_AX_PLE_FREE_PAGE_NUM_MASK); 1985 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1986 1987 return 0; 1988 } 1989 1990 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 1991 { 1992 u32 reg, mask; 1993 u32 ini; 1994 1995 if (wde_or_ple) { 1996 reg = R_AX_WDE_INI_STATUS; 1997 mask = WDE_MGN_INI_RDY; 1998 } else { 1999 reg = R_AX_PLE_INI_STATUS; 2000 mask = PLE_MGN_INI_RDY; 2001 } 2002 2003 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 2004 2000, false, rtwdev, reg); 2005 } 2006 2007 #define INVALID_QT_WCPU U16_MAX 2008 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 2009 do { \ 2010 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 2011 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 2012 rtw89_write32(rtwdev, \ 2013 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 2014 val); \ 2015 } while (0) 2016 #define SET_QUOTA(_x, _module, _idx) \ 2017 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 2018 2019 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 2020 const struct rtw89_wde_quota *min_cfg, 2021 const struct rtw89_wde_quota *max_cfg, 2022 u16 ext_wde_min_qt_wcpu) 2023 { 2024 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 2025 ext_wde_min_qt_wcpu : min_cfg->wcpu; 2026 u32 val; 2027 2028 SET_QUOTA(hif, WDE, 0); 2029 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 2030 SET_QUOTA(pkt_in, WDE, 3); 2031 SET_QUOTA(cpu_io, WDE, 4); 2032 } 2033 2034 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 2035 const struct rtw89_ple_quota *min_cfg, 2036 const struct rtw89_ple_quota *max_cfg) 2037 { 2038 u32 val; 2039 2040 SET_QUOTA(cma0_tx, PLE, 0); 2041 SET_QUOTA(cma1_tx, PLE, 1); 2042 SET_QUOTA(c2h, PLE, 2); 2043 SET_QUOTA(h2c, PLE, 3); 2044 SET_QUOTA(wcpu, PLE, 4); 2045 SET_QUOTA(mpdu_proc, PLE, 5); 2046 SET_QUOTA(cma0_dma, PLE, 6); 2047 SET_QUOTA(cma1_dma, PLE, 7); 2048 SET_QUOTA(bb_rpt, PLE, 8); 2049 SET_QUOTA(wd_rel, PLE, 9); 2050 SET_QUOTA(cpu_io, PLE, 10); 2051 if (rtwdev->chip->chip_id == RTL8852C) 2052 SET_QUOTA(tx_rpt, PLE, 11); 2053 } 2054 2055 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 2056 { 2057 const struct rtw89_ple_quota *min_cfg, *max_cfg; 2058 const struct rtw89_dle_mem *cfg; 2059 u32 val; 2060 2061 if (rtwdev->chip->chip_id == RTL8852C) 2062 return 0; 2063 2064 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2065 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2066 return -EINVAL; 2067 } 2068 2069 if (wow) 2070 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2071 else 2072 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2073 if (!cfg) { 2074 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2075 return -EINVAL; 2076 } 2077 2078 min_cfg = cfg->ple_min_qt; 2079 max_cfg = cfg->ple_max_qt; 2080 SET_QUOTA(cma0_dma, PLE, 6); 2081 SET_QUOTA(cma1_dma, PLE, 7); 2082 2083 return 0; 2084 } 2085 #undef SET_QUOTA 2086 2087 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2088 { 2089 const struct rtw89_chip_info *chip = rtwdev->chip; 2090 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2091 2092 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2093 return; 2094 2095 /* 8852C enable B_AX_UC_MGNT_DEC by default */ 2096 if (chip->chip_id == RTL8852C) 2097 msk32 = B_AX_BMC_MGNT_DEC; 2098 2099 if (enable) 2100 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2101 else 2102 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2103 } 2104 2105 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2106 const struct rtw89_dle_mem *cfg, 2107 u16 ext_wde_min_qt_wcpu) 2108 { 2109 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2110 2111 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2112 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2113 } 2114 2115 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2116 enum rtw89_qta_mode ext_mode) 2117 { 2118 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2119 const struct rtw89_dle_mem *cfg, *ext_cfg; 2120 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2121 int ret; 2122 2123 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2124 if (ret) 2125 return ret; 2126 2127 cfg = get_dle_mem_cfg(rtwdev, mode); 2128 if (!cfg) { 2129 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2130 ret = -EINVAL; 2131 goto error; 2132 } 2133 2134 if (mode == RTW89_QTA_DLFW) { 2135 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2136 if (!ext_cfg) { 2137 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2138 ext_mode); 2139 ret = -EINVAL; 2140 goto error; 2141 } 2142 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2143 } 2144 2145 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2146 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2147 ret = -EINVAL; 2148 goto error; 2149 } 2150 2151 mac->dle_func_en(rtwdev, false); 2152 mac->dle_clk_en(rtwdev, true); 2153 2154 ret = mac->dle_mix_cfg(rtwdev, cfg); 2155 if (ret) { 2156 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2157 goto error; 2158 } 2159 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2160 2161 mac->dle_func_en(rtwdev, true); 2162 2163 ret = mac->chk_dle_rdy(rtwdev, true); 2164 if (ret) { 2165 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2166 return ret; 2167 } 2168 2169 ret = mac->chk_dle_rdy(rtwdev, false); 2170 if (ret) { 2171 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2172 return ret; 2173 } 2174 2175 return 0; 2176 error: 2177 mac->dle_func_en(rtwdev, false); 2178 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2179 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2180 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2181 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2182 2183 return ret; 2184 } 2185 2186 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2187 enum rtw89_qta_mode mode) 2188 { 2189 u32 reg, max_preld_size, min_rsvd_size; 2190 2191 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2192 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2193 reg = mac_idx == RTW89_MAC_0 ? 2194 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2195 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2196 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2197 2198 min_rsvd_size = PRELD_AMSDU_SIZE; 2199 reg = mac_idx == RTW89_MAC_0 ? 2200 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2201 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2202 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2203 2204 return 0; 2205 } 2206 2207 static bool is_qta_poh(struct rtw89_dev *rtwdev) 2208 { 2209 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2210 } 2211 2212 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2213 enum rtw89_qta_mode mode) 2214 { 2215 const struct rtw89_chip_info *chip = rtwdev->chip; 2216 2217 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) || 2218 !is_qta_poh(rtwdev)) 2219 return 0; 2220 2221 return preload_init_set(rtwdev, mac_idx, mode); 2222 } 2223 2224 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2225 { 2226 u32 msk32; 2227 u32 val32; 2228 2229 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2230 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2231 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2232 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2233 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2234 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2235 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2236 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2237 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2238 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2239 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2240 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2241 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2242 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2243 2244 if ((val32 & msk32) == msk32) 2245 return true; 2246 2247 return false; 2248 } 2249 2250 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2251 { 2252 const struct rtw89_chip_info *chip = rtwdev->chip; 2253 2254 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2255 return; 2256 2257 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2258 SS2F_PATH_WLCPU); 2259 } 2260 2261 static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2262 { 2263 u32 p_val; 2264 u8 val; 2265 int ret; 2266 2267 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2268 if (ret) 2269 return ret; 2270 2271 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2272 val |= B_AX_SS_EN; 2273 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2274 2275 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2276 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2277 if (ret) { 2278 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2279 return ret; 2280 } 2281 2282 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2283 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2284 2285 _patch_ss2f_path(rtwdev); 2286 2287 return 0; 2288 } 2289 2290 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2291 { 2292 int ret; 2293 2294 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2295 if (ret) 2296 return ret; 2297 2298 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2299 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2300 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2301 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2302 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2303 2304 return 0; 2305 } 2306 2307 static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2308 { 2309 const struct rtw89_chip_info *chip = rtwdev->chip; 2310 u32 val = 0; 2311 int ret; 2312 2313 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2314 if (ret) 2315 return ret; 2316 2317 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2318 /* init clock */ 2319 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2320 /* init TX encryption */ 2321 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2322 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2323 if (chip->chip_id == RTL8852C) 2324 val |= B_AX_UC_MGNT_DEC; 2325 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2326 chip->chip_id == RTL8851B) 2327 val &= ~B_AX_TX_PARTIAL_MODE; 2328 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2329 2330 /* init MIC ICV append */ 2331 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2332 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2333 2334 /* option init */ 2335 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2336 2337 if (chip->chip_id == RTL8852C) 2338 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2339 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2340 2341 return 0; 2342 } 2343 2344 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2345 { 2346 int ret; 2347 2348 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2349 if (ret) { 2350 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2351 return ret; 2352 } 2353 2354 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2355 if (ret) { 2356 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2357 return ret; 2358 } 2359 2360 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2361 if (ret) { 2362 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2363 return ret; 2364 } 2365 2366 ret = sta_sch_init_ax(rtwdev); 2367 if (ret) { 2368 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2369 return ret; 2370 } 2371 2372 ret = mpdu_proc_init_ax(rtwdev); 2373 if (ret) { 2374 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2375 return ret; 2376 } 2377 2378 ret = sec_eng_init_ax(rtwdev); 2379 if (ret) { 2380 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2381 return ret; 2382 } 2383 2384 return ret; 2385 } 2386 2387 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2388 { 2389 u32 val, reg; 2390 u16 p_val; 2391 int ret; 2392 2393 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2394 if (ret) 2395 return ret; 2396 2397 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2398 2399 val = rtw89_read32(rtwdev, reg); 2400 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2401 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2402 rtw89_write32(rtwdev, reg, val); 2403 2404 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2405 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2406 if (ret) { 2407 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2408 return ret; 2409 } 2410 2411 return 0; 2412 } 2413 2414 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2415 { 2416 u32 ret; 2417 u32 reg; 2418 u32 val; 2419 2420 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2421 if (ret) 2422 return ret; 2423 2424 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2425 if (rtwdev->chip->chip_id == RTL8852C) 2426 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2427 SIFS_MACTXEN_T1_V1); 2428 else 2429 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2430 SIFS_MACTXEN_T1); 2431 2432 if (rtw89_is_rtl885xb(rtwdev)) { 2433 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2434 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2435 } 2436 2437 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2438 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2439 2440 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2441 if (rtwdev->chip->chip_id == RTL8852C) { 2442 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2443 B_AX_TX_PARTIAL_MODE); 2444 if (!val) 2445 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2446 SCH_PREBKF_24US); 2447 } else { 2448 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2449 SCH_PREBKF_24US); 2450 } 2451 2452 return 0; 2453 } 2454 2455 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2456 enum rtw89_machdr_frame_type type, 2457 enum rtw89_mac_fwd_target fwd_target, 2458 u8 mac_idx) 2459 { 2460 u32 reg; 2461 u32 val; 2462 2463 switch (fwd_target) { 2464 case RTW89_FWD_DONT_CARE: 2465 val = RX_FLTR_FRAME_DROP; 2466 break; 2467 case RTW89_FWD_TO_HOST: 2468 val = RX_FLTR_FRAME_TO_HOST; 2469 break; 2470 case RTW89_FWD_TO_WLAN_CPU: 2471 val = RX_FLTR_FRAME_TO_WLCPU; 2472 break; 2473 default: 2474 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2475 return -EINVAL; 2476 } 2477 2478 switch (type) { 2479 case RTW89_MGNT: 2480 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2481 break; 2482 case RTW89_CTRL: 2483 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2484 break; 2485 case RTW89_DATA: 2486 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2487 break; 2488 default: 2489 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2490 return -EINVAL; 2491 } 2492 rtw89_write32(rtwdev, reg, val); 2493 2494 return 0; 2495 } 2496 2497 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2498 { 2499 int ret, i; 2500 u32 mac_ftlr, plcp_ftlr; 2501 2502 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2503 if (ret) 2504 return ret; 2505 2506 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2507 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2508 mac_idx); 2509 if (ret) 2510 return ret; 2511 } 2512 mac_ftlr = rtwdev->hal.rx_fltr; 2513 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2514 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2515 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2516 B_AX_HE_SIGB_CRC_CHK; 2517 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2518 mac_ftlr); 2519 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2520 plcp_ftlr); 2521 2522 return 0; 2523 } 2524 2525 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2526 { 2527 u32 reg, val32; 2528 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2529 2530 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2531 B_AX_RSP_CHK_BASIC_NAV; 2532 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2533 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2534 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2535 2536 switch (rtwdev->chip->chip_id) { 2537 case RTL8852A: 2538 case RTL8852B: 2539 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2540 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2541 rtw89_write32(rtwdev, reg, val32); 2542 2543 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2544 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2545 rtw89_write32(rtwdev, reg, val32); 2546 break; 2547 default: 2548 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2549 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2550 rtw89_write32(rtwdev, reg, val32); 2551 2552 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2553 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2554 rtw89_write32(rtwdev, reg, val32); 2555 break; 2556 } 2557 } 2558 2559 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2560 { 2561 u32 val, reg; 2562 int ret; 2563 2564 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2565 if (ret) 2566 return ret; 2567 2568 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2569 val = rtw89_read32(rtwdev, reg); 2570 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2571 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2572 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2573 B_AX_CTN_CHK_INTRA_NAV | 2574 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2575 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2576 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2577 B_AX_CTN_CHK_CCA_P20); 2578 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2579 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2580 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2581 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2582 B_AX_SIFS_CHK_EDCCA); 2583 2584 rtw89_write32(rtwdev, reg, val); 2585 2586 _patch_dis_resp_chk(rtwdev, mac_idx); 2587 2588 return 0; 2589 } 2590 2591 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2592 { 2593 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2594 B_AX_WMAC_TF_UP_NAV_EN | 2595 B_AX_WMAC_NAV_UPPER_EN); 2596 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2597 2598 return 0; 2599 } 2600 2601 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2602 { 2603 u32 reg; 2604 int ret; 2605 2606 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2607 if (ret) 2608 return ret; 2609 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2610 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2611 2612 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2613 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2614 2615 return 0; 2616 } 2617 2618 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2619 { 2620 u32 reg; 2621 int ret; 2622 2623 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2624 if (ret) 2625 return ret; 2626 2627 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2628 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2629 2630 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2631 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2632 2633 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2634 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2635 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2636 2637 return 0; 2638 } 2639 2640 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2641 { 2642 const struct rtw89_chip_info *chip = rtwdev->chip; 2643 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2644 u32 reg, val, sifs; 2645 int ret; 2646 2647 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2648 if (ret) 2649 return ret; 2650 2651 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2652 val = rtw89_read32(rtwdev, reg); 2653 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2654 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2655 2656 switch (rtwdev->chip->chip_id) { 2657 case RTL8852A: 2658 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2659 break; 2660 case RTL8851B: 2661 case RTL8852B: 2662 case RTL8852BT: 2663 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2664 break; 2665 default: 2666 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2667 break; 2668 } 2669 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2670 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2671 rtw89_write32(rtwdev, reg, val); 2672 2673 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2674 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2675 2676 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2677 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2678 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2679 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2680 2681 return 0; 2682 } 2683 2684 static void rst_bacam(struct rtw89_dev *rtwdev) 2685 { 2686 u32 val32; 2687 int ret; 2688 2689 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2690 S_AX_BACAM_RST_ALL); 2691 2692 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2693 1, 1000, false, 2694 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2695 if (ret) 2696 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2697 } 2698 2699 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2700 { 2701 #define TRXCFG_RMAC_CCA_TO 32 2702 #define TRXCFG_RMAC_DATA_TO 15 2703 #define RX_MAX_LEN_UNIT 512 2704 #define PLD_RLS_MAX_PG 127 2705 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2706 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2707 int ret; 2708 u32 reg, rx_max_len, rx_qta; 2709 u16 val; 2710 2711 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2712 if (ret) 2713 return ret; 2714 2715 if (mac_idx == RTW89_MAC_0) 2716 rst_bacam(rtwdev); 2717 2718 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2719 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2720 2721 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2722 val = rtw89_read16(rtwdev, reg); 2723 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2724 B_AX_RX_DLK_DATA_TIME_MASK); 2725 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2726 B_AX_RX_DLK_CCA_TIME_MASK); 2727 if (chip_id == RTL8852BT) 2728 val |= B_AX_RX_DLK_RST_EN; 2729 rtw89_write16(rtwdev, reg, val); 2730 2731 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2732 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2733 2734 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2735 if (mac_idx == RTW89_MAC_0) 2736 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2737 else 2738 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2739 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2740 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2741 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2742 rx_max_len /= RX_MAX_LEN_UNIT; 2743 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2744 2745 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) { 2746 rtw89_write16_mask(rtwdev, 2747 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2748 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2749 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2750 BIT(12)); 2751 } 2752 2753 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2754 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2755 2756 return ret; 2757 } 2758 2759 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2760 { 2761 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2762 u32 val, reg; 2763 int ret; 2764 2765 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2766 if (ret) 2767 return ret; 2768 2769 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2770 val = rtw89_read32(rtwdev, reg); 2771 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2772 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2773 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2774 rtw89_write32(rtwdev, reg, val); 2775 2776 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2777 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2778 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2779 } 2780 2781 return 0; 2782 } 2783 2784 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2785 { 2786 const struct rtw89_dle_mem *cfg; 2787 2788 cfg = get_dle_mem_cfg(rtwdev, mode); 2789 if (!cfg) { 2790 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2791 return false; 2792 } 2793 2794 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2795 } 2796 2797 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2798 { 2799 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2800 u32 val, reg; 2801 int ret; 2802 2803 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2804 if (ret) 2805 return ret; 2806 2807 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2808 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2809 val = rtw89_read32(rtwdev, reg); 2810 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2811 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2812 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2813 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2814 val |= B_AX_HW_CTS2SELF_EN; 2815 rtw89_write32(rtwdev, reg, val); 2816 2817 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2818 val = rtw89_read32(rtwdev, reg); 2819 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2820 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2821 rtw89_write32(rtwdev, reg, val); 2822 } 2823 2824 if (mac_idx == RTW89_MAC_0) { 2825 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2826 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2827 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2828 B_AX_PTCL_TRIGGER_SS_EN_0 | 2829 B_AX_PTCL_TRIGGER_SS_EN_1 | 2830 B_AX_PTCL_TRIGGER_SS_EN_UL); 2831 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2832 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2833 } else if (mac_idx == RTW89_MAC_1) { 2834 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2835 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2836 } 2837 2838 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2839 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_VHT_0, mac_idx); 2840 rtw89_write32_mask(rtwdev, reg, 2841 B_AX_AMPDU_MAX_LEN_VHT_MASK, 0x3FF80); 2842 } 2843 2844 return 0; 2845 } 2846 2847 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2848 { 2849 u32 reg; 2850 int ret; 2851 2852 if (!rtw89_is_rtl885xb(rtwdev)) 2853 return 0; 2854 2855 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2856 if (ret) 2857 return ret; 2858 2859 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2860 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2861 2862 return 0; 2863 } 2864 2865 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2866 { 2867 int ret; 2868 2869 ret = scheduler_init_ax(rtwdev, mac_idx); 2870 if (ret) { 2871 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2872 return ret; 2873 } 2874 2875 ret = addr_cam_init_ax(rtwdev, mac_idx); 2876 if (ret) { 2877 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2878 ret); 2879 return ret; 2880 } 2881 2882 ret = rx_fltr_init_ax(rtwdev, mac_idx); 2883 if (ret) { 2884 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2885 ret); 2886 return ret; 2887 } 2888 2889 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 2890 if (ret) { 2891 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2892 ret); 2893 return ret; 2894 } 2895 2896 ret = nav_ctrl_init_ax(rtwdev); 2897 if (ret) { 2898 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2899 ret); 2900 return ret; 2901 } 2902 2903 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 2904 if (ret) { 2905 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2906 mac_idx, ret); 2907 return ret; 2908 } 2909 2910 ret = tmac_init_ax(rtwdev, mac_idx); 2911 if (ret) { 2912 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2913 return ret; 2914 } 2915 2916 ret = trxptcl_init_ax(rtwdev, mac_idx); 2917 if (ret) { 2918 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2919 return ret; 2920 } 2921 2922 ret = rmac_init_ax(rtwdev, mac_idx); 2923 if (ret) { 2924 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2925 return ret; 2926 } 2927 2928 ret = cmac_com_init_ax(rtwdev, mac_idx); 2929 if (ret) { 2930 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2931 return ret; 2932 } 2933 2934 ret = ptcl_init_ax(rtwdev, mac_idx); 2935 if (ret) { 2936 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2937 return ret; 2938 } 2939 2940 ret = cmac_dma_init_ax(rtwdev, mac_idx); 2941 if (ret) { 2942 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2943 return ret; 2944 } 2945 2946 return ret; 2947 } 2948 2949 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2950 struct rtw89_mac_c2h_info *c2h_info, u8 part_num) 2951 { 2952 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2953 const struct rtw89_chip_info *chip = rtwdev->chip; 2954 struct rtw89_mac_h2c_info h2c_info = {}; 2955 enum rtw89_mac_c2h_type c2h_type; 2956 u8 content_len; 2957 u32 ret; 2958 2959 if (chip->chip_gen == RTW89_CHIP_AX) 2960 content_len = 0; 2961 else 2962 content_len = 2; 2963 2964 switch (part_num) { 2965 case 0: 2966 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP; 2967 break; 2968 case 1: 2969 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1; 2970 break; 2971 default: 2972 return -EINVAL; 2973 } 2974 2975 mac->cnv_efuse_state(rtwdev, false); 2976 2977 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2978 h2c_info.content_len = content_len; 2979 h2c_info.u.hdr.w0 = u32_encode_bits(part_num, RTW89_H2CREG_GET_FEATURE_PART_NUM); 2980 2981 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2982 if (ret) 2983 goto out; 2984 2985 if (c2h_info->id != c2h_type) 2986 ret = -EINVAL; 2987 2988 out: 2989 mac->cnv_efuse_state(rtwdev, true); 2990 2991 return ret; 2992 } 2993 2994 static int rtw89_mac_setup_phycap_part0(struct rtw89_dev *rtwdev) 2995 { 2996 const struct rtw89_chip_info *chip = rtwdev->chip; 2997 const struct rtw89_c2hreg_phycap *phycap; 2998 struct rtw89_efuse *efuse = &rtwdev->efuse; 2999 struct rtw89_mac_c2h_info c2h_info = {}; 3000 struct rtw89_hal *hal = &rtwdev->hal; 3001 u8 tx_nss; 3002 u8 rx_nss; 3003 u8 tx_ant; 3004 u8 rx_ant; 3005 int ret; 3006 3007 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 0); 3008 if (ret) 3009 return ret; 3010 3011 phycap = &c2h_info.u.phycap; 3012 3013 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 3014 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 3015 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 3016 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 3017 3018 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 3019 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 3020 3021 if (tx_ant == 1) 3022 hal->antenna_tx = RF_B; 3023 if (rx_ant == 1) 3024 hal->antenna_rx = RF_B; 3025 3026 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 3027 hal->antenna_tx = RF_B; 3028 hal->tx_path_diversity = true; 3029 } 3030 3031 if (chip->rf_path_num == 1) { 3032 hal->antenna_tx = RF_A; 3033 hal->antenna_rx = RF_A; 3034 if ((efuse->rfe_type % 3) == 2) 3035 hal->ant_diversity = true; 3036 } 3037 3038 rtw89_debug(rtwdev, RTW89_DBG_FW, 3039 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 3040 hal->tx_nss, tx_nss, chip->tx_nss, 3041 hal->rx_nss, rx_nss, chip->rx_nss); 3042 rtw89_debug(rtwdev, RTW89_DBG_FW, 3043 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 3044 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 3045 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 3046 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 3047 3048 return 0; 3049 } 3050 3051 static int rtw89_mac_setup_phycap_part1(struct rtw89_dev *rtwdev) 3052 { 3053 const struct rtw89_chip_variant *variant = rtwdev->variant; 3054 const struct rtw89_c2hreg_phycap *phycap; 3055 struct rtw89_mac_c2h_info c2h_info = {}; 3056 struct rtw89_hal *hal = &rtwdev->hal; 3057 u8 qam_raw, qam; 3058 int ret; 3059 3060 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 1); 3061 if (ret) 3062 return ret; 3063 3064 phycap = &c2h_info.u.phycap; 3065 3066 qam_raw = u32_get_bits(phycap->w2, RTW89_C2HREG_PHYCAP_P1_W2_QAM); 3067 3068 switch (qam_raw) { 3069 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_256: 3070 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024: 3071 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096: 3072 qam = qam_raw; 3073 break; 3074 default: 3075 qam = RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096; 3076 break; 3077 } 3078 3079 if ((variant && variant->no_mcs_12_13) || 3080 qam <= RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024) 3081 hal->no_mcs_12_13 = true; 3082 3083 rtw89_debug(rtwdev, RTW89_DBG_FW, "phycap qam=%d/%d no_mcs_12_13=%d\n", 3084 qam_raw, qam, hal->no_mcs_12_13); 3085 3086 return 0; 3087 } 3088 3089 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 3090 { 3091 const struct rtw89_chip_info *chip = rtwdev->chip; 3092 int ret; 3093 3094 ret = rtw89_mac_setup_phycap_part0(rtwdev); 3095 if (ret) 3096 return ret; 3097 3098 if (chip->chip_gen == RTW89_CHIP_AX || 3099 RTW89_CHK_FW_FEATURE(NO_PHYCAP_P1, &rtwdev->fw)) 3100 return 0; 3101 3102 return rtw89_mac_setup_phycap_part1(rtwdev); 3103 } 3104 3105 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 3106 u16 tx_en_u16, u16 mask_u16) 3107 { 3108 u32 ret; 3109 struct rtw89_mac_c2h_info c2h_info = {0}; 3110 struct rtw89_mac_h2c_info h2c_info = {0}; 3111 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 3112 3113 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 3114 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 3115 3116 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 3117 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 3118 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 3119 3120 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 3121 if (ret) 3122 return ret; 3123 3124 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 3125 return -EINVAL; 3126 3127 return 0; 3128 } 3129 3130 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 3131 u16 tx_en, u16 tx_en_mask) 3132 { 3133 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 3134 u16 val; 3135 int ret; 3136 3137 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3138 if (ret) 3139 return ret; 3140 3141 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3142 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 3143 tx_en, tx_en_mask); 3144 3145 val = rtw89_read16(rtwdev, reg); 3146 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3147 rtw89_write16(rtwdev, reg, val); 3148 3149 return 0; 3150 } 3151 3152 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3153 u32 tx_en, u32 tx_en_mask) 3154 { 3155 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3156 u32 val; 3157 int ret; 3158 3159 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3160 if (ret) 3161 return ret; 3162 3163 val = rtw89_read32(rtwdev, reg); 3164 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3165 rtw89_write32(rtwdev, reg, val); 3166 3167 return 0; 3168 } 3169 3170 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3171 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3172 { 3173 int ret; 3174 3175 *tx_en = rtw89_read16(rtwdev, 3176 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3177 3178 switch (sel) { 3179 case RTW89_SCH_TX_SEL_ALL: 3180 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3181 B_AX_CTN_TXEN_ALL_MASK); 3182 if (ret) 3183 return ret; 3184 break; 3185 case RTW89_SCH_TX_SEL_HIQ: 3186 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3187 0, B_AX_CTN_TXEN_HGQ); 3188 if (ret) 3189 return ret; 3190 break; 3191 case RTW89_SCH_TX_SEL_MG0: 3192 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3193 0, B_AX_CTN_TXEN_MGQ); 3194 if (ret) 3195 return ret; 3196 break; 3197 case RTW89_SCH_TX_SEL_MACID: 3198 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3199 B_AX_CTN_TXEN_ALL_MASK); 3200 if (ret) 3201 return ret; 3202 break; 3203 default: 3204 return 0; 3205 } 3206 3207 return 0; 3208 } 3209 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3210 3211 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3212 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3213 { 3214 int ret; 3215 3216 *tx_en = rtw89_read32(rtwdev, 3217 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3218 3219 switch (sel) { 3220 case RTW89_SCH_TX_SEL_ALL: 3221 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3222 B_AX_CTN_TXEN_ALL_MASK_V1); 3223 if (ret) 3224 return ret; 3225 break; 3226 case RTW89_SCH_TX_SEL_HIQ: 3227 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3228 0, B_AX_CTN_TXEN_HGQ); 3229 if (ret) 3230 return ret; 3231 break; 3232 case RTW89_SCH_TX_SEL_MG0: 3233 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3234 0, B_AX_CTN_TXEN_MGQ); 3235 if (ret) 3236 return ret; 3237 break; 3238 case RTW89_SCH_TX_SEL_MACID: 3239 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3240 B_AX_CTN_TXEN_ALL_MASK_V1); 3241 if (ret) 3242 return ret; 3243 break; 3244 default: 3245 return 0; 3246 } 3247 3248 return 0; 3249 } 3250 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3251 3252 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3253 { 3254 int ret; 3255 3256 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3257 if (ret) 3258 return ret; 3259 3260 return 0; 3261 } 3262 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3263 3264 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3265 { 3266 int ret; 3267 3268 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3269 B_AX_CTN_TXEN_ALL_MASK_V1); 3270 if (ret) 3271 return ret; 3272 3273 return 0; 3274 } 3275 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3276 3277 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3278 { 3279 u32 val, reg; 3280 int ret; 3281 3282 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3283 val = buf_len; 3284 val |= B_AX_WD_BUF_REQ_EXEC; 3285 rtw89_write32(rtwdev, reg, val); 3286 3287 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3288 3289 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3290 1, 2000, false, rtwdev, reg); 3291 if (ret) 3292 return ret; 3293 3294 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3295 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3296 return -ENOENT; 3297 3298 return 0; 3299 } 3300 3301 static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3302 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3303 { 3304 u32 val, cmd_type, reg; 3305 int ret; 3306 3307 cmd_type = ctrl_para->cmd_type; 3308 3309 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3310 val = 0; 3311 val = u32_replace_bits(val, ctrl_para->start_pktid, 3312 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3313 val = u32_replace_bits(val, ctrl_para->end_pktid, 3314 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3315 rtw89_write32(rtwdev, reg, val); 3316 3317 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3318 val = 0; 3319 val = u32_replace_bits(val, ctrl_para->src_pid, 3320 B_AX_CPUQ_OP_SRC_PID_MASK); 3321 val = u32_replace_bits(val, ctrl_para->src_qid, 3322 B_AX_CPUQ_OP_SRC_QID_MASK); 3323 val = u32_replace_bits(val, ctrl_para->dst_pid, 3324 B_AX_CPUQ_OP_DST_PID_MASK); 3325 val = u32_replace_bits(val, ctrl_para->dst_qid, 3326 B_AX_CPUQ_OP_DST_QID_MASK); 3327 rtw89_write32(rtwdev, reg, val); 3328 3329 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3330 val = 0; 3331 val = u32_replace_bits(val, cmd_type, 3332 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3333 val = u32_replace_bits(val, ctrl_para->macid, 3334 B_AX_CPUQ_OP_MACID_MASK); 3335 val = u32_replace_bits(val, ctrl_para->pkt_num, 3336 B_AX_CPUQ_OP_PKTNUM_MASK); 3337 val |= B_AX_WD_CPUQ_OP_EXEC; 3338 rtw89_write32(rtwdev, reg, val); 3339 3340 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3341 3342 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3343 1, 2000, false, rtwdev, reg); 3344 if (ret) 3345 return ret; 3346 3347 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3348 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3349 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3350 3351 return 0; 3352 } 3353 3354 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3355 bool band1_en) 3356 { 3357 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3358 const struct rtw89_dle_mem *cfg; 3359 3360 cfg = get_dle_mem_cfg(rtwdev, mode); 3361 if (!cfg) { 3362 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3363 return -EINVAL; 3364 } 3365 3366 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3367 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3368 return -EINVAL; 3369 } 3370 3371 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3372 3373 return mac->dle_quota_change(rtwdev, band1_en); 3374 } 3375 3376 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3377 { 3378 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3379 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3380 u16 pkt_id; 3381 int ret; 3382 3383 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3384 if (ret) { 3385 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3386 return ret; 3387 } 3388 3389 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3390 ctrl_para.start_pktid = pkt_id; 3391 ctrl_para.end_pktid = pkt_id; 3392 ctrl_para.pkt_num = 0; 3393 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3394 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3395 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3396 if (ret) { 3397 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3398 return -EFAULT; 3399 } 3400 3401 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3402 if (ret) { 3403 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3404 return ret; 3405 } 3406 3407 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3408 ctrl_para.start_pktid = pkt_id; 3409 ctrl_para.end_pktid = pkt_id; 3410 ctrl_para.pkt_num = 0; 3411 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3412 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3413 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3414 if (ret) { 3415 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3416 return -EFAULT; 3417 } 3418 3419 return 0; 3420 } 3421 3422 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3423 { 3424 int ret; 3425 u32 reg; 3426 u8 val; 3427 3428 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3429 if (ret) 3430 return ret; 3431 3432 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3433 3434 ret = read_poll_timeout(rtw89_read8, val, 3435 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3436 SW_CVR_DUR_US, 3437 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3438 false, rtwdev, reg); 3439 if (ret) 3440 return ret; 3441 3442 return 0; 3443 } 3444 3445 static int band1_enable_ax(struct rtw89_dev *rtwdev) 3446 { 3447 int ret, i; 3448 u32 sleep_bak[4] = {0}; 3449 u32 pause_bak[4] = {0}; 3450 u32 tx_en; 3451 3452 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3453 if (ret) { 3454 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3455 return ret; 3456 } 3457 3458 for (i = 0; i < 4; i++) { 3459 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3460 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3461 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3462 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3463 } 3464 3465 ret = band_idle_ck_b(rtwdev, 0); 3466 if (ret) { 3467 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3468 return ret; 3469 } 3470 3471 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3472 if (ret) { 3473 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3474 return ret; 3475 } 3476 3477 for (i = 0; i < 4; i++) { 3478 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3479 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3480 } 3481 3482 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3483 if (ret) { 3484 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3485 return ret; 3486 } 3487 3488 ret = cmac_func_en_ax(rtwdev, 1, true); 3489 if (ret) { 3490 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3491 return ret; 3492 } 3493 3494 ret = cmac_init_ax(rtwdev, 1); 3495 if (ret) { 3496 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3497 return ret; 3498 } 3499 3500 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3501 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3502 3503 return 0; 3504 } 3505 3506 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3507 { 3508 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3509 3510 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3511 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3512 } 3513 3514 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3515 { 3516 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3517 3518 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3519 } 3520 3521 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3522 { 3523 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3524 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3525 3526 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3527 B_AX_TX_GET_ERRPKTID_INT_EN | 3528 B_AX_TX_NXT_ERRPKTID_INT_EN | 3529 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3530 B_AX_TX_OFFSET_ERR_INT_EN | 3531 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3532 if (chip_id == RTL8852C) 3533 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3534 B_AX_TX_ETH_TYPE_ERR_EN | 3535 B_AX_TX_LLC_PRE_ERR_EN | 3536 B_AX_TX_NW_TYPE_ERR_EN | 3537 B_AX_TX_KSRCH_ERR_EN); 3538 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3539 imr->mpdu_tx_imr_set); 3540 3541 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3542 B_AX_GETPKTID_ERR_INT_EN | 3543 B_AX_MHDRLEN_ERR_INT_EN | 3544 B_AX_RPT_ERR_INT_EN); 3545 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3546 imr->mpdu_rx_imr_set); 3547 } 3548 3549 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3550 { 3551 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3552 3553 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3554 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3555 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3556 B_AX_PLE_B_PKTID_ERR_INT_EN); 3557 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3558 imr->sta_sch_imr_set); 3559 } 3560 3561 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3562 { 3563 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3564 3565 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3566 imr->txpktctl_imr_b0_clr); 3567 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3568 imr->txpktctl_imr_b0_set); 3569 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3570 imr->txpktctl_imr_b1_clr); 3571 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3572 imr->txpktctl_imr_b1_set); 3573 } 3574 3575 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3576 { 3577 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3578 3579 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3580 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3581 } 3582 3583 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3584 { 3585 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3586 3587 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3588 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3589 } 3590 3591 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3592 { 3593 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3594 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3595 } 3596 3597 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3598 { 3599 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3600 3601 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3602 imr->host_disp_imr_clr); 3603 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3604 imr->host_disp_imr_set); 3605 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3606 imr->cpu_disp_imr_clr); 3607 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3608 imr->cpu_disp_imr_set); 3609 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3610 imr->other_disp_imr_clr); 3611 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3612 imr->other_disp_imr_set); 3613 } 3614 3615 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3616 { 3617 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3618 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3619 } 3620 3621 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3622 { 3623 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3624 3625 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3626 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3627 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3628 B_AX_BBRPT_CHINFO_IMR_CLR); 3629 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3630 imr->bbrpt_err_imr_set); 3631 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3632 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3633 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3634 } 3635 3636 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3637 { 3638 u32 reg; 3639 3640 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3641 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3642 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3643 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3644 } 3645 3646 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3647 { 3648 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3649 u32 reg; 3650 3651 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3652 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3653 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3654 } 3655 3656 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3657 { 3658 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3659 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3660 u32 reg; 3661 3662 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3663 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3664 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3665 3666 if (chip_id == RTL8852C) { 3667 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3668 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3669 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3670 } 3671 } 3672 3673 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3674 { 3675 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3676 u32 reg; 3677 3678 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3679 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3680 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3681 } 3682 3683 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3684 { 3685 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3686 u32 reg; 3687 3688 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3689 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3690 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3691 } 3692 3693 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3694 { 3695 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3696 u32 reg; 3697 3698 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3699 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3700 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3701 } 3702 3703 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3704 enum rtw89_mac_hwmod_sel sel) 3705 { 3706 int ret; 3707 3708 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3709 if (ret) { 3710 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3711 sel, mac_idx); 3712 return ret; 3713 } 3714 3715 if (sel == RTW89_DMAC_SEL) { 3716 rtw89_wdrls_imr_enable(rtwdev); 3717 rtw89_wsec_imr_enable(rtwdev); 3718 rtw89_mpdu_trx_imr_enable(rtwdev); 3719 rtw89_sta_sch_imr_enable(rtwdev); 3720 rtw89_txpktctl_imr_enable(rtwdev); 3721 rtw89_wde_imr_enable(rtwdev); 3722 rtw89_ple_imr_enable(rtwdev); 3723 rtw89_pktin_imr_enable(rtwdev); 3724 rtw89_dispatcher_imr_enable(rtwdev); 3725 rtw89_cpuio_imr_enable(rtwdev); 3726 rtw89_bbrpt_imr_enable(rtwdev); 3727 } else if (sel == RTW89_CMAC_SEL) { 3728 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3729 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3730 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3731 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3732 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3733 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3734 } else { 3735 return -EINVAL; 3736 } 3737 3738 return 0; 3739 } 3740 3741 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3742 { 3743 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3744 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3745 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3746 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3747 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta) 3748 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3749 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3750 } 3751 3752 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3753 { 3754 int ret = 0; 3755 3756 if (enable) { 3757 ret = band1_enable_ax(rtwdev); 3758 if (ret) { 3759 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3760 return ret; 3761 } 3762 3763 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3764 if (ret) { 3765 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3766 return ret; 3767 } 3768 } else { 3769 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3770 return -EINVAL; 3771 } 3772 3773 return 0; 3774 } 3775 3776 static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3777 { 3778 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3779 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3780 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3781 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3782 B_AX_RLSRPT0_FLTR_MAP_MASK); 3783 } else { 3784 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3785 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3786 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3787 B_AX_RLSRPT0_FLTR_MAP_MASK); 3788 } 3789 3790 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3791 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3792 3793 return 0; 3794 } 3795 3796 static int trx_init_ax(struct rtw89_dev *rtwdev) 3797 { 3798 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3799 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3800 int ret; 3801 3802 ret = dmac_init_ax(rtwdev, 0); 3803 if (ret) { 3804 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3805 return ret; 3806 } 3807 3808 ret = cmac_init_ax(rtwdev, 0); 3809 if (ret) { 3810 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3811 return ret; 3812 } 3813 3814 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3815 ret = dbcc_enable_ax(rtwdev, true); 3816 if (ret) { 3817 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3818 return ret; 3819 } 3820 } 3821 3822 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3823 if (ret) { 3824 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3825 return ret; 3826 } 3827 3828 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3829 if (ret) { 3830 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3831 return ret; 3832 } 3833 3834 err_imr_ctrl_ax(rtwdev, true); 3835 3836 ret = set_host_rpr_ax(rtwdev); 3837 if (ret) { 3838 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3839 return ret; 3840 } 3841 3842 if (chip_id == RTL8852C) 3843 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG, 3844 B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN); 3845 3846 return 0; 3847 } 3848 3849 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 3850 { 3851 #define BACAM_1024BMP_OCC_ENTRY 4 3852 #define BACAM_MAX_RU_SUPPORT_B0_STA 1 3853 #define BACAM_MAX_RU_SUPPORT_B1_STA 1 3854 const struct rtw89_chip_info *chip = rtwdev->chip; 3855 u8 users, offset; 3856 3857 if (chip->bacam_ver != RTW89_BACAM_V1) 3858 return 0; 3859 3860 offset = 0; 3861 users = BACAM_MAX_RU_SUPPORT_B0_STA; 3862 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 3863 3864 offset += users * BACAM_1024BMP_OCC_ENTRY; 3865 users = BACAM_MAX_RU_SUPPORT_B1_STA; 3866 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 3867 3868 return 0; 3869 } 3870 3871 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3872 { 3873 u32 val32; 3874 3875 if (rtw89_is_rtl885xb(rtwdev)) { 3876 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3877 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3878 return; 3879 } 3880 3881 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3882 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3883 3884 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3885 val32 |= B_AX_FS_WDT_INT; 3886 val32 &= ~B_AX_FS_WDT_INT_MSK; 3887 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3888 } 3889 3890 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3891 { 3892 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3893 3894 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3895 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3896 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3897 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3898 3899 rtw89_disable_fw_watchdog(rtwdev); 3900 3901 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3902 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3903 } 3904 3905 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3906 bool dlfw, bool include_bb) 3907 { 3908 u32 val; 3909 int ret; 3910 3911 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3912 return -EFAULT; 3913 3914 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3915 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3916 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3917 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3918 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3919 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3920 3921 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3922 3923 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3924 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3925 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3926 B_AX_WCPU_FWDL_STS_MASK); 3927 3928 if (dlfw) 3929 val |= B_AX_WCPU_FWDL_EN; 3930 3931 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3932 3933 if (rtw89_is_rtl885xb(rtwdev)) 3934 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3935 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3936 3937 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3938 boot_reason); 3939 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3940 3941 if (!dlfw) { 3942 mdelay(5); 3943 3944 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3945 if (ret) 3946 return ret; 3947 } 3948 3949 return 0; 3950 } 3951 3952 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 3953 { 3954 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3955 u32 val; 3956 3957 if (chip_id == RTL8852C) 3958 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3959 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3960 else 3961 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3962 B_AX_PKT_BUF_EN; 3963 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3964 } 3965 3966 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 3967 { 3968 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3969 u32 val; 3970 3971 if (chip_id == RTL8851B || chip_id == RTL8852BT) 3972 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3973 else 3974 val = B_AX_DISPATCHER_CLK_EN; 3975 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3976 3977 if (chip_id != RTL8852C) 3978 return; 3979 3980 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3981 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3982 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3983 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3984 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3985 3986 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3987 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3988 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3989 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3990 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3991 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3992 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3993 } 3994 3995 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3996 { 3997 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3998 int ret; 3999 4000 mac->hci_func_en(rtwdev); 4001 mac->dmac_func_pre_en(rtwdev); 4002 4003 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 4004 if (ret) { 4005 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 4006 return ret; 4007 } 4008 4009 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 4010 if (ret) { 4011 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 4012 return ret; 4013 } 4014 4015 return ret; 4016 } 4017 4018 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 4019 { 4020 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 4021 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 4022 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 4023 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 4024 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 4025 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 4026 4027 return 0; 4028 } 4029 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 4030 4031 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 4032 { 4033 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 4034 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 4035 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 4036 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 4037 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 4038 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 4039 4040 return 0; 4041 } 4042 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 4043 4044 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 4045 { 4046 int ret; 4047 4048 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 4049 4050 if (include_bb) { 4051 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 4052 if (rtwdev->dbcc_en) 4053 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 4054 } 4055 4056 ret = rtw89_mac_dmac_pre_init(rtwdev); 4057 if (ret) 4058 return ret; 4059 4060 if (rtwdev->hci.ops->mac_pre_init) { 4061 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 4062 if (ret) 4063 return ret; 4064 } 4065 4066 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 4067 if (ret) 4068 return ret; 4069 4070 return 0; 4071 } 4072 4073 int rtw89_mac_init(struct rtw89_dev *rtwdev) 4074 { 4075 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4076 const struct rtw89_chip_info *chip = rtwdev->chip; 4077 bool include_bb = !!chip->bbmcu_nr; 4078 int ret; 4079 4080 ret = rtw89_mac_pwr_on(rtwdev); 4081 if (ret) 4082 return ret; 4083 4084 ret = rtw89_mac_partial_init(rtwdev, include_bb); 4085 if (ret) 4086 goto fail; 4087 4088 ret = rtw89_chip_enable_bb_rf(rtwdev); 4089 if (ret) 4090 goto fail; 4091 4092 ret = mac->sys_init(rtwdev); 4093 if (ret) 4094 goto fail; 4095 4096 ret = mac->trx_init(rtwdev); 4097 if (ret) 4098 goto fail; 4099 4100 ret = rtw89_mac_feat_init(rtwdev); 4101 if (ret) 4102 goto fail; 4103 4104 if (rtwdev->hci.ops->mac_post_init) { 4105 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 4106 if (ret) 4107 goto fail; 4108 } 4109 4110 rtw89_fw_send_all_early_h2c(rtwdev); 4111 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 4112 4113 return ret; 4114 fail: 4115 rtw89_mac_pwr_off(rtwdev); 4116 4117 return ret; 4118 } 4119 4120 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4121 { 4122 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4123 u8 i; 4124 4125 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4126 return; 4127 4128 for (i = 0; i < 4; i++) { 4129 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4130 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 4131 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 4132 } 4133 } 4134 4135 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4136 { 4137 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4138 4139 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4140 return; 4141 4142 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4143 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 4144 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 4145 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 4146 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 4147 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 4148 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 4149 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 4150 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 4151 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 4152 } 4153 4154 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4155 { 4156 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4157 u8 grp = macid >> 5; 4158 int ret; 4159 4160 /* If this is called by change_interface() in the case of P2P, it could 4161 * be power-off, so ignore this operation. 4162 */ 4163 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4164 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4165 return 0; 4166 4167 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4168 if (ret) 4169 return ret; 4170 4171 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4172 4173 return 0; 4174 } 4175 4176 static const struct rtw89_port_reg rtw89_port_base_ax = { 4177 .port_cfg = R_AX_PORT_CFG_P0, 4178 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4179 .bcn_area = R_AX_BCN_AREA_P0, 4180 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4181 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4182 .tbtt_agg = R_AX_TBTT_AGG_P0, 4183 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4184 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4185 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4186 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4187 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4188 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4189 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4190 .tsftr_l = R_AX_TSFTR_LOW_P0, 4191 .tsftr_h = R_AX_TSFTR_HIGH_P0, 4192 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 4193 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4194 .mbssid = R_AX_MBSSID_CTRL, 4195 .mbssid_drop = R_AX_MBSSID_DROP_0, 4196 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4197 .ptcl_dbg = R_AX_PTCL_DBG, 4198 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4199 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4200 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4201 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4202 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4203 }; 4204 4205 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4206 struct rtw89_vif_link *rtwvif_link, u8 type) 4207 { 4208 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4209 const struct rtw89_port_reg *p = mac->port_base; 4210 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif_link->port); 4211 u32 reg_info, reg_ctrl; 4212 u32 val; 4213 int ret; 4214 4215 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif_link->mac_idx); 4216 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif_link->mac_idx); 4217 4218 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4219 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4220 fsleep(100); 4221 4222 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4223 true, rtwdev, reg_info, mask); 4224 if (ret) 4225 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4226 } 4227 4228 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, 4229 struct rtw89_vif_link *rtwvif_link) 4230 { 4231 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4232 const struct rtw89_port_reg *p = mac->port_base; 4233 4234 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4235 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 4236 1); 4237 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 4238 0); 4239 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 4240 0); 4241 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4242 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4243 B_AX_TBTTERLY_MASK, 1); 4244 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, 4245 B_AX_BCN_SPACE_MASK, 1); 4246 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4247 4248 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM0); 4249 if (rtwvif_link->port == RTW89_PORT_0) 4250 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM1); 4251 4252 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4253 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4254 fsleep(2000); 4255 } 4256 4257 #define BCN_INTERVAL 100 4258 #define BCN_ERLY_DEF 160 4259 #define BCN_SETUP_DEF 2 4260 #define BCN_HOLD_DEF 200 4261 #define BCN_MASK_DEF 0 4262 #define TBTT_ERLY_DEF 5 4263 #define BCN_SET_UNIT 32 4264 #define BCN_ERLY_SET_DLY (10 * 2) 4265 4266 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4267 struct rtw89_vif_link *rtwvif_link) 4268 { 4269 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4270 const struct rtw89_port_reg *p = mac->port_base; 4271 const struct rtw89_chip_info *chip = rtwdev->chip; 4272 struct ieee80211_bss_conf *bss_conf; 4273 bool need_backup = false; 4274 u32 backup_val; 4275 u16 beacon_int; 4276 4277 if (!rtw89_read32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN)) 4278 return; 4279 4280 if (chip->chip_id == RTL8852A && rtwvif_link->port != RTW89_PORT_0) { 4281 need_backup = true; 4282 backup_val = rtw89_read32_port(rtwdev, rtwvif_link, p->tbtt_prohib); 4283 } 4284 4285 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4286 rtw89_mac_bcn_drop(rtwdev, rtwvif_link); 4287 4288 if (chip->chip_id == RTL8852A) { 4289 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->tbtt_prohib, 4290 B_AX_TBTT_SETUP_MASK); 4291 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4292 B_AX_TBTT_HOLD_MASK, 1); 4293 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->tbtt_early, 4294 B_AX_TBTTERLY_MASK); 4295 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->bcn_early, 4296 B_AX_BCNERLY_MASK); 4297 } 4298 4299 rcu_read_lock(); 4300 4301 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4302 beacon_int = bss_conf->beacon_int; 4303 4304 rcu_read_unlock(); 4305 4306 msleep(beacon_int + 1); 4307 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN | 4308 B_AX_BRK_SETUP); 4309 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSFTR_RST); 4310 rtw89_write32_port(rtwdev, rtwvif_link, p->bcn_cnt_tmr, 0); 4311 4312 if (need_backup) 4313 rtw89_write32_port(rtwdev, rtwvif_link, p->tbtt_prohib, backup_val); 4314 } 4315 4316 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4317 struct rtw89_vif_link *rtwvif_link, bool en) 4318 { 4319 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4320 const struct rtw89_port_reg *p = mac->port_base; 4321 4322 if (en) 4323 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4324 B_AX_TXBCN_RPT_EN); 4325 else 4326 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4327 B_AX_TXBCN_RPT_EN); 4328 } 4329 4330 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4331 struct rtw89_vif_link *rtwvif_link, bool en) 4332 { 4333 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4334 const struct rtw89_port_reg *p = mac->port_base; 4335 4336 if (en) 4337 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4338 B_AX_RXBCN_RPT_EN); 4339 else 4340 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4341 B_AX_RXBCN_RPT_EN); 4342 } 4343 4344 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4345 struct rtw89_vif_link *rtwvif_link) 4346 { 4347 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4348 const struct rtw89_port_reg *p = mac->port_base; 4349 4350 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_NET_TYPE_MASK, 4351 rtwvif_link->net_type); 4352 } 4353 4354 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4355 struct rtw89_vif_link *rtwvif_link) 4356 { 4357 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4358 const struct rtw89_port_reg *p = mac->port_base; 4359 bool en = rtwvif_link->net_type != RTW89_NET_TYPE_NO_LINK; 4360 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4361 4362 if (en) 4363 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bits); 4364 else 4365 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bits); 4366 } 4367 4368 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4369 struct rtw89_vif_link *rtwvif_link) 4370 { 4371 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4372 const struct rtw89_port_reg *p = mac->port_base; 4373 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4374 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4375 u32 bit = B_AX_RX_BSSID_FIT_EN; 4376 4377 if (en) 4378 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bit); 4379 else 4380 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bit); 4381 } 4382 4383 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4384 struct rtw89_vif_link *rtwvif_link, bool en) 4385 { 4386 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4387 const struct rtw89_port_reg *p = mac->port_base; 4388 4389 if (en) 4390 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4391 else 4392 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4393 } 4394 4395 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4396 struct rtw89_vif_link *rtwvif_link) 4397 { 4398 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4399 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4400 4401 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif_link, en); 4402 } 4403 4404 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4405 struct rtw89_vif_link *rtwvif_link, bool en) 4406 { 4407 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4408 const struct rtw89_port_reg *p = mac->port_base; 4409 4410 if (en) 4411 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4412 else 4413 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4414 } 4415 4416 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4417 struct rtw89_vif_link *rtwvif_link) 4418 { 4419 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || 4420 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4421 4422 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4423 } 4424 4425 static void rtw89_mac_enable_ap_bcn_by_chan(struct rtw89_dev *rtwdev, 4426 struct rtw89_vif_link *rtwvif_link, 4427 const struct rtw89_chan *to_match, 4428 bool en) 4429 { 4430 const struct rtw89_chan *chan; 4431 4432 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 4433 return; 4434 4435 if (!to_match) 4436 goto doit; 4437 4438 /* @to_match may not be in the same domain as return of calling 4439 * rtw89_chan_get(). So, cannot compare their addresses directly. 4440 */ 4441 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 4442 if (chan->channel != to_match->channel) 4443 return; 4444 4445 doit: 4446 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4447 } 4448 4449 static void rtw89_mac_enable_aps_bcn_by_chan(struct rtw89_dev *rtwdev, 4450 const struct rtw89_chan *to_match, 4451 bool en) 4452 { 4453 struct rtw89_vif_link *rtwvif_link; 4454 struct rtw89_vif *rtwvif; 4455 unsigned int link_id; 4456 4457 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4458 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4459 rtw89_mac_enable_ap_bcn_by_chan(rtwdev, rtwvif_link, 4460 to_match, en); 4461 } 4462 4463 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4464 { 4465 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, NULL, en); 4466 } 4467 4468 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4469 struct rtw89_vif_link *rtwvif_link) 4470 { 4471 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4472 const struct rtw89_port_reg *p = mac->port_base; 4473 struct ieee80211_bss_conf *bss_conf; 4474 u16 bcn_int; 4475 4476 rcu_read_lock(); 4477 4478 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4479 if (bss_conf->beacon_int) 4480 bcn_int = bss_conf->beacon_int; 4481 else 4482 bcn_int = BCN_INTERVAL; 4483 4484 rcu_read_unlock(); 4485 4486 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, B_AX_BCN_SPACE_MASK, 4487 bcn_int); 4488 } 4489 4490 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4491 struct rtw89_vif_link *rtwvif_link) 4492 { 4493 u8 win = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4494 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4495 const struct rtw89_port_reg *p = mac->port_base; 4496 u8 port = rtwvif_link->port; 4497 u32 reg; 4498 4499 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif_link->mac_idx); 4500 rtw89_write8(rtwdev, reg, win); 4501 } 4502 4503 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4504 struct rtw89_vif_link *rtwvif_link) 4505 { 4506 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4507 const struct rtw89_port_reg *p = mac->port_base; 4508 struct ieee80211_bss_conf *bss_conf; 4509 u8 dtim_period; 4510 u32 addr; 4511 4512 rcu_read_lock(); 4513 4514 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4515 dtim_period = bss_conf->dtim_period; 4516 4517 rcu_read_unlock(); 4518 4519 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif_link->mac_idx); 4520 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4521 4522 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4523 dtim_period); 4524 } 4525 4526 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4527 struct rtw89_vif_link *rtwvif_link) 4528 { 4529 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4530 const struct rtw89_port_reg *p = mac->port_base; 4531 4532 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4533 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4534 } 4535 4536 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4537 struct rtw89_vif_link *rtwvif_link) 4538 { 4539 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4540 const struct rtw89_port_reg *p = mac->port_base; 4541 4542 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4543 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4544 } 4545 4546 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4547 struct rtw89_vif_link *rtwvif_link) 4548 { 4549 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4550 const struct rtw89_port_reg *p = mac->port_base; 4551 4552 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, 4553 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4554 } 4555 4556 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4557 struct rtw89_vif_link *rtwvif_link) 4558 { 4559 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4560 const struct rtw89_port_reg *p = mac->port_base; 4561 4562 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4563 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4564 } 4565 4566 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4567 struct rtw89_vif_link *rtwvif_link) 4568 { 4569 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4570 const struct rtw89_port_reg *p = mac->port_base; 4571 static const u32 masks[RTW89_PORT_NUM] = { 4572 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4573 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4574 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4575 }; 4576 struct ieee80211_bss_conf *bss_conf; 4577 u8 port = rtwvif_link->port; 4578 u32 reg_base; 4579 u32 reg; 4580 u8 bss_color; 4581 4582 rcu_read_lock(); 4583 4584 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4585 bss_color = bss_conf->he_bss_color.color; 4586 4587 rcu_read_unlock(); 4588 4589 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4590 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif_link->mac_idx); 4591 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4592 } 4593 4594 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4595 struct rtw89_vif_link *rtwvif_link) 4596 { 4597 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4598 const struct rtw89_port_reg *p = mac->port_base; 4599 u8 port = rtwvif_link->port; 4600 u32 reg; 4601 4602 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4603 return; 4604 4605 if (port == 0) { 4606 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif_link->mac_idx); 4607 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4608 } 4609 } 4610 4611 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4612 struct rtw89_vif_link *rtwvif_link) 4613 { 4614 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4615 const struct rtw89_port_reg *p = mac->port_base; 4616 u8 port = rtwvif_link->port; 4617 u32 reg; 4618 u32 val; 4619 4620 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif_link->mac_idx); 4621 val = rtw89_read32(rtwdev, reg); 4622 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4623 if (port == 0) 4624 val &= ~BIT(0); 4625 rtw89_write32(rtwdev, reg, val); 4626 } 4627 4628 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4629 struct rtw89_vif_link *rtwvif_link, bool enable) 4630 { 4631 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4632 const struct rtw89_port_reg *p = mac->port_base; 4633 4634 if (enable) 4635 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4636 B_AX_PORT_FUNC_EN); 4637 else 4638 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4639 B_AX_PORT_FUNC_EN); 4640 } 4641 4642 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4643 struct rtw89_vif_link *rtwvif_link) 4644 { 4645 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4646 const struct rtw89_port_reg *p = mac->port_base; 4647 4648 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 4649 BCN_ERLY_DEF); 4650 } 4651 4652 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4653 struct rtw89_vif_link *rtwvif_link) 4654 { 4655 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4656 const struct rtw89_port_reg *p = mac->port_base; 4657 u16 val; 4658 4659 if (rtwdev->chip->chip_id != RTL8852C) 4660 return; 4661 4662 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4663 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION) 4664 return; 4665 4666 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4667 B_AX_TBTT_SHIFT_OFST_SIGN; 4668 4669 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift, 4670 B_AX_TBTT_SHIFT_OFST_MASK, val); 4671 } 4672 4673 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4674 struct rtw89_vif_link *rtwvif_link, 4675 struct rtw89_vif_link *rtwvif_src, 4676 u16 offset_tu) 4677 { 4678 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4679 const struct rtw89_port_reg *p = mac->port_base; 4680 u32 val, reg; 4681 4682 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4683 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif_link->port * 4, 4684 rtwvif_link->mac_idx); 4685 4686 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4687 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4688 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4689 } 4690 4691 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4692 struct rtw89_vif_link *rtwvif_link, 4693 struct rtw89_vif_link *rtwvif_src, 4694 u8 offset, int *n_offset) 4695 { 4696 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif_link == rtwvif_src) 4697 return; 4698 4699 if (rtwvif_link->rand_tsf_done) 4700 goto out; 4701 4702 /* adjust offset randomly to avoid beacon conflict */ 4703 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4704 rtw89_mac_port_tsf_sync(rtwdev, rtwvif_link, rtwvif_src, 4705 (*n_offset) * offset); 4706 4707 rtwvif_link->rand_tsf_done = true; 4708 4709 out: 4710 (*n_offset)++; 4711 } 4712 4713 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4714 { 4715 struct rtw89_vif_link *src = NULL, *tmp; 4716 u8 offset = 100, vif_aps = 0; 4717 struct rtw89_vif *rtwvif; 4718 unsigned int link_id; 4719 int n_offset = 1; 4720 4721 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4722 rtw89_vif_for_each_link(rtwvif, tmp, link_id) { 4723 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4724 src = tmp; 4725 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4726 vif_aps++; 4727 } 4728 } 4729 4730 if (vif_aps == 0) 4731 return; 4732 4733 offset /= (vif_aps + 1); 4734 4735 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4736 rtw89_vif_for_each_link(rtwvif, tmp, link_id) 4737 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, 4738 &n_offset); 4739 } 4740 4741 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4742 { 4743 int ret; 4744 4745 ret = rtw89_mac_port_update(rtwdev, rtwvif_link); 4746 if (ret) 4747 return ret; 4748 4749 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4750 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4751 4752 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif_link->mac_id, false); 4753 if (ret) 4754 return ret; 4755 4756 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_CREATE); 4757 if (ret) 4758 return ret; 4759 4760 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, NULL, true); 4761 if (ret) 4762 return ret; 4763 4764 ret = rtw89_cam_init(rtwdev, rtwvif_link); 4765 if (ret) 4766 return ret; 4767 4768 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 4769 if (ret) 4770 return ret; 4771 4772 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, NULL); 4773 if (ret) 4774 return ret; 4775 4776 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, NULL); 4777 if (ret) 4778 return ret; 4779 4780 return 0; 4781 } 4782 4783 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4784 { 4785 int ret; 4786 4787 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_REMOVE); 4788 if (ret) 4789 return ret; 4790 4791 rtw89_cam_deinit(rtwdev, rtwvif_link); 4792 4793 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 4794 if (ret) 4795 return ret; 4796 4797 return 0; 4798 } 4799 4800 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4801 { 4802 u8 port = rtwvif_link->port; 4803 4804 if (port >= RTW89_PORT_NUM) 4805 return -EINVAL; 4806 4807 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 4808 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif_link, false); 4809 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif_link, false); 4810 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif_link); 4811 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif_link); 4812 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif_link); 4813 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif_link); 4814 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif_link); 4815 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif_link); 4816 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif_link); 4817 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif_link); 4818 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif_link); 4819 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif_link); 4820 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif_link); 4821 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif_link); 4822 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif_link); 4823 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif_link); 4824 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif_link); 4825 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif_link); 4826 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif_link, true); 4827 rtw89_mac_port_tsf_resync_all(rtwdev); 4828 fsleep(BCN_ERLY_SET_DLY); 4829 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif_link); 4830 4831 return 0; 4832 } 4833 4834 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4835 u64 *tsf) 4836 { 4837 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4838 const struct rtw89_port_reg *p = mac->port_base; 4839 u32 tsf_low, tsf_high; 4840 int ret; 4841 4842 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif_link->mac_idx, RTW89_CMAC_SEL); 4843 if (ret) 4844 return ret; 4845 4846 tsf_low = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_l); 4847 tsf_high = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_h); 4848 *tsf = (u64)tsf_high << 32 | tsf_low; 4849 4850 return 0; 4851 } 4852 4853 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4854 struct cfg80211_bss *bss, 4855 void *data) 4856 { 4857 const struct cfg80211_bss_ies *ies; 4858 const struct element *elem; 4859 bool *tolerated = data; 4860 4861 rcu_read_lock(); 4862 ies = rcu_dereference(bss->ies); 4863 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4864 ies->len); 4865 4866 if (!elem || elem->datalen < 10 || 4867 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4868 *tolerated = false; 4869 rcu_read_unlock(); 4870 } 4871 4872 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4873 struct rtw89_vif_link *rtwvif_link) 4874 { 4875 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4876 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4877 struct ieee80211_hw *hw = rtwdev->hw; 4878 struct ieee80211_bss_conf *bss_conf; 4879 struct cfg80211_chan_def oper; 4880 bool tolerated = true; 4881 u32 reg; 4882 4883 rcu_read_lock(); 4884 4885 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4886 if (!bss_conf->he_support || vif->type != NL80211_IFTYPE_STATION) { 4887 rcu_read_unlock(); 4888 return; 4889 } 4890 4891 oper = bss_conf->chanreq.oper; 4892 if (!(oper.chan->flags & IEEE80211_CHAN_RADAR)) { 4893 rcu_read_unlock(); 4894 return; 4895 } 4896 4897 rcu_read_unlock(); 4898 4899 cfg80211_bss_iter(hw->wiphy, &oper, 4900 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4901 &tolerated); 4902 4903 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 4904 rtwvif_link->mac_idx); 4905 if (tolerated) 4906 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4907 else 4908 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4909 } 4910 4911 void rtw89_mac_set_he_tb(struct rtw89_dev *rtwdev, 4912 struct rtw89_vif_link *rtwvif_link) 4913 { 4914 struct ieee80211_bss_conf *bss_conf; 4915 bool set; 4916 u32 reg; 4917 4918 if (rtwdev->chip->chip_gen != RTW89_CHIP_BE) 4919 return; 4920 4921 rcu_read_lock(); 4922 4923 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4924 set = bss_conf->he_support && !bss_conf->eht_support; 4925 4926 rcu_read_unlock(); 4927 4928 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CLIENT_OM_CTRL, 4929 rtwvif_link->mac_idx); 4930 4931 if (set) 4932 rtw89_write32_set(rtwdev, reg, B_BE_TRIG_DIS_EHTTB); 4933 else 4934 rtw89_write32_clr(rtwdev, reg, B_BE_TRIG_DIS_EHTTB); 4935 } 4936 4937 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4938 { 4939 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 4940 4941 rtwvif_link->rand_tsf_done = false; 4942 } 4943 4944 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4945 { 4946 return rtw89_mac_vif_init(rtwdev, rtwvif_link); 4947 } 4948 4949 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4950 { 4951 return rtw89_mac_vif_deinit(rtwdev, rtwvif_link); 4952 } 4953 4954 static void 4955 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4956 { 4957 } 4958 4959 static const struct rtw89_chan * 4960 rtw89_hw_scan_search_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4961 { 4962 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 4963 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4964 4965 if (band == op->band_type && channel == op->primary_channel) 4966 return op; 4967 4968 if (scan_info->extra_op.set) { 4969 op = &scan_info->extra_op.chan; 4970 if (band == op->band_type && channel == op->primary_channel) 4971 return op; 4972 } 4973 4974 return NULL; 4975 } 4976 4977 static void 4978 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4979 u32 len) 4980 { 4981 const struct rtw89_c2h_scanofld *c2h = 4982 (const struct rtw89_c2h_scanofld *)skb->data; 4983 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 4984 const struct rtw89_chan *op_chan; 4985 struct rtw89_vif *rtwvif; 4986 struct rtw89_chan new; 4987 u16 actual_period, expect_period; 4988 u8 reason, status, tx_fail, band; 4989 u8 mac_idx, sw_def, fw_def; 4990 u8 ver = U8_MAX; 4991 u32 report_tsf; 4992 u16 chan; 4993 int ret; 4994 4995 if (!rtwvif_link) 4996 return; 4997 4998 rtwvif = rtwvif_link->rtwvif; 4999 5000 if (RTW89_CHK_FW_FEATURE(CH_INFO_BE_V0, &rtwdev->fw)) 5001 ver = 0; 5002 5003 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 5004 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5005 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 5006 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5007 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 5008 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 5009 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 5010 5011 5012 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 5013 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 5014 5015 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 5016 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 5017 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 5018 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 5019 if (ver == 0) { 5020 expect_period = 5021 le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 5022 } else { 5023 actual_period = le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_PERIOD_V1); 5024 expect_period = 5025 le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1); 5026 } 5027 5028 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 5029 "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 5030 sw_def, fw_def, report_tsf, expect_period); 5031 } 5032 5033 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 5034 "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 5035 mac_idx, band, chan, reason, status, tx_fail, actual_period); 5036 5037 switch (reason) { 5038 case RTW89_SCAN_LEAVE_OP_NOTIFY: 5039 case RTW89_SCAN_LEAVE_CH_NOTIFY: 5040 op_chan = rtw89_hw_scan_search_op_chan(rtwdev, band, chan); 5041 if (op_chan) { 5042 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, op_chan, false); 5043 ieee80211_stop_queues(rtwdev->hw); 5044 } 5045 return; 5046 case RTW89_SCAN_END_SCAN_NOTIFY: 5047 if (rtwdev->scan_info.abort) 5048 return; 5049 5050 if (rtwvif_link && rtwvif->scan_req && 5051 !list_empty(&rtwdev->scan_info.chan_list)) { 5052 rtwdev->scan_info.delay = 0; 5053 ret = rtw89_hw_scan_offload(rtwdev, rtwvif_link, true); 5054 if (ret) { 5055 rtw89_hw_scan_abort(rtwdev, rtwvif_link); 5056 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 5057 } 5058 } else { 5059 rtw89_hw_scan_complete(rtwdev, rtwvif_link, false); 5060 } 5061 break; 5062 case RTW89_SCAN_ENTER_OP_NOTIFY: 5063 case RTW89_SCAN_ENTER_CH_NOTIFY: 5064 op_chan = rtw89_hw_scan_search_op_chan(rtwdev, band, chan); 5065 if (op_chan) { 5066 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, op_chan); 5067 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, op_chan, true); 5068 ieee80211_wake_queues(rtwdev->hw); 5069 } else { 5070 rtw89_chan_create(&new, chan, chan, band, 5071 RTW89_CHANNEL_WIDTH_20); 5072 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, 5073 &new); 5074 } 5075 break; 5076 default: 5077 return; 5078 } 5079 } 5080 5081 static void 5082 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5083 struct sk_buff *skb) 5084 { 5085 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5086 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5087 enum nl80211_cqm_rssi_threshold_event nl_event; 5088 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 5089 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 5090 u8 type, event, mac_id; 5091 bool start_detect; 5092 s8 sig; 5093 5094 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 5095 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 5096 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 5097 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 5098 5099 if (mac_id != rtwvif_link->mac_id) 5100 return; 5101 5102 rtw89_debug(rtwdev, RTW89_DBG_FW, 5103 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 5104 mac_id, type, sig, event); 5105 5106 switch (type) { 5107 case RTW89_BCN_FLTR_BEACON_LOSS: 5108 if (!rtwdev->scanning && !rtwvif->offchan && 5109 !rtwvif_link->noa_once.in_duration) { 5110 start_detect = rtw89_mcc_detect_go_bcn(rtwdev, rtwvif_link); 5111 if (start_detect) 5112 return; 5113 5114 ieee80211_connection_loss(vif); 5115 } else { 5116 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 5117 } 5118 return; 5119 case RTW89_BCN_FLTR_NOTIFY: 5120 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 5121 break; 5122 case RTW89_BCN_FLTR_RSSI: 5123 if (event == RTW89_BCN_FLTR_RSSI_LOW) 5124 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 5125 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 5126 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 5127 else 5128 return; 5129 break; 5130 default: 5131 return; 5132 } 5133 5134 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 5135 } 5136 5137 static void 5138 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5139 u32 len) 5140 { 5141 struct rtw89_vif_link *rtwvif_link; 5142 struct rtw89_vif *rtwvif; 5143 unsigned int link_id; 5144 5145 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5146 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 5147 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif_link, c2h); 5148 } 5149 5150 static void 5151 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5152 { 5153 /* N.B. This will run in interrupt context. */ 5154 5155 rtw89_debug(rtwdev, RTW89_DBG_FW, 5156 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 5157 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 5158 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 5159 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 5160 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 5161 } 5162 5163 static void 5164 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5165 { 5166 /* N.B. This will run in interrupt context. */ 5167 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5168 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 5169 struct rtw89_wait_info *ps_wait = &rtwdev->mac.ps_wait; 5170 const struct rtw89_c2h_done_ack *c2h = 5171 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 5172 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 5173 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 5174 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 5175 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 5176 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 5177 struct rtw89_completion_data data = {}; 5178 unsigned int cond; 5179 5180 rtw89_debug(rtwdev, RTW89_DBG_FW, 5181 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 5182 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 5183 5184 if (h2c_cat != H2C_CAT_MAC) 5185 return; 5186 5187 switch (h2c_class) { 5188 default: 5189 return; 5190 case H2C_CL_MAC_PS: 5191 switch (h2c_func) { 5192 default: 5193 return; 5194 case H2C_FUNC_IPS_CFG: 5195 cond = RTW89_PS_WAIT_COND_IPS_CFG; 5196 break; 5197 } 5198 5199 data.err = !!h2c_return; 5200 rtw89_complete_cond(ps_wait, cond, &data); 5201 return; 5202 case H2C_CL_MAC_FW_OFLD: 5203 switch (h2c_func) { 5204 default: 5205 return; 5206 case H2C_FUNC_ADD_SCANOFLD_CH: 5207 cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 5208 h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN; 5209 break; 5210 case H2C_FUNC_SCANOFLD: 5211 scan_info->seq++; 5212 cond = RTW89_SCANOFLD_WAIT_COND_START; 5213 break; 5214 case H2C_FUNC_SCANOFLD_BE: 5215 scan_info->seq++; 5216 cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 5217 h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN; 5218 break; 5219 } 5220 5221 data.err = !!h2c_return; 5222 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5223 return; 5224 } 5225 } 5226 5227 static void 5228 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5229 { 5230 rtw89_fw_log_dump(rtwdev, c2h->data, len); 5231 } 5232 5233 static void 5234 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5235 { 5236 } 5237 5238 static void 5239 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 5240 u32 len) 5241 { 5242 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 5243 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 5244 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 5245 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 5246 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 5247 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 5248 struct rtw89_completion_data data = {}; 5249 unsigned int cond; 5250 5251 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 5252 pkt_id, pkt_op, pkt_len); 5253 5254 data.err = !pkt_len; 5255 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 5256 5257 rtw89_complete_cond(wait, cond, &data); 5258 } 5259 5260 static void 5261 rtw89_mac_c2h_tx_duty_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5262 { 5263 struct rtw89_c2h_tx_duty_rpt *c2h = 5264 (struct rtw89_c2h_tx_duty_rpt *)skb_c2h->data; 5265 u8 err; 5266 5267 err = le32_get_bits(c2h->w2, RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR); 5268 5269 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "C2H TX duty rpt with err=%d\n", err); 5270 } 5271 5272 static void 5273 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5274 u32 len) 5275 { 5276 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 5277 } 5278 5279 static void 5280 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5281 { 5282 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 5283 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 5284 5285 switch (func) { 5286 case H2C_FUNC_ADD_MCC: 5287 case H2C_FUNC_START_MCC: 5288 case H2C_FUNC_STOP_MCC: 5289 case H2C_FUNC_DEL_MCC_GROUP: 5290 case H2C_FUNC_RESET_MCC_GROUP: 5291 case H2C_FUNC_MCC_REQ_TSF: 5292 case H2C_FUNC_MCC_MACID_BITMAP: 5293 case H2C_FUNC_MCC_SYNC: 5294 case H2C_FUNC_MCC_SET_DURATION: 5295 break; 5296 default: 5297 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5298 "invalid MCC C2H RCV ACK: func %d\n", func); 5299 return; 5300 } 5301 5302 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5303 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 5304 } 5305 5306 static void 5307 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5308 { 5309 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 5310 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 5311 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 5312 struct rtw89_completion_data data = {}; 5313 unsigned int cond; 5314 bool next = false; 5315 5316 switch (func) { 5317 case H2C_FUNC_MCC_REQ_TSF: 5318 next = true; 5319 break; 5320 case H2C_FUNC_MCC_MACID_BITMAP: 5321 case H2C_FUNC_MCC_SYNC: 5322 case H2C_FUNC_MCC_SET_DURATION: 5323 break; 5324 case H2C_FUNC_ADD_MCC: 5325 case H2C_FUNC_START_MCC: 5326 case H2C_FUNC_STOP_MCC: 5327 case H2C_FUNC_DEL_MCC_GROUP: 5328 case H2C_FUNC_RESET_MCC_GROUP: 5329 default: 5330 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5331 "invalid MCC C2H REQ ACK: func %d\n", func); 5332 return; 5333 } 5334 5335 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5336 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5337 group, func, retcode); 5338 5339 if (!retcode && next) 5340 return; 5341 5342 data.err = !!retcode; 5343 cond = RTW89_MCC_WAIT_COND(group, func); 5344 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5345 } 5346 5347 static void 5348 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5349 { 5350 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5351 struct rtw89_completion_data data = {}; 5352 struct rtw89_mac_mcc_tsf_rpt *rpt; 5353 unsigned int cond; 5354 5355 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5356 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5357 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5358 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5359 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5360 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5361 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5362 5363 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5364 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5365 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5366 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5367 5368 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5369 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5370 } 5371 5372 static void 5373 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5374 { 5375 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5376 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5377 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5378 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5379 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5380 struct rtw89_completion_data data = {}; 5381 unsigned int cond; 5382 bool rsp = true; 5383 bool err; 5384 u8 func; 5385 5386 switch (status) { 5387 case RTW89_MAC_MCC_ADD_ROLE_OK: 5388 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5389 func = H2C_FUNC_ADD_MCC; 5390 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5391 break; 5392 case RTW89_MAC_MCC_START_GROUP_OK: 5393 case RTW89_MAC_MCC_START_GROUP_FAIL: 5394 func = H2C_FUNC_START_MCC; 5395 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5396 break; 5397 case RTW89_MAC_MCC_STOP_GROUP_OK: 5398 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5399 func = H2C_FUNC_STOP_MCC; 5400 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5401 break; 5402 case RTW89_MAC_MCC_DEL_GROUP_OK: 5403 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5404 func = H2C_FUNC_DEL_MCC_GROUP; 5405 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5406 break; 5407 case RTW89_MAC_MCC_RESET_GROUP_OK: 5408 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5409 func = H2C_FUNC_RESET_MCC_GROUP; 5410 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5411 break; 5412 case RTW89_MAC_MCC_SWITCH_CH_OK: 5413 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5414 case RTW89_MAC_MCC_TXNULL0_OK: 5415 case RTW89_MAC_MCC_TXNULL0_FAIL: 5416 case RTW89_MAC_MCC_TXNULL1_OK: 5417 case RTW89_MAC_MCC_TXNULL1_FAIL: 5418 case RTW89_MAC_MCC_SWITCH_EARLY: 5419 case RTW89_MAC_MCC_TBTT: 5420 case RTW89_MAC_MCC_DURATION_START: 5421 case RTW89_MAC_MCC_DURATION_END: 5422 rsp = false; 5423 break; 5424 default: 5425 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5426 "invalid MCC C2H STS RPT: status %d\n", status); 5427 return; 5428 } 5429 5430 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5431 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5432 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5433 5434 if (!rsp) 5435 return; 5436 5437 data.err = err; 5438 cond = RTW89_MCC_WAIT_COND(group, func); 5439 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5440 } 5441 5442 static void 5443 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5444 { 5445 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5446 const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5447 struct rtw89_completion_data data = {}; 5448 struct rtw89_mac_mrc_tsf_rpt *rpt; 5449 unsigned int i; 5450 5451 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5452 rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5453 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5454 le32_get_bits(c2h_rpt->w2, 5455 RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5456 5457 for (i = 0; i < rpt->num; i++) { 5458 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5459 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5460 5461 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5462 5463 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5464 "MRC C2H TSF RPT: index %u> %llu\n", 5465 i, rpt->tsfs[i]); 5466 } 5467 5468 rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5469 } 5470 5471 static void 5472 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5473 { 5474 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 5475 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 5476 struct rtw89_wait_info *wait = &rtw_wow->wait; 5477 const struct rtw89_c2h_wow_aoac_report *c2h = 5478 (const struct rtw89_c2h_wow_aoac_report *)skb->data; 5479 struct rtw89_completion_data data = {}; 5480 5481 aoac_rpt->rpt_ver = c2h->rpt_ver; 5482 aoac_rpt->sec_type = c2h->sec_type; 5483 aoac_rpt->key_idx = c2h->key_idx; 5484 aoac_rpt->pattern_idx = c2h->pattern_idx; 5485 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok, 5486 RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX); 5487 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv)); 5488 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count, 5489 sizeof(aoac_rpt->eapol_key_replay_count)); 5490 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk)); 5491 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv)); 5492 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv)); 5493 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id); 5494 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn); 5495 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk)); 5496 5497 rtw89_complete_cond(wait, RTW89_WOW_WAIT_COND_AOAC, &data); 5498 } 5499 5500 static void 5501 rtw89_mac_c2h_mlo_link_cfg_stat(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5502 { 5503 const struct rtw89_c2h_mlo_link_cfg_rpt *c2h_rpt; 5504 struct rtw89_wait_info *wait = &rtwdev->mlo.wait; 5505 struct rtw89_completion_data data = {}; 5506 unsigned int cond; 5507 u16 mac_id; 5508 u8 status; 5509 5510 c2h_rpt = (const struct rtw89_c2h_mlo_link_cfg_rpt *)c2h->data; 5511 5512 mac_id = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MLO_LINK_CFG_RPT_W2_MACID); 5513 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MLO_LINK_CFG_RPT_W2_STATUS); 5514 5515 data.err = status == RTW89_C2H_MLO_LINK_CFG_ROLE_NOT_EXIST || 5516 status == RTW89_C2H_MLO_LINK_CFG_RUNNING; 5517 cond = RTW89_MLO_WAIT_COND(mac_id, H2C_FUNC_MLO_LINK_CFG); 5518 rtw89_complete_cond(wait, cond, &data); 5519 } 5520 5521 static void 5522 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5523 { 5524 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5525 const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5526 struct rtw89_completion_data data = {}; 5527 enum rtw89_mac_mrc_status status; 5528 unsigned int cond; 5529 bool next = false; 5530 u32 tsf_high; 5531 u32 tsf_low; 5532 u8 sch_idx; 5533 u8 func; 5534 5535 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5536 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5537 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5538 tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5539 tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5540 5541 switch (status) { 5542 case RTW89_MAC_MRC_START_SCH_OK: 5543 func = H2C_FUNC_START_MRC; 5544 break; 5545 case RTW89_MAC_MRC_STOP_SCH_OK: 5546 /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5547 func = H2C_FUNC_DEL_MRC; 5548 next = true; 5549 break; 5550 case RTW89_MAC_MRC_DEL_SCH_OK: 5551 func = H2C_FUNC_DEL_MRC; 5552 break; 5553 case RTW89_MAC_MRC_EMPTY_SCH_FAIL: 5554 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5555 "MRC C2H STS RPT: empty sch fail\n"); 5556 return; 5557 case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL: 5558 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5559 "MRC C2H STS RPT: role not exist fail\n"); 5560 return; 5561 case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL: 5562 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5563 "MRC C2H STS RPT: data not found fail\n"); 5564 return; 5565 case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL: 5566 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5567 "MRC C2H STS RPT: get next slot fail\n"); 5568 return; 5569 case RTW89_MAC_MRC_ALT_ROLE_FAIL: 5570 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5571 "MRC C2H STS RPT: alt role fail\n"); 5572 return; 5573 case RTW89_MAC_MRC_ADD_PSTIMER_FAIL: 5574 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5575 "MRC C2H STS RPT: add ps timer fail\n"); 5576 return; 5577 case RTW89_MAC_MRC_MALLOC_FAIL: 5578 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5579 "MRC C2H STS RPT: malloc fail\n"); 5580 return; 5581 case RTW89_MAC_MRC_SWITCH_CH_FAIL: 5582 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5583 "MRC C2H STS RPT: switch ch fail\n"); 5584 return; 5585 case RTW89_MAC_MRC_TXNULL0_FAIL: 5586 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5587 "MRC C2H STS RPT: tx null-0 fail\n"); 5588 return; 5589 case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL: 5590 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5591 "MRC C2H STS RPT: port func en fail\n"); 5592 return; 5593 default: 5594 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5595 "invalid MRC C2H STS RPT: status %d\n", status); 5596 return; 5597 } 5598 5599 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5600 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 5601 sch_idx, status, (u64)tsf_high << 32 | tsf_low); 5602 5603 if (next) 5604 return; 5605 5606 cond = RTW89_MRC_WAIT_COND(sch_idx, func); 5607 rtw89_complete_cond(wait, cond, &data); 5608 } 5609 5610 static void 5611 rtw89_mac_c2h_pwr_int_notify(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5612 { 5613 const struct rtw89_c2h_pwr_int_notify *c2h; 5614 struct rtw89_sta_link *rtwsta_link; 5615 struct ieee80211_sta *sta; 5616 struct rtw89_sta *rtwsta; 5617 u16 macid; 5618 bool ps; 5619 5620 c2h = (const struct rtw89_c2h_pwr_int_notify *)skb->data; 5621 macid = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_MACID); 5622 ps = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS); 5623 5624 rcu_read_lock(); 5625 5626 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 5627 if (unlikely(!rtwsta_link)) 5628 goto out; 5629 5630 rtwsta = rtwsta_link->rtwsta; 5631 if (ps) 5632 set_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5633 else 5634 clear_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5635 5636 sta = rtwsta_to_sta(rtwsta); 5637 ieee80211_sta_ps_transition(sta, ps); 5638 5639 out: 5640 rcu_read_unlock(); 5641 } 5642 5643 static 5644 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5645 struct sk_buff *c2h, u32 len) = { 5646 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5647 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5648 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5649 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 5650 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5651 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5652 [RTW89_MAC_C2H_FUNC_TX_DUTY_RPT] = rtw89_mac_c2h_tx_duty_rpt, 5653 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5654 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5655 }; 5656 5657 static 5658 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5659 struct sk_buff *c2h, u32 len) = { 5660 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5661 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5662 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5663 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5664 }; 5665 5666 static 5667 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5668 struct sk_buff *c2h, u32 len) = { 5669 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5670 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5671 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5672 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5673 }; 5674 5675 static 5676 void (* const rtw89_mac_c2h_mlo_handler[])(struct rtw89_dev *rtwdev, 5677 struct sk_buff *c2h, u32 len) = { 5678 [RTW89_MAC_C2H_FUNC_MLO_GET_TBL] = NULL, 5679 [RTW89_MAC_C2H_FUNC_MLO_EMLSR_TRANS_DONE] = NULL, 5680 [RTW89_MAC_C2H_FUNC_MLO_EMLSR_STA_CFG_DONE] = NULL, 5681 [RTW89_MAC_C2H_FUNC_MCMLO_RELINK_RPT] = NULL, 5682 [RTW89_MAC_C2H_FUNC_MCMLO_SN_SYNC_RPT] = NULL, 5683 [RTW89_MAC_C2H_FUNC_MLO_LINK_CFG_STAT] = rtw89_mac_c2h_mlo_link_cfg_stat, 5684 [RTW89_MAC_C2H_FUNC_MLO_DM_DBG_DUMP] = NULL, 5685 }; 5686 5687 static 5688 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 5689 struct sk_buff *c2h, u32 len) = { 5690 [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 5691 [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 5692 }; 5693 5694 static 5695 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev, 5696 struct sk_buff *c2h, u32 len) = { 5697 [RTW89_MAC_C2H_FUNC_AOAC_REPORT] = rtw89_mac_c2h_wow_aoac_rpt, 5698 }; 5699 5700 static 5701 void (* const rtw89_mac_c2h_ap_handler[])(struct rtw89_dev *rtwdev, 5702 struct sk_buff *c2h, u32 len) = { 5703 [RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY] = rtw89_mac_c2h_pwr_int_notify, 5704 }; 5705 5706 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 5707 struct sk_buff *skb) 5708 { 5709 const struct rtw89_c2h_scanofld *c2h = 5710 (const struct rtw89_c2h_scanofld *)skb->data; 5711 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5712 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 5713 struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(skb); 5714 struct rtw89_completion_data data = {}; 5715 unsigned int cond; 5716 u8 status, reason; 5717 5718 attr->is_scan_event = 1; 5719 attr->scan_seq = scan_info->seq; 5720 5721 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5722 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5723 data.err = status != RTW89_SCAN_STATUS_SUCCESS; 5724 5725 if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 5726 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 5727 cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 5728 else 5729 cond = RTW89_SCANOFLD_WAIT_COND_STOP; 5730 5731 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5732 } 5733 } 5734 5735 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5736 u8 class, u8 func) 5737 { 5738 switch (class) { 5739 default: 5740 return false; 5741 case RTW89_MAC_C2H_CLASS_INFO: 5742 switch (func) { 5743 default: 5744 return false; 5745 case RTW89_MAC_C2H_FUNC_REC_ACK: 5746 case RTW89_MAC_C2H_FUNC_DONE_ACK: 5747 return true; 5748 } 5749 case RTW89_MAC_C2H_CLASS_OFLD: 5750 switch (func) { 5751 default: 5752 return false; 5753 case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 5754 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 5755 return false; 5756 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 5757 return true; 5758 } 5759 case RTW89_MAC_C2H_CLASS_MCC: 5760 return true; 5761 case RTW89_MAC_C2H_CLASS_MLO: 5762 return true; 5763 case RTW89_MAC_C2H_CLASS_MRC: 5764 return true; 5765 case RTW89_MAC_C2H_CLASS_WOW: 5766 return true; 5767 case RTW89_MAC_C2H_CLASS_AP: 5768 switch (func) { 5769 default: 5770 return false; 5771 case RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY: 5772 return true; 5773 } 5774 } 5775 } 5776 5777 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5778 u32 len, u8 class, u8 func) 5779 { 5780 void (*handler)(struct rtw89_dev *rtwdev, 5781 struct sk_buff *c2h, u32 len) = NULL; 5782 5783 switch (class) { 5784 case RTW89_MAC_C2H_CLASS_INFO: 5785 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 5786 handler = rtw89_mac_c2h_info_handler[func]; 5787 break; 5788 case RTW89_MAC_C2H_CLASS_OFLD: 5789 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 5790 handler = rtw89_mac_c2h_ofld_handler[func]; 5791 break; 5792 case RTW89_MAC_C2H_CLASS_MCC: 5793 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 5794 handler = rtw89_mac_c2h_mcc_handler[func]; 5795 break; 5796 case RTW89_MAC_C2H_CLASS_MLO: 5797 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MLO) 5798 handler = rtw89_mac_c2h_mlo_handler[func]; 5799 break; 5800 case RTW89_MAC_C2H_CLASS_MRC: 5801 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 5802 handler = rtw89_mac_c2h_mrc_handler[func]; 5803 break; 5804 case RTW89_MAC_C2H_CLASS_WOW: 5805 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_WOW) 5806 handler = rtw89_mac_c2h_wow_handler[func]; 5807 break; 5808 case RTW89_MAC_C2H_CLASS_AP: 5809 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_AP) 5810 handler = rtw89_mac_c2h_ap_handler[func]; 5811 break; 5812 case RTW89_MAC_C2H_CLASS_FWDBG: 5813 case RTW89_MAC_C2H_CLASS_ROLE: 5814 return; 5815 default: 5816 rtw89_info(rtwdev, "MAC c2h class %d not support\n", class); 5817 return; 5818 } 5819 if (!handler) { 5820 rtw89_info(rtwdev, "MAC c2h class %d func %d not support\n", class, 5821 func); 5822 return; 5823 } 5824 handler(rtwdev, skb, len); 5825 } 5826 5827 static 5828 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 5829 enum rtw89_phy_idx phy_idx, 5830 u32 reg_base, u32 *cr) 5831 { 5832 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 5833 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 5834 5835 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 5836 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 5837 addr); 5838 goto error; 5839 } 5840 5841 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 5842 if (mode == RTW89_QTA_SCC) { 5843 rtw89_err(rtwdev, 5844 "[TXPWR] addr=0x%x but hw not enable\n", 5845 addr); 5846 goto error; 5847 } 5848 5849 *cr = addr; 5850 return true; 5851 5852 error: 5853 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 5854 addr, phy_idx); 5855 5856 return false; 5857 } 5858 5859 static 5860 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 5861 { 5862 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 5863 int ret; 5864 5865 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5866 if (ret) 5867 return ret; 5868 5869 if (!enable) { 5870 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 5871 return 0; 5872 } 5873 5874 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 5875 B_AX_APP_MAC_INFO_RPT | 5876 B_AX_APP_PLCP_HDR_RPT | 5877 B_AX_PPDU_STAT_RPT_CRC32); 5878 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 5879 RTW89_PRPT_DEST_HOST); 5880 5881 return 0; 5882 } 5883 5884 static 5885 void __rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 5886 { 5887 #define MAC_AX_TIME_TH_SH 5 5888 #define MAC_AX_LEN_TH_SH 4 5889 #define MAC_AX_TIME_TH_MAX 255 5890 #define MAC_AX_LEN_TH_MAX 255 5891 #define MAC_AX_TIME_TH_DEF 88 5892 #define MAC_AX_LEN_TH_DEF 4080 5893 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5894 struct ieee80211_hw *hw = rtwdev->hw; 5895 u32 rts_threshold = hw->wiphy->rts_threshold; 5896 u32 time_th, len_th; 5897 u32 reg; 5898 5899 if (rts_threshold == (u32)-1) { 5900 time_th = MAC_AX_TIME_TH_DEF; 5901 len_th = MAC_AX_LEN_TH_DEF; 5902 } else { 5903 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 5904 len_th = rts_threshold; 5905 } 5906 5907 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 5908 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 5909 5910 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 5911 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 5912 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 5913 } 5914 5915 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev) 5916 { 5917 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 5918 if (rtwdev->dbcc_en) 5919 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_1); 5920 } 5921 5922 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 5923 { 5924 bool empty; 5925 int ret; 5926 5927 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5928 return; 5929 5930 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 5931 10000, 200000, false, rtwdev); 5932 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 5933 rtw89_info(rtwdev, "timed out to flush queues\n"); 5934 } 5935 5936 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 5937 { 5938 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 5939 u8 val; 5940 u16 val16; 5941 u32 val32; 5942 int ret; 5943 5944 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 5945 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5946 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 5947 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 5948 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 5949 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 5950 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5951 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 5952 5953 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 5954 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 5955 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 5956 5957 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 5958 if (ret) { 5959 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 5960 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 5961 return ret; 5962 } 5963 val32 = val32 & B_AX_WL_RX_CTRL; 5964 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 5965 if (ret) { 5966 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 5967 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 5968 return ret; 5969 } 5970 5971 switch (coex->pta_mode) { 5972 case RTW89_MAC_AX_COEX_RTK_MODE: 5973 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5974 val &= ~B_AX_BTMODE_MASK; 5975 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 5976 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5977 5978 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 5979 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 5980 5981 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 5982 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 5983 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 5984 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 5985 break; 5986 case RTW89_MAC_AX_COEX_CSR_MODE: 5987 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5988 val &= ~B_AX_BTMODE_MASK; 5989 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 5990 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5991 5992 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 5993 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 5994 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 5995 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 5996 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 5997 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 5998 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 5999 val16 |= B_AX_ENHANCED_BT; 6000 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 6001 6002 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 6003 break; 6004 default: 6005 return -EINVAL; 6006 } 6007 6008 switch (coex->direction) { 6009 case RTW89_MAC_AX_COEX_INNER: 6010 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6011 val = (val & ~BIT(2)) | BIT(1); 6012 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6013 break; 6014 case RTW89_MAC_AX_COEX_OUTPUT: 6015 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6016 val = val | BIT(1) | BIT(0); 6017 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6018 break; 6019 case RTW89_MAC_AX_COEX_INPUT: 6020 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6021 val = val & ~(BIT(2) | BIT(1)); 6022 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6023 break; 6024 default: 6025 return -EINVAL; 6026 } 6027 6028 return 0; 6029 } 6030 EXPORT_SYMBOL(rtw89_mac_coex_init); 6031 6032 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 6033 const struct rtw89_mac_ax_coex *coex) 6034 { 6035 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 6036 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 6037 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 6038 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 6039 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 6040 6041 switch (coex->pta_mode) { 6042 case RTW89_MAC_AX_COEX_RTK_MODE: 6043 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 6044 MAC_AX_RTK_MODE); 6045 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 6046 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 6047 break; 6048 case RTW89_MAC_AX_COEX_CSR_MODE: 6049 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 6050 MAC_AX_CSR_MODE); 6051 break; 6052 default: 6053 return -EINVAL; 6054 } 6055 6056 return 0; 6057 } 6058 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 6059 6060 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6061 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6062 { 6063 u32 val = 0, ret; 6064 6065 if (gnt_cfg->band[0].gnt_bt) 6066 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 6067 6068 if (gnt_cfg->band[0].gnt_bt_sw_en) 6069 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 6070 6071 if (gnt_cfg->band[0].gnt_wl) 6072 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 6073 6074 if (gnt_cfg->band[0].gnt_wl_sw_en) 6075 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 6076 6077 if (gnt_cfg->band[1].gnt_bt) 6078 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 6079 6080 if (gnt_cfg->band[1].gnt_bt_sw_en) 6081 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 6082 6083 if (gnt_cfg->band[1].gnt_wl) 6084 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 6085 6086 if (gnt_cfg->band[1].gnt_wl_sw_en) 6087 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 6088 6089 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 6090 if (ret) { 6091 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6092 rtw89_err(rtwdev, "Write LTE fail!\n"); 6093 return ret; 6094 } 6095 6096 return 0; 6097 } 6098 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 6099 6100 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 6101 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6102 { 6103 u32 val = 0; 6104 6105 if (gnt_cfg->band[0].gnt_bt) 6106 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 6107 B_AX_GNT_BT_TX_VAL; 6108 else 6109 val |= B_AX_WL_ACT_VAL; 6110 6111 if (gnt_cfg->band[0].gnt_bt_sw_en) 6112 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 6113 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 6114 6115 if (gnt_cfg->band[0].gnt_wl) 6116 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 6117 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 6118 6119 if (gnt_cfg->band[0].gnt_wl_sw_en) 6120 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 6121 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 6122 6123 if (gnt_cfg->band[1].gnt_bt) 6124 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 6125 B_AX_GNT_BT_TX_VAL; 6126 else 6127 val |= B_AX_WL_ACT_VAL; 6128 6129 if (gnt_cfg->band[1].gnt_bt_sw_en) 6130 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 6131 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 6132 6133 if (gnt_cfg->band[1].gnt_wl) 6134 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 6135 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 6136 6137 if (gnt_cfg->band[1].gnt_wl_sw_en) 6138 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 6139 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 6140 6141 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 6142 6143 return 0; 6144 } 6145 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 6146 6147 static 6148 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 6149 { 6150 u32 reg; 6151 u16 val; 6152 int ret; 6153 6154 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 6155 if (ret) 6156 return ret; 6157 6158 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 6159 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 6160 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 6161 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 6162 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 6163 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 6164 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 6165 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 6166 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 6167 B_AX_PLT_EN; 6168 rtw89_write16(rtwdev, reg, val); 6169 6170 return 0; 6171 } 6172 6173 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 6174 { 6175 u32 fw_sb; 6176 6177 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 6178 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 6179 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 6180 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6181 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 6182 else 6183 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 6184 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 6185 val = B_AX_TOGGLE | 6186 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 6187 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 6188 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 6189 fsleep(1000); /* avoid BT FW loss information */ 6190 } 6191 6192 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 6193 { 6194 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 6195 } 6196 6197 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6198 { 6199 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 6200 6201 val = wl ? val | BIT(2) : val & ~BIT(2); 6202 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 6203 6204 return 0; 6205 } 6206 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 6207 6208 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 6209 { 6210 struct rtw89_btc *btc = &rtwdev->btc; 6211 struct rtw89_btc_dm *dm = &btc->dm; 6212 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 6213 int i; 6214 6215 if (wl) 6216 return 0; 6217 6218 for (i = 0; i < RTW89_PHY_NUM; i++) { 6219 g[i].gnt_bt_sw_en = 1; 6220 g[i].gnt_bt = 1; 6221 g[i].gnt_wl_sw_en = 1; 6222 g[i].gnt_wl = 0; 6223 } 6224 6225 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 6226 } 6227 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 6228 6229 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 6230 { 6231 const struct rtw89_chip_info *chip = rtwdev->chip; 6232 u8 val = 0; 6233 6234 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) 6235 return false; 6236 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6237 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 6238 B_AX_LTE_MUX_CTRL_PATH >> 24); 6239 6240 return !!val; 6241 } 6242 6243 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 6244 { 6245 u32 reg; 6246 u16 cnt; 6247 6248 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 6249 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 6250 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 6251 6252 return cnt; 6253 } 6254 6255 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 6256 bool keep) 6257 { 6258 u32 reg; 6259 6260 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 6261 return; 6262 6263 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 6264 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6265 if (keep) { 6266 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6267 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6268 BFRP_RX_STANDBY_TIMER_KEEP); 6269 } else { 6270 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6271 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6272 BFRP_RX_STANDBY_TIMER_RELEASE); 6273 } 6274 } 6275 6276 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 6277 { 6278 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6279 u32 reg; 6280 u32 mask = mac->bfee_ctrl.mask; 6281 6282 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 6283 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 6284 if (en) { 6285 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6286 rtw89_write32_set(rtwdev, reg, mask); 6287 } else { 6288 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6289 rtw89_write32_clr(rtwdev, reg, mask); 6290 } 6291 } 6292 6293 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 6294 { 6295 u32 reg; 6296 u32 val32; 6297 int ret; 6298 6299 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6300 if (ret) 6301 return ret; 6302 6303 /* AP mode set tx gid to 63 */ 6304 /* STA mode set tx gid to 0(default) */ 6305 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 6306 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 6307 6308 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 6309 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 6310 6311 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6312 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 6313 rtw89_write32(rtwdev, reg, val32); 6314 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 6315 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 6316 6317 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6318 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 6319 B_AX_BFMEE_USE_NSTS | 6320 B_AX_BFMEE_CSI_GID_SEL | 6321 B_AX_BFMEE_CSI_FORCE_RETE_EN); 6322 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 6323 rtw89_write32(rtwdev, reg, 6324 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 6325 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 6326 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 6327 6328 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 6329 rtw89_write32_set(rtwdev, reg, 6330 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 6331 6332 return 0; 6333 } 6334 6335 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 6336 struct rtw89_vif_link *rtwvif_link, 6337 struct rtw89_sta_link *rtwsta_link) 6338 { 6339 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 6340 struct ieee80211_link_sta *link_sta; 6341 u8 mac_idx = rtwvif_link->mac_idx; 6342 u8 port_sel = rtwvif_link->port; 6343 u8 sound_dim = 3, t; 6344 u8 *phy_cap; 6345 u32 reg; 6346 u16 val; 6347 int ret; 6348 6349 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6350 if (ret) 6351 return ret; 6352 6353 rcu_read_lock(); 6354 6355 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6356 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; 6357 6358 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6359 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 6360 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 6361 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 6362 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 6363 phy_cap[5]); 6364 sound_dim = min(sound_dim, t); 6365 } 6366 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6367 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 6368 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 6369 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 6370 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 6371 link_sta->vht_cap.cap); 6372 sound_dim = min(sound_dim, t); 6373 } 6374 nc = min(nc, sound_dim); 6375 nr = min(nr, sound_dim); 6376 6377 rcu_read_unlock(); 6378 6379 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6380 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6381 6382 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 6383 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 6384 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 6385 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 6386 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 6387 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 6388 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 6389 6390 if (port_sel == 0) 6391 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6392 else 6393 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 6394 6395 rtw89_write16(rtwdev, reg, val); 6396 6397 return 0; 6398 } 6399 6400 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 6401 struct rtw89_vif_link *rtwvif_link, 6402 struct rtw89_sta_link *rtwsta_link) 6403 { 6404 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 6405 struct ieee80211_link_sta *link_sta; 6406 u8 mac_idx = rtwvif_link->mac_idx; 6407 u32 reg; 6408 int ret; 6409 6410 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6411 if (ret) 6412 return ret; 6413 6414 rcu_read_lock(); 6415 6416 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6417 6418 if (link_sta->he_cap.has_he) { 6419 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 6420 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 6421 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 6422 } 6423 if (link_sta->vht_cap.vht_supported) { 6424 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 6425 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 6426 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 6427 } 6428 if (link_sta->ht_cap.ht_supported) { 6429 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 6430 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 6431 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 6432 } 6433 6434 rcu_read_unlock(); 6435 6436 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6437 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6438 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 6439 rtw89_write32(rtwdev, 6440 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 6441 rrsc); 6442 6443 return 0; 6444 } 6445 6446 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 6447 struct rtw89_vif_link *rtwvif_link, 6448 struct rtw89_sta_link *rtwsta_link) 6449 { 6450 struct ieee80211_link_sta *link_sta; 6451 bool has_beamformer_cap; 6452 6453 rcu_read_lock(); 6454 6455 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6456 has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta); 6457 6458 rcu_read_unlock(); 6459 6460 if (has_beamformer_cap) { 6461 rtw89_debug(rtwdev, RTW89_DBG_BF, 6462 "initialize bfee for new association\n"); 6463 rtw89_mac_init_bfee_ax(rtwdev, rtwvif_link->mac_idx); 6464 rtw89_mac_set_csi_para_reg_ax(rtwdev, rtwvif_link, rtwsta_link); 6465 rtw89_mac_csi_rrsc_ax(rtwdev, rtwvif_link, rtwsta_link); 6466 } 6467 } 6468 6469 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, 6470 struct rtw89_vif_link *rtwvif_link, 6471 struct rtw89_sta_link *rtwsta_link) 6472 { 6473 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, false); 6474 } 6475 6476 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6477 struct ieee80211_bss_conf *conf) 6478 { 6479 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 6480 struct rtw89_vif_link *rtwvif_link; 6481 u8 mac_idx; 6482 __le32 *p; 6483 6484 rtwvif_link = rtwvif->links[conf->link_id]; 6485 if (unlikely(!rtwvif_link)) { 6486 rtw89_err(rtwdev, 6487 "%s: rtwvif link (link_id %u) is not active\n", 6488 __func__, conf->link_id); 6489 return; 6490 } 6491 6492 mac_idx = rtwvif_link->mac_idx; 6493 6494 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 6495 6496 p = (__le32 *)conf->mu_group.membership; 6497 rtw89_write32(rtwdev, 6498 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 6499 le32_to_cpu(p[0])); 6500 rtw89_write32(rtwdev, 6501 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 6502 le32_to_cpu(p[1])); 6503 6504 p = (__le32 *)conf->mu_group.position; 6505 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 6506 le32_to_cpu(p[0])); 6507 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 6508 le32_to_cpu(p[1])); 6509 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 6510 le32_to_cpu(p[2])); 6511 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 6512 le32_to_cpu(p[3])); 6513 } 6514 6515 struct rtw89_mac_bf_monitor_iter_data { 6516 struct rtw89_dev *rtwdev; 6517 struct rtw89_sta_link *down_rtwsta_link; 6518 int count; 6519 }; 6520 6521 static 6522 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 6523 { 6524 struct rtw89_mac_bf_monitor_iter_data *iter_data = 6525 (struct rtw89_mac_bf_monitor_iter_data *)data; 6526 struct rtw89_sta_link *down_rtwsta_link = iter_data->down_rtwsta_link; 6527 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6528 struct ieee80211_link_sta *link_sta; 6529 struct rtw89_sta_link *rtwsta_link; 6530 bool has_beamformer_cap = false; 6531 int *count = &iter_data->count; 6532 unsigned int link_id; 6533 6534 rcu_read_lock(); 6535 6536 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6537 if (rtwsta_link == down_rtwsta_link) 6538 continue; 6539 6540 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 6541 if (rtw89_sta_has_beamformer_cap(link_sta)) { 6542 has_beamformer_cap = true; 6543 break; 6544 } 6545 } 6546 6547 if (has_beamformer_cap) 6548 (*count)++; 6549 6550 rcu_read_unlock(); 6551 } 6552 6553 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 6554 struct rtw89_sta_link *rtwsta_link, 6555 bool disconnect) 6556 { 6557 struct rtw89_mac_bf_monitor_iter_data data; 6558 6559 data.rtwdev = rtwdev; 6560 data.down_rtwsta_link = disconnect ? rtwsta_link : NULL; 6561 data.count = 0; 6562 ieee80211_iterate_stations_atomic(rtwdev->hw, 6563 rtw89_mac_bf_monitor_calc_iter, 6564 &data); 6565 6566 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 6567 if (data.count) 6568 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6569 else 6570 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6571 } 6572 6573 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 6574 { 6575 struct rtw89_traffic_stats *stats = &rtwdev->stats; 6576 struct rtw89_vif_link *rtwvif_link; 6577 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 6578 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6579 struct rtw89_vif *rtwvif; 6580 bool keep_timer = true; 6581 unsigned int link_id; 6582 bool old_keep_timer; 6583 6584 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6585 6586 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 6587 keep_timer = false; 6588 6589 if (keep_timer != old_keep_timer) { 6590 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6591 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6592 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif_link->mac_idx, 6593 keep_timer); 6594 } 6595 6596 if (en == old) 6597 return; 6598 6599 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6600 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6601 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, en); 6602 } 6603 6604 static int 6605 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6606 u32 tx_time) 6607 { 6608 #define MAC_AX_DFLT_TX_TIME 5280 6609 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6610 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6611 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 6612 u32 reg; 6613 int ret = 0; 6614 6615 if (rtwsta_link->cctl_tx_time) { 6616 rtwsta_link->ampdu_max_time = (max_tx_time - 512) >> 9; 6617 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6618 } else { 6619 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6620 if (ret) { 6621 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 6622 return ret; 6623 } 6624 6625 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_limit.addr, mac_idx); 6626 rtw89_write32_mask(rtwdev, reg, mac->agg_limit.mask, 6627 max_tx_time >> 5); 6628 } 6629 6630 return ret; 6631 } 6632 6633 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6634 bool resume, u32 tx_time) 6635 { 6636 int ret = 0; 6637 6638 if (!resume) { 6639 rtwsta_link->cctl_tx_time = true; 6640 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6641 } else { 6642 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6643 rtwsta_link->cctl_tx_time = false; 6644 } 6645 6646 return ret; 6647 } 6648 6649 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6650 u32 *tx_time) 6651 { 6652 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6653 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6654 u32 reg; 6655 int ret = 0; 6656 6657 if (rtwsta_link->cctl_tx_time) { 6658 *tx_time = (rtwsta_link->ampdu_max_time + 1) << 9; 6659 } else { 6660 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6661 if (ret) { 6662 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 6663 return ret; 6664 } 6665 6666 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_limit.addr, mac_idx); 6667 *tx_time = rtw89_read32_mask(rtwdev, reg, mac->agg_limit.mask) << 5; 6668 } 6669 6670 return ret; 6671 } 6672 6673 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 6674 struct rtw89_sta_link *rtwsta_link, 6675 bool resume, u8 tx_retry) 6676 { 6677 int ret = 0; 6678 6679 rtwsta_link->data_tx_cnt_lmt = tx_retry; 6680 6681 if (!resume) { 6682 rtwsta_link->cctl_tx_retry_limit = true; 6683 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6684 } else { 6685 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6686 rtwsta_link->cctl_tx_retry_limit = false; 6687 } 6688 6689 return ret; 6690 } 6691 6692 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 6693 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry) 6694 { 6695 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6696 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6697 u32 reg; 6698 int ret = 0; 6699 6700 if (rtwsta_link->cctl_tx_retry_limit) { 6701 *tx_retry = rtwsta_link->data_tx_cnt_lmt; 6702 } else { 6703 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6704 if (ret) { 6705 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 6706 return ret; 6707 } 6708 6709 reg = rtw89_mac_reg_by_idx(rtwdev, mac->txcnt_limit.addr, mac_idx); 6710 *tx_retry = rtw89_read32_mask(rtwdev, reg, mac->txcnt_limit.mask); 6711 } 6712 6713 return ret; 6714 } 6715 6716 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 6717 struct rtw89_vif_link *rtwvif_link, bool en) 6718 { 6719 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6720 u8 mac_idx = rtwvif_link->mac_idx; 6721 u16 set = mac->muedca_ctrl.mask; 6722 u32 reg; 6723 u32 ret; 6724 6725 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6726 if (ret) 6727 return ret; 6728 6729 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 6730 if (en) 6731 rtw89_write16_set(rtwdev, reg, set); 6732 else 6733 rtw89_write16_clr(rtwdev, reg, set); 6734 6735 return 0; 6736 } 6737 6738 static 6739 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 6740 { 6741 u32 val32; 6742 int ret; 6743 6744 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6745 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 6746 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 6747 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 6748 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6749 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6750 6751 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6752 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6753 if (ret) { 6754 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 6755 offset, val, mask); 6756 return ret; 6757 } 6758 6759 return 0; 6760 } 6761 6762 static 6763 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 6764 { 6765 u32 val32; 6766 int ret; 6767 6768 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6769 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 6770 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 6771 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 6772 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6773 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6774 6775 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6776 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6777 if (ret) { 6778 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 6779 return ret; 6780 } 6781 6782 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 6783 6784 return 0; 6785 } 6786 6787 static 6788 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, 6789 struct rtw89_vif_link *rtwvif_link, 6790 struct rtw89_sta_link *rtwsta_link) 6791 { 6792 static const enum rtw89_pkt_drop_sel sels[] = { 6793 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 6794 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 6795 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 6796 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 6797 }; 6798 struct rtw89_pkt_drop_params params = {0}; 6799 int i; 6800 6801 params.mac_band = rtwvif_link->mac_idx; 6802 params.macid = rtwsta_link->mac_id; 6803 params.port = rtwvif_link->port; 6804 params.mbssid = 0; 6805 params.tf_trs = rtwvif_link->trigger; 6806 6807 for (i = 0; i < ARRAY_SIZE(sels); i++) { 6808 params.sel = sels[i]; 6809 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6810 } 6811 } 6812 6813 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 6814 { 6815 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6816 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6817 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6818 struct rtw89_vif_link *rtwvif_link; 6819 struct rtw89_sta_link *rtwsta_link; 6820 struct rtw89_vif *target = data; 6821 unsigned int link_id; 6822 6823 if (rtwvif != target) 6824 return; 6825 6826 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6827 rtwvif_link = rtwsta_link->rtwvif_link; 6828 rtw89_mac_pkt_drop_sta(rtwdev, rtwvif_link, rtwsta_link); 6829 } 6830 } 6831 6832 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 6833 { 6834 ieee80211_iterate_stations_atomic(rtwdev->hw, 6835 rtw89_mac_pkt_drop_vif_iter, 6836 rtwvif); 6837 } 6838 6839 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 6840 enum rtw89_mac_idx band) 6841 { 6842 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6843 struct rtw89_pkt_drop_params params = {0}; 6844 bool empty; 6845 int i, ret = 0, try_cnt = 3; 6846 6847 params.mac_band = band; 6848 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 6849 6850 for (i = 0; i < try_cnt; i++) { 6851 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 6852 50000, false, rtwdev); 6853 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 6854 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6855 else 6856 return 0; 6857 } 6858 return ret; 6859 } 6860 6861 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 6862 { 6863 struct rtw89_mac_h2c_info h2c_info = {}; 6864 struct rtw89_mac_c2h_info c2h_info = {}; 6865 u32 ret; 6866 6867 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 6868 return 0; 6869 6870 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; 6871 h2c_info.content_len = sizeof(h2c_info.u.hdr); 6872 h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); 6873 6874 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 6875 if (ret) 6876 return ret; 6877 6878 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) 6879 ret = -EINVAL; 6880 6881 return ret; 6882 } 6883 6884 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 6885 { 6886 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6887 const struct rtw89_chip_info *chip = rtwdev->chip; 6888 int ret; 6889 6890 if (enable_wow) { 6891 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 6892 if (ret) { 6893 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6894 return ret; 6895 } 6896 6897 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6898 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6899 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 6900 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 6901 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 6902 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 6903 rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 6904 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 6905 6906 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 6907 return 0; 6908 6909 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6910 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 6911 else 6912 rtw89_write32_set(rtwdev, R_AX_DBG_WOW, 6913 B_AX_DBG_WOW_CPU_IO_RX_EN); 6914 } else { 6915 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 6916 if (ret) { 6917 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6918 return ret; 6919 } 6920 6921 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6922 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6923 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 6924 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 6925 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 6926 } 6927 6928 return 0; 6929 } 6930 6931 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 6932 { 6933 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 6934 6935 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 6936 } 6937 6938 static 6939 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 6940 bool h2c_or_fwdl) 6941 { 6942 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 6943 u32 timeout; 6944 u8 val; 6945 6946 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 6947 timeout = FWDL_WAIT_CNT_USB; 6948 else 6949 timeout = FWDL_WAIT_CNT; 6950 6951 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 6952 1, timeout, false, 6953 rtwdev, R_AX_WCPU_FW_CTRL); 6954 } 6955 6956 static 6957 void rtw89_fwdl_secure_idmem_share_mode_ax(struct rtw89_dev *rtwdev, u8 mode) 6958 { 6959 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 6960 6961 if (!sec->secure_boot) 6962 return; 6963 6964 rtw89_write32_mask(rtwdev, R_AX_WCPU_FW_CTRL, 6965 B_AX_IDMEM_SHARE_MODE_RECORD_MASK, mode); 6966 rtw89_write32_set(rtwdev, R_AX_WCPU_FW_CTRL, 6967 B_AX_IDMEM_SHARE_MODE_RECORD_VALID); 6968 } 6969 6970 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 6971 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 6972 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 6973 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 6974 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 6975 .mem_page_size = MAC_MEM_DUMP_PAGE_SIZE_AX, 6976 .rx_fltr = R_AX_RX_FLTR_OPT, 6977 .port_base = &rtw89_port_base_ax, 6978 .agg_len_ht = R_AX_AGG_LEN_HT_0, 6979 .ps_status = R_AX_PPWRBIT_SETTING, 6980 6981 .muedca_ctrl = { 6982 .addr = R_AX_MUEDCA_EN, 6983 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 6984 }, 6985 .bfee_ctrl = { 6986 .addr = R_AX_BFMEE_RESP_OPTION, 6987 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 6988 B_AX_BFMEE_HE_NDPA_EN, 6989 }, 6990 .narrow_bw_ru_dis = { 6991 .addr = R_AX_RXTRIG_TEST_USER_2, 6992 .mask = B_AX_RXTRIG_RU26_DIS, 6993 }, 6994 .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 6995 .agg_limit = {.addr = R_AX_AMPDU_AGG_LIMIT, .mask = B_AX_AMPDU_MAX_TIME_MASK,}, 6996 .txcnt_limit = {.addr = R_AX_TXCNT, .mask = B_AX_L_TXCNT_LMT_MASK,}, 6997 6998 .check_mac_en = rtw89_mac_check_mac_en_ax, 6999 .sys_init = sys_init_ax, 7000 .trx_init = trx_init_ax, 7001 .hci_func_en = rtw89_mac_hci_func_en_ax, 7002 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 7003 .dle_func_en = dle_func_en_ax, 7004 .dle_clk_en = dle_clk_en_ax, 7005 .bf_assoc = rtw89_mac_bf_assoc_ax, 7006 7007 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 7008 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 7009 .cfg_phy_rpt = NULL, 7010 7011 .dle_mix_cfg = dle_mix_cfg_ax, 7012 .chk_dle_rdy = chk_dle_rdy_ax, 7013 .dle_buf_req = dle_buf_req_ax, 7014 .hfc_func_en = hfc_func_en_ax, 7015 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 7016 .hfc_mix_cfg = hfc_mix_cfg_ax, 7017 .hfc_get_mix_info = hfc_get_mix_info_ax, 7018 .wde_quota_cfg = wde_quota_cfg_ax, 7019 .ple_quota_cfg = ple_quota_cfg_ax, 7020 .set_cpuio = set_cpuio_ax, 7021 .dle_quota_change = dle_quota_change_ax, 7022 7023 .disable_cpu = rtw89_mac_disable_cpu_ax, 7024 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 7025 .fwdl_get_status = rtw89_fw_get_rdy_ax, 7026 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 7027 .fwdl_secure_idmem_share_mode = rtw89_fwdl_secure_idmem_share_mode_ax, 7028 .parse_efuse_map = rtw89_parse_efuse_map_ax, 7029 .parse_phycap_map = rtw89_parse_phycap_map_ax, 7030 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 7031 .efuse_read_fw_secure = rtw89_efuse_read_fw_secure_ax, 7032 7033 .cfg_plt = rtw89_mac_cfg_plt_ax, 7034 .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 7035 7036 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 7037 7038 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 7039 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 7040 7041 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 7042 .dump_err_status = rtw89_mac_dump_err_status_ax, 7043 7044 .is_txq_empty = mac_is_txq_empty_ax, 7045 7046 .prep_chan_list = rtw89_hw_scan_prep_chan_list_ax, 7047 .free_chan_list = rtw89_hw_scan_free_chan_list_ax, 7048 .add_chan_list = rtw89_hw_scan_add_chan_list_ax, 7049 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_ax, 7050 .scan_offload = rtw89_fw_h2c_scan_offload_ax, 7051 7052 .wow_config_mac = rtw89_wow_config_mac_ax, 7053 }; 7054 EXPORT_SYMBOL(rtw89_mac_gen_ax); 7055