1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "util.h" 15 16 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 17 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 18 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 19 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 20 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 21 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 22 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 26 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 29 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 31 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 35 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 36 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 37 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 38 }; 39 40 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 41 u32 val, enum rtw89_mac_mem_sel sel) 42 { 43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44 u32 addr = mac->mem_base_addrs[sel] + offset; 45 46 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 47 rtw89_write32(rtwdev, mac->indir_access_addr, val); 48 } 49 50 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 51 enum rtw89_mac_mem_sel sel) 52 { 53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 54 u32 addr = mac->mem_base_addrs[sel] + offset; 55 56 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 57 return rtw89_read32(rtwdev, mac->indir_access_addr); 58 } 59 60 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 61 enum rtw89_mac_hwmod_sel sel) 62 { 63 u32 val, r_val; 64 65 if (sel == RTW89_DMAC_SEL) { 66 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 67 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 69 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 70 val = B_AX_CMAC_EN; 71 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 72 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 73 val = B_AX_CMAC1_FEN; 74 } else { 75 return -EINVAL; 76 } 77 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 78 (val & r_val) != val) 79 return -EFAULT; 80 81 return 0; 82 } 83 84 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 85 { 86 u8 lte_ctrl; 87 int ret; 88 89 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 90 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 91 if (ret) 92 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 93 94 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 95 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 96 97 return ret; 98 } 99 100 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 101 { 102 u8 lte_ctrl; 103 int ret; 104 105 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 106 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 107 if (ret) 108 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 109 110 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 111 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 112 113 return ret; 114 } 115 116 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 117 { 118 u32 ctrl_reg, data_reg, ctrl_data; 119 u32 val; 120 int ret; 121 122 switch (ctrl->type) { 123 case DLE_CTRL_TYPE_WDE: 124 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 125 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 126 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 127 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 128 B_AX_WDE_DFI_ACTIVE; 129 break; 130 case DLE_CTRL_TYPE_PLE: 131 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 132 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 133 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 134 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 135 B_AX_PLE_DFI_ACTIVE; 136 break; 137 default: 138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 139 return -EINVAL; 140 } 141 142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 143 144 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 145 1, 1000, false, rtwdev, ctrl_reg); 146 if (ret) { 147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 148 ctrl_reg, ctrl_data); 149 return ret; 150 } 151 152 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 153 return 0; 154 } 155 156 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 157 struct rtw89_mac_dle_dfi_quota *quota) 158 { 159 struct rtw89_mac_dle_dfi_ctrl ctrl; 160 int ret; 161 162 ctrl.type = quota->dle_type; 163 ctrl.target = DLE_DFI_TYPE_QUOTA; 164 ctrl.addr = quota->qtaid; 165 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 166 if (ret) { 167 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 168 return ret; 169 } 170 171 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 172 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 173 return 0; 174 } 175 176 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 177 struct rtw89_mac_dle_dfi_qempty *qempty) 178 { 179 struct rtw89_mac_dle_dfi_ctrl ctrl; 180 u32 ret; 181 182 ctrl.type = qempty->dle_type; 183 ctrl.target = DLE_DFI_TYPE_QEMPTY; 184 ctrl.addr = qempty->grpsel; 185 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 186 if (ret) { 187 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 188 return ret; 189 } 190 191 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 192 return 0; 193 } 194 195 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 196 { 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 209 } 210 211 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 212 { 213 struct rtw89_mac_dle_dfi_qempty qempty; 214 struct rtw89_mac_dle_dfi_quota quota; 215 struct rtw89_mac_dle_dfi_ctrl ctrl; 216 u32 val, not_empty, i; 217 int ret; 218 219 qempty.dle_type = DLE_CTRL_TYPE_PLE; 220 qempty.grpsel = 0; 221 qempty.qempty = ~(u32)0; 222 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 223 if (ret) 224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 225 else 226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 227 228 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 229 if (!(not_empty & BIT(0))) 230 continue; 231 ctrl.type = DLE_CTRL_TYPE_PLE; 232 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 233 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 234 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 235 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 236 if (ret) 237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 238 else 239 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 240 u32_get_bits(ctrl.out_data, 241 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 242 } 243 244 quota.dle_type = DLE_CTRL_TYPE_PLE; 245 quota.qtaid = 6; 246 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 247 if (ret) 248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 249 else 250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 251 quota.rsv_pgnum, quota.use_pgnum); 252 253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 255 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 257 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 258 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 259 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 260 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 261 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 262 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 263 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 264 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 265 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 266 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 267 268 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 269 quota.dle_type = DLE_CTRL_TYPE_PLE; 270 quota.qtaid = 7; 271 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 272 if (ret) 273 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 274 else 275 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 276 quota.rsv_pgnum, quota.use_pgnum); 277 278 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 279 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 280 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 282 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 283 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 284 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 285 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 286 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 287 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 288 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 289 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 290 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 291 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 292 } 293 294 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 295 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 298 299 dump_err_status_dispatcher_ax(rtwdev); 300 } 301 302 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 303 enum mac_ax_err_info err) 304 { 305 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 306 u32 dbg, event; 307 308 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 309 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 310 311 switch (event) { 312 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 313 rtw89_info(rtwdev, "quota lost!\n"); 314 mac->dump_qta_lost(rtwdev); 315 break; 316 default: 317 break; 318 } 319 } 320 321 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 322 { 323 const struct rtw89_chip_info *chip = rtwdev->chip; 324 u32 dmac_err; 325 int i, ret; 326 327 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 328 if (ret) { 329 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 330 return; 331 } 332 333 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 334 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 335 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 337 338 if (dmac_err) { 339 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 341 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 343 if (chip->chip_id == RTL8852C) { 344 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 345 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 346 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 348 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 352 } 353 } 354 355 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 356 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 357 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 360 if (chip->chip_id == RTL8852C) 361 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 363 else 364 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 365 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 366 } 367 368 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 369 if (chip->chip_id == RTL8852C) { 370 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 371 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 372 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 374 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 376 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 378 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 380 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 382 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 384 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 386 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 388 389 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 390 B_AX_DBG_SEL0, 0x8B); 391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392 B_AX_DBG_SEL1, 0x8B); 393 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 394 B_AX_SEL_0XC0_MASK, 1); 395 for (i = 0; i < 0x10; i++) { 396 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 397 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 398 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 399 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 400 } 401 } else if (chip->chip_id == RTL8922A) { 402 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 403 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 406 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 407 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 408 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 409 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 410 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 411 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 412 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 413 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 414 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 415 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 416 } else { 417 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 419 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 421 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 423 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 425 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 427 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 429 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 430 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 431 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 432 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 433 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 435 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 437 } 438 } 439 440 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 441 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 442 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 445 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 449 } 450 451 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 452 if (chip->chip_id == RTL8922A) { 453 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 454 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 455 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 456 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 457 } else { 458 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 459 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 462 } 463 } 464 465 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 466 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 468 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 470 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 471 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 472 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 474 } 475 476 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 477 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 478 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 479 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 486 } else { 487 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 491 } 492 } 493 494 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 495 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 501 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 503 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 509 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 510 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 515 if (chip->chip_id == RTL8922A) { 516 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 517 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 520 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 521 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 522 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 524 } else { 525 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 526 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 527 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 529 if (chip->chip_id == RTL8852C) { 530 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 531 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 532 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 533 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 534 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 535 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 536 } else { 537 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 538 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 543 } 544 } 545 } 546 547 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 548 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 549 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 552 } 553 554 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 555 if (chip->chip_id == RTL8922A) { 556 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 557 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 558 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 559 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 560 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 561 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 562 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 563 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 564 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 565 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 566 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 567 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 568 } else { 569 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 570 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 573 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 574 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 577 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 578 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 581 } 582 } 583 584 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 585 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 586 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 587 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 590 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 591 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 594 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 595 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 598 } else { 599 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 600 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 601 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 602 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 605 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 606 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 609 } 610 if (chip->chip_id == RTL8922A) { 611 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 612 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 615 } 616 } 617 618 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 619 if (chip->chip_id == RTL8922A) { 620 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 621 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 624 } else if (chip->chip_id == RTL8852C) { 625 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 626 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 629 } 630 } 631 632 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 633 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 634 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 635 RTW89_MAC_MEM_AXIDMA)); 636 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 637 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 638 RTW89_MAC_MEM_AXIDMA)); 639 } 640 641 if (dmac_err & B_BE_MLO_ERR_INT) { 642 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 643 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 644 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 646 } 647 648 if (dmac_err & B_BE_PLRLS_ERR_INT) { 649 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 650 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 653 } 654 } 655 656 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 657 u8 band) 658 { 659 const struct rtw89_chip_info *chip = rtwdev->chip; 660 u32 offset = 0; 661 u32 cmac_err; 662 int ret; 663 664 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 665 if (ret) { 666 if (band) 667 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 668 else 669 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 670 return; 671 } 672 673 if (band) 674 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 675 676 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 677 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 678 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 679 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 680 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 681 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 682 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 683 684 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 685 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 686 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 689 } 690 691 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 692 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 693 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 694 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 695 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 696 } 697 698 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 699 if (chip->chip_id == RTL8852C) { 700 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 701 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 704 } else { 705 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 706 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 707 } 708 } 709 710 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 711 if (chip->chip_id == RTL8852C) { 712 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 713 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 716 } else { 717 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 718 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 719 } 720 } 721 722 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 723 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 724 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 725 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 726 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 727 } 728 729 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 730 if (chip->chip_id == RTL8852C) { 731 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 732 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 735 } else { 736 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 737 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 738 } 739 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 740 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 741 } 742 743 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 744 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 745 } 746 747 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 748 enum mac_ax_err_info err) 749 { 750 if (err != MAC_AX_ERR_L1_ERR_DMAC && 751 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 752 err != MAC_AX_ERR_L0_ERR_CMAC0 && 753 err != MAC_AX_ERR_L0_ERR_CMAC1 && 754 err != MAC_AX_ERR_RXI300) 755 return; 756 757 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 758 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 759 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 762 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 763 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 764 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 766 767 rtw89_mac_dump_dmac_err_status(rtwdev); 768 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 769 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 770 771 rtwdev->hci.ops->dump_err_status(rtwdev); 772 773 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 774 rtw89_mac_dump_l0_to_l1(rtwdev, err); 775 776 rtw89_info(rtwdev, "<---\n"); 777 } 778 779 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 780 { 781 struct rtw89_ser *ser = &rtwdev->ser; 782 u32 dmac_err, imr, isr; 783 int ret; 784 785 if (rtwdev->chip->chip_id == RTL8852C) { 786 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 787 if (ret) 788 return true; 789 790 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 791 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 792 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 793 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 794 795 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 796 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 797 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 798 return true; 799 } 800 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 801 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 802 return true; 803 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 804 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 805 return true; 806 } 807 } 808 809 return false; 810 } 811 812 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 813 { 814 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 815 u32 err, err_scnr; 816 int ret; 817 818 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 819 false, rtwdev, R_AX_HALT_C2H_CTRL); 820 if (ret) { 821 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 822 return ret; 823 } 824 825 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 826 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 827 828 err_scnr = RTW89_ERROR_SCENARIO(err); 829 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 830 err = MAC_AX_ERR_CPU_EXCEPTION; 831 else if (err_scnr == RTW89_WCPU_ASSERTION) 832 err = MAC_AX_ERR_ASSERTION; 833 else if (err_scnr == RTW89_RXI300_ERROR) 834 err = MAC_AX_ERR_RXI300; 835 836 if (rtw89_mac_suppress_log(rtwdev, err)) 837 return err; 838 839 rtw89_fw_st_dbg_dump(rtwdev); 840 mac->dump_err_status(rtwdev, err); 841 842 return err; 843 } 844 EXPORT_SYMBOL(rtw89_mac_get_err_status); 845 846 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 847 { 848 struct rtw89_ser *ser = &rtwdev->ser; 849 u32 halt; 850 int ret = 0; 851 852 if (err > MAC_AX_SET_ERR_MAX) { 853 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 854 return -EINVAL; 855 } 856 857 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 858 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 859 if (ret) { 860 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 861 return -EFAULT; 862 } 863 864 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 865 866 if (ser->prehandle_l1 && 867 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 868 return 0; 869 870 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 871 872 return 0; 873 } 874 EXPORT_SYMBOL(rtw89_mac_set_err_status); 875 876 static int hfc_reset_param(struct rtw89_dev *rtwdev) 877 { 878 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 879 struct rtw89_hfc_param_ini param_ini = {NULL}; 880 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 881 882 switch (rtwdev->hci.type) { 883 case RTW89_HCI_TYPE_PCIE: 884 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 885 param->en = 0; 886 break; 887 default: 888 return -EINVAL; 889 } 890 891 if (param_ini.pub_cfg) 892 param->pub_cfg = *param_ini.pub_cfg; 893 894 if (param_ini.prec_cfg) 895 param->prec_cfg = *param_ini.prec_cfg; 896 897 if (param_ini.ch_cfg) 898 param->ch_cfg = param_ini.ch_cfg; 899 900 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 901 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 902 param->mode = param_ini.mode; 903 904 return 0; 905 } 906 907 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 908 { 909 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 910 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 911 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 912 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 913 914 if (ch >= RTW89_DMA_CH_NUM) 915 return -EINVAL; 916 917 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 918 ch_cfg[ch].max > pub_cfg->pub_max) 919 return -EINVAL; 920 if (ch_cfg[ch].grp >= grp_num) 921 return -EINVAL; 922 923 return 0; 924 } 925 926 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 927 { 928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 929 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 930 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 931 932 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 933 if (rtwdev->chip->chip_id == RTL8852A) 934 return 0; 935 else 936 return -EFAULT; 937 } 938 939 return 0; 940 } 941 942 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 943 { 944 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 945 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 946 947 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 948 return -EFAULT; 949 950 return 0; 951 } 952 953 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 954 { 955 const struct rtw89_chip_info *chip = rtwdev->chip; 956 const struct rtw89_page_regs *regs = chip->page_regs; 957 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 958 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 959 int ret = 0; 960 u32 val = 0; 961 962 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 963 if (ret) 964 return ret; 965 966 ret = hfc_ch_cfg_chk(rtwdev, ch); 967 if (ret) 968 return ret; 969 970 if (ch > RTW89_DMA_B1HI) 971 return -EINVAL; 972 973 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 974 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 975 (cfg[ch].grp ? B_AX_GRP : 0); 976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 977 978 return 0; 979 } 980 981 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 982 { 983 const struct rtw89_chip_info *chip = rtwdev->chip; 984 const struct rtw89_page_regs *regs = chip->page_regs; 985 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 986 struct rtw89_hfc_ch_info *info = param->ch_info; 987 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 988 u32 val; 989 u32 ret; 990 991 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 992 if (ret) 993 return ret; 994 995 if (ch > RTW89_DMA_H2C) 996 return -EINVAL; 997 998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 999 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1000 if (ch < RTW89_DMA_H2C) 1001 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1002 else 1003 info[ch].used = cfg[ch].min - info[ch].aval; 1004 1005 return 0; 1006 } 1007 1008 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1009 { 1010 const struct rtw89_chip_info *chip = rtwdev->chip; 1011 const struct rtw89_page_regs *regs = chip->page_regs; 1012 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1013 u32 val; 1014 int ret; 1015 1016 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1017 if (ret) 1018 return ret; 1019 1020 ret = hfc_pub_cfg_chk(rtwdev); 1021 if (ret) 1022 return ret; 1023 1024 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1025 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1027 1028 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1030 1031 return 0; 1032 } 1033 1034 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1035 { 1036 const struct rtw89_chip_info *chip = rtwdev->chip; 1037 const struct rtw89_page_regs *regs = chip->page_regs; 1038 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1039 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1040 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1041 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1042 u32 val; 1043 1044 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1045 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1046 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1047 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1048 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1049 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1050 info->pub_aval = 1051 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1052 B_AX_PUB_AVAL_PG_MASK); 1053 info->wp_aval = 1054 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1055 B_AX_WP_AVAL_PG_MASK); 1056 1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1058 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1059 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1060 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1061 prec_cfg->ch011_full_cond = 1062 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1063 prec_cfg->h2c_full_cond = 1064 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1065 prec_cfg->wp_ch07_full_cond = 1066 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1067 prec_cfg->wp_ch811_full_cond = 1068 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1069 1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1071 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1072 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1073 1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1075 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1076 1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1078 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1079 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1080 1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1082 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1083 1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1085 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1086 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1087 } 1088 1089 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1090 { 1091 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1092 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1093 int ret; 1094 1095 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1096 if (ret) 1097 return ret; 1098 1099 mac->hfc_get_mix_info(rtwdev); 1100 1101 ret = hfc_pub_info_chk(rtwdev); 1102 if (param->en && ret) 1103 return ret; 1104 1105 return 0; 1106 } 1107 1108 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1109 { 1110 const struct rtw89_chip_info *chip = rtwdev->chip; 1111 const struct rtw89_page_regs *regs = chip->page_regs; 1112 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1113 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1114 u32 val; 1115 1116 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1118 1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1120 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1121 prec_cfg->h2c_full_cond); 1122 } 1123 1124 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1125 { 1126 const struct rtw89_chip_info *chip = rtwdev->chip; 1127 const struct rtw89_page_regs *regs = chip->page_regs; 1128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1129 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1130 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1131 u32 val; 1132 1133 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1134 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1136 1137 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1139 1140 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1141 B_AX_PREC_PAGE_WP_CH07_MASK) | 1142 u32_encode_bits(prec_cfg->wp_ch811_prec, 1143 B_AX_PREC_PAGE_WP_CH811_MASK); 1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1145 1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1147 param->mode, B_AX_HCI_FC_MODE_MASK); 1148 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1149 B_AX_HCI_FC_WD_FULL_COND_MASK); 1150 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1151 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1152 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1153 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1154 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1155 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1157 } 1158 1159 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1160 { 1161 const struct rtw89_chip_info *chip = rtwdev->chip; 1162 const struct rtw89_page_regs *regs = chip->page_regs; 1163 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1164 u32 val; 1165 1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1167 param->en = en; 1168 param->h2c_en = h2c_en; 1169 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1170 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1171 (val & ~B_AX_HCI_FC_CH12_EN); 1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1173 } 1174 1175 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1176 { 1177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1178 const struct rtw89_chip_info *chip = rtwdev->chip; 1179 u32 dma_ch_mask = chip->dma_ch_mask; 1180 u8 ch; 1181 u32 ret = 0; 1182 1183 if (reset) 1184 ret = hfc_reset_param(rtwdev); 1185 if (ret) 1186 return ret; 1187 1188 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1189 if (ret) 1190 return ret; 1191 1192 mac->hfc_func_en(rtwdev, false, false); 1193 1194 if (!en && h2c_en) { 1195 mac->hfc_h2c_cfg(rtwdev); 1196 mac->hfc_func_en(rtwdev, en, h2c_en); 1197 return ret; 1198 } 1199 1200 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1201 if (dma_ch_mask & BIT(ch)) 1202 continue; 1203 ret = hfc_ch_ctrl(rtwdev, ch); 1204 if (ret) 1205 return ret; 1206 } 1207 1208 ret = hfc_pub_ctrl(rtwdev); 1209 if (ret) 1210 return ret; 1211 1212 mac->hfc_mix_cfg(rtwdev); 1213 if (en || h2c_en) { 1214 mac->hfc_func_en(rtwdev, en, h2c_en); 1215 udelay(10); 1216 } 1217 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1218 if (dma_ch_mask & BIT(ch)) 1219 continue; 1220 ret = hfc_upd_ch_info(rtwdev, ch); 1221 if (ret) 1222 return ret; 1223 } 1224 ret = hfc_upd_mix_info(rtwdev); 1225 1226 return ret; 1227 } 1228 1229 #define PWR_POLL_CNT 2000 1230 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1231 const struct rtw89_pwr_cfg *cfg) 1232 { 1233 u8 val = 0; 1234 int ret; 1235 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1236 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1237 1238 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1239 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1240 1241 if (!ret) 1242 return 0; 1243 1244 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1245 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1247 1248 return -EBUSY; 1249 } 1250 1251 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1252 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1253 { 1254 const struct rtw89_pwr_cfg *cur_cfg; 1255 u32 addr; 1256 u8 val; 1257 1258 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1259 if (!(cur_cfg->intf_msk & intf_msk) || 1260 !(cur_cfg->cv_msk & cv_msk)) 1261 continue; 1262 1263 switch (cur_cfg->cmd) { 1264 case PWR_CMD_WRITE: 1265 addr = cur_cfg->addr; 1266 1267 if (cur_cfg->base == PWR_BASE_SDIO) 1268 addr |= SDIO_LOCAL_BASE_ADDR; 1269 1270 val = rtw89_read8(rtwdev, addr); 1271 val &= ~(cur_cfg->msk); 1272 val |= (cur_cfg->val & cur_cfg->msk); 1273 1274 rtw89_write8(rtwdev, addr, val); 1275 break; 1276 case PWR_CMD_POLL: 1277 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1278 return -EBUSY; 1279 break; 1280 case PWR_CMD_DELAY: 1281 if (cur_cfg->val == PWR_DELAY_US) 1282 udelay(cur_cfg->addr); 1283 else 1284 fsleep(cur_cfg->addr * 1000); 1285 break; 1286 default: 1287 return -EINVAL; 1288 } 1289 } 1290 1291 return 0; 1292 } 1293 1294 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1295 const struct rtw89_pwr_cfg * const *cfg_seq) 1296 { 1297 int ret; 1298 1299 for (; *cfg_seq; cfg_seq++) { 1300 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1301 PWR_INTF_MSK_PCIE, *cfg_seq); 1302 if (ret) 1303 return -EBUSY; 1304 } 1305 1306 return 0; 1307 } 1308 1309 static enum rtw89_rpwm_req_pwr_state 1310 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1311 { 1312 enum rtw89_rpwm_req_pwr_state state; 1313 1314 switch (rtwdev->ps_mode) { 1315 case RTW89_PS_MODE_RFOFF: 1316 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1317 break; 1318 case RTW89_PS_MODE_CLK_GATED: 1319 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1320 break; 1321 case RTW89_PS_MODE_PWR_GATED: 1322 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1323 break; 1324 default: 1325 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1326 break; 1327 } 1328 return state; 1329 } 1330 1331 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1332 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1333 bool notify_wake) 1334 { 1335 u16 request; 1336 1337 spin_lock_bh(&rtwdev->rpwm_lock); 1338 1339 request = rtw89_read16(rtwdev, R_AX_RPWM); 1340 request ^= request | PS_RPWM_TOGGLE; 1341 request |= req_pwr_state; 1342 1343 if (notify_wake) { 1344 request |= PS_RPWM_NOTIFY_WAKE; 1345 } else { 1346 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1347 RPWM_SEQ_NUM_MAX; 1348 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1349 rtwdev->mac.rpwm_seq_num); 1350 1351 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1352 request |= PS_RPWM_ACK; 1353 } 1354 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1355 1356 spin_unlock_bh(&rtwdev->rpwm_lock); 1357 } 1358 1359 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1360 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1361 { 1362 bool request_deep_mode; 1363 bool in_deep_mode; 1364 u8 rpwm_req_num; 1365 u8 cpwm_rsp_seq; 1366 u8 cpwm_seq; 1367 u8 cpwm_status; 1368 1369 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1370 request_deep_mode = true; 1371 else 1372 request_deep_mode = false; 1373 1374 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1375 in_deep_mode = true; 1376 else 1377 in_deep_mode = false; 1378 1379 if (request_deep_mode != in_deep_mode) 1380 return -EPERM; 1381 1382 if (request_deep_mode) 1383 return 0; 1384 1385 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1386 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1387 PS_CPWM_RSP_SEQ_NUM); 1388 1389 if (rpwm_req_num != cpwm_rsp_seq) 1390 return -EPERM; 1391 1392 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1393 CPWM_SEQ_NUM_MAX; 1394 1395 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1396 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1397 return -EPERM; 1398 1399 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1400 if (cpwm_status != req_pwr_state) 1401 return -EPERM; 1402 1403 return 0; 1404 } 1405 1406 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1407 { 1408 enum rtw89_rpwm_req_pwr_state state; 1409 unsigned long delay = enter ? 10 : 150; 1410 int ret; 1411 int i; 1412 1413 if (enter) 1414 state = rtw89_mac_get_req_pwr_state(rtwdev); 1415 else 1416 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1417 1418 for (i = 0; i < RPWM_TRY_CNT; i++) { 1419 rtw89_mac_send_rpwm(rtwdev, state, false); 1420 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1421 !ret, delay, 15000, false, 1422 rtwdev, state); 1423 if (!ret) 1424 break; 1425 1426 if (i == RPWM_TRY_CNT - 1) 1427 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1428 enter ? "entering" : "leaving"); 1429 else 1430 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1431 "%d time firmware failed to ack for %s ps mode\n", 1432 i + 1, enter ? "entering" : "leaving"); 1433 } 1434 } 1435 1436 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1437 { 1438 enum rtw89_rpwm_req_pwr_state state; 1439 1440 state = rtw89_mac_get_req_pwr_state(rtwdev); 1441 rtw89_mac_send_rpwm(rtwdev, state, true); 1442 } 1443 1444 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1445 { 1446 #define PWR_ACT 1 1447 const struct rtw89_chip_info *chip = rtwdev->chip; 1448 const struct rtw89_pwr_cfg * const *cfg_seq; 1449 int (*cfg_func)(struct rtw89_dev *rtwdev); 1450 int ret; 1451 u8 val; 1452 1453 if (on) { 1454 cfg_seq = chip->pwr_on_seq; 1455 cfg_func = chip->ops->pwr_on_func; 1456 } else { 1457 cfg_seq = chip->pwr_off_seq; 1458 cfg_func = chip->ops->pwr_off_func; 1459 } 1460 1461 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1462 __rtw89_leave_ps_mode(rtwdev); 1463 1464 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1465 if (on && val == PWR_ACT) { 1466 rtw89_err(rtwdev, "MAC has already powered on\n"); 1467 return -EBUSY; 1468 } 1469 1470 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1471 if (ret) 1472 return ret; 1473 1474 if (on) { 1475 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1476 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1477 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1478 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1479 } else { 1480 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1481 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1482 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1483 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1484 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1485 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1486 rtw89_set_entity_state(rtwdev, false); 1487 } 1488 1489 return 0; 1490 #undef PWR_ACT 1491 } 1492 1493 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1494 { 1495 rtw89_mac_power_switch(rtwdev, false); 1496 } 1497 1498 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1499 { 1500 u32 func_en = 0; 1501 u32 ck_en = 0; 1502 u32 c1pc_en = 0; 1503 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1504 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1505 1506 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1507 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1508 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1509 B_AX_CMAC_CRPRT; 1510 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1511 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1512 B_AX_RMAC_CKEN; 1513 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1514 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1515 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1516 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1517 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1518 1519 if (en) { 1520 if (mac_idx == RTW89_MAC_1) { 1521 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1522 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1523 B_AX_R_SYM_ISO_CMAC12PP); 1524 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1525 B_AX_CMAC1_FEN); 1526 } 1527 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1528 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1529 } else { 1530 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1531 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1532 if (mac_idx == RTW89_MAC_1) { 1533 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1534 B_AX_CMAC1_FEN); 1535 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1536 B_AX_R_SYM_ISO_CMAC12PP); 1537 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1538 } 1539 } 1540 1541 return 0; 1542 } 1543 1544 static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1545 { 1546 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1547 u32 val32; 1548 1549 if (chip_id == RTL8852C) 1550 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1551 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1552 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1553 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1554 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1555 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1556 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1557 else 1558 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1559 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1560 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1561 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1562 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1563 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1564 B_AX_DMAC_CRPRT); 1565 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1566 1567 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1568 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1569 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1570 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1571 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1572 1573 return 0; 1574 } 1575 1576 static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1577 { 1578 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1579 1580 if (chip_id == RTL8852A || chip_id == RTL8852B) 1581 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1582 B_AX_OCP_L1_MASK); 1583 1584 return 0; 1585 } 1586 1587 static int sys_init_ax(struct rtw89_dev *rtwdev) 1588 { 1589 int ret; 1590 1591 ret = dmac_func_en_ax(rtwdev); 1592 if (ret) 1593 return ret; 1594 1595 ret = cmac_func_en_ax(rtwdev, 0, true); 1596 if (ret) 1597 return ret; 1598 1599 ret = chip_func_en_ax(rtwdev); 1600 if (ret) 1601 return ret; 1602 1603 return ret; 1604 } 1605 1606 const struct rtw89_mac_size_set rtw89_mac_size = { 1607 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1608 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0}, 1609 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0}, 1610 /* PCIE 64 */ 1611 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1612 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1613 /* DLFW */ 1614 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1615 .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1616 /* PCIE 64 */ 1617 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1618 /* 8852B PCIE SCC */ 1619 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1620 /* DLFW */ 1621 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1622 /* 8852C DLFW */ 1623 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1624 /* 8852C PCIE SCC */ 1625 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1626 /* PCIE */ 1627 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1628 .ple_size0_v1 = {RTW89_PLE_PG_128, 2672, 256, 212992,}, 1629 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1630 /* DLFW */ 1631 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1632 /* PCIE 64 */ 1633 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1634 /* DLFW */ 1635 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1636 /* 8852C DLFW */ 1637 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1638 /* 8852C PCIE SCC */ 1639 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1640 /* PCIE 64 */ 1641 .wde_qt0 = {3792, 196, 0, 107,}, 1642 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1643 /* DLFW */ 1644 .wde_qt4 = {0, 0, 0, 0,}, 1645 /* PCIE 64 */ 1646 .wde_qt6 = {448, 48, 0, 16,}, 1647 /* 8852B PCIE SCC */ 1648 .wde_qt7 = {446, 48, 0, 16,}, 1649 /* 8852C DLFW */ 1650 .wde_qt17 = {0, 0, 0, 0,}, 1651 /* 8852C PCIE SCC */ 1652 .wde_qt18 = {3228, 60, 0, 40,}, 1653 .ple_qt0 = {320, 0, 32, 16, 13, 13, 292, 0, 32, 18, 1, 4, 0,}, 1654 .ple_qt1 = {320, 0, 32, 16, 1944, 1944, 2223, 0, 1963, 1949, 1, 1935, 0,}, 1655 /* PCIE SCC */ 1656 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1657 /* PCIE SCC */ 1658 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1659 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1660 /* DLFW */ 1661 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1662 /* PCIE 64 */ 1663 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1664 /* DLFW 52C */ 1665 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1666 /* DLFW 52C */ 1667 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1668 /* 8852C PCIE SCC */ 1669 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1670 /* 8852C PCIE SCC */ 1671 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1672 /* PCIE 64 */ 1673 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1674 /* 8852A PCIE WOW */ 1675 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1676 /* 8852B PCIE WOW */ 1677 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1678 /* 8851B PCIE WOW */ 1679 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1680 .ple_rsvd_qt0 = {2, 112, 56, 6, 6, 6, 6, 0, 0, 62,}, 1681 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1682 .rsvd0_size0 = {212992, 0,}, 1683 .rsvd1_size0 = {587776, 2048,}, 1684 }; 1685 EXPORT_SYMBOL(rtw89_mac_size); 1686 1687 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1688 enum rtw89_qta_mode mode) 1689 { 1690 struct rtw89_mac_info *mac = &rtwdev->mac; 1691 const struct rtw89_dle_mem *cfg; 1692 1693 cfg = &rtwdev->chip->dle_mem[mode]; 1694 if (!cfg) 1695 return NULL; 1696 1697 if (cfg->mode != mode) { 1698 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1699 return NULL; 1700 } 1701 1702 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1703 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1704 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1705 mac->dle_info.qta_mode = mode; 1706 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1707 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1708 1709 return cfg; 1710 } 1711 1712 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1713 enum rtw89_mac_dle_rsvd_qt_type type, 1714 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1715 { 1716 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1717 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1718 1719 switch (type) { 1720 case DLE_RSVD_QT_MPDU_INFO: 1721 cfg->pktid = dle_info->ple_free_pg; 1722 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1723 break; 1724 case DLE_RSVD_QT_B0_CSI: 1725 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1726 cfg->pg_num = rsvd_qt->b0_csi; 1727 break; 1728 case DLE_RSVD_QT_B1_CSI: 1729 cfg->pktid = dle_info->ple_free_pg + 1730 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1731 cfg->pg_num = rsvd_qt->b1_csi; 1732 break; 1733 case DLE_RSVD_QT_B0_LMR: 1734 cfg->pktid = dle_info->ple_free_pg + 1735 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1736 cfg->pg_num = rsvd_qt->b0_lmr; 1737 break; 1738 case DLE_RSVD_QT_B1_LMR: 1739 cfg->pktid = dle_info->ple_free_pg + 1740 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1741 rsvd_qt->b0_lmr; 1742 cfg->pg_num = rsvd_qt->b1_lmr; 1743 break; 1744 case DLE_RSVD_QT_B0_FTM: 1745 cfg->pktid = dle_info->ple_free_pg + 1746 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1747 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1748 cfg->pg_num = rsvd_qt->b0_ftm; 1749 break; 1750 case DLE_RSVD_QT_B1_FTM: 1751 cfg->pktid = dle_info->ple_free_pg + 1752 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1753 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1754 cfg->pg_num = rsvd_qt->b1_ftm; 1755 break; 1756 default: 1757 return -EINVAL; 1758 } 1759 1760 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1761 1762 return 0; 1763 } 1764 1765 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1766 { 1767 struct rtw89_mac_dle_dfi_qempty qempty; 1768 u32 grpnum, qtmp, val32, msk32; 1769 int i, j, ret; 1770 1771 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1772 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1773 1774 for (i = 0; i < grpnum; i++) { 1775 qempty.grpsel = i; 1776 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1777 if (ret) { 1778 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1779 return false; 1780 } 1781 qtmp = qempty.qempty; 1782 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1783 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 1784 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1785 return false; 1786 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1787 } 1788 } 1789 1790 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1791 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1792 if (ret) { 1793 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1794 return false; 1795 } 1796 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1797 if ((qempty.qempty & msk32) != msk32) 1798 return false; 1799 1800 if (rtwdev->dbcc_en) { 1801 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1802 if ((qempty.qempty & msk32) != msk32) 1803 return false; 1804 } 1805 1806 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1807 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1808 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1809 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1810 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1811 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1812 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1813 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1814 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1815 1816 return (val32 & msk32) == msk32; 1817 } 1818 1819 static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1820 { 1821 const struct rtw89_dle_size *wde = cfg->wde_size; 1822 const struct rtw89_dle_size *ple = cfg->ple_size; 1823 u32 used; 1824 1825 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1826 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1827 1828 if (cfg->rsvd0_size && cfg->rsvd1_size) { 1829 used += cfg->rsvd0_size->size; 1830 used += cfg->rsvd1_size->size; 1831 } 1832 1833 return used; 1834 } 1835 1836 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1837 enum rtw89_qta_mode mode) 1838 { 1839 u32 size = rtwdev->chip->fifo_size; 1840 1841 if (mode == RTW89_QTA_SCC) 1842 size -= rtwdev->chip->dle_scc_rsvd_size; 1843 1844 return size; 1845 } 1846 1847 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 1848 { 1849 if (enable) 1850 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1851 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1852 else 1853 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1854 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1855 } 1856 1857 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 1858 { 1859 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1860 1861 if (enable) { 1862 if (rtwdev->chip->chip_id == RTL8851B) 1863 val |= B_AX_AXIDMA_CLK_EN; 1864 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1865 } else { 1866 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1867 } 1868 } 1869 1870 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1871 { 1872 const struct rtw89_dle_size *size_cfg; 1873 u32 val; 1874 u8 bound = 0; 1875 1876 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1877 size_cfg = cfg->wde_size; 1878 1879 switch (size_cfg->pge_size) { 1880 default: 1881 case RTW89_WDE_PG_64: 1882 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1883 B_AX_WDE_PAGE_SEL_MASK); 1884 break; 1885 case RTW89_WDE_PG_128: 1886 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1887 B_AX_WDE_PAGE_SEL_MASK); 1888 break; 1889 case RTW89_WDE_PG_256: 1890 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1891 return -EINVAL; 1892 } 1893 1894 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1895 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1896 B_AX_WDE_FREE_PAGE_NUM_MASK); 1897 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1898 1899 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1900 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1901 * size_cfg->pge_size / DLE_BOUND_UNIT; 1902 size_cfg = cfg->ple_size; 1903 1904 switch (size_cfg->pge_size) { 1905 default: 1906 case RTW89_PLE_PG_64: 1907 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1908 return -EINVAL; 1909 case RTW89_PLE_PG_128: 1910 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1911 B_AX_PLE_PAGE_SEL_MASK); 1912 break; 1913 case RTW89_PLE_PG_256: 1914 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1915 B_AX_PLE_PAGE_SEL_MASK); 1916 break; 1917 } 1918 1919 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1920 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1921 B_AX_PLE_FREE_PAGE_NUM_MASK); 1922 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1923 1924 return 0; 1925 } 1926 1927 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 1928 { 1929 u32 reg, mask; 1930 u32 ini; 1931 1932 if (wde_or_ple) { 1933 reg = R_AX_WDE_INI_STATUS; 1934 mask = WDE_MGN_INI_RDY; 1935 } else { 1936 reg = R_AX_PLE_INI_STATUS; 1937 mask = PLE_MGN_INI_RDY; 1938 } 1939 1940 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 1941 2000, false, rtwdev, reg); 1942 } 1943 1944 #define INVALID_QT_WCPU U16_MAX 1945 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1946 do { \ 1947 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1948 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1949 rtw89_write32(rtwdev, \ 1950 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1951 val); \ 1952 } while (0) 1953 #define SET_QUOTA(_x, _module, _idx) \ 1954 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1955 1956 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 1957 const struct rtw89_wde_quota *min_cfg, 1958 const struct rtw89_wde_quota *max_cfg, 1959 u16 ext_wde_min_qt_wcpu) 1960 { 1961 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1962 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1963 u32 val; 1964 1965 SET_QUOTA(hif, WDE, 0); 1966 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1967 SET_QUOTA(pkt_in, WDE, 3); 1968 SET_QUOTA(cpu_io, WDE, 4); 1969 } 1970 1971 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 1972 const struct rtw89_ple_quota *min_cfg, 1973 const struct rtw89_ple_quota *max_cfg) 1974 { 1975 u32 val; 1976 1977 SET_QUOTA(cma0_tx, PLE, 0); 1978 SET_QUOTA(cma1_tx, PLE, 1); 1979 SET_QUOTA(c2h, PLE, 2); 1980 SET_QUOTA(h2c, PLE, 3); 1981 SET_QUOTA(wcpu, PLE, 4); 1982 SET_QUOTA(mpdu_proc, PLE, 5); 1983 SET_QUOTA(cma0_dma, PLE, 6); 1984 SET_QUOTA(cma1_dma, PLE, 7); 1985 SET_QUOTA(bb_rpt, PLE, 8); 1986 SET_QUOTA(wd_rel, PLE, 9); 1987 SET_QUOTA(cpu_io, PLE, 10); 1988 if (rtwdev->chip->chip_id == RTL8852C) 1989 SET_QUOTA(tx_rpt, PLE, 11); 1990 } 1991 1992 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 1993 { 1994 const struct rtw89_ple_quota *min_cfg, *max_cfg; 1995 const struct rtw89_dle_mem *cfg; 1996 u32 val; 1997 1998 if (rtwdev->chip->chip_id == RTL8852C) 1999 return 0; 2000 2001 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2002 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2003 return -EINVAL; 2004 } 2005 2006 if (wow) 2007 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2008 else 2009 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2010 if (!cfg) { 2011 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2012 return -EINVAL; 2013 } 2014 2015 min_cfg = cfg->ple_min_qt; 2016 max_cfg = cfg->ple_max_qt; 2017 SET_QUOTA(cma0_dma, PLE, 6); 2018 SET_QUOTA(cma1_dma, PLE, 7); 2019 2020 return 0; 2021 } 2022 #undef SET_QUOTA 2023 2024 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2025 { 2026 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2027 2028 if (enable) 2029 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2030 else 2031 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2032 } 2033 2034 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2035 const struct rtw89_dle_mem *cfg, 2036 u16 ext_wde_min_qt_wcpu) 2037 { 2038 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2039 2040 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2041 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2042 } 2043 2044 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2045 enum rtw89_qta_mode ext_mode) 2046 { 2047 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2048 const struct rtw89_dle_mem *cfg, *ext_cfg; 2049 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2050 int ret; 2051 2052 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2053 if (ret) 2054 return ret; 2055 2056 cfg = get_dle_mem_cfg(rtwdev, mode); 2057 if (!cfg) { 2058 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2059 ret = -EINVAL; 2060 goto error; 2061 } 2062 2063 if (mode == RTW89_QTA_DLFW) { 2064 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2065 if (!ext_cfg) { 2066 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2067 ext_mode); 2068 ret = -EINVAL; 2069 goto error; 2070 } 2071 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2072 } 2073 2074 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2075 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2076 ret = -EINVAL; 2077 goto error; 2078 } 2079 2080 mac->dle_func_en(rtwdev, false); 2081 mac->dle_clk_en(rtwdev, true); 2082 2083 ret = mac->dle_mix_cfg(rtwdev, cfg); 2084 if (ret) { 2085 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2086 goto error; 2087 } 2088 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2089 2090 mac->dle_func_en(rtwdev, true); 2091 2092 ret = mac->chk_dle_rdy(rtwdev, true); 2093 if (ret) { 2094 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2095 return ret; 2096 } 2097 2098 ret = mac->chk_dle_rdy(rtwdev, false); 2099 if (ret) { 2100 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2101 return ret; 2102 } 2103 2104 return 0; 2105 error: 2106 mac->dle_func_en(rtwdev, false); 2107 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2108 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2109 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2110 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2111 2112 return ret; 2113 } 2114 2115 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2116 enum rtw89_qta_mode mode) 2117 { 2118 u32 reg, max_preld_size, min_rsvd_size; 2119 2120 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2121 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2122 reg = mac_idx == RTW89_MAC_0 ? 2123 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2124 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2125 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2126 2127 min_rsvd_size = PRELD_AMSDU_SIZE; 2128 reg = mac_idx == RTW89_MAC_0 ? 2129 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2130 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2131 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2132 2133 return 0; 2134 } 2135 2136 static bool is_qta_poh(struct rtw89_dev *rtwdev) 2137 { 2138 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2139 } 2140 2141 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2142 enum rtw89_qta_mode mode) 2143 { 2144 const struct rtw89_chip_info *chip = rtwdev->chip; 2145 2146 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2147 chip->chip_id == RTL8851B || !is_qta_poh(rtwdev)) 2148 return 0; 2149 2150 return preload_init_set(rtwdev, mac_idx, mode); 2151 } 2152 2153 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2154 { 2155 u32 msk32; 2156 u32 val32; 2157 2158 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2159 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2160 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2161 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2162 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2163 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2164 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2165 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2166 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2167 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2168 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2169 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2170 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2171 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2172 2173 if ((val32 & msk32) == msk32) 2174 return true; 2175 2176 return false; 2177 } 2178 2179 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2180 { 2181 const struct rtw89_chip_info *chip = rtwdev->chip; 2182 2183 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2184 chip->chip_id == RTL8851B) 2185 return; 2186 2187 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2188 SS2F_PATH_WLCPU); 2189 } 2190 2191 static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2192 { 2193 u32 p_val; 2194 u8 val; 2195 int ret; 2196 2197 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2198 if (ret) 2199 return ret; 2200 2201 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2202 val |= B_AX_SS_EN; 2203 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2204 2205 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2206 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2207 if (ret) { 2208 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2209 return ret; 2210 } 2211 2212 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2213 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2214 2215 _patch_ss2f_path(rtwdev); 2216 2217 return 0; 2218 } 2219 2220 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2221 { 2222 int ret; 2223 2224 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2225 if (ret) 2226 return ret; 2227 2228 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2229 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2230 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2231 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2232 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2233 2234 return 0; 2235 } 2236 2237 static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2238 { 2239 const struct rtw89_chip_info *chip = rtwdev->chip; 2240 u32 val = 0; 2241 int ret; 2242 2243 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2244 if (ret) 2245 return ret; 2246 2247 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2248 /* init clock */ 2249 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2250 /* init TX encryption */ 2251 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2252 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2253 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2254 chip->chip_id == RTL8851B) 2255 val &= ~B_AX_TX_PARTIAL_MODE; 2256 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2257 2258 /* init MIC ICV append */ 2259 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2260 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2261 2262 /* option init */ 2263 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2264 2265 if (chip->chip_id == RTL8852C) 2266 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2267 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2268 2269 return 0; 2270 } 2271 2272 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2273 { 2274 int ret; 2275 2276 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2277 if (ret) { 2278 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2279 return ret; 2280 } 2281 2282 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2283 if (ret) { 2284 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2285 return ret; 2286 } 2287 2288 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2289 if (ret) { 2290 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2291 return ret; 2292 } 2293 2294 ret = sta_sch_init_ax(rtwdev); 2295 if (ret) { 2296 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2297 return ret; 2298 } 2299 2300 ret = mpdu_proc_init_ax(rtwdev); 2301 if (ret) { 2302 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2303 return ret; 2304 } 2305 2306 ret = sec_eng_init_ax(rtwdev); 2307 if (ret) { 2308 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2309 return ret; 2310 } 2311 2312 return ret; 2313 } 2314 2315 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2316 { 2317 u32 val, reg; 2318 u16 p_val; 2319 int ret; 2320 2321 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2322 if (ret) 2323 return ret; 2324 2325 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2326 2327 val = rtw89_read32(rtwdev, reg); 2328 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2329 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2330 rtw89_write32(rtwdev, reg, val); 2331 2332 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2333 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2334 if (ret) { 2335 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2336 return ret; 2337 } 2338 2339 return 0; 2340 } 2341 2342 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2343 { 2344 u32 ret; 2345 u32 reg; 2346 u32 val; 2347 2348 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2349 if (ret) 2350 return ret; 2351 2352 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2353 if (rtwdev->chip->chip_id == RTL8852C) 2354 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2355 SIFS_MACTXEN_T1_V1); 2356 else 2357 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2358 SIFS_MACTXEN_T1); 2359 2360 if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) { 2361 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2362 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2363 } 2364 2365 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2366 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2367 2368 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2369 if (rtwdev->chip->chip_id == RTL8852C) { 2370 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2371 B_AX_TX_PARTIAL_MODE); 2372 if (!val) 2373 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2374 SCH_PREBKF_24US); 2375 } else { 2376 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2377 SCH_PREBKF_24US); 2378 } 2379 2380 return 0; 2381 } 2382 2383 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2384 enum rtw89_machdr_frame_type type, 2385 enum rtw89_mac_fwd_target fwd_target, 2386 u8 mac_idx) 2387 { 2388 u32 reg; 2389 u32 val; 2390 2391 switch (fwd_target) { 2392 case RTW89_FWD_DONT_CARE: 2393 val = RX_FLTR_FRAME_DROP; 2394 break; 2395 case RTW89_FWD_TO_HOST: 2396 val = RX_FLTR_FRAME_TO_HOST; 2397 break; 2398 case RTW89_FWD_TO_WLAN_CPU: 2399 val = RX_FLTR_FRAME_TO_WLCPU; 2400 break; 2401 default: 2402 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2403 return -EINVAL; 2404 } 2405 2406 switch (type) { 2407 case RTW89_MGNT: 2408 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2409 break; 2410 case RTW89_CTRL: 2411 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2412 break; 2413 case RTW89_DATA: 2414 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2415 break; 2416 default: 2417 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2418 return -EINVAL; 2419 } 2420 rtw89_write32(rtwdev, reg, val); 2421 2422 return 0; 2423 } 2424 2425 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2426 { 2427 int ret, i; 2428 u32 mac_ftlr, plcp_ftlr; 2429 2430 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2431 if (ret) 2432 return ret; 2433 2434 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2435 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2436 mac_idx); 2437 if (ret) 2438 return ret; 2439 } 2440 mac_ftlr = rtwdev->hal.rx_fltr; 2441 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2442 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2443 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2444 B_AX_HE_SIGB_CRC_CHK; 2445 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2446 mac_ftlr); 2447 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2448 plcp_ftlr); 2449 2450 return 0; 2451 } 2452 2453 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2454 { 2455 u32 reg, val32; 2456 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2457 2458 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2459 B_AX_RSP_CHK_BASIC_NAV; 2460 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2461 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2462 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2463 2464 switch (rtwdev->chip->chip_id) { 2465 case RTL8852A: 2466 case RTL8852B: 2467 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2468 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2469 rtw89_write32(rtwdev, reg, val32); 2470 2471 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2472 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2473 rtw89_write32(rtwdev, reg, val32); 2474 break; 2475 default: 2476 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2477 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2478 rtw89_write32(rtwdev, reg, val32); 2479 2480 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2481 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2482 rtw89_write32(rtwdev, reg, val32); 2483 break; 2484 } 2485 } 2486 2487 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2488 { 2489 u32 val, reg; 2490 int ret; 2491 2492 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2493 if (ret) 2494 return ret; 2495 2496 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2497 val = rtw89_read32(rtwdev, reg); 2498 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2499 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2500 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2501 B_AX_CTN_CHK_INTRA_NAV | 2502 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2503 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2504 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2505 B_AX_CTN_CHK_CCA_P20); 2506 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2507 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2508 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2509 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2510 B_AX_SIFS_CHK_EDCCA); 2511 2512 rtw89_write32(rtwdev, reg, val); 2513 2514 _patch_dis_resp_chk(rtwdev, mac_idx); 2515 2516 return 0; 2517 } 2518 2519 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2520 { 2521 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2522 B_AX_WMAC_TF_UP_NAV_EN | 2523 B_AX_WMAC_NAV_UPPER_EN); 2524 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2525 2526 return 0; 2527 } 2528 2529 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2530 { 2531 u32 reg; 2532 int ret; 2533 2534 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2535 if (ret) 2536 return ret; 2537 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2538 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2539 2540 return 0; 2541 } 2542 2543 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2544 { 2545 u32 reg; 2546 int ret; 2547 2548 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2549 if (ret) 2550 return ret; 2551 2552 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2553 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2554 2555 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2556 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2557 2558 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2559 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2560 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2561 2562 return 0; 2563 } 2564 2565 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2566 { 2567 const struct rtw89_chip_info *chip = rtwdev->chip; 2568 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2569 u32 reg, val, sifs; 2570 int ret; 2571 2572 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2573 if (ret) 2574 return ret; 2575 2576 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2577 val = rtw89_read32(rtwdev, reg); 2578 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2579 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2580 2581 switch (rtwdev->chip->chip_id) { 2582 case RTL8852A: 2583 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2584 break; 2585 case RTL8852B: 2586 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2587 break; 2588 default: 2589 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2590 break; 2591 } 2592 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2593 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2594 rtw89_write32(rtwdev, reg, val); 2595 2596 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2597 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2598 2599 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2600 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2601 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2602 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2603 2604 return 0; 2605 } 2606 2607 static void rst_bacam(struct rtw89_dev *rtwdev) 2608 { 2609 u32 val32; 2610 int ret; 2611 2612 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2613 S_AX_BACAM_RST_ALL); 2614 2615 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2616 1, 1000, false, 2617 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2618 if (ret) 2619 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2620 } 2621 2622 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2623 { 2624 #define TRXCFG_RMAC_CCA_TO 32 2625 #define TRXCFG_RMAC_DATA_TO 15 2626 #define RX_MAX_LEN_UNIT 512 2627 #define PLD_RLS_MAX_PG 127 2628 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2629 int ret; 2630 u32 reg, rx_max_len, rx_qta; 2631 u16 val; 2632 2633 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2634 if (ret) 2635 return ret; 2636 2637 if (mac_idx == RTW89_MAC_0) 2638 rst_bacam(rtwdev); 2639 2640 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2641 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2642 2643 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2644 val = rtw89_read16(rtwdev, reg); 2645 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2646 B_AX_RX_DLK_DATA_TIME_MASK); 2647 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2648 B_AX_RX_DLK_CCA_TIME_MASK); 2649 rtw89_write16(rtwdev, reg, val); 2650 2651 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2652 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2653 2654 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2655 if (mac_idx == RTW89_MAC_0) 2656 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2657 else 2658 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2659 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2660 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2661 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2662 rx_max_len /= RX_MAX_LEN_UNIT; 2663 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2664 2665 if (rtwdev->chip->chip_id == RTL8852A && 2666 rtwdev->hal.cv == CHIP_CBV) { 2667 rtw89_write16_mask(rtwdev, 2668 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2669 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2670 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2671 BIT(12)); 2672 } 2673 2674 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2675 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2676 2677 return ret; 2678 } 2679 2680 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2681 { 2682 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2683 u32 val, reg; 2684 int ret; 2685 2686 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2687 if (ret) 2688 return ret; 2689 2690 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2691 val = rtw89_read32(rtwdev, reg); 2692 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2693 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2694 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2695 rtw89_write32(rtwdev, reg, val); 2696 2697 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2698 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2699 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2700 } 2701 2702 return 0; 2703 } 2704 2705 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2706 { 2707 const struct rtw89_dle_mem *cfg; 2708 2709 cfg = get_dle_mem_cfg(rtwdev, mode); 2710 if (!cfg) { 2711 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2712 return false; 2713 } 2714 2715 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2716 } 2717 2718 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2719 { 2720 u32 val, reg; 2721 int ret; 2722 2723 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2724 if (ret) 2725 return ret; 2726 2727 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2728 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2729 val = rtw89_read32(rtwdev, reg); 2730 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2731 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2732 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2733 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2734 val |= B_AX_HW_CTS2SELF_EN; 2735 rtw89_write32(rtwdev, reg, val); 2736 2737 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2738 val = rtw89_read32(rtwdev, reg); 2739 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2740 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2741 rtw89_write32(rtwdev, reg, val); 2742 } 2743 2744 if (mac_idx == RTW89_MAC_0) { 2745 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2746 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2747 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2748 B_AX_PTCL_TRIGGER_SS_EN_0 | 2749 B_AX_PTCL_TRIGGER_SS_EN_1 | 2750 B_AX_PTCL_TRIGGER_SS_EN_UL); 2751 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2752 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2753 } else if (mac_idx == RTW89_MAC_1) { 2754 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2755 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2756 } 2757 2758 return 0; 2759 } 2760 2761 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2762 { 2763 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2764 u32 reg; 2765 int ret; 2766 2767 if (chip_id != RTL8852B) 2768 return 0; 2769 2770 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2771 if (ret) 2772 return ret; 2773 2774 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2775 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2776 2777 return 0; 2778 } 2779 2780 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2781 { 2782 int ret; 2783 2784 ret = scheduler_init_ax(rtwdev, mac_idx); 2785 if (ret) { 2786 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2787 return ret; 2788 } 2789 2790 ret = addr_cam_init_ax(rtwdev, mac_idx); 2791 if (ret) { 2792 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2793 ret); 2794 return ret; 2795 } 2796 2797 ret = rx_fltr_init_ax(rtwdev, mac_idx); 2798 if (ret) { 2799 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2800 ret); 2801 return ret; 2802 } 2803 2804 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 2805 if (ret) { 2806 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2807 ret); 2808 return ret; 2809 } 2810 2811 ret = nav_ctrl_init_ax(rtwdev); 2812 if (ret) { 2813 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2814 ret); 2815 return ret; 2816 } 2817 2818 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 2819 if (ret) { 2820 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2821 mac_idx, ret); 2822 return ret; 2823 } 2824 2825 ret = tmac_init_ax(rtwdev, mac_idx); 2826 if (ret) { 2827 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2828 return ret; 2829 } 2830 2831 ret = trxptcl_init_ax(rtwdev, mac_idx); 2832 if (ret) { 2833 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2834 return ret; 2835 } 2836 2837 ret = rmac_init_ax(rtwdev, mac_idx); 2838 if (ret) { 2839 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2840 return ret; 2841 } 2842 2843 ret = cmac_com_init_ax(rtwdev, mac_idx); 2844 if (ret) { 2845 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2846 return ret; 2847 } 2848 2849 ret = ptcl_init_ax(rtwdev, mac_idx); 2850 if (ret) { 2851 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2852 return ret; 2853 } 2854 2855 ret = cmac_dma_init_ax(rtwdev, mac_idx); 2856 if (ret) { 2857 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2858 return ret; 2859 } 2860 2861 return ret; 2862 } 2863 2864 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2865 struct rtw89_mac_c2h_info *c2h_info) 2866 { 2867 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2868 struct rtw89_mac_h2c_info h2c_info = {0}; 2869 u32 ret; 2870 2871 mac->cnv_efuse_state(rtwdev, false); 2872 2873 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2874 h2c_info.content_len = 0; 2875 2876 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2877 if (ret) 2878 goto out; 2879 2880 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2881 ret = -EINVAL; 2882 2883 out: 2884 mac->cnv_efuse_state(rtwdev, true); 2885 2886 return ret; 2887 } 2888 2889 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2890 { 2891 struct rtw89_efuse *efuse = &rtwdev->efuse; 2892 struct rtw89_hal *hal = &rtwdev->hal; 2893 const struct rtw89_chip_info *chip = rtwdev->chip; 2894 struct rtw89_mac_c2h_info c2h_info = {0}; 2895 const struct rtw89_c2hreg_phycap *phycap; 2896 u8 tx_nss; 2897 u8 rx_nss; 2898 u8 tx_ant; 2899 u8 rx_ant; 2900 u32 ret; 2901 2902 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2903 if (ret) 2904 return ret; 2905 2906 phycap = &c2h_info.u.phycap; 2907 2908 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 2909 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 2910 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 2911 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2912 2913 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2914 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2915 2916 if (tx_ant == 1) 2917 hal->antenna_tx = RF_B; 2918 if (rx_ant == 1) 2919 hal->antenna_rx = RF_B; 2920 2921 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2922 hal->antenna_tx = RF_B; 2923 hal->tx_path_diversity = true; 2924 } 2925 2926 if (chip->rf_path_num == 1) { 2927 hal->antenna_tx = RF_A; 2928 hal->antenna_rx = RF_A; 2929 if ((efuse->rfe_type % 3) == 2) 2930 hal->ant_diversity = true; 2931 } 2932 2933 rtw89_debug(rtwdev, RTW89_DBG_FW, 2934 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2935 hal->tx_nss, tx_nss, chip->tx_nss, 2936 hal->rx_nss, rx_nss, chip->rx_nss); 2937 rtw89_debug(rtwdev, RTW89_DBG_FW, 2938 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2939 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2940 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2941 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2942 2943 return 0; 2944 } 2945 2946 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2947 u16 tx_en_u16, u16 mask_u16) 2948 { 2949 u32 ret; 2950 struct rtw89_mac_c2h_info c2h_info = {0}; 2951 struct rtw89_mac_h2c_info h2c_info = {0}; 2952 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 2953 2954 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2955 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 2956 2957 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 2958 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 2959 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 2960 2961 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2962 if (ret) 2963 return ret; 2964 2965 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2966 return -EINVAL; 2967 2968 return 0; 2969 } 2970 2971 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2972 u16 tx_en, u16 tx_en_mask) 2973 { 2974 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 2975 u16 val; 2976 int ret; 2977 2978 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2979 if (ret) 2980 return ret; 2981 2982 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2983 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2984 tx_en, tx_en_mask); 2985 2986 val = rtw89_read16(rtwdev, reg); 2987 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2988 rtw89_write16(rtwdev, reg, val); 2989 2990 return 0; 2991 } 2992 2993 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2994 u32 tx_en, u32 tx_en_mask) 2995 { 2996 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 2997 u32 val; 2998 int ret; 2999 3000 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3001 if (ret) 3002 return ret; 3003 3004 val = rtw89_read32(rtwdev, reg); 3005 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3006 rtw89_write32(rtwdev, reg, val); 3007 3008 return 0; 3009 } 3010 3011 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3012 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3013 { 3014 int ret; 3015 3016 *tx_en = rtw89_read16(rtwdev, 3017 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3018 3019 switch (sel) { 3020 case RTW89_SCH_TX_SEL_ALL: 3021 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3022 B_AX_CTN_TXEN_ALL_MASK); 3023 if (ret) 3024 return ret; 3025 break; 3026 case RTW89_SCH_TX_SEL_HIQ: 3027 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3028 0, B_AX_CTN_TXEN_HGQ); 3029 if (ret) 3030 return ret; 3031 break; 3032 case RTW89_SCH_TX_SEL_MG0: 3033 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3034 0, B_AX_CTN_TXEN_MGQ); 3035 if (ret) 3036 return ret; 3037 break; 3038 case RTW89_SCH_TX_SEL_MACID: 3039 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3040 B_AX_CTN_TXEN_ALL_MASK); 3041 if (ret) 3042 return ret; 3043 break; 3044 default: 3045 return 0; 3046 } 3047 3048 return 0; 3049 } 3050 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3051 3052 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3053 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3054 { 3055 int ret; 3056 3057 *tx_en = rtw89_read32(rtwdev, 3058 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3059 3060 switch (sel) { 3061 case RTW89_SCH_TX_SEL_ALL: 3062 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3063 B_AX_CTN_TXEN_ALL_MASK_V1); 3064 if (ret) 3065 return ret; 3066 break; 3067 case RTW89_SCH_TX_SEL_HIQ: 3068 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3069 0, B_AX_CTN_TXEN_HGQ); 3070 if (ret) 3071 return ret; 3072 break; 3073 case RTW89_SCH_TX_SEL_MG0: 3074 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3075 0, B_AX_CTN_TXEN_MGQ); 3076 if (ret) 3077 return ret; 3078 break; 3079 case RTW89_SCH_TX_SEL_MACID: 3080 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3081 B_AX_CTN_TXEN_ALL_MASK_V1); 3082 if (ret) 3083 return ret; 3084 break; 3085 default: 3086 return 0; 3087 } 3088 3089 return 0; 3090 } 3091 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3092 3093 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3094 { 3095 int ret; 3096 3097 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3098 if (ret) 3099 return ret; 3100 3101 return 0; 3102 } 3103 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3104 3105 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3106 { 3107 int ret; 3108 3109 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3110 B_AX_CTN_TXEN_ALL_MASK_V1); 3111 if (ret) 3112 return ret; 3113 3114 return 0; 3115 } 3116 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3117 3118 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3119 { 3120 u32 val, reg; 3121 int ret; 3122 3123 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3124 val = buf_len; 3125 val |= B_AX_WD_BUF_REQ_EXEC; 3126 rtw89_write32(rtwdev, reg, val); 3127 3128 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3129 3130 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3131 1, 2000, false, rtwdev, reg); 3132 if (ret) 3133 return ret; 3134 3135 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3136 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3137 return -ENOENT; 3138 3139 return 0; 3140 } 3141 3142 static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3143 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3144 { 3145 u32 val, cmd_type, reg; 3146 int ret; 3147 3148 cmd_type = ctrl_para->cmd_type; 3149 3150 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3151 val = 0; 3152 val = u32_replace_bits(val, ctrl_para->start_pktid, 3153 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3154 val = u32_replace_bits(val, ctrl_para->end_pktid, 3155 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3156 rtw89_write32(rtwdev, reg, val); 3157 3158 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3159 val = 0; 3160 val = u32_replace_bits(val, ctrl_para->src_pid, 3161 B_AX_CPUQ_OP_SRC_PID_MASK); 3162 val = u32_replace_bits(val, ctrl_para->src_qid, 3163 B_AX_CPUQ_OP_SRC_QID_MASK); 3164 val = u32_replace_bits(val, ctrl_para->dst_pid, 3165 B_AX_CPUQ_OP_DST_PID_MASK); 3166 val = u32_replace_bits(val, ctrl_para->dst_qid, 3167 B_AX_CPUQ_OP_DST_QID_MASK); 3168 rtw89_write32(rtwdev, reg, val); 3169 3170 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3171 val = 0; 3172 val = u32_replace_bits(val, cmd_type, 3173 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3174 val = u32_replace_bits(val, ctrl_para->macid, 3175 B_AX_CPUQ_OP_MACID_MASK); 3176 val = u32_replace_bits(val, ctrl_para->pkt_num, 3177 B_AX_CPUQ_OP_PKTNUM_MASK); 3178 val |= B_AX_WD_CPUQ_OP_EXEC; 3179 rtw89_write32(rtwdev, reg, val); 3180 3181 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3182 3183 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3184 1, 2000, false, rtwdev, reg); 3185 if (ret) 3186 return ret; 3187 3188 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3189 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3190 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3191 3192 return 0; 3193 } 3194 3195 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 3196 { 3197 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3198 const struct rtw89_dle_mem *cfg; 3199 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3200 u16 pkt_id; 3201 int ret; 3202 3203 cfg = get_dle_mem_cfg(rtwdev, mode); 3204 if (!cfg) { 3205 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3206 return -EINVAL; 3207 } 3208 3209 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3210 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3211 return -EINVAL; 3212 } 3213 3214 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3215 3216 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3217 if (ret) { 3218 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3219 return ret; 3220 } 3221 3222 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3223 ctrl_para.start_pktid = pkt_id; 3224 ctrl_para.end_pktid = pkt_id; 3225 ctrl_para.pkt_num = 0; 3226 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3227 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3228 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3229 if (ret) { 3230 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3231 return -EFAULT; 3232 } 3233 3234 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3235 if (ret) { 3236 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3237 return ret; 3238 } 3239 3240 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3241 ctrl_para.start_pktid = pkt_id; 3242 ctrl_para.end_pktid = pkt_id; 3243 ctrl_para.pkt_num = 0; 3244 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3245 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3246 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3247 if (ret) { 3248 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3249 return -EFAULT; 3250 } 3251 3252 return 0; 3253 } 3254 3255 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3256 { 3257 int ret; 3258 u32 reg; 3259 u8 val; 3260 3261 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3262 if (ret) 3263 return ret; 3264 3265 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3266 3267 ret = read_poll_timeout(rtw89_read8, val, 3268 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3269 SW_CVR_DUR_US, 3270 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3271 false, rtwdev, reg); 3272 if (ret) 3273 return ret; 3274 3275 return 0; 3276 } 3277 3278 static int band1_enable_ax(struct rtw89_dev *rtwdev) 3279 { 3280 int ret, i; 3281 u32 sleep_bak[4] = {0}; 3282 u32 pause_bak[4] = {0}; 3283 u32 tx_en; 3284 3285 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3286 if (ret) { 3287 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3288 return ret; 3289 } 3290 3291 for (i = 0; i < 4; i++) { 3292 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3293 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3294 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3295 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3296 } 3297 3298 ret = band_idle_ck_b(rtwdev, 0); 3299 if (ret) { 3300 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3301 return ret; 3302 } 3303 3304 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 3305 if (ret) { 3306 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3307 return ret; 3308 } 3309 3310 for (i = 0; i < 4; i++) { 3311 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3312 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3313 } 3314 3315 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3316 if (ret) { 3317 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3318 return ret; 3319 } 3320 3321 ret = cmac_func_en_ax(rtwdev, 1, true); 3322 if (ret) { 3323 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3324 return ret; 3325 } 3326 3327 ret = cmac_init_ax(rtwdev, 1); 3328 if (ret) { 3329 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3330 return ret; 3331 } 3332 3333 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3334 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3335 3336 return 0; 3337 } 3338 3339 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3340 { 3341 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3342 3343 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3344 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3345 } 3346 3347 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3348 { 3349 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3350 3351 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3352 } 3353 3354 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3355 { 3356 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3357 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3358 3359 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3360 B_AX_TX_GET_ERRPKTID_INT_EN | 3361 B_AX_TX_NXT_ERRPKTID_INT_EN | 3362 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3363 B_AX_TX_OFFSET_ERR_INT_EN | 3364 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3365 if (chip_id == RTL8852C) 3366 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3367 B_AX_TX_ETH_TYPE_ERR_EN | 3368 B_AX_TX_LLC_PRE_ERR_EN | 3369 B_AX_TX_NW_TYPE_ERR_EN | 3370 B_AX_TX_KSRCH_ERR_EN); 3371 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3372 imr->mpdu_tx_imr_set); 3373 3374 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3375 B_AX_GETPKTID_ERR_INT_EN | 3376 B_AX_MHDRLEN_ERR_INT_EN | 3377 B_AX_RPT_ERR_INT_EN); 3378 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3379 imr->mpdu_rx_imr_set); 3380 } 3381 3382 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3383 { 3384 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3385 3386 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3387 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3388 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3389 B_AX_PLE_B_PKTID_ERR_INT_EN); 3390 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3391 imr->sta_sch_imr_set); 3392 } 3393 3394 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3395 { 3396 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3397 3398 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3399 imr->txpktctl_imr_b0_clr); 3400 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3401 imr->txpktctl_imr_b0_set); 3402 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3403 imr->txpktctl_imr_b1_clr); 3404 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3405 imr->txpktctl_imr_b1_set); 3406 } 3407 3408 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3409 { 3410 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3411 3412 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3413 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3414 } 3415 3416 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3417 { 3418 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3419 3420 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3421 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3422 } 3423 3424 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3425 { 3426 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3427 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3428 } 3429 3430 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3431 { 3432 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3433 3434 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3435 imr->host_disp_imr_clr); 3436 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3437 imr->host_disp_imr_set); 3438 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3439 imr->cpu_disp_imr_clr); 3440 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3441 imr->cpu_disp_imr_set); 3442 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3443 imr->other_disp_imr_clr); 3444 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3445 imr->other_disp_imr_set); 3446 } 3447 3448 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3449 { 3450 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3451 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3452 } 3453 3454 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3455 { 3456 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3457 3458 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3459 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3460 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3461 B_AX_BBRPT_CHINFO_IMR_CLR); 3462 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3463 imr->bbrpt_err_imr_set); 3464 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3465 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3466 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3467 } 3468 3469 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3470 { 3471 u32 reg; 3472 3473 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3474 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3475 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3476 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3477 } 3478 3479 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3480 { 3481 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3482 u32 reg; 3483 3484 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3485 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3486 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3487 } 3488 3489 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3490 { 3491 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3492 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3493 u32 reg; 3494 3495 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3496 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3497 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3498 3499 if (chip_id == RTL8852C) { 3500 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3501 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3502 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3503 } 3504 } 3505 3506 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3507 { 3508 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3509 u32 reg; 3510 3511 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3512 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3513 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3514 } 3515 3516 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3517 { 3518 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3519 u32 reg; 3520 3521 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3522 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3523 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3524 } 3525 3526 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3527 { 3528 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3529 u32 reg; 3530 3531 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3532 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3533 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3534 } 3535 3536 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3537 enum rtw89_mac_hwmod_sel sel) 3538 { 3539 int ret; 3540 3541 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3542 if (ret) { 3543 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3544 sel, mac_idx); 3545 return ret; 3546 } 3547 3548 if (sel == RTW89_DMAC_SEL) { 3549 rtw89_wdrls_imr_enable(rtwdev); 3550 rtw89_wsec_imr_enable(rtwdev); 3551 rtw89_mpdu_trx_imr_enable(rtwdev); 3552 rtw89_sta_sch_imr_enable(rtwdev); 3553 rtw89_txpktctl_imr_enable(rtwdev); 3554 rtw89_wde_imr_enable(rtwdev); 3555 rtw89_ple_imr_enable(rtwdev); 3556 rtw89_pktin_imr_enable(rtwdev); 3557 rtw89_dispatcher_imr_enable(rtwdev); 3558 rtw89_cpuio_imr_enable(rtwdev); 3559 rtw89_bbrpt_imr_enable(rtwdev); 3560 } else if (sel == RTW89_CMAC_SEL) { 3561 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3562 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3563 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3564 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3565 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3566 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3567 } else { 3568 return -EINVAL; 3569 } 3570 3571 return 0; 3572 } 3573 3574 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3575 { 3576 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3577 3578 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3579 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3580 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3581 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3582 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 3583 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3584 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3585 } 3586 3587 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3588 { 3589 int ret = 0; 3590 3591 if (enable) { 3592 ret = band1_enable_ax(rtwdev); 3593 if (ret) { 3594 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3595 return ret; 3596 } 3597 3598 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3599 if (ret) { 3600 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3601 return ret; 3602 } 3603 } else { 3604 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3605 return -EINVAL; 3606 } 3607 3608 return 0; 3609 } 3610 3611 static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3612 { 3613 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3614 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3615 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3616 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3617 B_AX_RLSRPT0_FLTR_MAP_MASK); 3618 } else { 3619 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3620 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3621 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3622 B_AX_RLSRPT0_FLTR_MAP_MASK); 3623 } 3624 3625 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3626 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3627 3628 return 0; 3629 } 3630 3631 static int trx_init_ax(struct rtw89_dev *rtwdev) 3632 { 3633 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3634 int ret; 3635 3636 ret = dmac_init_ax(rtwdev, 0); 3637 if (ret) { 3638 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3639 return ret; 3640 } 3641 3642 ret = cmac_init_ax(rtwdev, 0); 3643 if (ret) { 3644 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3645 return ret; 3646 } 3647 3648 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3649 ret = dbcc_enable_ax(rtwdev, true); 3650 if (ret) { 3651 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3652 return ret; 3653 } 3654 } 3655 3656 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3657 if (ret) { 3658 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3659 return ret; 3660 } 3661 3662 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3663 if (ret) { 3664 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3665 return ret; 3666 } 3667 3668 err_imr_ctrl_ax(rtwdev, true); 3669 3670 ret = set_host_rpr_ax(rtwdev); 3671 if (ret) { 3672 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3673 return ret; 3674 } 3675 3676 return 0; 3677 } 3678 3679 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3680 { 3681 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3682 u32 val32; 3683 3684 if (chip_id == RTL8852B || chip_id == RTL8851B) { 3685 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3686 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3687 return; 3688 } 3689 3690 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3691 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3692 3693 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3694 val32 |= B_AX_FS_WDT_INT; 3695 val32 &= ~B_AX_FS_WDT_INT_MSK; 3696 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3697 } 3698 3699 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3700 { 3701 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3702 3703 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3704 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3705 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3706 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3707 3708 rtw89_disable_fw_watchdog(rtwdev); 3709 3710 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3711 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3712 } 3713 3714 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3715 bool dlfw, bool include_bb) 3716 { 3717 u32 val; 3718 int ret; 3719 3720 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3721 return -EFAULT; 3722 3723 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3724 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3725 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3726 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3727 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3728 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3729 3730 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3731 3732 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3733 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3734 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3735 B_AX_WCPU_FWDL_STS_MASK); 3736 3737 if (dlfw) 3738 val |= B_AX_WCPU_FWDL_EN; 3739 3740 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3741 3742 if (rtwdev->chip->chip_id == RTL8852B) 3743 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3744 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3745 3746 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3747 boot_reason); 3748 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3749 3750 if (!dlfw) { 3751 mdelay(5); 3752 3753 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3754 if (ret) 3755 return ret; 3756 } 3757 3758 return 0; 3759 } 3760 3761 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 3762 { 3763 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3764 u32 val; 3765 3766 if (chip_id == RTL8852C) 3767 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3768 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3769 else 3770 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3771 B_AX_PKT_BUF_EN; 3772 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3773 } 3774 3775 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 3776 { 3777 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3778 u32 val; 3779 3780 if (chip_id == RTL8851B) 3781 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3782 else 3783 val = B_AX_DISPATCHER_CLK_EN; 3784 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3785 3786 if (chip_id != RTL8852C) 3787 return; 3788 3789 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3790 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3791 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3792 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3793 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3794 3795 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3796 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3797 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3798 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3799 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3800 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3801 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3802 } 3803 3804 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3805 { 3806 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3807 int ret; 3808 3809 mac->hci_func_en(rtwdev); 3810 mac->dmac_func_pre_en(rtwdev); 3811 3812 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3813 if (ret) { 3814 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3815 return ret; 3816 } 3817 3818 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 3819 if (ret) { 3820 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3821 return ret; 3822 } 3823 3824 return ret; 3825 } 3826 3827 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3828 { 3829 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3830 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3831 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3832 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3833 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3834 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3835 3836 return 0; 3837 } 3838 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3839 3840 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3841 { 3842 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3843 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3844 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3845 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3846 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3847 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3848 3849 return 0; 3850 } 3851 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3852 3853 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 3854 { 3855 int ret; 3856 3857 ret = rtw89_mac_power_switch(rtwdev, true); 3858 if (ret) { 3859 rtw89_mac_power_switch(rtwdev, false); 3860 ret = rtw89_mac_power_switch(rtwdev, true); 3861 if (ret) 3862 return ret; 3863 } 3864 3865 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3866 3867 if (include_bb) { 3868 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 3869 if (rtwdev->dbcc_en) 3870 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 3871 } 3872 3873 ret = rtw89_mac_dmac_pre_init(rtwdev); 3874 if (ret) 3875 return ret; 3876 3877 if (rtwdev->hci.ops->mac_pre_init) { 3878 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3879 if (ret) 3880 return ret; 3881 } 3882 3883 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 3884 if (ret) 3885 return ret; 3886 3887 return 0; 3888 } 3889 3890 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3891 { 3892 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3893 const struct rtw89_chip_info *chip = rtwdev->chip; 3894 bool include_bb = !!chip->bbmcu_nr; 3895 int ret; 3896 3897 ret = rtw89_mac_partial_init(rtwdev, include_bb); 3898 if (ret) 3899 goto fail; 3900 3901 ret = rtw89_chip_enable_bb_rf(rtwdev); 3902 if (ret) 3903 goto fail; 3904 3905 ret = mac->sys_init(rtwdev); 3906 if (ret) 3907 goto fail; 3908 3909 ret = mac->trx_init(rtwdev); 3910 if (ret) 3911 goto fail; 3912 3913 if (rtwdev->hci.ops->mac_post_init) { 3914 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3915 if (ret) 3916 goto fail; 3917 } 3918 3919 rtw89_fw_send_all_early_h2c(rtwdev); 3920 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3921 3922 return ret; 3923 fail: 3924 rtw89_mac_power_switch(rtwdev, false); 3925 3926 return ret; 3927 } 3928 3929 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3930 { 3931 u8 i; 3932 3933 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 3934 return; 3935 3936 for (i = 0; i < 4; i++) { 3937 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3938 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3939 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3940 } 3941 } 3942 3943 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3944 { 3945 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 3946 return; 3947 3948 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3949 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3950 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3951 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3952 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3953 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3954 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3955 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3956 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3957 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3958 } 3959 3960 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3961 { 3962 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3963 u8 grp = macid >> 5; 3964 int ret; 3965 3966 /* If this is called by change_interface() in the case of P2P, it could 3967 * be power-off, so ignore this operation. 3968 */ 3969 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 3970 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3971 return 0; 3972 3973 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3974 if (ret) 3975 return ret; 3976 3977 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3978 3979 return 0; 3980 } 3981 3982 static const struct rtw89_port_reg rtw89_port_base_ax = { 3983 .port_cfg = R_AX_PORT_CFG_P0, 3984 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3985 .bcn_area = R_AX_BCN_AREA_P0, 3986 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3987 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3988 .tbtt_agg = R_AX_TBTT_AGG_P0, 3989 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3990 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3991 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3992 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3993 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3994 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3995 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3996 .tsftr_l = R_AX_TSFTR_LOW_P0, 3997 .tsftr_h = R_AX_TSFTR_HIGH_P0, 3998 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 3999 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4000 .mbssid = R_AX_MBSSID_CTRL, 4001 .mbssid_drop = R_AX_MBSSID_DROP_0, 4002 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4003 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4004 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4005 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4006 }; 4007 4008 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4009 struct rtw89_vif *rtwvif, u8 type) 4010 { 4011 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif->port); 4012 u32 reg_info, reg_ctrl; 4013 u32 val; 4014 int ret; 4015 4016 reg_info = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_DBG_INFO, rtwvif->mac_idx); 4017 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_DBG, rtwvif->mac_idx); 4018 4019 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4020 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4021 fsleep(100); 4022 4023 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4024 true, rtwdev, reg_info, mask); 4025 if (ret) 4026 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4027 } 4028 4029 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4030 { 4031 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4032 const struct rtw89_port_reg *p = mac->port_base; 4033 4034 rtw89_write32_set(rtwdev, R_AX_BCN_DROP_ALL0, BIT(rtwvif->port)); 4035 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 1); 4036 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 0); 4037 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 0); 4038 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4039 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK, 1); 4040 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 1); 4041 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4042 4043 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM0); 4044 if (rtwvif->port == RTW89_PORT_0) 4045 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM1); 4046 4047 rtw89_write32_clr(rtwdev, R_AX_BCN_DROP_ALL0, BIT(rtwvif->port)); 4048 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4049 fsleep(2); 4050 } 4051 4052 #define BCN_INTERVAL 100 4053 #define BCN_ERLY_DEF 160 4054 #define BCN_SETUP_DEF 2 4055 #define BCN_HOLD_DEF 200 4056 #define BCN_MASK_DEF 0 4057 #define TBTT_ERLY_DEF 5 4058 #define BCN_SET_UNIT 32 4059 #define BCN_ERLY_SET_DLY (10 * 2) 4060 4061 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4062 struct rtw89_vif *rtwvif) 4063 { 4064 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4065 const struct rtw89_port_reg *p = mac->port_base; 4066 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4067 const struct rtw89_chip_info *chip = rtwdev->chip; 4068 bool need_backup = false; 4069 u32 backup_val; 4070 4071 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 4072 return; 4073 4074 if (chip->chip_id == RTL8852A && rtwvif->port != RTW89_PORT_0) { 4075 need_backup = true; 4076 backup_val = rtw89_read32_port(rtwdev, rtwvif, p->tbtt_prohib); 4077 } 4078 4079 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4080 rtw89_mac_bcn_drop(rtwdev, rtwvif); 4081 4082 if (chip->chip_id == RTL8852A) { 4083 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 4084 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 4085 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 4086 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 4087 } 4088 4089 msleep(vif->bss_conf.beacon_int + 1); 4090 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 4091 B_AX_BRK_SETUP); 4092 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 4093 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 4094 4095 if (need_backup) 4096 rtw89_write32_port(rtwdev, rtwvif, p->tbtt_prohib, backup_val); 4097 } 4098 4099 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4100 struct rtw89_vif *rtwvif, bool en) 4101 { 4102 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4103 const struct rtw89_port_reg *p = mac->port_base; 4104 4105 if (en) 4106 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4107 else 4108 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4109 } 4110 4111 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4112 struct rtw89_vif *rtwvif, bool en) 4113 { 4114 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4115 const struct rtw89_port_reg *p = mac->port_base; 4116 4117 if (en) 4118 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4119 else 4120 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4121 } 4122 4123 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4124 struct rtw89_vif *rtwvif) 4125 { 4126 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4127 const struct rtw89_port_reg *p = mac->port_base; 4128 4129 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 4130 rtwvif->net_type); 4131 } 4132 4133 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4134 struct rtw89_vif *rtwvif) 4135 { 4136 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4137 const struct rtw89_port_reg *p = mac->port_base; 4138 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 4139 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4140 4141 if (en) 4142 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 4143 else 4144 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 4145 } 4146 4147 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4148 struct rtw89_vif *rtwvif) 4149 { 4150 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4151 const struct rtw89_port_reg *p = mac->port_base; 4152 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4153 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4154 u32 bit = B_AX_RX_BSSID_FIT_EN; 4155 4156 if (en) 4157 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 4158 else 4159 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 4160 } 4161 4162 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4163 struct rtw89_vif *rtwvif) 4164 { 4165 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4166 const struct rtw89_port_reg *p = mac->port_base; 4167 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4168 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4169 4170 if (en) 4171 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4172 else 4173 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4174 } 4175 4176 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4177 struct rtw89_vif *rtwvif, bool en) 4178 { 4179 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4180 const struct rtw89_port_reg *p = mac->port_base; 4181 4182 if (en) 4183 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4184 else 4185 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4186 } 4187 4188 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4189 struct rtw89_vif *rtwvif) 4190 { 4191 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 4192 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4193 4194 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4195 } 4196 4197 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4198 { 4199 struct rtw89_vif *rtwvif; 4200 4201 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4202 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4203 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4204 } 4205 4206 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4207 struct rtw89_vif *rtwvif) 4208 { 4209 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4210 const struct rtw89_port_reg *p = mac->port_base; 4211 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4212 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 4213 4214 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 4215 bcn_int); 4216 } 4217 4218 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4219 struct rtw89_vif *rtwvif) 4220 { 4221 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4222 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4223 const struct rtw89_port_reg *p = mac->port_base; 4224 u8 port = rtwvif->port; 4225 u32 reg; 4226 4227 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif->mac_idx); 4228 rtw89_write8(rtwdev, reg, win); 4229 } 4230 4231 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4232 struct rtw89_vif *rtwvif) 4233 { 4234 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4235 const struct rtw89_port_reg *p = mac->port_base; 4236 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4237 u32 addr; 4238 4239 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif->mac_idx); 4240 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4241 4242 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4243 vif->bss_conf.dtim_period); 4244 } 4245 4246 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4247 struct rtw89_vif *rtwvif) 4248 { 4249 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4250 const struct rtw89_port_reg *p = mac->port_base; 4251 4252 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4253 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4254 } 4255 4256 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4257 struct rtw89_vif *rtwvif) 4258 { 4259 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4260 const struct rtw89_port_reg *p = mac->port_base; 4261 4262 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4263 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4264 } 4265 4266 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4267 struct rtw89_vif *rtwvif) 4268 { 4269 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4270 const struct rtw89_port_reg *p = mac->port_base; 4271 4272 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 4273 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4274 } 4275 4276 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4277 struct rtw89_vif *rtwvif) 4278 { 4279 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4280 const struct rtw89_port_reg *p = mac->port_base; 4281 4282 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 4283 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4284 } 4285 4286 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4287 struct rtw89_vif *rtwvif) 4288 { 4289 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4290 const struct rtw89_port_reg *p = mac->port_base; 4291 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4292 static const u32 masks[RTW89_PORT_NUM] = { 4293 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4294 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4295 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4296 }; 4297 u8 port = rtwvif->port; 4298 u32 reg_base; 4299 u32 reg; 4300 u8 bss_color; 4301 4302 bss_color = vif->bss_conf.he_bss_color.color; 4303 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4304 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx); 4305 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4306 } 4307 4308 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4309 struct rtw89_vif *rtwvif) 4310 { 4311 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4312 const struct rtw89_port_reg *p = mac->port_base; 4313 u8 port = rtwvif->port; 4314 u32 reg; 4315 4316 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4317 return; 4318 4319 if (port == 0) { 4320 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif->mac_idx); 4321 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4322 } 4323 } 4324 4325 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4326 struct rtw89_vif *rtwvif) 4327 { 4328 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4329 const struct rtw89_port_reg *p = mac->port_base; 4330 u8 port = rtwvif->port; 4331 u32 reg; 4332 u32 val; 4333 4334 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif->mac_idx); 4335 val = rtw89_read32(rtwdev, reg); 4336 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4337 if (port == 0) 4338 val &= ~BIT(0); 4339 rtw89_write32(rtwdev, reg, val); 4340 } 4341 4342 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4343 struct rtw89_vif *rtwvif, bool enable) 4344 { 4345 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4346 const struct rtw89_port_reg *p = mac->port_base; 4347 4348 if (enable) 4349 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 4350 B_AX_PORT_FUNC_EN); 4351 else 4352 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 4353 B_AX_PORT_FUNC_EN); 4354 } 4355 4356 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4357 struct rtw89_vif *rtwvif) 4358 { 4359 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4360 const struct rtw89_port_reg *p = mac->port_base; 4361 4362 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 4363 BCN_ERLY_DEF); 4364 } 4365 4366 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4367 struct rtw89_vif *rtwvif) 4368 { 4369 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4370 const struct rtw89_port_reg *p = mac->port_base; 4371 u16 val; 4372 4373 if (rtwdev->chip->chip_id != RTL8852C) 4374 return; 4375 4376 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4377 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4378 return; 4379 4380 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4381 B_AX_TBTT_SHIFT_OFST_SIGN; 4382 4383 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 4384 B_AX_TBTT_SHIFT_OFST_MASK, val); 4385 } 4386 4387 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4388 struct rtw89_vif *rtwvif, 4389 struct rtw89_vif *rtwvif_src, 4390 u16 offset_tu) 4391 { 4392 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4393 const struct rtw89_port_reg *p = mac->port_base; 4394 u32 val, reg; 4395 4396 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4397 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif->port * 4, 4398 rtwvif->mac_idx); 4399 4400 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4401 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4402 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4403 } 4404 4405 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4406 struct rtw89_vif *rtwvif, 4407 struct rtw89_vif *rtwvif_src, 4408 u8 offset, int *n_offset) 4409 { 4410 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 4411 return; 4412 4413 /* adjust offset randomly to avoid beacon conflict */ 4414 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4415 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 4416 (*n_offset) * offset); 4417 4418 (*n_offset)++; 4419 } 4420 4421 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4422 { 4423 struct rtw89_vif *src = NULL, *tmp; 4424 u8 offset = 100, vif_aps = 0; 4425 int n_offset = 1; 4426 4427 rtw89_for_each_rtwvif(rtwdev, tmp) { 4428 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4429 src = tmp; 4430 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4431 vif_aps++; 4432 } 4433 4434 if (vif_aps == 0) 4435 return; 4436 4437 offset /= (vif_aps + 1); 4438 4439 rtw89_for_each_rtwvif(rtwdev, tmp) 4440 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4441 } 4442 4443 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4444 { 4445 int ret; 4446 4447 ret = rtw89_mac_port_update(rtwdev, rtwvif); 4448 if (ret) 4449 return ret; 4450 4451 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4452 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4453 4454 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4455 if (ret) 4456 return ret; 4457 4458 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4459 if (ret) 4460 return ret; 4461 4462 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4463 if (ret) 4464 return ret; 4465 4466 ret = rtw89_cam_init(rtwdev, rtwvif); 4467 if (ret) 4468 return ret; 4469 4470 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4471 if (ret) 4472 return ret; 4473 4474 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 4475 if (ret) 4476 return ret; 4477 4478 return 0; 4479 } 4480 4481 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4482 { 4483 int ret; 4484 4485 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4486 if (ret) 4487 return ret; 4488 4489 rtw89_cam_deinit(rtwdev, rtwvif); 4490 4491 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4492 if (ret) 4493 return ret; 4494 4495 return 0; 4496 } 4497 4498 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4499 { 4500 u8 port = rtwvif->port; 4501 4502 if (port >= RTW89_PORT_NUM) 4503 return -EINVAL; 4504 4505 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4506 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4507 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4508 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4509 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4510 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4511 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 4512 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif); 4513 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4514 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4515 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4516 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4517 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4518 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4519 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4520 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4521 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4522 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4523 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4524 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4525 rtw89_mac_port_tsf_resync_all(rtwdev); 4526 fsleep(BCN_ERLY_SET_DLY); 4527 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4528 4529 return 0; 4530 } 4531 4532 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4533 u64 *tsf) 4534 { 4535 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4536 const struct rtw89_port_reg *p = mac->port_base; 4537 u32 tsf_low, tsf_high; 4538 int ret; 4539 4540 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 4541 if (ret) 4542 return ret; 4543 4544 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 4545 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 4546 *tsf = (u64)tsf_high << 32 | tsf_low; 4547 4548 return 0; 4549 } 4550 4551 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4552 struct cfg80211_bss *bss, 4553 void *data) 4554 { 4555 const struct cfg80211_bss_ies *ies; 4556 const struct element *elem; 4557 bool *tolerated = data; 4558 4559 rcu_read_lock(); 4560 ies = rcu_dereference(bss->ies); 4561 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4562 ies->len); 4563 4564 if (!elem || elem->datalen < 10 || 4565 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4566 *tolerated = false; 4567 rcu_read_unlock(); 4568 } 4569 4570 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4571 struct ieee80211_vif *vif) 4572 { 4573 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4574 struct ieee80211_hw *hw = rtwdev->hw; 4575 bool tolerated = true; 4576 u32 reg; 4577 4578 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 4579 return; 4580 4581 if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR)) 4582 return; 4583 4584 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef, 4585 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4586 &tolerated); 4587 4588 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); 4589 if (tolerated) 4590 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4591 else 4592 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4593 } 4594 4595 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4596 { 4597 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4598 } 4599 4600 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4601 { 4602 int ret; 4603 4604 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 4605 RTW89_MAX_MAC_ID_NUM); 4606 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4607 return -ENOSPC; 4608 4609 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4610 if (ret) 4611 goto release_mac_id; 4612 4613 return 0; 4614 4615 release_mac_id: 4616 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4617 4618 return ret; 4619 } 4620 4621 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4622 { 4623 int ret; 4624 4625 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4626 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4627 4628 return ret; 4629 } 4630 4631 static void 4632 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4633 { 4634 } 4635 4636 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4637 { 4638 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4639 4640 return band == op->band_type && channel == op->primary_channel; 4641 } 4642 4643 static void 4644 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4645 u32 len) 4646 { 4647 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4648 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4649 struct rtw89_chan new; 4650 u8 reason, status, tx_fail, band, actual_period; 4651 u32 last_chan = rtwdev->scan_info.last_chan_idx; 4652 u16 chan; 4653 int ret; 4654 4655 if (!rtwvif) 4656 return; 4657 4658 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 4659 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 4660 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 4661 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 4662 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 4663 actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data); 4664 4665 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4666 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4667 4668 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4669 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4670 band, chan, reason, status, tx_fail, actual_period); 4671 4672 switch (reason) { 4673 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4674 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4675 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, false); 4676 ieee80211_stop_queues(rtwdev->hw); 4677 } 4678 return; 4679 case RTW89_SCAN_END_SCAN_NOTIFY: 4680 if (rtwvif && rtwvif->scan_req && 4681 last_chan < rtwvif->scan_req->n_channels) { 4682 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4683 if (ret) { 4684 rtw89_hw_scan_abort(rtwdev, vif); 4685 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4686 } 4687 } else { 4688 rtw89_hw_scan_complete(rtwdev, vif, false); 4689 } 4690 break; 4691 case RTW89_SCAN_ENTER_CH_NOTIFY: 4692 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4693 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4694 &rtwdev->scan_info.op_chan); 4695 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, true); 4696 ieee80211_wake_queues(rtwdev->hw); 4697 } else { 4698 rtw89_chan_create(&new, chan, chan, band, 4699 RTW89_CHANNEL_WIDTH_20); 4700 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4701 &new); 4702 } 4703 break; 4704 default: 4705 return; 4706 } 4707 } 4708 4709 static void 4710 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4711 struct sk_buff *skb) 4712 { 4713 struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4714 enum nl80211_cqm_rssi_threshold_event nl_event; 4715 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4716 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4717 u8 type, event, mac_id; 4718 s8 sig; 4719 4720 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4721 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4722 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4723 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4724 4725 if (mac_id != rtwvif->mac_id) 4726 return; 4727 4728 rtw89_debug(rtwdev, RTW89_DBG_FW, 4729 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4730 mac_id, type, sig, event); 4731 4732 switch (type) { 4733 case RTW89_BCN_FLTR_BEACON_LOSS: 4734 if (!rtwdev->scanning && !rtwvif->offchan) 4735 ieee80211_connection_loss(vif); 4736 else 4737 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4738 return; 4739 case RTW89_BCN_FLTR_NOTIFY: 4740 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4741 break; 4742 case RTW89_BCN_FLTR_RSSI: 4743 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4744 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4745 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4746 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4747 else 4748 return; 4749 break; 4750 default: 4751 return; 4752 } 4753 4754 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4755 } 4756 4757 static void 4758 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4759 u32 len) 4760 { 4761 struct rtw89_vif *rtwvif; 4762 4763 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4764 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4765 } 4766 4767 static void 4768 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4769 { 4770 /* N.B. This will run in interrupt context. */ 4771 4772 rtw89_debug(rtwdev, RTW89_DBG_FW, 4773 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4774 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4775 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4776 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4777 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4778 } 4779 4780 static void 4781 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4782 { 4783 /* N.B. This will run in interrupt context. */ 4784 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4785 const struct rtw89_c2h_done_ack *c2h = 4786 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4787 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4788 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4789 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4790 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4791 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4792 struct rtw89_completion_data data = {}; 4793 unsigned int cond; 4794 4795 rtw89_debug(rtwdev, RTW89_DBG_FW, 4796 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4797 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4798 4799 if (h2c_cat != H2C_CAT_MAC) 4800 return; 4801 4802 switch (h2c_class) { 4803 default: 4804 return; 4805 case H2C_CL_MAC_FW_OFLD: 4806 switch (h2c_func) { 4807 default: 4808 return; 4809 case H2C_FUNC_ADD_SCANOFLD_CH: 4810 case H2C_FUNC_SCANOFLD: 4811 cond = RTW89_FW_OFLD_WAIT_COND(0, h2c_func); 4812 break; 4813 } 4814 4815 data.err = !!h2c_return; 4816 rtw89_complete_cond(fw_ofld_wait, cond, &data); 4817 return; 4818 } 4819 } 4820 4821 static void 4822 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4823 { 4824 rtw89_fw_log_dump(rtwdev, c2h->data, len); 4825 } 4826 4827 static void 4828 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4829 { 4830 } 4831 4832 static void 4833 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 4834 u32 len) 4835 { 4836 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 4837 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 4838 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 4839 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 4840 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 4841 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 4842 struct rtw89_completion_data data = {}; 4843 unsigned int cond; 4844 4845 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 4846 pkt_id, pkt_op, pkt_len); 4847 4848 data.err = !pkt_len; 4849 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 4850 4851 rtw89_complete_cond(wait, cond, &data); 4852 } 4853 4854 static void 4855 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4856 u32 len) 4857 { 4858 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 4859 } 4860 4861 static void 4862 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4863 { 4864 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4865 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4866 4867 switch (func) { 4868 case H2C_FUNC_ADD_MCC: 4869 case H2C_FUNC_START_MCC: 4870 case H2C_FUNC_STOP_MCC: 4871 case H2C_FUNC_DEL_MCC_GROUP: 4872 case H2C_FUNC_RESET_MCC_GROUP: 4873 case H2C_FUNC_MCC_REQ_TSF: 4874 case H2C_FUNC_MCC_MACID_BITMAP: 4875 case H2C_FUNC_MCC_SYNC: 4876 case H2C_FUNC_MCC_SET_DURATION: 4877 break; 4878 default: 4879 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4880 "invalid MCC C2H RCV ACK: func %d\n", func); 4881 return; 4882 } 4883 4884 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4885 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4886 } 4887 4888 static void 4889 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4890 { 4891 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4892 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4893 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4894 struct rtw89_completion_data data = {}; 4895 unsigned int cond; 4896 bool next = false; 4897 4898 switch (func) { 4899 case H2C_FUNC_MCC_REQ_TSF: 4900 next = true; 4901 break; 4902 case H2C_FUNC_MCC_MACID_BITMAP: 4903 case H2C_FUNC_MCC_SYNC: 4904 case H2C_FUNC_MCC_SET_DURATION: 4905 break; 4906 case H2C_FUNC_ADD_MCC: 4907 case H2C_FUNC_START_MCC: 4908 case H2C_FUNC_STOP_MCC: 4909 case H2C_FUNC_DEL_MCC_GROUP: 4910 case H2C_FUNC_RESET_MCC_GROUP: 4911 default: 4912 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4913 "invalid MCC C2H REQ ACK: func %d\n", func); 4914 return; 4915 } 4916 4917 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4918 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 4919 group, func, retcode); 4920 4921 if (!retcode && next) 4922 return; 4923 4924 data.err = !!retcode; 4925 cond = RTW89_MCC_WAIT_COND(group, func); 4926 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4927 } 4928 4929 static void 4930 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4931 { 4932 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 4933 struct rtw89_completion_data data = {}; 4934 struct rtw89_mac_mcc_tsf_rpt *rpt; 4935 unsigned int cond; 4936 4937 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 4938 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 4939 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 4940 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 4941 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 4942 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 4943 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 4944 4945 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4946 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 4947 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 4948 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 4949 4950 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 4951 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4952 } 4953 4954 static void 4955 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4956 { 4957 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 4958 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 4959 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 4960 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 4961 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 4962 struct rtw89_completion_data data = {}; 4963 unsigned int cond; 4964 bool rsp = true; 4965 bool err; 4966 u8 func; 4967 4968 switch (status) { 4969 case RTW89_MAC_MCC_ADD_ROLE_OK: 4970 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 4971 func = H2C_FUNC_ADD_MCC; 4972 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 4973 break; 4974 case RTW89_MAC_MCC_START_GROUP_OK: 4975 case RTW89_MAC_MCC_START_GROUP_FAIL: 4976 func = H2C_FUNC_START_MCC; 4977 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 4978 break; 4979 case RTW89_MAC_MCC_STOP_GROUP_OK: 4980 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 4981 func = H2C_FUNC_STOP_MCC; 4982 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 4983 break; 4984 case RTW89_MAC_MCC_DEL_GROUP_OK: 4985 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 4986 func = H2C_FUNC_DEL_MCC_GROUP; 4987 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 4988 break; 4989 case RTW89_MAC_MCC_RESET_GROUP_OK: 4990 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 4991 func = H2C_FUNC_RESET_MCC_GROUP; 4992 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 4993 break; 4994 case RTW89_MAC_MCC_SWITCH_CH_OK: 4995 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 4996 case RTW89_MAC_MCC_TXNULL0_OK: 4997 case RTW89_MAC_MCC_TXNULL0_FAIL: 4998 case RTW89_MAC_MCC_TXNULL1_OK: 4999 case RTW89_MAC_MCC_TXNULL1_FAIL: 5000 case RTW89_MAC_MCC_SWITCH_EARLY: 5001 case RTW89_MAC_MCC_TBTT: 5002 case RTW89_MAC_MCC_DURATION_START: 5003 case RTW89_MAC_MCC_DURATION_END: 5004 rsp = false; 5005 break; 5006 default: 5007 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5008 "invalid MCC C2H STS RPT: status %d\n", status); 5009 return; 5010 } 5011 5012 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5013 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5014 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5015 5016 if (!rsp) 5017 return; 5018 5019 data.err = err; 5020 cond = RTW89_MCC_WAIT_COND(group, func); 5021 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5022 } 5023 5024 static 5025 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5026 struct sk_buff *c2h, u32 len) = { 5027 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5028 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5029 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5030 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 5031 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5032 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5033 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5034 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5035 }; 5036 5037 static 5038 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5039 struct sk_buff *c2h, u32 len) = { 5040 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5041 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5042 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5043 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5044 }; 5045 5046 static 5047 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5048 struct sk_buff *c2h, u32 len) = { 5049 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5050 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5051 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5052 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5053 }; 5054 5055 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 5056 { 5057 switch (class) { 5058 default: 5059 return false; 5060 case RTW89_MAC_C2H_CLASS_INFO: 5061 switch (func) { 5062 default: 5063 return false; 5064 case RTW89_MAC_C2H_FUNC_REC_ACK: 5065 case RTW89_MAC_C2H_FUNC_DONE_ACK: 5066 return true; 5067 } 5068 case RTW89_MAC_C2H_CLASS_OFLD: 5069 switch (func) { 5070 default: 5071 return false; 5072 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 5073 return true; 5074 } 5075 case RTW89_MAC_C2H_CLASS_MCC: 5076 return true; 5077 } 5078 } 5079 5080 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5081 u32 len, u8 class, u8 func) 5082 { 5083 void (*handler)(struct rtw89_dev *rtwdev, 5084 struct sk_buff *c2h, u32 len) = NULL; 5085 5086 switch (class) { 5087 case RTW89_MAC_C2H_CLASS_INFO: 5088 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 5089 handler = rtw89_mac_c2h_info_handler[func]; 5090 break; 5091 case RTW89_MAC_C2H_CLASS_OFLD: 5092 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 5093 handler = rtw89_mac_c2h_ofld_handler[func]; 5094 break; 5095 case RTW89_MAC_C2H_CLASS_MCC: 5096 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 5097 handler = rtw89_mac_c2h_mcc_handler[func]; 5098 break; 5099 case RTW89_MAC_C2H_CLASS_FWDBG: 5100 return; 5101 default: 5102 rtw89_info(rtwdev, "c2h class %d not support\n", class); 5103 return; 5104 } 5105 if (!handler) { 5106 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 5107 func); 5108 return; 5109 } 5110 handler(rtwdev, skb, len); 5111 } 5112 5113 static 5114 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 5115 enum rtw89_phy_idx phy_idx, 5116 u32 reg_base, u32 *cr) 5117 { 5118 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 5119 enum rtw89_qta_mode mode = dle_mem->mode; 5120 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 5121 5122 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 5123 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 5124 addr); 5125 goto error; 5126 } 5127 5128 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 5129 if (mode == RTW89_QTA_SCC) { 5130 rtw89_err(rtwdev, 5131 "[TXPWR] addr=0x%x but hw not enable\n", 5132 addr); 5133 goto error; 5134 } 5135 5136 *cr = addr; 5137 return true; 5138 5139 error: 5140 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 5141 addr, phy_idx); 5142 5143 return false; 5144 } 5145 5146 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 5147 { 5148 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 5149 int ret; 5150 5151 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5152 if (ret) 5153 return ret; 5154 5155 if (!enable) { 5156 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 5157 return 0; 5158 } 5159 5160 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 5161 B_AX_APP_MAC_INFO_RPT | 5162 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 5163 B_AX_PPDU_STAT_RPT_CRC32); 5164 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 5165 RTW89_PRPT_DEST_HOST); 5166 5167 return 0; 5168 } 5169 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 5170 5171 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 5172 { 5173 #define MAC_AX_TIME_TH_SH 5 5174 #define MAC_AX_LEN_TH_SH 4 5175 #define MAC_AX_TIME_TH_MAX 255 5176 #define MAC_AX_LEN_TH_MAX 255 5177 #define MAC_AX_TIME_TH_DEF 88 5178 #define MAC_AX_LEN_TH_DEF 4080 5179 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5180 struct ieee80211_hw *hw = rtwdev->hw; 5181 u32 rts_threshold = hw->wiphy->rts_threshold; 5182 u32 time_th, len_th; 5183 u32 reg; 5184 5185 if (rts_threshold == (u32)-1) { 5186 time_th = MAC_AX_TIME_TH_DEF; 5187 len_th = MAC_AX_LEN_TH_DEF; 5188 } else { 5189 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 5190 len_th = rts_threshold; 5191 } 5192 5193 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 5194 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 5195 5196 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 5197 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 5198 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 5199 } 5200 5201 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 5202 { 5203 bool empty; 5204 int ret; 5205 5206 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5207 return; 5208 5209 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 5210 10000, 200000, false, rtwdev); 5211 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 5212 rtw89_info(rtwdev, "timed out to flush queues\n"); 5213 } 5214 5215 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 5216 { 5217 u8 val; 5218 u16 val16; 5219 u32 val32; 5220 int ret; 5221 5222 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 5223 if (rtwdev->chip->chip_id != RTL8851B) 5224 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 5225 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 5226 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 5227 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 5228 if (rtwdev->chip->chip_id != RTL8851B) 5229 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 5230 5231 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 5232 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 5233 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 5234 5235 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 5236 if (ret) { 5237 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 5238 return ret; 5239 } 5240 val32 = val32 & B_AX_WL_RX_CTRL; 5241 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 5242 if (ret) { 5243 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 5244 return ret; 5245 } 5246 5247 switch (coex->pta_mode) { 5248 case RTW89_MAC_AX_COEX_RTK_MODE: 5249 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5250 val &= ~B_AX_BTMODE_MASK; 5251 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 5252 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5253 5254 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 5255 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 5256 5257 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 5258 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 5259 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 5260 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 5261 break; 5262 case RTW89_MAC_AX_COEX_CSR_MODE: 5263 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5264 val &= ~B_AX_BTMODE_MASK; 5265 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 5266 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5267 5268 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 5269 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 5270 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 5271 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 5272 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 5273 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 5274 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 5275 val16 |= B_AX_ENHANCED_BT; 5276 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 5277 5278 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 5279 break; 5280 default: 5281 return -EINVAL; 5282 } 5283 5284 switch (coex->direction) { 5285 case RTW89_MAC_AX_COEX_INNER: 5286 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5287 val = (val & ~BIT(2)) | BIT(1); 5288 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5289 break; 5290 case RTW89_MAC_AX_COEX_OUTPUT: 5291 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5292 val = val | BIT(1) | BIT(0); 5293 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5294 break; 5295 case RTW89_MAC_AX_COEX_INPUT: 5296 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5297 val = val & ~(BIT(2) | BIT(1)); 5298 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5299 break; 5300 default: 5301 return -EINVAL; 5302 } 5303 5304 return 0; 5305 } 5306 EXPORT_SYMBOL(rtw89_mac_coex_init); 5307 5308 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 5309 const struct rtw89_mac_ax_coex *coex) 5310 { 5311 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 5312 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 5313 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 5314 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 5315 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 5316 5317 switch (coex->pta_mode) { 5318 case RTW89_MAC_AX_COEX_RTK_MODE: 5319 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5320 MAC_AX_RTK_MODE); 5321 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 5322 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 5323 break; 5324 case RTW89_MAC_AX_COEX_CSR_MODE: 5325 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5326 MAC_AX_CSR_MODE); 5327 break; 5328 default: 5329 return -EINVAL; 5330 } 5331 5332 return 0; 5333 } 5334 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 5335 5336 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5337 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5338 { 5339 u32 val = 0, ret; 5340 5341 if (gnt_cfg->band[0].gnt_bt) 5342 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 5343 5344 if (gnt_cfg->band[0].gnt_bt_sw_en) 5345 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 5346 5347 if (gnt_cfg->band[0].gnt_wl) 5348 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 5349 5350 if (gnt_cfg->band[0].gnt_wl_sw_en) 5351 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 5352 5353 if (gnt_cfg->band[1].gnt_bt) 5354 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 5355 5356 if (gnt_cfg->band[1].gnt_bt_sw_en) 5357 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 5358 5359 if (gnt_cfg->band[1].gnt_wl) 5360 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 5361 5362 if (gnt_cfg->band[1].gnt_wl_sw_en) 5363 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 5364 5365 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 5366 if (ret) { 5367 rtw89_err(rtwdev, "Write LTE fail!\n"); 5368 return ret; 5369 } 5370 5371 return 0; 5372 } 5373 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 5374 5375 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 5376 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5377 { 5378 u32 val = 0; 5379 5380 if (gnt_cfg->band[0].gnt_bt) 5381 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5382 B_AX_GNT_BT_TX_VAL; 5383 else 5384 val |= B_AX_WL_ACT_VAL; 5385 5386 if (gnt_cfg->band[0].gnt_bt_sw_en) 5387 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5388 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5389 5390 if (gnt_cfg->band[0].gnt_wl) 5391 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5392 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5393 5394 if (gnt_cfg->band[0].gnt_wl_sw_en) 5395 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5396 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5397 5398 if (gnt_cfg->band[1].gnt_bt) 5399 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5400 B_AX_GNT_BT_TX_VAL; 5401 else 5402 val |= B_AX_WL_ACT_VAL; 5403 5404 if (gnt_cfg->band[1].gnt_bt_sw_en) 5405 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5406 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5407 5408 if (gnt_cfg->band[1].gnt_wl) 5409 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5410 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5411 5412 if (gnt_cfg->band[1].gnt_wl_sw_en) 5413 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5414 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5415 5416 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5417 5418 return 0; 5419 } 5420 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5421 5422 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5423 { 5424 u32 reg; 5425 u16 val; 5426 int ret; 5427 5428 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5429 if (ret) 5430 return ret; 5431 5432 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 5433 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5434 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5435 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5436 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5437 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5438 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5439 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 5440 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 5441 B_AX_PLT_EN; 5442 rtw89_write16(rtwdev, reg, val); 5443 5444 return 0; 5445 } 5446 5447 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5448 { 5449 u32 fw_sb; 5450 5451 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5452 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5453 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5454 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5455 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5456 else 5457 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5458 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5459 val = B_AX_TOGGLE | 5460 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5461 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5462 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5463 fsleep(1000); /* avoid BT FW loss information */ 5464 } 5465 5466 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5467 { 5468 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5469 } 5470 5471 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5472 { 5473 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5474 5475 val = wl ? val | BIT(2) : val & ~BIT(2); 5476 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5477 5478 return 0; 5479 } 5480 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5481 5482 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5483 { 5484 struct rtw89_btc *btc = &rtwdev->btc; 5485 struct rtw89_btc_dm *dm = &btc->dm; 5486 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5487 int i; 5488 5489 if (wl) 5490 return 0; 5491 5492 for (i = 0; i < RTW89_PHY_MAX; i++) { 5493 g[i].gnt_bt_sw_en = 1; 5494 g[i].gnt_bt = 1; 5495 g[i].gnt_wl_sw_en = 1; 5496 g[i].gnt_wl = 0; 5497 } 5498 5499 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5500 } 5501 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5502 5503 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5504 { 5505 const struct rtw89_chip_info *chip = rtwdev->chip; 5506 u8 val = 0; 5507 5508 if (chip->chip_id == RTL8852C) 5509 return false; 5510 else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 5511 chip->chip_id == RTL8851B) 5512 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5513 B_AX_LTE_MUX_CTRL_PATH >> 24); 5514 5515 return !!val; 5516 } 5517 5518 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 5519 { 5520 u32 reg; 5521 u16 cnt; 5522 5523 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 5524 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 5525 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 5526 5527 return cnt; 5528 } 5529 5530 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 5531 bool keep) 5532 { 5533 u32 reg; 5534 5535 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 5536 return; 5537 5538 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5539 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5540 if (keep) { 5541 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5542 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5543 BFRP_RX_STANDBY_TIMER_KEEP); 5544 } else { 5545 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5546 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5547 BFRP_RX_STANDBY_TIMER_RELEASE); 5548 } 5549 } 5550 5551 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5552 { 5553 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5554 u32 reg; 5555 u32 mask = mac->bfee_ctrl.mask; 5556 5557 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5558 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 5559 if (en) { 5560 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5561 rtw89_write32_set(rtwdev, reg, mask); 5562 } else { 5563 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5564 rtw89_write32_clr(rtwdev, reg, mask); 5565 } 5566 } 5567 5568 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 5569 { 5570 u32 reg; 5571 u32 val32; 5572 int ret; 5573 5574 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5575 if (ret) 5576 return ret; 5577 5578 /* AP mode set tx gid to 63 */ 5579 /* STA mode set tx gid to 0(default) */ 5580 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 5581 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5582 5583 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5584 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5585 5586 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5587 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5588 rtw89_write32(rtwdev, reg, val32); 5589 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5590 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5591 5592 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5593 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5594 B_AX_BFMEE_USE_NSTS | 5595 B_AX_BFMEE_CSI_GID_SEL | 5596 B_AX_BFMEE_CSI_FORCE_RETE_EN); 5597 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5598 rtw89_write32(rtwdev, reg, 5599 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5600 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5601 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5602 5603 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 5604 rtw89_write32_set(rtwdev, reg, 5605 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 5606 5607 return 0; 5608 } 5609 5610 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 5611 struct ieee80211_vif *vif, 5612 struct ieee80211_sta *sta) 5613 { 5614 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5615 u8 mac_idx = rtwvif->mac_idx; 5616 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5617 u8 port_sel = rtwvif->port; 5618 u8 sound_dim = 3, t; 5619 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5620 u32 reg; 5621 u16 val; 5622 int ret; 5623 5624 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5625 if (ret) 5626 return ret; 5627 5628 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5629 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5630 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5631 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5632 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5633 phy_cap[5]); 5634 sound_dim = min(sound_dim, t); 5635 } 5636 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5637 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5638 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5639 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5640 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5641 sta->deflink.vht_cap.cap); 5642 sound_dim = min(sound_dim, t); 5643 } 5644 nc = min(nc, sound_dim); 5645 nr = min(nr, sound_dim); 5646 5647 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5648 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5649 5650 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5651 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5652 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5653 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5654 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5655 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5656 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5657 5658 if (port_sel == 0) 5659 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5660 else 5661 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5662 5663 rtw89_write16(rtwdev, reg, val); 5664 5665 return 0; 5666 } 5667 5668 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 5669 struct ieee80211_vif *vif, 5670 struct ieee80211_sta *sta) 5671 { 5672 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5673 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5674 u32 reg; 5675 u8 mac_idx = rtwvif->mac_idx; 5676 int ret; 5677 5678 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5679 if (ret) 5680 return ret; 5681 5682 if (sta->deflink.he_cap.has_he) { 5683 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5684 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5685 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5686 } 5687 if (sta->deflink.vht_cap.vht_supported) { 5688 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5689 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5690 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5691 } 5692 if (sta->deflink.ht_cap.ht_supported) { 5693 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5694 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5695 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5696 } 5697 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5698 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5699 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5700 rtw89_write32(rtwdev, 5701 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5702 rrsc); 5703 5704 return 0; 5705 } 5706 5707 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 5708 struct ieee80211_vif *vif, 5709 struct ieee80211_sta *sta) 5710 { 5711 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5712 5713 if (rtw89_sta_has_beamformer_cap(sta)) { 5714 rtw89_debug(rtwdev, RTW89_DBG_BF, 5715 "initialize bfee for new association\n"); 5716 rtw89_mac_init_bfee_ax(rtwdev, rtwvif->mac_idx); 5717 rtw89_mac_set_csi_para_reg_ax(rtwdev, vif, sta); 5718 rtw89_mac_csi_rrsc_ax(rtwdev, vif, sta); 5719 } 5720 } 5721 5722 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5723 struct ieee80211_sta *sta) 5724 { 5725 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5726 5727 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 5728 } 5729 5730 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5731 struct ieee80211_bss_conf *conf) 5732 { 5733 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5734 u8 mac_idx = rtwvif->mac_idx; 5735 __le32 *p; 5736 5737 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 5738 5739 p = (__le32 *)conf->mu_group.membership; 5740 rtw89_write32(rtwdev, 5741 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 5742 le32_to_cpu(p[0])); 5743 rtw89_write32(rtwdev, 5744 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 5745 le32_to_cpu(p[1])); 5746 5747 p = (__le32 *)conf->mu_group.position; 5748 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 5749 le32_to_cpu(p[0])); 5750 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 5751 le32_to_cpu(p[1])); 5752 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 5753 le32_to_cpu(p[2])); 5754 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 5755 le32_to_cpu(p[3])); 5756 } 5757 5758 struct rtw89_mac_bf_monitor_iter_data { 5759 struct rtw89_dev *rtwdev; 5760 struct ieee80211_sta *down_sta; 5761 int count; 5762 }; 5763 5764 static 5765 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 5766 { 5767 struct rtw89_mac_bf_monitor_iter_data *iter_data = 5768 (struct rtw89_mac_bf_monitor_iter_data *)data; 5769 struct ieee80211_sta *down_sta = iter_data->down_sta; 5770 int *count = &iter_data->count; 5771 5772 if (down_sta == sta) 5773 return; 5774 5775 if (rtw89_sta_has_beamformer_cap(sta)) 5776 (*count)++; 5777 } 5778 5779 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 5780 struct ieee80211_sta *sta, bool disconnect) 5781 { 5782 struct rtw89_mac_bf_monitor_iter_data data; 5783 5784 data.rtwdev = rtwdev; 5785 data.down_sta = disconnect ? sta : NULL; 5786 data.count = 0; 5787 ieee80211_iterate_stations_atomic(rtwdev->hw, 5788 rtw89_mac_bf_monitor_calc_iter, 5789 &data); 5790 5791 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 5792 if (data.count) 5793 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5794 else 5795 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5796 } 5797 5798 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 5799 { 5800 struct rtw89_traffic_stats *stats = &rtwdev->stats; 5801 struct rtw89_vif *rtwvif; 5802 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 5803 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5804 bool keep_timer = true; 5805 bool old_keep_timer; 5806 5807 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5808 5809 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 5810 keep_timer = false; 5811 5812 if (keep_timer != old_keep_timer) { 5813 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5814 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 5815 keep_timer); 5816 } 5817 5818 if (en == old) 5819 return; 5820 5821 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5822 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 5823 } 5824 5825 static int 5826 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5827 u32 tx_time) 5828 { 5829 #define MAC_AX_DFLT_TX_TIME 5280 5830 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5831 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 5832 u32 reg; 5833 int ret = 0; 5834 5835 if (rtwsta->cctl_tx_time) { 5836 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 5837 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5838 } else { 5839 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5840 if (ret) { 5841 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 5842 return ret; 5843 } 5844 5845 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 5846 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 5847 max_tx_time >> 5); 5848 } 5849 5850 return ret; 5851 } 5852 5853 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5854 bool resume, u32 tx_time) 5855 { 5856 int ret = 0; 5857 5858 if (!resume) { 5859 rtwsta->cctl_tx_time = true; 5860 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5861 } else { 5862 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5863 rtwsta->cctl_tx_time = false; 5864 } 5865 5866 return ret; 5867 } 5868 5869 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5870 u32 *tx_time) 5871 { 5872 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5873 u32 reg; 5874 int ret = 0; 5875 5876 if (rtwsta->cctl_tx_time) { 5877 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 5878 } else { 5879 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5880 if (ret) { 5881 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 5882 return ret; 5883 } 5884 5885 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 5886 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 5887 } 5888 5889 return ret; 5890 } 5891 5892 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 5893 struct rtw89_sta *rtwsta, 5894 bool resume, u8 tx_retry) 5895 { 5896 int ret = 0; 5897 5898 rtwsta->data_tx_cnt_lmt = tx_retry; 5899 5900 if (!resume) { 5901 rtwsta->cctl_tx_retry_limit = true; 5902 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5903 } else { 5904 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5905 rtwsta->cctl_tx_retry_limit = false; 5906 } 5907 5908 return ret; 5909 } 5910 5911 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 5912 struct rtw89_sta *rtwsta, u8 *tx_retry) 5913 { 5914 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5915 u32 reg; 5916 int ret = 0; 5917 5918 if (rtwsta->cctl_tx_retry_limit) { 5919 *tx_retry = rtwsta->data_tx_cnt_lmt; 5920 } else { 5921 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5922 if (ret) { 5923 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 5924 return ret; 5925 } 5926 5927 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); 5928 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 5929 } 5930 5931 return ret; 5932 } 5933 5934 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 5935 struct rtw89_vif *rtwvif, bool en) 5936 { 5937 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5938 u8 mac_idx = rtwvif->mac_idx; 5939 u16 set = mac->muedca_ctrl.mask; 5940 u32 reg; 5941 u32 ret; 5942 5943 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5944 if (ret) 5945 return ret; 5946 5947 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 5948 if (en) 5949 rtw89_write16_set(rtwdev, reg, set); 5950 else 5951 rtw89_write16_clr(rtwdev, reg, set); 5952 5953 return 0; 5954 } 5955 5956 static 5957 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 5958 { 5959 u32 val32; 5960 int ret; 5961 5962 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5963 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 5964 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 5965 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 5966 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5967 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5968 5969 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5970 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5971 if (ret) { 5972 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 5973 offset, val, mask); 5974 return ret; 5975 } 5976 5977 return 0; 5978 } 5979 5980 static 5981 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 5982 { 5983 u32 val32; 5984 int ret; 5985 5986 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5987 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 5988 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 5989 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 5990 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5991 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5992 5993 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5994 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5995 if (ret) { 5996 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 5997 return ret; 5998 } 5999 6000 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 6001 6002 return 0; 6003 } 6004 6005 static 6006 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 6007 { 6008 static const enum rtw89_pkt_drop_sel sels[] = { 6009 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 6010 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 6011 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 6012 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 6013 }; 6014 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6015 struct rtw89_pkt_drop_params params = {0}; 6016 int i; 6017 6018 params.mac_band = RTW89_MAC_0; 6019 params.macid = rtwsta->mac_id; 6020 params.port = rtwvif->port; 6021 params.mbssid = 0; 6022 params.tf_trs = rtwvif->trigger; 6023 6024 for (i = 0; i < ARRAY_SIZE(sels); i++) { 6025 params.sel = sels[i]; 6026 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6027 } 6028 } 6029 6030 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 6031 { 6032 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 6033 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6034 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 6035 struct rtw89_vif *target = data; 6036 6037 if (rtwvif != target) 6038 return; 6039 6040 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 6041 } 6042 6043 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 6044 { 6045 ieee80211_iterate_stations_atomic(rtwdev->hw, 6046 rtw89_mac_pkt_drop_vif_iter, 6047 rtwvif); 6048 } 6049 6050 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 6051 enum rtw89_mac_idx band) 6052 { 6053 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6054 struct rtw89_pkt_drop_params params = {0}; 6055 bool empty; 6056 int i, ret = 0, try_cnt = 3; 6057 6058 params.mac_band = band; 6059 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 6060 6061 for (i = 0; i < try_cnt; i++) { 6062 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 6063 50000, false, rtwdev); 6064 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 6065 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6066 else 6067 return 0; 6068 } 6069 return ret; 6070 } 6071 6072 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 6073 { 6074 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 6075 6076 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 6077 } 6078 6079 static 6080 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 6081 bool h2c_or_fwdl) 6082 { 6083 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 6084 u8 val; 6085 6086 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 6087 1, FWDL_WAIT_CNT, false, 6088 rtwdev, R_AX_WCPU_FW_CTRL); 6089 } 6090 6091 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 6092 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 6093 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 6094 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 6095 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 6096 .rx_fltr = R_AX_RX_FLTR_OPT, 6097 .port_base = &rtw89_port_base_ax, 6098 .agg_len_ht = R_AX_AGG_LEN_HT_0, 6099 6100 .muedca_ctrl = { 6101 .addr = R_AX_MUEDCA_EN, 6102 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 6103 }, 6104 .bfee_ctrl = { 6105 .addr = R_AX_BFMEE_RESP_OPTION, 6106 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 6107 B_AX_BFMEE_HE_NDPA_EN, 6108 }, 6109 6110 .check_mac_en = rtw89_mac_check_mac_en_ax, 6111 .sys_init = sys_init_ax, 6112 .trx_init = trx_init_ax, 6113 .hci_func_en = rtw89_mac_hci_func_en_ax, 6114 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 6115 .dle_func_en = dle_func_en_ax, 6116 .dle_clk_en = dle_clk_en_ax, 6117 .bf_assoc = rtw89_mac_bf_assoc_ax, 6118 6119 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 6120 6121 .dle_mix_cfg = dle_mix_cfg_ax, 6122 .chk_dle_rdy = chk_dle_rdy_ax, 6123 .dle_buf_req = dle_buf_req_ax, 6124 .hfc_func_en = hfc_func_en_ax, 6125 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 6126 .hfc_mix_cfg = hfc_mix_cfg_ax, 6127 .hfc_get_mix_info = hfc_get_mix_info_ax, 6128 .wde_quota_cfg = wde_quota_cfg_ax, 6129 .ple_quota_cfg = ple_quota_cfg_ax, 6130 .set_cpuio = set_cpuio_ax, 6131 6132 .disable_cpu = rtw89_mac_disable_cpu_ax, 6133 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 6134 .fwdl_get_status = rtw89_fw_get_rdy_ax, 6135 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 6136 .parse_efuse_map = rtw89_parse_efuse_map_ax, 6137 .parse_phycap_map = rtw89_parse_phycap_map_ax, 6138 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 6139 6140 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 6141 6142 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 6143 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 6144 6145 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 6146 .dump_err_status = rtw89_mac_dump_err_status_ax, 6147 6148 .is_txq_empty = mac_is_txq_empty_ax, 6149 }; 6150 EXPORT_SYMBOL(rtw89_mac_gen_ax); 6151