1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "pci.h" 11 #include "ps.h" 12 #include "reg.h" 13 #include "util.h" 14 15 const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = { 16 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 17 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 18 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 19 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 20 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 21 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 22 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 25 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 26 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 29 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 31 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 33 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 34 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 35 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 36 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 37 }; 38 39 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 40 u32 val, enum rtw89_mac_mem_sel sel) 41 { 42 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 43 44 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 45 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val); 46 } 47 48 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 49 enum rtw89_mac_mem_sel sel) 50 { 51 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 52 53 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 54 return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY); 55 } 56 57 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 58 enum rtw89_mac_hwmod_sel sel) 59 { 60 u32 val, r_val; 61 62 if (sel == RTW89_DMAC_SEL) { 63 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 64 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 65 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 66 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 67 val = B_AX_CMAC_EN; 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 69 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 70 val = B_AX_CMAC1_FEN; 71 } else { 72 return -EINVAL; 73 } 74 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 75 (val & r_val) != val) 76 return -EFAULT; 77 78 return 0; 79 } 80 81 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 82 { 83 u8 lte_ctrl; 84 int ret; 85 86 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 87 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 88 if (ret) 89 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 90 91 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 92 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 93 94 return ret; 95 } 96 97 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 98 { 99 u8 lte_ctrl; 100 int ret; 101 102 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 103 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 104 if (ret) 105 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 106 107 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 108 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 109 110 return ret; 111 } 112 113 static 114 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 115 { 116 u32 ctrl_reg, data_reg, ctrl_data; 117 u32 val; 118 int ret; 119 120 switch (ctrl->type) { 121 case DLE_CTRL_TYPE_WDE: 122 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 123 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 124 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 125 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 126 B_AX_WDE_DFI_ACTIVE; 127 break; 128 case DLE_CTRL_TYPE_PLE: 129 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 130 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 131 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 132 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 133 B_AX_PLE_DFI_ACTIVE; 134 break; 135 default: 136 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 137 return -EINVAL; 138 } 139 140 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 141 142 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 143 1, 1000, false, rtwdev, ctrl_reg); 144 if (ret) { 145 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 146 ctrl_reg, ctrl_data); 147 return ret; 148 } 149 150 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 151 return 0; 152 } 153 154 static int dle_dfi_quota(struct rtw89_dev *rtwdev, 155 struct rtw89_mac_dle_dfi_quota *quota) 156 { 157 struct rtw89_mac_dle_dfi_ctrl ctrl; 158 int ret; 159 160 ctrl.type = quota->dle_type; 161 ctrl.target = DLE_DFI_TYPE_QUOTA; 162 ctrl.addr = quota->qtaid; 163 ret = dle_dfi_ctrl(rtwdev, &ctrl); 164 if (ret) { 165 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 166 return ret; 167 } 168 169 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 170 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 171 return 0; 172 } 173 174 static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 175 struct rtw89_mac_dle_dfi_qempty *qempty) 176 { 177 struct rtw89_mac_dle_dfi_ctrl ctrl; 178 u32 ret; 179 180 ctrl.type = qempty->dle_type; 181 ctrl.target = DLE_DFI_TYPE_QEMPTY; 182 ctrl.addr = qempty->grpsel; 183 ret = dle_dfi_ctrl(rtwdev, &ctrl); 184 if (ret) { 185 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 186 return ret; 187 } 188 189 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 190 return 0; 191 } 192 193 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 194 { 195 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 196 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 199 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 200 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 203 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 204 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 207 } 208 209 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 210 { 211 struct rtw89_mac_dle_dfi_qempty qempty; 212 struct rtw89_mac_dle_dfi_quota quota; 213 struct rtw89_mac_dle_dfi_ctrl ctrl; 214 u32 val, not_empty, i; 215 int ret; 216 217 qempty.dle_type = DLE_CTRL_TYPE_PLE; 218 qempty.grpsel = 0; 219 qempty.qempty = ~(u32)0; 220 ret = dle_dfi_qempty(rtwdev, &qempty); 221 if (ret) 222 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 223 else 224 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 225 226 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 227 if (!(not_empty & BIT(0))) 228 continue; 229 ctrl.type = DLE_CTRL_TYPE_PLE; 230 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 231 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 232 FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 233 ret = dle_dfi_ctrl(rtwdev, &ctrl); 234 if (ret) 235 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 236 else 237 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 238 FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 239 ctrl.out_data)); 240 } 241 242 quota.dle_type = DLE_CTRL_TYPE_PLE; 243 quota.qtaid = 6; 244 ret = dle_dfi_quota(rtwdev, "a); 245 if (ret) 246 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 247 else 248 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 249 quota.rsv_pgnum, quota.use_pgnum); 250 251 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 252 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 253 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 255 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 256 257 dump_err_status_dispatcher(rtwdev); 258 } 259 260 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 261 enum mac_ax_err_info err) 262 { 263 u32 dbg, event; 264 265 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 266 event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 267 268 switch (event) { 269 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 270 rtw89_info(rtwdev, "quota lost!\n"); 271 rtw89_mac_dump_qta_lost(rtwdev); 272 break; 273 default: 274 break; 275 } 276 } 277 278 static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 279 { 280 const struct rtw89_chip_info *chip = rtwdev->chip; 281 u32 dmac_err; 282 int i, ret; 283 284 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 285 if (ret) { 286 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 287 return; 288 } 289 290 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 291 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 292 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 293 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 294 295 if (dmac_err) { 296 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 298 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 299 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 300 if (chip->chip_id == RTL8852C) { 301 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 302 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 303 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 304 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 305 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 306 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 307 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 308 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 309 } 310 } 311 312 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 313 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 314 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 315 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 316 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 317 if (chip->chip_id == RTL8852C) 318 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 319 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 320 else 321 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 322 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 323 } 324 325 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 326 if (chip->chip_id == RTL8852C) { 327 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 328 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 329 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 330 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 331 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 332 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 333 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 334 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 335 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 337 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 339 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 341 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 343 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 344 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 345 346 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 347 B_AX_DBG_SEL0, 0x8B); 348 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 349 B_AX_DBG_SEL1, 0x8B); 350 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 351 B_AX_SEL_0XC0_MASK, 1); 352 for (i = 0; i < 0x10; i++) { 353 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 354 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 355 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 356 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 357 } 358 } else { 359 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 360 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 361 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 363 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 364 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 365 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 366 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 367 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 368 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 369 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 370 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 371 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 372 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 373 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 374 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 375 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 376 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 377 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 378 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 379 } 380 } 381 382 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 383 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 384 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 385 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 386 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 387 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 388 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 389 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 390 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 391 } 392 393 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 394 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 395 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 396 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 397 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 398 } 399 400 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 401 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 402 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 403 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 404 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 405 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 406 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 407 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 408 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 409 } 410 411 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 412 if (chip->chip_id == RTL8852C) { 413 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 414 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 415 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 416 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 417 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 419 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 421 } else { 422 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 423 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 424 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 425 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 426 } 427 } 428 429 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 430 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 431 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 432 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 433 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 434 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 435 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 436 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 437 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 438 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 439 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 440 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 441 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 442 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 443 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 444 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 445 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 446 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 447 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 448 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 449 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 450 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 451 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 452 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 453 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 454 if (chip->chip_id == RTL8852C) { 455 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 456 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 457 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 458 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 459 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 460 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 461 } else { 462 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 463 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 464 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 465 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 466 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 468 } 469 } 470 471 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 472 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 474 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 475 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 476 } 477 478 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 479 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 480 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 481 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 482 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 483 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 484 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 485 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 486 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 487 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 489 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 491 } 492 493 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 494 if (chip->chip_id == RTL8852C) { 495 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 501 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 503 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 505 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 507 } else { 508 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 509 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 510 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 511 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 512 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 513 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 514 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 515 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 516 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 517 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 518 } 519 } 520 521 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 522 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 523 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 524 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 525 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 526 } 527 } 528 529 static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev, 530 u8 band) 531 { 532 const struct rtw89_chip_info *chip = rtwdev->chip; 533 u32 offset = 0; 534 u32 cmac_err; 535 int ret; 536 537 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 538 if (ret) { 539 if (band) 540 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 541 else 542 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 543 return; 544 } 545 546 if (band) 547 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 548 549 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 550 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 551 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 552 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 553 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 554 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 555 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 556 557 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 558 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 559 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 560 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 561 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 562 } 563 564 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 565 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 566 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 567 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 568 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 569 } 570 571 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 572 if (chip->chip_id == RTL8852C) { 573 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 574 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 575 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 576 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 577 } else { 578 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 579 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 580 } 581 } 582 583 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 584 if (chip->chip_id == RTL8852C) { 585 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 586 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 587 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 588 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 589 } else { 590 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 591 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 592 } 593 } 594 595 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 596 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 597 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 598 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 599 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 600 } 601 602 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 603 if (chip->chip_id == RTL8852C) { 604 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 605 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 606 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 607 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 608 } else { 609 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 610 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 611 } 612 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 613 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 614 } 615 616 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 617 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 618 } 619 620 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 621 enum mac_ax_err_info err) 622 { 623 if (err != MAC_AX_ERR_L1_ERR_DMAC && 624 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 625 err != MAC_AX_ERR_L0_ERR_CMAC0 && 626 err != MAC_AX_ERR_L0_ERR_CMAC1 && 627 err != MAC_AX_ERR_RXI300) 628 return; 629 630 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 631 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 632 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 633 634 rtw89_mac_dump_dmac_err_status(rtwdev); 635 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0); 636 if (rtwdev->dbcc_en) 637 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1); 638 639 rtwdev->hci.ops->dump_err_status(rtwdev); 640 641 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 642 rtw89_mac_dump_l0_to_l1(rtwdev, err); 643 644 rtw89_info(rtwdev, "<---\n"); 645 } 646 647 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 648 { 649 struct rtw89_ser *ser = &rtwdev->ser; 650 u32 dmac_err, imr, isr; 651 int ret; 652 653 if (rtwdev->chip->chip_id == RTL8852C) { 654 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 655 if (ret) 656 return true; 657 658 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 659 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 660 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 661 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 662 663 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 664 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 665 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 666 return true; 667 } 668 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 669 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 670 return true; 671 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 672 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 673 return true; 674 } 675 } 676 677 return false; 678 } 679 680 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 681 { 682 u32 err, err_scnr; 683 int ret; 684 685 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 686 false, rtwdev, R_AX_HALT_C2H_CTRL); 687 if (ret) { 688 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 689 return ret; 690 } 691 692 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 693 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 694 695 err_scnr = RTW89_ERROR_SCENARIO(err); 696 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 697 err = MAC_AX_ERR_CPU_EXCEPTION; 698 else if (err_scnr == RTW89_WCPU_ASSERTION) 699 err = MAC_AX_ERR_ASSERTION; 700 else if (err_scnr == RTW89_RXI300_ERROR) 701 err = MAC_AX_ERR_RXI300; 702 703 if (rtw89_mac_suppress_log(rtwdev, err)) 704 return err; 705 706 rtw89_fw_st_dbg_dump(rtwdev); 707 rtw89_mac_dump_err_status(rtwdev, err); 708 709 return err; 710 } 711 EXPORT_SYMBOL(rtw89_mac_get_err_status); 712 713 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 714 { 715 struct rtw89_ser *ser = &rtwdev->ser; 716 u32 halt; 717 int ret = 0; 718 719 if (err > MAC_AX_SET_ERR_MAX) { 720 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 721 return -EINVAL; 722 } 723 724 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 725 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 726 if (ret) { 727 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 728 return -EFAULT; 729 } 730 731 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 732 733 if (ser->prehandle_l1 && 734 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 735 return 0; 736 737 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 738 739 return 0; 740 } 741 EXPORT_SYMBOL(rtw89_mac_set_err_status); 742 743 static int hfc_reset_param(struct rtw89_dev *rtwdev) 744 { 745 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 746 struct rtw89_hfc_param_ini param_ini = {NULL}; 747 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 748 749 switch (rtwdev->hci.type) { 750 case RTW89_HCI_TYPE_PCIE: 751 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 752 param->en = 0; 753 break; 754 default: 755 return -EINVAL; 756 } 757 758 if (param_ini.pub_cfg) 759 param->pub_cfg = *param_ini.pub_cfg; 760 761 if (param_ini.prec_cfg) { 762 param->prec_cfg = *param_ini.prec_cfg; 763 rtwdev->hal.sw_amsdu_max_size = 764 param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; 765 } 766 767 if (param_ini.ch_cfg) 768 param->ch_cfg = param_ini.ch_cfg; 769 770 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 771 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 772 param->mode = param_ini.mode; 773 774 return 0; 775 } 776 777 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 778 { 779 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 780 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 781 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 782 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 783 784 if (ch >= RTW89_DMA_CH_NUM) 785 return -EINVAL; 786 787 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 788 ch_cfg[ch].max > pub_cfg->pub_max) 789 return -EINVAL; 790 if (ch_cfg[ch].grp >= grp_num) 791 return -EINVAL; 792 793 return 0; 794 } 795 796 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 797 { 798 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 799 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 800 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 801 802 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 803 if (rtwdev->chip->chip_id == RTL8852A) 804 return 0; 805 else 806 return -EFAULT; 807 } 808 809 return 0; 810 } 811 812 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 813 { 814 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 815 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 816 817 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 818 return -EFAULT; 819 820 return 0; 821 } 822 823 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 824 { 825 const struct rtw89_chip_info *chip = rtwdev->chip; 826 const struct rtw89_page_regs *regs = chip->page_regs; 827 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 828 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 829 int ret = 0; 830 u32 val = 0; 831 832 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 833 if (ret) 834 return ret; 835 836 ret = hfc_ch_cfg_chk(rtwdev, ch); 837 if (ret) 838 return ret; 839 840 if (ch > RTW89_DMA_B1HI) 841 return -EINVAL; 842 843 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 844 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 845 (cfg[ch].grp ? B_AX_GRP : 0); 846 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 847 848 return 0; 849 } 850 851 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 852 { 853 const struct rtw89_chip_info *chip = rtwdev->chip; 854 const struct rtw89_page_regs *regs = chip->page_regs; 855 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 856 struct rtw89_hfc_ch_info *info = param->ch_info; 857 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 858 u32 val; 859 u32 ret; 860 861 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 862 if (ret) 863 return ret; 864 865 if (ch > RTW89_DMA_H2C) 866 return -EINVAL; 867 868 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 869 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 870 if (ch < RTW89_DMA_H2C) 871 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 872 else 873 info[ch].used = cfg[ch].min - info[ch].aval; 874 875 return 0; 876 } 877 878 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 879 { 880 const struct rtw89_chip_info *chip = rtwdev->chip; 881 const struct rtw89_page_regs *regs = chip->page_regs; 882 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 883 u32 val; 884 int ret; 885 886 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 887 if (ret) 888 return ret; 889 890 ret = hfc_pub_cfg_chk(rtwdev); 891 if (ret) 892 return ret; 893 894 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 895 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 896 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 897 898 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 899 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 900 901 return 0; 902 } 903 904 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 905 { 906 const struct rtw89_chip_info *chip = rtwdev->chip; 907 const struct rtw89_page_regs *regs = chip->page_regs; 908 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 909 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 910 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 911 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 912 u32 val; 913 int ret; 914 915 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 916 if (ret) 917 return ret; 918 919 val = rtw89_read32(rtwdev, regs->pub_page_info1); 920 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 921 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 922 val = rtw89_read32(rtwdev, regs->pub_page_info3); 923 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 924 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 925 info->pub_aval = 926 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 927 B_AX_PUB_AVAL_PG_MASK); 928 info->wp_aval = 929 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 930 B_AX_WP_AVAL_PG_MASK); 931 932 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 933 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 934 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 935 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 936 prec_cfg->ch011_full_cond = 937 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 938 prec_cfg->h2c_full_cond = 939 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 940 prec_cfg->wp_ch07_full_cond = 941 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 942 prec_cfg->wp_ch811_full_cond = 943 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 944 945 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 946 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 947 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 948 949 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 950 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 951 952 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 953 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 954 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 955 956 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 957 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 958 959 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 960 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 961 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 962 963 ret = hfc_pub_info_chk(rtwdev); 964 if (param->en && ret) 965 return ret; 966 967 return 0; 968 } 969 970 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 971 { 972 const struct rtw89_chip_info *chip = rtwdev->chip; 973 const struct rtw89_page_regs *regs = chip->page_regs; 974 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 975 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 976 u32 val; 977 978 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 979 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 980 981 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 982 B_AX_HCI_FC_CH12_FULL_COND_MASK, 983 prec_cfg->h2c_full_cond); 984 } 985 986 static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 987 { 988 const struct rtw89_chip_info *chip = rtwdev->chip; 989 const struct rtw89_page_regs *regs = chip->page_regs; 990 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 991 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 992 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 993 u32 val; 994 995 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 996 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 997 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 998 999 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1000 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1001 1002 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1003 B_AX_PREC_PAGE_WP_CH07_MASK) | 1004 u32_encode_bits(prec_cfg->wp_ch811_prec, 1005 B_AX_PREC_PAGE_WP_CH811_MASK); 1006 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1007 1008 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1009 param->mode, B_AX_HCI_FC_MODE_MASK); 1010 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1011 B_AX_HCI_FC_WD_FULL_COND_MASK); 1012 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1013 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1014 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1015 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1016 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1017 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1018 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1019 } 1020 1021 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1022 { 1023 const struct rtw89_chip_info *chip = rtwdev->chip; 1024 const struct rtw89_page_regs *regs = chip->page_regs; 1025 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1026 u32 val; 1027 1028 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1029 param->en = en; 1030 param->h2c_en = h2c_en; 1031 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1032 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1033 (val & ~B_AX_HCI_FC_CH12_EN); 1034 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1035 } 1036 1037 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1038 { 1039 const struct rtw89_chip_info *chip = rtwdev->chip; 1040 u32 dma_ch_mask = chip->dma_ch_mask; 1041 u8 ch; 1042 u32 ret = 0; 1043 1044 if (reset) 1045 ret = hfc_reset_param(rtwdev); 1046 if (ret) 1047 return ret; 1048 1049 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1050 if (ret) 1051 return ret; 1052 1053 hfc_func_en(rtwdev, false, false); 1054 1055 if (!en && h2c_en) { 1056 hfc_h2c_cfg(rtwdev); 1057 hfc_func_en(rtwdev, en, h2c_en); 1058 return ret; 1059 } 1060 1061 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1062 if (dma_ch_mask & BIT(ch)) 1063 continue; 1064 ret = hfc_ch_ctrl(rtwdev, ch); 1065 if (ret) 1066 return ret; 1067 } 1068 1069 ret = hfc_pub_ctrl(rtwdev); 1070 if (ret) 1071 return ret; 1072 1073 hfc_mix_cfg(rtwdev); 1074 if (en || h2c_en) { 1075 hfc_func_en(rtwdev, en, h2c_en); 1076 udelay(10); 1077 } 1078 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1079 if (dma_ch_mask & BIT(ch)) 1080 continue; 1081 ret = hfc_upd_ch_info(rtwdev, ch); 1082 if (ret) 1083 return ret; 1084 } 1085 ret = hfc_upd_mix_info(rtwdev); 1086 1087 return ret; 1088 } 1089 1090 #define PWR_POLL_CNT 2000 1091 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1092 const struct rtw89_pwr_cfg *cfg) 1093 { 1094 u8 val = 0; 1095 int ret; 1096 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1097 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1098 1099 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1100 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1101 1102 if (!ret) 1103 return 0; 1104 1105 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1106 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1107 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1108 1109 return -EBUSY; 1110 } 1111 1112 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1113 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1114 { 1115 const struct rtw89_pwr_cfg *cur_cfg; 1116 u32 addr; 1117 u8 val; 1118 1119 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1120 if (!(cur_cfg->intf_msk & intf_msk) || 1121 !(cur_cfg->cv_msk & cv_msk)) 1122 continue; 1123 1124 switch (cur_cfg->cmd) { 1125 case PWR_CMD_WRITE: 1126 addr = cur_cfg->addr; 1127 1128 if (cur_cfg->base == PWR_BASE_SDIO) 1129 addr |= SDIO_LOCAL_BASE_ADDR; 1130 1131 val = rtw89_read8(rtwdev, addr); 1132 val &= ~(cur_cfg->msk); 1133 val |= (cur_cfg->val & cur_cfg->msk); 1134 1135 rtw89_write8(rtwdev, addr, val); 1136 break; 1137 case PWR_CMD_POLL: 1138 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1139 return -EBUSY; 1140 break; 1141 case PWR_CMD_DELAY: 1142 if (cur_cfg->val == PWR_DELAY_US) 1143 udelay(cur_cfg->addr); 1144 else 1145 fsleep(cur_cfg->addr * 1000); 1146 break; 1147 default: 1148 return -EINVAL; 1149 } 1150 } 1151 1152 return 0; 1153 } 1154 1155 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1156 const struct rtw89_pwr_cfg * const *cfg_seq) 1157 { 1158 int ret; 1159 1160 for (; *cfg_seq; cfg_seq++) { 1161 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1162 PWR_INTF_MSK_PCIE, *cfg_seq); 1163 if (ret) 1164 return -EBUSY; 1165 } 1166 1167 return 0; 1168 } 1169 1170 static enum rtw89_rpwm_req_pwr_state 1171 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1172 { 1173 enum rtw89_rpwm_req_pwr_state state; 1174 1175 switch (rtwdev->ps_mode) { 1176 case RTW89_PS_MODE_RFOFF: 1177 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1178 break; 1179 case RTW89_PS_MODE_CLK_GATED: 1180 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1181 break; 1182 case RTW89_PS_MODE_PWR_GATED: 1183 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1184 break; 1185 default: 1186 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1187 break; 1188 } 1189 return state; 1190 } 1191 1192 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1193 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1194 bool notify_wake) 1195 { 1196 u16 request; 1197 1198 spin_lock_bh(&rtwdev->rpwm_lock); 1199 1200 request = rtw89_read16(rtwdev, R_AX_RPWM); 1201 request ^= request | PS_RPWM_TOGGLE; 1202 request |= req_pwr_state; 1203 1204 if (notify_wake) { 1205 request |= PS_RPWM_NOTIFY_WAKE; 1206 } else { 1207 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1208 RPWM_SEQ_NUM_MAX; 1209 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1210 rtwdev->mac.rpwm_seq_num); 1211 1212 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1213 request |= PS_RPWM_ACK; 1214 } 1215 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1216 1217 spin_unlock_bh(&rtwdev->rpwm_lock); 1218 } 1219 1220 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1221 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1222 { 1223 bool request_deep_mode; 1224 bool in_deep_mode; 1225 u8 rpwm_req_num; 1226 u8 cpwm_rsp_seq; 1227 u8 cpwm_seq; 1228 u8 cpwm_status; 1229 1230 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1231 request_deep_mode = true; 1232 else 1233 request_deep_mode = false; 1234 1235 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1236 in_deep_mode = true; 1237 else 1238 in_deep_mode = false; 1239 1240 if (request_deep_mode != in_deep_mode) 1241 return -EPERM; 1242 1243 if (request_deep_mode) 1244 return 0; 1245 1246 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1247 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1248 PS_CPWM_RSP_SEQ_NUM); 1249 1250 if (rpwm_req_num != cpwm_rsp_seq) 1251 return -EPERM; 1252 1253 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1254 CPWM_SEQ_NUM_MAX; 1255 1256 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1257 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1258 return -EPERM; 1259 1260 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1261 if (cpwm_status != req_pwr_state) 1262 return -EPERM; 1263 1264 return 0; 1265 } 1266 1267 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1268 { 1269 enum rtw89_rpwm_req_pwr_state state; 1270 unsigned long delay = enter ? 10 : 150; 1271 int ret; 1272 int i; 1273 1274 if (enter) 1275 state = rtw89_mac_get_req_pwr_state(rtwdev); 1276 else 1277 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1278 1279 for (i = 0; i < RPWM_TRY_CNT; i++) { 1280 rtw89_mac_send_rpwm(rtwdev, state, false); 1281 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1282 !ret, delay, 15000, false, 1283 rtwdev, state); 1284 if (!ret) 1285 break; 1286 1287 if (i == RPWM_TRY_CNT - 1) 1288 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1289 enter ? "entering" : "leaving"); 1290 else 1291 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1292 "%d time firmware failed to ack for %s ps mode\n", 1293 i + 1, enter ? "entering" : "leaving"); 1294 } 1295 } 1296 1297 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1298 { 1299 enum rtw89_rpwm_req_pwr_state state; 1300 1301 state = rtw89_mac_get_req_pwr_state(rtwdev); 1302 rtw89_mac_send_rpwm(rtwdev, state, true); 1303 } 1304 1305 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1306 { 1307 #define PWR_ACT 1 1308 const struct rtw89_chip_info *chip = rtwdev->chip; 1309 const struct rtw89_pwr_cfg * const *cfg_seq; 1310 int (*cfg_func)(struct rtw89_dev *rtwdev); 1311 int ret; 1312 u8 val; 1313 1314 if (on) { 1315 cfg_seq = chip->pwr_on_seq; 1316 cfg_func = chip->ops->pwr_on_func; 1317 } else { 1318 cfg_seq = chip->pwr_off_seq; 1319 cfg_func = chip->ops->pwr_off_func; 1320 } 1321 1322 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1323 __rtw89_leave_ps_mode(rtwdev); 1324 1325 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1326 if (on && val == PWR_ACT) { 1327 rtw89_err(rtwdev, "MAC has already powered on\n"); 1328 return -EBUSY; 1329 } 1330 1331 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1332 if (ret) 1333 return ret; 1334 1335 if (on) { 1336 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1337 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1338 } else { 1339 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1340 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1341 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1342 rtw89_set_entity_state(rtwdev, false); 1343 } 1344 1345 return 0; 1346 #undef PWR_ACT 1347 } 1348 1349 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1350 { 1351 rtw89_mac_power_switch(rtwdev, false); 1352 } 1353 1354 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1355 { 1356 u32 func_en = 0; 1357 u32 ck_en = 0; 1358 u32 c1pc_en = 0; 1359 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1360 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1361 1362 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1363 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1364 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1365 B_AX_CMAC_CRPRT; 1366 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1367 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1368 B_AX_RMAC_CKEN; 1369 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1370 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1371 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1372 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1373 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1374 1375 if (en) { 1376 if (mac_idx == RTW89_MAC_1) { 1377 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1378 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1379 B_AX_R_SYM_ISO_CMAC12PP); 1380 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1381 B_AX_CMAC1_FEN); 1382 } 1383 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1384 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1385 } else { 1386 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1387 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1388 if (mac_idx == RTW89_MAC_1) { 1389 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1390 B_AX_CMAC1_FEN); 1391 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1392 B_AX_R_SYM_ISO_CMAC12PP); 1393 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1394 } 1395 } 1396 1397 return 0; 1398 } 1399 1400 static int dmac_func_en(struct rtw89_dev *rtwdev) 1401 { 1402 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1403 u32 val32; 1404 1405 if (chip_id == RTL8852C) 1406 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1407 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1408 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1409 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1410 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1411 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1412 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1413 else 1414 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1415 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1416 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1417 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1418 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1419 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1420 B_AX_DMAC_CRPRT); 1421 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1422 1423 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1424 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1425 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1426 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1427 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1428 1429 return 0; 1430 } 1431 1432 static int chip_func_en(struct rtw89_dev *rtwdev) 1433 { 1434 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1435 1436 if (chip_id == RTL8852A || chip_id == RTL8852B) 1437 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1438 B_AX_OCP_L1_MASK); 1439 1440 return 0; 1441 } 1442 1443 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1444 { 1445 int ret; 1446 1447 ret = dmac_func_en(rtwdev); 1448 if (ret) 1449 return ret; 1450 1451 ret = cmac_func_en(rtwdev, 0, true); 1452 if (ret) 1453 return ret; 1454 1455 ret = chip_func_en(rtwdev); 1456 if (ret) 1457 return ret; 1458 1459 return ret; 1460 } 1461 1462 const struct rtw89_mac_size_set rtw89_mac_size = { 1463 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1464 /* PCIE 64 */ 1465 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1466 /* DLFW */ 1467 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1468 /* PCIE 64 */ 1469 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1470 /* DLFW */ 1471 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1472 /* 8852C DLFW */ 1473 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1474 /* 8852C PCIE SCC */ 1475 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1476 /* PCIE */ 1477 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1478 /* DLFW */ 1479 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1480 /* PCIE 64 */ 1481 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1482 /* DLFW */ 1483 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1484 /* 8852C DLFW */ 1485 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1486 /* 8852C PCIE SCC */ 1487 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1488 /* PCIE 64 */ 1489 .wde_qt0 = {3792, 196, 0, 107,}, 1490 /* DLFW */ 1491 .wde_qt4 = {0, 0, 0, 0,}, 1492 /* PCIE 64 */ 1493 .wde_qt6 = {448, 48, 0, 16,}, 1494 /* 8852C DLFW */ 1495 .wde_qt17 = {0, 0, 0, 0,}, 1496 /* 8852C PCIE SCC */ 1497 .wde_qt18 = {3228, 60, 0, 40,}, 1498 /* PCIE SCC */ 1499 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1500 /* PCIE SCC */ 1501 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1502 /* DLFW */ 1503 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1504 /* PCIE 64 */ 1505 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1506 /* DLFW 52C */ 1507 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1508 /* DLFW 52C */ 1509 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1510 /* 8852C PCIE SCC */ 1511 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1512 /* 8852C PCIE SCC */ 1513 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1514 /* PCIE 64 */ 1515 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1516 /* 8852A PCIE WOW */ 1517 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1518 /* 8852B PCIE WOW */ 1519 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1520 /* 8851B PCIE WOW */ 1521 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1522 }; 1523 EXPORT_SYMBOL(rtw89_mac_size); 1524 1525 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1526 enum rtw89_qta_mode mode) 1527 { 1528 struct rtw89_mac_info *mac = &rtwdev->mac; 1529 const struct rtw89_dle_mem *cfg; 1530 1531 cfg = &rtwdev->chip->dle_mem[mode]; 1532 if (!cfg) 1533 return NULL; 1534 1535 if (cfg->mode != mode) { 1536 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1537 return NULL; 1538 } 1539 1540 mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; 1541 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1542 mac->dle_info.qta_mode = mode; 1543 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1544 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1545 1546 return cfg; 1547 } 1548 1549 static bool mac_is_txq_empty(struct rtw89_dev *rtwdev) 1550 { 1551 struct rtw89_mac_dle_dfi_qempty qempty; 1552 u32 qnum, qtmp, val32, msk32; 1553 int i, j, ret; 1554 1555 qnum = rtwdev->chip->wde_qempty_acq_num; 1556 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1557 1558 for (i = 0; i < qnum; i++) { 1559 qempty.grpsel = i; 1560 ret = dle_dfi_qempty(rtwdev, &qempty); 1561 if (ret) { 1562 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1563 return false; 1564 } 1565 qtmp = qempty.qempty; 1566 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1567 val32 = FIELD_GET(QEMP_ACQ_GRP_QSEL_MASK, qtmp); 1568 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1569 return false; 1570 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1571 } 1572 } 1573 1574 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel; 1575 ret = dle_dfi_qempty(rtwdev, &qempty); 1576 if (ret) { 1577 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1578 return false; 1579 } 1580 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1581 if ((qempty.qempty & msk32) != msk32) 1582 return false; 1583 1584 if (rtwdev->dbcc_en) { 1585 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1586 if ((qempty.qempty & msk32) != msk32) 1587 return false; 1588 } 1589 1590 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1591 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1592 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1593 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1594 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1595 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1596 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1597 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1598 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1599 1600 return (val32 & msk32) == msk32; 1601 } 1602 1603 static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1604 const struct rtw89_dle_size *ple) 1605 { 1606 return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1607 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1608 } 1609 1610 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1611 enum rtw89_qta_mode mode) 1612 { 1613 u32 size = rtwdev->chip->fifo_size; 1614 1615 if (mode == RTW89_QTA_SCC) 1616 size -= rtwdev->chip->dle_scc_rsvd_size; 1617 1618 return size; 1619 } 1620 1621 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1622 { 1623 if (enable) 1624 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1625 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1626 else 1627 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1628 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1629 } 1630 1631 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1632 { 1633 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1634 1635 if (enable) { 1636 if (rtwdev->chip->chip_id == RTL8851B) 1637 val |= B_AX_AXIDMA_CLK_EN; 1638 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1639 } else { 1640 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1641 } 1642 } 1643 1644 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1645 { 1646 const struct rtw89_dle_size *size_cfg; 1647 u32 val; 1648 u8 bound = 0; 1649 1650 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1651 size_cfg = cfg->wde_size; 1652 1653 switch (size_cfg->pge_size) { 1654 default: 1655 case RTW89_WDE_PG_64: 1656 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1657 B_AX_WDE_PAGE_SEL_MASK); 1658 break; 1659 case RTW89_WDE_PG_128: 1660 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1661 B_AX_WDE_PAGE_SEL_MASK); 1662 break; 1663 case RTW89_WDE_PG_256: 1664 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1665 return -EINVAL; 1666 } 1667 1668 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1669 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1670 B_AX_WDE_FREE_PAGE_NUM_MASK); 1671 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1672 1673 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1674 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1675 * size_cfg->pge_size / DLE_BOUND_UNIT; 1676 size_cfg = cfg->ple_size; 1677 1678 switch (size_cfg->pge_size) { 1679 default: 1680 case RTW89_PLE_PG_64: 1681 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1682 return -EINVAL; 1683 case RTW89_PLE_PG_128: 1684 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1685 B_AX_PLE_PAGE_SEL_MASK); 1686 break; 1687 case RTW89_PLE_PG_256: 1688 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1689 B_AX_PLE_PAGE_SEL_MASK); 1690 break; 1691 } 1692 1693 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1694 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1695 B_AX_PLE_FREE_PAGE_NUM_MASK); 1696 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1697 1698 return 0; 1699 } 1700 1701 #define INVALID_QT_WCPU U16_MAX 1702 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1703 do { \ 1704 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1705 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1706 rtw89_write32(rtwdev, \ 1707 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1708 val); \ 1709 } while (0) 1710 #define SET_QUOTA(_x, _module, _idx) \ 1711 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1712 1713 static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1714 const struct rtw89_wde_quota *min_cfg, 1715 const struct rtw89_wde_quota *max_cfg, 1716 u16 ext_wde_min_qt_wcpu) 1717 { 1718 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1719 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1720 u32 val; 1721 1722 SET_QUOTA(hif, WDE, 0); 1723 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1724 SET_QUOTA(pkt_in, WDE, 3); 1725 SET_QUOTA(cpu_io, WDE, 4); 1726 } 1727 1728 static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1729 const struct rtw89_ple_quota *min_cfg, 1730 const struct rtw89_ple_quota *max_cfg) 1731 { 1732 u32 val; 1733 1734 SET_QUOTA(cma0_tx, PLE, 0); 1735 SET_QUOTA(cma1_tx, PLE, 1); 1736 SET_QUOTA(c2h, PLE, 2); 1737 SET_QUOTA(h2c, PLE, 3); 1738 SET_QUOTA(wcpu, PLE, 4); 1739 SET_QUOTA(mpdu_proc, PLE, 5); 1740 SET_QUOTA(cma0_dma, PLE, 6); 1741 SET_QUOTA(cma1_dma, PLE, 7); 1742 SET_QUOTA(bb_rpt, PLE, 8); 1743 SET_QUOTA(wd_rel, PLE, 9); 1744 SET_QUOTA(cpu_io, PLE, 10); 1745 if (rtwdev->chip->chip_id == RTL8852C) 1746 SET_QUOTA(tx_rpt, PLE, 11); 1747 } 1748 1749 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 1750 { 1751 const struct rtw89_ple_quota *min_cfg, *max_cfg; 1752 const struct rtw89_dle_mem *cfg; 1753 u32 val; 1754 1755 if (rtwdev->chip->chip_id == RTL8852C) 1756 return 0; 1757 1758 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 1759 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 1760 return -EINVAL; 1761 } 1762 1763 if (wow) 1764 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 1765 else 1766 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 1767 if (!cfg) { 1768 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1769 return -EINVAL; 1770 } 1771 1772 min_cfg = cfg->ple_min_qt; 1773 max_cfg = cfg->ple_max_qt; 1774 SET_QUOTA(cma0_dma, PLE, 6); 1775 SET_QUOTA(cma1_dma, PLE, 7); 1776 1777 return 0; 1778 } 1779 #undef SET_QUOTA 1780 1781 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 1782 { 1783 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 1784 1785 if (enable) 1786 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1787 else 1788 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1789 } 1790 1791 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1792 const struct rtw89_dle_mem *cfg, 1793 u16 ext_wde_min_qt_wcpu) 1794 { 1795 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1796 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1797 } 1798 1799 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1800 enum rtw89_qta_mode ext_mode) 1801 { 1802 const struct rtw89_dle_mem *cfg, *ext_cfg; 1803 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1804 int ret = 0; 1805 u32 ini; 1806 1807 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1808 if (ret) 1809 return ret; 1810 1811 cfg = get_dle_mem_cfg(rtwdev, mode); 1812 if (!cfg) { 1813 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1814 ret = -EINVAL; 1815 goto error; 1816 } 1817 1818 if (mode == RTW89_QTA_DLFW) { 1819 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1820 if (!ext_cfg) { 1821 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1822 ext_mode); 1823 ret = -EINVAL; 1824 goto error; 1825 } 1826 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1827 } 1828 1829 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 1830 dle_expected_used_size(rtwdev, mode)) { 1831 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1832 ret = -EINVAL; 1833 goto error; 1834 } 1835 1836 dle_func_en(rtwdev, false); 1837 dle_clk_en(rtwdev, true); 1838 1839 ret = dle_mix_cfg(rtwdev, cfg); 1840 if (ret) { 1841 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1842 goto error; 1843 } 1844 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1845 1846 dle_func_en(rtwdev, true); 1847 1848 ret = read_poll_timeout(rtw89_read32, ini, 1849 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1850 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1851 if (ret) { 1852 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1853 return ret; 1854 } 1855 1856 ret = read_poll_timeout(rtw89_read32, ini, 1857 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1858 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1859 if (ret) { 1860 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1861 return ret; 1862 } 1863 1864 return 0; 1865 error: 1866 dle_func_en(rtwdev, false); 1867 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1868 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1869 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1870 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1871 1872 return ret; 1873 } 1874 1875 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1876 enum rtw89_qta_mode mode) 1877 { 1878 u32 reg, max_preld_size, min_rsvd_size; 1879 1880 max_preld_size = (mac_idx == RTW89_MAC_0 ? 1881 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1882 reg = mac_idx == RTW89_MAC_0 ? 1883 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1884 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1885 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1886 1887 min_rsvd_size = PRELD_AMSDU_SIZE; 1888 reg = mac_idx == RTW89_MAC_0 ? 1889 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1890 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1891 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1892 1893 return 0; 1894 } 1895 1896 static bool is_qta_poh(struct rtw89_dev *rtwdev) 1897 { 1898 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1899 } 1900 1901 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1902 enum rtw89_qta_mode mode) 1903 { 1904 const struct rtw89_chip_info *chip = rtwdev->chip; 1905 1906 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1907 chip->chip_id == RTL8851B || !is_qta_poh(rtwdev)) 1908 return 0; 1909 1910 return preload_init_set(rtwdev, mac_idx, mode); 1911 } 1912 1913 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1914 { 1915 u32 msk32; 1916 u32 val32; 1917 1918 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1919 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1920 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1921 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1922 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1923 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1924 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1925 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1926 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1927 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1928 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1929 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1930 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1931 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1932 1933 if ((val32 & msk32) == msk32) 1934 return true; 1935 1936 return false; 1937 } 1938 1939 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 1940 { 1941 const struct rtw89_chip_info *chip = rtwdev->chip; 1942 1943 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1944 chip->chip_id == RTL8851B) 1945 return; 1946 1947 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 1948 SS2F_PATH_WLCPU); 1949 } 1950 1951 static int sta_sch_init(struct rtw89_dev *rtwdev) 1952 { 1953 u32 p_val; 1954 u8 val; 1955 int ret; 1956 1957 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1958 if (ret) 1959 return ret; 1960 1961 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1962 val |= B_AX_SS_EN; 1963 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1964 1965 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1966 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1967 if (ret) { 1968 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1969 return ret; 1970 } 1971 1972 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 1973 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 1974 1975 _patch_ss2f_path(rtwdev); 1976 1977 return 0; 1978 } 1979 1980 static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1981 { 1982 int ret; 1983 1984 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1985 if (ret) 1986 return ret; 1987 1988 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1989 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1990 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1991 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1992 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1993 1994 return 0; 1995 } 1996 1997 static int sec_eng_init(struct rtw89_dev *rtwdev) 1998 { 1999 const struct rtw89_chip_info *chip = rtwdev->chip; 2000 u32 val = 0; 2001 int ret; 2002 2003 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2004 if (ret) 2005 return ret; 2006 2007 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2008 /* init clock */ 2009 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2010 /* init TX encryption */ 2011 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2012 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2013 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2014 chip->chip_id == RTL8851B) 2015 val &= ~B_AX_TX_PARTIAL_MODE; 2016 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2017 2018 /* init MIC ICV append */ 2019 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2020 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2021 2022 /* option init */ 2023 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2024 2025 if (chip->chip_id == RTL8852C) 2026 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2027 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2028 2029 return 0; 2030 } 2031 2032 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2033 { 2034 int ret; 2035 2036 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2037 if (ret) { 2038 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2039 return ret; 2040 } 2041 2042 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2043 if (ret) { 2044 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2045 return ret; 2046 } 2047 2048 ret = hfc_init(rtwdev, true, true, true); 2049 if (ret) { 2050 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2051 return ret; 2052 } 2053 2054 ret = sta_sch_init(rtwdev); 2055 if (ret) { 2056 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2057 return ret; 2058 } 2059 2060 ret = mpdu_proc_init(rtwdev); 2061 if (ret) { 2062 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2063 return ret; 2064 } 2065 2066 ret = sec_eng_init(rtwdev); 2067 if (ret) { 2068 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2069 return ret; 2070 } 2071 2072 return ret; 2073 } 2074 2075 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2076 { 2077 u32 val, reg; 2078 u16 p_val; 2079 int ret; 2080 2081 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2082 if (ret) 2083 return ret; 2084 2085 reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); 2086 2087 val = rtw89_read32(rtwdev, reg); 2088 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2089 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2090 rtw89_write32(rtwdev, reg, val); 2091 2092 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2093 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2094 if (ret) { 2095 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2096 return ret; 2097 } 2098 2099 return 0; 2100 } 2101 2102 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2103 { 2104 u32 ret; 2105 u32 reg; 2106 u32 val; 2107 2108 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2109 if (ret) 2110 return ret; 2111 2112 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx); 2113 if (rtwdev->chip->chip_id == RTL8852C) 2114 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2115 SIFS_MACTXEN_T1_V1); 2116 else 2117 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2118 SIFS_MACTXEN_T1); 2119 2120 if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) { 2121 reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx); 2122 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2123 } 2124 2125 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx); 2126 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2127 2128 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); 2129 if (rtwdev->chip->chip_id == RTL8852C) { 2130 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2131 B_AX_TX_PARTIAL_MODE); 2132 if (!val) 2133 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2134 SCH_PREBKF_24US); 2135 } else { 2136 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2137 SCH_PREBKF_24US); 2138 } 2139 2140 return 0; 2141 } 2142 2143 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 2144 enum rtw89_machdr_frame_type type, 2145 enum rtw89_mac_fwd_target fwd_target, 2146 u8 mac_idx) 2147 { 2148 u32 reg; 2149 u32 val; 2150 2151 switch (fwd_target) { 2152 case RTW89_FWD_DONT_CARE: 2153 val = RX_FLTR_FRAME_DROP; 2154 break; 2155 case RTW89_FWD_TO_HOST: 2156 val = RX_FLTR_FRAME_TO_HOST; 2157 break; 2158 case RTW89_FWD_TO_WLAN_CPU: 2159 val = RX_FLTR_FRAME_TO_WLCPU; 2160 break; 2161 default: 2162 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2163 return -EINVAL; 2164 } 2165 2166 switch (type) { 2167 case RTW89_MGNT: 2168 reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); 2169 break; 2170 case RTW89_CTRL: 2171 reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); 2172 break; 2173 case RTW89_DATA: 2174 reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); 2175 break; 2176 default: 2177 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2178 return -EINVAL; 2179 } 2180 rtw89_write32(rtwdev, reg, val); 2181 2182 return 0; 2183 } 2184 2185 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2186 { 2187 int ret, i; 2188 u32 mac_ftlr, plcp_ftlr; 2189 2190 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2191 if (ret) 2192 return ret; 2193 2194 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2195 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 2196 mac_idx); 2197 if (ret) 2198 return ret; 2199 } 2200 mac_ftlr = rtwdev->hal.rx_fltr; 2201 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2202 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2203 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2204 B_AX_HE_SIGB_CRC_CHK; 2205 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), 2206 mac_ftlr); 2207 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), 2208 plcp_ftlr); 2209 2210 return 0; 2211 } 2212 2213 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2214 { 2215 u32 reg, val32; 2216 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2217 2218 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2219 B_AX_RSP_CHK_BASIC_NAV; 2220 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2221 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2222 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2223 2224 switch (rtwdev->chip->chip_id) { 2225 case RTL8852A: 2226 case RTL8852B: 2227 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2228 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2229 rtw89_write32(rtwdev, reg, val32); 2230 2231 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2232 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2233 rtw89_write32(rtwdev, reg, val32); 2234 break; 2235 default: 2236 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2237 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2238 rtw89_write32(rtwdev, reg, val32); 2239 2240 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2241 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2242 rtw89_write32(rtwdev, reg, val32); 2243 break; 2244 } 2245 } 2246 2247 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2248 { 2249 u32 val, reg; 2250 int ret; 2251 2252 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2253 if (ret) 2254 return ret; 2255 2256 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); 2257 val = rtw89_read32(rtwdev, reg); 2258 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2259 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2260 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2261 B_AX_CTN_CHK_INTRA_NAV | 2262 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2263 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2264 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2265 B_AX_CTN_CHK_CCA_P20); 2266 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2267 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2268 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2269 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2270 B_AX_SIFS_CHK_EDCCA); 2271 2272 rtw89_write32(rtwdev, reg, val); 2273 2274 _patch_dis_resp_chk(rtwdev, mac_idx); 2275 2276 return 0; 2277 } 2278 2279 static int nav_ctrl_init(struct rtw89_dev *rtwdev) 2280 { 2281 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2282 B_AX_WMAC_TF_UP_NAV_EN | 2283 B_AX_WMAC_NAV_UPPER_EN); 2284 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2285 2286 return 0; 2287 } 2288 2289 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2290 { 2291 u32 reg; 2292 int ret; 2293 2294 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2295 if (ret) 2296 return ret; 2297 reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); 2298 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2299 2300 return 0; 2301 } 2302 2303 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2304 { 2305 u32 reg; 2306 int ret; 2307 2308 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2309 if (ret) 2310 return ret; 2311 2312 reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); 2313 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2314 2315 reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx); 2316 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2317 2318 reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx); 2319 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2320 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2321 2322 return 0; 2323 } 2324 2325 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2326 { 2327 const struct rtw89_chip_info *chip = rtwdev->chip; 2328 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2329 u32 reg, val, sifs; 2330 int ret; 2331 2332 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2333 if (ret) 2334 return ret; 2335 2336 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2337 val = rtw89_read32(rtwdev, reg); 2338 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2339 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2340 2341 switch (rtwdev->chip->chip_id) { 2342 case RTL8852A: 2343 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2344 break; 2345 case RTL8852B: 2346 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2347 break; 2348 default: 2349 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2350 break; 2351 } 2352 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2353 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2354 rtw89_write32(rtwdev, reg, val); 2355 2356 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); 2357 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2358 2359 reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx); 2360 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2361 reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx); 2362 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2363 2364 return 0; 2365 } 2366 2367 static void rst_bacam(struct rtw89_dev *rtwdev) 2368 { 2369 u32 val32; 2370 int ret; 2371 2372 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2373 S_AX_BACAM_RST_ALL); 2374 2375 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2376 1, 1000, false, 2377 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2378 if (ret) 2379 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2380 } 2381 2382 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2383 { 2384 #define TRXCFG_RMAC_CCA_TO 32 2385 #define TRXCFG_RMAC_DATA_TO 15 2386 #define RX_MAX_LEN_UNIT 512 2387 #define PLD_RLS_MAX_PG 127 2388 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2389 int ret; 2390 u32 reg, rx_max_len, rx_qta; 2391 u16 val; 2392 2393 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2394 if (ret) 2395 return ret; 2396 2397 if (mac_idx == RTW89_MAC_0) 2398 rst_bacam(rtwdev); 2399 2400 reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); 2401 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2402 2403 reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); 2404 val = rtw89_read16(rtwdev, reg); 2405 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2406 B_AX_RX_DLK_DATA_TIME_MASK); 2407 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2408 B_AX_RX_DLK_CCA_TIME_MASK); 2409 rtw89_write16(rtwdev, reg, val); 2410 2411 reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); 2412 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2413 2414 reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); 2415 if (mac_idx == RTW89_MAC_0) 2416 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2417 else 2418 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2419 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2420 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2421 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2422 rx_max_len /= RX_MAX_LEN_UNIT; 2423 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2424 2425 if (rtwdev->chip->chip_id == RTL8852A && 2426 rtwdev->hal.cv == CHIP_CBV) { 2427 rtw89_write16_mask(rtwdev, 2428 rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), 2429 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2430 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), 2431 BIT(12)); 2432 } 2433 2434 reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); 2435 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2436 2437 return ret; 2438 } 2439 2440 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2441 { 2442 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2443 u32 val, reg; 2444 int ret; 2445 2446 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2447 if (ret) 2448 return ret; 2449 2450 reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2451 val = rtw89_read32(rtwdev, reg); 2452 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2453 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2454 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2455 rtw89_write32(rtwdev, reg, val); 2456 2457 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2458 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx); 2459 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2460 } 2461 2462 return 0; 2463 } 2464 2465 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2466 { 2467 const struct rtw89_dle_mem *cfg; 2468 2469 cfg = get_dle_mem_cfg(rtwdev, mode); 2470 if (!cfg) { 2471 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2472 return false; 2473 } 2474 2475 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2476 } 2477 2478 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2479 { 2480 u32 val, reg; 2481 int ret; 2482 2483 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2484 if (ret) 2485 return ret; 2486 2487 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2488 reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2489 val = rtw89_read32(rtwdev, reg); 2490 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2491 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2492 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2493 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2494 val |= B_AX_HW_CTS2SELF_EN; 2495 rtw89_write32(rtwdev, reg, val); 2496 2497 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); 2498 val = rtw89_read32(rtwdev, reg); 2499 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2500 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2501 rtw89_write32(rtwdev, reg, val); 2502 } 2503 2504 if (mac_idx == RTW89_MAC_0) { 2505 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2506 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2507 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2508 B_AX_PTCL_TRIGGER_SS_EN_0 | 2509 B_AX_PTCL_TRIGGER_SS_EN_1 | 2510 B_AX_PTCL_TRIGGER_SS_EN_UL); 2511 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2512 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2513 } else if (mac_idx == RTW89_MAC_1) { 2514 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2515 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2516 } 2517 2518 return 0; 2519 } 2520 2521 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2522 { 2523 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2524 u32 reg; 2525 int ret; 2526 2527 if (chip_id != RTL8852A && chip_id != RTL8852B) 2528 return 0; 2529 2530 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2531 if (ret) 2532 return ret; 2533 2534 reg = rtw89_mac_reg_by_idx(R_AX_RXDMA_CTRL_0, mac_idx); 2535 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2536 2537 return 0; 2538 } 2539 2540 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2541 { 2542 int ret; 2543 2544 ret = scheduler_init(rtwdev, mac_idx); 2545 if (ret) { 2546 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2547 return ret; 2548 } 2549 2550 ret = addr_cam_init(rtwdev, mac_idx); 2551 if (ret) { 2552 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2553 ret); 2554 return ret; 2555 } 2556 2557 ret = rx_fltr_init(rtwdev, mac_idx); 2558 if (ret) { 2559 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2560 ret); 2561 return ret; 2562 } 2563 2564 ret = cca_ctrl_init(rtwdev, mac_idx); 2565 if (ret) { 2566 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2567 ret); 2568 return ret; 2569 } 2570 2571 ret = nav_ctrl_init(rtwdev); 2572 if (ret) { 2573 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2574 ret); 2575 return ret; 2576 } 2577 2578 ret = spatial_reuse_init(rtwdev, mac_idx); 2579 if (ret) { 2580 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2581 mac_idx, ret); 2582 return ret; 2583 } 2584 2585 ret = tmac_init(rtwdev, mac_idx); 2586 if (ret) { 2587 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2588 return ret; 2589 } 2590 2591 ret = trxptcl_init(rtwdev, mac_idx); 2592 if (ret) { 2593 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2594 return ret; 2595 } 2596 2597 ret = rmac_init(rtwdev, mac_idx); 2598 if (ret) { 2599 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2600 return ret; 2601 } 2602 2603 ret = cmac_com_init(rtwdev, mac_idx); 2604 if (ret) { 2605 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2606 return ret; 2607 } 2608 2609 ret = ptcl_init(rtwdev, mac_idx); 2610 if (ret) { 2611 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2612 return ret; 2613 } 2614 2615 ret = cmac_dma_init(rtwdev, mac_idx); 2616 if (ret) { 2617 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2618 return ret; 2619 } 2620 2621 return ret; 2622 } 2623 2624 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2625 struct rtw89_mac_c2h_info *c2h_info) 2626 { 2627 struct rtw89_mac_h2c_info h2c_info = {0}; 2628 u32 ret; 2629 2630 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2631 h2c_info.content_len = 0; 2632 2633 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2634 if (ret) 2635 return ret; 2636 2637 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2638 return -EINVAL; 2639 2640 return 0; 2641 } 2642 2643 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2644 { 2645 struct rtw89_efuse *efuse = &rtwdev->efuse; 2646 struct rtw89_hal *hal = &rtwdev->hal; 2647 const struct rtw89_chip_info *chip = rtwdev->chip; 2648 struct rtw89_mac_c2h_info c2h_info = {0}; 2649 u8 tx_nss; 2650 u8 rx_nss; 2651 u8 tx_ant; 2652 u8 rx_ant; 2653 u32 ret; 2654 2655 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2656 if (ret) 2657 return ret; 2658 2659 tx_nss = RTW89_GET_C2H_PHYCAP_TX_NSS(c2h_info.c2hreg); 2660 rx_nss = RTW89_GET_C2H_PHYCAP_RX_NSS(c2h_info.c2hreg); 2661 tx_ant = RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(c2h_info.c2hreg); 2662 rx_ant = RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(c2h_info.c2hreg); 2663 2664 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2665 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2666 2667 if (tx_ant == 1) 2668 hal->antenna_tx = RF_B; 2669 if (rx_ant == 1) 2670 hal->antenna_rx = RF_B; 2671 2672 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2673 hal->antenna_tx = RF_B; 2674 hal->tx_path_diversity = true; 2675 } 2676 2677 if (chip->rf_path_num == 1) { 2678 hal->antenna_tx = RF_A; 2679 hal->antenna_rx = RF_A; 2680 if ((efuse->rfe_type % 3) == 2) 2681 hal->ant_diversity = true; 2682 } 2683 2684 rtw89_debug(rtwdev, RTW89_DBG_FW, 2685 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2686 hal->tx_nss, tx_nss, chip->tx_nss, 2687 hal->rx_nss, rx_nss, chip->rx_nss); 2688 rtw89_debug(rtwdev, RTW89_DBG_FW, 2689 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2690 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2691 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2692 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2693 2694 return 0; 2695 } 2696 2697 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2698 u16 tx_en_u16, u16 mask_u16) 2699 { 2700 u32 ret; 2701 struct rtw89_mac_c2h_info c2h_info = {0}; 2702 struct rtw89_mac_h2c_info h2c_info = {0}; 2703 struct rtw89_h2creg_sch_tx_en *h2creg = 2704 (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; 2705 2706 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2707 h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; 2708 h2creg->tx_en = tx_en_u16; 2709 h2creg->mask = mask_u16; 2710 h2creg->band = band; 2711 2712 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2713 if (ret) 2714 return ret; 2715 2716 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2717 return -EINVAL; 2718 2719 return 0; 2720 } 2721 2722 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2723 u16 tx_en, u16 tx_en_mask) 2724 { 2725 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); 2726 u16 val; 2727 int ret; 2728 2729 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2730 if (ret) 2731 return ret; 2732 2733 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2734 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2735 tx_en, tx_en_mask); 2736 2737 val = rtw89_read16(rtwdev, reg); 2738 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2739 rtw89_write16(rtwdev, reg, val); 2740 2741 return 0; 2742 } 2743 2744 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2745 u32 tx_en, u32 tx_en_mask) 2746 { 2747 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx); 2748 u32 val; 2749 int ret; 2750 2751 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2752 if (ret) 2753 return ret; 2754 2755 val = rtw89_read32(rtwdev, reg); 2756 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2757 rtw89_write32(rtwdev, reg, val); 2758 2759 return 0; 2760 } 2761 2762 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2763 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2764 { 2765 int ret; 2766 2767 *tx_en = rtw89_read16(rtwdev, 2768 rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); 2769 2770 switch (sel) { 2771 case RTW89_SCH_TX_SEL_ALL: 2772 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2773 B_AX_CTN_TXEN_ALL_MASK); 2774 if (ret) 2775 return ret; 2776 break; 2777 case RTW89_SCH_TX_SEL_HIQ: 2778 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2779 0, B_AX_CTN_TXEN_HGQ); 2780 if (ret) 2781 return ret; 2782 break; 2783 case RTW89_SCH_TX_SEL_MG0: 2784 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2785 0, B_AX_CTN_TXEN_MGQ); 2786 if (ret) 2787 return ret; 2788 break; 2789 case RTW89_SCH_TX_SEL_MACID: 2790 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2791 B_AX_CTN_TXEN_ALL_MASK); 2792 if (ret) 2793 return ret; 2794 break; 2795 default: 2796 return 0; 2797 } 2798 2799 return 0; 2800 } 2801 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2802 2803 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2804 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2805 { 2806 int ret; 2807 2808 *tx_en = rtw89_read32(rtwdev, 2809 rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx)); 2810 2811 switch (sel) { 2812 case RTW89_SCH_TX_SEL_ALL: 2813 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2814 B_AX_CTN_TXEN_ALL_MASK_V1); 2815 if (ret) 2816 return ret; 2817 break; 2818 case RTW89_SCH_TX_SEL_HIQ: 2819 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2820 0, B_AX_CTN_TXEN_HGQ); 2821 if (ret) 2822 return ret; 2823 break; 2824 case RTW89_SCH_TX_SEL_MG0: 2825 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2826 0, B_AX_CTN_TXEN_MGQ); 2827 if (ret) 2828 return ret; 2829 break; 2830 case RTW89_SCH_TX_SEL_MACID: 2831 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2832 B_AX_CTN_TXEN_ALL_MASK_V1); 2833 if (ret) 2834 return ret; 2835 break; 2836 default: 2837 return 0; 2838 } 2839 2840 return 0; 2841 } 2842 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2843 2844 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2845 { 2846 int ret; 2847 2848 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2849 if (ret) 2850 return ret; 2851 2852 return 0; 2853 } 2854 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2855 2856 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2857 { 2858 int ret; 2859 2860 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2861 B_AX_CTN_TXEN_ALL_MASK_V1); 2862 if (ret) 2863 return ret; 2864 2865 return 0; 2866 } 2867 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2868 2869 int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 2870 { 2871 u32 val, reg; 2872 int ret; 2873 2874 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2875 val = buf_len; 2876 val |= B_AX_WD_BUF_REQ_EXEC; 2877 rtw89_write32(rtwdev, reg, val); 2878 2879 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2880 2881 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2882 1, 2000, false, rtwdev, reg); 2883 if (ret) 2884 return ret; 2885 2886 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2887 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 2888 return -ENOENT; 2889 2890 return 0; 2891 } 2892 2893 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2894 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 2895 { 2896 u32 val, cmd_type, reg; 2897 int ret; 2898 2899 cmd_type = ctrl_para->cmd_type; 2900 2901 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2902 val = 0; 2903 val = u32_replace_bits(val, ctrl_para->start_pktid, 2904 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2905 val = u32_replace_bits(val, ctrl_para->end_pktid, 2906 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2907 rtw89_write32(rtwdev, reg, val); 2908 2909 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2910 val = 0; 2911 val = u32_replace_bits(val, ctrl_para->src_pid, 2912 B_AX_CPUQ_OP_SRC_PID_MASK); 2913 val = u32_replace_bits(val, ctrl_para->src_qid, 2914 B_AX_CPUQ_OP_SRC_QID_MASK); 2915 val = u32_replace_bits(val, ctrl_para->dst_pid, 2916 B_AX_CPUQ_OP_DST_PID_MASK); 2917 val = u32_replace_bits(val, ctrl_para->dst_qid, 2918 B_AX_CPUQ_OP_DST_QID_MASK); 2919 rtw89_write32(rtwdev, reg, val); 2920 2921 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2922 val = 0; 2923 val = u32_replace_bits(val, cmd_type, 2924 B_AX_CPUQ_OP_CMD_TYPE_MASK); 2925 val = u32_replace_bits(val, ctrl_para->macid, 2926 B_AX_CPUQ_OP_MACID_MASK); 2927 val = u32_replace_bits(val, ctrl_para->pkt_num, 2928 B_AX_CPUQ_OP_PKTNUM_MASK); 2929 val |= B_AX_WD_CPUQ_OP_EXEC; 2930 rtw89_write32(rtwdev, reg, val); 2931 2932 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2933 2934 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2935 1, 2000, false, rtwdev, reg); 2936 if (ret) 2937 return ret; 2938 2939 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2940 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2941 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2942 2943 return 0; 2944 } 2945 2946 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2947 { 2948 const struct rtw89_dle_mem *cfg; 2949 struct rtw89_cpuio_ctrl ctrl_para = {0}; 2950 u16 pkt_id; 2951 int ret; 2952 2953 cfg = get_dle_mem_cfg(rtwdev, mode); 2954 if (!cfg) { 2955 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2956 return -EINVAL; 2957 } 2958 2959 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 2960 dle_expected_used_size(rtwdev, mode)) { 2961 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2962 return -EINVAL; 2963 } 2964 2965 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2966 2967 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id); 2968 if (ret) { 2969 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2970 return ret; 2971 } 2972 2973 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2974 ctrl_para.start_pktid = pkt_id; 2975 ctrl_para.end_pktid = pkt_id; 2976 ctrl_para.pkt_num = 0; 2977 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2978 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2979 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2980 if (ret) { 2981 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2982 return -EFAULT; 2983 } 2984 2985 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, false, &pkt_id); 2986 if (ret) { 2987 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2988 return ret; 2989 } 2990 2991 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2992 ctrl_para.start_pktid = pkt_id; 2993 ctrl_para.end_pktid = pkt_id; 2994 ctrl_para.pkt_num = 0; 2995 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 2996 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 2997 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 2998 if (ret) { 2999 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3000 return -EFAULT; 3001 } 3002 3003 return 0; 3004 } 3005 3006 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3007 { 3008 int ret; 3009 u32 reg; 3010 u8 val; 3011 3012 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3013 if (ret) 3014 return ret; 3015 3016 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); 3017 3018 ret = read_poll_timeout(rtw89_read8, val, 3019 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3020 SW_CVR_DUR_US, 3021 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3022 false, rtwdev, reg); 3023 if (ret) 3024 return ret; 3025 3026 return 0; 3027 } 3028 3029 static int band1_enable(struct rtw89_dev *rtwdev) 3030 { 3031 int ret, i; 3032 u32 sleep_bak[4] = {0}; 3033 u32 pause_bak[4] = {0}; 3034 u32 tx_en; 3035 3036 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3037 if (ret) { 3038 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3039 return ret; 3040 } 3041 3042 for (i = 0; i < 4; i++) { 3043 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3044 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3045 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3046 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3047 } 3048 3049 ret = band_idle_ck_b(rtwdev, 0); 3050 if (ret) { 3051 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3052 return ret; 3053 } 3054 3055 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 3056 if (ret) { 3057 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3058 return ret; 3059 } 3060 3061 for (i = 0; i < 4; i++) { 3062 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3063 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3064 } 3065 3066 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3067 if (ret) { 3068 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3069 return ret; 3070 } 3071 3072 ret = cmac_func_en(rtwdev, 1, true); 3073 if (ret) { 3074 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3075 return ret; 3076 } 3077 3078 ret = cmac_init(rtwdev, 1); 3079 if (ret) { 3080 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3081 return ret; 3082 } 3083 3084 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3085 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3086 3087 return 0; 3088 } 3089 3090 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3091 { 3092 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3093 3094 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3095 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3096 } 3097 3098 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3099 { 3100 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3101 3102 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3103 } 3104 3105 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3106 { 3107 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3108 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3109 3110 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3111 B_AX_TX_GET_ERRPKTID_INT_EN | 3112 B_AX_TX_NXT_ERRPKTID_INT_EN | 3113 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3114 B_AX_TX_OFFSET_ERR_INT_EN | 3115 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3116 if (chip_id == RTL8852C) 3117 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3118 B_AX_TX_ETH_TYPE_ERR_EN | 3119 B_AX_TX_LLC_PRE_ERR_EN | 3120 B_AX_TX_NW_TYPE_ERR_EN | 3121 B_AX_TX_KSRCH_ERR_EN); 3122 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3123 imr->mpdu_tx_imr_set); 3124 3125 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3126 B_AX_GETPKTID_ERR_INT_EN | 3127 B_AX_MHDRLEN_ERR_INT_EN | 3128 B_AX_RPT_ERR_INT_EN); 3129 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3130 imr->mpdu_rx_imr_set); 3131 } 3132 3133 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3134 { 3135 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3136 3137 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3138 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3139 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3140 B_AX_PLE_B_PKTID_ERR_INT_EN); 3141 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3142 imr->sta_sch_imr_set); 3143 } 3144 3145 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3146 { 3147 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3148 3149 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3150 imr->txpktctl_imr_b0_clr); 3151 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3152 imr->txpktctl_imr_b0_set); 3153 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3154 imr->txpktctl_imr_b1_clr); 3155 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3156 imr->txpktctl_imr_b1_set); 3157 } 3158 3159 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3160 { 3161 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3162 3163 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3164 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3165 } 3166 3167 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3168 { 3169 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3170 3171 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3172 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3173 } 3174 3175 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3176 { 3177 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3178 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3179 } 3180 3181 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3182 { 3183 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3184 3185 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3186 imr->host_disp_imr_clr); 3187 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3188 imr->host_disp_imr_set); 3189 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3190 imr->cpu_disp_imr_clr); 3191 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3192 imr->cpu_disp_imr_set); 3193 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3194 imr->other_disp_imr_clr); 3195 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3196 imr->other_disp_imr_set); 3197 } 3198 3199 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3200 { 3201 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3202 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3203 } 3204 3205 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3206 { 3207 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3208 3209 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3210 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3211 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3212 B_AX_BBRPT_CHINFO_IMR_CLR); 3213 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3214 imr->bbrpt_err_imr_set); 3215 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3216 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3217 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3218 } 3219 3220 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3221 { 3222 u32 reg; 3223 3224 reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); 3225 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3226 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3227 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3228 } 3229 3230 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3231 { 3232 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3233 u32 reg; 3234 3235 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); 3236 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3237 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3238 } 3239 3240 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3241 { 3242 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3243 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3244 u32 reg; 3245 3246 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx); 3247 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3248 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3249 3250 if (chip_id == RTL8852C) { 3251 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx); 3252 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3253 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3254 } 3255 } 3256 3257 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3258 { 3259 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3260 u32 reg; 3261 3262 reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx); 3263 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3264 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3265 } 3266 3267 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3268 { 3269 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3270 u32 reg; 3271 3272 reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx); 3273 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3274 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3275 } 3276 3277 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3278 { 3279 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3280 u32 reg; 3281 3282 reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx); 3283 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3284 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3285 } 3286 3287 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 3288 enum rtw89_mac_hwmod_sel sel) 3289 { 3290 int ret; 3291 3292 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3293 if (ret) { 3294 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3295 sel, mac_idx); 3296 return ret; 3297 } 3298 3299 if (sel == RTW89_DMAC_SEL) { 3300 rtw89_wdrls_imr_enable(rtwdev); 3301 rtw89_wsec_imr_enable(rtwdev); 3302 rtw89_mpdu_trx_imr_enable(rtwdev); 3303 rtw89_sta_sch_imr_enable(rtwdev); 3304 rtw89_txpktctl_imr_enable(rtwdev); 3305 rtw89_wde_imr_enable(rtwdev); 3306 rtw89_ple_imr_enable(rtwdev); 3307 rtw89_pktin_imr_enable(rtwdev); 3308 rtw89_dispatcher_imr_enable(rtwdev); 3309 rtw89_cpuio_imr_enable(rtwdev); 3310 rtw89_bbrpt_imr_enable(rtwdev); 3311 } else if (sel == RTW89_CMAC_SEL) { 3312 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3313 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3314 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3315 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3316 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3317 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3318 } else { 3319 return -EINVAL; 3320 } 3321 3322 return 0; 3323 } 3324 3325 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) 3326 { 3327 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3328 3329 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3330 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3331 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3332 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3333 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 3334 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3335 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3336 } 3337 3338 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 3339 { 3340 int ret = 0; 3341 3342 if (enable) { 3343 ret = band1_enable(rtwdev); 3344 if (ret) { 3345 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3346 return ret; 3347 } 3348 3349 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3350 if (ret) { 3351 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3352 return ret; 3353 } 3354 } else { 3355 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3356 return -EINVAL; 3357 } 3358 3359 return 0; 3360 } 3361 3362 static int set_host_rpr(struct rtw89_dev *rtwdev) 3363 { 3364 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3365 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3366 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3367 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3368 B_AX_RLSRPT0_FLTR_MAP_MASK); 3369 } else { 3370 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3371 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3372 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3373 B_AX_RLSRPT0_FLTR_MAP_MASK); 3374 } 3375 3376 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3377 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3378 3379 return 0; 3380 } 3381 3382 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 3383 { 3384 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3385 int ret; 3386 3387 ret = dmac_init(rtwdev, 0); 3388 if (ret) { 3389 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3390 return ret; 3391 } 3392 3393 ret = cmac_init(rtwdev, 0); 3394 if (ret) { 3395 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3396 return ret; 3397 } 3398 3399 if (is_qta_dbcc(rtwdev, qta_mode)) { 3400 ret = rtw89_mac_dbcc_enable(rtwdev, true); 3401 if (ret) { 3402 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3403 return ret; 3404 } 3405 } 3406 3407 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3408 if (ret) { 3409 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3410 return ret; 3411 } 3412 3413 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3414 if (ret) { 3415 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3416 return ret; 3417 } 3418 3419 rtw89_mac_err_imr_ctrl(rtwdev, true); 3420 3421 ret = set_host_rpr(rtwdev); 3422 if (ret) { 3423 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3424 return ret; 3425 } 3426 3427 return 0; 3428 } 3429 3430 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3431 { 3432 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3433 u32 val32; 3434 3435 if (chip_id == RTL8852B || chip_id == RTL8851B) { 3436 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3437 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3438 return; 3439 } 3440 3441 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3442 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3443 3444 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3445 val32 |= B_AX_FS_WDT_INT; 3446 val32 &= ~B_AX_FS_WDT_INT_MSK; 3447 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3448 } 3449 3450 void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) 3451 { 3452 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3453 3454 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3455 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3456 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3457 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3458 3459 rtw89_disable_fw_watchdog(rtwdev); 3460 3461 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3462 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3463 } 3464 3465 int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw) 3466 { 3467 u32 val; 3468 int ret; 3469 3470 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3471 return -EFAULT; 3472 3473 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3474 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3475 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3476 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3477 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3478 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3479 3480 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3481 3482 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3483 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3484 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3485 B_AX_WCPU_FWDL_STS_MASK); 3486 3487 if (dlfw) 3488 val |= B_AX_WCPU_FWDL_EN; 3489 3490 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3491 3492 if (rtwdev->chip->chip_id == RTL8852B) 3493 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3494 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3495 3496 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3497 boot_reason); 3498 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3499 3500 if (!dlfw) { 3501 mdelay(5); 3502 3503 ret = rtw89_fw_check_rdy(rtwdev); 3504 if (ret) 3505 return ret; 3506 } 3507 3508 return 0; 3509 } 3510 3511 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3512 { 3513 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3514 u32 val; 3515 int ret; 3516 3517 if (chip_id == RTL8852C) 3518 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3519 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3520 else 3521 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3522 B_AX_PKT_BUF_EN; 3523 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3524 3525 if (chip_id == RTL8851B) 3526 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3527 else 3528 val = B_AX_DISPATCHER_CLK_EN; 3529 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3530 3531 if (chip_id != RTL8852C) 3532 goto dle; 3533 3534 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3535 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3536 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3537 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3538 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3539 3540 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3541 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3542 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3543 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3544 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3545 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3546 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3547 3548 dle: 3549 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3550 if (ret) { 3551 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3552 return ret; 3553 } 3554 3555 ret = hfc_init(rtwdev, true, false, true); 3556 if (ret) { 3557 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3558 return ret; 3559 } 3560 3561 return ret; 3562 } 3563 3564 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3565 { 3566 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3567 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3568 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3569 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3570 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3571 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3572 3573 return 0; 3574 } 3575 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3576 3577 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3578 { 3579 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3580 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3581 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3582 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3583 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3584 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3585 3586 return 0; 3587 } 3588 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3589 3590 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) 3591 { 3592 int ret; 3593 3594 ret = rtw89_mac_power_switch(rtwdev, true); 3595 if (ret) { 3596 rtw89_mac_power_switch(rtwdev, false); 3597 ret = rtw89_mac_power_switch(rtwdev, true); 3598 if (ret) 3599 return ret; 3600 } 3601 3602 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3603 3604 ret = rtw89_mac_dmac_pre_init(rtwdev); 3605 if (ret) 3606 return ret; 3607 3608 if (rtwdev->hci.ops->mac_pre_init) { 3609 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3610 if (ret) 3611 return ret; 3612 } 3613 3614 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); 3615 if (ret) 3616 return ret; 3617 3618 return 0; 3619 } 3620 3621 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3622 { 3623 int ret; 3624 3625 ret = rtw89_mac_partial_init(rtwdev); 3626 if (ret) 3627 goto fail; 3628 3629 ret = rtw89_chip_enable_bb_rf(rtwdev); 3630 if (ret) 3631 goto fail; 3632 3633 ret = rtw89_mac_sys_init(rtwdev); 3634 if (ret) 3635 goto fail; 3636 3637 ret = rtw89_mac_trx_init(rtwdev); 3638 if (ret) 3639 goto fail; 3640 3641 if (rtwdev->hci.ops->mac_post_init) { 3642 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3643 if (ret) 3644 goto fail; 3645 } 3646 3647 rtw89_fw_send_all_early_h2c(rtwdev); 3648 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3649 3650 return ret; 3651 fail: 3652 rtw89_mac_power_switch(rtwdev, false); 3653 3654 return ret; 3655 } 3656 3657 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3658 { 3659 u8 i; 3660 3661 for (i = 0; i < 4; i++) { 3662 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3663 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3664 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3665 } 3666 } 3667 3668 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3669 { 3670 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3671 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3672 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3673 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3674 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3675 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3676 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3677 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3678 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3679 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3680 } 3681 3682 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3683 { 3684 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3685 u8 grp = macid >> 5; 3686 int ret; 3687 3688 /* If this is called by change_interface() in the case of P2P, it could 3689 * be power-off, so ignore this operation. 3690 */ 3691 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 3692 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3693 return 0; 3694 3695 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3696 if (ret) 3697 return ret; 3698 3699 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3700 3701 return 0; 3702 } 3703 3704 static const struct rtw89_port_reg rtw_port_base = { 3705 .port_cfg = R_AX_PORT_CFG_P0, 3706 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3707 .bcn_area = R_AX_BCN_AREA_P0, 3708 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3709 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3710 .tbtt_agg = R_AX_TBTT_AGG_P0, 3711 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3712 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3713 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3714 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3715 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3716 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3717 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3718 .tsftr_l = R_AX_TSFTR_LOW_P0, 3719 .tsftr_h = R_AX_TSFTR_HIGH_P0 3720 }; 3721 3722 #define BCN_INTERVAL 100 3723 #define BCN_ERLY_DEF 160 3724 #define BCN_SETUP_DEF 2 3725 #define BCN_HOLD_DEF 200 3726 #define BCN_MASK_DEF 0 3727 #define TBTT_ERLY_DEF 5 3728 #define BCN_SET_UNIT 32 3729 #define BCN_ERLY_SET_DLY (10 * 2) 3730 3731 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3732 struct rtw89_vif *rtwvif) 3733 { 3734 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3735 const struct rtw89_port_reg *p = &rtw_port_base; 3736 3737 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3738 return; 3739 3740 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3741 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3742 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3743 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3744 3745 msleep(vif->bss_conf.beacon_int + 1); 3746 3747 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3748 B_AX_BRK_SETUP); 3749 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3750 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3751 } 3752 3753 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3754 struct rtw89_vif *rtwvif, bool en) 3755 { 3756 const struct rtw89_port_reg *p = &rtw_port_base; 3757 3758 if (en) 3759 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3760 else 3761 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3762 } 3763 3764 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3765 struct rtw89_vif *rtwvif, bool en) 3766 { 3767 const struct rtw89_port_reg *p = &rtw_port_base; 3768 3769 if (en) 3770 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3771 else 3772 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3773 } 3774 3775 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3776 struct rtw89_vif *rtwvif) 3777 { 3778 const struct rtw89_port_reg *p = &rtw_port_base; 3779 3780 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3781 rtwvif->net_type); 3782 } 3783 3784 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3785 struct rtw89_vif *rtwvif) 3786 { 3787 const struct rtw89_port_reg *p = &rtw_port_base; 3788 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3789 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3790 3791 if (en) 3792 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3793 else 3794 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3795 } 3796 3797 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3798 struct rtw89_vif *rtwvif) 3799 { 3800 const struct rtw89_port_reg *p = &rtw_port_base; 3801 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3802 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3803 u32 bit = B_AX_RX_BSSID_FIT_EN; 3804 3805 if (en) 3806 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3807 else 3808 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3809 } 3810 3811 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3812 struct rtw89_vif *rtwvif) 3813 { 3814 const struct rtw89_port_reg *p = &rtw_port_base; 3815 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3816 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3817 3818 if (en) 3819 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3820 else 3821 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3822 } 3823 3824 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3825 struct rtw89_vif *rtwvif) 3826 { 3827 const struct rtw89_port_reg *p = &rtw_port_base; 3828 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3829 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3830 3831 if (en) 3832 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3833 else 3834 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3835 } 3836 3837 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3838 struct rtw89_vif *rtwvif) 3839 { 3840 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3841 const struct rtw89_port_reg *p = &rtw_port_base; 3842 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3843 3844 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3845 bcn_int); 3846 } 3847 3848 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3849 struct rtw89_vif *rtwvif) 3850 { 3851 static const u32 hiq_win_addr[RTW89_PORT_NUM] = { 3852 R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3853 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3854 R_AX_PORT_HGQ_WINDOW_CFG + 3, 3855 }; 3856 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3857 u8 port = rtwvif->port; 3858 u32 reg; 3859 3860 reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx); 3861 rtw89_write8(rtwdev, reg, win); 3862 } 3863 3864 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3865 struct rtw89_vif *rtwvif) 3866 { 3867 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3868 const struct rtw89_port_reg *p = &rtw_port_base; 3869 u32 addr; 3870 3871 addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); 3872 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3873 3874 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3875 vif->bss_conf.dtim_period); 3876 } 3877 3878 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3879 struct rtw89_vif *rtwvif) 3880 { 3881 const struct rtw89_port_reg *p = &rtw_port_base; 3882 3883 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3884 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3885 } 3886 3887 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3888 struct rtw89_vif *rtwvif) 3889 { 3890 const struct rtw89_port_reg *p = &rtw_port_base; 3891 3892 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3893 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3894 } 3895 3896 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3897 struct rtw89_vif *rtwvif) 3898 { 3899 const struct rtw89_port_reg *p = &rtw_port_base; 3900 3901 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3902 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3903 } 3904 3905 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3906 struct rtw89_vif *rtwvif) 3907 { 3908 const struct rtw89_port_reg *p = &rtw_port_base; 3909 3910 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3911 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3912 } 3913 3914 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3915 struct rtw89_vif *rtwvif) 3916 { 3917 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3918 static const u32 masks[RTW89_PORT_NUM] = { 3919 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3920 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3921 B_AX_BSS_COLOB_AX_PORT_4_MASK, 3922 }; 3923 u8 port = rtwvif->port; 3924 u32 reg_base; 3925 u32 reg; 3926 u8 bss_color; 3927 3928 bss_color = vif->bss_conf.he_bss_color.color; 3929 reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; 3930 reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); 3931 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3932 } 3933 3934 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3935 struct rtw89_vif *rtwvif) 3936 { 3937 u8 port = rtwvif->port; 3938 u32 reg; 3939 3940 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3941 return; 3942 3943 if (port == 0) { 3944 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); 3945 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3946 } 3947 } 3948 3949 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3950 struct rtw89_vif *rtwvif) 3951 { 3952 u8 port = rtwvif->port; 3953 u32 reg; 3954 u32 val; 3955 3956 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); 3957 val = rtw89_read32(rtwdev, reg); 3958 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 3959 if (port == 0) 3960 val &= ~BIT(0); 3961 rtw89_write32(rtwdev, reg, val); 3962 } 3963 3964 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 3965 struct rtw89_vif *rtwvif, bool enable) 3966 { 3967 const struct rtw89_port_reg *p = &rtw_port_base; 3968 3969 if (enable) 3970 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 3971 B_AX_PORT_FUNC_EN); 3972 else 3973 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 3974 B_AX_PORT_FUNC_EN); 3975 } 3976 3977 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 3978 struct rtw89_vif *rtwvif) 3979 { 3980 const struct rtw89_port_reg *p = &rtw_port_base; 3981 3982 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 3983 BCN_ERLY_DEF); 3984 } 3985 3986 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 3987 struct rtw89_vif *rtwvif) 3988 { 3989 const struct rtw89_port_reg *p = &rtw_port_base; 3990 u16 val; 3991 3992 if (rtwdev->chip->chip_id != RTL8852C) 3993 return; 3994 3995 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 3996 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 3997 return; 3998 3999 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4000 B_AX_TBTT_SHIFT_OFST_SIGN; 4001 4002 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 4003 B_AX_TBTT_SHIFT_OFST_MASK, val); 4004 } 4005 4006 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4007 struct rtw89_vif *rtwvif, 4008 struct rtw89_vif *rtwvif_src, 4009 u16 offset_tu) 4010 { 4011 u32 val, reg; 4012 4013 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4014 reg = rtw89_mac_reg_by_idx(R_AX_PORT0_TSF_SYNC + rtwvif->port * 4, 4015 rtwvif->mac_idx); 4016 4017 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4018 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4019 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4020 } 4021 4022 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4023 struct rtw89_vif *rtwvif, 4024 struct rtw89_vif *rtwvif_src, 4025 u8 offset, int *n_offset) 4026 { 4027 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 4028 return; 4029 4030 /* adjust offset randomly to avoid beacon conflict */ 4031 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4032 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 4033 (*n_offset) * offset); 4034 4035 (*n_offset)++; 4036 } 4037 4038 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4039 { 4040 struct rtw89_vif *src = NULL, *tmp; 4041 u8 offset = 100, vif_aps = 0; 4042 int n_offset = 1; 4043 4044 rtw89_for_each_rtwvif(rtwdev, tmp) { 4045 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4046 src = tmp; 4047 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4048 vif_aps++; 4049 } 4050 4051 if (vif_aps == 0) 4052 return; 4053 4054 offset /= (vif_aps + 1); 4055 4056 rtw89_for_each_rtwvif(rtwdev, tmp) 4057 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4058 } 4059 4060 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4061 { 4062 int ret; 4063 4064 ret = rtw89_mac_port_update(rtwdev, rtwvif); 4065 if (ret) 4066 return ret; 4067 4068 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4069 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4070 4071 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4072 if (ret) 4073 return ret; 4074 4075 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4076 if (ret) 4077 return ret; 4078 4079 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4080 if (ret) 4081 return ret; 4082 4083 ret = rtw89_cam_init(rtwdev, rtwvif); 4084 if (ret) 4085 return ret; 4086 4087 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4088 if (ret) 4089 return ret; 4090 4091 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 4092 if (ret) 4093 return ret; 4094 4095 return 0; 4096 } 4097 4098 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4099 { 4100 int ret; 4101 4102 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4103 if (ret) 4104 return ret; 4105 4106 rtw89_cam_deinit(rtwdev, rtwvif); 4107 4108 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4109 if (ret) 4110 return ret; 4111 4112 return 0; 4113 } 4114 4115 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4116 { 4117 u8 port = rtwvif->port; 4118 4119 if (port >= RTW89_PORT_NUM) 4120 return -EINVAL; 4121 4122 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4123 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4124 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4125 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4126 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4127 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4128 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 4129 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 4130 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4131 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4132 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4133 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4134 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4135 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4136 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4137 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4138 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4139 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4140 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4141 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4142 rtw89_mac_port_tsf_resync_all(rtwdev); 4143 fsleep(BCN_ERLY_SET_DLY); 4144 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4145 4146 return 0; 4147 } 4148 4149 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4150 u64 *tsf) 4151 { 4152 const struct rtw89_port_reg *p = &rtw_port_base; 4153 u32 tsf_low, tsf_high; 4154 int ret; 4155 4156 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 4157 if (ret) 4158 return ret; 4159 4160 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 4161 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 4162 *tsf = (u64)tsf_high << 32 | tsf_low; 4163 4164 return 0; 4165 } 4166 4167 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4168 struct cfg80211_bss *bss, 4169 void *data) 4170 { 4171 const struct cfg80211_bss_ies *ies; 4172 const struct element *elem; 4173 bool *tolerated = data; 4174 4175 rcu_read_lock(); 4176 ies = rcu_dereference(bss->ies); 4177 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4178 ies->len); 4179 4180 if (!elem || elem->datalen < 10 || 4181 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4182 *tolerated = false; 4183 rcu_read_unlock(); 4184 } 4185 4186 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4187 struct ieee80211_vif *vif) 4188 { 4189 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4190 struct ieee80211_hw *hw = rtwdev->hw; 4191 bool tolerated = true; 4192 u32 reg; 4193 4194 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 4195 return; 4196 4197 if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR)) 4198 return; 4199 4200 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef, 4201 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4202 &tolerated); 4203 4204 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); 4205 if (tolerated) 4206 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4207 else 4208 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4209 } 4210 4211 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4212 { 4213 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false); 4214 } 4215 4216 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4217 { 4218 int ret; 4219 4220 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 4221 RTW89_MAX_MAC_ID_NUM); 4222 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4223 return -ENOSPC; 4224 4225 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4226 if (ret) 4227 goto release_mac_id; 4228 4229 return 0; 4230 4231 release_mac_id: 4232 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4233 4234 return ret; 4235 } 4236 4237 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4238 { 4239 int ret; 4240 4241 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4242 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4243 4244 return ret; 4245 } 4246 4247 static void 4248 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4249 { 4250 } 4251 4252 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4253 { 4254 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4255 4256 return band == op->band_type && channel == op->primary_channel; 4257 } 4258 4259 static void 4260 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4261 u32 len) 4262 { 4263 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4264 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4265 struct rtw89_chan new; 4266 u8 reason, status, tx_fail, band, actual_period; 4267 u32 last_chan = rtwdev->scan_info.last_chan_idx; 4268 u16 chan; 4269 int ret; 4270 4271 if (!rtwvif) 4272 return; 4273 4274 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 4275 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 4276 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 4277 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 4278 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 4279 actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data); 4280 4281 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4282 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4283 4284 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4285 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4286 band, chan, reason, status, tx_fail, actual_period); 4287 4288 switch (reason) { 4289 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4290 if (rtw89_is_op_chan(rtwdev, band, chan)) 4291 ieee80211_stop_queues(rtwdev->hw); 4292 return; 4293 case RTW89_SCAN_END_SCAN_NOTIFY: 4294 if (rtwvif && rtwvif->scan_req && 4295 last_chan < rtwvif->scan_req->n_channels) { 4296 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4297 if (ret) { 4298 rtw89_hw_scan_abort(rtwdev, vif); 4299 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4300 } 4301 } else { 4302 rtw89_hw_scan_complete(rtwdev, vif, false); 4303 } 4304 break; 4305 case RTW89_SCAN_ENTER_CH_NOTIFY: 4306 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4307 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4308 &rtwdev->scan_info.op_chan); 4309 ieee80211_wake_queues(rtwdev->hw); 4310 } else { 4311 rtw89_chan_create(&new, chan, chan, band, 4312 RTW89_CHANNEL_WIDTH_20); 4313 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4314 &new); 4315 } 4316 break; 4317 default: 4318 return; 4319 } 4320 } 4321 4322 static void 4323 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4324 struct sk_buff *skb) 4325 { 4326 struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4327 enum nl80211_cqm_rssi_threshold_event nl_event; 4328 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4329 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4330 u8 type, event, mac_id; 4331 s8 sig; 4332 4333 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4334 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4335 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4336 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4337 4338 if (mac_id != rtwvif->mac_id) 4339 return; 4340 4341 rtw89_debug(rtwdev, RTW89_DBG_FW, 4342 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4343 mac_id, type, sig, event); 4344 4345 switch (type) { 4346 case RTW89_BCN_FLTR_BEACON_LOSS: 4347 if (!rtwdev->scanning && !rtwvif->offchan) 4348 ieee80211_connection_loss(vif); 4349 else 4350 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4351 return; 4352 case RTW89_BCN_FLTR_NOTIFY: 4353 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4354 break; 4355 case RTW89_BCN_FLTR_RSSI: 4356 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4357 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4358 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4359 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4360 else 4361 return; 4362 break; 4363 default: 4364 return; 4365 } 4366 4367 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4368 } 4369 4370 static void 4371 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4372 u32 len) 4373 { 4374 struct rtw89_vif *rtwvif; 4375 4376 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4377 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4378 } 4379 4380 static void 4381 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4382 { 4383 /* N.B. This will run in interrupt context. */ 4384 4385 rtw89_debug(rtwdev, RTW89_DBG_FW, 4386 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4387 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4388 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4389 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4390 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4391 } 4392 4393 static void 4394 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4395 { 4396 /* N.B. This will run in interrupt context. */ 4397 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4398 const struct rtw89_c2h_done_ack *c2h = 4399 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4400 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4401 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4402 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4403 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4404 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4405 struct rtw89_completion_data data = {}; 4406 unsigned int cond; 4407 4408 rtw89_debug(rtwdev, RTW89_DBG_FW, 4409 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4410 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4411 4412 if (h2c_cat != H2C_CAT_MAC) 4413 return; 4414 4415 switch (h2c_class) { 4416 default: 4417 return; 4418 case H2C_CL_MAC_FW_OFLD: 4419 switch (h2c_func) { 4420 default: 4421 return; 4422 case H2C_FUNC_ADD_SCANOFLD_CH: 4423 case H2C_FUNC_SCANOFLD: 4424 cond = RTW89_FW_OFLD_WAIT_COND(0, h2c_func); 4425 break; 4426 } 4427 4428 data.err = !!h2c_return; 4429 rtw89_complete_cond(fw_ofld_wait, cond, &data); 4430 return; 4431 } 4432 } 4433 4434 static void 4435 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4436 { 4437 rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), 4438 RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); 4439 } 4440 4441 static void 4442 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4443 { 4444 } 4445 4446 static void 4447 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 4448 u32 len) 4449 { 4450 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 4451 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 4452 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 4453 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 4454 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 4455 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 4456 struct rtw89_completion_data data = {}; 4457 unsigned int cond; 4458 4459 data.err = !pkt_len; 4460 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 4461 4462 rtw89_complete_cond(wait, cond, &data); 4463 } 4464 4465 static void 4466 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4467 u32 len) 4468 { 4469 } 4470 4471 static void 4472 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4473 { 4474 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4475 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4476 4477 switch (func) { 4478 case H2C_FUNC_ADD_MCC: 4479 case H2C_FUNC_START_MCC: 4480 case H2C_FUNC_STOP_MCC: 4481 case H2C_FUNC_DEL_MCC_GROUP: 4482 case H2C_FUNC_RESET_MCC_GROUP: 4483 case H2C_FUNC_MCC_REQ_TSF: 4484 case H2C_FUNC_MCC_MACID_BITMAP: 4485 case H2C_FUNC_MCC_SYNC: 4486 case H2C_FUNC_MCC_SET_DURATION: 4487 break; 4488 default: 4489 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4490 "invalid MCC C2H RCV ACK: func %d\n", func); 4491 return; 4492 } 4493 4494 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4495 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4496 } 4497 4498 static void 4499 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4500 { 4501 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4502 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4503 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4504 struct rtw89_completion_data data = {}; 4505 unsigned int cond; 4506 bool next = false; 4507 4508 switch (func) { 4509 case H2C_FUNC_MCC_REQ_TSF: 4510 next = true; 4511 break; 4512 case H2C_FUNC_MCC_MACID_BITMAP: 4513 case H2C_FUNC_MCC_SYNC: 4514 case H2C_FUNC_MCC_SET_DURATION: 4515 break; 4516 case H2C_FUNC_ADD_MCC: 4517 case H2C_FUNC_START_MCC: 4518 case H2C_FUNC_STOP_MCC: 4519 case H2C_FUNC_DEL_MCC_GROUP: 4520 case H2C_FUNC_RESET_MCC_GROUP: 4521 default: 4522 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4523 "invalid MCC C2H REQ ACK: func %d\n", func); 4524 return; 4525 } 4526 4527 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4528 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 4529 group, func, retcode); 4530 4531 if (!retcode && next) 4532 return; 4533 4534 data.err = !!retcode; 4535 cond = RTW89_MCC_WAIT_COND(group, func); 4536 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4537 } 4538 4539 static void 4540 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4541 { 4542 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 4543 struct rtw89_completion_data data = {}; 4544 struct rtw89_mac_mcc_tsf_rpt *rpt; 4545 unsigned int cond; 4546 4547 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 4548 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 4549 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 4550 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 4551 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 4552 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 4553 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 4554 4555 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4556 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 4557 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 4558 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 4559 4560 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 4561 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4562 } 4563 4564 static void 4565 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4566 { 4567 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 4568 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 4569 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 4570 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 4571 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 4572 struct rtw89_completion_data data = {}; 4573 unsigned int cond; 4574 bool rsp = true; 4575 bool err; 4576 u8 func; 4577 4578 switch (status) { 4579 case RTW89_MAC_MCC_ADD_ROLE_OK: 4580 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 4581 func = H2C_FUNC_ADD_MCC; 4582 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 4583 break; 4584 case RTW89_MAC_MCC_START_GROUP_OK: 4585 case RTW89_MAC_MCC_START_GROUP_FAIL: 4586 func = H2C_FUNC_START_MCC; 4587 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 4588 break; 4589 case RTW89_MAC_MCC_STOP_GROUP_OK: 4590 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 4591 func = H2C_FUNC_STOP_MCC; 4592 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 4593 break; 4594 case RTW89_MAC_MCC_DEL_GROUP_OK: 4595 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 4596 func = H2C_FUNC_DEL_MCC_GROUP; 4597 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 4598 break; 4599 case RTW89_MAC_MCC_RESET_GROUP_OK: 4600 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 4601 func = H2C_FUNC_RESET_MCC_GROUP; 4602 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 4603 break; 4604 case RTW89_MAC_MCC_SWITCH_CH_OK: 4605 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 4606 case RTW89_MAC_MCC_TXNULL0_OK: 4607 case RTW89_MAC_MCC_TXNULL0_FAIL: 4608 case RTW89_MAC_MCC_TXNULL1_OK: 4609 case RTW89_MAC_MCC_TXNULL1_FAIL: 4610 case RTW89_MAC_MCC_SWITCH_EARLY: 4611 case RTW89_MAC_MCC_TBTT: 4612 case RTW89_MAC_MCC_DURATION_START: 4613 case RTW89_MAC_MCC_DURATION_END: 4614 rsp = false; 4615 break; 4616 default: 4617 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4618 "invalid MCC C2H STS RPT: status %d\n", status); 4619 return; 4620 } 4621 4622 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4623 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 4624 group, macid, status, (u64)tsf_high << 32 | tsf_low); 4625 4626 if (!rsp) 4627 return; 4628 4629 data.err = err; 4630 cond = RTW89_MCC_WAIT_COND(group, func); 4631 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4632 } 4633 4634 static 4635 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 4636 struct sk_buff *c2h, u32 len) = { 4637 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 4638 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 4639 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 4640 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 4641 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 4642 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 4643 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 4644 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 4645 }; 4646 4647 static 4648 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 4649 struct sk_buff *c2h, u32 len) = { 4650 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 4651 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 4652 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 4653 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 4654 }; 4655 4656 static 4657 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 4658 struct sk_buff *c2h, u32 len) = { 4659 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 4660 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 4661 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 4662 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 4663 }; 4664 4665 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 4666 { 4667 switch (class) { 4668 default: 4669 return false; 4670 case RTW89_MAC_C2H_CLASS_INFO: 4671 switch (func) { 4672 default: 4673 return false; 4674 case RTW89_MAC_C2H_FUNC_REC_ACK: 4675 case RTW89_MAC_C2H_FUNC_DONE_ACK: 4676 return true; 4677 } 4678 case RTW89_MAC_C2H_CLASS_OFLD: 4679 switch (func) { 4680 default: 4681 return false; 4682 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 4683 return true; 4684 } 4685 case RTW89_MAC_C2H_CLASS_MCC: 4686 return true; 4687 } 4688 } 4689 4690 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4691 u32 len, u8 class, u8 func) 4692 { 4693 void (*handler)(struct rtw89_dev *rtwdev, 4694 struct sk_buff *c2h, u32 len) = NULL; 4695 4696 switch (class) { 4697 case RTW89_MAC_C2H_CLASS_INFO: 4698 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 4699 handler = rtw89_mac_c2h_info_handler[func]; 4700 break; 4701 case RTW89_MAC_C2H_CLASS_OFLD: 4702 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 4703 handler = rtw89_mac_c2h_ofld_handler[func]; 4704 break; 4705 case RTW89_MAC_C2H_CLASS_MCC: 4706 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 4707 handler = rtw89_mac_c2h_mcc_handler[func]; 4708 break; 4709 case RTW89_MAC_C2H_CLASS_FWDBG: 4710 return; 4711 default: 4712 rtw89_info(rtwdev, "c2h class %d not support\n", class); 4713 return; 4714 } 4715 if (!handler) { 4716 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 4717 func); 4718 return; 4719 } 4720 handler(rtwdev, skb, len); 4721 } 4722 4723 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 4724 enum rtw89_phy_idx phy_idx, 4725 u32 reg_base, u32 *cr) 4726 { 4727 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 4728 enum rtw89_qta_mode mode = dle_mem->mode; 4729 u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); 4730 4731 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { 4732 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 4733 addr); 4734 goto error; 4735 } 4736 4737 if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) 4738 if (mode == RTW89_QTA_SCC) { 4739 rtw89_err(rtwdev, 4740 "[TXPWR] addr=0x%x but hw not enable\n", 4741 addr); 4742 goto error; 4743 } 4744 4745 *cr = addr; 4746 return true; 4747 4748 error: 4749 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 4750 addr, phy_idx); 4751 4752 return false; 4753 } 4754 EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); 4755 4756 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 4757 { 4758 u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); 4759 int ret; 4760 4761 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4762 if (ret) 4763 return ret; 4764 4765 if (!enable) { 4766 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 4767 return 0; 4768 } 4769 4770 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 4771 B_AX_APP_MAC_INFO_RPT | 4772 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 4773 B_AX_PPDU_STAT_RPT_CRC32); 4774 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 4775 RTW89_PRPT_DEST_HOST); 4776 4777 return 0; 4778 } 4779 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 4780 4781 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 4782 { 4783 #define MAC_AX_TIME_TH_SH 5 4784 #define MAC_AX_LEN_TH_SH 4 4785 #define MAC_AX_TIME_TH_MAX 255 4786 #define MAC_AX_LEN_TH_MAX 255 4787 #define MAC_AX_TIME_TH_DEF 88 4788 #define MAC_AX_LEN_TH_DEF 4080 4789 struct ieee80211_hw *hw = rtwdev->hw; 4790 u32 rts_threshold = hw->wiphy->rts_threshold; 4791 u32 time_th, len_th; 4792 u32 reg; 4793 4794 if (rts_threshold == (u32)-1) { 4795 time_th = MAC_AX_TIME_TH_DEF; 4796 len_th = MAC_AX_LEN_TH_DEF; 4797 } else { 4798 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 4799 len_th = rts_threshold; 4800 } 4801 4802 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 4803 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 4804 4805 reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); 4806 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 4807 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 4808 } 4809 4810 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 4811 { 4812 bool empty; 4813 int ret; 4814 4815 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4816 return; 4817 4818 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 4819 10000, 200000, false, rtwdev); 4820 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 4821 rtw89_info(rtwdev, "timed out to flush queues\n"); 4822 } 4823 4824 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 4825 { 4826 u8 val; 4827 u16 val16; 4828 u32 val32; 4829 int ret; 4830 4831 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 4832 if (rtwdev->chip->chip_id != RTL8851B) 4833 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 4834 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 4835 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 4836 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 4837 if (rtwdev->chip->chip_id != RTL8851B) 4838 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 4839 4840 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 4841 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 4842 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 4843 4844 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 4845 if (ret) { 4846 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 4847 return ret; 4848 } 4849 val32 = val32 & B_AX_WL_RX_CTRL; 4850 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 4851 if (ret) { 4852 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 4853 return ret; 4854 } 4855 4856 switch (coex->pta_mode) { 4857 case RTW89_MAC_AX_COEX_RTK_MODE: 4858 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4859 val &= ~B_AX_BTMODE_MASK; 4860 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 4861 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4862 4863 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 4864 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 4865 4866 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 4867 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 4868 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 4869 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 4870 break; 4871 case RTW89_MAC_AX_COEX_CSR_MODE: 4872 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4873 val &= ~B_AX_BTMODE_MASK; 4874 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 4875 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4876 4877 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 4878 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 4879 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 4880 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 4881 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 4882 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 4883 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 4884 val16 |= B_AX_ENHANCED_BT; 4885 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 4886 4887 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 4888 break; 4889 default: 4890 return -EINVAL; 4891 } 4892 4893 switch (coex->direction) { 4894 case RTW89_MAC_AX_COEX_INNER: 4895 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4896 val = (val & ~BIT(2)) | BIT(1); 4897 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4898 break; 4899 case RTW89_MAC_AX_COEX_OUTPUT: 4900 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4901 val = val | BIT(1) | BIT(0); 4902 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4903 break; 4904 case RTW89_MAC_AX_COEX_INPUT: 4905 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4906 val = val & ~(BIT(2) | BIT(1)); 4907 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4908 break; 4909 default: 4910 return -EINVAL; 4911 } 4912 4913 return 0; 4914 } 4915 EXPORT_SYMBOL(rtw89_mac_coex_init); 4916 4917 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 4918 const struct rtw89_mac_ax_coex *coex) 4919 { 4920 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 4921 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 4922 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 4923 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 4924 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 4925 4926 switch (coex->pta_mode) { 4927 case RTW89_MAC_AX_COEX_RTK_MODE: 4928 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4929 MAC_AX_RTK_MODE); 4930 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 4931 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 4932 break; 4933 case RTW89_MAC_AX_COEX_CSR_MODE: 4934 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4935 MAC_AX_CSR_MODE); 4936 break; 4937 default: 4938 return -EINVAL; 4939 } 4940 4941 return 0; 4942 } 4943 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 4944 4945 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4946 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4947 { 4948 u32 val = 0, ret; 4949 4950 if (gnt_cfg->band[0].gnt_bt) 4951 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 4952 4953 if (gnt_cfg->band[0].gnt_bt_sw_en) 4954 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 4955 4956 if (gnt_cfg->band[0].gnt_wl) 4957 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 4958 4959 if (gnt_cfg->band[0].gnt_wl_sw_en) 4960 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 4961 4962 if (gnt_cfg->band[1].gnt_bt) 4963 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 4964 4965 if (gnt_cfg->band[1].gnt_bt_sw_en) 4966 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 4967 4968 if (gnt_cfg->band[1].gnt_wl) 4969 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 4970 4971 if (gnt_cfg->band[1].gnt_wl_sw_en) 4972 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 4973 4974 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 4975 if (ret) { 4976 rtw89_err(rtwdev, "Write LTE fail!\n"); 4977 return ret; 4978 } 4979 4980 return 0; 4981 } 4982 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 4983 4984 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 4985 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4986 { 4987 u32 val = 0; 4988 4989 if (gnt_cfg->band[0].gnt_bt) 4990 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 4991 B_AX_GNT_BT_TX_VAL; 4992 else 4993 val |= B_AX_WL_ACT_VAL; 4994 4995 if (gnt_cfg->band[0].gnt_bt_sw_en) 4996 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4997 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4998 4999 if (gnt_cfg->band[0].gnt_wl) 5000 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5001 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5002 5003 if (gnt_cfg->band[0].gnt_wl_sw_en) 5004 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5005 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5006 5007 if (gnt_cfg->band[1].gnt_bt) 5008 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5009 B_AX_GNT_BT_TX_VAL; 5010 else 5011 val |= B_AX_WL_ACT_VAL; 5012 5013 if (gnt_cfg->band[1].gnt_bt_sw_en) 5014 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5015 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5016 5017 if (gnt_cfg->band[1].gnt_wl) 5018 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5019 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5020 5021 if (gnt_cfg->band[1].gnt_wl_sw_en) 5022 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5023 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5024 5025 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5026 5027 return 0; 5028 } 5029 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5030 5031 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5032 { 5033 u32 reg; 5034 u16 val; 5035 int ret; 5036 5037 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5038 if (ret) 5039 return ret; 5040 5041 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); 5042 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5043 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5044 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5045 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5046 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5047 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5048 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 5049 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 5050 B_AX_PLT_EN; 5051 rtw89_write16(rtwdev, reg, val); 5052 5053 return 0; 5054 } 5055 5056 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5057 { 5058 u32 fw_sb; 5059 5060 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5061 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5062 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5063 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5064 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5065 else 5066 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5067 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5068 val = B_AX_TOGGLE | 5069 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5070 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5071 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5072 fsleep(1000); /* avoid BT FW loss information */ 5073 } 5074 5075 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5076 { 5077 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5078 } 5079 5080 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5081 { 5082 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5083 5084 val = wl ? val | BIT(2) : val & ~BIT(2); 5085 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5086 5087 return 0; 5088 } 5089 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5090 5091 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5092 { 5093 struct rtw89_btc *btc = &rtwdev->btc; 5094 struct rtw89_btc_dm *dm = &btc->dm; 5095 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5096 int i; 5097 5098 if (wl) 5099 return 0; 5100 5101 for (i = 0; i < RTW89_PHY_MAX; i++) { 5102 g[i].gnt_bt_sw_en = 1; 5103 g[i].gnt_bt = 1; 5104 g[i].gnt_wl_sw_en = 1; 5105 g[i].gnt_wl = 0; 5106 } 5107 5108 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5109 } 5110 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5111 5112 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5113 { 5114 const struct rtw89_chip_info *chip = rtwdev->chip; 5115 u8 val = 0; 5116 5117 if (chip->chip_id == RTL8852C) 5118 return false; 5119 else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 5120 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5121 B_AX_LTE_MUX_CTRL_PATH >> 24); 5122 5123 return !!val; 5124 } 5125 5126 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 5127 { 5128 u32 reg; 5129 u16 cnt; 5130 5131 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); 5132 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 5133 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 5134 5135 return cnt; 5136 } 5137 5138 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 5139 bool keep) 5140 { 5141 u32 reg; 5142 5143 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5144 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 5145 if (keep) { 5146 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5147 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5148 BFRP_RX_STANDBY_TIMER_KEEP); 5149 } else { 5150 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5151 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5152 BFRP_RX_STANDBY_TIMER_RELEASE); 5153 } 5154 } 5155 5156 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5157 { 5158 u32 reg; 5159 u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 5160 B_AX_BFMEE_HE_NDPA_EN; 5161 5162 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5163 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 5164 if (en) { 5165 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5166 rtw89_write32_set(rtwdev, reg, mask); 5167 } else { 5168 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5169 rtw89_write32_clr(rtwdev, reg, mask); 5170 } 5171 } 5172 5173 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 5174 { 5175 u32 reg; 5176 u32 val32; 5177 int ret; 5178 5179 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5180 if (ret) 5181 return ret; 5182 5183 /* AP mode set tx gid to 63 */ 5184 /* STA mode set tx gid to 0(default) */ 5185 reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); 5186 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5187 5188 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5189 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5190 5191 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 5192 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5193 rtw89_write32(rtwdev, reg, val32); 5194 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5195 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5196 5197 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5198 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5199 B_AX_BFMEE_USE_NSTS | 5200 B_AX_BFMEE_CSI_GID_SEL | 5201 B_AX_BFMEE_CSI_FORCE_RETE_EN); 5202 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5203 rtw89_write32(rtwdev, reg, 5204 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5205 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5206 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5207 5208 reg = rtw89_mac_reg_by_idx(R_AX_CSIRPT_OPTION, mac_idx); 5209 rtw89_write32_set(rtwdev, reg, 5210 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 5211 5212 return 0; 5213 } 5214 5215 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 5216 struct ieee80211_vif *vif, 5217 struct ieee80211_sta *sta) 5218 { 5219 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5220 u8 mac_idx = rtwvif->mac_idx; 5221 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5222 u8 port_sel = rtwvif->port; 5223 u8 sound_dim = 3, t; 5224 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5225 u32 reg; 5226 u16 val; 5227 int ret; 5228 5229 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5230 if (ret) 5231 return ret; 5232 5233 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5234 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5235 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5236 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5237 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5238 phy_cap[5]); 5239 sound_dim = min(sound_dim, t); 5240 } 5241 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5242 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5243 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5244 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5245 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5246 sta->deflink.vht_cap.cap); 5247 sound_dim = min(sound_dim, t); 5248 } 5249 nc = min(nc, sound_dim); 5250 nr = min(nr, sound_dim); 5251 5252 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5253 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5254 5255 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5256 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5257 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5258 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5259 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5260 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5261 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5262 5263 if (port_sel == 0) 5264 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5265 else 5266 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5267 5268 rtw89_write16(rtwdev, reg, val); 5269 5270 return 0; 5271 } 5272 5273 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 5274 struct ieee80211_vif *vif, 5275 struct ieee80211_sta *sta) 5276 { 5277 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5278 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5279 u32 reg; 5280 u8 mac_idx = rtwvif->mac_idx; 5281 int ret; 5282 5283 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5284 if (ret) 5285 return ret; 5286 5287 if (sta->deflink.he_cap.has_he) { 5288 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5289 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5290 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5291 } 5292 if (sta->deflink.vht_cap.vht_supported) { 5293 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5294 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5295 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5296 } 5297 if (sta->deflink.ht_cap.ht_supported) { 5298 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5299 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5300 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5301 } 5302 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5303 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5304 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5305 rtw89_write32(rtwdev, 5306 rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5307 rrsc); 5308 5309 return 0; 5310 } 5311 5312 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5313 struct ieee80211_sta *sta) 5314 { 5315 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5316 5317 if (rtw89_sta_has_beamformer_cap(sta)) { 5318 rtw89_debug(rtwdev, RTW89_DBG_BF, 5319 "initialize bfee for new association\n"); 5320 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 5321 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 5322 rtw89_mac_csi_rrsc(rtwdev, vif, sta); 5323 } 5324 } 5325 5326 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5327 struct ieee80211_sta *sta) 5328 { 5329 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5330 5331 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 5332 } 5333 5334 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5335 struct ieee80211_bss_conf *conf) 5336 { 5337 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5338 u8 mac_idx = rtwvif->mac_idx; 5339 __le32 *p; 5340 5341 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 5342 5343 p = (__le32 *)conf->mu_group.membership; 5344 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), 5345 le32_to_cpu(p[0])); 5346 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), 5347 le32_to_cpu(p[1])); 5348 5349 p = (__le32 *)conf->mu_group.position; 5350 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), 5351 le32_to_cpu(p[0])); 5352 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), 5353 le32_to_cpu(p[1])); 5354 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), 5355 le32_to_cpu(p[2])); 5356 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), 5357 le32_to_cpu(p[3])); 5358 } 5359 5360 struct rtw89_mac_bf_monitor_iter_data { 5361 struct rtw89_dev *rtwdev; 5362 struct ieee80211_sta *down_sta; 5363 int count; 5364 }; 5365 5366 static 5367 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 5368 { 5369 struct rtw89_mac_bf_monitor_iter_data *iter_data = 5370 (struct rtw89_mac_bf_monitor_iter_data *)data; 5371 struct ieee80211_sta *down_sta = iter_data->down_sta; 5372 int *count = &iter_data->count; 5373 5374 if (down_sta == sta) 5375 return; 5376 5377 if (rtw89_sta_has_beamformer_cap(sta)) 5378 (*count)++; 5379 } 5380 5381 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 5382 struct ieee80211_sta *sta, bool disconnect) 5383 { 5384 struct rtw89_mac_bf_monitor_iter_data data; 5385 5386 data.rtwdev = rtwdev; 5387 data.down_sta = disconnect ? sta : NULL; 5388 data.count = 0; 5389 ieee80211_iterate_stations_atomic(rtwdev->hw, 5390 rtw89_mac_bf_monitor_calc_iter, 5391 &data); 5392 5393 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 5394 if (data.count) 5395 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5396 else 5397 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5398 } 5399 5400 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 5401 { 5402 struct rtw89_traffic_stats *stats = &rtwdev->stats; 5403 struct rtw89_vif *rtwvif; 5404 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 5405 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5406 bool keep_timer = true; 5407 bool old_keep_timer; 5408 5409 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5410 5411 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 5412 keep_timer = false; 5413 5414 if (keep_timer != old_keep_timer) { 5415 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5416 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 5417 keep_timer); 5418 } 5419 5420 if (en == old) 5421 return; 5422 5423 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5424 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 5425 } 5426 5427 static int 5428 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5429 u32 tx_time) 5430 { 5431 #define MAC_AX_DFLT_TX_TIME 5280 5432 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5433 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 5434 u32 reg; 5435 int ret = 0; 5436 5437 if (rtwsta->cctl_tx_time) { 5438 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 5439 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5440 } else { 5441 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5442 if (ret) { 5443 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 5444 return ret; 5445 } 5446 5447 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5448 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 5449 max_tx_time >> 5); 5450 } 5451 5452 return ret; 5453 } 5454 5455 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5456 bool resume, u32 tx_time) 5457 { 5458 int ret = 0; 5459 5460 if (!resume) { 5461 rtwsta->cctl_tx_time = true; 5462 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5463 } else { 5464 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5465 rtwsta->cctl_tx_time = false; 5466 } 5467 5468 return ret; 5469 } 5470 5471 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5472 u32 *tx_time) 5473 { 5474 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5475 u32 reg; 5476 int ret = 0; 5477 5478 if (rtwsta->cctl_tx_time) { 5479 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 5480 } else { 5481 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5482 if (ret) { 5483 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 5484 return ret; 5485 } 5486 5487 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5488 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 5489 } 5490 5491 return ret; 5492 } 5493 5494 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 5495 struct rtw89_sta *rtwsta, 5496 bool resume, u8 tx_retry) 5497 { 5498 int ret = 0; 5499 5500 rtwsta->data_tx_cnt_lmt = tx_retry; 5501 5502 if (!resume) { 5503 rtwsta->cctl_tx_retry_limit = true; 5504 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5505 } else { 5506 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5507 rtwsta->cctl_tx_retry_limit = false; 5508 } 5509 5510 return ret; 5511 } 5512 5513 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 5514 struct rtw89_sta *rtwsta, u8 *tx_retry) 5515 { 5516 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5517 u32 reg; 5518 int ret = 0; 5519 5520 if (rtwsta->cctl_tx_retry_limit) { 5521 *tx_retry = rtwsta->data_tx_cnt_lmt; 5522 } else { 5523 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5524 if (ret) { 5525 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 5526 return ret; 5527 } 5528 5529 reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); 5530 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 5531 } 5532 5533 return ret; 5534 } 5535 5536 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 5537 struct rtw89_vif *rtwvif, bool en) 5538 { 5539 u8 mac_idx = rtwvif->mac_idx; 5540 u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; 5541 u32 reg; 5542 u32 ret; 5543 5544 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5545 if (ret) 5546 return ret; 5547 5548 reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); 5549 if (en) 5550 rtw89_write16_set(rtwdev, reg, set); 5551 else 5552 rtw89_write16_clr(rtwdev, reg, set); 5553 5554 return 0; 5555 } 5556 5557 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 5558 { 5559 u32 val32; 5560 int ret; 5561 5562 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5563 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 5564 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 5565 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 5566 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5567 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5568 5569 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5570 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5571 if (ret) { 5572 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 5573 offset, val, mask); 5574 return ret; 5575 } 5576 5577 return 0; 5578 } 5579 EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 5580 5581 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 5582 { 5583 u32 val32; 5584 int ret; 5585 5586 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5587 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 5588 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 5589 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 5590 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5591 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5592 5593 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5594 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5595 if (ret) { 5596 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 5597 return ret; 5598 } 5599 5600 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 5601 5602 return 0; 5603 } 5604 EXPORT_SYMBOL(rtw89_mac_read_xtal_si); 5605 5606 static 5607 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 5608 { 5609 static const enum rtw89_pkt_drop_sel sels[] = { 5610 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5611 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5612 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5613 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5614 }; 5615 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5616 struct rtw89_pkt_drop_params params = {0}; 5617 int i; 5618 5619 params.mac_band = RTW89_MAC_0; 5620 params.macid = rtwsta->mac_id; 5621 params.port = rtwvif->port; 5622 params.mbssid = 0; 5623 params.tf_trs = rtwvif->trigger; 5624 5625 for (i = 0; i < ARRAY_SIZE(sels); i++) { 5626 params.sel = sels[i]; 5627 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5628 } 5629 } 5630 5631 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 5632 { 5633 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 5634 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5635 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 5636 struct rtw89_vif *target = data; 5637 5638 if (rtwvif != target) 5639 return; 5640 5641 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 5642 } 5643 5644 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 5645 { 5646 ieee80211_iterate_stations_atomic(rtwdev->hw, 5647 rtw89_mac_pkt_drop_vif_iter, 5648 rtwvif); 5649 } 5650 5651 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 5652 enum rtw89_mac_idx band) 5653 { 5654 struct rtw89_pkt_drop_params params = {0}; 5655 bool empty; 5656 int i, ret = 0, try_cnt = 3; 5657 5658 params.mac_band = band; 5659 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 5660 5661 for (i = 0; i < try_cnt; i++) { 5662 ret = read_poll_timeout(mac_is_txq_empty, empty, empty, 50, 5663 50000, false, rtwdev); 5664 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 5665 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5666 else 5667 return 0; 5668 } 5669 return ret; 5670 } 5671