1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "util.h" 15 16 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 17 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 18 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 19 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 20 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 21 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 22 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 26 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 29 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 31 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 35 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 36 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 37 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 38 }; 39 40 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 41 u32 val, enum rtw89_mac_mem_sel sel) 42 { 43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44 u32 addr = mac->mem_base_addrs[sel] + offset; 45 46 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 47 rtw89_write32(rtwdev, mac->indir_access_addr, val); 48 } 49 50 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 51 enum rtw89_mac_mem_sel sel) 52 { 53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 54 u32 addr = mac->mem_base_addrs[sel] + offset; 55 56 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 57 return rtw89_read32(rtwdev, mac->indir_access_addr); 58 } 59 60 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 61 enum rtw89_mac_hwmod_sel sel) 62 { 63 u32 val, r_val; 64 65 if (sel == RTW89_DMAC_SEL) { 66 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 67 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 69 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 70 val = B_AX_CMAC_EN; 71 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 72 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 73 val = B_AX_CMAC1_FEN; 74 } else { 75 return -EINVAL; 76 } 77 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 78 (val & r_val) != val) 79 return -EFAULT; 80 81 return 0; 82 } 83 84 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 85 { 86 u8 lte_ctrl; 87 int ret; 88 89 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 90 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 91 if (ret) 92 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 93 94 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 95 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 96 97 return ret; 98 } 99 100 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 101 { 102 u8 lte_ctrl; 103 int ret; 104 105 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 106 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 107 if (ret) 108 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 109 110 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 111 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 112 113 return ret; 114 } 115 116 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 117 { 118 u32 ctrl_reg, data_reg, ctrl_data; 119 u32 val; 120 int ret; 121 122 switch (ctrl->type) { 123 case DLE_CTRL_TYPE_WDE: 124 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 125 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 126 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 127 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 128 B_AX_WDE_DFI_ACTIVE; 129 break; 130 case DLE_CTRL_TYPE_PLE: 131 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 132 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 133 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 134 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 135 B_AX_PLE_DFI_ACTIVE; 136 break; 137 default: 138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 139 return -EINVAL; 140 } 141 142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 143 144 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 145 1, 1000, false, rtwdev, ctrl_reg); 146 if (ret) { 147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 148 ctrl_reg, ctrl_data); 149 return ret; 150 } 151 152 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 153 return 0; 154 } 155 156 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 157 struct rtw89_mac_dle_dfi_quota *quota) 158 { 159 struct rtw89_mac_dle_dfi_ctrl ctrl; 160 int ret; 161 162 ctrl.type = quota->dle_type; 163 ctrl.target = DLE_DFI_TYPE_QUOTA; 164 ctrl.addr = quota->qtaid; 165 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 166 if (ret) { 167 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 168 return ret; 169 } 170 171 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 172 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 173 return 0; 174 } 175 176 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 177 struct rtw89_mac_dle_dfi_qempty *qempty) 178 { 179 struct rtw89_mac_dle_dfi_ctrl ctrl; 180 u32 ret; 181 182 ctrl.type = qempty->dle_type; 183 ctrl.target = DLE_DFI_TYPE_QEMPTY; 184 ctrl.addr = qempty->grpsel; 185 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 186 if (ret) { 187 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 188 return ret; 189 } 190 191 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 192 return 0; 193 } 194 195 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 196 { 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 209 } 210 211 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 212 { 213 struct rtw89_mac_dle_dfi_qempty qempty; 214 struct rtw89_mac_dle_dfi_quota quota; 215 struct rtw89_mac_dle_dfi_ctrl ctrl; 216 u32 val, not_empty, i; 217 int ret; 218 219 qempty.dle_type = DLE_CTRL_TYPE_PLE; 220 qempty.grpsel = 0; 221 qempty.qempty = ~(u32)0; 222 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 223 if (ret) 224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 225 else 226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 227 228 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 229 if (!(not_empty & BIT(0))) 230 continue; 231 ctrl.type = DLE_CTRL_TYPE_PLE; 232 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 233 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 234 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 235 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 236 if (ret) 237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 238 else 239 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 240 u32_get_bits(ctrl.out_data, 241 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 242 } 243 244 quota.dle_type = DLE_CTRL_TYPE_PLE; 245 quota.qtaid = 6; 246 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 247 if (ret) 248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 249 else 250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 251 quota.rsv_pgnum, quota.use_pgnum); 252 253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 255 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 257 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 258 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 259 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 260 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 261 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 262 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 263 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 264 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 265 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 266 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 267 268 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 269 quota.dle_type = DLE_CTRL_TYPE_PLE; 270 quota.qtaid = 7; 271 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 272 if (ret) 273 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 274 else 275 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 276 quota.rsv_pgnum, quota.use_pgnum); 277 278 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 279 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 280 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 282 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 283 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 284 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 285 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 286 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 287 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 288 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 289 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 290 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 291 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 292 } 293 294 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 295 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 298 299 dump_err_status_dispatcher_ax(rtwdev); 300 } 301 302 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 303 enum mac_ax_err_info err) 304 { 305 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 306 u32 dbg, event; 307 308 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 309 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 310 311 switch (event) { 312 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 313 rtw89_info(rtwdev, "quota lost!\n"); 314 mac->dump_qta_lost(rtwdev); 315 break; 316 default: 317 break; 318 } 319 } 320 321 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 322 { 323 const struct rtw89_chip_info *chip = rtwdev->chip; 324 u32 dmac_err; 325 int i, ret; 326 327 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 328 if (ret) { 329 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 330 return; 331 } 332 333 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 334 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 335 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 337 338 if (dmac_err) { 339 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 341 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 343 if (chip->chip_id == RTL8852C) { 344 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 345 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 346 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 348 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 352 } 353 } 354 355 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 356 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 357 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 360 if (chip->chip_id == RTL8852C) 361 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 363 else 364 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 365 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 366 } 367 368 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 369 if (chip->chip_id == RTL8852C) { 370 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 371 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 372 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 374 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 376 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 378 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 380 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 382 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 384 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 386 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 388 389 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 390 B_AX_DBG_SEL0, 0x8B); 391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392 B_AX_DBG_SEL1, 0x8B); 393 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 394 B_AX_SEL_0XC0_MASK, 1); 395 for (i = 0; i < 0x10; i++) { 396 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 397 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 398 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 399 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 400 } 401 } else if (chip->chip_id == RTL8922A) { 402 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 403 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 406 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 407 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 408 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 409 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 410 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 411 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 412 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 413 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 414 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 415 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 416 } else { 417 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 419 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 421 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 423 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 425 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 427 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 429 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 430 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 431 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 432 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 433 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 435 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 437 } 438 } 439 440 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 441 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 442 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 445 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 449 } 450 451 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 452 if (chip->chip_id == RTL8922A) { 453 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 454 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 455 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 456 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 457 } else { 458 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 459 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 462 } 463 } 464 465 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 466 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 468 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 470 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 471 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 472 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 474 } 475 476 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 477 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 478 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 479 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 486 } else { 487 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 491 } 492 } 493 494 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 495 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 501 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 503 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 509 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 510 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 515 if (chip->chip_id == RTL8922A) { 516 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 517 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 520 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 521 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 522 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 524 } else { 525 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 526 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 527 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 529 if (chip->chip_id == RTL8852C) { 530 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 531 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 532 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 533 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 534 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 535 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 536 } else { 537 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 538 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 543 } 544 } 545 } 546 547 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 548 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 549 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 552 } 553 554 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 555 if (chip->chip_id == RTL8922A) { 556 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 557 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 558 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 559 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 560 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 561 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 562 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 563 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 564 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 565 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 566 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 567 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 568 } else { 569 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 570 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 573 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 574 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 577 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 578 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 581 } 582 } 583 584 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 585 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 586 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 587 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 590 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 591 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 594 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 595 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 598 } else { 599 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 600 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 601 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 602 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 605 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 606 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 609 } 610 if (chip->chip_id == RTL8922A) { 611 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 612 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 615 } 616 } 617 618 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 619 if (chip->chip_id == RTL8922A) { 620 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 621 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 624 } else if (chip->chip_id == RTL8852C) { 625 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 626 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 629 } 630 } 631 632 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 633 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 634 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 635 RTW89_MAC_MEM_AXIDMA)); 636 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 637 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 638 RTW89_MAC_MEM_AXIDMA)); 639 } 640 641 if (dmac_err & B_BE_MLO_ERR_INT) { 642 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 643 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 644 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 646 } 647 648 if (dmac_err & B_BE_PLRLS_ERR_INT) { 649 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 650 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 653 } 654 } 655 656 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 657 u8 band) 658 { 659 const struct rtw89_chip_info *chip = rtwdev->chip; 660 u32 offset = 0; 661 u32 cmac_err; 662 int ret; 663 664 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 665 if (ret) { 666 if (band) 667 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 668 else 669 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 670 return; 671 } 672 673 if (band) 674 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 675 676 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 677 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 678 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 679 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 680 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 681 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 682 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 683 684 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 685 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 686 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 689 } 690 691 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 692 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 693 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 694 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 695 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 696 } 697 698 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 699 if (chip->chip_id == RTL8852C) { 700 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 701 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 704 } else { 705 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 706 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 707 } 708 } 709 710 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 711 if (chip->chip_id == RTL8852C) { 712 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 713 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 716 } else { 717 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 718 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 719 } 720 } 721 722 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 723 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 724 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 725 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 726 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 727 } 728 729 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 730 if (chip->chip_id == RTL8852C) { 731 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 732 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 735 } else { 736 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 737 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 738 } 739 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 740 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 741 } 742 743 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 744 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 745 } 746 747 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 748 enum mac_ax_err_info err) 749 { 750 if (err != MAC_AX_ERR_L1_ERR_DMAC && 751 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 752 err != MAC_AX_ERR_L0_ERR_CMAC0 && 753 err != MAC_AX_ERR_L0_ERR_CMAC1 && 754 err != MAC_AX_ERR_RXI300) 755 return; 756 757 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 758 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 759 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 762 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 763 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 764 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 766 767 rtw89_mac_dump_dmac_err_status(rtwdev); 768 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 769 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 770 771 rtwdev->hci.ops->dump_err_status(rtwdev); 772 773 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 774 rtw89_mac_dump_l0_to_l1(rtwdev, err); 775 776 rtw89_info(rtwdev, "<---\n"); 777 } 778 779 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 780 { 781 struct rtw89_ser *ser = &rtwdev->ser; 782 u32 dmac_err, imr, isr; 783 int ret; 784 785 if (rtwdev->chip->chip_id == RTL8852C) { 786 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 787 if (ret) 788 return true; 789 790 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 791 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 792 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 793 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 794 795 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 796 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 797 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 798 return true; 799 } 800 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 801 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 802 return true; 803 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 804 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 805 return true; 806 } 807 } 808 809 return false; 810 } 811 812 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 813 { 814 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 815 u32 err, err_scnr; 816 int ret; 817 818 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 819 false, rtwdev, R_AX_HALT_C2H_CTRL); 820 if (ret) { 821 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 822 return ret; 823 } 824 825 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 826 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 827 828 err_scnr = RTW89_ERROR_SCENARIO(err); 829 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 830 err = MAC_AX_ERR_CPU_EXCEPTION; 831 else if (err_scnr == RTW89_WCPU_ASSERTION) 832 err = MAC_AX_ERR_ASSERTION; 833 else if (err_scnr == RTW89_RXI300_ERROR) 834 err = MAC_AX_ERR_RXI300; 835 836 if (rtw89_mac_suppress_log(rtwdev, err)) 837 return err; 838 839 rtw89_fw_st_dbg_dump(rtwdev); 840 mac->dump_err_status(rtwdev, err); 841 842 return err; 843 } 844 EXPORT_SYMBOL(rtw89_mac_get_err_status); 845 846 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 847 { 848 struct rtw89_ser *ser = &rtwdev->ser; 849 u32 halt; 850 int ret = 0; 851 852 if (err > MAC_AX_SET_ERR_MAX) { 853 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 854 return -EINVAL; 855 } 856 857 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 858 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 859 if (ret) { 860 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 861 return -EFAULT; 862 } 863 864 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 865 866 if (ser->prehandle_l1 && 867 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 868 return 0; 869 870 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 871 872 return 0; 873 } 874 EXPORT_SYMBOL(rtw89_mac_set_err_status); 875 876 static int hfc_reset_param(struct rtw89_dev *rtwdev) 877 { 878 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 879 struct rtw89_hfc_param_ini param_ini = {NULL}; 880 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 881 882 switch (rtwdev->hci.type) { 883 case RTW89_HCI_TYPE_PCIE: 884 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 885 param->en = 0; 886 break; 887 default: 888 return -EINVAL; 889 } 890 891 if (param_ini.pub_cfg) 892 param->pub_cfg = *param_ini.pub_cfg; 893 894 if (param_ini.prec_cfg) 895 param->prec_cfg = *param_ini.prec_cfg; 896 897 if (param_ini.ch_cfg) 898 param->ch_cfg = param_ini.ch_cfg; 899 900 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 901 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 902 param->mode = param_ini.mode; 903 904 return 0; 905 } 906 907 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 908 { 909 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 910 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 911 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 912 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 913 914 if (ch >= RTW89_DMA_CH_NUM) 915 return -EINVAL; 916 917 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 918 ch_cfg[ch].max > pub_cfg->pub_max) 919 return -EINVAL; 920 if (ch_cfg[ch].grp >= grp_num) 921 return -EINVAL; 922 923 return 0; 924 } 925 926 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 927 { 928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 929 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 930 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 931 932 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 933 if (rtwdev->chip->chip_id == RTL8852A) 934 return 0; 935 else 936 return -EFAULT; 937 } 938 939 return 0; 940 } 941 942 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 943 { 944 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 945 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 946 947 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 948 return -EFAULT; 949 950 return 0; 951 } 952 953 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 954 { 955 const struct rtw89_chip_info *chip = rtwdev->chip; 956 const struct rtw89_page_regs *regs = chip->page_regs; 957 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 958 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 959 int ret = 0; 960 u32 val = 0; 961 962 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 963 if (ret) 964 return ret; 965 966 ret = hfc_ch_cfg_chk(rtwdev, ch); 967 if (ret) 968 return ret; 969 970 if (ch > RTW89_DMA_B1HI) 971 return -EINVAL; 972 973 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 974 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 975 (cfg[ch].grp ? B_AX_GRP : 0); 976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 977 978 return 0; 979 } 980 981 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 982 { 983 const struct rtw89_chip_info *chip = rtwdev->chip; 984 const struct rtw89_page_regs *regs = chip->page_regs; 985 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 986 struct rtw89_hfc_ch_info *info = param->ch_info; 987 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 988 u32 val; 989 u32 ret; 990 991 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 992 if (ret) 993 return ret; 994 995 if (ch > RTW89_DMA_H2C) 996 return -EINVAL; 997 998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 999 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1000 if (ch < RTW89_DMA_H2C) 1001 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1002 else 1003 info[ch].used = cfg[ch].min - info[ch].aval; 1004 1005 return 0; 1006 } 1007 1008 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1009 { 1010 const struct rtw89_chip_info *chip = rtwdev->chip; 1011 const struct rtw89_page_regs *regs = chip->page_regs; 1012 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1013 u32 val; 1014 int ret; 1015 1016 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1017 if (ret) 1018 return ret; 1019 1020 ret = hfc_pub_cfg_chk(rtwdev); 1021 if (ret) 1022 return ret; 1023 1024 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1025 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1027 1028 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1030 1031 return 0; 1032 } 1033 1034 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1035 { 1036 const struct rtw89_chip_info *chip = rtwdev->chip; 1037 const struct rtw89_page_regs *regs = chip->page_regs; 1038 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1039 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1040 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1041 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1042 u32 val; 1043 1044 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1045 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1046 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1047 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1048 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1049 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1050 info->pub_aval = 1051 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1052 B_AX_PUB_AVAL_PG_MASK); 1053 info->wp_aval = 1054 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1055 B_AX_WP_AVAL_PG_MASK); 1056 1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1058 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1059 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1060 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1061 prec_cfg->ch011_full_cond = 1062 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1063 prec_cfg->h2c_full_cond = 1064 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1065 prec_cfg->wp_ch07_full_cond = 1066 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1067 prec_cfg->wp_ch811_full_cond = 1068 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1069 1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1071 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1072 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1073 1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1075 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1076 1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1078 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1079 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1080 1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1082 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1083 1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1085 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1086 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1087 } 1088 1089 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1090 { 1091 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1092 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1093 int ret; 1094 1095 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1096 if (ret) 1097 return ret; 1098 1099 mac->hfc_get_mix_info(rtwdev); 1100 1101 ret = hfc_pub_info_chk(rtwdev); 1102 if (param->en && ret) 1103 return ret; 1104 1105 return 0; 1106 } 1107 1108 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1109 { 1110 const struct rtw89_chip_info *chip = rtwdev->chip; 1111 const struct rtw89_page_regs *regs = chip->page_regs; 1112 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1113 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1114 u32 val; 1115 1116 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1118 1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1120 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1121 prec_cfg->h2c_full_cond); 1122 } 1123 1124 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1125 { 1126 const struct rtw89_chip_info *chip = rtwdev->chip; 1127 const struct rtw89_page_regs *regs = chip->page_regs; 1128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1129 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1130 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1131 u32 val; 1132 1133 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1134 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1136 1137 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1139 1140 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1141 B_AX_PREC_PAGE_WP_CH07_MASK) | 1142 u32_encode_bits(prec_cfg->wp_ch811_prec, 1143 B_AX_PREC_PAGE_WP_CH811_MASK); 1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1145 1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1147 param->mode, B_AX_HCI_FC_MODE_MASK); 1148 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1149 B_AX_HCI_FC_WD_FULL_COND_MASK); 1150 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1151 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1152 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1153 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1154 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1155 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1157 } 1158 1159 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1160 { 1161 const struct rtw89_chip_info *chip = rtwdev->chip; 1162 const struct rtw89_page_regs *regs = chip->page_regs; 1163 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1164 u32 val; 1165 1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1167 param->en = en; 1168 param->h2c_en = h2c_en; 1169 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1170 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1171 (val & ~B_AX_HCI_FC_CH12_EN); 1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1173 } 1174 1175 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1176 { 1177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1178 const struct rtw89_chip_info *chip = rtwdev->chip; 1179 u32 dma_ch_mask = chip->dma_ch_mask; 1180 u8 ch; 1181 u32 ret = 0; 1182 1183 if (reset) 1184 ret = hfc_reset_param(rtwdev); 1185 if (ret) 1186 return ret; 1187 1188 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1189 if (ret) 1190 return ret; 1191 1192 mac->hfc_func_en(rtwdev, false, false); 1193 1194 if (!en && h2c_en) { 1195 mac->hfc_h2c_cfg(rtwdev); 1196 mac->hfc_func_en(rtwdev, en, h2c_en); 1197 return ret; 1198 } 1199 1200 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1201 if (dma_ch_mask & BIT(ch)) 1202 continue; 1203 ret = hfc_ch_ctrl(rtwdev, ch); 1204 if (ret) 1205 return ret; 1206 } 1207 1208 ret = hfc_pub_ctrl(rtwdev); 1209 if (ret) 1210 return ret; 1211 1212 mac->hfc_mix_cfg(rtwdev); 1213 if (en || h2c_en) { 1214 mac->hfc_func_en(rtwdev, en, h2c_en); 1215 udelay(10); 1216 } 1217 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1218 if (dma_ch_mask & BIT(ch)) 1219 continue; 1220 ret = hfc_upd_ch_info(rtwdev, ch); 1221 if (ret) 1222 return ret; 1223 } 1224 ret = hfc_upd_mix_info(rtwdev); 1225 1226 return ret; 1227 } 1228 1229 #define PWR_POLL_CNT 2000 1230 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1231 const struct rtw89_pwr_cfg *cfg) 1232 { 1233 u8 val = 0; 1234 int ret; 1235 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1236 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1237 1238 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1239 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1240 1241 if (!ret) 1242 return 0; 1243 1244 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1245 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1247 1248 return -EBUSY; 1249 } 1250 1251 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1252 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1253 { 1254 const struct rtw89_pwr_cfg *cur_cfg; 1255 u32 addr; 1256 u8 val; 1257 1258 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1259 if (!(cur_cfg->intf_msk & intf_msk) || 1260 !(cur_cfg->cv_msk & cv_msk)) 1261 continue; 1262 1263 switch (cur_cfg->cmd) { 1264 case PWR_CMD_WRITE: 1265 addr = cur_cfg->addr; 1266 1267 if (cur_cfg->base == PWR_BASE_SDIO) 1268 addr |= SDIO_LOCAL_BASE_ADDR; 1269 1270 val = rtw89_read8(rtwdev, addr); 1271 val &= ~(cur_cfg->msk); 1272 val |= (cur_cfg->val & cur_cfg->msk); 1273 1274 rtw89_write8(rtwdev, addr, val); 1275 break; 1276 case PWR_CMD_POLL: 1277 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1278 return -EBUSY; 1279 break; 1280 case PWR_CMD_DELAY: 1281 if (cur_cfg->val == PWR_DELAY_US) 1282 udelay(cur_cfg->addr); 1283 else 1284 fsleep(cur_cfg->addr * 1000); 1285 break; 1286 default: 1287 return -EINVAL; 1288 } 1289 } 1290 1291 return 0; 1292 } 1293 1294 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1295 const struct rtw89_pwr_cfg * const *cfg_seq) 1296 { 1297 int ret; 1298 1299 for (; *cfg_seq; cfg_seq++) { 1300 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1301 PWR_INTF_MSK_PCIE, *cfg_seq); 1302 if (ret) 1303 return -EBUSY; 1304 } 1305 1306 return 0; 1307 } 1308 1309 static enum rtw89_rpwm_req_pwr_state 1310 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1311 { 1312 enum rtw89_rpwm_req_pwr_state state; 1313 1314 switch (rtwdev->ps_mode) { 1315 case RTW89_PS_MODE_RFOFF: 1316 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1317 break; 1318 case RTW89_PS_MODE_CLK_GATED: 1319 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1320 break; 1321 case RTW89_PS_MODE_PWR_GATED: 1322 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1323 break; 1324 default: 1325 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1326 break; 1327 } 1328 return state; 1329 } 1330 1331 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1332 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1333 bool notify_wake) 1334 { 1335 u16 request; 1336 1337 spin_lock_bh(&rtwdev->rpwm_lock); 1338 1339 request = rtw89_read16(rtwdev, R_AX_RPWM); 1340 request ^= request | PS_RPWM_TOGGLE; 1341 request |= req_pwr_state; 1342 1343 if (notify_wake) { 1344 request |= PS_RPWM_NOTIFY_WAKE; 1345 } else { 1346 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1347 RPWM_SEQ_NUM_MAX; 1348 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1349 rtwdev->mac.rpwm_seq_num); 1350 1351 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1352 request |= PS_RPWM_ACK; 1353 } 1354 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1355 1356 spin_unlock_bh(&rtwdev->rpwm_lock); 1357 } 1358 1359 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1360 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1361 { 1362 bool request_deep_mode; 1363 bool in_deep_mode; 1364 u8 rpwm_req_num; 1365 u8 cpwm_rsp_seq; 1366 u8 cpwm_seq; 1367 u8 cpwm_status; 1368 1369 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1370 request_deep_mode = true; 1371 else 1372 request_deep_mode = false; 1373 1374 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1375 in_deep_mode = true; 1376 else 1377 in_deep_mode = false; 1378 1379 if (request_deep_mode != in_deep_mode) 1380 return -EPERM; 1381 1382 if (request_deep_mode) 1383 return 0; 1384 1385 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1386 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1387 PS_CPWM_RSP_SEQ_NUM); 1388 1389 if (rpwm_req_num != cpwm_rsp_seq) 1390 return -EPERM; 1391 1392 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1393 CPWM_SEQ_NUM_MAX; 1394 1395 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1396 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1397 return -EPERM; 1398 1399 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1400 if (cpwm_status != req_pwr_state) 1401 return -EPERM; 1402 1403 return 0; 1404 } 1405 1406 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1407 { 1408 enum rtw89_rpwm_req_pwr_state state; 1409 unsigned long delay = enter ? 10 : 150; 1410 int ret; 1411 int i; 1412 1413 if (enter) 1414 state = rtw89_mac_get_req_pwr_state(rtwdev); 1415 else 1416 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1417 1418 for (i = 0; i < RPWM_TRY_CNT; i++) { 1419 rtw89_mac_send_rpwm(rtwdev, state, false); 1420 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1421 !ret, delay, 15000, false, 1422 rtwdev, state); 1423 if (!ret) 1424 break; 1425 1426 if (i == RPWM_TRY_CNT - 1) 1427 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1428 enter ? "entering" : "leaving"); 1429 else 1430 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1431 "%d time firmware failed to ack for %s ps mode\n", 1432 i + 1, enter ? "entering" : "leaving"); 1433 } 1434 } 1435 1436 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1437 { 1438 enum rtw89_rpwm_req_pwr_state state; 1439 1440 state = rtw89_mac_get_req_pwr_state(rtwdev); 1441 rtw89_mac_send_rpwm(rtwdev, state, true); 1442 } 1443 1444 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1445 { 1446 #define PWR_ACT 1 1447 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1448 const struct rtw89_chip_info *chip = rtwdev->chip; 1449 const struct rtw89_pwr_cfg * const *cfg_seq; 1450 int (*cfg_func)(struct rtw89_dev *rtwdev); 1451 int ret; 1452 u8 val; 1453 1454 if (on) { 1455 cfg_seq = chip->pwr_on_seq; 1456 cfg_func = chip->ops->pwr_on_func; 1457 } else { 1458 cfg_seq = chip->pwr_off_seq; 1459 cfg_func = chip->ops->pwr_off_func; 1460 } 1461 1462 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1463 __rtw89_leave_ps_mode(rtwdev); 1464 1465 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1466 if (on && val == PWR_ACT) { 1467 rtw89_err(rtwdev, "MAC has already powered on\n"); 1468 return -EBUSY; 1469 } 1470 1471 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1472 if (ret) 1473 return ret; 1474 1475 if (on) { 1476 if (!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags)) 1477 mac->efuse_read_fw_secure(rtwdev); 1478 1479 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1480 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1481 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1482 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1483 } else { 1484 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1485 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1486 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1487 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1488 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1489 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1490 rtw89_set_entity_state(rtwdev, RTW89_PHY_0, false); 1491 rtw89_set_entity_state(rtwdev, RTW89_PHY_1, false); 1492 } 1493 1494 return 0; 1495 #undef PWR_ACT 1496 } 1497 1498 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1499 { 1500 rtw89_mac_power_switch(rtwdev, false); 1501 } 1502 1503 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1504 { 1505 u32 func_en = 0; 1506 u32 ck_en = 0; 1507 u32 c1pc_en = 0; 1508 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1509 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1510 1511 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1512 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1513 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1514 B_AX_CMAC_CRPRT; 1515 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1516 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1517 B_AX_RMAC_CKEN; 1518 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1519 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1520 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1521 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1522 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1523 1524 if (en) { 1525 if (mac_idx == RTW89_MAC_1) { 1526 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1527 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1528 B_AX_R_SYM_ISO_CMAC12PP); 1529 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1530 B_AX_CMAC1_FEN); 1531 } 1532 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1533 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1534 } else { 1535 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1536 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1537 if (mac_idx == RTW89_MAC_1) { 1538 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1539 B_AX_CMAC1_FEN); 1540 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1541 B_AX_R_SYM_ISO_CMAC12PP); 1542 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1543 } 1544 } 1545 1546 return 0; 1547 } 1548 1549 static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1550 { 1551 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1552 u32 val32; 1553 1554 if (chip_id == RTL8852C) 1555 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1556 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1557 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1558 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1559 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1560 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1561 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1562 else 1563 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1564 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1565 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1566 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1567 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1568 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1569 B_AX_DMAC_CRPRT); 1570 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1571 1572 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1573 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1574 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1575 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1576 if (chip_id == RTL8852BT) 1577 val32 |= B_AX_AXIDMA_CLK_EN; 1578 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1579 1580 return 0; 1581 } 1582 1583 static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1584 { 1585 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1586 1587 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 1588 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1589 B_AX_OCP_L1_MASK); 1590 1591 return 0; 1592 } 1593 1594 static int sys_init_ax(struct rtw89_dev *rtwdev) 1595 { 1596 int ret; 1597 1598 ret = dmac_func_en_ax(rtwdev); 1599 if (ret) 1600 return ret; 1601 1602 ret = cmac_func_en_ax(rtwdev, 0, true); 1603 if (ret) 1604 return ret; 1605 1606 ret = chip_func_en_ax(rtwdev); 1607 if (ret) 1608 return ret; 1609 1610 return ret; 1611 } 1612 1613 const struct rtw89_mac_size_set rtw89_mac_size = { 1614 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1615 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0}, 1616 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0}, 1617 /* PCIE 64 */ 1618 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1619 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1620 /* DLFW */ 1621 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1622 .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1623 /* PCIE 64 */ 1624 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1625 /* 8852B PCIE SCC */ 1626 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1627 /* DLFW */ 1628 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1629 /* 8852C DLFW */ 1630 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1631 /* 8852C PCIE SCC */ 1632 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1633 .wde_size23 = {RTW89_WDE_PG_64, 1022, 2,}, 1634 /* PCIE */ 1635 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1636 .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1637 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1638 /* DLFW */ 1639 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1640 /* PCIE 64 */ 1641 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1642 /* DLFW */ 1643 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1644 .ple_size9 = {RTW89_PLE_PG_128, 2288, 16,}, 1645 /* 8852C DLFW */ 1646 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1647 /* 8852C PCIE SCC */ 1648 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1649 /* PCIE 64 */ 1650 .wde_qt0 = {3792, 196, 0, 107,}, 1651 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1652 /* DLFW */ 1653 .wde_qt4 = {0, 0, 0, 0,}, 1654 /* PCIE 64 */ 1655 .wde_qt6 = {448, 48, 0, 16,}, 1656 /* 8852B PCIE SCC */ 1657 .wde_qt7 = {446, 48, 0, 16,}, 1658 /* 8852C DLFW */ 1659 .wde_qt17 = {0, 0, 0, 0,}, 1660 /* 8852C PCIE SCC */ 1661 .wde_qt18 = {3228, 60, 0, 40,}, 1662 .wde_qt23 = {958, 48, 0, 16,}, 1663 .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 1664 .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1665 /* PCIE SCC */ 1666 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1667 /* PCIE SCC */ 1668 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1669 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1670 /* DLFW */ 1671 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1672 /* PCIE 64 */ 1673 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1674 /* DLFW 52C */ 1675 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1676 /* DLFW 52C */ 1677 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1678 /* 8852C PCIE SCC */ 1679 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1680 /* 8852C PCIE SCC */ 1681 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1682 .ple_qt57 = {147, 0, 16, 20, 13, 13, 178, 0, 32, 14, 8, 0,}, 1683 /* PCIE 64 */ 1684 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1685 .ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,}, 1686 /* 8852A PCIE WOW */ 1687 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1688 /* 8852B PCIE WOW */ 1689 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1690 /* 8852BT PCIE WOW */ 1691 .ple_qt_52bt_wow = {147, 0, 32, 20, 1860, 13, 1929, 0, 1879, 14, 24, 0,}, 1692 /* 8851B PCIE WOW */ 1693 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1694 .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1695 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1696 .rsvd0_size0 = {212992, 0,}, 1697 .rsvd1_size0 = {587776, 2048,}, 1698 }; 1699 EXPORT_SYMBOL(rtw89_mac_size); 1700 1701 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1702 enum rtw89_qta_mode mode) 1703 { 1704 struct rtw89_mac_info *mac = &rtwdev->mac; 1705 const struct rtw89_dle_mem *cfg; 1706 1707 cfg = &rtwdev->chip->dle_mem[mode]; 1708 if (!cfg) 1709 return NULL; 1710 1711 if (cfg->mode != mode) { 1712 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1713 return NULL; 1714 } 1715 1716 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1717 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1718 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1719 mac->dle_info.qta_mode = mode; 1720 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1721 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1722 1723 return cfg; 1724 } 1725 1726 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1727 enum rtw89_mac_dle_rsvd_qt_type type, 1728 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1729 { 1730 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1731 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1732 1733 switch (type) { 1734 case DLE_RSVD_QT_MPDU_INFO: 1735 cfg->pktid = dle_info->ple_free_pg; 1736 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1737 break; 1738 case DLE_RSVD_QT_B0_CSI: 1739 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1740 cfg->pg_num = rsvd_qt->b0_csi; 1741 break; 1742 case DLE_RSVD_QT_B1_CSI: 1743 cfg->pktid = dle_info->ple_free_pg + 1744 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1745 cfg->pg_num = rsvd_qt->b1_csi; 1746 break; 1747 case DLE_RSVD_QT_B0_LMR: 1748 cfg->pktid = dle_info->ple_free_pg + 1749 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1750 cfg->pg_num = rsvd_qt->b0_lmr; 1751 break; 1752 case DLE_RSVD_QT_B1_LMR: 1753 cfg->pktid = dle_info->ple_free_pg + 1754 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1755 rsvd_qt->b0_lmr; 1756 cfg->pg_num = rsvd_qt->b1_lmr; 1757 break; 1758 case DLE_RSVD_QT_B0_FTM: 1759 cfg->pktid = dle_info->ple_free_pg + 1760 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1761 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1762 cfg->pg_num = rsvd_qt->b0_ftm; 1763 break; 1764 case DLE_RSVD_QT_B1_FTM: 1765 cfg->pktid = dle_info->ple_free_pg + 1766 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1767 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1768 cfg->pg_num = rsvd_qt->b1_ftm; 1769 break; 1770 default: 1771 return -EINVAL; 1772 } 1773 1774 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1775 1776 return 0; 1777 } 1778 1779 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1780 { 1781 struct rtw89_mac_dle_dfi_qempty qempty; 1782 u32 grpnum, qtmp, val32, msk32; 1783 int i, j, ret; 1784 1785 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1786 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1787 1788 for (i = 0; i < grpnum; i++) { 1789 qempty.grpsel = i; 1790 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1791 if (ret) { 1792 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1793 return false; 1794 } 1795 qtmp = qempty.qempty; 1796 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1797 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 1798 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1799 return false; 1800 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1801 } 1802 } 1803 1804 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1805 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1806 if (ret) { 1807 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1808 return false; 1809 } 1810 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1811 if ((qempty.qempty & msk32) != msk32) 1812 return false; 1813 1814 if (rtwdev->dbcc_en) { 1815 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1816 if ((qempty.qempty & msk32) != msk32) 1817 return false; 1818 } 1819 1820 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1821 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1822 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1823 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1824 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1825 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1826 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1827 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1828 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1829 1830 return (val32 & msk32) == msk32; 1831 } 1832 1833 static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1834 { 1835 const struct rtw89_dle_size *wde = cfg->wde_size; 1836 const struct rtw89_dle_size *ple = cfg->ple_size; 1837 u32 used; 1838 1839 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1840 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1841 1842 if (cfg->rsvd0_size && cfg->rsvd1_size) { 1843 used += cfg->rsvd0_size->size; 1844 used += cfg->rsvd1_size->size; 1845 } 1846 1847 return used; 1848 } 1849 1850 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1851 enum rtw89_qta_mode mode) 1852 { 1853 u32 size = rtwdev->chip->fifo_size; 1854 1855 if (mode == RTW89_QTA_SCC) 1856 size -= rtwdev->chip->dle_scc_rsvd_size; 1857 1858 return size; 1859 } 1860 1861 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 1862 { 1863 if (enable) 1864 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1865 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1866 else 1867 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1868 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1869 } 1870 1871 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 1872 { 1873 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1874 1875 if (enable) { 1876 if (rtwdev->chip->chip_id == RTL8851B) 1877 val |= B_AX_AXIDMA_CLK_EN; 1878 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1879 } else { 1880 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1881 } 1882 } 1883 1884 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1885 { 1886 const struct rtw89_dle_size *size_cfg; 1887 u32 val; 1888 u8 bound = 0; 1889 1890 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1891 size_cfg = cfg->wde_size; 1892 1893 switch (size_cfg->pge_size) { 1894 default: 1895 case RTW89_WDE_PG_64: 1896 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1897 B_AX_WDE_PAGE_SEL_MASK); 1898 break; 1899 case RTW89_WDE_PG_128: 1900 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1901 B_AX_WDE_PAGE_SEL_MASK); 1902 break; 1903 case RTW89_WDE_PG_256: 1904 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1905 return -EINVAL; 1906 } 1907 1908 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1909 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1910 B_AX_WDE_FREE_PAGE_NUM_MASK); 1911 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1912 1913 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1914 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1915 * size_cfg->pge_size / DLE_BOUND_UNIT; 1916 size_cfg = cfg->ple_size; 1917 1918 switch (size_cfg->pge_size) { 1919 default: 1920 case RTW89_PLE_PG_64: 1921 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1922 return -EINVAL; 1923 case RTW89_PLE_PG_128: 1924 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1925 B_AX_PLE_PAGE_SEL_MASK); 1926 break; 1927 case RTW89_PLE_PG_256: 1928 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1929 B_AX_PLE_PAGE_SEL_MASK); 1930 break; 1931 } 1932 1933 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1934 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1935 B_AX_PLE_FREE_PAGE_NUM_MASK); 1936 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1937 1938 return 0; 1939 } 1940 1941 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 1942 { 1943 u32 reg, mask; 1944 u32 ini; 1945 1946 if (wde_or_ple) { 1947 reg = R_AX_WDE_INI_STATUS; 1948 mask = WDE_MGN_INI_RDY; 1949 } else { 1950 reg = R_AX_PLE_INI_STATUS; 1951 mask = PLE_MGN_INI_RDY; 1952 } 1953 1954 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 1955 2000, false, rtwdev, reg); 1956 } 1957 1958 #define INVALID_QT_WCPU U16_MAX 1959 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1960 do { \ 1961 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1962 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1963 rtw89_write32(rtwdev, \ 1964 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1965 val); \ 1966 } while (0) 1967 #define SET_QUOTA(_x, _module, _idx) \ 1968 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1969 1970 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 1971 const struct rtw89_wde_quota *min_cfg, 1972 const struct rtw89_wde_quota *max_cfg, 1973 u16 ext_wde_min_qt_wcpu) 1974 { 1975 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1976 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1977 u32 val; 1978 1979 SET_QUOTA(hif, WDE, 0); 1980 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1981 SET_QUOTA(pkt_in, WDE, 3); 1982 SET_QUOTA(cpu_io, WDE, 4); 1983 } 1984 1985 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 1986 const struct rtw89_ple_quota *min_cfg, 1987 const struct rtw89_ple_quota *max_cfg) 1988 { 1989 u32 val; 1990 1991 SET_QUOTA(cma0_tx, PLE, 0); 1992 SET_QUOTA(cma1_tx, PLE, 1); 1993 SET_QUOTA(c2h, PLE, 2); 1994 SET_QUOTA(h2c, PLE, 3); 1995 SET_QUOTA(wcpu, PLE, 4); 1996 SET_QUOTA(mpdu_proc, PLE, 5); 1997 SET_QUOTA(cma0_dma, PLE, 6); 1998 SET_QUOTA(cma1_dma, PLE, 7); 1999 SET_QUOTA(bb_rpt, PLE, 8); 2000 SET_QUOTA(wd_rel, PLE, 9); 2001 SET_QUOTA(cpu_io, PLE, 10); 2002 if (rtwdev->chip->chip_id == RTL8852C) 2003 SET_QUOTA(tx_rpt, PLE, 11); 2004 } 2005 2006 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 2007 { 2008 const struct rtw89_ple_quota *min_cfg, *max_cfg; 2009 const struct rtw89_dle_mem *cfg; 2010 u32 val; 2011 2012 if (rtwdev->chip->chip_id == RTL8852C) 2013 return 0; 2014 2015 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2016 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2017 return -EINVAL; 2018 } 2019 2020 if (wow) 2021 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2022 else 2023 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2024 if (!cfg) { 2025 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2026 return -EINVAL; 2027 } 2028 2029 min_cfg = cfg->ple_min_qt; 2030 max_cfg = cfg->ple_max_qt; 2031 SET_QUOTA(cma0_dma, PLE, 6); 2032 SET_QUOTA(cma1_dma, PLE, 7); 2033 2034 return 0; 2035 } 2036 #undef SET_QUOTA 2037 2038 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2039 { 2040 const struct rtw89_chip_info *chip = rtwdev->chip; 2041 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2042 2043 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2044 return; 2045 2046 /* 8852C enable B_AX_UC_MGNT_DEC by default */ 2047 if (chip->chip_id == RTL8852C) 2048 msk32 = B_AX_BMC_MGNT_DEC; 2049 2050 if (enable) 2051 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2052 else 2053 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2054 } 2055 2056 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2057 const struct rtw89_dle_mem *cfg, 2058 u16 ext_wde_min_qt_wcpu) 2059 { 2060 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2061 2062 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2063 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2064 } 2065 2066 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2067 enum rtw89_qta_mode ext_mode) 2068 { 2069 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2070 const struct rtw89_dle_mem *cfg, *ext_cfg; 2071 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2072 int ret; 2073 2074 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2075 if (ret) 2076 return ret; 2077 2078 cfg = get_dle_mem_cfg(rtwdev, mode); 2079 if (!cfg) { 2080 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2081 ret = -EINVAL; 2082 goto error; 2083 } 2084 2085 if (mode == RTW89_QTA_DLFW) { 2086 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2087 if (!ext_cfg) { 2088 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2089 ext_mode); 2090 ret = -EINVAL; 2091 goto error; 2092 } 2093 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2094 } 2095 2096 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2097 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2098 ret = -EINVAL; 2099 goto error; 2100 } 2101 2102 mac->dle_func_en(rtwdev, false); 2103 mac->dle_clk_en(rtwdev, true); 2104 2105 ret = mac->dle_mix_cfg(rtwdev, cfg); 2106 if (ret) { 2107 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2108 goto error; 2109 } 2110 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2111 2112 mac->dle_func_en(rtwdev, true); 2113 2114 ret = mac->chk_dle_rdy(rtwdev, true); 2115 if (ret) { 2116 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2117 return ret; 2118 } 2119 2120 ret = mac->chk_dle_rdy(rtwdev, false); 2121 if (ret) { 2122 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2123 return ret; 2124 } 2125 2126 return 0; 2127 error: 2128 mac->dle_func_en(rtwdev, false); 2129 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2130 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2131 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2132 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2133 2134 return ret; 2135 } 2136 2137 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2138 enum rtw89_qta_mode mode) 2139 { 2140 u32 reg, max_preld_size, min_rsvd_size; 2141 2142 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2143 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2144 reg = mac_idx == RTW89_MAC_0 ? 2145 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2146 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2147 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2148 2149 min_rsvd_size = PRELD_AMSDU_SIZE; 2150 reg = mac_idx == RTW89_MAC_0 ? 2151 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2152 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2153 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2154 2155 return 0; 2156 } 2157 2158 static bool is_qta_poh(struct rtw89_dev *rtwdev) 2159 { 2160 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2161 } 2162 2163 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2164 enum rtw89_qta_mode mode) 2165 { 2166 const struct rtw89_chip_info *chip = rtwdev->chip; 2167 2168 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) || 2169 !is_qta_poh(rtwdev)) 2170 return 0; 2171 2172 return preload_init_set(rtwdev, mac_idx, mode); 2173 } 2174 2175 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2176 { 2177 u32 msk32; 2178 u32 val32; 2179 2180 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2181 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2182 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2183 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2184 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2185 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2186 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2187 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2188 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2189 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2190 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2191 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2192 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2193 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2194 2195 if ((val32 & msk32) == msk32) 2196 return true; 2197 2198 return false; 2199 } 2200 2201 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2202 { 2203 const struct rtw89_chip_info *chip = rtwdev->chip; 2204 2205 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2206 return; 2207 2208 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2209 SS2F_PATH_WLCPU); 2210 } 2211 2212 static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2213 { 2214 u32 p_val; 2215 u8 val; 2216 int ret; 2217 2218 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2219 if (ret) 2220 return ret; 2221 2222 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2223 val |= B_AX_SS_EN; 2224 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2225 2226 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2227 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2228 if (ret) { 2229 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2230 return ret; 2231 } 2232 2233 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2234 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2235 2236 _patch_ss2f_path(rtwdev); 2237 2238 return 0; 2239 } 2240 2241 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2242 { 2243 int ret; 2244 2245 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2246 if (ret) 2247 return ret; 2248 2249 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2250 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2251 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2252 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2253 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2254 2255 return 0; 2256 } 2257 2258 static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2259 { 2260 const struct rtw89_chip_info *chip = rtwdev->chip; 2261 u32 val = 0; 2262 int ret; 2263 2264 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2265 if (ret) 2266 return ret; 2267 2268 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2269 /* init clock */ 2270 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2271 /* init TX encryption */ 2272 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2273 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2274 if (chip->chip_id == RTL8852C) 2275 val |= B_AX_UC_MGNT_DEC; 2276 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2277 chip->chip_id == RTL8851B) 2278 val &= ~B_AX_TX_PARTIAL_MODE; 2279 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2280 2281 /* init MIC ICV append */ 2282 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2283 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2284 2285 /* option init */ 2286 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2287 2288 if (chip->chip_id == RTL8852C) 2289 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2290 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2291 2292 return 0; 2293 } 2294 2295 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2296 { 2297 int ret; 2298 2299 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2300 if (ret) { 2301 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2302 return ret; 2303 } 2304 2305 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2306 if (ret) { 2307 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2308 return ret; 2309 } 2310 2311 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2312 if (ret) { 2313 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2314 return ret; 2315 } 2316 2317 ret = sta_sch_init_ax(rtwdev); 2318 if (ret) { 2319 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2320 return ret; 2321 } 2322 2323 ret = mpdu_proc_init_ax(rtwdev); 2324 if (ret) { 2325 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2326 return ret; 2327 } 2328 2329 ret = sec_eng_init_ax(rtwdev); 2330 if (ret) { 2331 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2332 return ret; 2333 } 2334 2335 return ret; 2336 } 2337 2338 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2339 { 2340 u32 val, reg; 2341 u16 p_val; 2342 int ret; 2343 2344 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2345 if (ret) 2346 return ret; 2347 2348 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2349 2350 val = rtw89_read32(rtwdev, reg); 2351 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2352 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2353 rtw89_write32(rtwdev, reg, val); 2354 2355 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2356 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2357 if (ret) { 2358 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2359 return ret; 2360 } 2361 2362 return 0; 2363 } 2364 2365 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2366 { 2367 u32 ret; 2368 u32 reg; 2369 u32 val; 2370 2371 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2372 if (ret) 2373 return ret; 2374 2375 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2376 if (rtwdev->chip->chip_id == RTL8852C) 2377 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2378 SIFS_MACTXEN_T1_V1); 2379 else 2380 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2381 SIFS_MACTXEN_T1); 2382 2383 if (rtw89_is_rtl885xb(rtwdev)) { 2384 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2385 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2386 } 2387 2388 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2389 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2390 2391 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2392 if (rtwdev->chip->chip_id == RTL8852C) { 2393 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2394 B_AX_TX_PARTIAL_MODE); 2395 if (!val) 2396 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2397 SCH_PREBKF_24US); 2398 } else { 2399 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2400 SCH_PREBKF_24US); 2401 } 2402 2403 return 0; 2404 } 2405 2406 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2407 enum rtw89_machdr_frame_type type, 2408 enum rtw89_mac_fwd_target fwd_target, 2409 u8 mac_idx) 2410 { 2411 u32 reg; 2412 u32 val; 2413 2414 switch (fwd_target) { 2415 case RTW89_FWD_DONT_CARE: 2416 val = RX_FLTR_FRAME_DROP; 2417 break; 2418 case RTW89_FWD_TO_HOST: 2419 val = RX_FLTR_FRAME_TO_HOST; 2420 break; 2421 case RTW89_FWD_TO_WLAN_CPU: 2422 val = RX_FLTR_FRAME_TO_WLCPU; 2423 break; 2424 default: 2425 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2426 return -EINVAL; 2427 } 2428 2429 switch (type) { 2430 case RTW89_MGNT: 2431 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2432 break; 2433 case RTW89_CTRL: 2434 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2435 break; 2436 case RTW89_DATA: 2437 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2438 break; 2439 default: 2440 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2441 return -EINVAL; 2442 } 2443 rtw89_write32(rtwdev, reg, val); 2444 2445 return 0; 2446 } 2447 2448 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2449 { 2450 int ret, i; 2451 u32 mac_ftlr, plcp_ftlr; 2452 2453 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2454 if (ret) 2455 return ret; 2456 2457 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2458 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2459 mac_idx); 2460 if (ret) 2461 return ret; 2462 } 2463 mac_ftlr = rtwdev->hal.rx_fltr; 2464 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2465 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2466 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2467 B_AX_HE_SIGB_CRC_CHK; 2468 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2469 mac_ftlr); 2470 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2471 plcp_ftlr); 2472 2473 return 0; 2474 } 2475 2476 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2477 { 2478 u32 reg, val32; 2479 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2480 2481 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2482 B_AX_RSP_CHK_BASIC_NAV; 2483 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2484 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2485 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2486 2487 switch (rtwdev->chip->chip_id) { 2488 case RTL8852A: 2489 case RTL8852B: 2490 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2491 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2492 rtw89_write32(rtwdev, reg, val32); 2493 2494 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2495 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2496 rtw89_write32(rtwdev, reg, val32); 2497 break; 2498 default: 2499 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2500 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2501 rtw89_write32(rtwdev, reg, val32); 2502 2503 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2504 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2505 rtw89_write32(rtwdev, reg, val32); 2506 break; 2507 } 2508 } 2509 2510 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2511 { 2512 u32 val, reg; 2513 int ret; 2514 2515 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2516 if (ret) 2517 return ret; 2518 2519 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2520 val = rtw89_read32(rtwdev, reg); 2521 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2522 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2523 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2524 B_AX_CTN_CHK_INTRA_NAV | 2525 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2526 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2527 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2528 B_AX_CTN_CHK_CCA_P20); 2529 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2530 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2531 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2532 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2533 B_AX_SIFS_CHK_EDCCA); 2534 2535 rtw89_write32(rtwdev, reg, val); 2536 2537 _patch_dis_resp_chk(rtwdev, mac_idx); 2538 2539 return 0; 2540 } 2541 2542 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2543 { 2544 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2545 B_AX_WMAC_TF_UP_NAV_EN | 2546 B_AX_WMAC_NAV_UPPER_EN); 2547 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2548 2549 return 0; 2550 } 2551 2552 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2553 { 2554 u32 reg; 2555 int ret; 2556 2557 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2558 if (ret) 2559 return ret; 2560 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2561 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2562 2563 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2564 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2565 2566 return 0; 2567 } 2568 2569 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2570 { 2571 u32 reg; 2572 int ret; 2573 2574 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2575 if (ret) 2576 return ret; 2577 2578 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2579 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2580 2581 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2582 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2583 2584 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2585 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2586 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2587 2588 return 0; 2589 } 2590 2591 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2592 { 2593 const struct rtw89_chip_info *chip = rtwdev->chip; 2594 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2595 u32 reg, val, sifs; 2596 int ret; 2597 2598 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2599 if (ret) 2600 return ret; 2601 2602 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2603 val = rtw89_read32(rtwdev, reg); 2604 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2605 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2606 2607 switch (rtwdev->chip->chip_id) { 2608 case RTL8852A: 2609 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2610 break; 2611 case RTL8851B: 2612 case RTL8852B: 2613 case RTL8852BT: 2614 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2615 break; 2616 default: 2617 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2618 break; 2619 } 2620 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2621 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2622 rtw89_write32(rtwdev, reg, val); 2623 2624 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2625 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2626 2627 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2628 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2629 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2630 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2631 2632 return 0; 2633 } 2634 2635 static void rst_bacam(struct rtw89_dev *rtwdev) 2636 { 2637 u32 val32; 2638 int ret; 2639 2640 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2641 S_AX_BACAM_RST_ALL); 2642 2643 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2644 1, 1000, false, 2645 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2646 if (ret) 2647 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2648 } 2649 2650 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2651 { 2652 #define TRXCFG_RMAC_CCA_TO 32 2653 #define TRXCFG_RMAC_DATA_TO 15 2654 #define RX_MAX_LEN_UNIT 512 2655 #define PLD_RLS_MAX_PG 127 2656 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2657 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2658 int ret; 2659 u32 reg, rx_max_len, rx_qta; 2660 u16 val; 2661 2662 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2663 if (ret) 2664 return ret; 2665 2666 if (mac_idx == RTW89_MAC_0) 2667 rst_bacam(rtwdev); 2668 2669 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2670 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2671 2672 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2673 val = rtw89_read16(rtwdev, reg); 2674 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2675 B_AX_RX_DLK_DATA_TIME_MASK); 2676 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2677 B_AX_RX_DLK_CCA_TIME_MASK); 2678 if (chip_id == RTL8852BT) 2679 val |= B_AX_RX_DLK_RST_EN; 2680 rtw89_write16(rtwdev, reg, val); 2681 2682 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2683 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2684 2685 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2686 if (mac_idx == RTW89_MAC_0) 2687 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2688 else 2689 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2690 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2691 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2692 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2693 rx_max_len /= RX_MAX_LEN_UNIT; 2694 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2695 2696 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) { 2697 rtw89_write16_mask(rtwdev, 2698 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2699 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2700 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2701 BIT(12)); 2702 } 2703 2704 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2705 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2706 2707 return ret; 2708 } 2709 2710 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2711 { 2712 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2713 u32 val, reg; 2714 int ret; 2715 2716 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2717 if (ret) 2718 return ret; 2719 2720 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2721 val = rtw89_read32(rtwdev, reg); 2722 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2723 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2724 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2725 rtw89_write32(rtwdev, reg, val); 2726 2727 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2728 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2729 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2730 } 2731 2732 return 0; 2733 } 2734 2735 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2736 { 2737 const struct rtw89_dle_mem *cfg; 2738 2739 cfg = get_dle_mem_cfg(rtwdev, mode); 2740 if (!cfg) { 2741 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2742 return false; 2743 } 2744 2745 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2746 } 2747 2748 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2749 { 2750 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2751 u32 val, reg; 2752 int ret; 2753 2754 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2755 if (ret) 2756 return ret; 2757 2758 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2759 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2760 val = rtw89_read32(rtwdev, reg); 2761 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2762 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2763 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2764 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2765 val |= B_AX_HW_CTS2SELF_EN; 2766 rtw89_write32(rtwdev, reg, val); 2767 2768 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2769 val = rtw89_read32(rtwdev, reg); 2770 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2771 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2772 rtw89_write32(rtwdev, reg, val); 2773 } 2774 2775 if (mac_idx == RTW89_MAC_0) { 2776 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2777 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2778 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2779 B_AX_PTCL_TRIGGER_SS_EN_0 | 2780 B_AX_PTCL_TRIGGER_SS_EN_1 | 2781 B_AX_PTCL_TRIGGER_SS_EN_UL); 2782 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2783 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2784 } else if (mac_idx == RTW89_MAC_1) { 2785 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2786 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2787 } 2788 2789 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2790 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_VHT_0, mac_idx); 2791 rtw89_write32_mask(rtwdev, reg, 2792 B_AX_AMPDU_MAX_LEN_VHT_MASK, 0x3FF80); 2793 } 2794 2795 return 0; 2796 } 2797 2798 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2799 { 2800 u32 reg; 2801 int ret; 2802 2803 if (!rtw89_is_rtl885xb(rtwdev)) 2804 return 0; 2805 2806 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2807 if (ret) 2808 return ret; 2809 2810 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2811 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2812 2813 return 0; 2814 } 2815 2816 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2817 { 2818 int ret; 2819 2820 ret = scheduler_init_ax(rtwdev, mac_idx); 2821 if (ret) { 2822 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2823 return ret; 2824 } 2825 2826 ret = addr_cam_init_ax(rtwdev, mac_idx); 2827 if (ret) { 2828 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2829 ret); 2830 return ret; 2831 } 2832 2833 ret = rx_fltr_init_ax(rtwdev, mac_idx); 2834 if (ret) { 2835 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2836 ret); 2837 return ret; 2838 } 2839 2840 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 2841 if (ret) { 2842 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2843 ret); 2844 return ret; 2845 } 2846 2847 ret = nav_ctrl_init_ax(rtwdev); 2848 if (ret) { 2849 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2850 ret); 2851 return ret; 2852 } 2853 2854 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 2855 if (ret) { 2856 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2857 mac_idx, ret); 2858 return ret; 2859 } 2860 2861 ret = tmac_init_ax(rtwdev, mac_idx); 2862 if (ret) { 2863 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2864 return ret; 2865 } 2866 2867 ret = trxptcl_init_ax(rtwdev, mac_idx); 2868 if (ret) { 2869 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2870 return ret; 2871 } 2872 2873 ret = rmac_init_ax(rtwdev, mac_idx); 2874 if (ret) { 2875 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2876 return ret; 2877 } 2878 2879 ret = cmac_com_init_ax(rtwdev, mac_idx); 2880 if (ret) { 2881 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2882 return ret; 2883 } 2884 2885 ret = ptcl_init_ax(rtwdev, mac_idx); 2886 if (ret) { 2887 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2888 return ret; 2889 } 2890 2891 ret = cmac_dma_init_ax(rtwdev, mac_idx); 2892 if (ret) { 2893 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2894 return ret; 2895 } 2896 2897 return ret; 2898 } 2899 2900 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2901 struct rtw89_mac_c2h_info *c2h_info) 2902 { 2903 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2904 struct rtw89_mac_h2c_info h2c_info = {0}; 2905 u32 ret; 2906 2907 mac->cnv_efuse_state(rtwdev, false); 2908 2909 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2910 h2c_info.content_len = 0; 2911 2912 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2913 if (ret) 2914 goto out; 2915 2916 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2917 ret = -EINVAL; 2918 2919 out: 2920 mac->cnv_efuse_state(rtwdev, true); 2921 2922 return ret; 2923 } 2924 2925 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2926 { 2927 struct rtw89_efuse *efuse = &rtwdev->efuse; 2928 struct rtw89_hal *hal = &rtwdev->hal; 2929 const struct rtw89_chip_info *chip = rtwdev->chip; 2930 struct rtw89_mac_c2h_info c2h_info = {0}; 2931 const struct rtw89_c2hreg_phycap *phycap; 2932 u8 tx_nss; 2933 u8 rx_nss; 2934 u8 tx_ant; 2935 u8 rx_ant; 2936 u32 ret; 2937 2938 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2939 if (ret) 2940 return ret; 2941 2942 phycap = &c2h_info.u.phycap; 2943 2944 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 2945 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 2946 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 2947 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2948 2949 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2950 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2951 2952 if (tx_ant == 1) 2953 hal->antenna_tx = RF_B; 2954 if (rx_ant == 1) 2955 hal->antenna_rx = RF_B; 2956 2957 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2958 hal->antenna_tx = RF_B; 2959 hal->tx_path_diversity = true; 2960 } 2961 2962 if (chip->rf_path_num == 1) { 2963 hal->antenna_tx = RF_A; 2964 hal->antenna_rx = RF_A; 2965 if ((efuse->rfe_type % 3) == 2) 2966 hal->ant_diversity = true; 2967 } 2968 2969 rtw89_debug(rtwdev, RTW89_DBG_FW, 2970 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2971 hal->tx_nss, tx_nss, chip->tx_nss, 2972 hal->rx_nss, rx_nss, chip->rx_nss); 2973 rtw89_debug(rtwdev, RTW89_DBG_FW, 2974 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2975 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2976 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2977 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2978 2979 return 0; 2980 } 2981 2982 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2983 u16 tx_en_u16, u16 mask_u16) 2984 { 2985 u32 ret; 2986 struct rtw89_mac_c2h_info c2h_info = {0}; 2987 struct rtw89_mac_h2c_info h2c_info = {0}; 2988 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 2989 2990 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2991 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 2992 2993 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 2994 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 2995 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 2996 2997 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2998 if (ret) 2999 return ret; 3000 3001 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 3002 return -EINVAL; 3003 3004 return 0; 3005 } 3006 3007 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 3008 u16 tx_en, u16 tx_en_mask) 3009 { 3010 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 3011 u16 val; 3012 int ret; 3013 3014 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3015 if (ret) 3016 return ret; 3017 3018 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3019 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 3020 tx_en, tx_en_mask); 3021 3022 val = rtw89_read16(rtwdev, reg); 3023 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3024 rtw89_write16(rtwdev, reg, val); 3025 3026 return 0; 3027 } 3028 3029 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3030 u32 tx_en, u32 tx_en_mask) 3031 { 3032 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3033 u32 val; 3034 int ret; 3035 3036 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3037 if (ret) 3038 return ret; 3039 3040 val = rtw89_read32(rtwdev, reg); 3041 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3042 rtw89_write32(rtwdev, reg, val); 3043 3044 return 0; 3045 } 3046 3047 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3048 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3049 { 3050 int ret; 3051 3052 *tx_en = rtw89_read16(rtwdev, 3053 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3054 3055 switch (sel) { 3056 case RTW89_SCH_TX_SEL_ALL: 3057 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3058 B_AX_CTN_TXEN_ALL_MASK); 3059 if (ret) 3060 return ret; 3061 break; 3062 case RTW89_SCH_TX_SEL_HIQ: 3063 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3064 0, B_AX_CTN_TXEN_HGQ); 3065 if (ret) 3066 return ret; 3067 break; 3068 case RTW89_SCH_TX_SEL_MG0: 3069 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3070 0, B_AX_CTN_TXEN_MGQ); 3071 if (ret) 3072 return ret; 3073 break; 3074 case RTW89_SCH_TX_SEL_MACID: 3075 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3076 B_AX_CTN_TXEN_ALL_MASK); 3077 if (ret) 3078 return ret; 3079 break; 3080 default: 3081 return 0; 3082 } 3083 3084 return 0; 3085 } 3086 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3087 3088 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3089 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3090 { 3091 int ret; 3092 3093 *tx_en = rtw89_read32(rtwdev, 3094 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3095 3096 switch (sel) { 3097 case RTW89_SCH_TX_SEL_ALL: 3098 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3099 B_AX_CTN_TXEN_ALL_MASK_V1); 3100 if (ret) 3101 return ret; 3102 break; 3103 case RTW89_SCH_TX_SEL_HIQ: 3104 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3105 0, B_AX_CTN_TXEN_HGQ); 3106 if (ret) 3107 return ret; 3108 break; 3109 case RTW89_SCH_TX_SEL_MG0: 3110 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3111 0, B_AX_CTN_TXEN_MGQ); 3112 if (ret) 3113 return ret; 3114 break; 3115 case RTW89_SCH_TX_SEL_MACID: 3116 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3117 B_AX_CTN_TXEN_ALL_MASK_V1); 3118 if (ret) 3119 return ret; 3120 break; 3121 default: 3122 return 0; 3123 } 3124 3125 return 0; 3126 } 3127 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3128 3129 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3130 { 3131 int ret; 3132 3133 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3134 if (ret) 3135 return ret; 3136 3137 return 0; 3138 } 3139 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3140 3141 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3142 { 3143 int ret; 3144 3145 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3146 B_AX_CTN_TXEN_ALL_MASK_V1); 3147 if (ret) 3148 return ret; 3149 3150 return 0; 3151 } 3152 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3153 3154 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3155 { 3156 u32 val, reg; 3157 int ret; 3158 3159 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3160 val = buf_len; 3161 val |= B_AX_WD_BUF_REQ_EXEC; 3162 rtw89_write32(rtwdev, reg, val); 3163 3164 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3165 3166 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3167 1, 2000, false, rtwdev, reg); 3168 if (ret) 3169 return ret; 3170 3171 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3172 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3173 return -ENOENT; 3174 3175 return 0; 3176 } 3177 3178 static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3179 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3180 { 3181 u32 val, cmd_type, reg; 3182 int ret; 3183 3184 cmd_type = ctrl_para->cmd_type; 3185 3186 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3187 val = 0; 3188 val = u32_replace_bits(val, ctrl_para->start_pktid, 3189 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3190 val = u32_replace_bits(val, ctrl_para->end_pktid, 3191 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3192 rtw89_write32(rtwdev, reg, val); 3193 3194 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3195 val = 0; 3196 val = u32_replace_bits(val, ctrl_para->src_pid, 3197 B_AX_CPUQ_OP_SRC_PID_MASK); 3198 val = u32_replace_bits(val, ctrl_para->src_qid, 3199 B_AX_CPUQ_OP_SRC_QID_MASK); 3200 val = u32_replace_bits(val, ctrl_para->dst_pid, 3201 B_AX_CPUQ_OP_DST_PID_MASK); 3202 val = u32_replace_bits(val, ctrl_para->dst_qid, 3203 B_AX_CPUQ_OP_DST_QID_MASK); 3204 rtw89_write32(rtwdev, reg, val); 3205 3206 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3207 val = 0; 3208 val = u32_replace_bits(val, cmd_type, 3209 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3210 val = u32_replace_bits(val, ctrl_para->macid, 3211 B_AX_CPUQ_OP_MACID_MASK); 3212 val = u32_replace_bits(val, ctrl_para->pkt_num, 3213 B_AX_CPUQ_OP_PKTNUM_MASK); 3214 val |= B_AX_WD_CPUQ_OP_EXEC; 3215 rtw89_write32(rtwdev, reg, val); 3216 3217 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3218 3219 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3220 1, 2000, false, rtwdev, reg); 3221 if (ret) 3222 return ret; 3223 3224 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3225 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3226 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3227 3228 return 0; 3229 } 3230 3231 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3232 bool band1_en) 3233 { 3234 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3235 const struct rtw89_dle_mem *cfg; 3236 3237 cfg = get_dle_mem_cfg(rtwdev, mode); 3238 if (!cfg) { 3239 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3240 return -EINVAL; 3241 } 3242 3243 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3244 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3245 return -EINVAL; 3246 } 3247 3248 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3249 3250 return mac->dle_quota_change(rtwdev, band1_en); 3251 } 3252 3253 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3254 { 3255 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3256 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3257 u16 pkt_id; 3258 int ret; 3259 3260 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3261 if (ret) { 3262 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3263 return ret; 3264 } 3265 3266 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3267 ctrl_para.start_pktid = pkt_id; 3268 ctrl_para.end_pktid = pkt_id; 3269 ctrl_para.pkt_num = 0; 3270 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3271 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3272 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3273 if (ret) { 3274 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3275 return -EFAULT; 3276 } 3277 3278 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3279 if (ret) { 3280 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3281 return ret; 3282 } 3283 3284 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3285 ctrl_para.start_pktid = pkt_id; 3286 ctrl_para.end_pktid = pkt_id; 3287 ctrl_para.pkt_num = 0; 3288 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3289 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3290 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3291 if (ret) { 3292 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3293 return -EFAULT; 3294 } 3295 3296 return 0; 3297 } 3298 3299 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3300 { 3301 int ret; 3302 u32 reg; 3303 u8 val; 3304 3305 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3306 if (ret) 3307 return ret; 3308 3309 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3310 3311 ret = read_poll_timeout(rtw89_read8, val, 3312 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3313 SW_CVR_DUR_US, 3314 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3315 false, rtwdev, reg); 3316 if (ret) 3317 return ret; 3318 3319 return 0; 3320 } 3321 3322 static int band1_enable_ax(struct rtw89_dev *rtwdev) 3323 { 3324 int ret, i; 3325 u32 sleep_bak[4] = {0}; 3326 u32 pause_bak[4] = {0}; 3327 u32 tx_en; 3328 3329 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3330 if (ret) { 3331 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3332 return ret; 3333 } 3334 3335 for (i = 0; i < 4; i++) { 3336 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3337 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3338 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3339 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3340 } 3341 3342 ret = band_idle_ck_b(rtwdev, 0); 3343 if (ret) { 3344 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3345 return ret; 3346 } 3347 3348 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3349 if (ret) { 3350 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3351 return ret; 3352 } 3353 3354 for (i = 0; i < 4; i++) { 3355 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3356 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3357 } 3358 3359 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3360 if (ret) { 3361 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3362 return ret; 3363 } 3364 3365 ret = cmac_func_en_ax(rtwdev, 1, true); 3366 if (ret) { 3367 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3368 return ret; 3369 } 3370 3371 ret = cmac_init_ax(rtwdev, 1); 3372 if (ret) { 3373 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3374 return ret; 3375 } 3376 3377 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3378 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3379 3380 return 0; 3381 } 3382 3383 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3384 { 3385 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3386 3387 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3388 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3389 } 3390 3391 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3392 { 3393 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3394 3395 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3396 } 3397 3398 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3399 { 3400 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3401 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3402 3403 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3404 B_AX_TX_GET_ERRPKTID_INT_EN | 3405 B_AX_TX_NXT_ERRPKTID_INT_EN | 3406 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3407 B_AX_TX_OFFSET_ERR_INT_EN | 3408 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3409 if (chip_id == RTL8852C) 3410 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3411 B_AX_TX_ETH_TYPE_ERR_EN | 3412 B_AX_TX_LLC_PRE_ERR_EN | 3413 B_AX_TX_NW_TYPE_ERR_EN | 3414 B_AX_TX_KSRCH_ERR_EN); 3415 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3416 imr->mpdu_tx_imr_set); 3417 3418 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3419 B_AX_GETPKTID_ERR_INT_EN | 3420 B_AX_MHDRLEN_ERR_INT_EN | 3421 B_AX_RPT_ERR_INT_EN); 3422 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3423 imr->mpdu_rx_imr_set); 3424 } 3425 3426 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3427 { 3428 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3429 3430 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3431 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3432 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3433 B_AX_PLE_B_PKTID_ERR_INT_EN); 3434 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3435 imr->sta_sch_imr_set); 3436 } 3437 3438 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3439 { 3440 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3441 3442 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3443 imr->txpktctl_imr_b0_clr); 3444 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3445 imr->txpktctl_imr_b0_set); 3446 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3447 imr->txpktctl_imr_b1_clr); 3448 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3449 imr->txpktctl_imr_b1_set); 3450 } 3451 3452 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3453 { 3454 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3455 3456 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3457 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3458 } 3459 3460 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3461 { 3462 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3463 3464 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3465 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3466 } 3467 3468 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3469 { 3470 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3471 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3472 } 3473 3474 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3475 { 3476 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3477 3478 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3479 imr->host_disp_imr_clr); 3480 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3481 imr->host_disp_imr_set); 3482 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3483 imr->cpu_disp_imr_clr); 3484 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3485 imr->cpu_disp_imr_set); 3486 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3487 imr->other_disp_imr_clr); 3488 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3489 imr->other_disp_imr_set); 3490 } 3491 3492 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3493 { 3494 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3495 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3496 } 3497 3498 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3499 { 3500 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3501 3502 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3503 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3504 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3505 B_AX_BBRPT_CHINFO_IMR_CLR); 3506 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3507 imr->bbrpt_err_imr_set); 3508 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3509 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3510 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3511 } 3512 3513 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3514 { 3515 u32 reg; 3516 3517 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3518 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3519 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3520 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3521 } 3522 3523 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3524 { 3525 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3526 u32 reg; 3527 3528 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3529 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3530 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3531 } 3532 3533 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3534 { 3535 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3536 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3537 u32 reg; 3538 3539 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3540 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3541 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3542 3543 if (chip_id == RTL8852C) { 3544 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3545 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3546 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3547 } 3548 } 3549 3550 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3551 { 3552 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3553 u32 reg; 3554 3555 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3556 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3557 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3558 } 3559 3560 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3561 { 3562 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3563 u32 reg; 3564 3565 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3566 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3567 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3568 } 3569 3570 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3571 { 3572 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3573 u32 reg; 3574 3575 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3576 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3577 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3578 } 3579 3580 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3581 enum rtw89_mac_hwmod_sel sel) 3582 { 3583 int ret; 3584 3585 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3586 if (ret) { 3587 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3588 sel, mac_idx); 3589 return ret; 3590 } 3591 3592 if (sel == RTW89_DMAC_SEL) { 3593 rtw89_wdrls_imr_enable(rtwdev); 3594 rtw89_wsec_imr_enable(rtwdev); 3595 rtw89_mpdu_trx_imr_enable(rtwdev); 3596 rtw89_sta_sch_imr_enable(rtwdev); 3597 rtw89_txpktctl_imr_enable(rtwdev); 3598 rtw89_wde_imr_enable(rtwdev); 3599 rtw89_ple_imr_enable(rtwdev); 3600 rtw89_pktin_imr_enable(rtwdev); 3601 rtw89_dispatcher_imr_enable(rtwdev); 3602 rtw89_cpuio_imr_enable(rtwdev); 3603 rtw89_bbrpt_imr_enable(rtwdev); 3604 } else if (sel == RTW89_CMAC_SEL) { 3605 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3606 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3607 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3608 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3609 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3610 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3611 } else { 3612 return -EINVAL; 3613 } 3614 3615 return 0; 3616 } 3617 3618 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3619 { 3620 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3621 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3622 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3623 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3624 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta) 3625 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3626 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3627 } 3628 3629 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3630 { 3631 int ret = 0; 3632 3633 if (enable) { 3634 ret = band1_enable_ax(rtwdev); 3635 if (ret) { 3636 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3637 return ret; 3638 } 3639 3640 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3641 if (ret) { 3642 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3643 return ret; 3644 } 3645 } else { 3646 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3647 return -EINVAL; 3648 } 3649 3650 return 0; 3651 } 3652 3653 static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3654 { 3655 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3656 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3657 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3658 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3659 B_AX_RLSRPT0_FLTR_MAP_MASK); 3660 } else { 3661 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3662 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3663 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3664 B_AX_RLSRPT0_FLTR_MAP_MASK); 3665 } 3666 3667 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3668 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3669 3670 return 0; 3671 } 3672 3673 static int trx_init_ax(struct rtw89_dev *rtwdev) 3674 { 3675 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3676 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3677 int ret; 3678 3679 ret = dmac_init_ax(rtwdev, 0); 3680 if (ret) { 3681 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3682 return ret; 3683 } 3684 3685 ret = cmac_init_ax(rtwdev, 0); 3686 if (ret) { 3687 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3688 return ret; 3689 } 3690 3691 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3692 ret = dbcc_enable_ax(rtwdev, true); 3693 if (ret) { 3694 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3695 return ret; 3696 } 3697 } 3698 3699 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3700 if (ret) { 3701 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3702 return ret; 3703 } 3704 3705 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3706 if (ret) { 3707 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3708 return ret; 3709 } 3710 3711 err_imr_ctrl_ax(rtwdev, true); 3712 3713 ret = set_host_rpr_ax(rtwdev); 3714 if (ret) { 3715 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3716 return ret; 3717 } 3718 3719 if (chip_id == RTL8852C) 3720 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG, 3721 B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN); 3722 3723 return 0; 3724 } 3725 3726 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 3727 { 3728 #define BACAM_1024BMP_OCC_ENTRY 4 3729 #define BACAM_MAX_RU_SUPPORT_B0_STA 1 3730 #define BACAM_MAX_RU_SUPPORT_B1_STA 1 3731 const struct rtw89_chip_info *chip = rtwdev->chip; 3732 u8 users, offset; 3733 3734 if (chip->bacam_ver != RTW89_BACAM_V1) 3735 return 0; 3736 3737 offset = 0; 3738 users = BACAM_MAX_RU_SUPPORT_B0_STA; 3739 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 3740 3741 offset += users * BACAM_1024BMP_OCC_ENTRY; 3742 users = BACAM_MAX_RU_SUPPORT_B1_STA; 3743 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 3744 3745 return 0; 3746 } 3747 3748 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3749 { 3750 u32 val32; 3751 3752 if (rtw89_is_rtl885xb(rtwdev)) { 3753 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3754 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3755 return; 3756 } 3757 3758 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3759 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3760 3761 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3762 val32 |= B_AX_FS_WDT_INT; 3763 val32 &= ~B_AX_FS_WDT_INT_MSK; 3764 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3765 } 3766 3767 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3768 { 3769 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3770 3771 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3772 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3773 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3774 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3775 3776 rtw89_disable_fw_watchdog(rtwdev); 3777 3778 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3779 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3780 } 3781 3782 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3783 bool dlfw, bool include_bb) 3784 { 3785 u32 val; 3786 int ret; 3787 3788 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3789 return -EFAULT; 3790 3791 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3792 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3793 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3794 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3795 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3796 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3797 3798 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3799 3800 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3801 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3802 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3803 B_AX_WCPU_FWDL_STS_MASK); 3804 3805 if (dlfw) 3806 val |= B_AX_WCPU_FWDL_EN; 3807 3808 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3809 3810 if (rtw89_is_rtl885xb(rtwdev)) 3811 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3812 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3813 3814 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3815 boot_reason); 3816 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3817 3818 if (!dlfw) { 3819 mdelay(5); 3820 3821 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3822 if (ret) 3823 return ret; 3824 } 3825 3826 return 0; 3827 } 3828 3829 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 3830 { 3831 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3832 u32 val; 3833 3834 if (chip_id == RTL8852C) 3835 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3836 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3837 else 3838 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3839 B_AX_PKT_BUF_EN; 3840 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3841 } 3842 3843 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 3844 { 3845 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3846 u32 val; 3847 3848 if (chip_id == RTL8851B || chip_id == RTL8852BT) 3849 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3850 else 3851 val = B_AX_DISPATCHER_CLK_EN; 3852 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3853 3854 if (chip_id != RTL8852C) 3855 return; 3856 3857 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3858 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3859 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3860 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3861 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3862 3863 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3864 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3865 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3866 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3867 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3868 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3869 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3870 } 3871 3872 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3873 { 3874 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3875 int ret; 3876 3877 mac->hci_func_en(rtwdev); 3878 mac->dmac_func_pre_en(rtwdev); 3879 3880 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3881 if (ret) { 3882 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3883 return ret; 3884 } 3885 3886 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 3887 if (ret) { 3888 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3889 return ret; 3890 } 3891 3892 return ret; 3893 } 3894 3895 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3896 { 3897 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3898 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3899 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3900 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3901 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3902 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3903 3904 return 0; 3905 } 3906 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3907 3908 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3909 { 3910 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3911 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3912 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3913 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3914 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3915 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3916 3917 return 0; 3918 } 3919 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3920 3921 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 3922 { 3923 int ret; 3924 3925 ret = rtw89_mac_power_switch(rtwdev, true); 3926 if (ret) { 3927 rtw89_mac_power_switch(rtwdev, false); 3928 ret = rtw89_mac_power_switch(rtwdev, true); 3929 if (ret) 3930 return ret; 3931 } 3932 3933 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3934 3935 if (include_bb) { 3936 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 3937 if (rtwdev->dbcc_en) 3938 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 3939 } 3940 3941 ret = rtw89_mac_dmac_pre_init(rtwdev); 3942 if (ret) 3943 return ret; 3944 3945 if (rtwdev->hci.ops->mac_pre_init) { 3946 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3947 if (ret) 3948 return ret; 3949 } 3950 3951 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 3952 if (ret) 3953 return ret; 3954 3955 return 0; 3956 } 3957 3958 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3959 { 3960 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3961 const struct rtw89_chip_info *chip = rtwdev->chip; 3962 bool include_bb = !!chip->bbmcu_nr; 3963 int ret; 3964 3965 ret = rtw89_mac_partial_init(rtwdev, include_bb); 3966 if (ret) 3967 goto fail; 3968 3969 ret = rtw89_chip_enable_bb_rf(rtwdev); 3970 if (ret) 3971 goto fail; 3972 3973 ret = mac->sys_init(rtwdev); 3974 if (ret) 3975 goto fail; 3976 3977 ret = mac->trx_init(rtwdev); 3978 if (ret) 3979 goto fail; 3980 3981 ret = rtw89_mac_feat_init(rtwdev); 3982 if (ret) 3983 goto fail; 3984 3985 if (rtwdev->hci.ops->mac_post_init) { 3986 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3987 if (ret) 3988 goto fail; 3989 } 3990 3991 rtw89_fw_send_all_early_h2c(rtwdev); 3992 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3993 3994 return ret; 3995 fail: 3996 rtw89_mac_power_switch(rtwdev, false); 3997 3998 return ret; 3999 } 4000 4001 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4002 { 4003 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4004 u8 i; 4005 4006 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4007 return; 4008 4009 for (i = 0; i < 4; i++) { 4010 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4011 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 4012 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 4013 } 4014 } 4015 4016 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4017 { 4018 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4019 4020 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4021 return; 4022 4023 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4024 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 4025 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 4026 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 4027 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 4028 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 4029 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 4030 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 4031 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 4032 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 4033 } 4034 4035 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4036 { 4037 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4038 u8 grp = macid >> 5; 4039 int ret; 4040 4041 /* If this is called by change_interface() in the case of P2P, it could 4042 * be power-off, so ignore this operation. 4043 */ 4044 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4045 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4046 return 0; 4047 4048 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4049 if (ret) 4050 return ret; 4051 4052 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4053 4054 return 0; 4055 } 4056 4057 static const struct rtw89_port_reg rtw89_port_base_ax = { 4058 .port_cfg = R_AX_PORT_CFG_P0, 4059 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4060 .bcn_area = R_AX_BCN_AREA_P0, 4061 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4062 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4063 .tbtt_agg = R_AX_TBTT_AGG_P0, 4064 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4065 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4066 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4067 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4068 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4069 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4070 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4071 .tsftr_l = R_AX_TSFTR_LOW_P0, 4072 .tsftr_h = R_AX_TSFTR_HIGH_P0, 4073 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 4074 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4075 .mbssid = R_AX_MBSSID_CTRL, 4076 .mbssid_drop = R_AX_MBSSID_DROP_0, 4077 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4078 .ptcl_dbg = R_AX_PTCL_DBG, 4079 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4080 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4081 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4082 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4083 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4084 }; 4085 4086 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4087 struct rtw89_vif_link *rtwvif_link, u8 type) 4088 { 4089 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4090 const struct rtw89_port_reg *p = mac->port_base; 4091 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif_link->port); 4092 u32 reg_info, reg_ctrl; 4093 u32 val; 4094 int ret; 4095 4096 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif_link->mac_idx); 4097 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif_link->mac_idx); 4098 4099 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4100 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4101 fsleep(100); 4102 4103 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4104 true, rtwdev, reg_info, mask); 4105 if (ret) 4106 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4107 } 4108 4109 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, 4110 struct rtw89_vif_link *rtwvif_link) 4111 { 4112 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4113 const struct rtw89_port_reg *p = mac->port_base; 4114 4115 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4116 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 4117 1); 4118 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 4119 0); 4120 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 4121 0); 4122 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4123 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4124 B_AX_TBTTERLY_MASK, 1); 4125 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, 4126 B_AX_BCN_SPACE_MASK, 1); 4127 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4128 4129 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM0); 4130 if (rtwvif_link->port == RTW89_PORT_0) 4131 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM1); 4132 4133 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4134 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4135 fsleep(2000); 4136 } 4137 4138 #define BCN_INTERVAL 100 4139 #define BCN_ERLY_DEF 160 4140 #define BCN_SETUP_DEF 2 4141 #define BCN_HOLD_DEF 200 4142 #define BCN_MASK_DEF 0 4143 #define TBTT_ERLY_DEF 5 4144 #define BCN_SET_UNIT 32 4145 #define BCN_ERLY_SET_DLY (10 * 2) 4146 4147 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4148 struct rtw89_vif_link *rtwvif_link) 4149 { 4150 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4151 const struct rtw89_port_reg *p = mac->port_base; 4152 const struct rtw89_chip_info *chip = rtwdev->chip; 4153 struct ieee80211_bss_conf *bss_conf; 4154 bool need_backup = false; 4155 u32 backup_val; 4156 u16 beacon_int; 4157 4158 if (!rtw89_read32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN)) 4159 return; 4160 4161 if (chip->chip_id == RTL8852A && rtwvif_link->port != RTW89_PORT_0) { 4162 need_backup = true; 4163 backup_val = rtw89_read32_port(rtwdev, rtwvif_link, p->tbtt_prohib); 4164 } 4165 4166 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4167 rtw89_mac_bcn_drop(rtwdev, rtwvif_link); 4168 4169 if (chip->chip_id == RTL8852A) { 4170 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->tbtt_prohib, 4171 B_AX_TBTT_SETUP_MASK); 4172 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4173 B_AX_TBTT_HOLD_MASK, 1); 4174 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->tbtt_early, 4175 B_AX_TBTTERLY_MASK); 4176 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->bcn_early, 4177 B_AX_BCNERLY_MASK); 4178 } 4179 4180 rcu_read_lock(); 4181 4182 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4183 beacon_int = bss_conf->beacon_int; 4184 4185 rcu_read_unlock(); 4186 4187 msleep(beacon_int + 1); 4188 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN | 4189 B_AX_BRK_SETUP); 4190 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSFTR_RST); 4191 rtw89_write32_port(rtwdev, rtwvif_link, p->bcn_cnt_tmr, 0); 4192 4193 if (need_backup) 4194 rtw89_write32_port(rtwdev, rtwvif_link, p->tbtt_prohib, backup_val); 4195 } 4196 4197 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4198 struct rtw89_vif_link *rtwvif_link, bool en) 4199 { 4200 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4201 const struct rtw89_port_reg *p = mac->port_base; 4202 4203 if (en) 4204 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4205 B_AX_TXBCN_RPT_EN); 4206 else 4207 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4208 B_AX_TXBCN_RPT_EN); 4209 } 4210 4211 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4212 struct rtw89_vif_link *rtwvif_link, bool en) 4213 { 4214 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4215 const struct rtw89_port_reg *p = mac->port_base; 4216 4217 if (en) 4218 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4219 B_AX_RXBCN_RPT_EN); 4220 else 4221 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4222 B_AX_RXBCN_RPT_EN); 4223 } 4224 4225 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4226 struct rtw89_vif_link *rtwvif_link) 4227 { 4228 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4229 const struct rtw89_port_reg *p = mac->port_base; 4230 4231 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_NET_TYPE_MASK, 4232 rtwvif_link->net_type); 4233 } 4234 4235 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4236 struct rtw89_vif_link *rtwvif_link) 4237 { 4238 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4239 const struct rtw89_port_reg *p = mac->port_base; 4240 bool en = rtwvif_link->net_type != RTW89_NET_TYPE_NO_LINK; 4241 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4242 4243 if (en) 4244 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bits); 4245 else 4246 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bits); 4247 } 4248 4249 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4250 struct rtw89_vif_link *rtwvif_link) 4251 { 4252 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4253 const struct rtw89_port_reg *p = mac->port_base; 4254 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4255 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4256 u32 bit = B_AX_RX_BSSID_FIT_EN; 4257 4258 if (en) 4259 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bit); 4260 else 4261 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bit); 4262 } 4263 4264 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4265 struct rtw89_vif_link *rtwvif_link, bool en) 4266 { 4267 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4268 const struct rtw89_port_reg *p = mac->port_base; 4269 4270 if (en) 4271 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4272 else 4273 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4274 } 4275 4276 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4277 struct rtw89_vif_link *rtwvif_link) 4278 { 4279 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4280 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4281 4282 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif_link, en); 4283 } 4284 4285 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4286 struct rtw89_vif_link *rtwvif_link, bool en) 4287 { 4288 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4289 const struct rtw89_port_reg *p = mac->port_base; 4290 4291 if (en) 4292 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4293 else 4294 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4295 } 4296 4297 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4298 struct rtw89_vif_link *rtwvif_link) 4299 { 4300 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || 4301 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4302 4303 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4304 } 4305 4306 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4307 { 4308 struct rtw89_vif_link *rtwvif_link; 4309 struct rtw89_vif *rtwvif; 4310 unsigned int link_id; 4311 4312 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4313 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4314 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4315 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4316 } 4317 4318 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4319 struct rtw89_vif_link *rtwvif_link) 4320 { 4321 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4322 const struct rtw89_port_reg *p = mac->port_base; 4323 struct ieee80211_bss_conf *bss_conf; 4324 u16 bcn_int; 4325 4326 rcu_read_lock(); 4327 4328 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4329 if (bss_conf->beacon_int) 4330 bcn_int = bss_conf->beacon_int; 4331 else 4332 bcn_int = BCN_INTERVAL; 4333 4334 rcu_read_unlock(); 4335 4336 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, B_AX_BCN_SPACE_MASK, 4337 bcn_int); 4338 } 4339 4340 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4341 struct rtw89_vif_link *rtwvif_link) 4342 { 4343 u8 win = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4344 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4345 const struct rtw89_port_reg *p = mac->port_base; 4346 u8 port = rtwvif_link->port; 4347 u32 reg; 4348 4349 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif_link->mac_idx); 4350 rtw89_write8(rtwdev, reg, win); 4351 } 4352 4353 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4354 struct rtw89_vif_link *rtwvif_link) 4355 { 4356 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4357 const struct rtw89_port_reg *p = mac->port_base; 4358 struct ieee80211_bss_conf *bss_conf; 4359 u8 dtim_period; 4360 u32 addr; 4361 4362 rcu_read_lock(); 4363 4364 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4365 dtim_period = bss_conf->dtim_period; 4366 4367 rcu_read_unlock(); 4368 4369 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif_link->mac_idx); 4370 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4371 4372 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4373 dtim_period); 4374 } 4375 4376 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4377 struct rtw89_vif_link *rtwvif_link) 4378 { 4379 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4380 const struct rtw89_port_reg *p = mac->port_base; 4381 4382 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4383 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4384 } 4385 4386 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4387 struct rtw89_vif_link *rtwvif_link) 4388 { 4389 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4390 const struct rtw89_port_reg *p = mac->port_base; 4391 4392 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4393 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4394 } 4395 4396 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4397 struct rtw89_vif_link *rtwvif_link) 4398 { 4399 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4400 const struct rtw89_port_reg *p = mac->port_base; 4401 4402 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, 4403 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4404 } 4405 4406 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4407 struct rtw89_vif_link *rtwvif_link) 4408 { 4409 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4410 const struct rtw89_port_reg *p = mac->port_base; 4411 4412 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4413 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4414 } 4415 4416 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4417 struct rtw89_vif_link *rtwvif_link) 4418 { 4419 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4420 const struct rtw89_port_reg *p = mac->port_base; 4421 static const u32 masks[RTW89_PORT_NUM] = { 4422 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4423 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4424 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4425 }; 4426 struct ieee80211_bss_conf *bss_conf; 4427 u8 port = rtwvif_link->port; 4428 u32 reg_base; 4429 u32 reg; 4430 u8 bss_color; 4431 4432 rcu_read_lock(); 4433 4434 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4435 bss_color = bss_conf->he_bss_color.color; 4436 4437 rcu_read_unlock(); 4438 4439 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4440 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif_link->mac_idx); 4441 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4442 } 4443 4444 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4445 struct rtw89_vif_link *rtwvif_link) 4446 { 4447 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4448 const struct rtw89_port_reg *p = mac->port_base; 4449 u8 port = rtwvif_link->port; 4450 u32 reg; 4451 4452 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4453 return; 4454 4455 if (port == 0) { 4456 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif_link->mac_idx); 4457 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4458 } 4459 } 4460 4461 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4462 struct rtw89_vif_link *rtwvif_link) 4463 { 4464 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4465 const struct rtw89_port_reg *p = mac->port_base; 4466 u8 port = rtwvif_link->port; 4467 u32 reg; 4468 u32 val; 4469 4470 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif_link->mac_idx); 4471 val = rtw89_read32(rtwdev, reg); 4472 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4473 if (port == 0) 4474 val &= ~BIT(0); 4475 rtw89_write32(rtwdev, reg, val); 4476 } 4477 4478 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4479 struct rtw89_vif_link *rtwvif_link, bool enable) 4480 { 4481 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4482 const struct rtw89_port_reg *p = mac->port_base; 4483 4484 if (enable) 4485 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4486 B_AX_PORT_FUNC_EN); 4487 else 4488 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4489 B_AX_PORT_FUNC_EN); 4490 } 4491 4492 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4493 struct rtw89_vif_link *rtwvif_link) 4494 { 4495 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4496 const struct rtw89_port_reg *p = mac->port_base; 4497 4498 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 4499 BCN_ERLY_DEF); 4500 } 4501 4502 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4503 struct rtw89_vif_link *rtwvif_link) 4504 { 4505 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4506 const struct rtw89_port_reg *p = mac->port_base; 4507 u16 val; 4508 4509 if (rtwdev->chip->chip_id != RTL8852C) 4510 return; 4511 4512 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4513 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION) 4514 return; 4515 4516 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4517 B_AX_TBTT_SHIFT_OFST_SIGN; 4518 4519 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift, 4520 B_AX_TBTT_SHIFT_OFST_MASK, val); 4521 } 4522 4523 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4524 struct rtw89_vif_link *rtwvif_link, 4525 struct rtw89_vif_link *rtwvif_src, 4526 u16 offset_tu) 4527 { 4528 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4529 const struct rtw89_port_reg *p = mac->port_base; 4530 u32 val, reg; 4531 4532 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4533 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif_link->port * 4, 4534 rtwvif_link->mac_idx); 4535 4536 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4537 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4538 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4539 } 4540 4541 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4542 struct rtw89_vif_link *rtwvif_link, 4543 struct rtw89_vif_link *rtwvif_src, 4544 u8 offset, int *n_offset) 4545 { 4546 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif_link == rtwvif_src) 4547 return; 4548 4549 /* adjust offset randomly to avoid beacon conflict */ 4550 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4551 rtw89_mac_port_tsf_sync(rtwdev, rtwvif_link, rtwvif_src, 4552 (*n_offset) * offset); 4553 4554 (*n_offset)++; 4555 } 4556 4557 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4558 { 4559 struct rtw89_vif_link *src = NULL, *tmp; 4560 u8 offset = 100, vif_aps = 0; 4561 struct rtw89_vif *rtwvif; 4562 unsigned int link_id; 4563 int n_offset = 1; 4564 4565 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4566 rtw89_vif_for_each_link(rtwvif, tmp, link_id) { 4567 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4568 src = tmp; 4569 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4570 vif_aps++; 4571 } 4572 } 4573 4574 if (vif_aps == 0) 4575 return; 4576 4577 offset /= (vif_aps + 1); 4578 4579 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4580 rtw89_vif_for_each_link(rtwvif, tmp, link_id) 4581 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, 4582 &n_offset); 4583 } 4584 4585 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4586 { 4587 int ret; 4588 4589 ret = rtw89_mac_port_update(rtwdev, rtwvif_link); 4590 if (ret) 4591 return ret; 4592 4593 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4594 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4595 4596 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif_link->mac_id, false); 4597 if (ret) 4598 return ret; 4599 4600 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_CREATE); 4601 if (ret) 4602 return ret; 4603 4604 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, NULL, true); 4605 if (ret) 4606 return ret; 4607 4608 ret = rtw89_cam_init(rtwdev, rtwvif_link); 4609 if (ret) 4610 return ret; 4611 4612 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 4613 if (ret) 4614 return ret; 4615 4616 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, NULL); 4617 if (ret) 4618 return ret; 4619 4620 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, NULL); 4621 if (ret) 4622 return ret; 4623 4624 return 0; 4625 } 4626 4627 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4628 { 4629 int ret; 4630 4631 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_REMOVE); 4632 if (ret) 4633 return ret; 4634 4635 rtw89_cam_deinit(rtwdev, rtwvif_link); 4636 4637 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 4638 if (ret) 4639 return ret; 4640 4641 return 0; 4642 } 4643 4644 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4645 { 4646 u8 port = rtwvif_link->port; 4647 4648 if (port >= RTW89_PORT_NUM) 4649 return -EINVAL; 4650 4651 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 4652 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif_link, false); 4653 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif_link, false); 4654 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif_link); 4655 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif_link); 4656 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif_link); 4657 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif_link); 4658 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif_link); 4659 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif_link); 4660 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif_link); 4661 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif_link); 4662 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif_link); 4663 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif_link); 4664 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif_link); 4665 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif_link); 4666 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif_link); 4667 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif_link); 4668 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif_link); 4669 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif_link); 4670 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif_link, true); 4671 rtw89_mac_port_tsf_resync_all(rtwdev); 4672 fsleep(BCN_ERLY_SET_DLY); 4673 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif_link); 4674 4675 return 0; 4676 } 4677 4678 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4679 u64 *tsf) 4680 { 4681 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4682 const struct rtw89_port_reg *p = mac->port_base; 4683 u32 tsf_low, tsf_high; 4684 int ret; 4685 4686 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif_link->mac_idx, RTW89_CMAC_SEL); 4687 if (ret) 4688 return ret; 4689 4690 tsf_low = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_l); 4691 tsf_high = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_h); 4692 *tsf = (u64)tsf_high << 32 | tsf_low; 4693 4694 return 0; 4695 } 4696 4697 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4698 struct cfg80211_bss *bss, 4699 void *data) 4700 { 4701 const struct cfg80211_bss_ies *ies; 4702 const struct element *elem; 4703 bool *tolerated = data; 4704 4705 rcu_read_lock(); 4706 ies = rcu_dereference(bss->ies); 4707 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4708 ies->len); 4709 4710 if (!elem || elem->datalen < 10 || 4711 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4712 *tolerated = false; 4713 rcu_read_unlock(); 4714 } 4715 4716 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4717 struct rtw89_vif_link *rtwvif_link) 4718 { 4719 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4720 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4721 struct ieee80211_hw *hw = rtwdev->hw; 4722 struct ieee80211_bss_conf *bss_conf; 4723 struct cfg80211_chan_def oper; 4724 bool tolerated = true; 4725 u32 reg; 4726 4727 rcu_read_lock(); 4728 4729 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4730 if (!bss_conf->he_support || vif->type != NL80211_IFTYPE_STATION) { 4731 rcu_read_unlock(); 4732 return; 4733 } 4734 4735 oper = bss_conf->chanreq.oper; 4736 if (!(oper.chan->flags & IEEE80211_CHAN_RADAR)) { 4737 rcu_read_unlock(); 4738 return; 4739 } 4740 4741 rcu_read_unlock(); 4742 4743 cfg80211_bss_iter(hw->wiphy, &oper, 4744 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4745 &tolerated); 4746 4747 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 4748 rtwvif_link->mac_idx); 4749 if (tolerated) 4750 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4751 else 4752 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4753 } 4754 4755 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4756 { 4757 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 4758 } 4759 4760 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4761 { 4762 return rtw89_mac_vif_init(rtwdev, rtwvif_link); 4763 } 4764 4765 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4766 { 4767 return rtw89_mac_vif_deinit(rtwdev, rtwvif_link); 4768 } 4769 4770 static void 4771 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4772 { 4773 } 4774 4775 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4776 { 4777 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4778 4779 return band == op->band_type && channel == op->primary_channel; 4780 } 4781 4782 static void 4783 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4784 u32 len) 4785 { 4786 const struct rtw89_c2h_scanofld *c2h = 4787 (const struct rtw89_c2h_scanofld *)skb->data; 4788 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 4789 struct rtw89_vif *rtwvif; 4790 struct rtw89_chan new; 4791 u32 last_chan = rtwdev->scan_info.last_chan_idx, report_tsf; 4792 u16 actual_period, expect_period; 4793 u8 reason, status, tx_fail, band; 4794 u8 mac_idx, sw_def, fw_def; 4795 u8 ver = U8_MAX; 4796 u16 chan; 4797 int ret; 4798 4799 if (!rtwvif_link) 4800 return; 4801 4802 rtwvif = rtwvif_link->rtwvif; 4803 4804 if (RTW89_CHK_FW_FEATURE(CH_INFO_BE_V0, &rtwdev->fw)) 4805 ver = 0; 4806 4807 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 4808 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 4809 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 4810 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 4811 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 4812 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 4813 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 4814 4815 4816 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4817 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4818 4819 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4820 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 4821 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 4822 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 4823 if (ver == 0) { 4824 expect_period = 4825 le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 4826 } else { 4827 actual_period = le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_PERIOD_V1); 4828 expect_period = 4829 le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1); 4830 } 4831 4832 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4833 "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 4834 sw_def, fw_def, report_tsf, expect_period); 4835 } 4836 4837 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4838 "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4839 mac_idx, band, chan, reason, status, tx_fail, actual_period); 4840 4841 switch (reason) { 4842 case RTW89_SCAN_LEAVE_OP_NOTIFY: 4843 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4844 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4845 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, false); 4846 ieee80211_stop_queues(rtwdev->hw); 4847 } 4848 return; 4849 case RTW89_SCAN_END_SCAN_NOTIFY: 4850 if (rtwdev->scan_info.abort) 4851 return; 4852 4853 if (rtwvif_link && rtwvif->scan_req && 4854 last_chan < rtwvif->scan_req->n_channels) { 4855 ret = rtw89_hw_scan_offload(rtwdev, rtwvif_link, true); 4856 if (ret) { 4857 rtw89_hw_scan_abort(rtwdev, rtwvif_link); 4858 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4859 } 4860 } else { 4861 rtw89_hw_scan_complete(rtwdev, rtwvif_link, false); 4862 } 4863 break; 4864 case RTW89_SCAN_ENTER_OP_NOTIFY: 4865 case RTW89_SCAN_ENTER_CH_NOTIFY: 4866 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4867 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, 4868 &rtwdev->scan_info.op_chan); 4869 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, true); 4870 ieee80211_wake_queues(rtwdev->hw); 4871 } else { 4872 rtw89_chan_create(&new, chan, chan, band, 4873 RTW89_CHANNEL_WIDTH_20); 4874 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, 4875 &new); 4876 } 4877 break; 4878 default: 4879 return; 4880 } 4881 } 4882 4883 static void 4884 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4885 struct sk_buff *skb) 4886 { 4887 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4888 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 4889 enum nl80211_cqm_rssi_threshold_event nl_event; 4890 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4891 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4892 u8 type, event, mac_id; 4893 s8 sig; 4894 4895 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4896 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4897 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4898 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4899 4900 if (mac_id != rtwvif_link->mac_id) 4901 return; 4902 4903 rtw89_debug(rtwdev, RTW89_DBG_FW, 4904 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4905 mac_id, type, sig, event); 4906 4907 switch (type) { 4908 case RTW89_BCN_FLTR_BEACON_LOSS: 4909 if (!rtwdev->scanning && !rtwvif->offchan) 4910 ieee80211_connection_loss(vif); 4911 else 4912 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 4913 return; 4914 case RTW89_BCN_FLTR_NOTIFY: 4915 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4916 break; 4917 case RTW89_BCN_FLTR_RSSI: 4918 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4919 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4920 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4921 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4922 else 4923 return; 4924 break; 4925 default: 4926 return; 4927 } 4928 4929 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4930 } 4931 4932 static void 4933 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4934 u32 len) 4935 { 4936 struct rtw89_vif_link *rtwvif_link; 4937 struct rtw89_vif *rtwvif; 4938 unsigned int link_id; 4939 4940 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4941 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4942 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif_link, c2h); 4943 } 4944 4945 static void 4946 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4947 { 4948 /* N.B. This will run in interrupt context. */ 4949 4950 rtw89_debug(rtwdev, RTW89_DBG_FW, 4951 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4952 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4953 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4954 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4955 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4956 } 4957 4958 static void 4959 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4960 { 4961 /* N.B. This will run in interrupt context. */ 4962 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4963 struct rtw89_wait_info *ps_wait = &rtwdev->mac.ps_wait; 4964 const struct rtw89_c2h_done_ack *c2h = 4965 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4966 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4967 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4968 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4969 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4970 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4971 struct rtw89_completion_data data = {}; 4972 unsigned int cond; 4973 4974 rtw89_debug(rtwdev, RTW89_DBG_FW, 4975 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4976 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4977 4978 if (h2c_cat != H2C_CAT_MAC) 4979 return; 4980 4981 switch (h2c_class) { 4982 default: 4983 return; 4984 case H2C_CL_MAC_PS: 4985 switch (h2c_func) { 4986 default: 4987 return; 4988 case H2C_FUNC_IPS_CFG: 4989 cond = RTW89_PS_WAIT_COND_IPS_CFG; 4990 break; 4991 } 4992 4993 data.err = !!h2c_return; 4994 rtw89_complete_cond(ps_wait, cond, &data); 4995 return; 4996 case H2C_CL_MAC_FW_OFLD: 4997 switch (h2c_func) { 4998 default: 4999 return; 5000 case H2C_FUNC_ADD_SCANOFLD_CH: 5001 cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 5002 break; 5003 case H2C_FUNC_SCANOFLD: 5004 cond = RTW89_SCANOFLD_WAIT_COND_START; 5005 break; 5006 case H2C_FUNC_SCANOFLD_BE: 5007 cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 5008 break; 5009 } 5010 5011 data.err = !!h2c_return; 5012 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5013 return; 5014 } 5015 } 5016 5017 static void 5018 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5019 { 5020 rtw89_fw_log_dump(rtwdev, c2h->data, len); 5021 } 5022 5023 static void 5024 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5025 { 5026 } 5027 5028 static void 5029 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 5030 u32 len) 5031 { 5032 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 5033 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 5034 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 5035 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 5036 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 5037 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 5038 struct rtw89_completion_data data = {}; 5039 unsigned int cond; 5040 5041 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 5042 pkt_id, pkt_op, pkt_len); 5043 5044 data.err = !pkt_len; 5045 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 5046 5047 rtw89_complete_cond(wait, cond, &data); 5048 } 5049 5050 static void 5051 rtw89_mac_c2h_tx_duty_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5052 { 5053 struct rtw89_c2h_tx_duty_rpt *c2h = 5054 (struct rtw89_c2h_tx_duty_rpt *)skb_c2h->data; 5055 u8 err; 5056 5057 err = le32_get_bits(c2h->w2, RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR); 5058 5059 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "C2H TX duty rpt with err=%d\n", err); 5060 } 5061 5062 static void 5063 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5064 u32 len) 5065 { 5066 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 5067 } 5068 5069 static void 5070 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5071 { 5072 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 5073 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 5074 5075 switch (func) { 5076 case H2C_FUNC_ADD_MCC: 5077 case H2C_FUNC_START_MCC: 5078 case H2C_FUNC_STOP_MCC: 5079 case H2C_FUNC_DEL_MCC_GROUP: 5080 case H2C_FUNC_RESET_MCC_GROUP: 5081 case H2C_FUNC_MCC_REQ_TSF: 5082 case H2C_FUNC_MCC_MACID_BITMAP: 5083 case H2C_FUNC_MCC_SYNC: 5084 case H2C_FUNC_MCC_SET_DURATION: 5085 break; 5086 default: 5087 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5088 "invalid MCC C2H RCV ACK: func %d\n", func); 5089 return; 5090 } 5091 5092 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5093 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 5094 } 5095 5096 static void 5097 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5098 { 5099 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 5100 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 5101 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 5102 struct rtw89_completion_data data = {}; 5103 unsigned int cond; 5104 bool next = false; 5105 5106 switch (func) { 5107 case H2C_FUNC_MCC_REQ_TSF: 5108 next = true; 5109 break; 5110 case H2C_FUNC_MCC_MACID_BITMAP: 5111 case H2C_FUNC_MCC_SYNC: 5112 case H2C_FUNC_MCC_SET_DURATION: 5113 break; 5114 case H2C_FUNC_ADD_MCC: 5115 case H2C_FUNC_START_MCC: 5116 case H2C_FUNC_STOP_MCC: 5117 case H2C_FUNC_DEL_MCC_GROUP: 5118 case H2C_FUNC_RESET_MCC_GROUP: 5119 default: 5120 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5121 "invalid MCC C2H REQ ACK: func %d\n", func); 5122 return; 5123 } 5124 5125 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5126 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5127 group, func, retcode); 5128 5129 if (!retcode && next) 5130 return; 5131 5132 data.err = !!retcode; 5133 cond = RTW89_MCC_WAIT_COND(group, func); 5134 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5135 } 5136 5137 static void 5138 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5139 { 5140 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5141 struct rtw89_completion_data data = {}; 5142 struct rtw89_mac_mcc_tsf_rpt *rpt; 5143 unsigned int cond; 5144 5145 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5146 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5147 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5148 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5149 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5150 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5151 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5152 5153 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5154 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5155 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5156 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5157 5158 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5159 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5160 } 5161 5162 static void 5163 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5164 { 5165 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5166 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5167 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5168 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5169 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5170 struct rtw89_completion_data data = {}; 5171 unsigned int cond; 5172 bool rsp = true; 5173 bool err; 5174 u8 func; 5175 5176 switch (status) { 5177 case RTW89_MAC_MCC_ADD_ROLE_OK: 5178 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5179 func = H2C_FUNC_ADD_MCC; 5180 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5181 break; 5182 case RTW89_MAC_MCC_START_GROUP_OK: 5183 case RTW89_MAC_MCC_START_GROUP_FAIL: 5184 func = H2C_FUNC_START_MCC; 5185 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5186 break; 5187 case RTW89_MAC_MCC_STOP_GROUP_OK: 5188 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5189 func = H2C_FUNC_STOP_MCC; 5190 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5191 break; 5192 case RTW89_MAC_MCC_DEL_GROUP_OK: 5193 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5194 func = H2C_FUNC_DEL_MCC_GROUP; 5195 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5196 break; 5197 case RTW89_MAC_MCC_RESET_GROUP_OK: 5198 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5199 func = H2C_FUNC_RESET_MCC_GROUP; 5200 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5201 break; 5202 case RTW89_MAC_MCC_SWITCH_CH_OK: 5203 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5204 case RTW89_MAC_MCC_TXNULL0_OK: 5205 case RTW89_MAC_MCC_TXNULL0_FAIL: 5206 case RTW89_MAC_MCC_TXNULL1_OK: 5207 case RTW89_MAC_MCC_TXNULL1_FAIL: 5208 case RTW89_MAC_MCC_SWITCH_EARLY: 5209 case RTW89_MAC_MCC_TBTT: 5210 case RTW89_MAC_MCC_DURATION_START: 5211 case RTW89_MAC_MCC_DURATION_END: 5212 rsp = false; 5213 break; 5214 default: 5215 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5216 "invalid MCC C2H STS RPT: status %d\n", status); 5217 return; 5218 } 5219 5220 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5221 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5222 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5223 5224 if (!rsp) 5225 return; 5226 5227 data.err = err; 5228 cond = RTW89_MCC_WAIT_COND(group, func); 5229 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5230 } 5231 5232 static void 5233 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5234 { 5235 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5236 const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5237 struct rtw89_completion_data data = {}; 5238 struct rtw89_mac_mrc_tsf_rpt *rpt; 5239 unsigned int i; 5240 5241 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5242 rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5243 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5244 le32_get_bits(c2h_rpt->w2, 5245 RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5246 5247 for (i = 0; i < rpt->num; i++) { 5248 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5249 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5250 5251 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5252 5253 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5254 "MRC C2H TSF RPT: index %u> %llu\n", 5255 i, rpt->tsfs[i]); 5256 } 5257 5258 rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5259 } 5260 5261 static void 5262 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5263 { 5264 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 5265 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 5266 struct rtw89_wait_info *wait = &rtw_wow->wait; 5267 const struct rtw89_c2h_wow_aoac_report *c2h = 5268 (const struct rtw89_c2h_wow_aoac_report *)skb->data; 5269 struct rtw89_completion_data data = {}; 5270 5271 aoac_rpt->rpt_ver = c2h->rpt_ver; 5272 aoac_rpt->sec_type = c2h->sec_type; 5273 aoac_rpt->key_idx = c2h->key_idx; 5274 aoac_rpt->pattern_idx = c2h->pattern_idx; 5275 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok, 5276 RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX); 5277 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv)); 5278 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count, 5279 sizeof(aoac_rpt->eapol_key_replay_count)); 5280 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk)); 5281 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv)); 5282 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv)); 5283 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id); 5284 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn); 5285 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk)); 5286 5287 rtw89_complete_cond(wait, RTW89_WOW_WAIT_COND_AOAC, &data); 5288 } 5289 5290 static void 5291 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5292 { 5293 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5294 const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5295 struct rtw89_completion_data data = {}; 5296 enum rtw89_mac_mrc_status status; 5297 unsigned int cond; 5298 bool next = false; 5299 u32 tsf_high; 5300 u32 tsf_low; 5301 u8 sch_idx; 5302 u8 func; 5303 5304 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5305 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5306 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5307 tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5308 tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5309 5310 switch (status) { 5311 case RTW89_MAC_MRC_START_SCH_OK: 5312 func = H2C_FUNC_START_MRC; 5313 break; 5314 case RTW89_MAC_MRC_STOP_SCH_OK: 5315 /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5316 func = H2C_FUNC_DEL_MRC; 5317 next = true; 5318 break; 5319 case RTW89_MAC_MRC_DEL_SCH_OK: 5320 func = H2C_FUNC_DEL_MRC; 5321 break; 5322 case RTW89_MAC_MRC_EMPTY_SCH_FAIL: 5323 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5324 "MRC C2H STS RPT: empty sch fail\n"); 5325 return; 5326 case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL: 5327 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5328 "MRC C2H STS RPT: role not exist fail\n"); 5329 return; 5330 case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL: 5331 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5332 "MRC C2H STS RPT: data not found fail\n"); 5333 return; 5334 case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL: 5335 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5336 "MRC C2H STS RPT: get next slot fail\n"); 5337 return; 5338 case RTW89_MAC_MRC_ALT_ROLE_FAIL: 5339 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5340 "MRC C2H STS RPT: alt role fail\n"); 5341 return; 5342 case RTW89_MAC_MRC_ADD_PSTIMER_FAIL: 5343 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5344 "MRC C2H STS RPT: add ps timer fail\n"); 5345 return; 5346 case RTW89_MAC_MRC_MALLOC_FAIL: 5347 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5348 "MRC C2H STS RPT: malloc fail\n"); 5349 return; 5350 case RTW89_MAC_MRC_SWITCH_CH_FAIL: 5351 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5352 "MRC C2H STS RPT: switch ch fail\n"); 5353 return; 5354 case RTW89_MAC_MRC_TXNULL0_FAIL: 5355 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5356 "MRC C2H STS RPT: tx null-0 fail\n"); 5357 return; 5358 case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL: 5359 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5360 "MRC C2H STS RPT: port func en fail\n"); 5361 return; 5362 default: 5363 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5364 "invalid MRC C2H STS RPT: status %d\n", status); 5365 return; 5366 } 5367 5368 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5369 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 5370 sch_idx, status, (u64)tsf_high << 32 | tsf_low); 5371 5372 if (next) 5373 return; 5374 5375 cond = RTW89_MRC_WAIT_COND(sch_idx, func); 5376 rtw89_complete_cond(wait, cond, &data); 5377 } 5378 5379 static void 5380 rtw89_mac_c2h_pwr_int_notify(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5381 { 5382 const struct rtw89_c2h_pwr_int_notify *c2h; 5383 struct rtw89_sta_link *rtwsta_link; 5384 struct ieee80211_sta *sta; 5385 struct rtw89_sta *rtwsta; 5386 u16 macid; 5387 bool ps; 5388 5389 c2h = (const struct rtw89_c2h_pwr_int_notify *)skb->data; 5390 macid = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_MACID); 5391 ps = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS); 5392 5393 rcu_read_lock(); 5394 5395 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 5396 if (unlikely(!rtwsta_link)) 5397 goto out; 5398 5399 rtwsta = rtwsta_link->rtwsta; 5400 if (ps) 5401 set_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5402 else 5403 clear_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5404 5405 sta = rtwsta_to_sta(rtwsta); 5406 ieee80211_sta_ps_transition(sta, ps); 5407 5408 out: 5409 rcu_read_unlock(); 5410 } 5411 5412 static 5413 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5414 struct sk_buff *c2h, u32 len) = { 5415 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5416 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5417 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5418 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 5419 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5420 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5421 [RTW89_MAC_C2H_FUNC_TX_DUTY_RPT] = rtw89_mac_c2h_tx_duty_rpt, 5422 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5423 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5424 }; 5425 5426 static 5427 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5428 struct sk_buff *c2h, u32 len) = { 5429 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5430 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5431 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5432 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5433 }; 5434 5435 static 5436 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5437 struct sk_buff *c2h, u32 len) = { 5438 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5439 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5440 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5441 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5442 }; 5443 5444 static 5445 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 5446 struct sk_buff *c2h, u32 len) = { 5447 [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 5448 [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 5449 }; 5450 5451 static 5452 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev, 5453 struct sk_buff *c2h, u32 len) = { 5454 [RTW89_MAC_C2H_FUNC_AOAC_REPORT] = rtw89_mac_c2h_wow_aoac_rpt, 5455 }; 5456 5457 static 5458 void (* const rtw89_mac_c2h_ap_handler[])(struct rtw89_dev *rtwdev, 5459 struct sk_buff *c2h, u32 len) = { 5460 [RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY] = rtw89_mac_c2h_pwr_int_notify, 5461 }; 5462 5463 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 5464 struct sk_buff *skb) 5465 { 5466 const struct rtw89_c2h_scanofld *c2h = 5467 (const struct rtw89_c2h_scanofld *)skb->data; 5468 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5469 struct rtw89_completion_data data = {}; 5470 unsigned int cond; 5471 u8 status, reason; 5472 5473 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5474 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5475 data.err = status != RTW89_SCAN_STATUS_SUCCESS; 5476 5477 if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 5478 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 5479 cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 5480 else 5481 cond = RTW89_SCANOFLD_WAIT_COND_STOP; 5482 5483 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5484 } 5485 } 5486 5487 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5488 u8 class, u8 func) 5489 { 5490 switch (class) { 5491 default: 5492 return false; 5493 case RTW89_MAC_C2H_CLASS_INFO: 5494 switch (func) { 5495 default: 5496 return false; 5497 case RTW89_MAC_C2H_FUNC_REC_ACK: 5498 case RTW89_MAC_C2H_FUNC_DONE_ACK: 5499 return true; 5500 } 5501 case RTW89_MAC_C2H_CLASS_OFLD: 5502 switch (func) { 5503 default: 5504 return false; 5505 case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 5506 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 5507 return false; 5508 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 5509 return true; 5510 } 5511 case RTW89_MAC_C2H_CLASS_MCC: 5512 return true; 5513 case RTW89_MAC_C2H_CLASS_MRC: 5514 return true; 5515 case RTW89_MAC_C2H_CLASS_WOW: 5516 return true; 5517 case RTW89_MAC_C2H_CLASS_AP: 5518 switch (func) { 5519 default: 5520 return false; 5521 case RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY: 5522 return true; 5523 } 5524 } 5525 } 5526 5527 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5528 u32 len, u8 class, u8 func) 5529 { 5530 void (*handler)(struct rtw89_dev *rtwdev, 5531 struct sk_buff *c2h, u32 len) = NULL; 5532 5533 switch (class) { 5534 case RTW89_MAC_C2H_CLASS_INFO: 5535 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 5536 handler = rtw89_mac_c2h_info_handler[func]; 5537 break; 5538 case RTW89_MAC_C2H_CLASS_OFLD: 5539 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 5540 handler = rtw89_mac_c2h_ofld_handler[func]; 5541 break; 5542 case RTW89_MAC_C2H_CLASS_MCC: 5543 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 5544 handler = rtw89_mac_c2h_mcc_handler[func]; 5545 break; 5546 case RTW89_MAC_C2H_CLASS_MRC: 5547 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 5548 handler = rtw89_mac_c2h_mrc_handler[func]; 5549 break; 5550 case RTW89_MAC_C2H_CLASS_WOW: 5551 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_WOW) 5552 handler = rtw89_mac_c2h_wow_handler[func]; 5553 break; 5554 case RTW89_MAC_C2H_CLASS_AP: 5555 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_AP) 5556 handler = rtw89_mac_c2h_ap_handler[func]; 5557 break; 5558 case RTW89_MAC_C2H_CLASS_FWDBG: 5559 return; 5560 default: 5561 rtw89_info(rtwdev, "MAC c2h class %d not support\n", class); 5562 return; 5563 } 5564 if (!handler) { 5565 rtw89_info(rtwdev, "MAC c2h class %d func %d not support\n", class, 5566 func); 5567 return; 5568 } 5569 handler(rtwdev, skb, len); 5570 } 5571 5572 static 5573 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 5574 enum rtw89_phy_idx phy_idx, 5575 u32 reg_base, u32 *cr) 5576 { 5577 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 5578 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 5579 5580 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 5581 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 5582 addr); 5583 goto error; 5584 } 5585 5586 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 5587 if (mode == RTW89_QTA_SCC) { 5588 rtw89_err(rtwdev, 5589 "[TXPWR] addr=0x%x but hw not enable\n", 5590 addr); 5591 goto error; 5592 } 5593 5594 *cr = addr; 5595 return true; 5596 5597 error: 5598 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 5599 addr, phy_idx); 5600 5601 return false; 5602 } 5603 5604 static 5605 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 5606 { 5607 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 5608 int ret; 5609 5610 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5611 if (ret) 5612 return ret; 5613 5614 if (!enable) { 5615 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 5616 return 0; 5617 } 5618 5619 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 5620 B_AX_APP_MAC_INFO_RPT | 5621 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 5622 B_AX_PPDU_STAT_RPT_CRC32); 5623 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 5624 RTW89_PRPT_DEST_HOST); 5625 5626 return 0; 5627 } 5628 5629 static 5630 void __rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 5631 { 5632 #define MAC_AX_TIME_TH_SH 5 5633 #define MAC_AX_LEN_TH_SH 4 5634 #define MAC_AX_TIME_TH_MAX 255 5635 #define MAC_AX_LEN_TH_MAX 255 5636 #define MAC_AX_TIME_TH_DEF 88 5637 #define MAC_AX_LEN_TH_DEF 4080 5638 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5639 struct ieee80211_hw *hw = rtwdev->hw; 5640 u32 rts_threshold = hw->wiphy->rts_threshold; 5641 u32 time_th, len_th; 5642 u32 reg; 5643 5644 if (rts_threshold == (u32)-1) { 5645 time_th = MAC_AX_TIME_TH_DEF; 5646 len_th = MAC_AX_LEN_TH_DEF; 5647 } else { 5648 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 5649 len_th = rts_threshold; 5650 } 5651 5652 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 5653 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 5654 5655 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 5656 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 5657 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 5658 } 5659 5660 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev) 5661 { 5662 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 5663 if (rtwdev->dbcc_en) 5664 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_1); 5665 } 5666 5667 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 5668 { 5669 bool empty; 5670 int ret; 5671 5672 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5673 return; 5674 5675 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 5676 10000, 200000, false, rtwdev); 5677 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 5678 rtw89_info(rtwdev, "timed out to flush queues\n"); 5679 } 5680 5681 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 5682 { 5683 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 5684 u8 val; 5685 u16 val16; 5686 u32 val32; 5687 int ret; 5688 5689 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 5690 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5691 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 5692 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 5693 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 5694 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 5695 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5696 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 5697 5698 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 5699 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 5700 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 5701 5702 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 5703 if (ret) { 5704 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 5705 return ret; 5706 } 5707 val32 = val32 & B_AX_WL_RX_CTRL; 5708 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 5709 if (ret) { 5710 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 5711 return ret; 5712 } 5713 5714 switch (coex->pta_mode) { 5715 case RTW89_MAC_AX_COEX_RTK_MODE: 5716 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5717 val &= ~B_AX_BTMODE_MASK; 5718 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 5719 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5720 5721 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 5722 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 5723 5724 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 5725 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 5726 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 5727 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 5728 break; 5729 case RTW89_MAC_AX_COEX_CSR_MODE: 5730 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5731 val &= ~B_AX_BTMODE_MASK; 5732 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 5733 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5734 5735 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 5736 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 5737 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 5738 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 5739 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 5740 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 5741 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 5742 val16 |= B_AX_ENHANCED_BT; 5743 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 5744 5745 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 5746 break; 5747 default: 5748 return -EINVAL; 5749 } 5750 5751 switch (coex->direction) { 5752 case RTW89_MAC_AX_COEX_INNER: 5753 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5754 val = (val & ~BIT(2)) | BIT(1); 5755 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5756 break; 5757 case RTW89_MAC_AX_COEX_OUTPUT: 5758 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5759 val = val | BIT(1) | BIT(0); 5760 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5761 break; 5762 case RTW89_MAC_AX_COEX_INPUT: 5763 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5764 val = val & ~(BIT(2) | BIT(1)); 5765 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5766 break; 5767 default: 5768 return -EINVAL; 5769 } 5770 5771 return 0; 5772 } 5773 EXPORT_SYMBOL(rtw89_mac_coex_init); 5774 5775 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 5776 const struct rtw89_mac_ax_coex *coex) 5777 { 5778 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 5779 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 5780 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 5781 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 5782 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 5783 5784 switch (coex->pta_mode) { 5785 case RTW89_MAC_AX_COEX_RTK_MODE: 5786 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5787 MAC_AX_RTK_MODE); 5788 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 5789 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 5790 break; 5791 case RTW89_MAC_AX_COEX_CSR_MODE: 5792 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5793 MAC_AX_CSR_MODE); 5794 break; 5795 default: 5796 return -EINVAL; 5797 } 5798 5799 return 0; 5800 } 5801 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 5802 5803 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5804 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5805 { 5806 u32 val = 0, ret; 5807 5808 if (gnt_cfg->band[0].gnt_bt) 5809 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 5810 5811 if (gnt_cfg->band[0].gnt_bt_sw_en) 5812 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 5813 5814 if (gnt_cfg->band[0].gnt_wl) 5815 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 5816 5817 if (gnt_cfg->band[0].gnt_wl_sw_en) 5818 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 5819 5820 if (gnt_cfg->band[1].gnt_bt) 5821 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 5822 5823 if (gnt_cfg->band[1].gnt_bt_sw_en) 5824 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 5825 5826 if (gnt_cfg->band[1].gnt_wl) 5827 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 5828 5829 if (gnt_cfg->band[1].gnt_wl_sw_en) 5830 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 5831 5832 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 5833 if (ret) { 5834 rtw89_err(rtwdev, "Write LTE fail!\n"); 5835 return ret; 5836 } 5837 5838 return 0; 5839 } 5840 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 5841 5842 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 5843 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5844 { 5845 u32 val = 0; 5846 5847 if (gnt_cfg->band[0].gnt_bt) 5848 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5849 B_AX_GNT_BT_TX_VAL; 5850 else 5851 val |= B_AX_WL_ACT_VAL; 5852 5853 if (gnt_cfg->band[0].gnt_bt_sw_en) 5854 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5855 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5856 5857 if (gnt_cfg->band[0].gnt_wl) 5858 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5859 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5860 5861 if (gnt_cfg->band[0].gnt_wl_sw_en) 5862 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5863 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5864 5865 if (gnt_cfg->band[1].gnt_bt) 5866 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5867 B_AX_GNT_BT_TX_VAL; 5868 else 5869 val |= B_AX_WL_ACT_VAL; 5870 5871 if (gnt_cfg->band[1].gnt_bt_sw_en) 5872 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5873 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5874 5875 if (gnt_cfg->band[1].gnt_wl) 5876 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5877 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5878 5879 if (gnt_cfg->band[1].gnt_wl_sw_en) 5880 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5881 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5882 5883 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5884 5885 return 0; 5886 } 5887 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5888 5889 static 5890 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5891 { 5892 u32 reg; 5893 u16 val; 5894 int ret; 5895 5896 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5897 if (ret) 5898 return ret; 5899 5900 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 5901 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5902 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5903 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5904 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5905 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5906 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5907 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 5908 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 5909 B_AX_PLT_EN; 5910 rtw89_write16(rtwdev, reg, val); 5911 5912 return 0; 5913 } 5914 5915 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5916 { 5917 u32 fw_sb; 5918 5919 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5920 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5921 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5922 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5923 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5924 else 5925 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5926 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5927 val = B_AX_TOGGLE | 5928 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5929 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5930 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5931 fsleep(1000); /* avoid BT FW loss information */ 5932 } 5933 5934 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5935 { 5936 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5937 } 5938 5939 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5940 { 5941 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5942 5943 val = wl ? val | BIT(2) : val & ~BIT(2); 5944 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5945 5946 return 0; 5947 } 5948 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5949 5950 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5951 { 5952 struct rtw89_btc *btc = &rtwdev->btc; 5953 struct rtw89_btc_dm *dm = &btc->dm; 5954 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5955 int i; 5956 5957 if (wl) 5958 return 0; 5959 5960 for (i = 0; i < RTW89_PHY_MAX; i++) { 5961 g[i].gnt_bt_sw_en = 1; 5962 g[i].gnt_bt = 1; 5963 g[i].gnt_wl_sw_en = 1; 5964 g[i].gnt_wl = 0; 5965 } 5966 5967 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5968 } 5969 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5970 5971 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5972 { 5973 const struct rtw89_chip_info *chip = rtwdev->chip; 5974 u8 val = 0; 5975 5976 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) 5977 return false; 5978 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 5979 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5980 B_AX_LTE_MUX_CTRL_PATH >> 24); 5981 5982 return !!val; 5983 } 5984 5985 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 5986 { 5987 u32 reg; 5988 u16 cnt; 5989 5990 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 5991 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 5992 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 5993 5994 return cnt; 5995 } 5996 5997 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 5998 bool keep) 5999 { 6000 u32 reg; 6001 6002 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 6003 return; 6004 6005 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 6006 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6007 if (keep) { 6008 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6009 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6010 BFRP_RX_STANDBY_TIMER_KEEP); 6011 } else { 6012 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6013 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6014 BFRP_RX_STANDBY_TIMER_RELEASE); 6015 } 6016 } 6017 6018 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 6019 { 6020 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6021 u32 reg; 6022 u32 mask = mac->bfee_ctrl.mask; 6023 6024 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 6025 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 6026 if (en) { 6027 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6028 rtw89_write32_set(rtwdev, reg, mask); 6029 } else { 6030 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6031 rtw89_write32_clr(rtwdev, reg, mask); 6032 } 6033 } 6034 6035 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 6036 { 6037 u32 reg; 6038 u32 val32; 6039 int ret; 6040 6041 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6042 if (ret) 6043 return ret; 6044 6045 /* AP mode set tx gid to 63 */ 6046 /* STA mode set tx gid to 0(default) */ 6047 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 6048 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 6049 6050 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 6051 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 6052 6053 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6054 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 6055 rtw89_write32(rtwdev, reg, val32); 6056 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 6057 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 6058 6059 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6060 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 6061 B_AX_BFMEE_USE_NSTS | 6062 B_AX_BFMEE_CSI_GID_SEL | 6063 B_AX_BFMEE_CSI_FORCE_RETE_EN); 6064 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 6065 rtw89_write32(rtwdev, reg, 6066 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 6067 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 6068 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 6069 6070 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 6071 rtw89_write32_set(rtwdev, reg, 6072 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 6073 6074 return 0; 6075 } 6076 6077 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 6078 struct rtw89_vif_link *rtwvif_link, 6079 struct rtw89_sta_link *rtwsta_link) 6080 { 6081 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 6082 struct ieee80211_link_sta *link_sta; 6083 u8 mac_idx = rtwvif_link->mac_idx; 6084 u8 port_sel = rtwvif_link->port; 6085 u8 sound_dim = 3, t; 6086 u8 *phy_cap; 6087 u32 reg; 6088 u16 val; 6089 int ret; 6090 6091 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6092 if (ret) 6093 return ret; 6094 6095 rcu_read_lock(); 6096 6097 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6098 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; 6099 6100 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6101 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 6102 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 6103 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 6104 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 6105 phy_cap[5]); 6106 sound_dim = min(sound_dim, t); 6107 } 6108 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6109 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 6110 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 6111 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 6112 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 6113 link_sta->vht_cap.cap); 6114 sound_dim = min(sound_dim, t); 6115 } 6116 nc = min(nc, sound_dim); 6117 nr = min(nr, sound_dim); 6118 6119 rcu_read_unlock(); 6120 6121 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6122 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6123 6124 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 6125 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 6126 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 6127 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 6128 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 6129 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 6130 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 6131 6132 if (port_sel == 0) 6133 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6134 else 6135 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 6136 6137 rtw89_write16(rtwdev, reg, val); 6138 6139 return 0; 6140 } 6141 6142 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 6143 struct rtw89_vif_link *rtwvif_link, 6144 struct rtw89_sta_link *rtwsta_link) 6145 { 6146 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 6147 struct ieee80211_link_sta *link_sta; 6148 u8 mac_idx = rtwvif_link->mac_idx; 6149 u32 reg; 6150 int ret; 6151 6152 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6153 if (ret) 6154 return ret; 6155 6156 rcu_read_lock(); 6157 6158 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6159 6160 if (link_sta->he_cap.has_he) { 6161 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 6162 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 6163 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 6164 } 6165 if (link_sta->vht_cap.vht_supported) { 6166 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 6167 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 6168 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 6169 } 6170 if (link_sta->ht_cap.ht_supported) { 6171 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 6172 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 6173 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 6174 } 6175 6176 rcu_read_unlock(); 6177 6178 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6179 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6180 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 6181 rtw89_write32(rtwdev, 6182 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 6183 rrsc); 6184 6185 return 0; 6186 } 6187 6188 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 6189 struct rtw89_vif_link *rtwvif_link, 6190 struct rtw89_sta_link *rtwsta_link) 6191 { 6192 struct ieee80211_link_sta *link_sta; 6193 bool has_beamformer_cap; 6194 6195 rcu_read_lock(); 6196 6197 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6198 has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta); 6199 6200 rcu_read_unlock(); 6201 6202 if (has_beamformer_cap) { 6203 rtw89_debug(rtwdev, RTW89_DBG_BF, 6204 "initialize bfee for new association\n"); 6205 rtw89_mac_init_bfee_ax(rtwdev, rtwvif_link->mac_idx); 6206 rtw89_mac_set_csi_para_reg_ax(rtwdev, rtwvif_link, rtwsta_link); 6207 rtw89_mac_csi_rrsc_ax(rtwdev, rtwvif_link, rtwsta_link); 6208 } 6209 } 6210 6211 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, 6212 struct rtw89_vif_link *rtwvif_link, 6213 struct rtw89_sta_link *rtwsta_link) 6214 { 6215 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, false); 6216 } 6217 6218 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6219 struct ieee80211_bss_conf *conf) 6220 { 6221 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 6222 struct rtw89_vif_link *rtwvif_link; 6223 u8 mac_idx; 6224 __le32 *p; 6225 6226 rtwvif_link = rtwvif->links[conf->link_id]; 6227 if (unlikely(!rtwvif_link)) { 6228 rtw89_err(rtwdev, 6229 "%s: rtwvif link (link_id %u) is not active\n", 6230 __func__, conf->link_id); 6231 return; 6232 } 6233 6234 mac_idx = rtwvif_link->mac_idx; 6235 6236 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 6237 6238 p = (__le32 *)conf->mu_group.membership; 6239 rtw89_write32(rtwdev, 6240 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 6241 le32_to_cpu(p[0])); 6242 rtw89_write32(rtwdev, 6243 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 6244 le32_to_cpu(p[1])); 6245 6246 p = (__le32 *)conf->mu_group.position; 6247 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 6248 le32_to_cpu(p[0])); 6249 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 6250 le32_to_cpu(p[1])); 6251 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 6252 le32_to_cpu(p[2])); 6253 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 6254 le32_to_cpu(p[3])); 6255 } 6256 6257 struct rtw89_mac_bf_monitor_iter_data { 6258 struct rtw89_dev *rtwdev; 6259 struct rtw89_sta_link *down_rtwsta_link; 6260 int count; 6261 }; 6262 6263 static 6264 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 6265 { 6266 struct rtw89_mac_bf_monitor_iter_data *iter_data = 6267 (struct rtw89_mac_bf_monitor_iter_data *)data; 6268 struct rtw89_sta_link *down_rtwsta_link = iter_data->down_rtwsta_link; 6269 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6270 struct ieee80211_link_sta *link_sta; 6271 struct rtw89_sta_link *rtwsta_link; 6272 bool has_beamformer_cap = false; 6273 int *count = &iter_data->count; 6274 unsigned int link_id; 6275 6276 rcu_read_lock(); 6277 6278 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6279 if (rtwsta_link == down_rtwsta_link) 6280 continue; 6281 6282 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 6283 if (rtw89_sta_has_beamformer_cap(link_sta)) { 6284 has_beamformer_cap = true; 6285 break; 6286 } 6287 } 6288 6289 if (has_beamformer_cap) 6290 (*count)++; 6291 6292 rcu_read_unlock(); 6293 } 6294 6295 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 6296 struct rtw89_sta_link *rtwsta_link, 6297 bool disconnect) 6298 { 6299 struct rtw89_mac_bf_monitor_iter_data data; 6300 6301 data.rtwdev = rtwdev; 6302 data.down_rtwsta_link = disconnect ? rtwsta_link : NULL; 6303 data.count = 0; 6304 ieee80211_iterate_stations_atomic(rtwdev->hw, 6305 rtw89_mac_bf_monitor_calc_iter, 6306 &data); 6307 6308 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 6309 if (data.count) 6310 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6311 else 6312 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6313 } 6314 6315 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 6316 { 6317 struct rtw89_traffic_stats *stats = &rtwdev->stats; 6318 struct rtw89_vif_link *rtwvif_link; 6319 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 6320 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6321 struct rtw89_vif *rtwvif; 6322 bool keep_timer = true; 6323 unsigned int link_id; 6324 bool old_keep_timer; 6325 6326 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6327 6328 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 6329 keep_timer = false; 6330 6331 if (keep_timer != old_keep_timer) { 6332 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6333 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6334 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif_link->mac_idx, 6335 keep_timer); 6336 } 6337 6338 if (en == old) 6339 return; 6340 6341 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6342 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6343 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, en); 6344 } 6345 6346 static int 6347 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6348 u32 tx_time) 6349 { 6350 #define MAC_AX_DFLT_TX_TIME 5280 6351 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6352 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 6353 u32 reg; 6354 int ret = 0; 6355 6356 if (rtwsta_link->cctl_tx_time) { 6357 rtwsta_link->ampdu_max_time = (max_tx_time - 512) >> 9; 6358 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6359 } else { 6360 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6361 if (ret) { 6362 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 6363 return ret; 6364 } 6365 6366 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6367 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 6368 max_tx_time >> 5); 6369 } 6370 6371 return ret; 6372 } 6373 6374 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6375 bool resume, u32 tx_time) 6376 { 6377 int ret = 0; 6378 6379 if (!resume) { 6380 rtwsta_link->cctl_tx_time = true; 6381 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6382 } else { 6383 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6384 rtwsta_link->cctl_tx_time = false; 6385 } 6386 6387 return ret; 6388 } 6389 6390 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6391 u32 *tx_time) 6392 { 6393 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6394 u32 reg; 6395 int ret = 0; 6396 6397 if (rtwsta_link->cctl_tx_time) { 6398 *tx_time = (rtwsta_link->ampdu_max_time + 1) << 9; 6399 } else { 6400 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6401 if (ret) { 6402 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 6403 return ret; 6404 } 6405 6406 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6407 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 6408 } 6409 6410 return ret; 6411 } 6412 6413 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 6414 struct rtw89_sta_link *rtwsta_link, 6415 bool resume, u8 tx_retry) 6416 { 6417 int ret = 0; 6418 6419 rtwsta_link->data_tx_cnt_lmt = tx_retry; 6420 6421 if (!resume) { 6422 rtwsta_link->cctl_tx_retry_limit = true; 6423 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6424 } else { 6425 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6426 rtwsta_link->cctl_tx_retry_limit = false; 6427 } 6428 6429 return ret; 6430 } 6431 6432 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 6433 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry) 6434 { 6435 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6436 u32 reg; 6437 int ret = 0; 6438 6439 if (rtwsta_link->cctl_tx_retry_limit) { 6440 *tx_retry = rtwsta_link->data_tx_cnt_lmt; 6441 } else { 6442 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6443 if (ret) { 6444 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 6445 return ret; 6446 } 6447 6448 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); 6449 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 6450 } 6451 6452 return ret; 6453 } 6454 6455 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 6456 struct rtw89_vif_link *rtwvif_link, bool en) 6457 { 6458 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6459 u8 mac_idx = rtwvif_link->mac_idx; 6460 u16 set = mac->muedca_ctrl.mask; 6461 u32 reg; 6462 u32 ret; 6463 6464 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6465 if (ret) 6466 return ret; 6467 6468 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 6469 if (en) 6470 rtw89_write16_set(rtwdev, reg, set); 6471 else 6472 rtw89_write16_clr(rtwdev, reg, set); 6473 6474 return 0; 6475 } 6476 6477 static 6478 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 6479 { 6480 u32 val32; 6481 int ret; 6482 6483 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6484 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 6485 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 6486 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 6487 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6488 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6489 6490 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6491 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6492 if (ret) { 6493 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 6494 offset, val, mask); 6495 return ret; 6496 } 6497 6498 return 0; 6499 } 6500 6501 static 6502 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 6503 { 6504 u32 val32; 6505 int ret; 6506 6507 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6508 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 6509 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 6510 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 6511 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6512 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6513 6514 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6515 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6516 if (ret) { 6517 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 6518 return ret; 6519 } 6520 6521 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 6522 6523 return 0; 6524 } 6525 6526 static 6527 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, 6528 struct rtw89_vif_link *rtwvif_link, 6529 struct rtw89_sta_link *rtwsta_link) 6530 { 6531 static const enum rtw89_pkt_drop_sel sels[] = { 6532 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 6533 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 6534 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 6535 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 6536 }; 6537 struct rtw89_pkt_drop_params params = {0}; 6538 int i; 6539 6540 params.mac_band = rtwvif_link->mac_idx; 6541 params.macid = rtwsta_link->mac_id; 6542 params.port = rtwvif_link->port; 6543 params.mbssid = 0; 6544 params.tf_trs = rtwvif_link->trigger; 6545 6546 for (i = 0; i < ARRAY_SIZE(sels); i++) { 6547 params.sel = sels[i]; 6548 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6549 } 6550 } 6551 6552 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 6553 { 6554 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6555 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6556 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6557 struct rtw89_vif_link *rtwvif_link; 6558 struct rtw89_sta_link *rtwsta_link; 6559 struct rtw89_vif *target = data; 6560 unsigned int link_id; 6561 6562 if (rtwvif != target) 6563 return; 6564 6565 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6566 rtwvif_link = rtwsta_link->rtwvif_link; 6567 rtw89_mac_pkt_drop_sta(rtwdev, rtwvif_link, rtwsta_link); 6568 } 6569 } 6570 6571 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 6572 { 6573 ieee80211_iterate_stations_atomic(rtwdev->hw, 6574 rtw89_mac_pkt_drop_vif_iter, 6575 rtwvif); 6576 } 6577 6578 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 6579 enum rtw89_mac_idx band) 6580 { 6581 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6582 struct rtw89_pkt_drop_params params = {0}; 6583 bool empty; 6584 int i, ret = 0, try_cnt = 3; 6585 6586 params.mac_band = band; 6587 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 6588 6589 for (i = 0; i < try_cnt; i++) { 6590 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 6591 50000, false, rtwdev); 6592 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 6593 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6594 else 6595 return 0; 6596 } 6597 return ret; 6598 } 6599 6600 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 6601 { 6602 struct rtw89_mac_h2c_info h2c_info = {}; 6603 struct rtw89_mac_c2h_info c2h_info = {}; 6604 u32 ret; 6605 6606 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 6607 return 0; 6608 6609 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; 6610 h2c_info.content_len = sizeof(h2c_info.u.hdr); 6611 h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); 6612 6613 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 6614 if (ret) 6615 return ret; 6616 6617 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) 6618 ret = -EINVAL; 6619 6620 return ret; 6621 } 6622 6623 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 6624 { 6625 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6626 const struct rtw89_chip_info *chip = rtwdev->chip; 6627 int ret; 6628 6629 if (enable_wow) { 6630 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 6631 if (ret) { 6632 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6633 return ret; 6634 } 6635 6636 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6637 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6638 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 6639 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 6640 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 6641 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 6642 rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 6643 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 6644 6645 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 6646 return 0; 6647 6648 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6649 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 6650 else 6651 rtw89_write32_set(rtwdev, R_AX_DBG_WOW, 6652 B_AX_DBG_WOW_CPU_IO_RX_EN); 6653 } else { 6654 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 6655 if (ret) { 6656 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6657 return ret; 6658 } 6659 6660 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6661 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6662 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 6663 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 6664 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 6665 } 6666 6667 return 0; 6668 } 6669 6670 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 6671 { 6672 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 6673 6674 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 6675 } 6676 6677 static 6678 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 6679 bool h2c_or_fwdl) 6680 { 6681 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 6682 u8 val; 6683 6684 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 6685 1, FWDL_WAIT_CNT, false, 6686 rtwdev, R_AX_WCPU_FW_CTRL); 6687 } 6688 6689 static 6690 void rtw89_fwdl_secure_idmem_share_mode_ax(struct rtw89_dev *rtwdev, u8 mode) 6691 { 6692 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 6693 6694 if (!sec->secure_boot) 6695 return; 6696 6697 rtw89_write32_mask(rtwdev, R_AX_WCPU_FW_CTRL, 6698 B_AX_IDMEM_SHARE_MODE_RECORD_MASK, mode); 6699 rtw89_write32_set(rtwdev, R_AX_WCPU_FW_CTRL, 6700 B_AX_IDMEM_SHARE_MODE_RECORD_VALID); 6701 } 6702 6703 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 6704 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 6705 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 6706 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 6707 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 6708 .rx_fltr = R_AX_RX_FLTR_OPT, 6709 .port_base = &rtw89_port_base_ax, 6710 .agg_len_ht = R_AX_AGG_LEN_HT_0, 6711 .ps_status = R_AX_PPWRBIT_SETTING, 6712 6713 .muedca_ctrl = { 6714 .addr = R_AX_MUEDCA_EN, 6715 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 6716 }, 6717 .bfee_ctrl = { 6718 .addr = R_AX_BFMEE_RESP_OPTION, 6719 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 6720 B_AX_BFMEE_HE_NDPA_EN, 6721 }, 6722 .narrow_bw_ru_dis = { 6723 .addr = R_AX_RXTRIG_TEST_USER_2, 6724 .mask = B_AX_RXTRIG_RU26_DIS, 6725 }, 6726 .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 6727 6728 .check_mac_en = rtw89_mac_check_mac_en_ax, 6729 .sys_init = sys_init_ax, 6730 .trx_init = trx_init_ax, 6731 .hci_func_en = rtw89_mac_hci_func_en_ax, 6732 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 6733 .dle_func_en = dle_func_en_ax, 6734 .dle_clk_en = dle_clk_en_ax, 6735 .bf_assoc = rtw89_mac_bf_assoc_ax, 6736 6737 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 6738 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 6739 .cfg_phy_rpt = NULL, 6740 6741 .dle_mix_cfg = dle_mix_cfg_ax, 6742 .chk_dle_rdy = chk_dle_rdy_ax, 6743 .dle_buf_req = dle_buf_req_ax, 6744 .hfc_func_en = hfc_func_en_ax, 6745 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 6746 .hfc_mix_cfg = hfc_mix_cfg_ax, 6747 .hfc_get_mix_info = hfc_get_mix_info_ax, 6748 .wde_quota_cfg = wde_quota_cfg_ax, 6749 .ple_quota_cfg = ple_quota_cfg_ax, 6750 .set_cpuio = set_cpuio_ax, 6751 .dle_quota_change = dle_quota_change_ax, 6752 6753 .disable_cpu = rtw89_mac_disable_cpu_ax, 6754 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 6755 .fwdl_get_status = rtw89_fw_get_rdy_ax, 6756 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 6757 .fwdl_secure_idmem_share_mode = rtw89_fwdl_secure_idmem_share_mode_ax, 6758 .parse_efuse_map = rtw89_parse_efuse_map_ax, 6759 .parse_phycap_map = rtw89_parse_phycap_map_ax, 6760 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 6761 .efuse_read_fw_secure = rtw89_efuse_read_fw_secure_ax, 6762 6763 .cfg_plt = rtw89_mac_cfg_plt_ax, 6764 .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 6765 6766 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 6767 6768 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 6769 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 6770 6771 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 6772 .dump_err_status = rtw89_mac_dump_err_status_ax, 6773 6774 .is_txq_empty = mac_is_txq_empty_ax, 6775 6776 .add_chan_list = rtw89_hw_scan_add_chan_list_ax, 6777 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_ax, 6778 .scan_offload = rtw89_fw_h2c_scan_offload_ax, 6779 6780 .wow_config_mac = rtw89_wow_config_mac_ax, 6781 }; 6782 EXPORT_SYMBOL(rtw89_mac_gen_ax); 6783