1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "phy.h" 13 #include "ps.h" 14 #include "reg.h" 15 #include "ser.h" 16 #include "util.h" 17 18 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 19 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 20 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 21 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 22 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 23 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 24 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 26 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 28 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 29 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 30 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 31 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 35 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 36 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 37 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 38 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 39 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 40 }; 41 42 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 43 u32 val, enum rtw89_mac_mem_sel sel) 44 { 45 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 46 u32 addr = mac->mem_base_addrs[sel] + offset; 47 48 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 49 rtw89_write32(rtwdev, mac->indir_access_addr, val); 50 } 51 52 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 53 enum rtw89_mac_mem_sel sel) 54 { 55 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 56 u32 addr = mac->mem_base_addrs[sel] + offset; 57 58 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 59 return rtw89_read32(rtwdev, mac->indir_access_addr); 60 } 61 62 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 63 enum rtw89_mac_hwmod_sel sel) 64 { 65 u32 val, r_val; 66 67 if (sel == RTW89_DMAC_SEL) { 68 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 69 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 70 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 71 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 72 val = B_AX_CMAC_EN; 73 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 74 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 75 val = B_AX_CMAC1_FEN; 76 } else { 77 return -EINVAL; 78 } 79 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 80 (val & r_val) != val) 81 return -EFAULT; 82 83 return 0; 84 } 85 86 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 87 { 88 u8 lte_ctrl; 89 int ret; 90 91 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 92 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 93 if (ret && !test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 94 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 95 96 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 97 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 98 99 return ret; 100 } 101 102 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 103 { 104 u8 lte_ctrl; 105 int ret; 106 107 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 108 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 109 if (ret && !test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 110 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 111 112 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 113 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 114 115 return ret; 116 } 117 118 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 119 { 120 u32 ctrl_reg, data_reg, ctrl_data; 121 u32 val; 122 int ret; 123 124 switch (ctrl->type) { 125 case DLE_CTRL_TYPE_WDE: 126 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 127 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 128 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 129 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 130 B_AX_WDE_DFI_ACTIVE; 131 break; 132 case DLE_CTRL_TYPE_PLE: 133 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 134 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 135 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 136 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 137 B_AX_PLE_DFI_ACTIVE; 138 break; 139 default: 140 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 141 return -EINVAL; 142 } 143 144 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 145 146 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 147 1, 1000, false, rtwdev, ctrl_reg); 148 if (ret) { 149 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 150 ctrl_reg, ctrl_data); 151 return ret; 152 } 153 154 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 155 return 0; 156 } 157 158 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 159 struct rtw89_mac_dle_dfi_quota *quota) 160 { 161 struct rtw89_mac_dle_dfi_ctrl ctrl; 162 int ret; 163 164 ctrl.type = quota->dle_type; 165 ctrl.target = DLE_DFI_TYPE_QUOTA; 166 ctrl.addr = quota->qtaid; 167 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 168 if (ret) { 169 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 170 return ret; 171 } 172 173 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 174 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 175 return 0; 176 } 177 178 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 179 struct rtw89_mac_dle_dfi_qempty *qempty) 180 { 181 struct rtw89_mac_dle_dfi_ctrl ctrl; 182 int ret; 183 184 ctrl.type = qempty->dle_type; 185 ctrl.target = DLE_DFI_TYPE_QEMPTY; 186 ctrl.addr = qempty->grpsel; 187 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 188 if (ret) { 189 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 190 return ret; 191 } 192 193 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 194 return 0; 195 } 196 197 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 198 { 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 201 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 202 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 205 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 206 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 209 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 210 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 211 } 212 213 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 214 { 215 struct rtw89_mac_dle_dfi_qempty qempty; 216 struct rtw89_mac_dle_dfi_quota quota; 217 struct rtw89_mac_dle_dfi_ctrl ctrl; 218 u32 val, not_empty, i; 219 int ret; 220 221 qempty.dle_type = DLE_CTRL_TYPE_PLE; 222 qempty.grpsel = 0; 223 qempty.qempty = ~(u32)0; 224 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 225 if (ret) 226 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 227 else 228 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 229 230 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 231 if (!(not_empty & BIT(0))) 232 continue; 233 ctrl.type = DLE_CTRL_TYPE_PLE; 234 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 235 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 236 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 237 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 238 if (ret) 239 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 240 else 241 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 242 u32_get_bits(ctrl.out_data, 243 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 244 } 245 246 quota.dle_type = DLE_CTRL_TYPE_PLE; 247 quota.qtaid = 6; 248 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 249 if (ret) 250 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 251 else 252 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 253 quota.rsv_pgnum, quota.use_pgnum); 254 255 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 257 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 258 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 259 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 260 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 261 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 262 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 263 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 264 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 265 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 266 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 267 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 268 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 269 270 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 271 quota.dle_type = DLE_CTRL_TYPE_PLE; 272 quota.qtaid = 7; 273 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 274 if (ret) 275 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 276 else 277 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 278 quota.rsv_pgnum, quota.use_pgnum); 279 280 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 282 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 283 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 284 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 285 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 286 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 287 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 288 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 289 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 290 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 291 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 292 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 293 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 294 } 295 296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 298 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 299 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 300 301 dump_err_status_dispatcher_ax(rtwdev); 302 } 303 304 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 305 enum mac_ax_err_info err) 306 { 307 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 308 u32 dbg, event; 309 310 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 311 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 312 313 switch (event) { 314 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 315 rtw89_info(rtwdev, "quota lost!\n"); 316 mac->dump_qta_lost(rtwdev); 317 break; 318 default: 319 break; 320 } 321 } 322 323 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 324 { 325 const struct rtw89_chip_info *chip = rtwdev->chip; 326 u32 dmac_err; 327 int i, ret; 328 329 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 330 if (ret) { 331 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 332 return; 333 } 334 335 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 336 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 337 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 339 340 if (dmac_err) { 341 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 343 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 344 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 345 if (chip->chip_id == RTL8852C) { 346 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 348 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 352 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 353 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 354 } 355 } 356 357 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 360 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 361 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 362 if (chip->chip_id == RTL8852C) 363 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 364 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 365 else 366 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 367 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 368 } 369 370 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 371 if (chip->chip_id == RTL8852C) { 372 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 374 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 376 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 378 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 380 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 382 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 384 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 386 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 388 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 389 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 390 391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392 B_AX_DBG_SEL0, 0x8B); 393 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 394 B_AX_DBG_SEL1, 0x8B); 395 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 396 B_AX_SEL_0XC0_MASK, 1); 397 for (i = 0; i < 0x10; i++) { 398 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 399 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 400 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 401 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 402 } 403 } else if (chip->chip_id == RTL8922A) { 404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 406 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 407 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 408 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 409 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 410 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 411 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 412 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 413 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 414 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 415 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 416 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 417 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 418 } else { 419 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 421 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 423 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 425 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 427 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 429 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 430 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 431 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 432 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 433 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 435 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 437 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 438 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 439 } 440 } 441 442 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 445 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 449 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 450 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 451 } 452 453 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 454 if (chip->chip_id == RTL8922A) { 455 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 456 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 457 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 458 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 459 } else { 460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 462 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 463 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 464 } 465 } 466 467 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 468 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 470 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 471 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 472 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 474 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 475 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 476 } 477 478 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 479 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 486 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 487 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 488 } else { 489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 491 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 492 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 493 } 494 } 495 496 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 497 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 499 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 501 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 503 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 509 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 510 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 515 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 516 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 517 if (chip->chip_id == RTL8922A) { 518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 520 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 521 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 522 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 524 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 525 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 526 } else { 527 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 529 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 530 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 531 if (chip->chip_id == RTL8852C) { 532 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 533 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 534 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 535 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 536 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 537 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 538 } else { 539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 543 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 544 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 545 } 546 } 547 } 548 549 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 552 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 553 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 554 } 555 556 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 557 if (chip->chip_id == RTL8922A) { 558 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 559 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 560 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 561 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 562 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 563 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 564 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 565 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 566 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 567 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 568 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 569 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 570 } else { 571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 573 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 574 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 577 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 578 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 581 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 582 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 583 } 584 } 585 586 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 587 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 590 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 591 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 594 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 595 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 598 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 599 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 600 } else { 601 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 602 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 605 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 606 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 609 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 610 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 611 } 612 if (chip->chip_id == RTL8922A) { 613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 615 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 616 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 617 } 618 } 619 620 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 621 if (chip->chip_id == RTL8922A) { 622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 624 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 625 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 626 } else if (chip->chip_id == RTL8852C) { 627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 629 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 630 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 631 } 632 } 633 634 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 635 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 636 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 637 RTW89_MAC_MEM_AXIDMA)); 638 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 639 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 640 RTW89_MAC_MEM_AXIDMA)); 641 } 642 643 if (dmac_err & B_BE_MLO_ERR_INT) { 644 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 646 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 647 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 648 } 649 650 if (dmac_err & B_BE_PLRLS_ERR_INT) { 651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 653 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 654 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 655 } 656 } 657 658 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 659 u8 band) 660 { 661 const struct rtw89_chip_info *chip = rtwdev->chip; 662 u32 offset = 0; 663 u32 cmac_err; 664 int ret; 665 666 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 667 if (ret) { 668 if (band) 669 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 670 else 671 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 672 return; 673 } 674 675 if (band) 676 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 677 678 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 679 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 680 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 681 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 682 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 683 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 684 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 685 686 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 689 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 690 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 691 } 692 693 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 694 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 695 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 696 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 697 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 698 } 699 700 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 701 if (chip->chip_id == RTL8852C) { 702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 704 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 705 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 706 } else { 707 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 708 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 709 } 710 } 711 712 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 713 if (chip->chip_id == RTL8852C) { 714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 716 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 717 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 718 } else { 719 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 720 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 721 } 722 } 723 724 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 725 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 726 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 727 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 728 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 729 } 730 731 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 732 if (chip->chip_id == RTL8852C) { 733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 735 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 736 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 737 } else { 738 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 739 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 740 } 741 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 742 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 743 } 744 745 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 746 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 747 } 748 749 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 750 enum mac_ax_err_info err) 751 { 752 if (err != MAC_AX_ERR_L1_ERR_DMAC && 753 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 754 err != MAC_AX_ERR_L0_ERR_CMAC0 && 755 err != MAC_AX_ERR_L0_ERR_CMAC1 && 756 err != MAC_AX_ERR_RXI300) 757 return; 758 759 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 762 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 763 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 764 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 766 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 767 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 768 769 rtw89_mac_dump_dmac_err_status(rtwdev); 770 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 771 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 772 773 rtwdev->hci.ops->dump_err_status(rtwdev); 774 775 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 776 rtw89_mac_dump_l0_to_l1(rtwdev, err); 777 778 rtw89_info(rtwdev, "<---\n"); 779 } 780 781 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 782 { 783 struct rtw89_ser *ser = &rtwdev->ser; 784 u32 dmac_err, imr, isr; 785 int ret; 786 787 if (rtwdev->chip->chip_id == RTL8852C) { 788 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 789 if (ret) 790 return true; 791 792 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 793 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 794 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 795 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 796 797 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 798 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 799 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 800 return true; 801 } 802 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 803 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 804 return true; 805 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 806 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 807 return true; 808 } 809 } 810 811 return false; 812 } 813 814 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 815 { 816 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 817 u32 err, err_scnr; 818 int ret; 819 820 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 821 false, rtwdev, R_AX_HALT_C2H_CTRL); 822 if (ret) { 823 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 824 return ret; 825 } 826 827 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 828 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 829 830 err_scnr = RTW89_ERROR_SCENARIO(err); 831 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 832 err = MAC_AX_ERR_CPU_EXCEPTION; 833 else if (err_scnr == RTW89_WCPU_ASSERTION) 834 err = MAC_AX_ERR_ASSERTION; 835 else if (err_scnr == RTW89_RXI300_ERROR) 836 err = MAC_AX_ERR_RXI300; 837 838 if (rtw89_mac_suppress_log(rtwdev, err)) 839 return err; 840 841 rtw89_fw_st_dbg_dump(rtwdev); 842 mac->dump_err_status(rtwdev, err); 843 844 return err; 845 } 846 EXPORT_SYMBOL(rtw89_mac_get_err_status); 847 848 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 849 { 850 struct rtw89_ser *ser = &rtwdev->ser; 851 bool ser_l1_hdl = false; 852 u32 halt; 853 int ret = 0; 854 855 if (err > MAC_AX_SET_ERR_MAX) { 856 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 857 return -EINVAL; 858 } 859 860 if (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN) 861 ser_l1_hdl = true; 862 863 if (RTW89_CHK_FW_FEATURE(SER_L1_BY_EVENT, &rtwdev->fw) && ser_l1_hdl) 864 goto set; 865 866 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 867 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 868 if (ret) { 869 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 870 return -EFAULT; 871 } 872 873 set: 874 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 875 876 if (ser->prehandle_l1 && ser_l1_hdl) 877 return 0; 878 879 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 880 881 return 0; 882 } 883 EXPORT_SYMBOL(rtw89_mac_set_err_status); 884 885 static int hfc_reset_param(struct rtw89_dev *rtwdev) 886 { 887 const struct rtw89_hfc_param_ini *param_ini, *param_inis; 888 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 889 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 890 891 param_inis = rtwdev->chip->hfc_param_ini[rtwdev->hci.type]; 892 if (!param_inis) 893 return -EINVAL; 894 895 param_ini = ¶m_inis[qta_mode]; 896 897 param->en = 0; 898 899 if (param_ini->pub_cfg) 900 param->pub_cfg = *param_ini->pub_cfg; 901 902 if (param_ini->prec_cfg) 903 param->prec_cfg = *param_ini->prec_cfg; 904 905 if (param_ini->ch_cfg) 906 param->ch_cfg = param_ini->ch_cfg; 907 908 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 909 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 910 param->mode = param_ini->mode; 911 912 return 0; 913 } 914 915 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 916 { 917 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 918 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 919 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 920 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 921 922 if (ch >= RTW89_DMA_CH_NUM) 923 return -EINVAL; 924 925 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 926 ch_cfg[ch].max > pub_cfg->pub_max) 927 return -EINVAL; 928 if (ch_cfg[ch].grp >= grp_num) 929 return -EINVAL; 930 931 return 0; 932 } 933 934 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 935 { 936 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 937 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 938 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 939 940 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 941 if (rtwdev->chip->chip_id == RTL8852A) 942 return 0; 943 else 944 return -EFAULT; 945 } 946 947 return 0; 948 } 949 950 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 951 { 952 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 953 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 954 955 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 956 return -EFAULT; 957 958 return 0; 959 } 960 961 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 962 { 963 const struct rtw89_chip_info *chip = rtwdev->chip; 964 const struct rtw89_page_regs *regs = chip->page_regs; 965 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 966 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 967 int ret = 0; 968 u32 val = 0; 969 970 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 971 if (ret) 972 return ret; 973 974 ret = hfc_ch_cfg_chk(rtwdev, ch); 975 if (ret) 976 return ret; 977 978 if (ch > RTW89_DMA_B1HI) 979 return -EINVAL; 980 981 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 982 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 983 (cfg[ch].grp ? B_AX_GRP : 0); 984 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 985 986 return 0; 987 } 988 989 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 990 { 991 const struct rtw89_chip_info *chip = rtwdev->chip; 992 const struct rtw89_page_regs *regs = chip->page_regs; 993 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 994 struct rtw89_hfc_ch_info *info = param->ch_info; 995 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 996 u32 val; 997 int ret; 998 999 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1000 if (ret) 1001 return ret; 1002 1003 if (ch > RTW89_DMA_H2C) 1004 return -EINVAL; 1005 1006 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 1007 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1008 if (ch < RTW89_DMA_H2C) 1009 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1010 else 1011 info[ch].used = cfg[ch].min - info[ch].aval; 1012 1013 return 0; 1014 } 1015 1016 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1017 { 1018 const struct rtw89_chip_info *chip = rtwdev->chip; 1019 const struct rtw89_page_regs *regs = chip->page_regs; 1020 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1021 u32 val; 1022 int ret; 1023 1024 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1025 if (ret) 1026 return ret; 1027 1028 ret = hfc_pub_cfg_chk(rtwdev); 1029 if (ret) 1030 return ret; 1031 1032 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1033 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1034 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1035 1036 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1037 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1038 1039 return 0; 1040 } 1041 1042 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1043 { 1044 const struct rtw89_chip_info *chip = rtwdev->chip; 1045 const struct rtw89_page_regs *regs = chip->page_regs; 1046 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1047 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1048 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1049 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1050 u32 val; 1051 1052 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1053 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1054 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1055 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1056 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1057 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1058 info->pub_aval = 1059 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1060 B_AX_PUB_AVAL_PG_MASK); 1061 info->wp_aval = 1062 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1063 B_AX_WP_AVAL_PG_MASK); 1064 1065 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1066 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1067 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1068 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1069 prec_cfg->ch011_full_cond = 1070 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1071 prec_cfg->h2c_full_cond = 1072 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1073 prec_cfg->wp_ch07_full_cond = 1074 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1075 prec_cfg->wp_ch811_full_cond = 1076 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1077 1078 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1079 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1080 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1081 1082 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1083 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1084 1085 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1086 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1087 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1088 1089 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1090 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1091 1092 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1093 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1094 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1095 } 1096 1097 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1098 { 1099 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1100 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1101 int ret; 1102 1103 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1104 if (ret) 1105 return ret; 1106 1107 mac->hfc_get_mix_info(rtwdev); 1108 1109 ret = hfc_pub_info_chk(rtwdev); 1110 if (param->en && ret) 1111 return ret; 1112 1113 return 0; 1114 } 1115 1116 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1117 { 1118 const struct rtw89_chip_info *chip = rtwdev->chip; 1119 const struct rtw89_page_regs *regs = chip->page_regs; 1120 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1121 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1122 u32 val; 1123 1124 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1125 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1126 1127 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1128 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1129 prec_cfg->h2c_full_cond); 1130 } 1131 1132 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1133 { 1134 const struct rtw89_chip_info *chip = rtwdev->chip; 1135 const struct rtw89_page_regs *regs = chip->page_regs; 1136 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1137 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1138 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1139 u32 val; 1140 1141 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1142 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1143 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1144 1145 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1146 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1147 1148 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1149 B_AX_PREC_PAGE_WP_CH07_MASK) | 1150 u32_encode_bits(prec_cfg->wp_ch811_prec, 1151 B_AX_PREC_PAGE_WP_CH811_MASK); 1152 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1153 1154 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1155 param->mode, B_AX_HCI_FC_MODE_MASK); 1156 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1157 B_AX_HCI_FC_WD_FULL_COND_MASK); 1158 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1159 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1160 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1161 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1162 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1163 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1164 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1165 } 1166 1167 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1168 { 1169 const struct rtw89_chip_info *chip = rtwdev->chip; 1170 const struct rtw89_page_regs *regs = chip->page_regs; 1171 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1172 u32 val; 1173 1174 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1175 param->en = en; 1176 param->h2c_en = h2c_en; 1177 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1178 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1179 (val & ~B_AX_HCI_FC_CH12_EN); 1180 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1181 } 1182 1183 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1184 { 1185 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1186 const struct rtw89_chip_info *chip = rtwdev->chip; 1187 u32 dma_ch_mask = chip->dma_ch_mask; 1188 int ret = 0; 1189 u8 ch; 1190 1191 if (reset) 1192 ret = hfc_reset_param(rtwdev); 1193 if (ret) 1194 return ret; 1195 1196 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1197 if (ret) 1198 return ret; 1199 1200 mac->hfc_func_en(rtwdev, false, false); 1201 1202 if (!en && h2c_en) { 1203 mac->hfc_h2c_cfg(rtwdev); 1204 mac->hfc_func_en(rtwdev, en, h2c_en); 1205 return 0; 1206 } 1207 1208 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1209 if (dma_ch_mask & BIT(ch)) 1210 continue; 1211 ret = hfc_ch_ctrl(rtwdev, ch); 1212 if (ret) 1213 return ret; 1214 } 1215 1216 ret = hfc_pub_ctrl(rtwdev); 1217 if (ret) 1218 return ret; 1219 1220 mac->hfc_mix_cfg(rtwdev); 1221 if (en || h2c_en) { 1222 mac->hfc_func_en(rtwdev, en, h2c_en); 1223 udelay(10); 1224 } 1225 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1226 if (dma_ch_mask & BIT(ch)) 1227 continue; 1228 ret = hfc_upd_ch_info(rtwdev, ch); 1229 if (ret) 1230 return ret; 1231 } 1232 ret = hfc_upd_mix_info(rtwdev); 1233 1234 return ret; 1235 } 1236 1237 #define PWR_POLL_CNT 2000 1238 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1239 const struct rtw89_pwr_cfg *cfg) 1240 { 1241 u8 val = 0; 1242 int ret; 1243 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1244 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1245 1246 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1247 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1248 1249 if (!ret) 1250 return 0; 1251 1252 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1253 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1254 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1255 1256 return -EBUSY; 1257 } 1258 1259 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1260 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1261 { 1262 const struct rtw89_pwr_cfg *cur_cfg; 1263 u32 addr; 1264 u8 val; 1265 1266 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1267 if (!(cur_cfg->intf_msk & intf_msk) || 1268 !(cur_cfg->cv_msk & cv_msk)) 1269 continue; 1270 1271 switch (cur_cfg->cmd) { 1272 case PWR_CMD_WRITE: 1273 addr = cur_cfg->addr; 1274 1275 if (cur_cfg->base == PWR_BASE_SDIO) 1276 addr |= SDIO_LOCAL_BASE_ADDR; 1277 1278 val = rtw89_read8(rtwdev, addr); 1279 val &= ~(cur_cfg->msk); 1280 val |= (cur_cfg->val & cur_cfg->msk); 1281 1282 rtw89_write8(rtwdev, addr, val); 1283 break; 1284 case PWR_CMD_POLL: 1285 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1286 return -EBUSY; 1287 break; 1288 case PWR_CMD_DELAY: 1289 if (cur_cfg->val == PWR_DELAY_US) 1290 udelay(cur_cfg->addr); 1291 else 1292 fsleep(cur_cfg->addr * 1000); 1293 break; 1294 default: 1295 return -EINVAL; 1296 } 1297 } 1298 1299 return 0; 1300 } 1301 1302 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1303 const struct rtw89_pwr_cfg * const *cfg_seq) 1304 { 1305 u8 intf_msk; 1306 int ret; 1307 1308 switch (rtwdev->hci.type) { 1309 case RTW89_HCI_TYPE_PCIE: 1310 intf_msk = PWR_INTF_MSK_PCIE; 1311 break; 1312 case RTW89_HCI_TYPE_USB: 1313 intf_msk = PWR_INTF_MSK_USB; 1314 break; 1315 case RTW89_HCI_TYPE_SDIO: 1316 intf_msk = PWR_INTF_MSK_SDIO; 1317 break; 1318 default: 1319 return -EOPNOTSUPP; 1320 } 1321 1322 for (; *cfg_seq; cfg_seq++) { 1323 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1324 intf_msk, *cfg_seq); 1325 if (ret) 1326 return -EBUSY; 1327 } 1328 1329 return 0; 1330 } 1331 1332 static enum rtw89_rpwm_req_pwr_state 1333 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1334 { 1335 enum rtw89_rpwm_req_pwr_state state; 1336 1337 switch (rtwdev->ps_mode) { 1338 case RTW89_PS_MODE_RFOFF: 1339 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1340 break; 1341 case RTW89_PS_MODE_CLK_GATED: 1342 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1343 break; 1344 case RTW89_PS_MODE_PWR_GATED: 1345 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1346 break; 1347 default: 1348 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1349 break; 1350 } 1351 return state; 1352 } 1353 1354 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1355 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1356 bool notify_wake) 1357 { 1358 u16 request; 1359 1360 spin_lock_bh(&rtwdev->rpwm_lock); 1361 1362 request = rtw89_read16(rtwdev, R_AX_RPWM); 1363 request ^= request | PS_RPWM_TOGGLE; 1364 request |= req_pwr_state; 1365 1366 if (notify_wake) { 1367 request |= PS_RPWM_NOTIFY_WAKE; 1368 } else { 1369 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1370 RPWM_SEQ_NUM_MAX; 1371 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1372 rtwdev->mac.rpwm_seq_num); 1373 1374 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1375 request |= PS_RPWM_ACK; 1376 } 1377 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1378 1379 spin_unlock_bh(&rtwdev->rpwm_lock); 1380 } 1381 1382 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1383 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1384 { 1385 bool request_deep_mode; 1386 bool in_deep_mode; 1387 u8 rpwm_req_num; 1388 u8 cpwm_rsp_seq; 1389 u8 cpwm_seq; 1390 u8 cpwm_status; 1391 1392 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1393 request_deep_mode = true; 1394 else 1395 request_deep_mode = false; 1396 1397 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1398 in_deep_mode = true; 1399 else 1400 in_deep_mode = false; 1401 1402 if (request_deep_mode != in_deep_mode) 1403 return -EPERM; 1404 1405 if (request_deep_mode) 1406 return 0; 1407 1408 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1409 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1410 PS_CPWM_RSP_SEQ_NUM); 1411 1412 if (rpwm_req_num != cpwm_rsp_seq) 1413 return -EPERM; 1414 1415 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1416 CPWM_SEQ_NUM_MAX; 1417 1418 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1419 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1420 return -EPERM; 1421 1422 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1423 if (cpwm_status != req_pwr_state) 1424 return -EPERM; 1425 1426 return 0; 1427 } 1428 1429 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1430 { 1431 enum rtw89_rpwm_req_pwr_state state; 1432 unsigned long delay = enter ? 10 : 150; 1433 int ret; 1434 int i; 1435 1436 if (enter) 1437 state = rtw89_mac_get_req_pwr_state(rtwdev); 1438 else 1439 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1440 1441 for (i = 0; i < RPWM_TRY_CNT; i++) { 1442 rtw89_mac_send_rpwm(rtwdev, state, false); 1443 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1444 !ret, delay, 15000, false, 1445 rtwdev, state); 1446 if (!ret) 1447 break; 1448 1449 if (i == RPWM_TRY_CNT - 1) { 1450 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1451 enter ? "entering" : "leaving"); 1452 rtw89_ser_notify(rtwdev, MAC_AX_ERR_ASSERTION); 1453 } else { 1454 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1455 "%d time firmware failed to ack for %s ps mode\n", 1456 i + 1, enter ? "entering" : "leaving"); 1457 } 1458 } 1459 } 1460 1461 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1462 { 1463 enum rtw89_rpwm_req_pwr_state state; 1464 1465 state = rtw89_mac_get_req_pwr_state(rtwdev); 1466 rtw89_mac_send_rpwm(rtwdev, state, true); 1467 } 1468 1469 static void rtw89_mac_power_switch_boot_mode(struct rtw89_dev *rtwdev) 1470 { 1471 u32 boot_mode; 1472 1473 if (rtwdev->hci.type != RTW89_HCI_TYPE_USB) 1474 return; 1475 1476 boot_mode = rtw89_read32_mask(rtwdev, R_AX_GPIO_MUXCFG, B_AX_BOOT_MODE); 1477 if (!boot_mode) 1478 return; 1479 1480 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 1481 rtw89_write32_clr(rtwdev, R_AX_SYS_STATUS1, B_AX_AUTO_WLPON); 1482 rtw89_write32_clr(rtwdev, R_AX_GPIO_MUXCFG, B_AX_BOOT_MODE); 1483 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); 1484 } 1485 1486 static int rtw89_mac_pwr_off_func_for_unplugged(struct rtw89_dev *rtwdev) 1487 { 1488 /* 1489 * Avoid accessing IO for unplugged power-off to prevent warnings, 1490 * especially XTAL SI. 1491 */ 1492 return 0; 1493 } 1494 1495 static void rtw89_mac_update_scoreboard(struct rtw89_dev *rtwdev, u8 val) 1496 { 1497 const struct rtw89_chip_info *chip = rtwdev->chip; 1498 u32 reg; 1499 int i; 1500 1501 for (i = 0; i < ARRAY_SIZE(chip->btc_sb.n); i++) { 1502 reg = chip->btc_sb.n[i].cfg; 1503 if (!reg) 1504 continue; 1505 1506 rtw89_write8(rtwdev, reg + 3, val); 1507 } 1508 } 1509 1510 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1511 { 1512 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1513 const struct rtw89_chip_info *chip = rtwdev->chip; 1514 const struct rtw89_pwr_cfg * const *cfg_seq; 1515 int (*cfg_func)(struct rtw89_dev *rtwdev); 1516 int ret; 1517 1518 rtw89_mac_power_switch_boot_mode(rtwdev); 1519 1520 if (on) { 1521 cfg_seq = chip->pwr_on_seq; 1522 cfg_func = chip->ops->pwr_on_func; 1523 } else { 1524 if (test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) { 1525 cfg_seq = NULL; 1526 cfg_func = rtw89_mac_pwr_off_func_for_unplugged; 1527 } else { 1528 cfg_seq = chip->pwr_off_seq; 1529 cfg_func = chip->ops->pwr_off_func; 1530 } 1531 } 1532 1533 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1534 __rtw89_leave_ps_mode(rtwdev); 1535 1536 if (on) { 1537 ret = mac->reset_pwr_state(rtwdev); 1538 if (ret) 1539 return ret; 1540 } 1541 1542 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1543 if (ret) 1544 return ret; 1545 1546 if (on) { 1547 if (!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags)) { 1548 rtw89_mac_efuse_read_ecv(rtwdev); 1549 mac->efuse_read_fw_secure(rtwdev); 1550 } 1551 1552 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1553 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1554 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1555 1556 rtw89_mac_update_scoreboard(rtwdev, MAC_AX_NOTIFY_TP_MAJOR); 1557 rtw89_mac_clr_aon_intr(rtwdev); 1558 } else { 1559 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1560 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1561 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1562 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1563 clear_bit(RTW89_FLAG_CMAC0_PWR, rtwdev->flags); 1564 clear_bit(RTW89_FLAG_CMAC1_PWR, rtwdev->flags); 1565 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1566 1567 rtw89_mac_update_scoreboard(rtwdev, MAC_AX_NOTIFY_PWR_MAJOR); 1568 rtw89_set_entity_state(rtwdev, RTW89_PHY_0, false); 1569 rtw89_set_entity_state(rtwdev, RTW89_PHY_1, false); 1570 } 1571 1572 return 0; 1573 } 1574 1575 int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev) 1576 { 1577 int ret; 1578 1579 ret = rtw89_mac_power_switch(rtwdev, true); 1580 if (ret) { 1581 rtw89_mac_power_switch(rtwdev, false); 1582 ret = rtw89_mac_power_switch(rtwdev, true); 1583 if (ret) 1584 return ret; 1585 } 1586 1587 return 0; 1588 } 1589 1590 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1591 { 1592 rtw89_mac_power_switch(rtwdev, false); 1593 } 1594 1595 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1596 { 1597 u32 func_en = 0; 1598 u32 ck_en = 0; 1599 u32 c1pc_en = 0; 1600 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1601 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1602 1603 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1604 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1605 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1606 B_AX_CMAC_CRPRT; 1607 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1608 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1609 B_AX_RMAC_CKEN; 1610 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1611 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1612 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1613 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1614 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1615 1616 if (en) { 1617 if (mac_idx == RTW89_MAC_1) { 1618 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1619 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1620 B_AX_R_SYM_ISO_CMAC12PP); 1621 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1622 B_AX_CMAC1_FEN); 1623 } 1624 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1625 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1626 } else { 1627 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1628 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1629 if (mac_idx == RTW89_MAC_1) { 1630 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1631 B_AX_CMAC1_FEN); 1632 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1633 B_AX_R_SYM_ISO_CMAC12PP); 1634 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1635 } 1636 } 1637 1638 return 0; 1639 } 1640 1641 static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1642 { 1643 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1644 u32 val32; 1645 1646 if (chip_id == RTL8852C) 1647 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1648 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1649 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1650 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1651 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1652 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1653 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1654 else 1655 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1656 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1657 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1658 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1659 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1660 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1661 B_AX_DMAC_CRPRT); 1662 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1663 1664 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1665 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1666 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1667 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1668 if (chip_id == RTL8852BT) 1669 val32 |= B_AX_AXIDMA_CLK_EN; 1670 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1671 1672 return 0; 1673 } 1674 1675 static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1676 { 1677 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1678 1679 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 1680 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1681 B_AX_OCP_L1_MASK); 1682 1683 return 0; 1684 } 1685 1686 static int sys_init_ax(struct rtw89_dev *rtwdev) 1687 { 1688 int ret; 1689 1690 ret = dmac_func_en_ax(rtwdev); 1691 if (ret) 1692 return ret; 1693 1694 ret = cmac_func_en_ax(rtwdev, 0, true); 1695 if (ret) 1696 return ret; 1697 1698 ret = chip_func_en_ax(rtwdev); 1699 if (ret) 1700 return ret; 1701 1702 return ret; 1703 } 1704 1705 const struct rtw89_mac_size_set rtw89_mac_size = { 1706 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1707 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0, 2, 32, 0, 0}, 1708 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0, 0, 256, 0, 0}, 1709 /* PCIE 64 */ 1710 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1711 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1712 /* 8852A USB */ 1713 .wde_size1 = {RTW89_WDE_PG_64, 768, 0,}, 1714 /* DLFW */ 1715 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1716 .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1717 /* PCIE 64 */ 1718 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1719 /* 8852B PCIE SCC */ 1720 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1721 /* DLFW */ 1722 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1723 .wde_size16_v1 = {RTW89_WDE_PG_64, 639, 1, 0,}, 1724 /* 8852C USB3.0 */ 1725 .wde_size17 = {RTW89_WDE_PG_64, 354, 30,}, 1726 /* 8852C DLFW */ 1727 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1728 .wde_size18_v1 = {RTW89_WDE_PG_64, 0, 640, 0,}, 1729 /* 8852C PCIE SCC */ 1730 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1731 .wde_size23 = {RTW89_WDE_PG_64, 1022, 2,}, 1732 /* 8852B USB2.0/USB3.0 SCC */ 1733 .wde_size25 = {RTW89_WDE_PG_64, 162, 94,}, 1734 /* 8852C USB2.0 */ 1735 .wde_size31 = {RTW89_WDE_PG_64, 384, 0,}, 1736 /* PCIE */ 1737 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1738 .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1739 /* 8852A USB */ 1740 .ple_size1 = {RTW89_PLE_PG_128, 3184, 16,}, 1741 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1742 /* DLFW */ 1743 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1744 /* PCIE 64 */ 1745 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1746 /* DLFW */ 1747 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1748 .ple_size9 = {RTW89_PLE_PG_128, 2288, 16,}, 1749 /* 8852C USB */ 1750 .ple_size17 = {RTW89_PLE_PG_128, 3368, 24,}, 1751 /* 8852C DLFW */ 1752 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1753 /* 8852C PCIE SCC */ 1754 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1755 .ple_size20_v1 = {RTW89_PLE_PG_128, 2554, 182, 40960,}, 1756 .ple_size22_v1 = {RTW89_PLE_PG_128, 2736, 0, 40960,}, 1757 /* 8852B USB2.0 SCC */ 1758 .ple_size32 = {RTW89_PLE_PG_128, 620, 20,}, 1759 /* 8852B USB3.0 SCC */ 1760 .ple_size33 = {RTW89_PLE_PG_128, 632, 8,}, 1761 /* 8852C USB2.0 */ 1762 .ple_size34 = {RTW89_PLE_PG_128, 3374, 18,}, 1763 /* PCIE 64 */ 1764 .wde_qt0 = {3792, 196, 0, 107,}, 1765 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1766 /* 8852A USB */ 1767 .wde_qt1 = {512, 196, 0, 60,}, 1768 .wde_qt3 = {0, 0, 0, 0,}, 1769 /* DLFW */ 1770 .wde_qt4 = {0, 0, 0, 0,}, 1771 /* PCIE 64 */ 1772 .wde_qt6 = {448, 48, 0, 16,}, 1773 /* 8852B PCIE SCC */ 1774 .wde_qt7 = {446, 48, 0, 16,}, 1775 /* 8852C USB3.0 */ 1776 .wde_qt16 = {344, 2, 0, 8,}, 1777 /* 8852C DLFW */ 1778 .wde_qt17 = {0, 0, 0, 0,}, 1779 /* 8852C PCIE SCC */ 1780 .wde_qt18 = {3228, 60, 0, 40,}, 1781 .wde_qt19_v1 = {613, 6, 0, 20,}, 1782 .wde_qt23 = {958, 48, 0, 16,}, 1783 /* 8852B USB2.0/USB3.0 SCC */ 1784 .wde_qt25 = {152, 2, 0, 8,}, 1785 /* 8852C USB2.0 */ 1786 .wde_qt31 = {338, 6, 0, 40,}, 1787 .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 1788 .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1789 /* PCIE SCC */ 1790 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1791 /* PCIE SCC */ 1792 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1793 .ple_qt5_v2 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,}, 1794 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1795 /* DLFW */ 1796 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1797 /* PCIE 64 */ 1798 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1799 /* 8852A USB SCC */ 1800 .ple_qt25 = {1536, 0, 16, 48, 13, 13, 360, 0, 32, 40, 8, 0,}, 1801 .ple_qt26 = {2654, 0, 1134, 48, 64, 13, 1478, 0, 64, 128, 120, 0,}, 1802 /* USB 52C USB3.0 */ 1803 .ple_qt42 = {1068, 0, 16, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,}, 1804 .ple_qt42_v2 = {91, 91, 32, 16, 19, 13, 91, 91, 44, 18, 1, 4, 0, 0,}, 1805 /* USB 52C USB3.0 */ 1806 .ple_qt43 = {3068, 0, 32, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,}, 1807 .ple_qt43_v2 = {645, 645, 32, 16, 2062, 2056, 2134, 2134, 2087, 2061, 1, 2047, 0, 0,}, 1808 /* DLFW 52C */ 1809 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1810 /* DLFW 52C */ 1811 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1812 /* 8852C PCIE SCC */ 1813 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1814 /* 8852C PCIE SCC */ 1815 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1816 .ple_qt57 = {147, 0, 16, 20, 13, 13, 178, 0, 32, 14, 8, 0,}, 1817 /* PCIE 64 */ 1818 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1819 .ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,}, 1820 /* USB2.0 52B SCC */ 1821 .ple_qt72 = {130, 0, 16, 48, 4, 13, 322, 0, 32, 14, 8, 0, 0,}, 1822 /* USB2.0 52B 92K */ 1823 .ple_qt73 = {130, 0, 32, 48, 37, 13, 355, 0, 65, 14, 24, 0, 0,}, 1824 /* USB3.0 52B 92K */ 1825 .ple_qt74 = {286, 0, 16, 48, 4, 13, 178, 0, 32, 14, 8, 0, 0,}, 1826 .ple_qt75 = {286, 0, 32, 48, 37, 13, 211, 0, 65, 14, 24, 0, 0,}, 1827 /* USB2.0 52C */ 1828 .ple_qt78 = {1560, 0, 16, 48, 13, 13, 390, 0, 32, 38, 8, 16, 0,}, 1829 /* USB2.0 52C */ 1830 .ple_qt79 = {1560, 0, 32, 48, 1253, 13, 1630, 0, 1272, 38, 120, 1256, 0,}, 1831 /* 8852A PCIE WOW */ 1832 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1833 /* 8852B PCIE WOW */ 1834 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1835 /* 8852BT PCIE WOW */ 1836 .ple_qt_52bt_wow = {147, 0, 32, 20, 1860, 13, 1929, 0, 1879, 14, 24, 0,}, 1837 /* 8851B PCIE WOW */ 1838 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1839 .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1840 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1841 .ple_rsvd_qt9 = {1, 44, 44, 6, 6, 6, 6, 69, 0, 0,}, 1842 .rsvd0_size0 = {212992, 0,}, 1843 .rsvd0_size6 = {40960, 0,}, 1844 .rsvd1_size0 = {587776, 2048,}, 1845 .rsvd1_size2 = {391168, 2048,}, 1846 .dle_input3 = {0, 0, 0, 16384, 0, 2048, 0, 0,}, 1847 .dle_input18 = {128, 128, 11454, 2048, 0, 2048, 24, 24,}, 1848 }; 1849 EXPORT_SYMBOL(rtw89_mac_size); 1850 1851 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1852 enum rtw89_qta_mode mode) 1853 { 1854 struct rtw89_mac_info *mac = &rtwdev->mac; 1855 const struct rtw89_dle_mem *cfg, *cfgs; 1856 1857 cfgs = rtwdev->chip->dle_mem[rtwdev->hci.dle_type]; 1858 if (!cfgs) 1859 return NULL; 1860 1861 cfg = &cfgs[mode]; 1862 if (cfg->mode != mode) { 1863 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1864 return NULL; 1865 } 1866 1867 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1868 mac->dle_info.dle_input = cfg->dle_input; 1869 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1870 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1871 mac->dle_info.qta_mode = mode; 1872 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1873 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1874 1875 return cfg; 1876 } 1877 1878 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1879 enum rtw89_mac_dle_rsvd_qt_type type, 1880 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1881 { 1882 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1883 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1884 1885 switch (type) { 1886 case DLE_RSVD_QT_MPDU_INFO: 1887 cfg->pktid = dle_info->ple_free_pg; 1888 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1889 break; 1890 case DLE_RSVD_QT_B0_CSI: 1891 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1892 cfg->pg_num = rsvd_qt->b0_csi; 1893 break; 1894 case DLE_RSVD_QT_B1_CSI: 1895 cfg->pktid = dle_info->ple_free_pg + 1896 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1897 cfg->pg_num = rsvd_qt->b1_csi; 1898 break; 1899 case DLE_RSVD_QT_B0_LMR: 1900 cfg->pktid = dle_info->ple_free_pg + 1901 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1902 cfg->pg_num = rsvd_qt->b0_lmr; 1903 break; 1904 case DLE_RSVD_QT_B1_LMR: 1905 cfg->pktid = dle_info->ple_free_pg + 1906 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1907 rsvd_qt->b0_lmr; 1908 cfg->pg_num = rsvd_qt->b1_lmr; 1909 break; 1910 case DLE_RSVD_QT_B0_FTM: 1911 cfg->pktid = dle_info->ple_free_pg + 1912 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1913 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1914 cfg->pg_num = rsvd_qt->b0_ftm; 1915 break; 1916 case DLE_RSVD_QT_B1_FTM: 1917 cfg->pktid = dle_info->ple_free_pg + 1918 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1919 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1920 cfg->pg_num = rsvd_qt->b1_ftm; 1921 break; 1922 default: 1923 return -EINVAL; 1924 } 1925 1926 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1927 1928 return 0; 1929 } 1930 1931 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1932 { 1933 struct rtw89_mac_dle_dfi_qempty qempty; 1934 u32 grpnum, qtmp, val32, msk32; 1935 int i, j, ret; 1936 1937 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1938 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1939 1940 for (i = 0; i < grpnum; i++) { 1941 qempty.grpsel = i; 1942 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1943 if (ret) { 1944 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1945 return false; 1946 } 1947 qtmp = qempty.qempty; 1948 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1949 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 1950 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1951 return false; 1952 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1953 } 1954 } 1955 1956 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1957 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1958 if (ret) { 1959 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1960 return false; 1961 } 1962 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1963 if ((qempty.qempty & msk32) != msk32) 1964 return false; 1965 1966 if (rtwdev->dbcc_en) { 1967 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1968 if ((qempty.qempty & msk32) != msk32) 1969 return false; 1970 } 1971 1972 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1973 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1974 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1975 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1976 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1977 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1978 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1979 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1980 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1981 1982 return (val32 & msk32) == msk32; 1983 } 1984 1985 static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1986 { 1987 const struct rtw89_dle_size *wde = cfg->wde_size; 1988 const struct rtw89_dle_size *ple = cfg->ple_size; 1989 u32 used; 1990 1991 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1992 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1993 1994 if (cfg->rsvd0_size && cfg->rsvd1_size) { 1995 used += cfg->rsvd0_size->size; 1996 used += cfg->rsvd1_size->size; 1997 } 1998 1999 return used; 2000 } 2001 2002 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 2003 enum rtw89_qta_mode mode) 2004 { 2005 u32 size = rtwdev->chip->fifo_size; 2006 2007 if (mode == RTW89_QTA_SCC) 2008 size -= rtwdev->chip->dle_scc_rsvd_size; 2009 2010 return size; 2011 } 2012 2013 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 2014 { 2015 if (enable) 2016 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 2017 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 2018 else 2019 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 2020 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 2021 } 2022 2023 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 2024 { 2025 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 2026 2027 if (enable) { 2028 if (rtwdev->chip->chip_id == RTL8851B) 2029 val |= B_AX_AXIDMA_CLK_EN; 2030 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 2031 } else { 2032 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 2033 } 2034 } 2035 2036 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 2037 { 2038 const struct rtw89_dle_size *size_cfg; 2039 u32 val; 2040 u8 bound = 0; 2041 2042 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 2043 size_cfg = cfg->wde_size; 2044 2045 switch (size_cfg->pge_size) { 2046 default: 2047 case RTW89_WDE_PG_64: 2048 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 2049 B_AX_WDE_PAGE_SEL_MASK); 2050 break; 2051 case RTW89_WDE_PG_128: 2052 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 2053 B_AX_WDE_PAGE_SEL_MASK); 2054 break; 2055 case RTW89_WDE_PG_256: 2056 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 2057 return -EINVAL; 2058 } 2059 2060 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 2061 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 2062 B_AX_WDE_FREE_PAGE_NUM_MASK); 2063 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 2064 2065 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 2066 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 2067 * size_cfg->pge_size / DLE_BOUND_UNIT; 2068 size_cfg = cfg->ple_size; 2069 2070 switch (size_cfg->pge_size) { 2071 default: 2072 case RTW89_PLE_PG_64: 2073 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 2074 return -EINVAL; 2075 case RTW89_PLE_PG_128: 2076 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 2077 B_AX_PLE_PAGE_SEL_MASK); 2078 break; 2079 case RTW89_PLE_PG_256: 2080 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 2081 B_AX_PLE_PAGE_SEL_MASK); 2082 break; 2083 } 2084 2085 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 2086 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 2087 B_AX_PLE_FREE_PAGE_NUM_MASK); 2088 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 2089 2090 return 0; 2091 } 2092 2093 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 2094 { 2095 u32 reg, mask; 2096 u32 ini; 2097 2098 if (wde_or_ple) { 2099 reg = R_AX_WDE_INI_STATUS; 2100 mask = WDE_MGN_INI_RDY; 2101 } else { 2102 reg = R_AX_PLE_INI_STATUS; 2103 mask = PLE_MGN_INI_RDY; 2104 } 2105 2106 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 2107 2000, false, rtwdev, reg); 2108 } 2109 2110 #define INVALID_QT_WCPU U16_MAX 2111 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 2112 do { \ 2113 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 2114 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 2115 rtw89_write32(rtwdev, \ 2116 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 2117 val); \ 2118 } while (0) 2119 #define SET_QUOTA(_x, _module, _idx) \ 2120 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 2121 2122 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 2123 const struct rtw89_wde_quota *min_cfg, 2124 const struct rtw89_wde_quota *max_cfg, 2125 u16 ext_wde_min_qt_wcpu) 2126 { 2127 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 2128 ext_wde_min_qt_wcpu : min_cfg->wcpu; 2129 u32 val; 2130 2131 SET_QUOTA(hif, WDE, 0); 2132 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 2133 SET_QUOTA(pkt_in, WDE, 3); 2134 SET_QUOTA(cpu_io, WDE, 4); 2135 } 2136 2137 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 2138 const struct rtw89_ple_quota *min_cfg, 2139 const struct rtw89_ple_quota *max_cfg) 2140 { 2141 u32 val; 2142 2143 SET_QUOTA(cma0_tx, PLE, 0); 2144 SET_QUOTA(cma1_tx, PLE, 1); 2145 SET_QUOTA(c2h, PLE, 2); 2146 SET_QUOTA(h2c, PLE, 3); 2147 SET_QUOTA(wcpu, PLE, 4); 2148 SET_QUOTA(mpdu_proc, PLE, 5); 2149 SET_QUOTA(cma0_dma, PLE, 6); 2150 SET_QUOTA(cma1_dma, PLE, 7); 2151 SET_QUOTA(bb_rpt, PLE, 8); 2152 SET_QUOTA(wd_rel, PLE, 9); 2153 SET_QUOTA(cpu_io, PLE, 10); 2154 if (rtwdev->chip->chip_id == RTL8852C) 2155 SET_QUOTA(tx_rpt, PLE, 11); 2156 } 2157 2158 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 2159 { 2160 const struct rtw89_ple_quota *min_cfg, *max_cfg; 2161 const struct rtw89_dle_mem *cfg; 2162 u32 val; 2163 2164 if (rtwdev->chip->chip_id == RTL8852C) 2165 return 0; 2166 2167 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2168 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2169 return -EINVAL; 2170 } 2171 2172 if (wow) 2173 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2174 else 2175 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2176 if (!cfg) { 2177 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2178 return -EINVAL; 2179 } 2180 2181 min_cfg = cfg->ple_min_qt; 2182 max_cfg = cfg->ple_max_qt; 2183 SET_QUOTA(cma0_dma, PLE, 6); 2184 SET_QUOTA(cma1_dma, PLE, 7); 2185 2186 return 0; 2187 } 2188 #undef SET_QUOTA 2189 2190 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2191 { 2192 const struct rtw89_chip_info *chip = rtwdev->chip; 2193 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2194 2195 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2196 return; 2197 2198 /* 8852C enable B_AX_UC_MGNT_DEC by default */ 2199 if (chip->chip_id == RTL8852C) 2200 msk32 = B_AX_BMC_MGNT_DEC; 2201 2202 if (enable) 2203 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2204 else 2205 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2206 } 2207 2208 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2209 const struct rtw89_dle_mem *cfg, 2210 u16 ext_wde_min_qt_wcpu) 2211 { 2212 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2213 2214 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2215 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2216 } 2217 2218 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2219 enum rtw89_qta_mode ext_mode) 2220 { 2221 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2222 const struct rtw89_dle_mem *cfg, *ext_cfg; 2223 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2224 int ret; 2225 2226 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2227 if (ret) 2228 return ret; 2229 2230 cfg = get_dle_mem_cfg(rtwdev, mode); 2231 if (!cfg) { 2232 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2233 ret = -EINVAL; 2234 goto error; 2235 } 2236 2237 if (mode == RTW89_QTA_DLFW) { 2238 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2239 if (!ext_cfg) { 2240 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2241 ext_mode); 2242 ret = -EINVAL; 2243 goto error; 2244 } 2245 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2246 } 2247 2248 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2249 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2250 ret = -EINVAL; 2251 goto error; 2252 } 2253 2254 mac->dle_func_en(rtwdev, false); 2255 mac->dle_clk_en(rtwdev, true); 2256 2257 ret = mac->dle_mix_cfg(rtwdev, cfg); 2258 if (ret) { 2259 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2260 goto error; 2261 } 2262 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2263 2264 mac->dle_func_en(rtwdev, true); 2265 2266 ret = mac->chk_dle_rdy(rtwdev, true); 2267 if (ret) { 2268 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2269 return ret; 2270 } 2271 2272 ret = mac->chk_dle_rdy(rtwdev, false); 2273 if (ret) { 2274 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2275 return ret; 2276 } 2277 2278 return 0; 2279 error: 2280 mac->dle_func_en(rtwdev, false); 2281 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2282 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2283 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2284 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2285 2286 return ret; 2287 } 2288 2289 static int preload_init_set_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 2290 enum rtw89_qta_mode mode) 2291 { 2292 u32 reg, max_preld_size, min_rsvd_size; 2293 2294 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2295 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2296 reg = mac_idx == RTW89_MAC_0 ? 2297 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2298 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2299 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2300 2301 min_rsvd_size = PRELD_AMSDU_SIZE; 2302 reg = mac_idx == RTW89_MAC_0 ? 2303 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2304 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2305 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2306 2307 return 0; 2308 } 2309 2310 static bool is_qta_poh(struct rtw89_dev *rtwdev) 2311 { 2312 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2313 } 2314 2315 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2316 enum rtw89_qta_mode mode) 2317 { 2318 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2319 const struct rtw89_chip_info *chip = rtwdev->chip; 2320 2321 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) || 2322 !is_qta_poh(rtwdev)) 2323 return 0; 2324 2325 return mac->preload_init(rtwdev, mac_idx, mode); 2326 } 2327 2328 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2329 { 2330 u32 msk32; 2331 u32 val32; 2332 2333 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2334 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2335 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2336 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2337 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2338 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2339 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2340 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2341 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2342 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2343 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2344 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2345 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2346 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2347 2348 if ((val32 & msk32) == msk32) 2349 return true; 2350 2351 return false; 2352 } 2353 2354 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2355 { 2356 const struct rtw89_chip_info *chip = rtwdev->chip; 2357 2358 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2359 return; 2360 2361 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2362 SS2F_PATH_WLCPU); 2363 } 2364 2365 static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2366 { 2367 u32 p_val; 2368 u8 val; 2369 int ret; 2370 2371 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2372 if (ret) 2373 return ret; 2374 2375 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2376 val |= B_AX_SS_EN; 2377 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2378 2379 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2380 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2381 if (ret) { 2382 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2383 return ret; 2384 } 2385 2386 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2387 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2388 2389 _patch_ss2f_path(rtwdev); 2390 2391 return 0; 2392 } 2393 2394 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2395 { 2396 int ret; 2397 2398 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2399 if (ret) 2400 return ret; 2401 2402 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2403 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2404 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2405 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2406 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2407 2408 return 0; 2409 } 2410 2411 static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2412 { 2413 const struct rtw89_chip_info *chip = rtwdev->chip; 2414 u32 val = 0; 2415 int ret; 2416 2417 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2418 if (ret) 2419 return ret; 2420 2421 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2422 /* init clock */ 2423 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2424 /* init TX encryption */ 2425 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2426 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2427 if (chip->chip_id == RTL8852C) 2428 val |= B_AX_UC_MGNT_DEC; 2429 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2430 chip->chip_id == RTL8851B || 2431 (chip->chip_id == RTL8852C && rtwdev->hci.type == RTW89_HCI_TYPE_USB)) 2432 val &= ~B_AX_TX_PARTIAL_MODE; 2433 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2434 2435 /* init MIC ICV append */ 2436 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2437 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2438 2439 /* option init */ 2440 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2441 2442 if (chip->chip_id == RTL8852C) 2443 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2444 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2445 2446 return 0; 2447 } 2448 2449 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2450 { 2451 int ret; 2452 2453 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2454 if (ret) { 2455 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2456 return ret; 2457 } 2458 2459 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2460 if (ret) { 2461 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2462 return ret; 2463 } 2464 2465 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2466 if (ret) { 2467 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2468 return ret; 2469 } 2470 2471 ret = sta_sch_init_ax(rtwdev); 2472 if (ret) { 2473 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2474 return ret; 2475 } 2476 2477 ret = mpdu_proc_init_ax(rtwdev); 2478 if (ret) { 2479 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2480 return ret; 2481 } 2482 2483 ret = sec_eng_init_ax(rtwdev); 2484 if (ret) { 2485 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2486 return ret; 2487 } 2488 2489 return ret; 2490 } 2491 2492 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2493 { 2494 u32 val, reg; 2495 u16 p_val; 2496 int ret; 2497 2498 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2499 if (ret) 2500 return ret; 2501 2502 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2503 2504 val = rtw89_read32(rtwdev, reg); 2505 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2506 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2507 rtw89_write32(rtwdev, reg, val); 2508 2509 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2510 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2511 if (ret) { 2512 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2513 return ret; 2514 } 2515 2516 return 0; 2517 } 2518 2519 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2520 { 2521 int ret; 2522 u32 reg; 2523 u32 val; 2524 2525 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2526 if (ret) 2527 return ret; 2528 2529 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2530 if (rtwdev->chip->chip_id == RTL8852C) 2531 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2532 SIFS_MACTXEN_T1_V1); 2533 else 2534 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2535 SIFS_MACTXEN_T1); 2536 2537 if (rtw89_is_rtl885xb(rtwdev)) { 2538 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2539 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2540 } 2541 2542 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2543 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2544 2545 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2546 if (rtwdev->chip->chip_id == RTL8852C) { 2547 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2548 B_AX_TX_PARTIAL_MODE); 2549 if (!val) 2550 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2551 SCH_PREBKF_24US); 2552 } else { 2553 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2554 SCH_PREBKF_24US); 2555 } 2556 2557 return 0; 2558 } 2559 2560 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2561 enum rtw89_machdr_frame_type type, 2562 enum rtw89_mac_fwd_target fwd_target, 2563 u8 mac_idx) 2564 { 2565 u32 reg; 2566 u32 val; 2567 2568 switch (fwd_target) { 2569 case RTW89_FWD_DONT_CARE: 2570 val = RX_FLTR_FRAME_DROP; 2571 break; 2572 case RTW89_FWD_TO_HOST: 2573 val = RX_FLTR_FRAME_TO_HOST; 2574 break; 2575 case RTW89_FWD_TO_WLAN_CPU: 2576 val = RX_FLTR_FRAME_TO_WLCPU; 2577 break; 2578 default: 2579 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2580 return -EINVAL; 2581 } 2582 2583 switch (type) { 2584 case RTW89_MGNT: 2585 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2586 break; 2587 case RTW89_CTRL: 2588 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2589 break; 2590 case RTW89_DATA: 2591 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2592 break; 2593 default: 2594 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2595 return -EINVAL; 2596 } 2597 rtw89_write32(rtwdev, reg, val); 2598 2599 return 0; 2600 } 2601 2602 void rtw89_mac_set_rx_fltr(struct rtw89_dev *rtwdev, u8 mac_idx, u32 rx_fltr) 2603 { 2604 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2605 u32 reg; 2606 u32 val; 2607 2608 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, mac_idx); 2609 2610 val = rtw89_read32(rtwdev, reg); 2611 /* B_AX_RX_FLTR_CFG_MASK is not a consecutive bit mask */ 2612 val = (val & ~B_AX_RX_FLTR_CFG_MASK) | (rx_fltr & B_AX_RX_FLTR_CFG_MASK); 2613 rtw89_write32(rtwdev, reg, val); 2614 } 2615 2616 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2617 { 2618 int ret, i; 2619 u32 mac_ftlr, plcp_ftlr; 2620 2621 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2622 if (ret) 2623 return ret; 2624 2625 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2626 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2627 mac_idx); 2628 if (ret) 2629 return ret; 2630 } 2631 mac_ftlr = rtwdev->hal.rx_fltr; 2632 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2633 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2634 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2635 B_AX_HE_SIGB_CRC_CHK; 2636 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2637 mac_ftlr); 2638 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2639 plcp_ftlr); 2640 2641 return 0; 2642 } 2643 2644 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2645 { 2646 u32 reg, val32; 2647 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2648 2649 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2650 B_AX_RSP_CHK_BASIC_NAV; 2651 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2652 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2653 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2654 2655 switch (rtwdev->chip->chip_id) { 2656 case RTL8852A: 2657 case RTL8852B: 2658 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2659 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2660 rtw89_write32(rtwdev, reg, val32); 2661 2662 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2663 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2664 rtw89_write32(rtwdev, reg, val32); 2665 break; 2666 default: 2667 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2668 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2669 rtw89_write32(rtwdev, reg, val32); 2670 2671 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2672 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2673 rtw89_write32(rtwdev, reg, val32); 2674 break; 2675 } 2676 } 2677 2678 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2679 { 2680 u32 val, reg; 2681 int ret; 2682 2683 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2684 if (ret) 2685 return ret; 2686 2687 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2688 val = rtw89_read32(rtwdev, reg); 2689 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2690 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2691 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2692 B_AX_CTN_CHK_INTRA_NAV | 2693 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2694 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2695 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2696 B_AX_CTN_CHK_CCA_P20); 2697 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2698 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2699 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2700 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2701 B_AX_SIFS_CHK_EDCCA); 2702 2703 rtw89_write32(rtwdev, reg, val); 2704 2705 _patch_dis_resp_chk(rtwdev, mac_idx); 2706 2707 return 0; 2708 } 2709 2710 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2711 { 2712 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2713 B_AX_WMAC_TF_UP_NAV_EN | 2714 B_AX_WMAC_NAV_UPPER_EN); 2715 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2716 2717 return 0; 2718 } 2719 2720 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2721 { 2722 u32 reg; 2723 int ret; 2724 2725 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2726 if (ret) 2727 return ret; 2728 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2729 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2730 2731 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2732 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2733 2734 return 0; 2735 } 2736 2737 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2738 { 2739 u32 reg; 2740 int ret; 2741 2742 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2743 if (ret) 2744 return ret; 2745 2746 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2747 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2748 2749 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2750 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2751 2752 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2753 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2754 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2755 2756 return 0; 2757 } 2758 2759 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2760 { 2761 const struct rtw89_chip_info *chip = rtwdev->chip; 2762 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2763 u32 reg, val, sifs; 2764 int ret; 2765 2766 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2767 if (ret) 2768 return ret; 2769 2770 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2771 val = rtw89_read32(rtwdev, reg); 2772 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2773 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2774 2775 switch (rtwdev->chip->chip_id) { 2776 case RTL8852A: 2777 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2778 break; 2779 case RTL8851B: 2780 case RTL8852B: 2781 case RTL8852BT: 2782 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2783 break; 2784 default: 2785 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2786 break; 2787 } 2788 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2789 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2790 rtw89_write32(rtwdev, reg, val); 2791 2792 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2793 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2794 2795 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2796 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2797 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2798 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2799 2800 return 0; 2801 } 2802 2803 static void rst_bacam(struct rtw89_dev *rtwdev) 2804 { 2805 u32 val32; 2806 int ret; 2807 2808 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2809 S_AX_BACAM_RST_ALL); 2810 2811 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2812 1, 1000, false, 2813 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2814 if (ret) 2815 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2816 } 2817 2818 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2819 { 2820 #define TRXCFG_RMAC_CCA_TO 32 2821 #define TRXCFG_RMAC_DATA_TO 15 2822 #define RX_MAX_LEN_UNIT 512 2823 #define PLD_RLS_MAX_PG 127 2824 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2825 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2826 int ret; 2827 u32 reg, rx_max_len, rx_qta; 2828 u16 val; 2829 2830 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2831 if (ret) 2832 return ret; 2833 2834 if (mac_idx == RTW89_MAC_0) 2835 rst_bacam(rtwdev); 2836 2837 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2838 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2839 2840 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2841 val = rtw89_read16(rtwdev, reg); 2842 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2843 B_AX_RX_DLK_DATA_TIME_MASK); 2844 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2845 B_AX_RX_DLK_CCA_TIME_MASK); 2846 if (chip_id == RTL8852BT) 2847 val |= B_AX_RX_DLK_RST_EN; 2848 rtw89_write16(rtwdev, reg, val); 2849 2850 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2851 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2852 2853 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2854 if (mac_idx == RTW89_MAC_0) 2855 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2856 else 2857 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2858 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2859 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2860 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2861 rx_max_len /= RX_MAX_LEN_UNIT; 2862 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2863 2864 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) { 2865 rtw89_write16_mask(rtwdev, 2866 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2867 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2868 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2869 BIT(12)); 2870 } 2871 2872 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2873 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2874 2875 return ret; 2876 } 2877 2878 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2879 { 2880 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2881 u32 val, reg; 2882 int ret; 2883 2884 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2885 if (ret) 2886 return ret; 2887 2888 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2889 val = rtw89_read32(rtwdev, reg); 2890 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2891 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2892 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2893 rtw89_write32(rtwdev, reg, val); 2894 2895 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2896 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2897 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2898 } 2899 2900 return 0; 2901 } 2902 2903 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2904 { 2905 const struct rtw89_dle_mem *cfg; 2906 2907 cfg = get_dle_mem_cfg(rtwdev, mode); 2908 if (!cfg) { 2909 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2910 return false; 2911 } 2912 2913 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2914 } 2915 2916 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2917 { 2918 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2919 u32 val, reg; 2920 int ret; 2921 2922 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2923 if (ret) 2924 return ret; 2925 2926 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2927 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2928 val = rtw89_read32(rtwdev, reg); 2929 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2930 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2931 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2932 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2933 val |= B_AX_HW_CTS2SELF_EN; 2934 rtw89_write32(rtwdev, reg, val); 2935 2936 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2937 val = rtw89_read32(rtwdev, reg); 2938 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2939 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2940 rtw89_write32(rtwdev, reg, val); 2941 } 2942 2943 if (mac_idx == RTW89_MAC_0) { 2944 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2945 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2946 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2947 B_AX_PTCL_TRIGGER_SS_EN_0 | 2948 B_AX_PTCL_TRIGGER_SS_EN_1 | 2949 B_AX_PTCL_TRIGGER_SS_EN_UL); 2950 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2951 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2952 } else if (mac_idx == RTW89_MAC_1) { 2953 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2954 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2955 } 2956 2957 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2958 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_VHT_0, mac_idx); 2959 rtw89_write32_mask(rtwdev, reg, 2960 B_AX_AMPDU_MAX_LEN_VHT_MASK, 0x3FF80); 2961 } 2962 2963 return 0; 2964 } 2965 2966 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2967 { 2968 u32 reg; 2969 int ret; 2970 2971 if (!rtw89_is_rtl885xb(rtwdev)) 2972 return 0; 2973 2974 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2975 if (ret) 2976 return ret; 2977 2978 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2979 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2980 2981 return 0; 2982 } 2983 2984 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2985 { 2986 int ret; 2987 2988 ret = scheduler_init_ax(rtwdev, mac_idx); 2989 if (ret) { 2990 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2991 return ret; 2992 } 2993 2994 ret = addr_cam_init_ax(rtwdev, mac_idx); 2995 if (ret) { 2996 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2997 ret); 2998 return ret; 2999 } 3000 3001 ret = rx_fltr_init_ax(rtwdev, mac_idx); 3002 if (ret) { 3003 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 3004 ret); 3005 return ret; 3006 } 3007 3008 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 3009 if (ret) { 3010 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 3011 ret); 3012 return ret; 3013 } 3014 3015 ret = nav_ctrl_init_ax(rtwdev); 3016 if (ret) { 3017 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 3018 ret); 3019 return ret; 3020 } 3021 3022 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 3023 if (ret) { 3024 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 3025 mac_idx, ret); 3026 return ret; 3027 } 3028 3029 ret = tmac_init_ax(rtwdev, mac_idx); 3030 if (ret) { 3031 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 3032 return ret; 3033 } 3034 3035 ret = trxptcl_init_ax(rtwdev, mac_idx); 3036 if (ret) { 3037 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 3038 return ret; 3039 } 3040 3041 ret = rmac_init_ax(rtwdev, mac_idx); 3042 if (ret) { 3043 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 3044 return ret; 3045 } 3046 3047 ret = cmac_com_init_ax(rtwdev, mac_idx); 3048 if (ret) { 3049 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 3050 return ret; 3051 } 3052 3053 ret = ptcl_init_ax(rtwdev, mac_idx); 3054 if (ret) { 3055 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 3056 return ret; 3057 } 3058 3059 ret = cmac_dma_init_ax(rtwdev, mac_idx); 3060 if (ret) { 3061 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 3062 return ret; 3063 } 3064 3065 return ret; 3066 } 3067 3068 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 3069 struct rtw89_mac_c2h_info *c2h_info, u8 part_num) 3070 { 3071 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3072 const struct rtw89_chip_info *chip = rtwdev->chip; 3073 struct rtw89_mac_h2c_info h2c_info = {}; 3074 enum rtw89_mac_c2h_type c2h_type; 3075 u8 content_len; 3076 int ret; 3077 3078 if (chip->chip_gen == RTW89_CHIP_AX) 3079 content_len = 0; 3080 else 3081 content_len = 2; 3082 3083 switch (part_num) { 3084 case 0: 3085 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP; 3086 break; 3087 case 1: 3088 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1; 3089 break; 3090 default: 3091 return -EINVAL; 3092 } 3093 3094 mac->cnv_efuse_state(rtwdev, false); 3095 3096 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 3097 h2c_info.content_len = content_len; 3098 h2c_info.u.hdr.w0 = u32_encode_bits(part_num, RTW89_H2CREG_GET_FEATURE_PART_NUM); 3099 3100 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 3101 if (ret) 3102 goto out; 3103 3104 if (c2h_info->id != c2h_type) 3105 ret = -EINVAL; 3106 3107 out: 3108 mac->cnv_efuse_state(rtwdev, true); 3109 3110 return ret; 3111 } 3112 3113 static int rtw89_mac_setup_phycap_part0(struct rtw89_dev *rtwdev) 3114 { 3115 const struct rtw89_chip_info *chip = rtwdev->chip; 3116 const struct rtw89_c2hreg_phycap *phycap; 3117 struct rtw89_efuse *efuse = &rtwdev->efuse; 3118 struct rtw89_mac_c2h_info c2h_info = {}; 3119 struct rtw89_hal *hal = &rtwdev->hal; 3120 u8 protocol; 3121 u8 tx_nss; 3122 u8 rx_nss; 3123 u8 tx_ant; 3124 u8 rx_ant; 3125 int ret; 3126 3127 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 0); 3128 if (ret) 3129 return ret; 3130 3131 phycap = &c2h_info.u.phycap; 3132 3133 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 3134 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 3135 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 3136 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 3137 3138 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 3139 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 3140 3141 if (tx_ant == 1) 3142 hal->antenna_tx = RF_B; 3143 if (rx_ant == 1) 3144 hal->antenna_rx = RF_B; 3145 3146 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 3147 hal->antenna_tx = RF_B; 3148 hal->tx_path_diversity = true; 3149 } 3150 3151 if (chip->rf_path_num == 1) { 3152 hal->antenna_tx = RF_A; 3153 hal->antenna_rx = RF_A; 3154 if ((efuse->rfe_type % 3) == 2) 3155 hal->ant_diversity = true; 3156 } 3157 3158 rtw89_debug(rtwdev, RTW89_DBG_FW, 3159 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 3160 hal->tx_nss, tx_nss, chip->tx_nss, 3161 hal->rx_nss, rx_nss, chip->rx_nss); 3162 rtw89_debug(rtwdev, RTW89_DBG_FW, 3163 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 3164 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 3165 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 3166 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 3167 3168 protocol = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_PROT); 3169 if (protocol < RTW89_C2HREG_PHYCAP_W1_PROT_11BE) 3170 hal->no_eht = true; 3171 3172 return 0; 3173 } 3174 3175 static int rtw89_mac_setup_phycap_part1(struct rtw89_dev *rtwdev) 3176 { 3177 const struct rtw89_chip_variant *variant = rtwdev->variant; 3178 const struct rtw89_c2hreg_phycap *phycap; 3179 struct rtw89_mac_c2h_info c2h_info = {}; 3180 struct rtw89_hal *hal = &rtwdev->hal; 3181 u8 qam_raw, qam; 3182 int ret; 3183 3184 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 1); 3185 if (ret) 3186 return ret; 3187 3188 phycap = &c2h_info.u.phycap; 3189 3190 qam_raw = u32_get_bits(phycap->w2, RTW89_C2HREG_PHYCAP_P1_W2_QAM); 3191 3192 switch (qam_raw) { 3193 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_256: 3194 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024: 3195 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096: 3196 qam = qam_raw; 3197 break; 3198 default: 3199 qam = RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096; 3200 break; 3201 } 3202 3203 if ((variant && variant->no_mcs_12_13) || 3204 qam <= RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024) 3205 hal->no_mcs_12_13 = true; 3206 3207 rtw89_debug(rtwdev, RTW89_DBG_FW, "phycap qam=%d/%d no_mcs_12_13=%d\n", 3208 qam_raw, qam, hal->no_mcs_12_13); 3209 3210 return 0; 3211 } 3212 3213 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 3214 { 3215 const struct rtw89_chip_info *chip = rtwdev->chip; 3216 int ret; 3217 3218 ret = rtw89_mac_setup_phycap_part0(rtwdev); 3219 if (ret) 3220 return ret; 3221 3222 if (chip->chip_gen == RTW89_CHIP_AX || 3223 RTW89_CHK_FW_FEATURE(NO_PHYCAP_P1, &rtwdev->fw)) 3224 return 0; 3225 3226 return rtw89_mac_setup_phycap_part1(rtwdev); 3227 } 3228 3229 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 3230 u16 tx_en_u16, u16 mask_u16) 3231 { 3232 struct rtw89_mac_c2h_info c2h_info = {0}; 3233 struct rtw89_mac_h2c_info h2c_info = {0}; 3234 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 3235 int ret; 3236 3237 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 3238 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 3239 3240 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 3241 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 3242 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 3243 3244 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 3245 if (ret) 3246 return ret; 3247 3248 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 3249 return -EINVAL; 3250 3251 return 0; 3252 } 3253 3254 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 3255 u16 tx_en, u16 tx_en_mask) 3256 { 3257 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 3258 u16 val; 3259 int ret; 3260 3261 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3262 if (ret) 3263 return ret; 3264 3265 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3266 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 3267 tx_en, tx_en_mask); 3268 3269 val = rtw89_read16(rtwdev, reg); 3270 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3271 rtw89_write16(rtwdev, reg, val); 3272 3273 return 0; 3274 } 3275 3276 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3277 u32 tx_en, u32 tx_en_mask) 3278 { 3279 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3280 u32 val; 3281 int ret; 3282 3283 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3284 if (ret) 3285 return ret; 3286 3287 val = rtw89_read32(rtwdev, reg); 3288 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3289 rtw89_write32(rtwdev, reg, val); 3290 3291 return 0; 3292 } 3293 3294 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3295 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3296 { 3297 int ret; 3298 3299 *tx_en = rtw89_read16(rtwdev, 3300 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3301 3302 switch (sel) { 3303 case RTW89_SCH_TX_SEL_ALL: 3304 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3305 B_AX_CTN_TXEN_ALL_MASK); 3306 if (ret) 3307 return ret; 3308 break; 3309 case RTW89_SCH_TX_SEL_HIQ: 3310 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3311 0, B_AX_CTN_TXEN_HGQ); 3312 if (ret) 3313 return ret; 3314 break; 3315 case RTW89_SCH_TX_SEL_MG0: 3316 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3317 0, B_AX_CTN_TXEN_MGQ); 3318 if (ret) 3319 return ret; 3320 break; 3321 case RTW89_SCH_TX_SEL_MACID: 3322 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3323 B_AX_CTN_TXEN_ALL_MASK); 3324 if (ret) 3325 return ret; 3326 break; 3327 default: 3328 return 0; 3329 } 3330 3331 return 0; 3332 } 3333 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3334 3335 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3336 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3337 { 3338 int ret; 3339 3340 *tx_en = rtw89_read32(rtwdev, 3341 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3342 3343 switch (sel) { 3344 case RTW89_SCH_TX_SEL_ALL: 3345 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3346 B_AX_CTN_TXEN_ALL_MASK_V1); 3347 if (ret) 3348 return ret; 3349 break; 3350 case RTW89_SCH_TX_SEL_HIQ: 3351 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3352 0, B_AX_CTN_TXEN_HGQ); 3353 if (ret) 3354 return ret; 3355 break; 3356 case RTW89_SCH_TX_SEL_MG0: 3357 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3358 0, B_AX_CTN_TXEN_MGQ); 3359 if (ret) 3360 return ret; 3361 break; 3362 case RTW89_SCH_TX_SEL_MACID: 3363 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3364 B_AX_CTN_TXEN_ALL_MASK_V1); 3365 if (ret) 3366 return ret; 3367 break; 3368 default: 3369 return 0; 3370 } 3371 3372 return 0; 3373 } 3374 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3375 3376 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3377 { 3378 int ret; 3379 3380 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3381 if (ret) 3382 return ret; 3383 3384 return 0; 3385 } 3386 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3387 3388 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3389 { 3390 int ret; 3391 3392 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3393 B_AX_CTN_TXEN_ALL_MASK_V1); 3394 if (ret) 3395 return ret; 3396 3397 return 0; 3398 } 3399 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3400 3401 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3402 { 3403 u32 val, reg; 3404 int ret; 3405 3406 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3407 val = buf_len; 3408 val |= B_AX_WD_BUF_REQ_EXEC; 3409 rtw89_write32(rtwdev, reg, val); 3410 3411 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3412 3413 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3414 1, 2000, false, rtwdev, reg); 3415 if (ret) 3416 return ret; 3417 3418 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3419 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3420 return -ENOENT; 3421 3422 return 0; 3423 } 3424 3425 static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3426 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3427 { 3428 u32 val, cmd_type, reg; 3429 int ret; 3430 3431 cmd_type = ctrl_para->cmd_type; 3432 3433 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3434 val = 0; 3435 val = u32_replace_bits(val, ctrl_para->start_pktid, 3436 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3437 val = u32_replace_bits(val, ctrl_para->end_pktid, 3438 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3439 rtw89_write32(rtwdev, reg, val); 3440 3441 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3442 val = 0; 3443 val = u32_replace_bits(val, ctrl_para->src_pid, 3444 B_AX_CPUQ_OP_SRC_PID_MASK); 3445 val = u32_replace_bits(val, ctrl_para->src_qid, 3446 B_AX_CPUQ_OP_SRC_QID_MASK); 3447 val = u32_replace_bits(val, ctrl_para->dst_pid, 3448 B_AX_CPUQ_OP_DST_PID_MASK); 3449 val = u32_replace_bits(val, ctrl_para->dst_qid, 3450 B_AX_CPUQ_OP_DST_QID_MASK); 3451 rtw89_write32(rtwdev, reg, val); 3452 3453 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3454 val = 0; 3455 val = u32_replace_bits(val, cmd_type, 3456 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3457 val = u32_replace_bits(val, ctrl_para->macid, 3458 B_AX_CPUQ_OP_MACID_MASK); 3459 val = u32_replace_bits(val, ctrl_para->pkt_num, 3460 B_AX_CPUQ_OP_PKTNUM_MASK); 3461 val |= B_AX_WD_CPUQ_OP_EXEC; 3462 rtw89_write32(rtwdev, reg, val); 3463 3464 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3465 3466 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3467 1, 2000, false, rtwdev, reg); 3468 if (ret) 3469 return ret; 3470 3471 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3472 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3473 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3474 3475 return 0; 3476 } 3477 3478 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3479 bool band1_en) 3480 { 3481 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3482 const struct rtw89_dle_mem *cfg; 3483 3484 cfg = get_dle_mem_cfg(rtwdev, mode); 3485 if (!cfg) { 3486 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3487 return -EINVAL; 3488 } 3489 3490 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3491 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3492 return -EINVAL; 3493 } 3494 3495 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3496 3497 return mac->dle_quota_change(rtwdev, band1_en); 3498 } 3499 3500 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3501 { 3502 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3503 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3504 u16 pkt_id; 3505 int ret; 3506 3507 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3508 if (ret) { 3509 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3510 return ret; 3511 } 3512 3513 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3514 ctrl_para.start_pktid = pkt_id; 3515 ctrl_para.end_pktid = pkt_id; 3516 ctrl_para.pkt_num = 0; 3517 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3518 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3519 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3520 if (ret) { 3521 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3522 return -EFAULT; 3523 } 3524 3525 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3526 if (ret) { 3527 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3528 return ret; 3529 } 3530 3531 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3532 ctrl_para.start_pktid = pkt_id; 3533 ctrl_para.end_pktid = pkt_id; 3534 ctrl_para.pkt_num = 0; 3535 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3536 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3537 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3538 if (ret) { 3539 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3540 return -EFAULT; 3541 } 3542 3543 return 0; 3544 } 3545 3546 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3547 { 3548 int ret; 3549 u32 reg; 3550 u8 val; 3551 3552 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3553 if (ret) 3554 return ret; 3555 3556 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3557 3558 ret = read_poll_timeout(rtw89_read8, val, 3559 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3560 SW_CVR_DUR_US, 3561 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3562 false, rtwdev, reg); 3563 if (ret) 3564 return ret; 3565 3566 return 0; 3567 } 3568 3569 static int band1_enable_ax(struct rtw89_dev *rtwdev) 3570 { 3571 int ret, i; 3572 u32 sleep_bak[4] = {0}; 3573 u32 pause_bak[4] = {0}; 3574 u32 tx_en; 3575 3576 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3577 if (ret) { 3578 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3579 return ret; 3580 } 3581 3582 for (i = 0; i < 4; i++) { 3583 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3584 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3585 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3586 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3587 } 3588 3589 ret = band_idle_ck_b(rtwdev, 0); 3590 if (ret) { 3591 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3592 return ret; 3593 } 3594 3595 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3596 if (ret) { 3597 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3598 return ret; 3599 } 3600 3601 for (i = 0; i < 4; i++) { 3602 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3603 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3604 } 3605 3606 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3607 if (ret) { 3608 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3609 return ret; 3610 } 3611 3612 ret = cmac_func_en_ax(rtwdev, 1, true); 3613 if (ret) { 3614 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3615 return ret; 3616 } 3617 3618 ret = cmac_init_ax(rtwdev, 1); 3619 if (ret) { 3620 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3621 return ret; 3622 } 3623 3624 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3625 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3626 3627 return 0; 3628 } 3629 3630 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3631 { 3632 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3633 3634 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3635 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3636 } 3637 3638 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3639 { 3640 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3641 3642 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3643 } 3644 3645 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3646 { 3647 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3648 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3649 3650 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3651 B_AX_TX_GET_ERRPKTID_INT_EN | 3652 B_AX_TX_NXT_ERRPKTID_INT_EN | 3653 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3654 B_AX_TX_OFFSET_ERR_INT_EN | 3655 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3656 if (chip_id == RTL8852C) 3657 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3658 B_AX_TX_ETH_TYPE_ERR_EN | 3659 B_AX_TX_LLC_PRE_ERR_EN | 3660 B_AX_TX_NW_TYPE_ERR_EN | 3661 B_AX_TX_KSRCH_ERR_EN); 3662 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3663 imr->mpdu_tx_imr_set); 3664 3665 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3666 B_AX_GETPKTID_ERR_INT_EN | 3667 B_AX_MHDRLEN_ERR_INT_EN | 3668 B_AX_RPT_ERR_INT_EN); 3669 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3670 imr->mpdu_rx_imr_set); 3671 } 3672 3673 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3674 { 3675 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3676 3677 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3678 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3679 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3680 B_AX_PLE_B_PKTID_ERR_INT_EN); 3681 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3682 imr->sta_sch_imr_set); 3683 } 3684 3685 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3686 { 3687 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3688 3689 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3690 imr->txpktctl_imr_b0_clr); 3691 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3692 imr->txpktctl_imr_b0_set); 3693 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3694 imr->txpktctl_imr_b1_clr); 3695 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3696 imr->txpktctl_imr_b1_set); 3697 } 3698 3699 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3700 { 3701 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3702 3703 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3704 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3705 } 3706 3707 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3708 { 3709 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3710 3711 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3712 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3713 } 3714 3715 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3716 { 3717 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3718 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3719 } 3720 3721 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3722 { 3723 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3724 3725 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3726 imr->host_disp_imr_clr); 3727 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3728 imr->host_disp_imr_set); 3729 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3730 imr->cpu_disp_imr_clr); 3731 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3732 imr->cpu_disp_imr_set); 3733 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3734 imr->other_disp_imr_clr); 3735 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3736 imr->other_disp_imr_set); 3737 } 3738 3739 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3740 { 3741 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3742 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3743 } 3744 3745 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3746 { 3747 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3748 3749 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3750 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3751 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3752 B_AX_BBRPT_CHINFO_IMR_CLR); 3753 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3754 imr->bbrpt_err_imr_set); 3755 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3756 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3757 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3758 } 3759 3760 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3761 { 3762 u32 reg; 3763 3764 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3765 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3766 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3767 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3768 } 3769 3770 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3771 { 3772 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3773 u32 reg; 3774 3775 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3776 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3777 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3778 } 3779 3780 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3781 { 3782 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3783 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3784 u32 reg; 3785 3786 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3787 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3788 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3789 3790 if (chip_id == RTL8852C) { 3791 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3792 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3793 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3794 } 3795 } 3796 3797 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3798 { 3799 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3800 u32 reg; 3801 3802 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3803 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3804 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3805 } 3806 3807 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3808 { 3809 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3810 u32 reg; 3811 3812 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3813 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3814 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3815 } 3816 3817 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3818 { 3819 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3820 u32 reg; 3821 3822 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3823 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3824 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3825 } 3826 3827 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3828 enum rtw89_mac_hwmod_sel sel) 3829 { 3830 int ret; 3831 3832 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3833 if (ret) { 3834 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3835 sel, mac_idx); 3836 return ret; 3837 } 3838 3839 if (sel == RTW89_DMAC_SEL) { 3840 rtw89_wdrls_imr_enable(rtwdev); 3841 rtw89_wsec_imr_enable(rtwdev); 3842 rtw89_mpdu_trx_imr_enable(rtwdev); 3843 rtw89_sta_sch_imr_enable(rtwdev); 3844 rtw89_txpktctl_imr_enable(rtwdev); 3845 rtw89_wde_imr_enable(rtwdev); 3846 rtw89_ple_imr_enable(rtwdev); 3847 rtw89_pktin_imr_enable(rtwdev); 3848 rtw89_dispatcher_imr_enable(rtwdev); 3849 rtw89_cpuio_imr_enable(rtwdev); 3850 rtw89_bbrpt_imr_enable(rtwdev); 3851 } else if (sel == RTW89_CMAC_SEL) { 3852 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3853 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3854 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3855 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3856 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3857 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3858 } else { 3859 return -EINVAL; 3860 } 3861 3862 return 0; 3863 } 3864 3865 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3866 { 3867 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3868 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3869 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3870 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3871 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta) 3872 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3873 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3874 } 3875 3876 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3877 { 3878 int ret = 0; 3879 3880 if (enable) { 3881 ret = band1_enable_ax(rtwdev); 3882 if (ret) { 3883 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3884 return ret; 3885 } 3886 3887 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3888 if (ret) { 3889 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3890 return ret; 3891 } 3892 } else { 3893 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3894 return -EINVAL; 3895 } 3896 3897 return 0; 3898 } 3899 3900 static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3901 { 3902 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3903 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3904 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3905 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3906 B_AX_RLSRPT0_FLTR_MAP_MASK); 3907 } else { 3908 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3909 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3910 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3911 B_AX_RLSRPT0_FLTR_MAP_MASK); 3912 } 3913 3914 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3915 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3916 3917 return 0; 3918 } 3919 3920 static int trx_init_ax(struct rtw89_dev *rtwdev) 3921 { 3922 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3923 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3924 int ret; 3925 3926 ret = dmac_init_ax(rtwdev, 0); 3927 if (ret) { 3928 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3929 return ret; 3930 } 3931 3932 ret = cmac_init_ax(rtwdev, 0); 3933 if (ret) { 3934 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3935 return ret; 3936 } 3937 3938 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3939 ret = dbcc_enable_ax(rtwdev, true); 3940 if (ret) { 3941 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3942 return ret; 3943 } 3944 } 3945 3946 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3947 if (ret) { 3948 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3949 return ret; 3950 } 3951 3952 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3953 if (ret) { 3954 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3955 return ret; 3956 } 3957 3958 err_imr_ctrl_ax(rtwdev, true); 3959 3960 ret = set_host_rpr_ax(rtwdev); 3961 if (ret) { 3962 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3963 return ret; 3964 } 3965 3966 if (chip_id == RTL8852C) 3967 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG, 3968 B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN); 3969 3970 return 0; 3971 } 3972 3973 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 3974 { 3975 #define BACAM_1024BMP_OCC_ENTRY 4 3976 #define BACAM_MAX_RU_SUPPORT_B0_STA 1 3977 #define BACAM_MAX_RU_SUPPORT_B1_STA 1 3978 const struct rtw89_chip_info *chip = rtwdev->chip; 3979 u8 users, offset; 3980 3981 if (chip->bacam_ver != RTW89_BACAM_V1) 3982 return 0; 3983 3984 offset = 0; 3985 users = BACAM_MAX_RU_SUPPORT_B0_STA; 3986 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 3987 3988 offset += users * BACAM_1024BMP_OCC_ENTRY; 3989 users = BACAM_MAX_RU_SUPPORT_B1_STA; 3990 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 3991 3992 return 0; 3993 } 3994 3995 static int rtw89_mac_reset_pwr_state_ax(struct rtw89_dev *rtwdev) 3996 { 3997 u8 val; 3998 3999 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 4000 if (val == MAC_AX_MAC_ON) { 4001 /* 4002 * A USB adapter might play as USB mass storage with driver and 4003 * then switch to WiFi adapter, causing it stays on power-on 4004 * state when doing WiFi USB probe. Return EAGAIN to caller to 4005 * power-off and power-on again to reset the state. 4006 */ 4007 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB && 4008 !test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags)) 4009 return -EAGAIN; 4010 4011 rtw89_err(rtwdev, "MAC has already powered on\n"); 4012 return -EBUSY; 4013 } 4014 4015 return 0; 4016 } 4017 4018 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 4019 { 4020 u32 val32; 4021 4022 if (rtw89_is_rtl885xb(rtwdev)) { 4023 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 4024 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 4025 return; 4026 } 4027 4028 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 4029 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 4030 4031 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 4032 val32 |= B_AX_FS_WDT_INT; 4033 val32 &= ~B_AX_FS_WDT_INT_MSK; 4034 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 4035 } 4036 4037 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 4038 { 4039 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 4040 4041 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 4042 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 4043 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 4044 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 4045 4046 rtw89_disable_fw_watchdog(rtwdev); 4047 4048 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 4049 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 4050 } 4051 4052 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 4053 bool dlfw, bool include_bb) 4054 { 4055 u32 val; 4056 int ret; 4057 4058 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 4059 return -EFAULT; 4060 4061 rtw89_write32(rtwdev, R_AX_UDM1, 0); 4062 rtw89_write32(rtwdev, R_AX_UDM2, 0); 4063 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 4064 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 4065 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 4066 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 4067 4068 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 4069 4070 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 4071 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 4072 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 4073 B_AX_WCPU_FWDL_STS_MASK); 4074 4075 if (dlfw) 4076 val |= B_AX_WCPU_FWDL_EN; 4077 4078 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 4079 4080 if (rtw89_is_rtl885xb(rtwdev)) 4081 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 4082 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 4083 4084 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 4085 boot_reason); 4086 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 4087 4088 if (!dlfw) { 4089 mdelay(5); 4090 4091 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 4092 if (ret) 4093 return ret; 4094 } 4095 4096 return 0; 4097 } 4098 4099 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 4100 { 4101 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4102 u32 val; 4103 4104 if (chip_id == RTL8852C) 4105 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 4106 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 4107 else 4108 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 4109 B_AX_PKT_BUF_EN; 4110 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 4111 } 4112 4113 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 4114 { 4115 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4116 u32 val; 4117 4118 if (chip_id == RTL8851B || chip_id == RTL8852BT) 4119 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 4120 else 4121 val = B_AX_DISPATCHER_CLK_EN; 4122 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 4123 4124 if (chip_id != RTL8852C) 4125 return; 4126 4127 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 4128 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 4129 val |= B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 4130 4131 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) 4132 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B); 4133 else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 4134 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_USB); 4135 else 4136 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_SDIO); 4137 4138 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 4139 4140 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 4141 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 4142 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 4143 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 4144 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 4145 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 4146 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 4147 } 4148 4149 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 4150 { 4151 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4152 int ret; 4153 4154 mac->hci_func_en(rtwdev); 4155 mac->dmac_func_pre_en(rtwdev); 4156 4157 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 4158 if (ret) { 4159 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 4160 return ret; 4161 } 4162 4163 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 4164 if (ret) { 4165 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 4166 return ret; 4167 } 4168 4169 return ret; 4170 } 4171 4172 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 4173 { 4174 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 4175 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 4176 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 4177 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 4178 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 4179 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 4180 4181 return 0; 4182 } 4183 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 4184 4185 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 4186 { 4187 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 4188 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 4189 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 4190 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 4191 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 4192 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 4193 4194 return 0; 4195 } 4196 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 4197 4198 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 4199 { 4200 int ret; 4201 4202 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 4203 4204 if (include_bb) { 4205 /* Only call BB preinit including configuration of BB MCU for 4206 * the chips which need to download BB MCU firmware. Otherwise, 4207 * calling preinit later to prevent touching registers affecting 4208 * download firmware. 4209 */ 4210 rtw89_chip_bb_preinit(rtwdev); 4211 } 4212 4213 ret = rtw89_mac_dmac_pre_init(rtwdev); 4214 if (ret) 4215 return ret; 4216 4217 if (rtwdev->hci.ops->mac_pre_init) { 4218 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 4219 if (ret) 4220 return ret; 4221 } 4222 4223 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 4224 if (ret) 4225 return ret; 4226 4227 return 0; 4228 } 4229 4230 int rtw89_mac_preinit(struct rtw89_dev *rtwdev) 4231 { 4232 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4233 int ret; 4234 4235 ret = rtw89_mac_pwr_on(rtwdev); 4236 if (ret) 4237 return ret; 4238 4239 if (mac->mac_func_en) { 4240 ret = mac->mac_func_en(rtwdev); 4241 if (ret) 4242 return ret; 4243 } 4244 4245 return 0; 4246 } 4247 4248 int rtw89_mac_init(struct rtw89_dev *rtwdev) 4249 { 4250 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4251 const struct rtw89_chip_info *chip = rtwdev->chip; 4252 bool include_bb = !!chip->bbmcu_nr; 4253 int ret; 4254 4255 ret = rtw89_mac_partial_init(rtwdev, include_bb); 4256 if (ret) 4257 goto fail; 4258 4259 ret = rtw89_chip_enable_bb_rf(rtwdev); 4260 if (ret) 4261 goto fail; 4262 4263 ret = mac->sys_init(rtwdev); 4264 if (ret) 4265 goto fail; 4266 4267 ret = mac->trx_init(rtwdev); 4268 if (ret) 4269 goto fail; 4270 4271 ret = rtw89_mac_feat_init(rtwdev); 4272 if (ret) 4273 goto fail; 4274 4275 if (rtwdev->hci.ops->mac_post_init) { 4276 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 4277 if (ret) 4278 goto fail; 4279 } 4280 4281 rtw89_fw_send_all_early_h2c(rtwdev); 4282 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 4283 4284 return ret; 4285 fail: 4286 rtw89_mac_pwr_off(rtwdev); 4287 4288 return ret; 4289 } 4290 4291 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4292 { 4293 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4294 u8 i; 4295 4296 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4297 return; 4298 4299 for (i = 0; i < 4; i++) { 4300 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4301 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 4302 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 4303 } 4304 } 4305 4306 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4307 { 4308 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4309 4310 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4311 return; 4312 4313 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4314 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 4315 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 4316 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 4317 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 4318 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 4319 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 4320 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 4321 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 4322 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 4323 } 4324 4325 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4326 { 4327 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4328 u8 grp = macid >> 5; 4329 int ret; 4330 4331 /* If this is called by change_interface() in the case of P2P, it could 4332 * be power-off, so ignore this operation. 4333 */ 4334 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4335 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4336 return 0; 4337 4338 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4339 if (ret) 4340 return ret; 4341 4342 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4343 4344 return 0; 4345 } 4346 4347 static const struct rtw89_port_reg rtw89_port_base_ax = { 4348 .port_cfg = R_AX_PORT_CFG_P0, 4349 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4350 .bcn_area = R_AX_BCN_AREA_P0, 4351 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4352 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4353 .tbtt_agg = R_AX_TBTT_AGG_P0, 4354 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4355 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4356 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4357 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4358 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4359 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4360 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4361 .tsftr_l = R_AX_TSFTR_LOW_P0, 4362 .tsftr_h = R_AX_TSFTR_HIGH_P0, 4363 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 4364 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4365 .mbssid = R_AX_MBSSID_CTRL, 4366 .mbssid_drop = R_AX_MBSSID_DROP_0, 4367 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4368 .ptcl_dbg = R_AX_PTCL_DBG, 4369 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4370 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4371 .bcn_psr_rpt = R_AX_BCN_PSR_RPT_P0, 4372 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4373 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4374 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4375 }; 4376 4377 static const struct rtw89_mac_mu_gid_addr rtw89_mac_mu_gid_addr_ax = { 4378 .position_en = {R_AX_GID_POSITION_EN0, R_AX_GID_POSITION_EN1}, 4379 .position = {R_AX_GID_POSITION0, R_AX_GID_POSITION1, 4380 R_AX_GID_POSITION2, R_AX_GID_POSITION3}, 4381 }; 4382 4383 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4384 struct rtw89_vif_link *rtwvif_link, u8 type) 4385 { 4386 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4387 const struct rtw89_port_reg *p = mac->port_base; 4388 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif_link->port); 4389 u32 reg_info, reg_ctrl; 4390 u32 val; 4391 int ret; 4392 4393 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif_link->mac_idx); 4394 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif_link->mac_idx); 4395 4396 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4397 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4398 fsleep(100); 4399 4400 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4401 true, rtwdev, reg_info, mask); 4402 if (ret) 4403 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4404 } 4405 4406 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, 4407 struct rtw89_vif_link *rtwvif_link) 4408 { 4409 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4410 const struct rtw89_port_reg *p = mac->port_base; 4411 4412 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4413 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 4414 1); 4415 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 4416 0); 4417 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 4418 0); 4419 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4420 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4421 B_AX_TBTTERLY_MASK, 1); 4422 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, 4423 B_AX_BCN_SPACE_MASK, 1); 4424 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4425 4426 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM0); 4427 if (rtwvif_link->port == RTW89_PORT_0) 4428 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM1); 4429 4430 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4431 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4432 fsleep(2000); 4433 } 4434 4435 #define BCN_INTERVAL 100 4436 #define BCN_ERLY_DEF 160 4437 #define BCN_SETUP_DEF 2 4438 #define BCN_HOLD_DEF 200 4439 #define BCN_MASK_DEF 0 4440 #define TBTT_ERLY_DEF 5 4441 #define TBTT_AGG_DEF 1 4442 #define BCN_SET_UNIT 32 4443 #define BCN_ERLY_SET_DLY (10 * 2) 4444 4445 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4446 struct rtw89_vif_link *rtwvif_link) 4447 { 4448 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4449 const struct rtw89_port_reg *p = mac->port_base; 4450 const struct rtw89_chip_info *chip = rtwdev->chip; 4451 struct ieee80211_bss_conf *bss_conf; 4452 bool need_backup = false; 4453 u32 backup_val; 4454 u16 beacon_int; 4455 4456 if (!rtw89_read32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN)) 4457 return; 4458 4459 if (chip->chip_id == RTL8852A && rtwvif_link->port != RTW89_PORT_0) { 4460 need_backup = true; 4461 backup_val = rtw89_read32_port(rtwdev, rtwvif_link, p->tbtt_prohib); 4462 } 4463 4464 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4465 rtw89_mac_bcn_drop(rtwdev, rtwvif_link); 4466 4467 if (chip->chip_id == RTL8852A) { 4468 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->tbtt_prohib, 4469 B_AX_TBTT_SETUP_MASK); 4470 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4471 B_AX_TBTT_HOLD_MASK, 1); 4472 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->tbtt_early, 4473 B_AX_TBTTERLY_MASK); 4474 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->bcn_early, 4475 B_AX_BCNERLY_MASK); 4476 } 4477 4478 rcu_read_lock(); 4479 4480 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4481 beacon_int = bss_conf->beacon_int; 4482 4483 rcu_read_unlock(); 4484 4485 msleep(beacon_int + 1); 4486 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN | 4487 B_AX_BRK_SETUP); 4488 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSFTR_RST); 4489 rtw89_write32_port(rtwdev, rtwvif_link, p->bcn_cnt_tmr, 0); 4490 4491 if (need_backup) 4492 rtw89_write32_port(rtwdev, rtwvif_link, p->tbtt_prohib, backup_val); 4493 } 4494 4495 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4496 struct rtw89_vif_link *rtwvif_link, bool en) 4497 { 4498 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4499 const struct rtw89_port_reg *p = mac->port_base; 4500 4501 if (en) 4502 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4503 B_AX_TXBCN_RPT_EN); 4504 else 4505 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4506 B_AX_TXBCN_RPT_EN); 4507 } 4508 4509 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4510 struct rtw89_vif_link *rtwvif_link, bool en) 4511 { 4512 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4513 const struct rtw89_port_reg *p = mac->port_base; 4514 4515 if (en) 4516 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4517 B_AX_RXBCN_RPT_EN); 4518 else 4519 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4520 B_AX_RXBCN_RPT_EN); 4521 } 4522 4523 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4524 struct rtw89_vif_link *rtwvif_link) 4525 { 4526 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4527 const struct rtw89_port_reg *p = mac->port_base; 4528 4529 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_NET_TYPE_MASK, 4530 rtwvif_link->net_type); 4531 } 4532 4533 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4534 struct rtw89_vif_link *rtwvif_link) 4535 { 4536 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4537 const struct rtw89_port_reg *p = mac->port_base; 4538 bool en = rtwvif_link->net_type != RTW89_NET_TYPE_NO_LINK; 4539 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4540 4541 if (en) 4542 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bits); 4543 else 4544 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bits); 4545 } 4546 4547 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4548 struct rtw89_vif_link *rtwvif_link) 4549 { 4550 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4551 const struct rtw89_port_reg *p = mac->port_base; 4552 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4553 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4554 u32 bit = B_AX_RX_BSSID_FIT_EN; 4555 4556 if (en) 4557 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bit); 4558 else 4559 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bit); 4560 } 4561 4562 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4563 struct rtw89_vif_link *rtwvif_link, bool en) 4564 { 4565 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4566 const struct rtw89_port_reg *p = mac->port_base; 4567 4568 if (en) 4569 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4570 else 4571 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4572 } 4573 4574 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4575 struct rtw89_vif_link *rtwvif_link) 4576 { 4577 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4578 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4579 4580 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif_link, en); 4581 } 4582 4583 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4584 struct rtw89_vif_link *rtwvif_link, bool en) 4585 { 4586 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4587 const struct rtw89_port_reg *p = mac->port_base; 4588 4589 if (en) 4590 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4591 else 4592 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4593 } 4594 4595 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4596 struct rtw89_vif_link *rtwvif_link) 4597 { 4598 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || 4599 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4600 4601 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4602 } 4603 4604 static void rtw89_mac_enable_ap_bcn_by_chan(struct rtw89_dev *rtwdev, 4605 struct rtw89_vif_link *rtwvif_link, 4606 const struct rtw89_chan *to_match, 4607 bool en) 4608 { 4609 const struct rtw89_chan *chan; 4610 4611 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 4612 return; 4613 4614 if (!to_match) 4615 goto doit; 4616 4617 /* @to_match may not be in the same domain as return of calling 4618 * rtw89_chan_get(). So, cannot compare their addresses directly. 4619 */ 4620 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 4621 if (chan->channel != to_match->channel) 4622 return; 4623 4624 doit: 4625 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4626 } 4627 4628 static void rtw89_mac_enable_aps_bcn_by_chan(struct rtw89_dev *rtwdev, 4629 const struct rtw89_chan *to_match, 4630 bool en) 4631 { 4632 struct rtw89_vif_link *rtwvif_link; 4633 struct rtw89_vif *rtwvif; 4634 unsigned int link_id; 4635 4636 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4637 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4638 rtw89_mac_enable_ap_bcn_by_chan(rtwdev, rtwvif_link, 4639 to_match, en); 4640 } 4641 4642 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4643 { 4644 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, NULL, en); 4645 } 4646 4647 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4648 struct rtw89_vif_link *rtwvif_link) 4649 { 4650 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4651 const struct rtw89_port_reg *p = mac->port_base; 4652 struct ieee80211_bss_conf *bss_conf; 4653 u16 bcn_int; 4654 4655 rcu_read_lock(); 4656 4657 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4658 if (bss_conf->beacon_int) 4659 bcn_int = bss_conf->beacon_int; 4660 else 4661 bcn_int = BCN_INTERVAL; 4662 4663 rcu_read_unlock(); 4664 4665 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, B_AX_BCN_SPACE_MASK, 4666 bcn_int); 4667 } 4668 4669 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4670 struct rtw89_vif_link *rtwvif_link) 4671 { 4672 u8 win = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4673 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4674 const struct rtw89_port_reg *p = mac->port_base; 4675 u8 port = rtwvif_link->port; 4676 u32 reg; 4677 4678 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif_link->mac_idx); 4679 rtw89_write8(rtwdev, reg, win); 4680 } 4681 4682 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4683 struct rtw89_vif_link *rtwvif_link) 4684 { 4685 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4686 const struct rtw89_port_reg *p = mac->port_base; 4687 struct ieee80211_bss_conf *bss_conf; 4688 u8 dtim_period; 4689 u32 addr; 4690 4691 rcu_read_lock(); 4692 4693 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4694 dtim_period = bss_conf->dtim_period; 4695 4696 rcu_read_unlock(); 4697 4698 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif_link->mac_idx); 4699 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4700 4701 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4702 dtim_period); 4703 } 4704 4705 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4706 struct rtw89_vif_link *rtwvif_link) 4707 { 4708 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4709 const struct rtw89_port_reg *p = mac->port_base; 4710 4711 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4712 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4713 } 4714 4715 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4716 struct rtw89_vif_link *rtwvif_link) 4717 { 4718 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4719 const struct rtw89_port_reg *p = mac->port_base; 4720 4721 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4722 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4723 } 4724 4725 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4726 struct rtw89_vif_link *rtwvif_link) 4727 { 4728 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4729 const struct rtw89_port_reg *p = mac->port_base; 4730 4731 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, 4732 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4733 } 4734 4735 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4736 struct rtw89_vif_link *rtwvif_link) 4737 { 4738 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4739 const struct rtw89_port_reg *p = mac->port_base; 4740 4741 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4742 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4743 } 4744 4745 static void rtw89_mac_port_cfg_tbtt_agg(struct rtw89_dev *rtwdev, 4746 struct rtw89_vif_link *rtwvif_link) 4747 { 4748 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4749 const struct rtw89_port_reg *p = mac->port_base; 4750 4751 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_agg, 4752 B_AX_TBTT_AGG_NUM_MASK, TBTT_AGG_DEF); 4753 } 4754 4755 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4756 struct rtw89_vif_link *rtwvif_link) 4757 { 4758 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4759 const struct rtw89_port_reg *p = mac->port_base; 4760 static const u32 masks[RTW89_PORT_NUM] = { 4761 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4762 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4763 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4764 }; 4765 struct ieee80211_bss_conf *bss_conf; 4766 u8 port = rtwvif_link->port; 4767 u32 reg_base; 4768 u32 reg; 4769 u8 bss_color; 4770 4771 rcu_read_lock(); 4772 4773 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4774 bss_color = bss_conf->he_bss_color.color; 4775 4776 rcu_read_unlock(); 4777 4778 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4779 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif_link->mac_idx); 4780 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4781 } 4782 4783 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4784 struct rtw89_vif_link *rtwvif_link) 4785 { 4786 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4787 const struct rtw89_port_reg *p = mac->port_base; 4788 u8 port = rtwvif_link->port; 4789 u32 reg; 4790 4791 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4792 return; 4793 4794 if (port == 0) { 4795 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif_link->mac_idx); 4796 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4797 } 4798 } 4799 4800 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4801 struct rtw89_vif_link *rtwvif_link) 4802 { 4803 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4804 const struct rtw89_port_reg *p = mac->port_base; 4805 u8 port = rtwvif_link->port; 4806 u32 reg; 4807 u32 val; 4808 4809 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif_link->mac_idx); 4810 val = rtw89_read32(rtwdev, reg); 4811 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4812 if (port == 0) 4813 val &= ~BIT(0); 4814 rtw89_write32(rtwdev, reg, val); 4815 } 4816 4817 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4818 struct rtw89_vif_link *rtwvif_link, bool enable) 4819 { 4820 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4821 const struct rtw89_port_reg *p = mac->port_base; 4822 4823 if (enable) 4824 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4825 B_AX_PORT_FUNC_EN); 4826 else 4827 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4828 B_AX_PORT_FUNC_EN); 4829 } 4830 4831 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4832 struct rtw89_vif_link *rtwvif_link) 4833 { 4834 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4835 const struct rtw89_port_reg *p = mac->port_base; 4836 4837 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 4838 BCN_ERLY_DEF); 4839 } 4840 4841 static void rtw89_mac_port_cfg_bcn_psr_rpt(struct rtw89_dev *rtwdev, 4842 struct rtw89_vif_link *rtwvif_link) 4843 { 4844 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4845 const struct rtw89_port_reg *p = mac->port_base; 4846 struct ieee80211_bss_conf *bss_conf; 4847 u8 bssid_index; 4848 u32 reg; 4849 4850 rcu_read_lock(); 4851 4852 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4853 if (bss_conf->nontransmitted) 4854 bssid_index = bss_conf->bssid_index; 4855 else 4856 bssid_index = 0; 4857 4858 rcu_read_unlock(); 4859 4860 reg = rtw89_mac_reg_by_idx(rtwdev, p->bcn_psr_rpt + rtwvif_link->port * 4, 4861 rtwvif_link->mac_idx); 4862 rtw89_write32_mask(rtwdev, reg, B_AX_BCAID_P0_MASK, bssid_index); 4863 } 4864 4865 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4866 struct rtw89_vif_link *rtwvif_link, 4867 struct rtw89_vif_link *rtwvif_src, 4868 u16 offset_tu) 4869 { 4870 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4871 const struct rtw89_port_reg *p = mac->port_base; 4872 u32 val, reg; 4873 4874 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4875 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif_link->port * 4, 4876 rtwvif_link->mac_idx); 4877 4878 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4879 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4880 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4881 } 4882 4883 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4884 struct rtw89_vif_link *rtwvif_link, 4885 struct rtw89_vif_link *rtwvif_src, 4886 u8 offset, int *n_offset) 4887 { 4888 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif_link == rtwvif_src) 4889 return; 4890 4891 if (rtwvif_link->rand_tsf_done) 4892 goto out; 4893 4894 /* adjust offset randomly to avoid beacon conflict */ 4895 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4896 rtw89_mac_port_tsf_sync(rtwdev, rtwvif_link, rtwvif_src, 4897 (*n_offset) * offset); 4898 4899 rtwvif_link->rand_tsf_done = true; 4900 4901 out: 4902 (*n_offset)++; 4903 } 4904 4905 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4906 { 4907 struct rtw89_vif_link *src = NULL, *tmp; 4908 u8 offset = 100, vif_aps = 0; 4909 struct rtw89_vif *rtwvif; 4910 unsigned int link_id; 4911 int n_offset = 1; 4912 4913 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4914 rtw89_vif_for_each_link(rtwvif, tmp, link_id) { 4915 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4916 src = tmp; 4917 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4918 vif_aps++; 4919 } 4920 } 4921 4922 if (vif_aps == 0) 4923 return; 4924 4925 offset /= (vif_aps + 1); 4926 4927 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4928 rtw89_vif_for_each_link(rtwvif, tmp, link_id) 4929 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, 4930 &n_offset); 4931 } 4932 4933 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4934 { 4935 int ret; 4936 4937 ret = rtw89_mac_port_update(rtwdev, rtwvif_link); 4938 if (ret) 4939 return ret; 4940 4941 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4942 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif_link->mac_id); 4943 4944 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif_link->mac_id, false); 4945 if (ret) 4946 return ret; 4947 4948 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_CREATE); 4949 if (ret) 4950 return ret; 4951 4952 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, NULL, true); 4953 if (ret) 4954 return ret; 4955 4956 ret = rtw89_cam_init(rtwdev, rtwvif_link); 4957 if (ret) 4958 return ret; 4959 4960 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, RTW89_ROLE_CREATE); 4961 if (ret) 4962 return ret; 4963 4964 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, NULL); 4965 if (ret) 4966 return ret; 4967 4968 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, NULL); 4969 if (ret) 4970 return ret; 4971 4972 return 0; 4973 } 4974 4975 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4976 { 4977 int ret; 4978 4979 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_REMOVE); 4980 if (ret) 4981 return ret; 4982 4983 rtw89_cam_deinit(rtwdev, rtwvif_link); 4984 4985 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, RTW89_ROLE_REMOVE); 4986 if (ret) 4987 return ret; 4988 4989 return 0; 4990 } 4991 4992 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4993 { 4994 u8 port = rtwvif_link->port; 4995 4996 if (port >= RTW89_PORT_NUM) 4997 return -EINVAL; 4998 4999 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 5000 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif_link, false); 5001 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif_link, false); 5002 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif_link); 5003 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif_link); 5004 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif_link); 5005 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif_link); 5006 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif_link); 5007 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif_link); 5008 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif_link); 5009 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif_link); 5010 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif_link); 5011 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif_link); 5012 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif_link); 5013 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif_link); 5014 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif_link); 5015 rtw89_mac_port_cfg_tbtt_agg(rtwdev, rtwvif_link); 5016 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif_link); 5017 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif_link); 5018 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif_link, true); 5019 rtw89_mac_port_tsf_resync_all(rtwdev); 5020 fsleep(BCN_ERLY_SET_DLY); 5021 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif_link); 5022 rtw89_mac_port_cfg_bcn_psr_rpt(rtwdev, rtwvif_link); 5023 5024 return 0; 5025 } 5026 5027 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5028 u64 *tsf) 5029 { 5030 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5031 const struct rtw89_port_reg *p = mac->port_base; 5032 u32 tsf_low, tsf_high; 5033 int ret; 5034 5035 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif_link->mac_idx, RTW89_CMAC_SEL); 5036 if (ret) 5037 return ret; 5038 5039 tsf_low = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_l); 5040 tsf_high = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_h); 5041 *tsf = (u64)tsf_high << 32 | tsf_low; 5042 5043 return 0; 5044 } 5045 5046 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 5047 struct cfg80211_bss *bss, 5048 void *data) 5049 { 5050 const struct cfg80211_bss_ies *ies; 5051 const struct element *elem; 5052 bool *tolerated = data; 5053 5054 rcu_read_lock(); 5055 ies = rcu_dereference(bss->ies); 5056 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 5057 ies->len); 5058 5059 if (!elem || elem->datalen < 10 || 5060 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 5061 *tolerated = false; 5062 rcu_read_unlock(); 5063 } 5064 5065 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 5066 struct rtw89_vif_link *rtwvif_link) 5067 { 5068 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5069 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5070 struct ieee80211_hw *hw = rtwdev->hw; 5071 struct ieee80211_bss_conf *bss_conf; 5072 struct cfg80211_chan_def oper; 5073 bool tolerated = true; 5074 u32 reg; 5075 5076 rcu_read_lock(); 5077 5078 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5079 if (!bss_conf->he_support || vif->type != NL80211_IFTYPE_STATION) { 5080 rcu_read_unlock(); 5081 return; 5082 } 5083 5084 oper = bss_conf->chanreq.oper; 5085 if (!(oper.chan->flags & IEEE80211_CHAN_RADAR)) { 5086 rcu_read_unlock(); 5087 return; 5088 } 5089 5090 rcu_read_unlock(); 5091 5092 cfg80211_bss_iter(hw->wiphy, &oper, 5093 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 5094 &tolerated); 5095 5096 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 5097 rtwvif_link->mac_idx); 5098 if (tolerated) 5099 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 5100 else 5101 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 5102 } 5103 5104 void rtw89_mac_set_he_tb(struct rtw89_dev *rtwdev, 5105 struct rtw89_vif_link *rtwvif_link) 5106 { 5107 struct ieee80211_bss_conf *bss_conf; 5108 bool set; 5109 u32 reg; 5110 5111 if (rtwdev->chip->chip_gen != RTW89_CHIP_BE) 5112 return; 5113 5114 rcu_read_lock(); 5115 5116 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5117 set = bss_conf->he_support && !bss_conf->eht_support; 5118 5119 rcu_read_unlock(); 5120 5121 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CLIENT_OM_CTRL, 5122 rtwvif_link->mac_idx); 5123 5124 if (set) 5125 rtw89_write32_set(rtwdev, reg, B_BE_TRIG_DIS_EHTTB); 5126 else 5127 rtw89_write32_clr(rtwdev, reg, B_BE_TRIG_DIS_EHTTB); 5128 } 5129 5130 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5131 { 5132 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 5133 5134 rtwvif_link->rand_tsf_done = false; 5135 } 5136 5137 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5138 { 5139 return rtw89_mac_vif_init(rtwdev, rtwvif_link); 5140 } 5141 5142 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5143 { 5144 return rtw89_mac_vif_deinit(rtwdev, rtwvif_link); 5145 } 5146 5147 static void 5148 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5149 { 5150 } 5151 5152 static const struct rtw89_chan * 5153 rtw89_hw_scan_search_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 5154 { 5155 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 5156 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 5157 5158 if (band == op->band_type && channel == op->primary_channel) 5159 return op; 5160 5161 if (scan_info->extra_op.set) { 5162 op = &scan_info->extra_op.chan; 5163 if (band == op->band_type && channel == op->primary_channel) 5164 return op; 5165 } 5166 5167 return NULL; 5168 } 5169 5170 static void 5171 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5172 u32 len) 5173 { 5174 const struct rtw89_c2h_scanofld *c2h = 5175 (const struct rtw89_c2h_scanofld *)skb->data; 5176 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 5177 const struct rtw89_chan *op_chan; 5178 struct rtw89_vif *rtwvif; 5179 struct rtw89_chan new; 5180 u16 actual_period, expect_period; 5181 u8 reason, status, tx_fail, band; 5182 u8 mac_idx, sw_def, fw_def; 5183 u8 ver = U8_MAX; 5184 u32 report_tsf; 5185 u16 chan; 5186 int ret; 5187 5188 if (!rtwvif_link) 5189 return; 5190 5191 rtwvif = rtwvif_link->rtwvif; 5192 5193 if (RTW89_CHK_FW_FEATURE(CH_INFO_BE_V0, &rtwdev->fw)) 5194 ver = 0; 5195 5196 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 5197 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5198 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 5199 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5200 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 5201 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 5202 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 5203 5204 5205 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 5206 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 5207 5208 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 5209 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 5210 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 5211 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 5212 if (ver == 0) { 5213 expect_period = 5214 le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 5215 } else { 5216 actual_period = le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_PERIOD_V1); 5217 expect_period = 5218 le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1); 5219 } 5220 5221 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 5222 "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 5223 sw_def, fw_def, report_tsf, expect_period); 5224 } 5225 5226 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 5227 "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 5228 mac_idx, band, chan, reason, status, tx_fail, actual_period); 5229 5230 switch (reason) { 5231 case RTW89_SCAN_LEAVE_OP_NOTIFY: 5232 case RTW89_SCAN_LEAVE_CH_NOTIFY: 5233 op_chan = rtw89_hw_scan_search_op_chan(rtwdev, band, chan); 5234 if (op_chan) { 5235 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, op_chan, false); 5236 ieee80211_stop_queues(rtwdev->hw); 5237 } else { 5238 rtw89_phy_nhm_get_result(rtwdev, band, chan); 5239 } 5240 return; 5241 case RTW89_SCAN_END_SCAN_NOTIFY: 5242 if (rtwdev->scan_info.abort) 5243 return; 5244 5245 if (rtwvif_link && rtwvif->scan_req && 5246 !list_empty(&rtwdev->scan_info.chan_list)) { 5247 rtwdev->scan_info.delay = 0; 5248 ret = rtw89_hw_scan_offload(rtwdev, rtwvif_link, true); 5249 if (ret) { 5250 rtw89_hw_scan_abort(rtwdev, rtwvif_link); 5251 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 5252 } 5253 } else { 5254 rtw89_hw_scan_complete(rtwdev, rtwvif_link, false); 5255 } 5256 break; 5257 case RTW89_SCAN_ENTER_OP_NOTIFY: 5258 case RTW89_SCAN_ENTER_CH_NOTIFY: 5259 op_chan = rtw89_hw_scan_search_op_chan(rtwdev, band, chan); 5260 if (op_chan) { 5261 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, op_chan); 5262 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, op_chan, true); 5263 ieee80211_wake_queues(rtwdev->hw); 5264 } else { 5265 rtw89_chan_create(&new, chan, chan, band, 5266 RTW89_CHANNEL_WIDTH_20); 5267 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, 5268 &new); 5269 rtw89_phy_nhm_trigger(rtwdev); 5270 } 5271 break; 5272 default: 5273 return; 5274 } 5275 } 5276 5277 static void 5278 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5279 struct sk_buff *skb) 5280 { 5281 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5282 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5283 enum nl80211_cqm_rssi_threshold_event nl_event; 5284 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 5285 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 5286 u8 type, event, mac_id; 5287 bool start_detect; 5288 s8 sig; 5289 5290 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 5291 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 5292 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 5293 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 5294 5295 if (mac_id != rtwvif_link->mac_id) 5296 return; 5297 5298 rtw89_debug(rtwdev, RTW89_DBG_FW, 5299 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 5300 mac_id, type, sig, event); 5301 5302 switch (type) { 5303 case RTW89_BCN_FLTR_BEACON_LOSS: 5304 if (!rtwdev->scanning && !rtwvif->offchan && 5305 !rtwvif_link->noa_once.in_duration) { 5306 start_detect = rtw89_mcc_detect_go_bcn(rtwdev, rtwvif_link); 5307 if (start_detect) 5308 return; 5309 5310 ieee80211_beacon_loss(vif); 5311 } 5312 5313 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 5314 return; 5315 case RTW89_BCN_FLTR_NOTIFY: 5316 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 5317 break; 5318 case RTW89_BCN_FLTR_RSSI: 5319 if (event == RTW89_BCN_FLTR_RSSI_LOW) 5320 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 5321 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 5322 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 5323 else 5324 return; 5325 break; 5326 default: 5327 return; 5328 } 5329 5330 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 5331 } 5332 5333 static void 5334 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5335 u32 len) 5336 { 5337 struct rtw89_vif_link *rtwvif_link; 5338 struct rtw89_vif *rtwvif; 5339 unsigned int link_id; 5340 5341 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5342 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 5343 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif_link, c2h); 5344 } 5345 5346 static void 5347 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5348 { 5349 /* N.B. This will run in interrupt context. */ 5350 5351 rtw89_debug(rtwdev, RTW89_DBG_FW, 5352 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 5353 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 5354 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 5355 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 5356 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 5357 } 5358 5359 static void 5360 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5361 { 5362 /* N.B. This will run in interrupt context. */ 5363 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5364 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 5365 struct rtw89_wait_info *ps_wait = &rtwdev->mac.ps_wait; 5366 const struct rtw89_c2h_done_ack *c2h = 5367 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 5368 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 5369 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 5370 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 5371 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 5372 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 5373 struct rtw89_completion_data data = {}; 5374 unsigned int cond; 5375 5376 rtw89_debug(rtwdev, RTW89_DBG_FW, 5377 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 5378 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 5379 5380 if (h2c_cat != H2C_CAT_MAC) 5381 return; 5382 5383 switch (h2c_class) { 5384 default: 5385 return; 5386 case H2C_CL_MAC_PS: 5387 switch (h2c_func) { 5388 default: 5389 return; 5390 case H2C_FUNC_IPS_CFG: 5391 cond = RTW89_PS_WAIT_COND_IPS_CFG; 5392 break; 5393 } 5394 5395 data.err = !!h2c_return; 5396 rtw89_complete_cond(ps_wait, cond, &data); 5397 return; 5398 case H2C_CL_MAC_FW_OFLD: 5399 switch (h2c_func) { 5400 default: 5401 return; 5402 case H2C_FUNC_ADD_SCANOFLD_CH: 5403 cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 5404 h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN; 5405 break; 5406 case H2C_FUNC_SCANOFLD: 5407 scan_info->seq++; 5408 cond = RTW89_SCANOFLD_WAIT_COND_START; 5409 break; 5410 case H2C_FUNC_SCANOFLD_BE: 5411 scan_info->seq++; 5412 cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 5413 h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN; 5414 break; 5415 } 5416 5417 data.err = !!h2c_return; 5418 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5419 return; 5420 } 5421 } 5422 5423 static void 5424 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5425 { 5426 rtw89_fw_log_dump(rtwdev, c2h->data, len); 5427 } 5428 5429 static void 5430 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5431 { 5432 } 5433 5434 static void 5435 rtw89_mac_c2h_bcn_upd_done(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5436 { 5437 const struct rtw89_c2h_bcn_upd_done *c2h = 5438 (const struct rtw89_c2h_bcn_upd_done *)skb_c2h->data; 5439 u8 band, port, mbssid; 5440 5441 port = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_PORT); 5442 mbssid = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_MBSSID); 5443 band = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_BAND_IDX); 5444 5445 rtw89_debug(rtwdev, RTW89_DBG_FW, 5446 "BCN update done on port:%d mbssid:%d band:%d\n", 5447 port, mbssid, band); 5448 } 5449 5450 static void 5451 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 5452 u32 len) 5453 { 5454 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 5455 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 5456 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 5457 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 5458 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 5459 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 5460 struct rtw89_completion_data data = {}; 5461 unsigned int cond; 5462 5463 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 5464 pkt_id, pkt_op, pkt_len); 5465 5466 data.err = !pkt_len; 5467 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 5468 5469 rtw89_complete_cond(wait, cond, &data); 5470 } 5471 5472 static void 5473 rtw89_mac_c2h_bcn_resend(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5474 { 5475 } 5476 5477 static void 5478 rtw89_mac_c2h_tx_duty_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5479 { 5480 struct rtw89_c2h_tx_duty_rpt *c2h = 5481 (struct rtw89_c2h_tx_duty_rpt *)skb_c2h->data; 5482 u8 err; 5483 5484 err = le32_get_bits(c2h->w2, RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR); 5485 5486 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "C2H TX duty rpt with err=%d\n", err); 5487 } 5488 5489 static void 5490 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5491 u32 len) 5492 { 5493 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 5494 } 5495 5496 static void 5497 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5498 { 5499 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 5500 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 5501 5502 switch (func) { 5503 case H2C_FUNC_ADD_MCC: 5504 case H2C_FUNC_START_MCC: 5505 case H2C_FUNC_STOP_MCC: 5506 case H2C_FUNC_DEL_MCC_GROUP: 5507 case H2C_FUNC_RESET_MCC_GROUP: 5508 case H2C_FUNC_MCC_REQ_TSF: 5509 case H2C_FUNC_MCC_MACID_BITMAP: 5510 case H2C_FUNC_MCC_SYNC: 5511 case H2C_FUNC_MCC_SET_DURATION: 5512 break; 5513 default: 5514 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5515 "invalid MCC C2H RCV ACK: func %d\n", func); 5516 return; 5517 } 5518 5519 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5520 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 5521 } 5522 5523 static void 5524 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5525 { 5526 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 5527 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 5528 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 5529 struct rtw89_completion_data data = {}; 5530 unsigned int cond; 5531 bool next = false; 5532 5533 switch (func) { 5534 case H2C_FUNC_MCC_REQ_TSF: 5535 next = true; 5536 break; 5537 case H2C_FUNC_MCC_MACID_BITMAP: 5538 case H2C_FUNC_MCC_SYNC: 5539 case H2C_FUNC_MCC_SET_DURATION: 5540 break; 5541 case H2C_FUNC_ADD_MCC: 5542 case H2C_FUNC_START_MCC: 5543 case H2C_FUNC_STOP_MCC: 5544 case H2C_FUNC_DEL_MCC_GROUP: 5545 case H2C_FUNC_RESET_MCC_GROUP: 5546 default: 5547 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5548 "invalid MCC C2H REQ ACK: func %d\n", func); 5549 return; 5550 } 5551 5552 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5553 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5554 group, func, retcode); 5555 5556 if (!retcode && next) 5557 return; 5558 5559 data.err = !!retcode; 5560 cond = RTW89_MCC_WAIT_COND(group, func); 5561 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5562 } 5563 5564 static void 5565 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5566 { 5567 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5568 struct rtw89_completion_data data = {}; 5569 struct rtw89_mac_mcc_tsf_rpt *rpt; 5570 unsigned int cond; 5571 5572 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5573 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5574 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5575 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5576 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5577 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5578 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5579 5580 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5581 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5582 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5583 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5584 5585 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5586 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5587 } 5588 5589 static void 5590 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5591 { 5592 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5593 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5594 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5595 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5596 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5597 struct rtw89_completion_data data = {}; 5598 unsigned int cond; 5599 bool rsp = true; 5600 bool err; 5601 u8 func; 5602 5603 switch (status) { 5604 case RTW89_MAC_MCC_ADD_ROLE_OK: 5605 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5606 func = H2C_FUNC_ADD_MCC; 5607 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5608 break; 5609 case RTW89_MAC_MCC_START_GROUP_OK: 5610 case RTW89_MAC_MCC_START_GROUP_FAIL: 5611 func = H2C_FUNC_START_MCC; 5612 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5613 break; 5614 case RTW89_MAC_MCC_STOP_GROUP_OK: 5615 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5616 func = H2C_FUNC_STOP_MCC; 5617 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5618 break; 5619 case RTW89_MAC_MCC_DEL_GROUP_OK: 5620 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5621 func = H2C_FUNC_DEL_MCC_GROUP; 5622 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5623 break; 5624 case RTW89_MAC_MCC_RESET_GROUP_OK: 5625 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5626 func = H2C_FUNC_RESET_MCC_GROUP; 5627 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5628 break; 5629 case RTW89_MAC_MCC_SWITCH_CH_OK: 5630 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5631 case RTW89_MAC_MCC_TXNULL0_OK: 5632 case RTW89_MAC_MCC_TXNULL0_FAIL: 5633 case RTW89_MAC_MCC_TXNULL1_OK: 5634 case RTW89_MAC_MCC_TXNULL1_FAIL: 5635 case RTW89_MAC_MCC_SWITCH_EARLY: 5636 case RTW89_MAC_MCC_TBTT: 5637 case RTW89_MAC_MCC_DURATION_START: 5638 case RTW89_MAC_MCC_DURATION_END: 5639 rsp = false; 5640 break; 5641 default: 5642 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5643 "invalid MCC C2H STS RPT: status %d\n", status); 5644 return; 5645 } 5646 5647 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5648 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5649 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5650 5651 if (!rsp) 5652 return; 5653 5654 data.err = err; 5655 cond = RTW89_MCC_WAIT_COND(group, func); 5656 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5657 } 5658 5659 static void 5660 rtw89_mac_c2h_tx_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5661 { 5662 struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt; 5663 struct rtw89_tx_skb_data *skb_data; 5664 u8 sw_define, tx_status, txcnt; 5665 struct sk_buff *skb; 5666 5667 if (rtwdev->chip->chip_id == RTL8922A) { 5668 const struct rtw89_c2h_mac_tx_rpt_v2 *rpt_v2; 5669 5670 rpt_v2 = (const struct rtw89_c2h_mac_tx_rpt_v2 *)c2h->data; 5671 sw_define = le32_get_bits(rpt_v2->w12, 5672 RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2); 5673 tx_status = le32_get_bits(rpt_v2->w12, 5674 RTW89_C2H_MAC_TX_RPT_W12_TX_STATE_V2); 5675 txcnt = le32_get_bits(rpt_v2->w14, 5676 RTW89_C2H_MAC_TX_RPT_W14_DATA_TX_CNT_V2); 5677 } else { 5678 const struct rtw89_c2h_mac_tx_rpt *rpt; 5679 5680 rpt = (const struct rtw89_c2h_mac_tx_rpt *)c2h->data; 5681 sw_define = le32_get_bits(rpt->w2, RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE); 5682 tx_status = le32_get_bits(rpt->w2, RTW89_C2H_MAC_TX_RPT_W2_TX_STATE); 5683 if (rtwdev->chip->chip_id == RTL8852C) 5684 txcnt = le32_get_bits(rpt->w5, 5685 RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT_V1); 5686 else 5687 txcnt = le32_get_bits(rpt->w5, 5688 RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT); 5689 } 5690 5691 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 5692 "C2H TX RPT: sn %d, tx_status %d, txcnt %d\n", 5693 sw_define, tx_status, txcnt); 5694 5695 /* claim sw_define is not over size of tx_rpt->skbs[] */ 5696 static_assert(hweight32(RTW89_MAX_TX_RPTS_MASK) == 5697 hweight32(RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2) && 5698 hweight32(RTW89_MAX_TX_RPTS_MASK) == 5699 hweight32(RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE)); 5700 5701 scoped_guard(spinlock_irqsave, &tx_rpt->skb_lock) { 5702 skb = tx_rpt->skbs[sw_define]; 5703 5704 /* skip if no skb (normally shouldn't happen) */ 5705 if (!skb) { 5706 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 5707 "C2H TX RPT: no skb found in queue\n"); 5708 return; 5709 } 5710 5711 skb_data = RTW89_TX_SKB_CB(skb); 5712 5713 /* skip if TX attempt has failed and retry limit has not been 5714 * reached yet 5715 */ 5716 if (tx_status != RTW89_TX_DONE && 5717 txcnt != skb_data->tx_pkt_cnt_lmt) 5718 return; 5719 5720 tx_rpt->skbs[sw_define] = NULL; 5721 rtw89_tx_rpt_tx_status(rtwdev, skb, tx_status); 5722 } 5723 } 5724 5725 static void 5726 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5727 { 5728 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5729 const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5730 struct rtw89_completion_data data = {}; 5731 struct rtw89_mac_mrc_tsf_rpt *rpt; 5732 unsigned int i; 5733 5734 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5735 rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5736 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5737 le32_get_bits(c2h_rpt->w2, 5738 RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5739 5740 for (i = 0; i < rpt->num; i++) { 5741 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5742 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5743 5744 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5745 5746 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5747 "MRC C2H TSF RPT: index %u> %llu\n", 5748 i, rpt->tsfs[i]); 5749 } 5750 5751 rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5752 } 5753 5754 static void 5755 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5756 { 5757 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 5758 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 5759 struct rtw89_wait_info *wait = &rtw_wow->wait; 5760 const struct rtw89_c2h_wow_aoac_report *c2h = 5761 (const struct rtw89_c2h_wow_aoac_report *)skb->data; 5762 struct rtw89_completion_data data = {}; 5763 5764 aoac_rpt->rpt_ver = c2h->rpt_ver; 5765 aoac_rpt->sec_type = c2h->sec_type; 5766 aoac_rpt->key_idx = c2h->key_idx; 5767 aoac_rpt->pattern_idx = c2h->pattern_idx; 5768 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok, 5769 RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX); 5770 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv)); 5771 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count, 5772 sizeof(aoac_rpt->eapol_key_replay_count)); 5773 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk)); 5774 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv)); 5775 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv)); 5776 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id); 5777 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn); 5778 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk)); 5779 5780 rtw89_complete_cond(wait, RTW89_WOW_WAIT_COND_AOAC, &data); 5781 } 5782 5783 static void 5784 rtw89_mac_c2h_mlo_link_cfg_stat(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5785 { 5786 const struct rtw89_c2h_mlo_link_cfg_rpt *c2h_rpt; 5787 struct rtw89_wait_info *wait = &rtwdev->mlo.wait; 5788 struct rtw89_completion_data data = {}; 5789 unsigned int cond; 5790 u16 mac_id; 5791 u8 status; 5792 5793 c2h_rpt = (const struct rtw89_c2h_mlo_link_cfg_rpt *)c2h->data; 5794 5795 mac_id = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MLO_LINK_CFG_RPT_W2_MACID); 5796 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MLO_LINK_CFG_RPT_W2_STATUS); 5797 5798 data.err = status == RTW89_C2H_MLO_LINK_CFG_ROLE_NOT_EXIST || 5799 status == RTW89_C2H_MLO_LINK_CFG_RUNNING; 5800 cond = RTW89_MLO_WAIT_COND(mac_id, H2C_FUNC_MLO_LINK_CFG); 5801 rtw89_complete_cond(wait, cond, &data); 5802 } 5803 5804 static void 5805 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5806 { 5807 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5808 const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5809 struct rtw89_completion_data data = {}; 5810 enum rtw89_mac_mrc_status status; 5811 unsigned int cond; 5812 bool next = false; 5813 u32 tsf_high; 5814 u32 tsf_low; 5815 u8 sch_idx; 5816 u8 func; 5817 5818 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5819 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5820 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5821 tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5822 tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5823 5824 switch (status) { 5825 case RTW89_MAC_MRC_START_SCH_OK: 5826 func = H2C_FUNC_START_MRC; 5827 break; 5828 case RTW89_MAC_MRC_STOP_SCH_OK: 5829 /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5830 func = H2C_FUNC_DEL_MRC; 5831 next = true; 5832 break; 5833 case RTW89_MAC_MRC_DEL_SCH_OK: 5834 func = H2C_FUNC_DEL_MRC; 5835 break; 5836 case RTW89_MAC_MRC_EMPTY_SCH_FAIL: 5837 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5838 "MRC C2H STS RPT: empty sch fail\n"); 5839 return; 5840 case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL: 5841 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5842 "MRC C2H STS RPT: role not exist fail\n"); 5843 return; 5844 case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL: 5845 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5846 "MRC C2H STS RPT: data not found fail\n"); 5847 return; 5848 case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL: 5849 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5850 "MRC C2H STS RPT: get next slot fail\n"); 5851 return; 5852 case RTW89_MAC_MRC_ALT_ROLE_FAIL: 5853 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5854 "MRC C2H STS RPT: alt role fail\n"); 5855 return; 5856 case RTW89_MAC_MRC_ADD_PSTIMER_FAIL: 5857 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5858 "MRC C2H STS RPT: add ps timer fail\n"); 5859 return; 5860 case RTW89_MAC_MRC_MALLOC_FAIL: 5861 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5862 "MRC C2H STS RPT: malloc fail\n"); 5863 return; 5864 case RTW89_MAC_MRC_SWITCH_CH_FAIL: 5865 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5866 "MRC C2H STS RPT: switch ch fail\n"); 5867 return; 5868 case RTW89_MAC_MRC_TXNULL0_FAIL: 5869 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5870 "MRC C2H STS RPT: tx null-0 fail\n"); 5871 return; 5872 case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL: 5873 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5874 "MRC C2H STS RPT: port func en fail\n"); 5875 return; 5876 default: 5877 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5878 "invalid MRC C2H STS RPT: status %d\n", status); 5879 return; 5880 } 5881 5882 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5883 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 5884 sch_idx, status, (u64)tsf_high << 32 | tsf_low); 5885 5886 if (next) 5887 return; 5888 5889 cond = RTW89_MRC_WAIT_COND(sch_idx, func); 5890 rtw89_complete_cond(wait, cond, &data); 5891 } 5892 5893 static void 5894 rtw89_mac_c2h_pwr_int_notify(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5895 { 5896 const struct rtw89_c2h_pwr_int_notify *c2h; 5897 struct rtw89_sta_link *rtwsta_link; 5898 struct ieee80211_sta *sta; 5899 struct rtw89_sta *rtwsta; 5900 u16 macid; 5901 bool ps; 5902 5903 c2h = (const struct rtw89_c2h_pwr_int_notify *)skb->data; 5904 macid = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_MACID); 5905 ps = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS); 5906 5907 rcu_read_lock(); 5908 5909 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 5910 if (unlikely(!rtwsta_link)) 5911 goto out; 5912 5913 rtwsta = rtwsta_link->rtwsta; 5914 if (ps) 5915 set_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5916 else 5917 clear_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags); 5918 5919 sta = rtwsta_to_sta(rtwsta); 5920 ieee80211_sta_ps_transition(sta, ps); 5921 5922 out: 5923 rcu_read_unlock(); 5924 } 5925 5926 static 5927 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5928 struct sk_buff *c2h, u32 len) = { 5929 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5930 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5931 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5932 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = rtw89_mac_c2h_bcn_resend, 5933 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5934 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5935 [RTW89_MAC_C2H_FUNC_TX_DUTY_RPT] = rtw89_mac_c2h_tx_duty_rpt, 5936 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5937 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5938 }; 5939 5940 static 5941 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5942 struct sk_buff *c2h, u32 len) = { 5943 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5944 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5945 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5946 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5947 [RTW89_MAC_C2H_FUNC_BCN_UPD_DONE] = rtw89_mac_c2h_bcn_upd_done, 5948 }; 5949 5950 static 5951 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5952 struct sk_buff *c2h, u32 len) = { 5953 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5954 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5955 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5956 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5957 }; 5958 5959 static 5960 void (* const rtw89_mac_c2h_misc_handler[])(struct rtw89_dev *rtwdev, 5961 struct sk_buff *c2h, u32 len) = { 5962 [RTW89_MAC_C2H_FUNC_TX_REPORT] = rtw89_mac_c2h_tx_rpt, 5963 }; 5964 5965 static 5966 void (* const rtw89_mac_c2h_mlo_handler[])(struct rtw89_dev *rtwdev, 5967 struct sk_buff *c2h, u32 len) = { 5968 [RTW89_MAC_C2H_FUNC_MLO_GET_TBL] = NULL, 5969 [RTW89_MAC_C2H_FUNC_MLO_EMLSR_TRANS_DONE] = NULL, 5970 [RTW89_MAC_C2H_FUNC_MLO_EMLSR_STA_CFG_DONE] = NULL, 5971 [RTW89_MAC_C2H_FUNC_MCMLO_RELINK_RPT] = NULL, 5972 [RTW89_MAC_C2H_FUNC_MCMLO_SN_SYNC_RPT] = NULL, 5973 [RTW89_MAC_C2H_FUNC_MLO_LINK_CFG_STAT] = rtw89_mac_c2h_mlo_link_cfg_stat, 5974 [RTW89_MAC_C2H_FUNC_MLO_DM_DBG_DUMP] = NULL, 5975 }; 5976 5977 static 5978 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 5979 struct sk_buff *c2h, u32 len) = { 5980 [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 5981 [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 5982 }; 5983 5984 static 5985 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev, 5986 struct sk_buff *c2h, u32 len) = { 5987 [RTW89_MAC_C2H_FUNC_AOAC_REPORT] = rtw89_mac_c2h_wow_aoac_rpt, 5988 }; 5989 5990 static 5991 void (* const rtw89_mac_c2h_ap_handler[])(struct rtw89_dev *rtwdev, 5992 struct sk_buff *c2h, u32 len) = { 5993 [RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY] = rtw89_mac_c2h_pwr_int_notify, 5994 }; 5995 5996 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 5997 struct sk_buff *skb) 5998 { 5999 const struct rtw89_c2h_scanofld *c2h = 6000 (const struct rtw89_c2h_scanofld *)skb->data; 6001 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 6002 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 6003 struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(skb); 6004 struct rtw89_completion_data data = {}; 6005 unsigned int cond; 6006 u8 status, reason; 6007 6008 attr->is_scan_event = 1; 6009 attr->scan_seq = scan_info->seq; 6010 6011 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 6012 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 6013 data.err = status != RTW89_SCAN_STATUS_SUCCESS; 6014 6015 if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 6016 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 6017 cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 6018 else 6019 cond = RTW89_SCANOFLD_WAIT_COND_STOP; 6020 6021 rtw89_complete_cond(fw_ofld_wait, cond, &data); 6022 } 6023 } 6024 6025 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 6026 u8 class, u8 func) 6027 { 6028 switch (class) { 6029 default: 6030 return false; 6031 case RTW89_MAC_C2H_CLASS_INFO: 6032 switch (func) { 6033 default: 6034 return false; 6035 case RTW89_MAC_C2H_FUNC_REC_ACK: 6036 case RTW89_MAC_C2H_FUNC_DONE_ACK: 6037 return true; 6038 } 6039 case RTW89_MAC_C2H_CLASS_OFLD: 6040 switch (func) { 6041 default: 6042 return false; 6043 case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 6044 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 6045 return false; 6046 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 6047 return true; 6048 } 6049 case RTW89_MAC_C2H_CLASS_MCC: 6050 return true; 6051 case RTW89_MAC_C2H_CLASS_MISC: 6052 return true; 6053 case RTW89_MAC_C2H_CLASS_MLO: 6054 return true; 6055 case RTW89_MAC_C2H_CLASS_MRC: 6056 return true; 6057 case RTW89_MAC_C2H_CLASS_WOW: 6058 return true; 6059 case RTW89_MAC_C2H_CLASS_AP: 6060 switch (func) { 6061 default: 6062 return false; 6063 case RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY: 6064 return true; 6065 } 6066 } 6067 } 6068 6069 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6070 u32 len, u8 class, u8 func) 6071 { 6072 void (*handler)(struct rtw89_dev *rtwdev, 6073 struct sk_buff *c2h, u32 len) = NULL; 6074 6075 switch (class) { 6076 case RTW89_MAC_C2H_CLASS_INFO: 6077 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 6078 handler = rtw89_mac_c2h_info_handler[func]; 6079 break; 6080 case RTW89_MAC_C2H_CLASS_OFLD: 6081 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 6082 handler = rtw89_mac_c2h_ofld_handler[func]; 6083 break; 6084 case RTW89_MAC_C2H_CLASS_MCC: 6085 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 6086 handler = rtw89_mac_c2h_mcc_handler[func]; 6087 break; 6088 case RTW89_MAC_C2H_CLASS_MISC: 6089 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MISC) 6090 handler = rtw89_mac_c2h_misc_handler[func]; 6091 break; 6092 case RTW89_MAC_C2H_CLASS_MLO: 6093 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MLO) 6094 handler = rtw89_mac_c2h_mlo_handler[func]; 6095 break; 6096 case RTW89_MAC_C2H_CLASS_MRC: 6097 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 6098 handler = rtw89_mac_c2h_mrc_handler[func]; 6099 break; 6100 case RTW89_MAC_C2H_CLASS_WOW: 6101 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_WOW) 6102 handler = rtw89_mac_c2h_wow_handler[func]; 6103 break; 6104 case RTW89_MAC_C2H_CLASS_AP: 6105 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_AP) 6106 handler = rtw89_mac_c2h_ap_handler[func]; 6107 break; 6108 case RTW89_MAC_C2H_CLASS_FWDBG: 6109 case RTW89_MAC_C2H_CLASS_ROLE: 6110 return; 6111 default: 6112 break; 6113 } 6114 if (!handler) { 6115 rtw89_info_once(rtwdev, "MAC c2h class %d func %d not support\n", 6116 class, func); 6117 return; 6118 } 6119 handler(rtwdev, skb, len); 6120 } 6121 6122 static 6123 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 6124 enum rtw89_phy_idx phy_idx, 6125 u32 reg_base, u32 *cr) 6126 { 6127 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 6128 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 6129 6130 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 6131 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 6132 addr); 6133 goto error; 6134 } 6135 6136 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 6137 if (mode == RTW89_QTA_SCC) { 6138 rtw89_err(rtwdev, 6139 "[TXPWR] addr=0x%x but hw not enable\n", 6140 addr); 6141 goto error; 6142 } 6143 6144 *cr = addr; 6145 return true; 6146 6147 error: 6148 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 6149 addr, phy_idx); 6150 6151 return false; 6152 } 6153 6154 static 6155 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 6156 { 6157 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 6158 int ret; 6159 6160 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6161 if (ret) 6162 return ret; 6163 6164 if (!enable) { 6165 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 6166 return 0; 6167 } 6168 6169 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 6170 B_AX_APP_MAC_INFO_RPT | 6171 B_AX_APP_PLCP_HDR_RPT | 6172 B_AX_PPDU_STAT_RPT_CRC32); 6173 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 6174 RTW89_PRPT_DEST_HOST); 6175 6176 return 0; 6177 } 6178 6179 static 6180 void __rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 6181 { 6182 #define MAC_AX_TIME_TH_SH 5 6183 #define MAC_AX_LEN_TH_SH 4 6184 #define MAC_AX_TIME_TH_MAX 255 6185 #define MAC_AX_LEN_TH_MAX 255 6186 #define MAC_AX_TIME_TH_DEF 88 6187 #define MAC_AX_LEN_TH_DEF 4080 6188 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6189 struct ieee80211_hw *hw = rtwdev->hw; 6190 u32 rts_threshold = hw->wiphy->rts_threshold; 6191 u32 time_th, len_th; 6192 u32 reg; 6193 6194 if (rts_threshold == (u32)-1) { 6195 time_th = MAC_AX_TIME_TH_DEF; 6196 len_th = MAC_AX_LEN_TH_DEF; 6197 } else { 6198 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 6199 len_th = rts_threshold; 6200 } 6201 6202 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 6203 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 6204 6205 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 6206 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 6207 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 6208 } 6209 6210 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev) 6211 { 6212 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 6213 if (rtwdev->dbcc_en) 6214 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_1); 6215 } 6216 6217 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 6218 { 6219 bool empty; 6220 int ret; 6221 6222 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6223 return; 6224 6225 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 6226 10000, 200000, false, rtwdev); 6227 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 6228 rtw89_info(rtwdev, "timed out to flush queues\n"); 6229 } 6230 6231 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 6232 { 6233 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 6234 u8 val; 6235 u16 val16; 6236 u32 val32; 6237 int ret; 6238 6239 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 6240 if (chip_id != RTL8851B && chip_id != RTL8852BT) 6241 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 6242 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 6243 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 6244 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 6245 if (chip_id != RTL8851B && chip_id != RTL8852BT) 6246 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 6247 6248 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 6249 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 6250 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 6251 6252 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 6253 if (ret) { 6254 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6255 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 6256 return ret; 6257 } 6258 val32 = val32 & B_AX_WL_RX_CTRL; 6259 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 6260 if (ret) { 6261 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6262 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 6263 return ret; 6264 } 6265 6266 switch (coex->pta_mode) { 6267 case RTW89_MAC_AX_COEX_RTK_MODE: 6268 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 6269 val &= ~B_AX_BTMODE_MASK; 6270 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 6271 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 6272 6273 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 6274 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 6275 6276 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 6277 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 6278 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 6279 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 6280 break; 6281 case RTW89_MAC_AX_COEX_CSR_MODE: 6282 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 6283 val &= ~B_AX_BTMODE_MASK; 6284 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 6285 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 6286 6287 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 6288 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 6289 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 6290 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 6291 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 6292 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 6293 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 6294 val16 |= B_AX_ENHANCED_BT; 6295 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 6296 6297 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 6298 break; 6299 default: 6300 return -EINVAL; 6301 } 6302 6303 switch (coex->direction) { 6304 case RTW89_MAC_AX_COEX_INNER: 6305 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6306 val = (val & ~BIT(2)) | BIT(1); 6307 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6308 break; 6309 case RTW89_MAC_AX_COEX_OUTPUT: 6310 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6311 val = val | BIT(1) | BIT(0); 6312 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6313 break; 6314 case RTW89_MAC_AX_COEX_INPUT: 6315 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6316 val = val & ~(BIT(2) | BIT(1)); 6317 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6318 break; 6319 default: 6320 return -EINVAL; 6321 } 6322 6323 return 0; 6324 } 6325 EXPORT_SYMBOL(rtw89_mac_coex_init); 6326 6327 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 6328 const struct rtw89_mac_ax_coex *coex) 6329 { 6330 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 6331 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 6332 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 6333 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 6334 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 6335 6336 switch (coex->pta_mode) { 6337 case RTW89_MAC_AX_COEX_RTK_MODE: 6338 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 6339 MAC_AX_RTK_MODE); 6340 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 6341 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 6342 break; 6343 case RTW89_MAC_AX_COEX_CSR_MODE: 6344 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 6345 MAC_AX_CSR_MODE); 6346 break; 6347 default: 6348 return -EINVAL; 6349 } 6350 6351 return 0; 6352 } 6353 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 6354 6355 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6356 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6357 { 6358 u32 val = 0, ret; 6359 6360 if (gnt_cfg->band[0].gnt_bt) 6361 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 6362 6363 if (gnt_cfg->band[0].gnt_bt_sw_en) 6364 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 6365 6366 if (gnt_cfg->band[0].gnt_wl) 6367 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 6368 6369 if (gnt_cfg->band[0].gnt_wl_sw_en) 6370 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 6371 6372 if (gnt_cfg->band[1].gnt_bt) 6373 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 6374 6375 if (gnt_cfg->band[1].gnt_bt_sw_en) 6376 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 6377 6378 if (gnt_cfg->band[1].gnt_wl) 6379 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 6380 6381 if (gnt_cfg->band[1].gnt_wl_sw_en) 6382 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 6383 6384 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 6385 if (ret) { 6386 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6387 rtw89_err(rtwdev, "Write LTE fail!\n"); 6388 return ret; 6389 } 6390 6391 return 0; 6392 } 6393 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 6394 6395 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 6396 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6397 { 6398 u32 val = 0; 6399 6400 if (gnt_cfg->band[0].gnt_bt) 6401 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 6402 B_AX_GNT_BT_TX_VAL; 6403 else 6404 val |= B_AX_WL_ACT_VAL; 6405 6406 if (gnt_cfg->band[0].gnt_bt_sw_en) 6407 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 6408 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 6409 6410 if (gnt_cfg->band[0].gnt_wl) 6411 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 6412 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 6413 6414 if (gnt_cfg->band[0].gnt_wl_sw_en) 6415 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 6416 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 6417 6418 if (gnt_cfg->band[1].gnt_bt) 6419 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 6420 B_AX_GNT_BT_TX_VAL; 6421 else 6422 val |= B_AX_WL_ACT_VAL; 6423 6424 if (gnt_cfg->band[1].gnt_bt_sw_en) 6425 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 6426 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 6427 6428 if (gnt_cfg->band[1].gnt_wl) 6429 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 6430 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 6431 6432 if (gnt_cfg->band[1].gnt_wl_sw_en) 6433 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 6434 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 6435 6436 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 6437 6438 return 0; 6439 } 6440 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 6441 6442 static 6443 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 6444 { 6445 u32 reg; 6446 u16 val; 6447 int ret; 6448 6449 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 6450 if (ret) 6451 return ret; 6452 6453 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 6454 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 6455 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 6456 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 6457 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 6458 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 6459 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 6460 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 6461 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 6462 B_AX_PLT_EN; 6463 rtw89_write16(rtwdev, reg, val); 6464 6465 return 0; 6466 } 6467 6468 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 6469 { 6470 const struct rtw89_chip_info *chip = rtwdev->chip; 6471 u32 reg = chip->btc_sb.n[0].cfg; 6472 u32 fw_sb; 6473 6474 fw_sb = rtw89_read32(rtwdev, reg); 6475 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 6476 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 6477 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6478 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 6479 else 6480 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 6481 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 6482 val = B_AX_TOGGLE | 6483 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 6484 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 6485 rtw89_write32(rtwdev, reg, val); 6486 fsleep(1000); /* avoid BT FW loss information */ 6487 } 6488 6489 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 6490 { 6491 const struct rtw89_chip_info *chip = rtwdev->chip; 6492 u32 reg = chip->btc_sb.n[0].get; 6493 6494 return rtw89_read32(rtwdev, reg); 6495 } 6496 6497 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6498 { 6499 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 6500 6501 val = wl ? val | BIT(2) : val & ~BIT(2); 6502 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 6503 6504 return 0; 6505 } 6506 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 6507 6508 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 6509 { 6510 struct rtw89_btc *btc = &rtwdev->btc; 6511 struct rtw89_btc_dm *dm = &btc->dm; 6512 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 6513 int i; 6514 6515 if (wl) 6516 return 0; 6517 6518 for (i = 0; i < RTW89_PHY_NUM; i++) { 6519 g[i].gnt_bt_sw_en = 1; 6520 g[i].gnt_bt = 1; 6521 g[i].gnt_wl_sw_en = 1; 6522 g[i].gnt_wl = 0; 6523 } 6524 6525 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 6526 } 6527 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 6528 6529 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 6530 { 6531 const struct rtw89_chip_info *chip = rtwdev->chip; 6532 u8 val = 0; 6533 6534 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) 6535 return false; 6536 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6537 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 6538 B_AX_LTE_MUX_CTRL_PATH >> 24); 6539 6540 return !!val; 6541 } 6542 6543 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 6544 { 6545 u32 reg; 6546 u16 cnt; 6547 6548 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 6549 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 6550 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 6551 6552 return cnt; 6553 } 6554 6555 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 6556 bool keep) 6557 { 6558 u32 reg; 6559 6560 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 6561 return; 6562 6563 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 6564 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6565 if (keep) { 6566 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6567 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6568 BFRP_RX_STANDBY_TIMER_KEEP); 6569 } else { 6570 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6571 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6572 BFRP_RX_STANDBY_TIMER_RELEASE); 6573 } 6574 } 6575 6576 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 6577 { 6578 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6579 u32 reg; 6580 u32 mask = mac->bfee_ctrl.mask; 6581 6582 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 6583 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 6584 if (en) { 6585 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6586 rtw89_write32_set(rtwdev, reg, mask); 6587 } else { 6588 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6589 rtw89_write32_clr(rtwdev, reg, mask); 6590 } 6591 } 6592 6593 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 6594 { 6595 u32 reg; 6596 u32 val32; 6597 int ret; 6598 6599 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6600 if (ret) 6601 return ret; 6602 6603 /* AP mode set tx gid to 63 */ 6604 /* STA mode set tx gid to 0(default) */ 6605 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 6606 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 6607 6608 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 6609 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 6610 6611 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6612 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 6613 rtw89_write32(rtwdev, reg, val32); 6614 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 6615 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 6616 6617 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6618 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 6619 B_AX_BFMEE_USE_NSTS | 6620 B_AX_BFMEE_CSI_GID_SEL | 6621 B_AX_BFMEE_CSI_FORCE_RETE_EN); 6622 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 6623 rtw89_write32(rtwdev, reg, 6624 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 6625 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 6626 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 6627 6628 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 6629 rtw89_write32_set(rtwdev, reg, 6630 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 6631 6632 return 0; 6633 } 6634 6635 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 6636 struct rtw89_vif_link *rtwvif_link, 6637 struct rtw89_sta_link *rtwsta_link) 6638 { 6639 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 6640 struct ieee80211_link_sta *link_sta; 6641 u8 mac_idx = rtwvif_link->mac_idx; 6642 u8 port_sel = rtwvif_link->port; 6643 u8 sound_dim = 3, t; 6644 u8 *phy_cap; 6645 u32 reg; 6646 u16 val; 6647 int ret; 6648 6649 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6650 if (ret) 6651 return ret; 6652 6653 rcu_read_lock(); 6654 6655 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6656 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; 6657 6658 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6659 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 6660 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 6661 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 6662 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 6663 phy_cap[5]); 6664 sound_dim = min(sound_dim, t); 6665 } 6666 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6667 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 6668 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 6669 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 6670 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 6671 link_sta->vht_cap.cap); 6672 sound_dim = min(sound_dim, t); 6673 } 6674 nc = min(nc, sound_dim); 6675 nr = min(nr, sound_dim); 6676 6677 rcu_read_unlock(); 6678 6679 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6680 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6681 6682 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 6683 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 6684 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 6685 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 6686 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 6687 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 6688 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 6689 6690 if (port_sel == 0) 6691 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6692 else 6693 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 6694 6695 rtw89_write16(rtwdev, reg, val); 6696 6697 return 0; 6698 } 6699 6700 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 6701 struct rtw89_vif_link *rtwvif_link, 6702 struct rtw89_sta_link *rtwsta_link) 6703 { 6704 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 6705 struct ieee80211_link_sta *link_sta; 6706 u8 mac_idx = rtwvif_link->mac_idx; 6707 u32 reg; 6708 int ret; 6709 6710 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6711 if (ret) 6712 return ret; 6713 6714 rcu_read_lock(); 6715 6716 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6717 6718 if (link_sta->he_cap.has_he) { 6719 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 6720 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 6721 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 6722 } 6723 if (link_sta->vht_cap.vht_supported) { 6724 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 6725 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 6726 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 6727 } 6728 if (link_sta->ht_cap.ht_supported) { 6729 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 6730 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 6731 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 6732 } 6733 6734 rcu_read_unlock(); 6735 6736 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6737 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6738 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 6739 rtw89_write32(rtwdev, 6740 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 6741 rrsc); 6742 6743 return 0; 6744 } 6745 6746 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 6747 struct rtw89_vif_link *rtwvif_link, 6748 struct rtw89_sta_link *rtwsta_link) 6749 { 6750 struct ieee80211_link_sta *link_sta; 6751 bool has_beamformer_cap; 6752 6753 rcu_read_lock(); 6754 6755 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6756 has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta); 6757 6758 rcu_read_unlock(); 6759 6760 if (has_beamformer_cap) { 6761 rtw89_debug(rtwdev, RTW89_DBG_BF, 6762 "initialize bfee for new association\n"); 6763 rtw89_mac_init_bfee_ax(rtwdev, rtwvif_link->mac_idx); 6764 rtw89_mac_set_csi_para_reg_ax(rtwdev, rtwvif_link, rtwsta_link); 6765 rtw89_mac_csi_rrsc_ax(rtwdev, rtwvif_link, rtwsta_link); 6766 } 6767 } 6768 6769 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, 6770 struct rtw89_vif_link *rtwvif_link, 6771 struct rtw89_sta_link *rtwsta_link) 6772 { 6773 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, false); 6774 } 6775 6776 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6777 struct ieee80211_bss_conf *conf) 6778 { 6779 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6780 const struct rtw89_mac_mu_gid_addr *addr = mac->mu_gid; 6781 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 6782 struct rtw89_vif_link *rtwvif_link; 6783 u8 mac_idx; 6784 __le32 *p; 6785 6786 rtwvif_link = rtwvif->links[conf->link_id]; 6787 if (unlikely(!rtwvif_link)) { 6788 rtw89_err(rtwdev, 6789 "%s: rtwvif link (link_id %u) is not active\n", 6790 __func__, conf->link_id); 6791 return; 6792 } 6793 6794 mac_idx = rtwvif_link->mac_idx; 6795 6796 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 6797 6798 p = (__le32 *)conf->mu_group.membership; 6799 rtw89_write32(rtwdev, 6800 rtw89_mac_reg_by_idx(rtwdev, addr->position_en[0], mac_idx), 6801 le32_to_cpu(p[0])); 6802 rtw89_write32(rtwdev, 6803 rtw89_mac_reg_by_idx(rtwdev, addr->position_en[1], mac_idx), 6804 le32_to_cpu(p[1])); 6805 6806 p = (__le32 *)conf->mu_group.position; 6807 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[0], mac_idx), 6808 le32_to_cpu(p[0])); 6809 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[1], mac_idx), 6810 le32_to_cpu(p[1])); 6811 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[2], mac_idx), 6812 le32_to_cpu(p[2])); 6813 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[3], mac_idx), 6814 le32_to_cpu(p[3])); 6815 } 6816 6817 struct rtw89_mac_bf_monitor_iter_data { 6818 struct rtw89_dev *rtwdev; 6819 struct rtw89_sta_link *down_rtwsta_link; 6820 int count; 6821 }; 6822 6823 static 6824 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 6825 { 6826 struct rtw89_mac_bf_monitor_iter_data *iter_data = 6827 (struct rtw89_mac_bf_monitor_iter_data *)data; 6828 struct rtw89_sta_link *down_rtwsta_link = iter_data->down_rtwsta_link; 6829 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6830 struct ieee80211_link_sta *link_sta; 6831 struct rtw89_sta_link *rtwsta_link; 6832 bool has_beamformer_cap = false; 6833 int *count = &iter_data->count; 6834 unsigned int link_id; 6835 6836 rcu_read_lock(); 6837 6838 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6839 if (rtwsta_link == down_rtwsta_link) 6840 continue; 6841 6842 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 6843 if (rtw89_sta_has_beamformer_cap(link_sta)) { 6844 has_beamformer_cap = true; 6845 break; 6846 } 6847 } 6848 6849 if (has_beamformer_cap) 6850 (*count)++; 6851 6852 rcu_read_unlock(); 6853 } 6854 6855 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 6856 struct rtw89_sta_link *rtwsta_link, 6857 bool disconnect) 6858 { 6859 struct rtw89_mac_bf_monitor_iter_data data; 6860 6861 data.rtwdev = rtwdev; 6862 data.down_rtwsta_link = disconnect ? rtwsta_link : NULL; 6863 data.count = 0; 6864 ieee80211_iterate_stations_atomic(rtwdev->hw, 6865 rtw89_mac_bf_monitor_calc_iter, 6866 &data); 6867 6868 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 6869 if (data.count) 6870 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6871 else 6872 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6873 } 6874 6875 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 6876 { 6877 struct rtw89_traffic_stats *stats = &rtwdev->stats; 6878 struct rtw89_vif_link *rtwvif_link; 6879 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 6880 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6881 struct rtw89_vif *rtwvif; 6882 bool keep_timer = true; 6883 unsigned int link_id; 6884 bool old_keep_timer; 6885 6886 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6887 6888 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 6889 keep_timer = false; 6890 6891 if (keep_timer != old_keep_timer) { 6892 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6893 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6894 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif_link->mac_idx, 6895 keep_timer); 6896 } 6897 6898 if (en == old) 6899 return; 6900 6901 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6902 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 6903 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, en); 6904 } 6905 6906 static int 6907 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6908 u32 tx_time) 6909 { 6910 #define MAC_AX_DFLT_TX_TIME 5280 6911 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6912 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6913 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 6914 u32 reg; 6915 int ret = 0; 6916 6917 if (rtwsta_link->cctl_tx_time) { 6918 rtwsta_link->ampdu_max_time = (max_tx_time - 512) >> 9; 6919 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6920 } else { 6921 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6922 if (ret) { 6923 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 6924 return ret; 6925 } 6926 6927 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_limit.addr, mac_idx); 6928 rtw89_write32_mask(rtwdev, reg, mac->agg_limit.mask, 6929 max_tx_time >> 5); 6930 } 6931 6932 return ret; 6933 } 6934 6935 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6936 bool resume, u32 tx_time) 6937 { 6938 int ret = 0; 6939 6940 if (!resume) { 6941 rtwsta_link->cctl_tx_time = true; 6942 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6943 } else { 6944 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 6945 rtwsta_link->cctl_tx_time = false; 6946 } 6947 6948 return ret; 6949 } 6950 6951 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 6952 u32 *tx_time) 6953 { 6954 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6955 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6956 u32 reg; 6957 int ret = 0; 6958 6959 if (rtwsta_link->cctl_tx_time) { 6960 *tx_time = (rtwsta_link->ampdu_max_time + 1) << 9; 6961 } else { 6962 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6963 if (ret) { 6964 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 6965 return ret; 6966 } 6967 6968 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_limit.addr, mac_idx); 6969 *tx_time = rtw89_read32_mask(rtwdev, reg, mac->agg_limit.mask) << 5; 6970 } 6971 6972 return ret; 6973 } 6974 6975 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 6976 struct rtw89_sta_link *rtwsta_link, 6977 bool resume, u8 tx_retry) 6978 { 6979 int ret = 0; 6980 6981 rtwsta_link->data_tx_cnt_lmt = tx_retry; 6982 6983 if (!resume) { 6984 rtwsta_link->cctl_tx_retry_limit = true; 6985 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6986 } else { 6987 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 6988 rtwsta_link->cctl_tx_retry_limit = false; 6989 } 6990 6991 return ret; 6992 } 6993 6994 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 6995 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry) 6996 { 6997 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6998 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 6999 u32 reg; 7000 int ret = 0; 7001 7002 if (rtwsta_link->cctl_tx_retry_limit) { 7003 *tx_retry = rtwsta_link->data_tx_cnt_lmt; 7004 } else { 7005 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 7006 if (ret) { 7007 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 7008 return ret; 7009 } 7010 7011 reg = rtw89_mac_reg_by_idx(rtwdev, mac->txcnt_limit.addr, mac_idx); 7012 *tx_retry = rtw89_read32_mask(rtwdev, reg, mac->txcnt_limit.mask); 7013 } 7014 7015 return ret; 7016 } 7017 7018 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 7019 struct rtw89_vif_link *rtwvif_link, bool en) 7020 { 7021 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7022 u8 mac_idx = rtwvif_link->mac_idx; 7023 u16 set = mac->muedca_ctrl.mask; 7024 u32 reg; 7025 int ret; 7026 7027 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 7028 if (ret) 7029 return ret; 7030 7031 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 7032 if (en) 7033 rtw89_write16_set(rtwdev, reg, set); 7034 else 7035 rtw89_write16_clr(rtwdev, reg, set); 7036 7037 return 0; 7038 } 7039 7040 static 7041 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 7042 { 7043 u32 val32; 7044 int ret; 7045 7046 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 7047 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 7048 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 7049 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 7050 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 7051 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 7052 7053 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 7054 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 7055 if (ret) { 7056 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 7057 offset, val, mask); 7058 return ret; 7059 } 7060 7061 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) && 7062 (u32_get_bits(val32, B_AX_WL_XTAL_SI_ADDR_MASK) != offset || 7063 u32_get_bits(val32, B_AX_WL_XTAL_SI_DATA_MASK) != val)) 7064 rtw89_warn(rtwdev, "xtal si write: offset=%x val=%x poll=%x\n", 7065 offset, val, val32); 7066 7067 return 0; 7068 } 7069 7070 static 7071 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 7072 { 7073 u32 val32; 7074 int ret; 7075 7076 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 7077 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 7078 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 7079 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 7080 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 7081 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 7082 7083 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 7084 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 7085 if (ret) { 7086 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 7087 return ret; 7088 } 7089 7090 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) && 7091 u32_get_bits(val32, B_AX_WL_XTAL_SI_ADDR_MASK) != offset) 7092 rtw89_warn(rtwdev, "xtal si read: offset=%x poll=%x\n", 7093 offset, val32); 7094 7095 *val = u32_get_bits(val32, B_AX_WL_XTAL_SI_DATA_MASK); 7096 7097 return 0; 7098 } 7099 7100 static 7101 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, 7102 struct rtw89_vif_link *rtwvif_link, 7103 struct rtw89_sta_link *rtwsta_link) 7104 { 7105 static const enum rtw89_pkt_drop_sel sels[] = { 7106 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 7107 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 7108 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 7109 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 7110 }; 7111 struct rtw89_pkt_drop_params params = {0}; 7112 int i; 7113 7114 params.mac_band = rtwvif_link->mac_idx; 7115 params.macid = rtwsta_link->mac_id; 7116 params.port = rtwvif_link->port; 7117 params.mbssid = 0; 7118 params.tf_trs = rtwvif_link->trigger; 7119 7120 for (i = 0; i < ARRAY_SIZE(sels); i++) { 7121 params.sel = sels[i]; 7122 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 7123 } 7124 } 7125 7126 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 7127 { 7128 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 7129 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 7130 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 7131 struct rtw89_vif_link *rtwvif_link; 7132 struct rtw89_sta_link *rtwsta_link; 7133 struct rtw89_vif *target = data; 7134 unsigned int link_id; 7135 7136 if (rtwvif != target) 7137 return; 7138 7139 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 7140 rtwvif_link = rtwsta_link->rtwvif_link; 7141 rtw89_mac_pkt_drop_sta(rtwdev, rtwvif_link, rtwsta_link); 7142 } 7143 } 7144 7145 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 7146 { 7147 ieee80211_iterate_stations_atomic(rtwdev->hw, 7148 rtw89_mac_pkt_drop_vif_iter, 7149 rtwvif); 7150 } 7151 7152 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 7153 enum rtw89_mac_idx band) 7154 { 7155 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7156 struct rtw89_pkt_drop_params params = {0}; 7157 bool empty; 7158 int i, ret = 0, try_cnt = 3; 7159 7160 params.mac_band = band; 7161 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 7162 7163 for (i = 0; i < try_cnt; i++) { 7164 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 7165 50000, false, rtwdev); 7166 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 7167 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 7168 else 7169 return 0; 7170 } 7171 return ret; 7172 } 7173 7174 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 7175 { 7176 struct rtw89_mac_h2c_info h2c_info = {}; 7177 struct rtw89_mac_c2h_info c2h_info = {}; 7178 int ret; 7179 7180 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 7181 return 0; 7182 7183 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; 7184 h2c_info.content_len = sizeof(h2c_info.u.hdr); 7185 h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); 7186 7187 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 7188 if (ret) 7189 return ret; 7190 7191 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) 7192 ret = -EINVAL; 7193 7194 return ret; 7195 } 7196 7197 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 7198 { 7199 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7200 const struct rtw89_chip_info *chip = rtwdev->chip; 7201 int ret; 7202 7203 if (enable_wow) { 7204 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 7205 if (ret) { 7206 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 7207 return ret; 7208 } 7209 7210 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 7211 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 7212 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 7213 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 7214 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 7215 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 7216 rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 7217 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 7218 7219 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 7220 return 0; 7221 7222 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 7223 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 7224 else 7225 rtw89_write32_set(rtwdev, R_AX_DBG_WOW, 7226 B_AX_DBG_WOW_CPU_IO_RX_EN); 7227 } else { 7228 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 7229 if (ret) { 7230 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 7231 return ret; 7232 } 7233 7234 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 7235 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 7236 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 7237 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 7238 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 7239 } 7240 7241 return 0; 7242 } 7243 7244 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 7245 { 7246 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 7247 7248 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 7249 } 7250 7251 static 7252 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 7253 bool h2c_or_fwdl) 7254 { 7255 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 7256 u32 timeout; 7257 u8 val; 7258 7259 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 7260 timeout = FWDL_WAIT_CNT_USB; 7261 else 7262 timeout = FWDL_WAIT_CNT; 7263 7264 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 7265 1, timeout, false, 7266 rtwdev, R_AX_WCPU_FW_CTRL); 7267 } 7268 7269 static 7270 void rtw89_fwdl_secure_idmem_share_mode_ax(struct rtw89_dev *rtwdev, u8 mode) 7271 { 7272 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 7273 7274 if (!sec->secure_boot) 7275 return; 7276 7277 rtw89_write32_mask(rtwdev, R_AX_WCPU_FW_CTRL, 7278 B_AX_IDMEM_SHARE_MODE_RECORD_MASK, mode); 7279 rtw89_write32_set(rtwdev, R_AX_WCPU_FW_CTRL, 7280 B_AX_IDMEM_SHARE_MODE_RECORD_VALID); 7281 } 7282 7283 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 7284 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 7285 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 7286 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 7287 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 7288 .mem_page_size = MAC_MEM_DUMP_PAGE_SIZE_AX, 7289 .rx_fltr = R_AX_RX_FLTR_OPT, 7290 .port_base = &rtw89_port_base_ax, 7291 .agg_len_ht = R_AX_AGG_LEN_HT_0, 7292 .ps_status = R_AX_PPWRBIT_SETTING, 7293 .mu_gid = &rtw89_mac_mu_gid_addr_ax, 7294 7295 .muedca_ctrl = { 7296 .addr = R_AX_MUEDCA_EN, 7297 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 7298 }, 7299 .bfee_ctrl = { 7300 .addr = R_AX_BFMEE_RESP_OPTION, 7301 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 7302 B_AX_BFMEE_HE_NDPA_EN, 7303 }, 7304 .narrow_bw_ru_dis = { 7305 .addr = R_AX_RXTRIG_TEST_USER_2, 7306 .mask = B_AX_RXTRIG_RU26_DIS, 7307 }, 7308 .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 7309 .agg_limit = {.addr = R_AX_AMPDU_AGG_LIMIT, .mask = B_AX_AMPDU_MAX_TIME_MASK,}, 7310 .txcnt_limit = {.addr = R_AX_TXCNT, .mask = B_AX_L_TXCNT_LMT_MASK,}, 7311 7312 .check_mac_en = rtw89_mac_check_mac_en_ax, 7313 .sys_init = sys_init_ax, 7314 .trx_init = trx_init_ax, 7315 .preload_init = preload_init_set_ax, 7316 .clr_aon_intr = NULL, 7317 .err_imr_ctrl = err_imr_ctrl_ax, 7318 .mac_func_en = NULL, 7319 .hci_func_en = rtw89_mac_hci_func_en_ax, 7320 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 7321 .dle_func_en = dle_func_en_ax, 7322 .dle_clk_en = dle_clk_en_ax, 7323 .bf_assoc = rtw89_mac_bf_assoc_ax, 7324 7325 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 7326 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 7327 .cfg_phy_rpt = NULL, 7328 .set_edcca_mode = NULL, 7329 7330 .dle_mix_cfg = dle_mix_cfg_ax, 7331 .chk_dle_rdy = chk_dle_rdy_ax, 7332 .dle_buf_req = dle_buf_req_ax, 7333 .hfc_func_en = hfc_func_en_ax, 7334 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 7335 .hfc_mix_cfg = hfc_mix_cfg_ax, 7336 .hfc_get_mix_info = hfc_get_mix_info_ax, 7337 .wde_quota_cfg = wde_quota_cfg_ax, 7338 .ple_quota_cfg = ple_quota_cfg_ax, 7339 .set_cpuio = set_cpuio_ax, 7340 .dle_quota_change = dle_quota_change_ax, 7341 7342 .reset_pwr_state = rtw89_mac_reset_pwr_state_ax, 7343 .disable_cpu = rtw89_mac_disable_cpu_ax, 7344 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 7345 .fwdl_get_status = rtw89_fw_get_rdy_ax, 7346 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 7347 .fwdl_secure_idmem_share_mode = rtw89_fwdl_secure_idmem_share_mode_ax, 7348 .parse_efuse_map = rtw89_parse_efuse_map_ax, 7349 .parse_phycap_map = rtw89_parse_phycap_map_ax, 7350 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 7351 .efuse_read_fw_secure = rtw89_efuse_read_fw_secure_ax, 7352 .efuse_read_ecv = NULL, 7353 7354 .cfg_plt = rtw89_mac_cfg_plt_ax, 7355 .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 7356 7357 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 7358 7359 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 7360 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 7361 7362 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 7363 .dump_err_status = rtw89_mac_dump_err_status_ax, 7364 7365 .is_txq_empty = mac_is_txq_empty_ax, 7366 7367 .prep_chan_list = rtw89_hw_scan_prep_chan_list_ax, 7368 .free_chan_list = rtw89_hw_scan_free_chan_list_ax, 7369 .add_chan_list = rtw89_hw_scan_add_chan_list_ax, 7370 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_ax, 7371 .scan_offload = rtw89_fw_h2c_scan_offload_ax, 7372 7373 .wow_config_mac = rtw89_wow_config_mac_ax, 7374 }; 7375 EXPORT_SYMBOL(rtw89_mac_gen_ax); 7376