1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "pci.h" 11 #include "ps.h" 12 #include "reg.h" 13 #include "util.h" 14 15 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 16 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 17 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 18 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 19 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 20 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 21 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 22 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 25 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 26 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 29 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 31 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 33 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 34 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 35 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 36 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 37 }; 38 39 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 40 u32 val, enum rtw89_mac_mem_sel sel) 41 { 42 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43 u32 addr = mac->mem_base_addrs[sel] + offset; 44 45 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 46 rtw89_write32(rtwdev, mac->indir_access_addr, val); 47 } 48 49 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 50 enum rtw89_mac_mem_sel sel) 51 { 52 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 53 u32 addr = mac->mem_base_addrs[sel] + offset; 54 55 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 56 return rtw89_read32(rtwdev, mac->indir_access_addr); 57 } 58 59 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 60 enum rtw89_mac_hwmod_sel sel) 61 { 62 u32 val, r_val; 63 64 if (sel == RTW89_DMAC_SEL) { 65 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 66 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 67 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 68 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 69 val = B_AX_CMAC_EN; 70 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 71 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 72 val = B_AX_CMAC1_FEN; 73 } else { 74 return -EINVAL; 75 } 76 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 77 (val & r_val) != val) 78 return -EFAULT; 79 80 return 0; 81 } 82 83 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 84 { 85 u8 lte_ctrl; 86 int ret; 87 88 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 89 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 90 if (ret) 91 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 92 93 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 94 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 95 96 return ret; 97 } 98 99 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 100 { 101 u8 lte_ctrl; 102 int ret; 103 104 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 105 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 106 if (ret) 107 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 108 109 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 110 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 111 112 return ret; 113 } 114 115 static 116 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 117 { 118 u32 ctrl_reg, data_reg, ctrl_data; 119 u32 val; 120 int ret; 121 122 switch (ctrl->type) { 123 case DLE_CTRL_TYPE_WDE: 124 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 125 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 126 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 127 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 128 B_AX_WDE_DFI_ACTIVE; 129 break; 130 case DLE_CTRL_TYPE_PLE: 131 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 132 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 133 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 134 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 135 B_AX_PLE_DFI_ACTIVE; 136 break; 137 default: 138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 139 return -EINVAL; 140 } 141 142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 143 144 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 145 1, 1000, false, rtwdev, ctrl_reg); 146 if (ret) { 147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 148 ctrl_reg, ctrl_data); 149 return ret; 150 } 151 152 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 153 return 0; 154 } 155 156 static int dle_dfi_quota(struct rtw89_dev *rtwdev, 157 struct rtw89_mac_dle_dfi_quota *quota) 158 { 159 struct rtw89_mac_dle_dfi_ctrl ctrl; 160 int ret; 161 162 ctrl.type = quota->dle_type; 163 ctrl.target = DLE_DFI_TYPE_QUOTA; 164 ctrl.addr = quota->qtaid; 165 ret = dle_dfi_ctrl(rtwdev, &ctrl); 166 if (ret) { 167 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 168 return ret; 169 } 170 171 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 172 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 173 return 0; 174 } 175 176 static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 177 struct rtw89_mac_dle_dfi_qempty *qempty) 178 { 179 struct rtw89_mac_dle_dfi_ctrl ctrl; 180 u32 ret; 181 182 ctrl.type = qempty->dle_type; 183 ctrl.target = DLE_DFI_TYPE_QEMPTY; 184 ctrl.addr = qempty->grpsel; 185 ret = dle_dfi_ctrl(rtwdev, &ctrl); 186 if (ret) { 187 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 188 return ret; 189 } 190 191 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 192 return 0; 193 } 194 195 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 196 { 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 209 } 210 211 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 212 { 213 struct rtw89_mac_dle_dfi_qempty qempty; 214 struct rtw89_mac_dle_dfi_quota quota; 215 struct rtw89_mac_dle_dfi_ctrl ctrl; 216 u32 val, not_empty, i; 217 int ret; 218 219 qempty.dle_type = DLE_CTRL_TYPE_PLE; 220 qempty.grpsel = 0; 221 qempty.qempty = ~(u32)0; 222 ret = dle_dfi_qempty(rtwdev, &qempty); 223 if (ret) 224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 225 else 226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 227 228 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 229 if (!(not_empty & BIT(0))) 230 continue; 231 ctrl.type = DLE_CTRL_TYPE_PLE; 232 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 233 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 234 FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 235 ret = dle_dfi_ctrl(rtwdev, &ctrl); 236 if (ret) 237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 238 else 239 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 240 FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 241 ctrl.out_data)); 242 } 243 244 quota.dle_type = DLE_CTRL_TYPE_PLE; 245 quota.qtaid = 6; 246 ret = dle_dfi_quota(rtwdev, "a); 247 if (ret) 248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 249 else 250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 251 quota.rsv_pgnum, quota.use_pgnum); 252 253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 255 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 257 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 258 259 dump_err_status_dispatcher(rtwdev); 260 } 261 262 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 263 enum mac_ax_err_info err) 264 { 265 u32 dbg, event; 266 267 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 268 event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 269 270 switch (event) { 271 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 272 rtw89_info(rtwdev, "quota lost!\n"); 273 rtw89_mac_dump_qta_lost(rtwdev); 274 break; 275 default: 276 break; 277 } 278 } 279 280 static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 281 { 282 const struct rtw89_chip_info *chip = rtwdev->chip; 283 u32 dmac_err; 284 int i, ret; 285 286 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 287 if (ret) { 288 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 289 return; 290 } 291 292 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 293 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 294 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 295 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 296 297 if (dmac_err) { 298 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 299 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 300 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 301 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 302 if (chip->chip_id == RTL8852C) { 303 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 304 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 305 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 306 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 307 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 308 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 309 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 310 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 311 } 312 } 313 314 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 315 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 316 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 317 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 318 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 319 if (chip->chip_id == RTL8852C) 320 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 321 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 322 else 323 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 324 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 325 } 326 327 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 328 if (chip->chip_id == RTL8852C) { 329 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 330 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 331 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 332 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 333 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 334 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 335 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 337 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 339 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 341 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 343 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 344 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 345 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 346 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 347 348 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 349 B_AX_DBG_SEL0, 0x8B); 350 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 351 B_AX_DBG_SEL1, 0x8B); 352 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 353 B_AX_SEL_0XC0_MASK, 1); 354 for (i = 0; i < 0x10; i++) { 355 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 356 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 357 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 358 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 359 } 360 } else { 361 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 363 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 364 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 365 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 366 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 367 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 368 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 369 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 370 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 371 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 372 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 373 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 374 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 375 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 376 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 377 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 378 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 379 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 380 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 381 } 382 } 383 384 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 385 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 386 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 387 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 388 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 389 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 390 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 391 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 392 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 393 } 394 395 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 396 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 397 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 398 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 399 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 400 } 401 402 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 403 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 404 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 405 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 406 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 407 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 408 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 409 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 410 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 411 } 412 413 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 414 if (chip->chip_id == RTL8852C) { 415 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 416 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 417 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 419 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 421 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 423 } else { 424 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 425 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 426 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 427 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 428 } 429 } 430 431 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 432 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 433 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 434 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 435 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 436 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 437 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 438 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 439 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 440 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 441 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 442 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 443 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 444 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 445 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 446 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 447 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 448 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 449 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 450 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 451 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 452 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 453 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 454 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 455 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 456 if (chip->chip_id == RTL8852C) { 457 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 458 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 459 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 460 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 461 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 462 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 463 } else { 464 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 465 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 466 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 468 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 470 } 471 } 472 473 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 474 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 475 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 476 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 477 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 478 } 479 480 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 481 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 482 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 483 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 484 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 485 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 486 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 487 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 489 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 491 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 492 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 493 } 494 495 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 496 if (chip->chip_id == RTL8852C) { 497 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 499 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 501 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 503 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 505 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 507 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 509 } else { 510 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 511 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 512 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 513 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 514 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 515 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 516 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 517 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 518 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 519 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 520 } 521 } 522 523 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 524 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 525 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 526 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 527 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 528 } 529 } 530 531 static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev, 532 u8 band) 533 { 534 const struct rtw89_chip_info *chip = rtwdev->chip; 535 u32 offset = 0; 536 u32 cmac_err; 537 int ret; 538 539 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 540 if (ret) { 541 if (band) 542 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 543 else 544 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 545 return; 546 } 547 548 if (band) 549 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 550 551 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 552 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 553 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 554 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 555 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 556 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 557 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 558 559 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 560 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 561 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 562 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 563 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 564 } 565 566 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 567 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 568 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 569 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 570 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 571 } 572 573 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 574 if (chip->chip_id == RTL8852C) { 575 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 576 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 577 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 578 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 579 } else { 580 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 581 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 582 } 583 } 584 585 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 586 if (chip->chip_id == RTL8852C) { 587 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 588 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 589 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 590 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 591 } else { 592 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 593 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 594 } 595 } 596 597 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 598 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 599 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 600 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 601 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 602 } 603 604 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 605 if (chip->chip_id == RTL8852C) { 606 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 607 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 608 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 609 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 610 } else { 611 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 612 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 613 } 614 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 615 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 616 } 617 618 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 619 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 620 } 621 622 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 623 enum mac_ax_err_info err) 624 { 625 if (err != MAC_AX_ERR_L1_ERR_DMAC && 626 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 627 err != MAC_AX_ERR_L0_ERR_CMAC0 && 628 err != MAC_AX_ERR_L0_ERR_CMAC1 && 629 err != MAC_AX_ERR_RXI300) 630 return; 631 632 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 633 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 634 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 635 636 rtw89_mac_dump_dmac_err_status(rtwdev); 637 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0); 638 if (rtwdev->dbcc_en) 639 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1); 640 641 rtwdev->hci.ops->dump_err_status(rtwdev); 642 643 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 644 rtw89_mac_dump_l0_to_l1(rtwdev, err); 645 646 rtw89_info(rtwdev, "<---\n"); 647 } 648 649 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 650 { 651 struct rtw89_ser *ser = &rtwdev->ser; 652 u32 dmac_err, imr, isr; 653 int ret; 654 655 if (rtwdev->chip->chip_id == RTL8852C) { 656 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 657 if (ret) 658 return true; 659 660 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 661 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 662 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 663 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 664 665 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 666 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 667 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 668 return true; 669 } 670 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 671 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 672 return true; 673 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 674 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 675 return true; 676 } 677 } 678 679 return false; 680 } 681 682 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 683 { 684 u32 err, err_scnr; 685 int ret; 686 687 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 688 false, rtwdev, R_AX_HALT_C2H_CTRL); 689 if (ret) { 690 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 691 return ret; 692 } 693 694 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 695 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 696 697 err_scnr = RTW89_ERROR_SCENARIO(err); 698 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 699 err = MAC_AX_ERR_CPU_EXCEPTION; 700 else if (err_scnr == RTW89_WCPU_ASSERTION) 701 err = MAC_AX_ERR_ASSERTION; 702 else if (err_scnr == RTW89_RXI300_ERROR) 703 err = MAC_AX_ERR_RXI300; 704 705 if (rtw89_mac_suppress_log(rtwdev, err)) 706 return err; 707 708 rtw89_fw_st_dbg_dump(rtwdev); 709 rtw89_mac_dump_err_status(rtwdev, err); 710 711 return err; 712 } 713 EXPORT_SYMBOL(rtw89_mac_get_err_status); 714 715 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 716 { 717 struct rtw89_ser *ser = &rtwdev->ser; 718 u32 halt; 719 int ret = 0; 720 721 if (err > MAC_AX_SET_ERR_MAX) { 722 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 723 return -EINVAL; 724 } 725 726 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 727 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 728 if (ret) { 729 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 730 return -EFAULT; 731 } 732 733 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 734 735 if (ser->prehandle_l1 && 736 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 737 return 0; 738 739 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 740 741 return 0; 742 } 743 EXPORT_SYMBOL(rtw89_mac_set_err_status); 744 745 static int hfc_reset_param(struct rtw89_dev *rtwdev) 746 { 747 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 748 struct rtw89_hfc_param_ini param_ini = {NULL}; 749 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 750 751 switch (rtwdev->hci.type) { 752 case RTW89_HCI_TYPE_PCIE: 753 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 754 param->en = 0; 755 break; 756 default: 757 return -EINVAL; 758 } 759 760 if (param_ini.pub_cfg) 761 param->pub_cfg = *param_ini.pub_cfg; 762 763 if (param_ini.prec_cfg) 764 param->prec_cfg = *param_ini.prec_cfg; 765 766 if (param_ini.ch_cfg) 767 param->ch_cfg = param_ini.ch_cfg; 768 769 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 770 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 771 param->mode = param_ini.mode; 772 773 return 0; 774 } 775 776 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 777 { 778 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 779 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 780 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 781 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 782 783 if (ch >= RTW89_DMA_CH_NUM) 784 return -EINVAL; 785 786 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 787 ch_cfg[ch].max > pub_cfg->pub_max) 788 return -EINVAL; 789 if (ch_cfg[ch].grp >= grp_num) 790 return -EINVAL; 791 792 return 0; 793 } 794 795 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 796 { 797 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 798 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 799 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 800 801 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 802 if (rtwdev->chip->chip_id == RTL8852A) 803 return 0; 804 else 805 return -EFAULT; 806 } 807 808 return 0; 809 } 810 811 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 812 { 813 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 814 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 815 816 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 817 return -EFAULT; 818 819 return 0; 820 } 821 822 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 823 { 824 const struct rtw89_chip_info *chip = rtwdev->chip; 825 const struct rtw89_page_regs *regs = chip->page_regs; 826 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 827 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 828 int ret = 0; 829 u32 val = 0; 830 831 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 832 if (ret) 833 return ret; 834 835 ret = hfc_ch_cfg_chk(rtwdev, ch); 836 if (ret) 837 return ret; 838 839 if (ch > RTW89_DMA_B1HI) 840 return -EINVAL; 841 842 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 843 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 844 (cfg[ch].grp ? B_AX_GRP : 0); 845 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 846 847 return 0; 848 } 849 850 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 851 { 852 const struct rtw89_chip_info *chip = rtwdev->chip; 853 const struct rtw89_page_regs *regs = chip->page_regs; 854 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 855 struct rtw89_hfc_ch_info *info = param->ch_info; 856 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 857 u32 val; 858 u32 ret; 859 860 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 861 if (ret) 862 return ret; 863 864 if (ch > RTW89_DMA_H2C) 865 return -EINVAL; 866 867 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 868 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 869 if (ch < RTW89_DMA_H2C) 870 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 871 else 872 info[ch].used = cfg[ch].min - info[ch].aval; 873 874 return 0; 875 } 876 877 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 878 { 879 const struct rtw89_chip_info *chip = rtwdev->chip; 880 const struct rtw89_page_regs *regs = chip->page_regs; 881 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 882 u32 val; 883 int ret; 884 885 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 886 if (ret) 887 return ret; 888 889 ret = hfc_pub_cfg_chk(rtwdev); 890 if (ret) 891 return ret; 892 893 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 894 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 895 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 896 897 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 898 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 899 900 return 0; 901 } 902 903 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 904 { 905 const struct rtw89_chip_info *chip = rtwdev->chip; 906 const struct rtw89_page_regs *regs = chip->page_regs; 907 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 908 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 909 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 910 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 911 u32 val; 912 int ret; 913 914 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 915 if (ret) 916 return ret; 917 918 val = rtw89_read32(rtwdev, regs->pub_page_info1); 919 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 920 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 921 val = rtw89_read32(rtwdev, regs->pub_page_info3); 922 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 923 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 924 info->pub_aval = 925 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 926 B_AX_PUB_AVAL_PG_MASK); 927 info->wp_aval = 928 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 929 B_AX_WP_AVAL_PG_MASK); 930 931 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 932 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 933 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 934 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 935 prec_cfg->ch011_full_cond = 936 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 937 prec_cfg->h2c_full_cond = 938 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 939 prec_cfg->wp_ch07_full_cond = 940 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 941 prec_cfg->wp_ch811_full_cond = 942 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 943 944 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 945 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 946 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 947 948 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 949 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 950 951 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 952 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 953 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 954 955 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 956 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 957 958 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 959 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 960 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 961 962 ret = hfc_pub_info_chk(rtwdev); 963 if (param->en && ret) 964 return ret; 965 966 return 0; 967 } 968 969 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 970 { 971 const struct rtw89_chip_info *chip = rtwdev->chip; 972 const struct rtw89_page_regs *regs = chip->page_regs; 973 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 974 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 975 u32 val; 976 977 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 978 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 979 980 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 981 B_AX_HCI_FC_CH12_FULL_COND_MASK, 982 prec_cfg->h2c_full_cond); 983 } 984 985 static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 986 { 987 const struct rtw89_chip_info *chip = rtwdev->chip; 988 const struct rtw89_page_regs *regs = chip->page_regs; 989 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 990 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 991 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 992 u32 val; 993 994 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 995 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 996 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 997 998 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 999 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1000 1001 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1002 B_AX_PREC_PAGE_WP_CH07_MASK) | 1003 u32_encode_bits(prec_cfg->wp_ch811_prec, 1004 B_AX_PREC_PAGE_WP_CH811_MASK); 1005 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1006 1007 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1008 param->mode, B_AX_HCI_FC_MODE_MASK); 1009 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1010 B_AX_HCI_FC_WD_FULL_COND_MASK); 1011 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1012 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1013 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1014 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1015 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1016 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1017 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1018 } 1019 1020 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1021 { 1022 const struct rtw89_chip_info *chip = rtwdev->chip; 1023 const struct rtw89_page_regs *regs = chip->page_regs; 1024 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1025 u32 val; 1026 1027 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1028 param->en = en; 1029 param->h2c_en = h2c_en; 1030 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1031 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1032 (val & ~B_AX_HCI_FC_CH12_EN); 1033 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1034 } 1035 1036 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1037 { 1038 const struct rtw89_chip_info *chip = rtwdev->chip; 1039 u32 dma_ch_mask = chip->dma_ch_mask; 1040 u8 ch; 1041 u32 ret = 0; 1042 1043 if (reset) 1044 ret = hfc_reset_param(rtwdev); 1045 if (ret) 1046 return ret; 1047 1048 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1049 if (ret) 1050 return ret; 1051 1052 hfc_func_en(rtwdev, false, false); 1053 1054 if (!en && h2c_en) { 1055 hfc_h2c_cfg(rtwdev); 1056 hfc_func_en(rtwdev, en, h2c_en); 1057 return ret; 1058 } 1059 1060 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1061 if (dma_ch_mask & BIT(ch)) 1062 continue; 1063 ret = hfc_ch_ctrl(rtwdev, ch); 1064 if (ret) 1065 return ret; 1066 } 1067 1068 ret = hfc_pub_ctrl(rtwdev); 1069 if (ret) 1070 return ret; 1071 1072 hfc_mix_cfg(rtwdev); 1073 if (en || h2c_en) { 1074 hfc_func_en(rtwdev, en, h2c_en); 1075 udelay(10); 1076 } 1077 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1078 if (dma_ch_mask & BIT(ch)) 1079 continue; 1080 ret = hfc_upd_ch_info(rtwdev, ch); 1081 if (ret) 1082 return ret; 1083 } 1084 ret = hfc_upd_mix_info(rtwdev); 1085 1086 return ret; 1087 } 1088 1089 #define PWR_POLL_CNT 2000 1090 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1091 const struct rtw89_pwr_cfg *cfg) 1092 { 1093 u8 val = 0; 1094 int ret; 1095 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1096 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1097 1098 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1099 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1100 1101 if (!ret) 1102 return 0; 1103 1104 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1105 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1106 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1107 1108 return -EBUSY; 1109 } 1110 1111 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1112 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1113 { 1114 const struct rtw89_pwr_cfg *cur_cfg; 1115 u32 addr; 1116 u8 val; 1117 1118 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1119 if (!(cur_cfg->intf_msk & intf_msk) || 1120 !(cur_cfg->cv_msk & cv_msk)) 1121 continue; 1122 1123 switch (cur_cfg->cmd) { 1124 case PWR_CMD_WRITE: 1125 addr = cur_cfg->addr; 1126 1127 if (cur_cfg->base == PWR_BASE_SDIO) 1128 addr |= SDIO_LOCAL_BASE_ADDR; 1129 1130 val = rtw89_read8(rtwdev, addr); 1131 val &= ~(cur_cfg->msk); 1132 val |= (cur_cfg->val & cur_cfg->msk); 1133 1134 rtw89_write8(rtwdev, addr, val); 1135 break; 1136 case PWR_CMD_POLL: 1137 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1138 return -EBUSY; 1139 break; 1140 case PWR_CMD_DELAY: 1141 if (cur_cfg->val == PWR_DELAY_US) 1142 udelay(cur_cfg->addr); 1143 else 1144 fsleep(cur_cfg->addr * 1000); 1145 break; 1146 default: 1147 return -EINVAL; 1148 } 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1155 const struct rtw89_pwr_cfg * const *cfg_seq) 1156 { 1157 int ret; 1158 1159 for (; *cfg_seq; cfg_seq++) { 1160 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1161 PWR_INTF_MSK_PCIE, *cfg_seq); 1162 if (ret) 1163 return -EBUSY; 1164 } 1165 1166 return 0; 1167 } 1168 1169 static enum rtw89_rpwm_req_pwr_state 1170 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1171 { 1172 enum rtw89_rpwm_req_pwr_state state; 1173 1174 switch (rtwdev->ps_mode) { 1175 case RTW89_PS_MODE_RFOFF: 1176 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1177 break; 1178 case RTW89_PS_MODE_CLK_GATED: 1179 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1180 break; 1181 case RTW89_PS_MODE_PWR_GATED: 1182 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1183 break; 1184 default: 1185 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1186 break; 1187 } 1188 return state; 1189 } 1190 1191 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1192 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1193 bool notify_wake) 1194 { 1195 u16 request; 1196 1197 spin_lock_bh(&rtwdev->rpwm_lock); 1198 1199 request = rtw89_read16(rtwdev, R_AX_RPWM); 1200 request ^= request | PS_RPWM_TOGGLE; 1201 request |= req_pwr_state; 1202 1203 if (notify_wake) { 1204 request |= PS_RPWM_NOTIFY_WAKE; 1205 } else { 1206 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1207 RPWM_SEQ_NUM_MAX; 1208 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1209 rtwdev->mac.rpwm_seq_num); 1210 1211 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1212 request |= PS_RPWM_ACK; 1213 } 1214 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1215 1216 spin_unlock_bh(&rtwdev->rpwm_lock); 1217 } 1218 1219 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1220 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1221 { 1222 bool request_deep_mode; 1223 bool in_deep_mode; 1224 u8 rpwm_req_num; 1225 u8 cpwm_rsp_seq; 1226 u8 cpwm_seq; 1227 u8 cpwm_status; 1228 1229 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1230 request_deep_mode = true; 1231 else 1232 request_deep_mode = false; 1233 1234 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1235 in_deep_mode = true; 1236 else 1237 in_deep_mode = false; 1238 1239 if (request_deep_mode != in_deep_mode) 1240 return -EPERM; 1241 1242 if (request_deep_mode) 1243 return 0; 1244 1245 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1246 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1247 PS_CPWM_RSP_SEQ_NUM); 1248 1249 if (rpwm_req_num != cpwm_rsp_seq) 1250 return -EPERM; 1251 1252 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1253 CPWM_SEQ_NUM_MAX; 1254 1255 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1256 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1257 return -EPERM; 1258 1259 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1260 if (cpwm_status != req_pwr_state) 1261 return -EPERM; 1262 1263 return 0; 1264 } 1265 1266 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1267 { 1268 enum rtw89_rpwm_req_pwr_state state; 1269 unsigned long delay = enter ? 10 : 150; 1270 int ret; 1271 int i; 1272 1273 if (enter) 1274 state = rtw89_mac_get_req_pwr_state(rtwdev); 1275 else 1276 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1277 1278 for (i = 0; i < RPWM_TRY_CNT; i++) { 1279 rtw89_mac_send_rpwm(rtwdev, state, false); 1280 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1281 !ret, delay, 15000, false, 1282 rtwdev, state); 1283 if (!ret) 1284 break; 1285 1286 if (i == RPWM_TRY_CNT - 1) 1287 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1288 enter ? "entering" : "leaving"); 1289 else 1290 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1291 "%d time firmware failed to ack for %s ps mode\n", 1292 i + 1, enter ? "entering" : "leaving"); 1293 } 1294 } 1295 1296 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1297 { 1298 enum rtw89_rpwm_req_pwr_state state; 1299 1300 state = rtw89_mac_get_req_pwr_state(rtwdev); 1301 rtw89_mac_send_rpwm(rtwdev, state, true); 1302 } 1303 1304 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1305 { 1306 #define PWR_ACT 1 1307 const struct rtw89_chip_info *chip = rtwdev->chip; 1308 const struct rtw89_pwr_cfg * const *cfg_seq; 1309 int (*cfg_func)(struct rtw89_dev *rtwdev); 1310 int ret; 1311 u8 val; 1312 1313 if (on) { 1314 cfg_seq = chip->pwr_on_seq; 1315 cfg_func = chip->ops->pwr_on_func; 1316 } else { 1317 cfg_seq = chip->pwr_off_seq; 1318 cfg_func = chip->ops->pwr_off_func; 1319 } 1320 1321 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1322 __rtw89_leave_ps_mode(rtwdev); 1323 1324 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1325 if (on && val == PWR_ACT) { 1326 rtw89_err(rtwdev, "MAC has already powered on\n"); 1327 return -EBUSY; 1328 } 1329 1330 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1331 if (ret) 1332 return ret; 1333 1334 if (on) { 1335 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1336 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1337 } else { 1338 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1339 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1340 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1341 rtw89_set_entity_state(rtwdev, false); 1342 } 1343 1344 return 0; 1345 #undef PWR_ACT 1346 } 1347 1348 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1349 { 1350 rtw89_mac_power_switch(rtwdev, false); 1351 } 1352 1353 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1354 { 1355 u32 func_en = 0; 1356 u32 ck_en = 0; 1357 u32 c1pc_en = 0; 1358 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1359 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1360 1361 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1362 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1363 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1364 B_AX_CMAC_CRPRT; 1365 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1366 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1367 B_AX_RMAC_CKEN; 1368 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1369 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1370 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1371 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1372 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1373 1374 if (en) { 1375 if (mac_idx == RTW89_MAC_1) { 1376 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1377 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1378 B_AX_R_SYM_ISO_CMAC12PP); 1379 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1380 B_AX_CMAC1_FEN); 1381 } 1382 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1383 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1384 } else { 1385 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1386 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1387 if (mac_idx == RTW89_MAC_1) { 1388 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1389 B_AX_CMAC1_FEN); 1390 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1391 B_AX_R_SYM_ISO_CMAC12PP); 1392 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1393 } 1394 } 1395 1396 return 0; 1397 } 1398 1399 static int dmac_func_en(struct rtw89_dev *rtwdev) 1400 { 1401 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1402 u32 val32; 1403 1404 if (chip_id == RTL8852C) 1405 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1406 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1407 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1408 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1409 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1410 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1411 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1412 else 1413 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1414 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1415 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1416 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1417 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1418 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1419 B_AX_DMAC_CRPRT); 1420 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1421 1422 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1423 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1424 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1425 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1426 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1427 1428 return 0; 1429 } 1430 1431 static int chip_func_en(struct rtw89_dev *rtwdev) 1432 { 1433 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1434 1435 if (chip_id == RTL8852A || chip_id == RTL8852B) 1436 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1437 B_AX_OCP_L1_MASK); 1438 1439 return 0; 1440 } 1441 1442 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1443 { 1444 int ret; 1445 1446 ret = dmac_func_en(rtwdev); 1447 if (ret) 1448 return ret; 1449 1450 ret = cmac_func_en(rtwdev, 0, true); 1451 if (ret) 1452 return ret; 1453 1454 ret = chip_func_en(rtwdev); 1455 if (ret) 1456 return ret; 1457 1458 return ret; 1459 } 1460 1461 const struct rtw89_mac_size_set rtw89_mac_size = { 1462 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1463 /* PCIE 64 */ 1464 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1465 /* DLFW */ 1466 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1467 /* PCIE 64 */ 1468 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1469 /* 8852B PCIE SCC */ 1470 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1471 /* DLFW */ 1472 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1473 /* 8852C DLFW */ 1474 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1475 /* 8852C PCIE SCC */ 1476 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1477 /* PCIE */ 1478 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1479 /* DLFW */ 1480 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1481 /* PCIE 64 */ 1482 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1483 /* DLFW */ 1484 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1485 /* 8852C DLFW */ 1486 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1487 /* 8852C PCIE SCC */ 1488 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1489 /* PCIE 64 */ 1490 .wde_qt0 = {3792, 196, 0, 107,}, 1491 /* DLFW */ 1492 .wde_qt4 = {0, 0, 0, 0,}, 1493 /* PCIE 64 */ 1494 .wde_qt6 = {448, 48, 0, 16,}, 1495 /* 8852B PCIE SCC */ 1496 .wde_qt7 = {446, 48, 0, 16,}, 1497 /* 8852C DLFW */ 1498 .wde_qt17 = {0, 0, 0, 0,}, 1499 /* 8852C PCIE SCC */ 1500 .wde_qt18 = {3228, 60, 0, 40,}, 1501 /* PCIE SCC */ 1502 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1503 /* PCIE SCC */ 1504 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1505 /* DLFW */ 1506 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1507 /* PCIE 64 */ 1508 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1509 /* DLFW 52C */ 1510 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1511 /* DLFW 52C */ 1512 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1513 /* 8852C PCIE SCC */ 1514 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1515 /* 8852C PCIE SCC */ 1516 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1517 /* PCIE 64 */ 1518 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1519 /* 8852A PCIE WOW */ 1520 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1521 /* 8852B PCIE WOW */ 1522 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1523 /* 8851B PCIE WOW */ 1524 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1525 }; 1526 EXPORT_SYMBOL(rtw89_mac_size); 1527 1528 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1529 enum rtw89_qta_mode mode) 1530 { 1531 struct rtw89_mac_info *mac = &rtwdev->mac; 1532 const struct rtw89_dle_mem *cfg; 1533 1534 cfg = &rtwdev->chip->dle_mem[mode]; 1535 if (!cfg) 1536 return NULL; 1537 1538 if (cfg->mode != mode) { 1539 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1540 return NULL; 1541 } 1542 1543 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1544 mac->dle_info.qta_mode = mode; 1545 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1546 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1547 1548 return cfg; 1549 } 1550 1551 static bool mac_is_txq_empty(struct rtw89_dev *rtwdev) 1552 { 1553 struct rtw89_mac_dle_dfi_qempty qempty; 1554 u32 qnum, qtmp, val32, msk32; 1555 int i, j, ret; 1556 1557 qnum = rtwdev->chip->wde_qempty_acq_num; 1558 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1559 1560 for (i = 0; i < qnum; i++) { 1561 qempty.grpsel = i; 1562 ret = dle_dfi_qempty(rtwdev, &qempty); 1563 if (ret) { 1564 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1565 return false; 1566 } 1567 qtmp = qempty.qempty; 1568 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1569 val32 = FIELD_GET(QEMP_ACQ_GRP_QSEL_MASK, qtmp); 1570 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1571 return false; 1572 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1573 } 1574 } 1575 1576 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel; 1577 ret = dle_dfi_qempty(rtwdev, &qempty); 1578 if (ret) { 1579 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1580 return false; 1581 } 1582 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1583 if ((qempty.qempty & msk32) != msk32) 1584 return false; 1585 1586 if (rtwdev->dbcc_en) { 1587 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1588 if ((qempty.qempty & msk32) != msk32) 1589 return false; 1590 } 1591 1592 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1593 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1594 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1595 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1596 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1597 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1598 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1599 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1600 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1601 1602 return (val32 & msk32) == msk32; 1603 } 1604 1605 static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1606 const struct rtw89_dle_size *ple) 1607 { 1608 return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1609 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1610 } 1611 1612 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1613 enum rtw89_qta_mode mode) 1614 { 1615 u32 size = rtwdev->chip->fifo_size; 1616 1617 if (mode == RTW89_QTA_SCC) 1618 size -= rtwdev->chip->dle_scc_rsvd_size; 1619 1620 return size; 1621 } 1622 1623 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1624 { 1625 if (enable) 1626 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1627 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1628 else 1629 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1630 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1631 } 1632 1633 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1634 { 1635 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1636 1637 if (enable) { 1638 if (rtwdev->chip->chip_id == RTL8851B) 1639 val |= B_AX_AXIDMA_CLK_EN; 1640 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1641 } else { 1642 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1643 } 1644 } 1645 1646 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1647 { 1648 const struct rtw89_dle_size *size_cfg; 1649 u32 val; 1650 u8 bound = 0; 1651 1652 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1653 size_cfg = cfg->wde_size; 1654 1655 switch (size_cfg->pge_size) { 1656 default: 1657 case RTW89_WDE_PG_64: 1658 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1659 B_AX_WDE_PAGE_SEL_MASK); 1660 break; 1661 case RTW89_WDE_PG_128: 1662 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1663 B_AX_WDE_PAGE_SEL_MASK); 1664 break; 1665 case RTW89_WDE_PG_256: 1666 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1667 return -EINVAL; 1668 } 1669 1670 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1671 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1672 B_AX_WDE_FREE_PAGE_NUM_MASK); 1673 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1674 1675 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1676 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1677 * size_cfg->pge_size / DLE_BOUND_UNIT; 1678 size_cfg = cfg->ple_size; 1679 1680 switch (size_cfg->pge_size) { 1681 default: 1682 case RTW89_PLE_PG_64: 1683 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1684 return -EINVAL; 1685 case RTW89_PLE_PG_128: 1686 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1687 B_AX_PLE_PAGE_SEL_MASK); 1688 break; 1689 case RTW89_PLE_PG_256: 1690 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1691 B_AX_PLE_PAGE_SEL_MASK); 1692 break; 1693 } 1694 1695 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1696 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1697 B_AX_PLE_FREE_PAGE_NUM_MASK); 1698 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1699 1700 return 0; 1701 } 1702 1703 #define INVALID_QT_WCPU U16_MAX 1704 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1705 do { \ 1706 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1707 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1708 rtw89_write32(rtwdev, \ 1709 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1710 val); \ 1711 } while (0) 1712 #define SET_QUOTA(_x, _module, _idx) \ 1713 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1714 1715 static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1716 const struct rtw89_wde_quota *min_cfg, 1717 const struct rtw89_wde_quota *max_cfg, 1718 u16 ext_wde_min_qt_wcpu) 1719 { 1720 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1721 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1722 u32 val; 1723 1724 SET_QUOTA(hif, WDE, 0); 1725 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1726 SET_QUOTA(pkt_in, WDE, 3); 1727 SET_QUOTA(cpu_io, WDE, 4); 1728 } 1729 1730 static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1731 const struct rtw89_ple_quota *min_cfg, 1732 const struct rtw89_ple_quota *max_cfg) 1733 { 1734 u32 val; 1735 1736 SET_QUOTA(cma0_tx, PLE, 0); 1737 SET_QUOTA(cma1_tx, PLE, 1); 1738 SET_QUOTA(c2h, PLE, 2); 1739 SET_QUOTA(h2c, PLE, 3); 1740 SET_QUOTA(wcpu, PLE, 4); 1741 SET_QUOTA(mpdu_proc, PLE, 5); 1742 SET_QUOTA(cma0_dma, PLE, 6); 1743 SET_QUOTA(cma1_dma, PLE, 7); 1744 SET_QUOTA(bb_rpt, PLE, 8); 1745 SET_QUOTA(wd_rel, PLE, 9); 1746 SET_QUOTA(cpu_io, PLE, 10); 1747 if (rtwdev->chip->chip_id == RTL8852C) 1748 SET_QUOTA(tx_rpt, PLE, 11); 1749 } 1750 1751 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 1752 { 1753 const struct rtw89_ple_quota *min_cfg, *max_cfg; 1754 const struct rtw89_dle_mem *cfg; 1755 u32 val; 1756 1757 if (rtwdev->chip->chip_id == RTL8852C) 1758 return 0; 1759 1760 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 1761 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 1762 return -EINVAL; 1763 } 1764 1765 if (wow) 1766 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 1767 else 1768 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 1769 if (!cfg) { 1770 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1771 return -EINVAL; 1772 } 1773 1774 min_cfg = cfg->ple_min_qt; 1775 max_cfg = cfg->ple_max_qt; 1776 SET_QUOTA(cma0_dma, PLE, 6); 1777 SET_QUOTA(cma1_dma, PLE, 7); 1778 1779 return 0; 1780 } 1781 #undef SET_QUOTA 1782 1783 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 1784 { 1785 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 1786 1787 if (enable) 1788 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1789 else 1790 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1791 } 1792 1793 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1794 const struct rtw89_dle_mem *cfg, 1795 u16 ext_wde_min_qt_wcpu) 1796 { 1797 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1798 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1799 } 1800 1801 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1802 enum rtw89_qta_mode ext_mode) 1803 { 1804 const struct rtw89_dle_mem *cfg, *ext_cfg; 1805 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1806 int ret = 0; 1807 u32 ini; 1808 1809 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1810 if (ret) 1811 return ret; 1812 1813 cfg = get_dle_mem_cfg(rtwdev, mode); 1814 if (!cfg) { 1815 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1816 ret = -EINVAL; 1817 goto error; 1818 } 1819 1820 if (mode == RTW89_QTA_DLFW) { 1821 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1822 if (!ext_cfg) { 1823 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1824 ext_mode); 1825 ret = -EINVAL; 1826 goto error; 1827 } 1828 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1829 } 1830 1831 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 1832 dle_expected_used_size(rtwdev, mode)) { 1833 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1834 ret = -EINVAL; 1835 goto error; 1836 } 1837 1838 dle_func_en(rtwdev, false); 1839 dle_clk_en(rtwdev, true); 1840 1841 ret = dle_mix_cfg(rtwdev, cfg); 1842 if (ret) { 1843 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1844 goto error; 1845 } 1846 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1847 1848 dle_func_en(rtwdev, true); 1849 1850 ret = read_poll_timeout(rtw89_read32, ini, 1851 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1852 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1853 if (ret) { 1854 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1855 return ret; 1856 } 1857 1858 ret = read_poll_timeout(rtw89_read32, ini, 1859 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1860 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1861 if (ret) { 1862 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1863 return ret; 1864 } 1865 1866 return 0; 1867 error: 1868 dle_func_en(rtwdev, false); 1869 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1870 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1871 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1872 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1873 1874 return ret; 1875 } 1876 1877 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1878 enum rtw89_qta_mode mode) 1879 { 1880 u32 reg, max_preld_size, min_rsvd_size; 1881 1882 max_preld_size = (mac_idx == RTW89_MAC_0 ? 1883 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1884 reg = mac_idx == RTW89_MAC_0 ? 1885 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1886 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1887 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1888 1889 min_rsvd_size = PRELD_AMSDU_SIZE; 1890 reg = mac_idx == RTW89_MAC_0 ? 1891 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1892 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1893 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1894 1895 return 0; 1896 } 1897 1898 static bool is_qta_poh(struct rtw89_dev *rtwdev) 1899 { 1900 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1901 } 1902 1903 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1904 enum rtw89_qta_mode mode) 1905 { 1906 const struct rtw89_chip_info *chip = rtwdev->chip; 1907 1908 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1909 chip->chip_id == RTL8851B || !is_qta_poh(rtwdev)) 1910 return 0; 1911 1912 return preload_init_set(rtwdev, mac_idx, mode); 1913 } 1914 1915 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1916 { 1917 u32 msk32; 1918 u32 val32; 1919 1920 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1921 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1922 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1923 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1924 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1925 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1926 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1927 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1928 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1929 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1930 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1931 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1932 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1933 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1934 1935 if ((val32 & msk32) == msk32) 1936 return true; 1937 1938 return false; 1939 } 1940 1941 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 1942 { 1943 const struct rtw89_chip_info *chip = rtwdev->chip; 1944 1945 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1946 chip->chip_id == RTL8851B) 1947 return; 1948 1949 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 1950 SS2F_PATH_WLCPU); 1951 } 1952 1953 static int sta_sch_init(struct rtw89_dev *rtwdev) 1954 { 1955 u32 p_val; 1956 u8 val; 1957 int ret; 1958 1959 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1960 if (ret) 1961 return ret; 1962 1963 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1964 val |= B_AX_SS_EN; 1965 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1966 1967 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1968 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1969 if (ret) { 1970 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1971 return ret; 1972 } 1973 1974 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 1975 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 1976 1977 _patch_ss2f_path(rtwdev); 1978 1979 return 0; 1980 } 1981 1982 static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1983 { 1984 int ret; 1985 1986 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1987 if (ret) 1988 return ret; 1989 1990 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1991 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1992 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1993 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1994 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1995 1996 return 0; 1997 } 1998 1999 static int sec_eng_init(struct rtw89_dev *rtwdev) 2000 { 2001 const struct rtw89_chip_info *chip = rtwdev->chip; 2002 u32 val = 0; 2003 int ret; 2004 2005 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2006 if (ret) 2007 return ret; 2008 2009 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2010 /* init clock */ 2011 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2012 /* init TX encryption */ 2013 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2014 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2015 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2016 chip->chip_id == RTL8851B) 2017 val &= ~B_AX_TX_PARTIAL_MODE; 2018 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2019 2020 /* init MIC ICV append */ 2021 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2022 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2023 2024 /* option init */ 2025 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2026 2027 if (chip->chip_id == RTL8852C) 2028 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2029 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2030 2031 return 0; 2032 } 2033 2034 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2035 { 2036 int ret; 2037 2038 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2039 if (ret) { 2040 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2041 return ret; 2042 } 2043 2044 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2045 if (ret) { 2046 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2047 return ret; 2048 } 2049 2050 ret = hfc_init(rtwdev, true, true, true); 2051 if (ret) { 2052 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2053 return ret; 2054 } 2055 2056 ret = sta_sch_init(rtwdev); 2057 if (ret) { 2058 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2059 return ret; 2060 } 2061 2062 ret = mpdu_proc_init(rtwdev); 2063 if (ret) { 2064 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2065 return ret; 2066 } 2067 2068 ret = sec_eng_init(rtwdev); 2069 if (ret) { 2070 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2071 return ret; 2072 } 2073 2074 return ret; 2075 } 2076 2077 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2078 { 2079 u32 val, reg; 2080 u16 p_val; 2081 int ret; 2082 2083 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2084 if (ret) 2085 return ret; 2086 2087 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2088 2089 val = rtw89_read32(rtwdev, reg); 2090 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2091 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2092 rtw89_write32(rtwdev, reg, val); 2093 2094 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2095 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2096 if (ret) { 2097 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2098 return ret; 2099 } 2100 2101 return 0; 2102 } 2103 2104 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2105 { 2106 u32 ret; 2107 u32 reg; 2108 u32 val; 2109 2110 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2111 if (ret) 2112 return ret; 2113 2114 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2115 if (rtwdev->chip->chip_id == RTL8852C) 2116 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2117 SIFS_MACTXEN_T1_V1); 2118 else 2119 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2120 SIFS_MACTXEN_T1); 2121 2122 if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) { 2123 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2124 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2125 } 2126 2127 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2128 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2129 2130 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2131 if (rtwdev->chip->chip_id == RTL8852C) { 2132 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2133 B_AX_TX_PARTIAL_MODE); 2134 if (!val) 2135 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2136 SCH_PREBKF_24US); 2137 } else { 2138 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2139 SCH_PREBKF_24US); 2140 } 2141 2142 return 0; 2143 } 2144 2145 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 2146 enum rtw89_machdr_frame_type type, 2147 enum rtw89_mac_fwd_target fwd_target, 2148 u8 mac_idx) 2149 { 2150 u32 reg; 2151 u32 val; 2152 2153 switch (fwd_target) { 2154 case RTW89_FWD_DONT_CARE: 2155 val = RX_FLTR_FRAME_DROP; 2156 break; 2157 case RTW89_FWD_TO_HOST: 2158 val = RX_FLTR_FRAME_TO_HOST; 2159 break; 2160 case RTW89_FWD_TO_WLAN_CPU: 2161 val = RX_FLTR_FRAME_TO_WLCPU; 2162 break; 2163 default: 2164 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2165 return -EINVAL; 2166 } 2167 2168 switch (type) { 2169 case RTW89_MGNT: 2170 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2171 break; 2172 case RTW89_CTRL: 2173 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2174 break; 2175 case RTW89_DATA: 2176 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2177 break; 2178 default: 2179 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2180 return -EINVAL; 2181 } 2182 rtw89_write32(rtwdev, reg, val); 2183 2184 return 0; 2185 } 2186 2187 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2188 { 2189 int ret, i; 2190 u32 mac_ftlr, plcp_ftlr; 2191 2192 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2193 if (ret) 2194 return ret; 2195 2196 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2197 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 2198 mac_idx); 2199 if (ret) 2200 return ret; 2201 } 2202 mac_ftlr = rtwdev->hal.rx_fltr; 2203 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2204 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2205 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2206 B_AX_HE_SIGB_CRC_CHK; 2207 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2208 mac_ftlr); 2209 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2210 plcp_ftlr); 2211 2212 return 0; 2213 } 2214 2215 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2216 { 2217 u32 reg, val32; 2218 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2219 2220 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2221 B_AX_RSP_CHK_BASIC_NAV; 2222 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2223 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2224 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2225 2226 switch (rtwdev->chip->chip_id) { 2227 case RTL8852A: 2228 case RTL8852B: 2229 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2230 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2231 rtw89_write32(rtwdev, reg, val32); 2232 2233 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2234 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2235 rtw89_write32(rtwdev, reg, val32); 2236 break; 2237 default: 2238 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2239 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2240 rtw89_write32(rtwdev, reg, val32); 2241 2242 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2243 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2244 rtw89_write32(rtwdev, reg, val32); 2245 break; 2246 } 2247 } 2248 2249 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2250 { 2251 u32 val, reg; 2252 int ret; 2253 2254 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2255 if (ret) 2256 return ret; 2257 2258 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2259 val = rtw89_read32(rtwdev, reg); 2260 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2261 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2262 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2263 B_AX_CTN_CHK_INTRA_NAV | 2264 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2265 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2266 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2267 B_AX_CTN_CHK_CCA_P20); 2268 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2269 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2270 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2271 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2272 B_AX_SIFS_CHK_EDCCA); 2273 2274 rtw89_write32(rtwdev, reg, val); 2275 2276 _patch_dis_resp_chk(rtwdev, mac_idx); 2277 2278 return 0; 2279 } 2280 2281 static int nav_ctrl_init(struct rtw89_dev *rtwdev) 2282 { 2283 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2284 B_AX_WMAC_TF_UP_NAV_EN | 2285 B_AX_WMAC_NAV_UPPER_EN); 2286 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2287 2288 return 0; 2289 } 2290 2291 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2292 { 2293 u32 reg; 2294 int ret; 2295 2296 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2297 if (ret) 2298 return ret; 2299 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2300 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2301 2302 return 0; 2303 } 2304 2305 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2306 { 2307 u32 reg; 2308 int ret; 2309 2310 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2311 if (ret) 2312 return ret; 2313 2314 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2315 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2316 2317 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2318 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2319 2320 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2321 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2322 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2323 2324 return 0; 2325 } 2326 2327 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2328 { 2329 const struct rtw89_chip_info *chip = rtwdev->chip; 2330 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2331 u32 reg, val, sifs; 2332 int ret; 2333 2334 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2335 if (ret) 2336 return ret; 2337 2338 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2339 val = rtw89_read32(rtwdev, reg); 2340 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2341 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2342 2343 switch (rtwdev->chip->chip_id) { 2344 case RTL8852A: 2345 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2346 break; 2347 case RTL8852B: 2348 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2349 break; 2350 default: 2351 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2352 break; 2353 } 2354 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2355 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2356 rtw89_write32(rtwdev, reg, val); 2357 2358 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2359 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2360 2361 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2362 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2363 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2364 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2365 2366 return 0; 2367 } 2368 2369 static void rst_bacam(struct rtw89_dev *rtwdev) 2370 { 2371 u32 val32; 2372 int ret; 2373 2374 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2375 S_AX_BACAM_RST_ALL); 2376 2377 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2378 1, 1000, false, 2379 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2380 if (ret) 2381 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2382 } 2383 2384 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2385 { 2386 #define TRXCFG_RMAC_CCA_TO 32 2387 #define TRXCFG_RMAC_DATA_TO 15 2388 #define RX_MAX_LEN_UNIT 512 2389 #define PLD_RLS_MAX_PG 127 2390 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2391 int ret; 2392 u32 reg, rx_max_len, rx_qta; 2393 u16 val; 2394 2395 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2396 if (ret) 2397 return ret; 2398 2399 if (mac_idx == RTW89_MAC_0) 2400 rst_bacam(rtwdev); 2401 2402 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2403 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2404 2405 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2406 val = rtw89_read16(rtwdev, reg); 2407 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2408 B_AX_RX_DLK_DATA_TIME_MASK); 2409 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2410 B_AX_RX_DLK_CCA_TIME_MASK); 2411 rtw89_write16(rtwdev, reg, val); 2412 2413 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2414 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2415 2416 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2417 if (mac_idx == RTW89_MAC_0) 2418 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2419 else 2420 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2421 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2422 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2423 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2424 rx_max_len /= RX_MAX_LEN_UNIT; 2425 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2426 2427 if (rtwdev->chip->chip_id == RTL8852A && 2428 rtwdev->hal.cv == CHIP_CBV) { 2429 rtw89_write16_mask(rtwdev, 2430 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2431 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2432 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2433 BIT(12)); 2434 } 2435 2436 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2437 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2438 2439 return ret; 2440 } 2441 2442 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2443 { 2444 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2445 u32 val, reg; 2446 int ret; 2447 2448 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2449 if (ret) 2450 return ret; 2451 2452 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2453 val = rtw89_read32(rtwdev, reg); 2454 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2455 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2456 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2457 rtw89_write32(rtwdev, reg, val); 2458 2459 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2460 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2461 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2462 } 2463 2464 return 0; 2465 } 2466 2467 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2468 { 2469 const struct rtw89_dle_mem *cfg; 2470 2471 cfg = get_dle_mem_cfg(rtwdev, mode); 2472 if (!cfg) { 2473 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2474 return false; 2475 } 2476 2477 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2478 } 2479 2480 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2481 { 2482 u32 val, reg; 2483 int ret; 2484 2485 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2486 if (ret) 2487 return ret; 2488 2489 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2490 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2491 val = rtw89_read32(rtwdev, reg); 2492 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2493 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2494 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2495 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2496 val |= B_AX_HW_CTS2SELF_EN; 2497 rtw89_write32(rtwdev, reg, val); 2498 2499 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2500 val = rtw89_read32(rtwdev, reg); 2501 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2502 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2503 rtw89_write32(rtwdev, reg, val); 2504 } 2505 2506 if (mac_idx == RTW89_MAC_0) { 2507 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2508 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2509 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2510 B_AX_PTCL_TRIGGER_SS_EN_0 | 2511 B_AX_PTCL_TRIGGER_SS_EN_1 | 2512 B_AX_PTCL_TRIGGER_SS_EN_UL); 2513 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2514 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2515 } else if (mac_idx == RTW89_MAC_1) { 2516 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2517 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2518 } 2519 2520 return 0; 2521 } 2522 2523 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2524 { 2525 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2526 u32 reg; 2527 int ret; 2528 2529 if (chip_id != RTL8852B) 2530 return 0; 2531 2532 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2533 if (ret) 2534 return ret; 2535 2536 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2537 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2538 2539 return 0; 2540 } 2541 2542 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2543 { 2544 int ret; 2545 2546 ret = scheduler_init(rtwdev, mac_idx); 2547 if (ret) { 2548 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2549 return ret; 2550 } 2551 2552 ret = addr_cam_init(rtwdev, mac_idx); 2553 if (ret) { 2554 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2555 ret); 2556 return ret; 2557 } 2558 2559 ret = rx_fltr_init(rtwdev, mac_idx); 2560 if (ret) { 2561 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2562 ret); 2563 return ret; 2564 } 2565 2566 ret = cca_ctrl_init(rtwdev, mac_idx); 2567 if (ret) { 2568 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2569 ret); 2570 return ret; 2571 } 2572 2573 ret = nav_ctrl_init(rtwdev); 2574 if (ret) { 2575 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2576 ret); 2577 return ret; 2578 } 2579 2580 ret = spatial_reuse_init(rtwdev, mac_idx); 2581 if (ret) { 2582 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2583 mac_idx, ret); 2584 return ret; 2585 } 2586 2587 ret = tmac_init(rtwdev, mac_idx); 2588 if (ret) { 2589 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2590 return ret; 2591 } 2592 2593 ret = trxptcl_init(rtwdev, mac_idx); 2594 if (ret) { 2595 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2596 return ret; 2597 } 2598 2599 ret = rmac_init(rtwdev, mac_idx); 2600 if (ret) { 2601 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2602 return ret; 2603 } 2604 2605 ret = cmac_com_init(rtwdev, mac_idx); 2606 if (ret) { 2607 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2608 return ret; 2609 } 2610 2611 ret = ptcl_init(rtwdev, mac_idx); 2612 if (ret) { 2613 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2614 return ret; 2615 } 2616 2617 ret = cmac_dma_init(rtwdev, mac_idx); 2618 if (ret) { 2619 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2620 return ret; 2621 } 2622 2623 return ret; 2624 } 2625 2626 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2627 struct rtw89_mac_c2h_info *c2h_info) 2628 { 2629 struct rtw89_mac_h2c_info h2c_info = {0}; 2630 u32 ret; 2631 2632 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2633 h2c_info.content_len = 0; 2634 2635 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2636 if (ret) 2637 return ret; 2638 2639 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2640 return -EINVAL; 2641 2642 return 0; 2643 } 2644 2645 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2646 { 2647 struct rtw89_efuse *efuse = &rtwdev->efuse; 2648 struct rtw89_hal *hal = &rtwdev->hal; 2649 const struct rtw89_chip_info *chip = rtwdev->chip; 2650 struct rtw89_mac_c2h_info c2h_info = {0}; 2651 const struct rtw89_c2hreg_phycap *phycap; 2652 u8 tx_nss; 2653 u8 rx_nss; 2654 u8 tx_ant; 2655 u8 rx_ant; 2656 u32 ret; 2657 2658 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2659 if (ret) 2660 return ret; 2661 2662 phycap = &c2h_info.u.phycap; 2663 2664 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 2665 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 2666 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 2667 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2668 2669 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2670 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2671 2672 if (tx_ant == 1) 2673 hal->antenna_tx = RF_B; 2674 if (rx_ant == 1) 2675 hal->antenna_rx = RF_B; 2676 2677 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2678 hal->antenna_tx = RF_B; 2679 hal->tx_path_diversity = true; 2680 } 2681 2682 if (chip->rf_path_num == 1) { 2683 hal->antenna_tx = RF_A; 2684 hal->antenna_rx = RF_A; 2685 if ((efuse->rfe_type % 3) == 2) 2686 hal->ant_diversity = true; 2687 } 2688 2689 rtw89_debug(rtwdev, RTW89_DBG_FW, 2690 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2691 hal->tx_nss, tx_nss, chip->tx_nss, 2692 hal->rx_nss, rx_nss, chip->rx_nss); 2693 rtw89_debug(rtwdev, RTW89_DBG_FW, 2694 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2695 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2696 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2697 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2698 2699 return 0; 2700 } 2701 2702 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2703 u16 tx_en_u16, u16 mask_u16) 2704 { 2705 u32 ret; 2706 struct rtw89_mac_c2h_info c2h_info = {0}; 2707 struct rtw89_mac_h2c_info h2c_info = {0}; 2708 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 2709 2710 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2711 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 2712 2713 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 2714 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 2715 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 2716 2717 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2718 if (ret) 2719 return ret; 2720 2721 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2722 return -EINVAL; 2723 2724 return 0; 2725 } 2726 2727 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2728 u16 tx_en, u16 tx_en_mask) 2729 { 2730 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 2731 u16 val; 2732 int ret; 2733 2734 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2735 if (ret) 2736 return ret; 2737 2738 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2739 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2740 tx_en, tx_en_mask); 2741 2742 val = rtw89_read16(rtwdev, reg); 2743 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2744 rtw89_write16(rtwdev, reg, val); 2745 2746 return 0; 2747 } 2748 2749 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2750 u32 tx_en, u32 tx_en_mask) 2751 { 2752 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 2753 u32 val; 2754 int ret; 2755 2756 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2757 if (ret) 2758 return ret; 2759 2760 val = rtw89_read32(rtwdev, reg); 2761 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2762 rtw89_write32(rtwdev, reg, val); 2763 2764 return 0; 2765 } 2766 2767 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2768 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2769 { 2770 int ret; 2771 2772 *tx_en = rtw89_read16(rtwdev, 2773 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 2774 2775 switch (sel) { 2776 case RTW89_SCH_TX_SEL_ALL: 2777 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2778 B_AX_CTN_TXEN_ALL_MASK); 2779 if (ret) 2780 return ret; 2781 break; 2782 case RTW89_SCH_TX_SEL_HIQ: 2783 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2784 0, B_AX_CTN_TXEN_HGQ); 2785 if (ret) 2786 return ret; 2787 break; 2788 case RTW89_SCH_TX_SEL_MG0: 2789 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2790 0, B_AX_CTN_TXEN_MGQ); 2791 if (ret) 2792 return ret; 2793 break; 2794 case RTW89_SCH_TX_SEL_MACID: 2795 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2796 B_AX_CTN_TXEN_ALL_MASK); 2797 if (ret) 2798 return ret; 2799 break; 2800 default: 2801 return 0; 2802 } 2803 2804 return 0; 2805 } 2806 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2807 2808 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2809 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2810 { 2811 int ret; 2812 2813 *tx_en = rtw89_read32(rtwdev, 2814 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 2815 2816 switch (sel) { 2817 case RTW89_SCH_TX_SEL_ALL: 2818 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2819 B_AX_CTN_TXEN_ALL_MASK_V1); 2820 if (ret) 2821 return ret; 2822 break; 2823 case RTW89_SCH_TX_SEL_HIQ: 2824 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2825 0, B_AX_CTN_TXEN_HGQ); 2826 if (ret) 2827 return ret; 2828 break; 2829 case RTW89_SCH_TX_SEL_MG0: 2830 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2831 0, B_AX_CTN_TXEN_MGQ); 2832 if (ret) 2833 return ret; 2834 break; 2835 case RTW89_SCH_TX_SEL_MACID: 2836 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2837 B_AX_CTN_TXEN_ALL_MASK_V1); 2838 if (ret) 2839 return ret; 2840 break; 2841 default: 2842 return 0; 2843 } 2844 2845 return 0; 2846 } 2847 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2848 2849 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2850 { 2851 int ret; 2852 2853 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2854 if (ret) 2855 return ret; 2856 2857 return 0; 2858 } 2859 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2860 2861 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2862 { 2863 int ret; 2864 2865 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2866 B_AX_CTN_TXEN_ALL_MASK_V1); 2867 if (ret) 2868 return ret; 2869 2870 return 0; 2871 } 2872 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2873 2874 int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 2875 { 2876 u32 val, reg; 2877 int ret; 2878 2879 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2880 val = buf_len; 2881 val |= B_AX_WD_BUF_REQ_EXEC; 2882 rtw89_write32(rtwdev, reg, val); 2883 2884 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2885 2886 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2887 1, 2000, false, rtwdev, reg); 2888 if (ret) 2889 return ret; 2890 2891 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2892 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 2893 return -ENOENT; 2894 2895 return 0; 2896 } 2897 2898 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2899 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 2900 { 2901 u32 val, cmd_type, reg; 2902 int ret; 2903 2904 cmd_type = ctrl_para->cmd_type; 2905 2906 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2907 val = 0; 2908 val = u32_replace_bits(val, ctrl_para->start_pktid, 2909 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2910 val = u32_replace_bits(val, ctrl_para->end_pktid, 2911 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2912 rtw89_write32(rtwdev, reg, val); 2913 2914 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2915 val = 0; 2916 val = u32_replace_bits(val, ctrl_para->src_pid, 2917 B_AX_CPUQ_OP_SRC_PID_MASK); 2918 val = u32_replace_bits(val, ctrl_para->src_qid, 2919 B_AX_CPUQ_OP_SRC_QID_MASK); 2920 val = u32_replace_bits(val, ctrl_para->dst_pid, 2921 B_AX_CPUQ_OP_DST_PID_MASK); 2922 val = u32_replace_bits(val, ctrl_para->dst_qid, 2923 B_AX_CPUQ_OP_DST_QID_MASK); 2924 rtw89_write32(rtwdev, reg, val); 2925 2926 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2927 val = 0; 2928 val = u32_replace_bits(val, cmd_type, 2929 B_AX_CPUQ_OP_CMD_TYPE_MASK); 2930 val = u32_replace_bits(val, ctrl_para->macid, 2931 B_AX_CPUQ_OP_MACID_MASK); 2932 val = u32_replace_bits(val, ctrl_para->pkt_num, 2933 B_AX_CPUQ_OP_PKTNUM_MASK); 2934 val |= B_AX_WD_CPUQ_OP_EXEC; 2935 rtw89_write32(rtwdev, reg, val); 2936 2937 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2938 2939 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2940 1, 2000, false, rtwdev, reg); 2941 if (ret) 2942 return ret; 2943 2944 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2945 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2946 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2947 2948 return 0; 2949 } 2950 2951 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2952 { 2953 const struct rtw89_dle_mem *cfg; 2954 struct rtw89_cpuio_ctrl ctrl_para = {0}; 2955 u16 pkt_id; 2956 int ret; 2957 2958 cfg = get_dle_mem_cfg(rtwdev, mode); 2959 if (!cfg) { 2960 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2961 return -EINVAL; 2962 } 2963 2964 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 2965 dle_expected_used_size(rtwdev, mode)) { 2966 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2967 return -EINVAL; 2968 } 2969 2970 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2971 2972 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id); 2973 if (ret) { 2974 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2975 return ret; 2976 } 2977 2978 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2979 ctrl_para.start_pktid = pkt_id; 2980 ctrl_para.end_pktid = pkt_id; 2981 ctrl_para.pkt_num = 0; 2982 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2983 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2984 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2985 if (ret) { 2986 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2987 return -EFAULT; 2988 } 2989 2990 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, false, &pkt_id); 2991 if (ret) { 2992 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2993 return ret; 2994 } 2995 2996 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2997 ctrl_para.start_pktid = pkt_id; 2998 ctrl_para.end_pktid = pkt_id; 2999 ctrl_para.pkt_num = 0; 3000 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3001 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3002 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 3003 if (ret) { 3004 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3005 return -EFAULT; 3006 } 3007 3008 return 0; 3009 } 3010 3011 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3012 { 3013 int ret; 3014 u32 reg; 3015 u8 val; 3016 3017 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3018 if (ret) 3019 return ret; 3020 3021 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3022 3023 ret = read_poll_timeout(rtw89_read8, val, 3024 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3025 SW_CVR_DUR_US, 3026 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3027 false, rtwdev, reg); 3028 if (ret) 3029 return ret; 3030 3031 return 0; 3032 } 3033 3034 static int band1_enable(struct rtw89_dev *rtwdev) 3035 { 3036 int ret, i; 3037 u32 sleep_bak[4] = {0}; 3038 u32 pause_bak[4] = {0}; 3039 u32 tx_en; 3040 3041 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3042 if (ret) { 3043 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3044 return ret; 3045 } 3046 3047 for (i = 0; i < 4; i++) { 3048 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3049 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3050 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3051 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3052 } 3053 3054 ret = band_idle_ck_b(rtwdev, 0); 3055 if (ret) { 3056 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3057 return ret; 3058 } 3059 3060 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 3061 if (ret) { 3062 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3063 return ret; 3064 } 3065 3066 for (i = 0; i < 4; i++) { 3067 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3068 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3069 } 3070 3071 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3072 if (ret) { 3073 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3074 return ret; 3075 } 3076 3077 ret = cmac_func_en(rtwdev, 1, true); 3078 if (ret) { 3079 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3080 return ret; 3081 } 3082 3083 ret = cmac_init(rtwdev, 1); 3084 if (ret) { 3085 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3086 return ret; 3087 } 3088 3089 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3090 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3091 3092 return 0; 3093 } 3094 3095 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3096 { 3097 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3098 3099 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3100 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3101 } 3102 3103 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3104 { 3105 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3106 3107 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3108 } 3109 3110 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3111 { 3112 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3113 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3114 3115 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3116 B_AX_TX_GET_ERRPKTID_INT_EN | 3117 B_AX_TX_NXT_ERRPKTID_INT_EN | 3118 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3119 B_AX_TX_OFFSET_ERR_INT_EN | 3120 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3121 if (chip_id == RTL8852C) 3122 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3123 B_AX_TX_ETH_TYPE_ERR_EN | 3124 B_AX_TX_LLC_PRE_ERR_EN | 3125 B_AX_TX_NW_TYPE_ERR_EN | 3126 B_AX_TX_KSRCH_ERR_EN); 3127 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3128 imr->mpdu_tx_imr_set); 3129 3130 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3131 B_AX_GETPKTID_ERR_INT_EN | 3132 B_AX_MHDRLEN_ERR_INT_EN | 3133 B_AX_RPT_ERR_INT_EN); 3134 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3135 imr->mpdu_rx_imr_set); 3136 } 3137 3138 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3139 { 3140 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3141 3142 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3143 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3144 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3145 B_AX_PLE_B_PKTID_ERR_INT_EN); 3146 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3147 imr->sta_sch_imr_set); 3148 } 3149 3150 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3151 { 3152 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3153 3154 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3155 imr->txpktctl_imr_b0_clr); 3156 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3157 imr->txpktctl_imr_b0_set); 3158 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3159 imr->txpktctl_imr_b1_clr); 3160 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3161 imr->txpktctl_imr_b1_set); 3162 } 3163 3164 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3165 { 3166 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3167 3168 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3169 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3170 } 3171 3172 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3173 { 3174 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3175 3176 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3177 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3178 } 3179 3180 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3181 { 3182 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3183 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3184 } 3185 3186 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3187 { 3188 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3189 3190 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3191 imr->host_disp_imr_clr); 3192 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3193 imr->host_disp_imr_set); 3194 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3195 imr->cpu_disp_imr_clr); 3196 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3197 imr->cpu_disp_imr_set); 3198 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3199 imr->other_disp_imr_clr); 3200 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3201 imr->other_disp_imr_set); 3202 } 3203 3204 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3205 { 3206 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3207 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3208 } 3209 3210 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3211 { 3212 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3213 3214 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3215 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3216 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3217 B_AX_BBRPT_CHINFO_IMR_CLR); 3218 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3219 imr->bbrpt_err_imr_set); 3220 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3221 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3222 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3223 } 3224 3225 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3226 { 3227 u32 reg; 3228 3229 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3230 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3231 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3232 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3233 } 3234 3235 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3236 { 3237 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3238 u32 reg; 3239 3240 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3241 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3242 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3243 } 3244 3245 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3246 { 3247 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3248 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3249 u32 reg; 3250 3251 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3252 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3253 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3254 3255 if (chip_id == RTL8852C) { 3256 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3257 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3258 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3259 } 3260 } 3261 3262 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3263 { 3264 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3265 u32 reg; 3266 3267 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3268 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3269 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3270 } 3271 3272 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3273 { 3274 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3275 u32 reg; 3276 3277 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3278 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3279 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3280 } 3281 3282 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3283 { 3284 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3285 u32 reg; 3286 3287 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3288 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3289 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3290 } 3291 3292 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 3293 enum rtw89_mac_hwmod_sel sel) 3294 { 3295 int ret; 3296 3297 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3298 if (ret) { 3299 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3300 sel, mac_idx); 3301 return ret; 3302 } 3303 3304 if (sel == RTW89_DMAC_SEL) { 3305 rtw89_wdrls_imr_enable(rtwdev); 3306 rtw89_wsec_imr_enable(rtwdev); 3307 rtw89_mpdu_trx_imr_enable(rtwdev); 3308 rtw89_sta_sch_imr_enable(rtwdev); 3309 rtw89_txpktctl_imr_enable(rtwdev); 3310 rtw89_wde_imr_enable(rtwdev); 3311 rtw89_ple_imr_enable(rtwdev); 3312 rtw89_pktin_imr_enable(rtwdev); 3313 rtw89_dispatcher_imr_enable(rtwdev); 3314 rtw89_cpuio_imr_enable(rtwdev); 3315 rtw89_bbrpt_imr_enable(rtwdev); 3316 } else if (sel == RTW89_CMAC_SEL) { 3317 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3318 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3319 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3320 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3321 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3322 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3323 } else { 3324 return -EINVAL; 3325 } 3326 3327 return 0; 3328 } 3329 3330 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) 3331 { 3332 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3333 3334 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3335 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3336 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3337 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3338 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 3339 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3340 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3341 } 3342 3343 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 3344 { 3345 int ret = 0; 3346 3347 if (enable) { 3348 ret = band1_enable(rtwdev); 3349 if (ret) { 3350 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3351 return ret; 3352 } 3353 3354 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3355 if (ret) { 3356 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3357 return ret; 3358 } 3359 } else { 3360 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3361 return -EINVAL; 3362 } 3363 3364 return 0; 3365 } 3366 3367 static int set_host_rpr(struct rtw89_dev *rtwdev) 3368 { 3369 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3370 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3371 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3372 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3373 B_AX_RLSRPT0_FLTR_MAP_MASK); 3374 } else { 3375 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3376 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3377 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3378 B_AX_RLSRPT0_FLTR_MAP_MASK); 3379 } 3380 3381 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3382 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3383 3384 return 0; 3385 } 3386 3387 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 3388 { 3389 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3390 int ret; 3391 3392 ret = dmac_init(rtwdev, 0); 3393 if (ret) { 3394 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3395 return ret; 3396 } 3397 3398 ret = cmac_init(rtwdev, 0); 3399 if (ret) { 3400 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3401 return ret; 3402 } 3403 3404 if (is_qta_dbcc(rtwdev, qta_mode)) { 3405 ret = rtw89_mac_dbcc_enable(rtwdev, true); 3406 if (ret) { 3407 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3408 return ret; 3409 } 3410 } 3411 3412 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3413 if (ret) { 3414 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3415 return ret; 3416 } 3417 3418 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3419 if (ret) { 3420 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3421 return ret; 3422 } 3423 3424 rtw89_mac_err_imr_ctrl(rtwdev, true); 3425 3426 ret = set_host_rpr(rtwdev); 3427 if (ret) { 3428 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3429 return ret; 3430 } 3431 3432 return 0; 3433 } 3434 3435 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3436 { 3437 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3438 u32 val32; 3439 3440 if (chip_id == RTL8852B || chip_id == RTL8851B) { 3441 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3442 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3443 return; 3444 } 3445 3446 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3447 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3448 3449 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3450 val32 |= B_AX_FS_WDT_INT; 3451 val32 &= ~B_AX_FS_WDT_INT_MSK; 3452 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3453 } 3454 3455 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3456 { 3457 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3458 3459 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3460 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3461 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3462 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3463 3464 rtw89_disable_fw_watchdog(rtwdev); 3465 3466 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3467 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3468 } 3469 3470 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3471 bool dlfw, bool include_bb) 3472 { 3473 u32 val; 3474 int ret; 3475 3476 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3477 return -EFAULT; 3478 3479 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3480 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3481 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3482 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3483 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3484 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3485 3486 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3487 3488 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3489 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3490 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3491 B_AX_WCPU_FWDL_STS_MASK); 3492 3493 if (dlfw) 3494 val |= B_AX_WCPU_FWDL_EN; 3495 3496 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3497 3498 if (rtwdev->chip->chip_id == RTL8852B) 3499 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3500 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3501 3502 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3503 boot_reason); 3504 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3505 3506 if (!dlfw) { 3507 mdelay(5); 3508 3509 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3510 if (ret) 3511 return ret; 3512 } 3513 3514 return 0; 3515 } 3516 3517 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3518 { 3519 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3520 u32 val; 3521 int ret; 3522 3523 if (chip_id == RTL8852C) 3524 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3525 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3526 else 3527 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3528 B_AX_PKT_BUF_EN; 3529 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3530 3531 if (chip_id == RTL8851B) 3532 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3533 else 3534 val = B_AX_DISPATCHER_CLK_EN; 3535 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3536 3537 if (chip_id != RTL8852C) 3538 goto dle; 3539 3540 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3541 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3542 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3543 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3544 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3545 3546 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3547 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3548 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3549 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3550 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3551 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3552 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3553 3554 dle: 3555 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3556 if (ret) { 3557 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3558 return ret; 3559 } 3560 3561 ret = hfc_init(rtwdev, true, false, true); 3562 if (ret) { 3563 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3564 return ret; 3565 } 3566 3567 return ret; 3568 } 3569 3570 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3571 { 3572 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3573 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3574 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3575 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3576 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3577 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3578 3579 return 0; 3580 } 3581 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3582 3583 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3584 { 3585 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3586 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3587 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3588 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3589 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3590 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3591 3592 return 0; 3593 } 3594 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3595 3596 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 3597 { 3598 int ret; 3599 3600 ret = rtw89_mac_power_switch(rtwdev, true); 3601 if (ret) { 3602 rtw89_mac_power_switch(rtwdev, false); 3603 ret = rtw89_mac_power_switch(rtwdev, true); 3604 if (ret) 3605 return ret; 3606 } 3607 3608 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3609 3610 if (include_bb) { 3611 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 3612 if (rtwdev->dbcc_en) 3613 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 3614 } 3615 3616 ret = rtw89_mac_dmac_pre_init(rtwdev); 3617 if (ret) 3618 return ret; 3619 3620 if (rtwdev->hci.ops->mac_pre_init) { 3621 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3622 if (ret) 3623 return ret; 3624 } 3625 3626 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 3627 if (ret) 3628 return ret; 3629 3630 return 0; 3631 } 3632 3633 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3634 { 3635 const struct rtw89_chip_info *chip = rtwdev->chip; 3636 bool include_bb = !!chip->bbmcu_nr; 3637 int ret; 3638 3639 ret = rtw89_mac_partial_init(rtwdev, include_bb); 3640 if (ret) 3641 goto fail; 3642 3643 ret = rtw89_chip_enable_bb_rf(rtwdev); 3644 if (ret) 3645 goto fail; 3646 3647 ret = rtw89_mac_sys_init(rtwdev); 3648 if (ret) 3649 goto fail; 3650 3651 ret = rtw89_mac_trx_init(rtwdev); 3652 if (ret) 3653 goto fail; 3654 3655 if (rtwdev->hci.ops->mac_post_init) { 3656 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3657 if (ret) 3658 goto fail; 3659 } 3660 3661 rtw89_fw_send_all_early_h2c(rtwdev); 3662 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3663 3664 return ret; 3665 fail: 3666 rtw89_mac_power_switch(rtwdev, false); 3667 3668 return ret; 3669 } 3670 3671 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3672 { 3673 u8 i; 3674 3675 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 3676 return; 3677 3678 for (i = 0; i < 4; i++) { 3679 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3680 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3681 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3682 } 3683 } 3684 3685 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3686 { 3687 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 3688 return; 3689 3690 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3691 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3692 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3693 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3694 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3695 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3696 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3697 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3698 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3699 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3700 } 3701 3702 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3703 { 3704 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3705 u8 grp = macid >> 5; 3706 int ret; 3707 3708 /* If this is called by change_interface() in the case of P2P, it could 3709 * be power-off, so ignore this operation. 3710 */ 3711 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 3712 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3713 return 0; 3714 3715 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3716 if (ret) 3717 return ret; 3718 3719 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3720 3721 return 0; 3722 } 3723 3724 static const struct rtw89_port_reg rtw89_port_base_ax = { 3725 .port_cfg = R_AX_PORT_CFG_P0, 3726 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3727 .bcn_area = R_AX_BCN_AREA_P0, 3728 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3729 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3730 .tbtt_agg = R_AX_TBTT_AGG_P0, 3731 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3732 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3733 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3734 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3735 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3736 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3737 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3738 .tsftr_l = R_AX_TSFTR_LOW_P0, 3739 .tsftr_h = R_AX_TSFTR_HIGH_P0, 3740 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 3741 .bss_color = R_AX_PTCL_BSS_COLOR_0, 3742 .mbssid = R_AX_MBSSID_CTRL, 3743 .mbssid_drop = R_AX_MBSSID_DROP_0, 3744 .tsf_sync = R_AX_PORT0_TSF_SYNC, 3745 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3746 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3747 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 3748 }; 3749 3750 #define BCN_INTERVAL 100 3751 #define BCN_ERLY_DEF 160 3752 #define BCN_SETUP_DEF 2 3753 #define BCN_HOLD_DEF 200 3754 #define BCN_MASK_DEF 0 3755 #define TBTT_ERLY_DEF 5 3756 #define BCN_SET_UNIT 32 3757 #define BCN_ERLY_SET_DLY (10 * 2) 3758 3759 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3760 struct rtw89_vif *rtwvif) 3761 { 3762 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3763 const struct rtw89_port_reg *p = mac->port_base; 3764 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3765 3766 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3767 return; 3768 3769 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3770 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3771 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3772 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3773 3774 msleep(vif->bss_conf.beacon_int + 1); 3775 3776 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3777 B_AX_BRK_SETUP); 3778 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3779 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3780 } 3781 3782 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3783 struct rtw89_vif *rtwvif, bool en) 3784 { 3785 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3786 const struct rtw89_port_reg *p = mac->port_base; 3787 3788 if (en) 3789 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3790 else 3791 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3792 } 3793 3794 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3795 struct rtw89_vif *rtwvif, bool en) 3796 { 3797 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3798 const struct rtw89_port_reg *p = mac->port_base; 3799 3800 if (en) 3801 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3802 else 3803 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3804 } 3805 3806 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3807 struct rtw89_vif *rtwvif) 3808 { 3809 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3810 const struct rtw89_port_reg *p = mac->port_base; 3811 3812 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3813 rtwvif->net_type); 3814 } 3815 3816 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3817 struct rtw89_vif *rtwvif) 3818 { 3819 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3820 const struct rtw89_port_reg *p = mac->port_base; 3821 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3822 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3823 3824 if (en) 3825 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3826 else 3827 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3828 } 3829 3830 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3831 struct rtw89_vif *rtwvif) 3832 { 3833 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3834 const struct rtw89_port_reg *p = mac->port_base; 3835 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3836 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3837 u32 bit = B_AX_RX_BSSID_FIT_EN; 3838 3839 if (en) 3840 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3841 else 3842 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3843 } 3844 3845 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3846 struct rtw89_vif *rtwvif) 3847 { 3848 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3849 const struct rtw89_port_reg *p = mac->port_base; 3850 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3851 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3852 3853 if (en) 3854 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3855 else 3856 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3857 } 3858 3859 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3860 struct rtw89_vif *rtwvif) 3861 { 3862 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3863 const struct rtw89_port_reg *p = mac->port_base; 3864 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3865 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3866 3867 if (en) 3868 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3869 else 3870 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3871 } 3872 3873 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3874 struct rtw89_vif *rtwvif) 3875 { 3876 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3877 const struct rtw89_port_reg *p = mac->port_base; 3878 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3879 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3880 3881 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3882 bcn_int); 3883 } 3884 3885 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3886 struct rtw89_vif *rtwvif) 3887 { 3888 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3889 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3890 const struct rtw89_port_reg *p = mac->port_base; 3891 u8 port = rtwvif->port; 3892 u32 reg; 3893 3894 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif->mac_idx); 3895 rtw89_write8(rtwdev, reg, win); 3896 } 3897 3898 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3899 struct rtw89_vif *rtwvif) 3900 { 3901 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3902 const struct rtw89_port_reg *p = mac->port_base; 3903 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3904 u32 addr; 3905 3906 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif->mac_idx); 3907 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3908 3909 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3910 vif->bss_conf.dtim_period); 3911 } 3912 3913 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3914 struct rtw89_vif *rtwvif) 3915 { 3916 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3917 const struct rtw89_port_reg *p = mac->port_base; 3918 3919 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3920 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3921 } 3922 3923 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3924 struct rtw89_vif *rtwvif) 3925 { 3926 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3927 const struct rtw89_port_reg *p = mac->port_base; 3928 3929 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3930 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3931 } 3932 3933 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3934 struct rtw89_vif *rtwvif) 3935 { 3936 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3937 const struct rtw89_port_reg *p = mac->port_base; 3938 3939 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3940 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3941 } 3942 3943 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3944 struct rtw89_vif *rtwvif) 3945 { 3946 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3947 const struct rtw89_port_reg *p = mac->port_base; 3948 3949 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3950 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3951 } 3952 3953 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3954 struct rtw89_vif *rtwvif) 3955 { 3956 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3957 const struct rtw89_port_reg *p = mac->port_base; 3958 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3959 static const u32 masks[RTW89_PORT_NUM] = { 3960 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3961 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3962 B_AX_BSS_COLOB_AX_PORT_4_MASK, 3963 }; 3964 u8 port = rtwvif->port; 3965 u32 reg_base; 3966 u32 reg; 3967 u8 bss_color; 3968 3969 bss_color = vif->bss_conf.he_bss_color.color; 3970 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 3971 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx); 3972 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3973 } 3974 3975 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3976 struct rtw89_vif *rtwvif) 3977 { 3978 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3979 const struct rtw89_port_reg *p = mac->port_base; 3980 u8 port = rtwvif->port; 3981 u32 reg; 3982 3983 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3984 return; 3985 3986 if (port == 0) { 3987 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif->mac_idx); 3988 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3989 } 3990 } 3991 3992 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3993 struct rtw89_vif *rtwvif) 3994 { 3995 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3996 const struct rtw89_port_reg *p = mac->port_base; 3997 u8 port = rtwvif->port; 3998 u32 reg; 3999 u32 val; 4000 4001 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif->mac_idx); 4002 val = rtw89_read32(rtwdev, reg); 4003 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4004 if (port == 0) 4005 val &= ~BIT(0); 4006 rtw89_write32(rtwdev, reg, val); 4007 } 4008 4009 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4010 struct rtw89_vif *rtwvif, bool enable) 4011 { 4012 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4013 const struct rtw89_port_reg *p = mac->port_base; 4014 4015 if (enable) 4016 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 4017 B_AX_PORT_FUNC_EN); 4018 else 4019 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 4020 B_AX_PORT_FUNC_EN); 4021 } 4022 4023 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4024 struct rtw89_vif *rtwvif) 4025 { 4026 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4027 const struct rtw89_port_reg *p = mac->port_base; 4028 4029 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 4030 BCN_ERLY_DEF); 4031 } 4032 4033 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4034 struct rtw89_vif *rtwvif) 4035 { 4036 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4037 const struct rtw89_port_reg *p = mac->port_base; 4038 u16 val; 4039 4040 if (rtwdev->chip->chip_id != RTL8852C) 4041 return; 4042 4043 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4044 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4045 return; 4046 4047 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4048 B_AX_TBTT_SHIFT_OFST_SIGN; 4049 4050 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 4051 B_AX_TBTT_SHIFT_OFST_MASK, val); 4052 } 4053 4054 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4055 struct rtw89_vif *rtwvif, 4056 struct rtw89_vif *rtwvif_src, 4057 u16 offset_tu) 4058 { 4059 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4060 const struct rtw89_port_reg *p = mac->port_base; 4061 u32 val, reg; 4062 4063 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4064 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif->port * 4, 4065 rtwvif->mac_idx); 4066 4067 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4068 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4069 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4070 } 4071 4072 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4073 struct rtw89_vif *rtwvif, 4074 struct rtw89_vif *rtwvif_src, 4075 u8 offset, int *n_offset) 4076 { 4077 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 4078 return; 4079 4080 /* adjust offset randomly to avoid beacon conflict */ 4081 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4082 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 4083 (*n_offset) * offset); 4084 4085 (*n_offset)++; 4086 } 4087 4088 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4089 { 4090 struct rtw89_vif *src = NULL, *tmp; 4091 u8 offset = 100, vif_aps = 0; 4092 int n_offset = 1; 4093 4094 rtw89_for_each_rtwvif(rtwdev, tmp) { 4095 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4096 src = tmp; 4097 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4098 vif_aps++; 4099 } 4100 4101 if (vif_aps == 0) 4102 return; 4103 4104 offset /= (vif_aps + 1); 4105 4106 rtw89_for_each_rtwvif(rtwdev, tmp) 4107 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4108 } 4109 4110 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4111 { 4112 int ret; 4113 4114 ret = rtw89_mac_port_update(rtwdev, rtwvif); 4115 if (ret) 4116 return ret; 4117 4118 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4119 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4120 4121 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4122 if (ret) 4123 return ret; 4124 4125 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4126 if (ret) 4127 return ret; 4128 4129 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4130 if (ret) 4131 return ret; 4132 4133 ret = rtw89_cam_init(rtwdev, rtwvif); 4134 if (ret) 4135 return ret; 4136 4137 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4138 if (ret) 4139 return ret; 4140 4141 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 4142 if (ret) 4143 return ret; 4144 4145 return 0; 4146 } 4147 4148 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4149 { 4150 int ret; 4151 4152 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4153 if (ret) 4154 return ret; 4155 4156 rtw89_cam_deinit(rtwdev, rtwvif); 4157 4158 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4159 if (ret) 4160 return ret; 4161 4162 return 0; 4163 } 4164 4165 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4166 { 4167 u8 port = rtwvif->port; 4168 4169 if (port >= RTW89_PORT_NUM) 4170 return -EINVAL; 4171 4172 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4173 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4174 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4175 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4176 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4177 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4178 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 4179 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 4180 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4181 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4182 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4183 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4184 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4185 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4186 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4187 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4188 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4189 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4190 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4191 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4192 rtw89_mac_port_tsf_resync_all(rtwdev); 4193 fsleep(BCN_ERLY_SET_DLY); 4194 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4195 4196 return 0; 4197 } 4198 4199 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4200 u64 *tsf) 4201 { 4202 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4203 const struct rtw89_port_reg *p = mac->port_base; 4204 u32 tsf_low, tsf_high; 4205 int ret; 4206 4207 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 4208 if (ret) 4209 return ret; 4210 4211 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 4212 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 4213 *tsf = (u64)tsf_high << 32 | tsf_low; 4214 4215 return 0; 4216 } 4217 4218 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4219 struct cfg80211_bss *bss, 4220 void *data) 4221 { 4222 const struct cfg80211_bss_ies *ies; 4223 const struct element *elem; 4224 bool *tolerated = data; 4225 4226 rcu_read_lock(); 4227 ies = rcu_dereference(bss->ies); 4228 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4229 ies->len); 4230 4231 if (!elem || elem->datalen < 10 || 4232 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4233 *tolerated = false; 4234 rcu_read_unlock(); 4235 } 4236 4237 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4238 struct ieee80211_vif *vif) 4239 { 4240 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4241 struct ieee80211_hw *hw = rtwdev->hw; 4242 bool tolerated = true; 4243 u32 reg; 4244 4245 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 4246 return; 4247 4248 if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR)) 4249 return; 4250 4251 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef, 4252 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4253 &tolerated); 4254 4255 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); 4256 if (tolerated) 4257 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4258 else 4259 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4260 } 4261 4262 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4263 { 4264 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false); 4265 } 4266 4267 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4268 { 4269 int ret; 4270 4271 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 4272 RTW89_MAX_MAC_ID_NUM); 4273 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4274 return -ENOSPC; 4275 4276 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4277 if (ret) 4278 goto release_mac_id; 4279 4280 return 0; 4281 4282 release_mac_id: 4283 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4284 4285 return ret; 4286 } 4287 4288 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4289 { 4290 int ret; 4291 4292 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4293 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4294 4295 return ret; 4296 } 4297 4298 static void 4299 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4300 { 4301 } 4302 4303 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4304 { 4305 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4306 4307 return band == op->band_type && channel == op->primary_channel; 4308 } 4309 4310 static void 4311 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4312 u32 len) 4313 { 4314 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4315 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4316 struct rtw89_chan new; 4317 u8 reason, status, tx_fail, band, actual_period; 4318 u32 last_chan = rtwdev->scan_info.last_chan_idx; 4319 u16 chan; 4320 int ret; 4321 4322 if (!rtwvif) 4323 return; 4324 4325 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 4326 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 4327 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 4328 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 4329 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 4330 actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data); 4331 4332 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4333 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4334 4335 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4336 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4337 band, chan, reason, status, tx_fail, actual_period); 4338 4339 switch (reason) { 4340 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4341 if (rtw89_is_op_chan(rtwdev, band, chan)) 4342 ieee80211_stop_queues(rtwdev->hw); 4343 return; 4344 case RTW89_SCAN_END_SCAN_NOTIFY: 4345 if (rtwvif && rtwvif->scan_req && 4346 last_chan < rtwvif->scan_req->n_channels) { 4347 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4348 if (ret) { 4349 rtw89_hw_scan_abort(rtwdev, vif); 4350 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4351 } 4352 } else { 4353 rtw89_hw_scan_complete(rtwdev, vif, false); 4354 } 4355 break; 4356 case RTW89_SCAN_ENTER_CH_NOTIFY: 4357 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4358 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4359 &rtwdev->scan_info.op_chan); 4360 ieee80211_wake_queues(rtwdev->hw); 4361 } else { 4362 rtw89_chan_create(&new, chan, chan, band, 4363 RTW89_CHANNEL_WIDTH_20); 4364 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4365 &new); 4366 } 4367 break; 4368 default: 4369 return; 4370 } 4371 } 4372 4373 static void 4374 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4375 struct sk_buff *skb) 4376 { 4377 struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4378 enum nl80211_cqm_rssi_threshold_event nl_event; 4379 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4380 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4381 u8 type, event, mac_id; 4382 s8 sig; 4383 4384 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4385 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4386 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4387 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4388 4389 if (mac_id != rtwvif->mac_id) 4390 return; 4391 4392 rtw89_debug(rtwdev, RTW89_DBG_FW, 4393 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4394 mac_id, type, sig, event); 4395 4396 switch (type) { 4397 case RTW89_BCN_FLTR_BEACON_LOSS: 4398 if (!rtwdev->scanning && !rtwvif->offchan) 4399 ieee80211_connection_loss(vif); 4400 else 4401 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4402 return; 4403 case RTW89_BCN_FLTR_NOTIFY: 4404 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4405 break; 4406 case RTW89_BCN_FLTR_RSSI: 4407 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4408 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4409 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4410 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4411 else 4412 return; 4413 break; 4414 default: 4415 return; 4416 } 4417 4418 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4419 } 4420 4421 static void 4422 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4423 u32 len) 4424 { 4425 struct rtw89_vif *rtwvif; 4426 4427 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4428 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4429 } 4430 4431 static void 4432 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4433 { 4434 /* N.B. This will run in interrupt context. */ 4435 4436 rtw89_debug(rtwdev, RTW89_DBG_FW, 4437 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4438 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4439 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4440 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4441 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4442 } 4443 4444 static void 4445 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4446 { 4447 /* N.B. This will run in interrupt context. */ 4448 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4449 const struct rtw89_c2h_done_ack *c2h = 4450 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4451 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4452 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4453 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4454 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4455 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4456 struct rtw89_completion_data data = {}; 4457 unsigned int cond; 4458 4459 rtw89_debug(rtwdev, RTW89_DBG_FW, 4460 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4461 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4462 4463 if (h2c_cat != H2C_CAT_MAC) 4464 return; 4465 4466 switch (h2c_class) { 4467 default: 4468 return; 4469 case H2C_CL_MAC_FW_OFLD: 4470 switch (h2c_func) { 4471 default: 4472 return; 4473 case H2C_FUNC_ADD_SCANOFLD_CH: 4474 case H2C_FUNC_SCANOFLD: 4475 cond = RTW89_FW_OFLD_WAIT_COND(0, h2c_func); 4476 break; 4477 } 4478 4479 data.err = !!h2c_return; 4480 rtw89_complete_cond(fw_ofld_wait, cond, &data); 4481 return; 4482 } 4483 } 4484 4485 static void 4486 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4487 { 4488 rtw89_fw_log_dump(rtwdev, c2h->data, len); 4489 } 4490 4491 static void 4492 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4493 { 4494 } 4495 4496 static void 4497 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 4498 u32 len) 4499 { 4500 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 4501 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 4502 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 4503 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 4504 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 4505 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 4506 struct rtw89_completion_data data = {}; 4507 unsigned int cond; 4508 4509 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 4510 pkt_id, pkt_op, pkt_len); 4511 4512 data.err = !pkt_len; 4513 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 4514 4515 rtw89_complete_cond(wait, cond, &data); 4516 } 4517 4518 static void 4519 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4520 u32 len) 4521 { 4522 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 4523 } 4524 4525 static void 4526 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4527 { 4528 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4529 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4530 4531 switch (func) { 4532 case H2C_FUNC_ADD_MCC: 4533 case H2C_FUNC_START_MCC: 4534 case H2C_FUNC_STOP_MCC: 4535 case H2C_FUNC_DEL_MCC_GROUP: 4536 case H2C_FUNC_RESET_MCC_GROUP: 4537 case H2C_FUNC_MCC_REQ_TSF: 4538 case H2C_FUNC_MCC_MACID_BITMAP: 4539 case H2C_FUNC_MCC_SYNC: 4540 case H2C_FUNC_MCC_SET_DURATION: 4541 break; 4542 default: 4543 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4544 "invalid MCC C2H RCV ACK: func %d\n", func); 4545 return; 4546 } 4547 4548 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4549 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4550 } 4551 4552 static void 4553 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4554 { 4555 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4556 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4557 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4558 struct rtw89_completion_data data = {}; 4559 unsigned int cond; 4560 bool next = false; 4561 4562 switch (func) { 4563 case H2C_FUNC_MCC_REQ_TSF: 4564 next = true; 4565 break; 4566 case H2C_FUNC_MCC_MACID_BITMAP: 4567 case H2C_FUNC_MCC_SYNC: 4568 case H2C_FUNC_MCC_SET_DURATION: 4569 break; 4570 case H2C_FUNC_ADD_MCC: 4571 case H2C_FUNC_START_MCC: 4572 case H2C_FUNC_STOP_MCC: 4573 case H2C_FUNC_DEL_MCC_GROUP: 4574 case H2C_FUNC_RESET_MCC_GROUP: 4575 default: 4576 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4577 "invalid MCC C2H REQ ACK: func %d\n", func); 4578 return; 4579 } 4580 4581 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4582 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 4583 group, func, retcode); 4584 4585 if (!retcode && next) 4586 return; 4587 4588 data.err = !!retcode; 4589 cond = RTW89_MCC_WAIT_COND(group, func); 4590 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4591 } 4592 4593 static void 4594 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4595 { 4596 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 4597 struct rtw89_completion_data data = {}; 4598 struct rtw89_mac_mcc_tsf_rpt *rpt; 4599 unsigned int cond; 4600 4601 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 4602 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 4603 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 4604 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 4605 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 4606 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 4607 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 4608 4609 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4610 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 4611 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 4612 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 4613 4614 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 4615 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4616 } 4617 4618 static void 4619 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4620 { 4621 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 4622 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 4623 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 4624 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 4625 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 4626 struct rtw89_completion_data data = {}; 4627 unsigned int cond; 4628 bool rsp = true; 4629 bool err; 4630 u8 func; 4631 4632 switch (status) { 4633 case RTW89_MAC_MCC_ADD_ROLE_OK: 4634 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 4635 func = H2C_FUNC_ADD_MCC; 4636 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 4637 break; 4638 case RTW89_MAC_MCC_START_GROUP_OK: 4639 case RTW89_MAC_MCC_START_GROUP_FAIL: 4640 func = H2C_FUNC_START_MCC; 4641 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 4642 break; 4643 case RTW89_MAC_MCC_STOP_GROUP_OK: 4644 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 4645 func = H2C_FUNC_STOP_MCC; 4646 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 4647 break; 4648 case RTW89_MAC_MCC_DEL_GROUP_OK: 4649 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 4650 func = H2C_FUNC_DEL_MCC_GROUP; 4651 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 4652 break; 4653 case RTW89_MAC_MCC_RESET_GROUP_OK: 4654 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 4655 func = H2C_FUNC_RESET_MCC_GROUP; 4656 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 4657 break; 4658 case RTW89_MAC_MCC_SWITCH_CH_OK: 4659 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 4660 case RTW89_MAC_MCC_TXNULL0_OK: 4661 case RTW89_MAC_MCC_TXNULL0_FAIL: 4662 case RTW89_MAC_MCC_TXNULL1_OK: 4663 case RTW89_MAC_MCC_TXNULL1_FAIL: 4664 case RTW89_MAC_MCC_SWITCH_EARLY: 4665 case RTW89_MAC_MCC_TBTT: 4666 case RTW89_MAC_MCC_DURATION_START: 4667 case RTW89_MAC_MCC_DURATION_END: 4668 rsp = false; 4669 break; 4670 default: 4671 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4672 "invalid MCC C2H STS RPT: status %d\n", status); 4673 return; 4674 } 4675 4676 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4677 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 4678 group, macid, status, (u64)tsf_high << 32 | tsf_low); 4679 4680 if (!rsp) 4681 return; 4682 4683 data.err = err; 4684 cond = RTW89_MCC_WAIT_COND(group, func); 4685 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4686 } 4687 4688 static 4689 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 4690 struct sk_buff *c2h, u32 len) = { 4691 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 4692 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 4693 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 4694 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 4695 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 4696 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 4697 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 4698 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 4699 }; 4700 4701 static 4702 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 4703 struct sk_buff *c2h, u32 len) = { 4704 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 4705 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 4706 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 4707 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 4708 }; 4709 4710 static 4711 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 4712 struct sk_buff *c2h, u32 len) = { 4713 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 4714 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 4715 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 4716 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 4717 }; 4718 4719 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 4720 { 4721 switch (class) { 4722 default: 4723 return false; 4724 case RTW89_MAC_C2H_CLASS_INFO: 4725 switch (func) { 4726 default: 4727 return false; 4728 case RTW89_MAC_C2H_FUNC_REC_ACK: 4729 case RTW89_MAC_C2H_FUNC_DONE_ACK: 4730 return true; 4731 } 4732 case RTW89_MAC_C2H_CLASS_OFLD: 4733 switch (func) { 4734 default: 4735 return false; 4736 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 4737 return true; 4738 } 4739 case RTW89_MAC_C2H_CLASS_MCC: 4740 return true; 4741 } 4742 } 4743 4744 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4745 u32 len, u8 class, u8 func) 4746 { 4747 void (*handler)(struct rtw89_dev *rtwdev, 4748 struct sk_buff *c2h, u32 len) = NULL; 4749 4750 switch (class) { 4751 case RTW89_MAC_C2H_CLASS_INFO: 4752 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 4753 handler = rtw89_mac_c2h_info_handler[func]; 4754 break; 4755 case RTW89_MAC_C2H_CLASS_OFLD: 4756 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 4757 handler = rtw89_mac_c2h_ofld_handler[func]; 4758 break; 4759 case RTW89_MAC_C2H_CLASS_MCC: 4760 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 4761 handler = rtw89_mac_c2h_mcc_handler[func]; 4762 break; 4763 case RTW89_MAC_C2H_CLASS_FWDBG: 4764 return; 4765 default: 4766 rtw89_info(rtwdev, "c2h class %d not support\n", class); 4767 return; 4768 } 4769 if (!handler) { 4770 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 4771 func); 4772 return; 4773 } 4774 handler(rtwdev, skb, len); 4775 } 4776 4777 static 4778 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 4779 enum rtw89_phy_idx phy_idx, 4780 u32 reg_base, u32 *cr) 4781 { 4782 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 4783 enum rtw89_qta_mode mode = dle_mem->mode; 4784 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 4785 4786 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 4787 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 4788 addr); 4789 goto error; 4790 } 4791 4792 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 4793 if (mode == RTW89_QTA_SCC) { 4794 rtw89_err(rtwdev, 4795 "[TXPWR] addr=0x%x but hw not enable\n", 4796 addr); 4797 goto error; 4798 } 4799 4800 *cr = addr; 4801 return true; 4802 4803 error: 4804 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 4805 addr, phy_idx); 4806 4807 return false; 4808 } 4809 4810 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 4811 { 4812 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 4813 int ret; 4814 4815 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4816 if (ret) 4817 return ret; 4818 4819 if (!enable) { 4820 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 4821 return 0; 4822 } 4823 4824 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 4825 B_AX_APP_MAC_INFO_RPT | 4826 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 4827 B_AX_PPDU_STAT_RPT_CRC32); 4828 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 4829 RTW89_PRPT_DEST_HOST); 4830 4831 return 0; 4832 } 4833 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 4834 4835 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 4836 { 4837 #define MAC_AX_TIME_TH_SH 5 4838 #define MAC_AX_LEN_TH_SH 4 4839 #define MAC_AX_TIME_TH_MAX 255 4840 #define MAC_AX_LEN_TH_MAX 255 4841 #define MAC_AX_TIME_TH_DEF 88 4842 #define MAC_AX_LEN_TH_DEF 4080 4843 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4844 struct ieee80211_hw *hw = rtwdev->hw; 4845 u32 rts_threshold = hw->wiphy->rts_threshold; 4846 u32 time_th, len_th; 4847 u32 reg; 4848 4849 if (rts_threshold == (u32)-1) { 4850 time_th = MAC_AX_TIME_TH_DEF; 4851 len_th = MAC_AX_LEN_TH_DEF; 4852 } else { 4853 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 4854 len_th = rts_threshold; 4855 } 4856 4857 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 4858 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 4859 4860 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 4861 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 4862 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 4863 } 4864 4865 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 4866 { 4867 bool empty; 4868 int ret; 4869 4870 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4871 return; 4872 4873 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 4874 10000, 200000, false, rtwdev); 4875 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 4876 rtw89_info(rtwdev, "timed out to flush queues\n"); 4877 } 4878 4879 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 4880 { 4881 u8 val; 4882 u16 val16; 4883 u32 val32; 4884 int ret; 4885 4886 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 4887 if (rtwdev->chip->chip_id != RTL8851B) 4888 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 4889 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 4890 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 4891 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 4892 if (rtwdev->chip->chip_id != RTL8851B) 4893 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 4894 4895 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 4896 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 4897 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 4898 4899 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 4900 if (ret) { 4901 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 4902 return ret; 4903 } 4904 val32 = val32 & B_AX_WL_RX_CTRL; 4905 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 4906 if (ret) { 4907 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 4908 return ret; 4909 } 4910 4911 switch (coex->pta_mode) { 4912 case RTW89_MAC_AX_COEX_RTK_MODE: 4913 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4914 val &= ~B_AX_BTMODE_MASK; 4915 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 4916 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4917 4918 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 4919 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 4920 4921 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 4922 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 4923 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 4924 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 4925 break; 4926 case RTW89_MAC_AX_COEX_CSR_MODE: 4927 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4928 val &= ~B_AX_BTMODE_MASK; 4929 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 4930 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4931 4932 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 4933 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 4934 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 4935 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 4936 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 4937 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 4938 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 4939 val16 |= B_AX_ENHANCED_BT; 4940 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 4941 4942 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 4943 break; 4944 default: 4945 return -EINVAL; 4946 } 4947 4948 switch (coex->direction) { 4949 case RTW89_MAC_AX_COEX_INNER: 4950 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4951 val = (val & ~BIT(2)) | BIT(1); 4952 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4953 break; 4954 case RTW89_MAC_AX_COEX_OUTPUT: 4955 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4956 val = val | BIT(1) | BIT(0); 4957 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4958 break; 4959 case RTW89_MAC_AX_COEX_INPUT: 4960 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4961 val = val & ~(BIT(2) | BIT(1)); 4962 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4963 break; 4964 default: 4965 return -EINVAL; 4966 } 4967 4968 return 0; 4969 } 4970 EXPORT_SYMBOL(rtw89_mac_coex_init); 4971 4972 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 4973 const struct rtw89_mac_ax_coex *coex) 4974 { 4975 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 4976 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 4977 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 4978 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 4979 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 4980 4981 switch (coex->pta_mode) { 4982 case RTW89_MAC_AX_COEX_RTK_MODE: 4983 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4984 MAC_AX_RTK_MODE); 4985 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 4986 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 4987 break; 4988 case RTW89_MAC_AX_COEX_CSR_MODE: 4989 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4990 MAC_AX_CSR_MODE); 4991 break; 4992 default: 4993 return -EINVAL; 4994 } 4995 4996 return 0; 4997 } 4998 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 4999 5000 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5001 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5002 { 5003 u32 val = 0, ret; 5004 5005 if (gnt_cfg->band[0].gnt_bt) 5006 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 5007 5008 if (gnt_cfg->band[0].gnt_bt_sw_en) 5009 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 5010 5011 if (gnt_cfg->band[0].gnt_wl) 5012 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 5013 5014 if (gnt_cfg->band[0].gnt_wl_sw_en) 5015 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 5016 5017 if (gnt_cfg->band[1].gnt_bt) 5018 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 5019 5020 if (gnt_cfg->band[1].gnt_bt_sw_en) 5021 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 5022 5023 if (gnt_cfg->band[1].gnt_wl) 5024 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 5025 5026 if (gnt_cfg->band[1].gnt_wl_sw_en) 5027 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 5028 5029 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 5030 if (ret) { 5031 rtw89_err(rtwdev, "Write LTE fail!\n"); 5032 return ret; 5033 } 5034 5035 return 0; 5036 } 5037 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 5038 5039 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 5040 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5041 { 5042 u32 val = 0; 5043 5044 if (gnt_cfg->band[0].gnt_bt) 5045 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5046 B_AX_GNT_BT_TX_VAL; 5047 else 5048 val |= B_AX_WL_ACT_VAL; 5049 5050 if (gnt_cfg->band[0].gnt_bt_sw_en) 5051 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5052 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5053 5054 if (gnt_cfg->band[0].gnt_wl) 5055 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5056 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5057 5058 if (gnt_cfg->band[0].gnt_wl_sw_en) 5059 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5060 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5061 5062 if (gnt_cfg->band[1].gnt_bt) 5063 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5064 B_AX_GNT_BT_TX_VAL; 5065 else 5066 val |= B_AX_WL_ACT_VAL; 5067 5068 if (gnt_cfg->band[1].gnt_bt_sw_en) 5069 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5070 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5071 5072 if (gnt_cfg->band[1].gnt_wl) 5073 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5074 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5075 5076 if (gnt_cfg->band[1].gnt_wl_sw_en) 5077 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5078 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5079 5080 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5081 5082 return 0; 5083 } 5084 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5085 5086 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5087 { 5088 u32 reg; 5089 u16 val; 5090 int ret; 5091 5092 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5093 if (ret) 5094 return ret; 5095 5096 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 5097 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5098 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5099 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5100 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5101 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5102 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5103 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 5104 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 5105 B_AX_PLT_EN; 5106 rtw89_write16(rtwdev, reg, val); 5107 5108 return 0; 5109 } 5110 5111 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5112 { 5113 u32 fw_sb; 5114 5115 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5116 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5117 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5118 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5119 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5120 else 5121 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5122 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5123 val = B_AX_TOGGLE | 5124 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5125 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5126 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5127 fsleep(1000); /* avoid BT FW loss information */ 5128 } 5129 5130 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5131 { 5132 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5133 } 5134 5135 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5136 { 5137 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5138 5139 val = wl ? val | BIT(2) : val & ~BIT(2); 5140 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5141 5142 return 0; 5143 } 5144 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5145 5146 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5147 { 5148 struct rtw89_btc *btc = &rtwdev->btc; 5149 struct rtw89_btc_dm *dm = &btc->dm; 5150 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5151 int i; 5152 5153 if (wl) 5154 return 0; 5155 5156 for (i = 0; i < RTW89_PHY_MAX; i++) { 5157 g[i].gnt_bt_sw_en = 1; 5158 g[i].gnt_bt = 1; 5159 g[i].gnt_wl_sw_en = 1; 5160 g[i].gnt_wl = 0; 5161 } 5162 5163 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5164 } 5165 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5166 5167 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5168 { 5169 const struct rtw89_chip_info *chip = rtwdev->chip; 5170 u8 val = 0; 5171 5172 if (chip->chip_id == RTL8852C) 5173 return false; 5174 else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 5175 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5176 B_AX_LTE_MUX_CTRL_PATH >> 24); 5177 5178 return !!val; 5179 } 5180 5181 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 5182 { 5183 u32 reg; 5184 u16 cnt; 5185 5186 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 5187 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 5188 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 5189 5190 return cnt; 5191 } 5192 5193 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 5194 bool keep) 5195 { 5196 u32 reg; 5197 5198 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 5199 return; 5200 5201 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5202 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5203 if (keep) { 5204 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5205 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5206 BFRP_RX_STANDBY_TIMER_KEEP); 5207 } else { 5208 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5209 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5210 BFRP_RX_STANDBY_TIMER_RELEASE); 5211 } 5212 } 5213 5214 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5215 { 5216 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5217 u32 reg; 5218 u32 mask = mac->bfee_ctrl.mask; 5219 5220 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5221 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 5222 if (en) { 5223 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5224 rtw89_write32_set(rtwdev, reg, mask); 5225 } else { 5226 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5227 rtw89_write32_clr(rtwdev, reg, mask); 5228 } 5229 } 5230 5231 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 5232 { 5233 u32 reg; 5234 u32 val32; 5235 int ret; 5236 5237 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5238 if (ret) 5239 return ret; 5240 5241 /* AP mode set tx gid to 63 */ 5242 /* STA mode set tx gid to 0(default) */ 5243 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 5244 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5245 5246 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5247 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5248 5249 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5250 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5251 rtw89_write32(rtwdev, reg, val32); 5252 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5253 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5254 5255 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5256 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5257 B_AX_BFMEE_USE_NSTS | 5258 B_AX_BFMEE_CSI_GID_SEL | 5259 B_AX_BFMEE_CSI_FORCE_RETE_EN); 5260 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5261 rtw89_write32(rtwdev, reg, 5262 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5263 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5264 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5265 5266 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 5267 rtw89_write32_set(rtwdev, reg, 5268 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 5269 5270 return 0; 5271 } 5272 5273 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 5274 struct ieee80211_vif *vif, 5275 struct ieee80211_sta *sta) 5276 { 5277 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5278 u8 mac_idx = rtwvif->mac_idx; 5279 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5280 u8 port_sel = rtwvif->port; 5281 u8 sound_dim = 3, t; 5282 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5283 u32 reg; 5284 u16 val; 5285 int ret; 5286 5287 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5288 if (ret) 5289 return ret; 5290 5291 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5292 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5293 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5294 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5295 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5296 phy_cap[5]); 5297 sound_dim = min(sound_dim, t); 5298 } 5299 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5300 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5301 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5302 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5303 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5304 sta->deflink.vht_cap.cap); 5305 sound_dim = min(sound_dim, t); 5306 } 5307 nc = min(nc, sound_dim); 5308 nr = min(nr, sound_dim); 5309 5310 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5311 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5312 5313 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5314 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5315 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5316 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5317 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5318 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5319 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5320 5321 if (port_sel == 0) 5322 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5323 else 5324 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5325 5326 rtw89_write16(rtwdev, reg, val); 5327 5328 return 0; 5329 } 5330 5331 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 5332 struct ieee80211_vif *vif, 5333 struct ieee80211_sta *sta) 5334 { 5335 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5336 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5337 u32 reg; 5338 u8 mac_idx = rtwvif->mac_idx; 5339 int ret; 5340 5341 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5342 if (ret) 5343 return ret; 5344 5345 if (sta->deflink.he_cap.has_he) { 5346 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5347 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5348 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5349 } 5350 if (sta->deflink.vht_cap.vht_supported) { 5351 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5352 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5353 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5354 } 5355 if (sta->deflink.ht_cap.ht_supported) { 5356 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5357 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5358 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5359 } 5360 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5361 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5362 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5363 rtw89_write32(rtwdev, 5364 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5365 rrsc); 5366 5367 return 0; 5368 } 5369 5370 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 5371 struct ieee80211_vif *vif, 5372 struct ieee80211_sta *sta) 5373 { 5374 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5375 5376 if (rtw89_sta_has_beamformer_cap(sta)) { 5377 rtw89_debug(rtwdev, RTW89_DBG_BF, 5378 "initialize bfee for new association\n"); 5379 rtw89_mac_init_bfee_ax(rtwdev, rtwvif->mac_idx); 5380 rtw89_mac_set_csi_para_reg_ax(rtwdev, vif, sta); 5381 rtw89_mac_csi_rrsc_ax(rtwdev, vif, sta); 5382 } 5383 } 5384 5385 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5386 struct ieee80211_sta *sta) 5387 { 5388 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5389 5390 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 5391 } 5392 5393 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5394 struct ieee80211_bss_conf *conf) 5395 { 5396 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5397 u8 mac_idx = rtwvif->mac_idx; 5398 __le32 *p; 5399 5400 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 5401 5402 p = (__le32 *)conf->mu_group.membership; 5403 rtw89_write32(rtwdev, 5404 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 5405 le32_to_cpu(p[0])); 5406 rtw89_write32(rtwdev, 5407 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 5408 le32_to_cpu(p[1])); 5409 5410 p = (__le32 *)conf->mu_group.position; 5411 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 5412 le32_to_cpu(p[0])); 5413 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 5414 le32_to_cpu(p[1])); 5415 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 5416 le32_to_cpu(p[2])); 5417 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 5418 le32_to_cpu(p[3])); 5419 } 5420 5421 struct rtw89_mac_bf_monitor_iter_data { 5422 struct rtw89_dev *rtwdev; 5423 struct ieee80211_sta *down_sta; 5424 int count; 5425 }; 5426 5427 static 5428 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 5429 { 5430 struct rtw89_mac_bf_monitor_iter_data *iter_data = 5431 (struct rtw89_mac_bf_monitor_iter_data *)data; 5432 struct ieee80211_sta *down_sta = iter_data->down_sta; 5433 int *count = &iter_data->count; 5434 5435 if (down_sta == sta) 5436 return; 5437 5438 if (rtw89_sta_has_beamformer_cap(sta)) 5439 (*count)++; 5440 } 5441 5442 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 5443 struct ieee80211_sta *sta, bool disconnect) 5444 { 5445 struct rtw89_mac_bf_monitor_iter_data data; 5446 5447 data.rtwdev = rtwdev; 5448 data.down_sta = disconnect ? sta : NULL; 5449 data.count = 0; 5450 ieee80211_iterate_stations_atomic(rtwdev->hw, 5451 rtw89_mac_bf_monitor_calc_iter, 5452 &data); 5453 5454 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 5455 if (data.count) 5456 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5457 else 5458 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5459 } 5460 5461 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 5462 { 5463 struct rtw89_traffic_stats *stats = &rtwdev->stats; 5464 struct rtw89_vif *rtwvif; 5465 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 5466 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5467 bool keep_timer = true; 5468 bool old_keep_timer; 5469 5470 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5471 5472 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 5473 keep_timer = false; 5474 5475 if (keep_timer != old_keep_timer) { 5476 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5477 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 5478 keep_timer); 5479 } 5480 5481 if (en == old) 5482 return; 5483 5484 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5485 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 5486 } 5487 5488 static int 5489 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5490 u32 tx_time) 5491 { 5492 #define MAC_AX_DFLT_TX_TIME 5280 5493 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5494 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 5495 u32 reg; 5496 int ret = 0; 5497 5498 if (rtwsta->cctl_tx_time) { 5499 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 5500 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5501 } else { 5502 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5503 if (ret) { 5504 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 5505 return ret; 5506 } 5507 5508 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 5509 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 5510 max_tx_time >> 5); 5511 } 5512 5513 return ret; 5514 } 5515 5516 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5517 bool resume, u32 tx_time) 5518 { 5519 int ret = 0; 5520 5521 if (!resume) { 5522 rtwsta->cctl_tx_time = true; 5523 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5524 } else { 5525 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5526 rtwsta->cctl_tx_time = false; 5527 } 5528 5529 return ret; 5530 } 5531 5532 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5533 u32 *tx_time) 5534 { 5535 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5536 u32 reg; 5537 int ret = 0; 5538 5539 if (rtwsta->cctl_tx_time) { 5540 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 5541 } else { 5542 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5543 if (ret) { 5544 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 5545 return ret; 5546 } 5547 5548 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 5549 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 5550 } 5551 5552 return ret; 5553 } 5554 5555 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 5556 struct rtw89_sta *rtwsta, 5557 bool resume, u8 tx_retry) 5558 { 5559 int ret = 0; 5560 5561 rtwsta->data_tx_cnt_lmt = tx_retry; 5562 5563 if (!resume) { 5564 rtwsta->cctl_tx_retry_limit = true; 5565 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5566 } else { 5567 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5568 rtwsta->cctl_tx_retry_limit = false; 5569 } 5570 5571 return ret; 5572 } 5573 5574 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 5575 struct rtw89_sta *rtwsta, u8 *tx_retry) 5576 { 5577 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5578 u32 reg; 5579 int ret = 0; 5580 5581 if (rtwsta->cctl_tx_retry_limit) { 5582 *tx_retry = rtwsta->data_tx_cnt_lmt; 5583 } else { 5584 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5585 if (ret) { 5586 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 5587 return ret; 5588 } 5589 5590 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); 5591 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 5592 } 5593 5594 return ret; 5595 } 5596 5597 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 5598 struct rtw89_vif *rtwvif, bool en) 5599 { 5600 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5601 u8 mac_idx = rtwvif->mac_idx; 5602 u16 set = mac->muedca_ctrl.mask; 5603 u32 reg; 5604 u32 ret; 5605 5606 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5607 if (ret) 5608 return ret; 5609 5610 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 5611 if (en) 5612 rtw89_write16_set(rtwdev, reg, set); 5613 else 5614 rtw89_write16_clr(rtwdev, reg, set); 5615 5616 return 0; 5617 } 5618 5619 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 5620 { 5621 u32 val32; 5622 int ret; 5623 5624 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5625 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 5626 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 5627 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 5628 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5629 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5630 5631 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5632 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5633 if (ret) { 5634 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 5635 offset, val, mask); 5636 return ret; 5637 } 5638 5639 return 0; 5640 } 5641 EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 5642 5643 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 5644 { 5645 u32 val32; 5646 int ret; 5647 5648 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5649 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 5650 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 5651 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 5652 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5653 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5654 5655 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5656 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5657 if (ret) { 5658 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 5659 return ret; 5660 } 5661 5662 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 5663 5664 return 0; 5665 } 5666 EXPORT_SYMBOL(rtw89_mac_read_xtal_si); 5667 5668 static 5669 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 5670 { 5671 static const enum rtw89_pkt_drop_sel sels[] = { 5672 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5673 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5674 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5675 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5676 }; 5677 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5678 struct rtw89_pkt_drop_params params = {0}; 5679 int i; 5680 5681 params.mac_band = RTW89_MAC_0; 5682 params.macid = rtwsta->mac_id; 5683 params.port = rtwvif->port; 5684 params.mbssid = 0; 5685 params.tf_trs = rtwvif->trigger; 5686 5687 for (i = 0; i < ARRAY_SIZE(sels); i++) { 5688 params.sel = sels[i]; 5689 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5690 } 5691 } 5692 5693 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 5694 { 5695 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 5696 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5697 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 5698 struct rtw89_vif *target = data; 5699 5700 if (rtwvif != target) 5701 return; 5702 5703 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 5704 } 5705 5706 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 5707 { 5708 ieee80211_iterate_stations_atomic(rtwdev->hw, 5709 rtw89_mac_pkt_drop_vif_iter, 5710 rtwvif); 5711 } 5712 5713 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 5714 enum rtw89_mac_idx band) 5715 { 5716 struct rtw89_pkt_drop_params params = {0}; 5717 bool empty; 5718 int i, ret = 0, try_cnt = 3; 5719 5720 params.mac_band = band; 5721 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 5722 5723 for (i = 0; i < try_cnt; i++) { 5724 ret = read_poll_timeout(mac_is_txq_empty, empty, empty, 50, 5725 50000, false, rtwdev); 5726 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 5727 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5728 else 5729 return 0; 5730 } 5731 return ret; 5732 } 5733 5734 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 5735 { 5736 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 5737 5738 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 5739 } 5740 5741 static 5742 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 5743 bool h2c_or_fwdl) 5744 { 5745 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 5746 u8 val; 5747 5748 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 5749 1, FWDL_WAIT_CNT, false, 5750 rtwdev, R_AX_WCPU_FW_CTRL); 5751 } 5752 5753 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 5754 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 5755 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 5756 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 5757 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 5758 .rx_fltr = R_AX_RX_FLTR_OPT, 5759 .port_base = &rtw89_port_base_ax, 5760 .agg_len_ht = R_AX_AGG_LEN_HT_0, 5761 5762 .muedca_ctrl = { 5763 .addr = R_AX_MUEDCA_EN, 5764 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 5765 }, 5766 .bfee_ctrl = { 5767 .addr = R_AX_BFMEE_RESP_OPTION, 5768 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 5769 B_AX_BFMEE_HE_NDPA_EN, 5770 }, 5771 5772 .bf_assoc = rtw89_mac_bf_assoc_ax, 5773 5774 .disable_cpu = rtw89_mac_disable_cpu_ax, 5775 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 5776 .fwdl_get_status = rtw89_fw_get_rdy_ax, 5777 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 5778 5779 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 5780 }; 5781 EXPORT_SYMBOL(rtw89_mac_gen_ax); 5782