1e3ec7017SPing-Ke Shih // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2e3ec7017SPing-Ke Shih /* Copyright(c) 2019-2020 Realtek Corporation 3e3ec7017SPing-Ke Shih */ 4e3ec7017SPing-Ke Shih 5e3ec7017SPing-Ke Shih #include "cam.h" 6967439c7SZong-Zhe Yang #include "chan.h" 7e3ec7017SPing-Ke Shih #include "debug.h" 8e3ec7017SPing-Ke Shih #include "fw.h" 9e3ec7017SPing-Ke Shih #include "mac.h" 10f7333fc2SChia-Yuan Li #include "pci.h" 11e3ec7017SPing-Ke Shih #include "ps.h" 12e3ec7017SPing-Ke Shih #include "reg.h" 13e3ec7017SPing-Ke Shih #include "util.h" 14e3ec7017SPing-Ke Shih 15ec356ffbSChia-Yuan Li const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = { 16e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 17e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 18e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 19e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 20e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 21e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 22e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 23e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 24e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 25e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 26e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 27e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 28e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 29e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 30e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 31e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 32e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 33ec356ffbSChia-Yuan Li [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 34dadb2086SPing-Ke Shih [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 35732dd91dSPing-Ke Shih [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 36732dd91dSPing-Ke Shih [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 37e1400b11SZong-Zhe Yang }; 38e1400b11SZong-Zhe Yang 39ec356ffbSChia-Yuan Li static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 40ec356ffbSChia-Yuan Li u32 val, enum rtw89_mac_mem_sel sel) 41ec356ffbSChia-Yuan Li { 42ec356ffbSChia-Yuan Li u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 43ec356ffbSChia-Yuan Li 44ec356ffbSChia-Yuan Li rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 45ec356ffbSChia-Yuan Li rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val); 46ec356ffbSChia-Yuan Li } 47ec356ffbSChia-Yuan Li 48ec356ffbSChia-Yuan Li static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 49ec356ffbSChia-Yuan Li enum rtw89_mac_mem_sel sel) 50ec356ffbSChia-Yuan Li { 51ec356ffbSChia-Yuan Li u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 52ec356ffbSChia-Yuan Li 53ec356ffbSChia-Yuan Li rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 54ec356ffbSChia-Yuan Li return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY); 55ec356ffbSChia-Yuan Li } 56ec356ffbSChia-Yuan Li 57e3ec7017SPing-Ke Shih int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 58e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 59e3ec7017SPing-Ke Shih { 60e3ec7017SPing-Ke Shih u32 val, r_val; 61e3ec7017SPing-Ke Shih 62e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 63e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 64e3ec7017SPing-Ke Shih val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 65e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 66e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 67e3ec7017SPing-Ke Shih val = B_AX_CMAC_EN; 68e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 69e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 70e3ec7017SPing-Ke Shih val = B_AX_CMAC1_FEN; 71e3ec7017SPing-Ke Shih } else { 72e3ec7017SPing-Ke Shih return -EINVAL; 73e3ec7017SPing-Ke Shih } 74e3ec7017SPing-Ke Shih if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 75e3ec7017SPing-Ke Shih (val & r_val) != val) 76e3ec7017SPing-Ke Shih return -EFAULT; 77e3ec7017SPing-Ke Shih 78e3ec7017SPing-Ke Shih return 0; 79e3ec7017SPing-Ke Shih } 80e3ec7017SPing-Ke Shih 81e3ec7017SPing-Ke Shih int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 82e3ec7017SPing-Ke Shih { 83e3ec7017SPing-Ke Shih u8 lte_ctrl; 84e3ec7017SPing-Ke Shih int ret; 85e3ec7017SPing-Ke Shih 86e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 87e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 88e3ec7017SPing-Ke Shih if (ret) 89e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 90e3ec7017SPing-Ke Shih 91e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 92e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 93e3ec7017SPing-Ke Shih 94e3ec7017SPing-Ke Shih return ret; 95e3ec7017SPing-Ke Shih } 96e3ec7017SPing-Ke Shih 97e3ec7017SPing-Ke Shih int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 98e3ec7017SPing-Ke Shih { 99e3ec7017SPing-Ke Shih u8 lte_ctrl; 100e3ec7017SPing-Ke Shih int ret; 101e3ec7017SPing-Ke Shih 102e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 103e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 104e3ec7017SPing-Ke Shih if (ret) 105e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 106e3ec7017SPing-Ke Shih 107e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 108e3ec7017SPing-Ke Shih *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 109e3ec7017SPing-Ke Shih 110e3ec7017SPing-Ke Shih return ret; 111e3ec7017SPing-Ke Shih } 112e3ec7017SPing-Ke Shih 113e3ec7017SPing-Ke Shih static 114e3ec7017SPing-Ke Shih int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 115e3ec7017SPing-Ke Shih { 116e3ec7017SPing-Ke Shih u32 ctrl_reg, data_reg, ctrl_data; 117e3ec7017SPing-Ke Shih u32 val; 118e3ec7017SPing-Ke Shih int ret; 119e3ec7017SPing-Ke Shih 120e3ec7017SPing-Ke Shih switch (ctrl->type) { 121e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_WDE: 122e3ec7017SPing-Ke Shih ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 123e3ec7017SPing-Ke Shih data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 124e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 125e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 126e3ec7017SPing-Ke Shih B_AX_WDE_DFI_ACTIVE; 127e3ec7017SPing-Ke Shih break; 128e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_PLE: 129e3ec7017SPing-Ke Shih ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 130e3ec7017SPing-Ke Shih data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 131e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 132e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 133e3ec7017SPing-Ke Shih B_AX_PLE_DFI_ACTIVE; 134e3ec7017SPing-Ke Shih break; 135e3ec7017SPing-Ke Shih default: 136e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 137e3ec7017SPing-Ke Shih return -EINVAL; 138e3ec7017SPing-Ke Shih } 139e3ec7017SPing-Ke Shih 140e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 141e3ec7017SPing-Ke Shih 142e3ec7017SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 143e3ec7017SPing-Ke Shih 1, 1000, false, rtwdev, ctrl_reg); 144e3ec7017SPing-Ke Shih if (ret) { 145e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 146e3ec7017SPing-Ke Shih ctrl_reg, ctrl_data); 147e3ec7017SPing-Ke Shih return ret; 148e3ec7017SPing-Ke Shih } 149e3ec7017SPing-Ke Shih 150e3ec7017SPing-Ke Shih ctrl->out_data = rtw89_read32(rtwdev, data_reg); 151e3ec7017SPing-Ke Shih return 0; 152e3ec7017SPing-Ke Shih } 153e3ec7017SPing-Ke Shih 154e3ec7017SPing-Ke Shih static int dle_dfi_quota(struct rtw89_dev *rtwdev, 155e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota *quota) 156e3ec7017SPing-Ke Shih { 157e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 158e3ec7017SPing-Ke Shih int ret; 159e3ec7017SPing-Ke Shih 160e3ec7017SPing-Ke Shih ctrl.type = quota->dle_type; 161e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QUOTA; 162e3ec7017SPing-Ke Shih ctrl.addr = quota->qtaid; 163e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 164e3ec7017SPing-Ke Shih if (ret) { 165e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 166e3ec7017SPing-Ke Shih return ret; 167e3ec7017SPing-Ke Shih } 168e3ec7017SPing-Ke Shih 169e3ec7017SPing-Ke Shih quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 170e3ec7017SPing-Ke Shih quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 171e3ec7017SPing-Ke Shih return 0; 172e3ec7017SPing-Ke Shih } 173e3ec7017SPing-Ke Shih 174e3ec7017SPing-Ke Shih static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 175e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty *qempty) 176e3ec7017SPing-Ke Shih { 177e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 178e3ec7017SPing-Ke Shih u32 ret; 179e3ec7017SPing-Ke Shih 180e3ec7017SPing-Ke Shih ctrl.type = qempty->dle_type; 181e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QEMPTY; 182e3ec7017SPing-Ke Shih ctrl.addr = qempty->grpsel; 183e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 184e3ec7017SPing-Ke Shih if (ret) { 185e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 186e3ec7017SPing-Ke Shih return ret; 187e3ec7017SPing-Ke Shih } 188e3ec7017SPing-Ke Shih 189e3ec7017SPing-Ke Shih qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 190e3ec7017SPing-Ke Shih return 0; 191e3ec7017SPing-Ke Shih } 192e3ec7017SPing-Ke Shih 193e3ec7017SPing-Ke Shih static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 194e3ec7017SPing-Ke Shih { 195e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 196e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 197e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 198e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 199e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 200e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 201e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 202e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 203e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 204e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 205e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 206e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 207e3ec7017SPing-Ke Shih } 208e3ec7017SPing-Ke Shih 209e3ec7017SPing-Ke Shih static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 210e3ec7017SPing-Ke Shih { 211e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty qempty; 212e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota quota; 213e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 214e3ec7017SPing-Ke Shih u32 val, not_empty, i; 215e3ec7017SPing-Ke Shih int ret; 216e3ec7017SPing-Ke Shih 217e3ec7017SPing-Ke Shih qempty.dle_type = DLE_CTRL_TYPE_PLE; 218e3ec7017SPing-Ke Shih qempty.grpsel = 0; 21989e4a00fSÍñigo Huguet qempty.qempty = ~(u32)0; 220e3ec7017SPing-Ke Shih ret = dle_dfi_qempty(rtwdev, &qempty); 221e3ec7017SPing-Ke Shih if (ret) 222e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 223e3ec7017SPing-Ke Shih else 224e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 225e3ec7017SPing-Ke Shih 226e3ec7017SPing-Ke Shih for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 227e3ec7017SPing-Ke Shih if (!(not_empty & BIT(0))) 228e3ec7017SPing-Ke Shih continue; 229e3ec7017SPing-Ke Shih ctrl.type = DLE_CTRL_TYPE_PLE; 230e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QLNKTBL; 231e3ec7017SPing-Ke Shih ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 232e3ec7017SPing-Ke Shih FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 233e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 234e3ec7017SPing-Ke Shih if (ret) 235e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 236e3ec7017SPing-Ke Shih else 237e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 238e3ec7017SPing-Ke Shih FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 239e3ec7017SPing-Ke Shih ctrl.out_data)); 240e3ec7017SPing-Ke Shih } 241e3ec7017SPing-Ke Shih 242e3ec7017SPing-Ke Shih quota.dle_type = DLE_CTRL_TYPE_PLE; 243e3ec7017SPing-Ke Shih quota.qtaid = 6; 244e3ec7017SPing-Ke Shih ret = dle_dfi_quota(rtwdev, "a); 245e3ec7017SPing-Ke Shih if (ret) 246e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 247e3ec7017SPing-Ke Shih else 248e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 249e3ec7017SPing-Ke Shih quota.rsv_pgnum, quota.use_pgnum); 250e3ec7017SPing-Ke Shih 251e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 252e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 253e3ec7017SPing-Ke Shih FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 254e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 255e3ec7017SPing-Ke Shih FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 256e3ec7017SPing-Ke Shih 257e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 258e3ec7017SPing-Ke Shih } 259e3ec7017SPing-Ke Shih 260e3ec7017SPing-Ke Shih static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 261e3ec7017SPing-Ke Shih enum mac_ax_err_info err) 262e3ec7017SPing-Ke Shih { 263e3ec7017SPing-Ke Shih u32 dbg, event; 264e3ec7017SPing-Ke Shih 265e3ec7017SPing-Ke Shih dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 266e3ec7017SPing-Ke Shih event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 267e3ec7017SPing-Ke Shih 268e3ec7017SPing-Ke Shih switch (event) { 269e3ec7017SPing-Ke Shih case MAC_AX_L0_TO_L1_RX_QTA_LOST: 270e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota lost!\n"); 271e3ec7017SPing-Ke Shih rtw89_mac_dump_qta_lost(rtwdev); 272e3ec7017SPing-Ke Shih break; 273e3ec7017SPing-Ke Shih default: 274e3ec7017SPing-Ke Shih break; 275e3ec7017SPing-Ke Shih } 276e3ec7017SPing-Ke Shih } 277e3ec7017SPing-Ke Shih 278f7333fc2SChia-Yuan Li static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 279e3ec7017SPing-Ke Shih { 280f7333fc2SChia-Yuan Li const struct rtw89_chip_info *chip = rtwdev->chip; 281f7333fc2SChia-Yuan Li u32 dmac_err; 282f7333fc2SChia-Yuan Li int i, ret; 283e3ec7017SPing-Ke Shih 284f7333fc2SChia-Yuan Li ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 285f7333fc2SChia-Yuan Li if (ret) { 286f7333fc2SChia-Yuan Li rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 287e3ec7017SPing-Ke Shih return; 288f7333fc2SChia-Yuan Li } 289e3ec7017SPing-Ke Shih 290e3ec7017SPing-Ke Shih dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 291e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 292f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 293f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 294e3ec7017SPing-Ke Shih 295e3ec7017SPing-Ke Shih if (dmac_err) { 296f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 297f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 298e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 299f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 300f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 301f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 302f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 303f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 304f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 305f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 306f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 307f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 308f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 309f7333fc2SChia-Yuan Li } 310e3ec7017SPing-Ke Shih } 311e3ec7017SPing-Ke Shih 312e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 313f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 314e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 315e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 316e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 317f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) 318f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 319f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 320f7333fc2SChia-Yuan Li else 321f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 322f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 323e3ec7017SPing-Ke Shih } 324e3ec7017SPing-Ke Shih 325e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WSEC_ERR_FLAG) { 326f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 327f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 328f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 329f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 330f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 331f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 332f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 333f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 334f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 335f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 336f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 337f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 338f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 339f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 340f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 341f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 342f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 343f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 344f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 345f7333fc2SChia-Yuan Li 346f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 347f7333fc2SChia-Yuan Li B_AX_DBG_SEL0, 0x8B); 348f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 349f7333fc2SChia-Yuan Li B_AX_DBG_SEL1, 0x8B); 350f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 351f7333fc2SChia-Yuan Li B_AX_SEL_0XC0_MASK, 1); 352f7333fc2SChia-Yuan Li for (i = 0; i < 0x10; i++) { 353f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 354f7333fc2SChia-Yuan Li B_AX_SEC_DBG_PORT_FIELD_MASK, i); 355f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 356f7333fc2SChia-Yuan Li i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 357f7333fc2SChia-Yuan Li } 358f7333fc2SChia-Yuan Li } else { 359e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 360e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 361f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 362e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 363f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 364e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 365f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 366e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 367f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 368e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 369f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 370e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 371f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 372e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 373f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 374e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 375f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 376e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 377f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 378e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 379e3ec7017SPing-Ke Shih } 380f7333fc2SChia-Yuan Li } 381e3ec7017SPing-Ke Shih 382e3ec7017SPing-Ke Shih if (dmac_err & B_AX_MPDU_ERR_FLAG) { 383f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 384e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 385e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 386e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 387f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 388e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 389e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 390e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 391e3ec7017SPing-Ke Shih } 392e3ec7017SPing-Ke Shih 393e3ec7017SPing-Ke Shih if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 394f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 395e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 396e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 397e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 398e3ec7017SPing-Ke Shih } 399e3ec7017SPing-Ke Shih 400e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 401f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 402e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 403e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 404e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 405f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 406e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 407e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 408e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 409e3ec7017SPing-Ke Shih } 410e3ec7017SPing-Ke Shih 411e3ec7017SPing-Ke Shih if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 412f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 413f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 414f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 415f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 416f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 417f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 418f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 419f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 420f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 421f7333fc2SChia-Yuan Li } else { 422e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 423e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 424e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 425e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 426e3ec7017SPing-Ke Shih } 427f7333fc2SChia-Yuan Li } 428e3ec7017SPing-Ke Shih 429e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 430f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 431e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 432e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 433e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 434f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 435e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 436e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 437e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 438e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 439e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 440e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 441e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 442e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 443e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 444e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 445e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 446e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 447e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 448e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 449e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 450e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 451e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 452e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 453e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 454f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 455f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 456f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 457f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 458f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 459f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 460f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 461f7333fc2SChia-Yuan Li } else { 462e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 463e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 464e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 465e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 466e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 467e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 468f7333fc2SChia-Yuan Li } 469e3ec7017SPing-Ke Shih } 470e3ec7017SPing-Ke Shih 471e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 472f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 473e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 474e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 475e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 476e3ec7017SPing-Ke Shih } 477e3ec7017SPing-Ke Shih 478f7333fc2SChia-Yuan Li if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 479f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 480f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 481f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 482f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 483f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 484f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 485f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 486f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 487f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 488f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 489f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 490f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 491e3ec7017SPing-Ke Shih } 492e3ec7017SPing-Ke Shih 493f7333fc2SChia-Yuan Li if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 494f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 495f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 496f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 497f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 498f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 499f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 500f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 501f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 502f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 503f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 504f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 505f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 506f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 507f7333fc2SChia-Yuan Li } else { 508e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 509e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 510f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 511f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 512f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 513f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 514f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 515f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 516f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 517f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 518f7333fc2SChia-Yuan Li } 519e3ec7017SPing-Ke Shih } 520e3ec7017SPing-Ke Shih 521f7333fc2SChia-Yuan Li if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 522f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 523f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 524f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 525f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 526f7333fc2SChia-Yuan Li } 527f7333fc2SChia-Yuan Li } 528f7333fc2SChia-Yuan Li 529f7333fc2SChia-Yuan Li static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev, 530f7333fc2SChia-Yuan Li u8 band) 531f7333fc2SChia-Yuan Li { 532f7333fc2SChia-Yuan Li const struct rtw89_chip_info *chip = rtwdev->chip; 533f7333fc2SChia-Yuan Li u32 offset = 0; 534f7333fc2SChia-Yuan Li u32 cmac_err; 535f7333fc2SChia-Yuan Li int ret; 536f7333fc2SChia-Yuan Li 537f7333fc2SChia-Yuan Li ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 538f7333fc2SChia-Yuan Li if (ret) { 539f7333fc2SChia-Yuan Li if (band) 540f7333fc2SChia-Yuan Li rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 541f7333fc2SChia-Yuan Li else 542f7333fc2SChia-Yuan Li rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 543f7333fc2SChia-Yuan Li return; 544f7333fc2SChia-Yuan Li } 545f7333fc2SChia-Yuan Li 546f7333fc2SChia-Yuan Li if (band) 547f7333fc2SChia-Yuan Li offset = RTW89_MAC_AX_BAND_REG_OFFSET; 548f7333fc2SChia-Yuan Li 549f7333fc2SChia-Yuan Li cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 550f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 551f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 552f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 553f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 554f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 555f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 556f7333fc2SChia-Yuan Li 557e3ec7017SPing-Ke Shih if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 558f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 559f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 560f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 561f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 562e3ec7017SPing-Ke Shih } 563e3ec7017SPing-Ke Shih 564e3ec7017SPing-Ke Shih if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 565f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 566f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 567f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 568f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 569e3ec7017SPing-Ke Shih } 570e3ec7017SPing-Ke Shih 571e3ec7017SPing-Ke Shih if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 572f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 573f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 574f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 575f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 576f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 577f7333fc2SChia-Yuan Li } else { 578f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 579f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 580f7333fc2SChia-Yuan Li } 581e3ec7017SPing-Ke Shih } 582e3ec7017SPing-Ke Shih 583f7333fc2SChia-Yuan Li if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 584f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 585f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 586f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 587f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 588f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 589f7333fc2SChia-Yuan Li } else { 590f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 591f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 592f7333fc2SChia-Yuan Li } 593e3ec7017SPing-Ke Shih } 594e3ec7017SPing-Ke Shih 595e3ec7017SPing-Ke Shih if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 596f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 597f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 598f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 599f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 600e3ec7017SPing-Ke Shih } 601e3ec7017SPing-Ke Shih 602e3ec7017SPing-Ke Shih if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 603f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 604f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 605f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 606f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 607f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 608f7333fc2SChia-Yuan Li } else { 609f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 610f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 611e3ec7017SPing-Ke Shih } 612f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 613f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 614f7333fc2SChia-Yuan Li } 615f7333fc2SChia-Yuan Li 616f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 617f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 618f7333fc2SChia-Yuan Li } 619f7333fc2SChia-Yuan Li 620f7333fc2SChia-Yuan Li static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 621f7333fc2SChia-Yuan Li enum mac_ax_err_info err) 622f7333fc2SChia-Yuan Li { 623f7333fc2SChia-Yuan Li if (err != MAC_AX_ERR_L1_ERR_DMAC && 624f7333fc2SChia-Yuan Li err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 625f7333fc2SChia-Yuan Li err != MAC_AX_ERR_L0_ERR_CMAC0 && 626f5d98831SZong-Zhe Yang err != MAC_AX_ERR_L0_ERR_CMAC1 && 627f5d98831SZong-Zhe Yang err != MAC_AX_ERR_RXI300) 628f7333fc2SChia-Yuan Li return; 629f7333fc2SChia-Yuan Li 630f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 631f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 632f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 633f7333fc2SChia-Yuan Li 634f7333fc2SChia-Yuan Li rtw89_mac_dump_dmac_err_status(rtwdev); 635f7333fc2SChia-Yuan Li rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0); 636f7333fc2SChia-Yuan Li if (rtwdev->dbcc_en) 637f7333fc2SChia-Yuan Li rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1); 638e3ec7017SPing-Ke Shih 639e3ec7017SPing-Ke Shih rtwdev->hci.ops->dump_err_status(rtwdev); 640e3ec7017SPing-Ke Shih 641e3ec7017SPing-Ke Shih if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 642e3ec7017SPing-Ke Shih rtw89_mac_dump_l0_to_l1(rtwdev, err); 643e3ec7017SPing-Ke Shih 644e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "<---\n"); 645e3ec7017SPing-Ke Shih } 646e3ec7017SPing-Ke Shih 647e3ec7017SPing-Ke Shih u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 648e3ec7017SPing-Ke Shih { 649198b6cf7SZong-Zhe Yang u32 err, err_scnr; 650e3ec7017SPing-Ke Shih int ret; 651e3ec7017SPing-Ke Shih 652e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 653e3ec7017SPing-Ke Shih false, rtwdev, R_AX_HALT_C2H_CTRL); 654e3ec7017SPing-Ke Shih if (ret) { 655e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "Polling FW err status fail\n"); 656e3ec7017SPing-Ke Shih return ret; 657e3ec7017SPing-Ke Shih } 658e3ec7017SPing-Ke Shih 659e3ec7017SPing-Ke Shih err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 660e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 661e3ec7017SPing-Ke Shih 662198b6cf7SZong-Zhe Yang err_scnr = RTW89_ERROR_SCENARIO(err); 663198b6cf7SZong-Zhe Yang if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 664198b6cf7SZong-Zhe Yang err = MAC_AX_ERR_CPU_EXCEPTION; 665198b6cf7SZong-Zhe Yang else if (err_scnr == RTW89_WCPU_ASSERTION) 666198b6cf7SZong-Zhe Yang err = MAC_AX_ERR_ASSERTION; 667f5d98831SZong-Zhe Yang else if (err_scnr == RTW89_RXI300_ERROR) 668f5d98831SZong-Zhe Yang err = MAC_AX_ERR_RXI300; 669198b6cf7SZong-Zhe Yang 670e3ec7017SPing-Ke Shih rtw89_fw_st_dbg_dump(rtwdev); 671e3ec7017SPing-Ke Shih rtw89_mac_dump_err_status(rtwdev, err); 672e3ec7017SPing-Ke Shih 673e3ec7017SPing-Ke Shih return err; 674e3ec7017SPing-Ke Shih } 675e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_get_err_status); 676e3ec7017SPing-Ke Shih 677e3ec7017SPing-Ke Shih int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 678e3ec7017SPing-Ke Shih { 679e3ec7017SPing-Ke Shih u32 halt; 680e3ec7017SPing-Ke Shih int ret = 0; 681e3ec7017SPing-Ke Shih 682e3ec7017SPing-Ke Shih if (err > MAC_AX_SET_ERR_MAX) { 683e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 684e3ec7017SPing-Ke Shih return -EINVAL; 685e3ec7017SPing-Ke Shih } 686e3ec7017SPing-Ke Shih 687e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 688e3ec7017SPing-Ke Shih 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 689e3ec7017SPing-Ke Shih if (ret) { 690e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 691e3ec7017SPing-Ke Shih return -EFAULT; 692e3ec7017SPing-Ke Shih } 693e3ec7017SPing-Ke Shih 694e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 695e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 696e3ec7017SPing-Ke Shih 697e3ec7017SPing-Ke Shih return 0; 698e3ec7017SPing-Ke Shih } 699e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_set_err_status); 700e3ec7017SPing-Ke Shih 701e3ec7017SPing-Ke Shih static int hfc_reset_param(struct rtw89_dev *rtwdev) 702e3ec7017SPing-Ke Shih { 703e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 704e3ec7017SPing-Ke Shih struct rtw89_hfc_param_ini param_ini = {NULL}; 705e3ec7017SPing-Ke Shih u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 706e3ec7017SPing-Ke Shih 707e3ec7017SPing-Ke Shih switch (rtwdev->hci.type) { 708e3ec7017SPing-Ke Shih case RTW89_HCI_TYPE_PCIE: 709e3ec7017SPing-Ke Shih param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 710e3ec7017SPing-Ke Shih param->en = 0; 711e3ec7017SPing-Ke Shih break; 712e3ec7017SPing-Ke Shih default: 713e3ec7017SPing-Ke Shih return -EINVAL; 714e3ec7017SPing-Ke Shih } 715e3ec7017SPing-Ke Shih 716e3ec7017SPing-Ke Shih if (param_ini.pub_cfg) 717e3ec7017SPing-Ke Shih param->pub_cfg = *param_ini.pub_cfg; 718e3ec7017SPing-Ke Shih 719e3ec7017SPing-Ke Shih if (param_ini.prec_cfg) { 720e3ec7017SPing-Ke Shih param->prec_cfg = *param_ini.prec_cfg; 721e3ec7017SPing-Ke Shih rtwdev->hal.sw_amsdu_max_size = 722e3ec7017SPing-Ke Shih param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; 723e3ec7017SPing-Ke Shih } 724e3ec7017SPing-Ke Shih 725e3ec7017SPing-Ke Shih if (param_ini.ch_cfg) 726e3ec7017SPing-Ke Shih param->ch_cfg = param_ini.ch_cfg; 727e3ec7017SPing-Ke Shih 728e3ec7017SPing-Ke Shih memset(¶m->ch_info, 0, sizeof(param->ch_info)); 729e3ec7017SPing-Ke Shih memset(¶m->pub_info, 0, sizeof(param->pub_info)); 730e3ec7017SPing-Ke Shih param->mode = param_ini.mode; 731e3ec7017SPing-Ke Shih 732e3ec7017SPing-Ke Shih return 0; 733e3ec7017SPing-Ke Shih } 734e3ec7017SPing-Ke Shih 735e3ec7017SPing-Ke Shih static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 736e3ec7017SPing-Ke Shih { 737e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 738e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 739e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 740e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 741e3ec7017SPing-Ke Shih 742e3ec7017SPing-Ke Shih if (ch >= RTW89_DMA_CH_NUM) 743e3ec7017SPing-Ke Shih return -EINVAL; 744e3ec7017SPing-Ke Shih 745e3ec7017SPing-Ke Shih if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 746e3ec7017SPing-Ke Shih ch_cfg[ch].max > pub_cfg->pub_max) 747e3ec7017SPing-Ke Shih return -EINVAL; 748e3ec7017SPing-Ke Shih if (ch_cfg[ch].grp >= grp_num) 749e3ec7017SPing-Ke Shih return -EINVAL; 750e3ec7017SPing-Ke Shih 751e3ec7017SPing-Ke Shih return 0; 752e3ec7017SPing-Ke Shih } 753e3ec7017SPing-Ke Shih 754e3ec7017SPing-Ke Shih static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 755e3ec7017SPing-Ke Shih { 756e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 757e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 758e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 759e3ec7017SPing-Ke Shih 760e3ec7017SPing-Ke Shih if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 761e3ec7017SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852A) 762e3ec7017SPing-Ke Shih return 0; 763e3ec7017SPing-Ke Shih else 764e3ec7017SPing-Ke Shih return -EFAULT; 765e3ec7017SPing-Ke Shih } 766e3ec7017SPing-Ke Shih 767e3ec7017SPing-Ke Shih return 0; 768e3ec7017SPing-Ke Shih } 769e3ec7017SPing-Ke Shih 770e3ec7017SPing-Ke Shih static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 771e3ec7017SPing-Ke Shih { 772e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 773e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 774e3ec7017SPing-Ke Shih 775e3ec7017SPing-Ke Shih if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 776c6477cb2SKevin Lo return -EFAULT; 777e3ec7017SPing-Ke Shih 778e3ec7017SPing-Ke Shih return 0; 779e3ec7017SPing-Ke Shih } 780e3ec7017SPing-Ke Shih 781e3ec7017SPing-Ke Shih static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 782e3ec7017SPing-Ke Shih { 783ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 784ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 785e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 786e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 787e3ec7017SPing-Ke Shih int ret = 0; 788e3ec7017SPing-Ke Shih u32 val = 0; 789e3ec7017SPing-Ke Shih 790e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 791e3ec7017SPing-Ke Shih if (ret) 792e3ec7017SPing-Ke Shih return ret; 793e3ec7017SPing-Ke Shih 794e3ec7017SPing-Ke Shih ret = hfc_ch_cfg_chk(rtwdev, ch); 795e3ec7017SPing-Ke Shih if (ret) 796e3ec7017SPing-Ke Shih return ret; 797e3ec7017SPing-Ke Shih 798e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_B1HI) 799e3ec7017SPing-Ke Shih return -EINVAL; 800e3ec7017SPing-Ke Shih 801e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 802e3ec7017SPing-Ke Shih u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 803e3ec7017SPing-Ke Shih (cfg[ch].grp ? B_AX_GRP : 0); 804ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 805e3ec7017SPing-Ke Shih 806e3ec7017SPing-Ke Shih return 0; 807e3ec7017SPing-Ke Shih } 808e3ec7017SPing-Ke Shih 809e3ec7017SPing-Ke Shih static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 810e3ec7017SPing-Ke Shih { 811ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 812ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 813e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 814e3ec7017SPing-Ke Shih struct rtw89_hfc_ch_info *info = param->ch_info; 815e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 816e3ec7017SPing-Ke Shih u32 val; 817e3ec7017SPing-Ke Shih u32 ret; 818e3ec7017SPing-Ke Shih 819e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 820e3ec7017SPing-Ke Shih if (ret) 821e3ec7017SPing-Ke Shih return ret; 822e3ec7017SPing-Ke Shih 823e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_H2C) 824e3ec7017SPing-Ke Shih return -EINVAL; 825e3ec7017SPing-Ke Shih 826ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 827e3ec7017SPing-Ke Shih info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 828e3ec7017SPing-Ke Shih if (ch < RTW89_DMA_H2C) 829e3ec7017SPing-Ke Shih info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 830e3ec7017SPing-Ke Shih else 831e3ec7017SPing-Ke Shih info[ch].used = cfg[ch].min - info[ch].aval; 832e3ec7017SPing-Ke Shih 833e3ec7017SPing-Ke Shih return 0; 834e3ec7017SPing-Ke Shih } 835e3ec7017SPing-Ke Shih 836e3ec7017SPing-Ke Shih static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 837e3ec7017SPing-Ke Shih { 838ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 839ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 840e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 841e3ec7017SPing-Ke Shih u32 val; 842e3ec7017SPing-Ke Shih int ret; 843e3ec7017SPing-Ke Shih 844e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 845e3ec7017SPing-Ke Shih if (ret) 846e3ec7017SPing-Ke Shih return ret; 847e3ec7017SPing-Ke Shih 848e3ec7017SPing-Ke Shih ret = hfc_pub_cfg_chk(rtwdev); 849e3ec7017SPing-Ke Shih if (ret) 850e3ec7017SPing-Ke Shih return ret; 851e3ec7017SPing-Ke Shih 852e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 853e3ec7017SPing-Ke Shih u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 854ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 855e3ec7017SPing-Ke Shih 856e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 857ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 858e3ec7017SPing-Ke Shih 859e3ec7017SPing-Ke Shih return 0; 860e3ec7017SPing-Ke Shih } 861e3ec7017SPing-Ke Shih 862e3ec7017SPing-Ke Shih static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 863e3ec7017SPing-Ke Shih { 864ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 865ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 866e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 867e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 868e3ec7017SPing-Ke Shih struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 869e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 870e3ec7017SPing-Ke Shih u32 val; 871e3ec7017SPing-Ke Shih int ret; 872e3ec7017SPing-Ke Shih 873e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 874e3ec7017SPing-Ke Shih if (ret) 875e3ec7017SPing-Ke Shih return ret; 876e3ec7017SPing-Ke Shih 877ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_info1); 878e3ec7017SPing-Ke Shih info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 879e3ec7017SPing-Ke Shih info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 880ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_info3); 881e3ec7017SPing-Ke Shih info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 882e3ec7017SPing-Ke Shih info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 883e3ec7017SPing-Ke Shih info->pub_aval = 884ab8a5671SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 885e3ec7017SPing-Ke Shih B_AX_PUB_AVAL_PG_MASK); 886e3ec7017SPing-Ke Shih info->wp_aval = 887ab8a5671SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 888e3ec7017SPing-Ke Shih B_AX_WP_AVAL_PG_MASK); 889e3ec7017SPing-Ke Shih 890ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 891e3ec7017SPing-Ke Shih param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 892e3ec7017SPing-Ke Shih param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 893e3ec7017SPing-Ke Shih param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 894e3ec7017SPing-Ke Shih prec_cfg->ch011_full_cond = 895e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 896e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond = 897e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 898e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_full_cond = 899e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 900e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_full_cond = 901e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 902e3ec7017SPing-Ke Shih 903ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 904e3ec7017SPing-Ke Shih prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 905e3ec7017SPing-Ke Shih prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 906e3ec7017SPing-Ke Shih 907ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 908e3ec7017SPing-Ke Shih pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 909e3ec7017SPing-Ke Shih 910ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 911e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 912e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 913e3ec7017SPing-Ke Shih 914ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 915e3ec7017SPing-Ke Shih pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 916e3ec7017SPing-Ke Shih 917ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 918e3ec7017SPing-Ke Shih pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 919e3ec7017SPing-Ke Shih pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 920e3ec7017SPing-Ke Shih 921e3ec7017SPing-Ke Shih ret = hfc_pub_info_chk(rtwdev); 922e3ec7017SPing-Ke Shih if (param->en && ret) 923e3ec7017SPing-Ke Shih return ret; 924e3ec7017SPing-Ke Shih 925e3ec7017SPing-Ke Shih return 0; 926e3ec7017SPing-Ke Shih } 927e3ec7017SPing-Ke Shih 928e3ec7017SPing-Ke Shih static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 929e3ec7017SPing-Ke Shih { 930ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 931ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 932e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 933e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 934e3ec7017SPing-Ke Shih u32 val; 935e3ec7017SPing-Ke Shih 936e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 937ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 938e3ec7017SPing-Ke Shih 939ab8a5671SPing-Ke Shih rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 940e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK, 941e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond); 942e3ec7017SPing-Ke Shih } 943e3ec7017SPing-Ke Shih 944e3ec7017SPing-Ke Shih static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 945e3ec7017SPing-Ke Shih { 946ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 947ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 948e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 949e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 950e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 951e3ec7017SPing-Ke Shih u32 val; 952e3ec7017SPing-Ke Shih 953e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 954e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 955ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 956e3ec7017SPing-Ke Shih 957e3ec7017SPing-Ke Shih val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 958ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 959e3ec7017SPing-Ke Shih 960e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->wp_ch07_prec, 961e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH07_MASK) | 962e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->wp_ch811_prec, 963e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH811_MASK); 964ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 965e3ec7017SPing-Ke Shih 966ab8a5671SPing-Ke Shih val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 967e3ec7017SPing-Ke Shih param->mode, B_AX_HCI_FC_MODE_MASK); 968e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 969e3ec7017SPing-Ke Shih B_AX_HCI_FC_WD_FULL_COND_MASK); 970e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 971e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK); 972e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 973e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 974e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 975e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 976ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 977e3ec7017SPing-Ke Shih } 978e3ec7017SPing-Ke Shih 979e3ec7017SPing-Ke Shih static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 980e3ec7017SPing-Ke Shih { 981ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 982ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 983e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 984e3ec7017SPing-Ke Shih u32 val; 985e3ec7017SPing-Ke Shih 986ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 987e3ec7017SPing-Ke Shih param->en = en; 988e3ec7017SPing-Ke Shih param->h2c_en = h2c_en; 989e3ec7017SPing-Ke Shih val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 990e3ec7017SPing-Ke Shih val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 991e3ec7017SPing-Ke Shih (val & ~B_AX_HCI_FC_CH12_EN); 992ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 993e3ec7017SPing-Ke Shih } 994e3ec7017SPing-Ke Shih 995e3ec7017SPing-Ke Shih static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 996e3ec7017SPing-Ke Shih { 997a1b7163aSPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 998a1b7163aSPing-Ke Shih u32 dma_ch_mask = chip->dma_ch_mask; 999e3ec7017SPing-Ke Shih u8 ch; 1000e3ec7017SPing-Ke Shih u32 ret = 0; 1001e3ec7017SPing-Ke Shih 1002e3ec7017SPing-Ke Shih if (reset) 1003e3ec7017SPing-Ke Shih ret = hfc_reset_param(rtwdev); 1004e3ec7017SPing-Ke Shih if (ret) 1005e3ec7017SPing-Ke Shih return ret; 1006e3ec7017SPing-Ke Shih 1007e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1008e3ec7017SPing-Ke Shih if (ret) 1009e3ec7017SPing-Ke Shih return ret; 1010e3ec7017SPing-Ke Shih 1011e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, false, false); 1012e3ec7017SPing-Ke Shih 1013e3ec7017SPing-Ke Shih if (!en && h2c_en) { 1014e3ec7017SPing-Ke Shih hfc_h2c_cfg(rtwdev); 1015e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, en, h2c_en); 1016e3ec7017SPing-Ke Shih return ret; 1017e3ec7017SPing-Ke Shih } 1018e3ec7017SPing-Ke Shih 1019e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1020a1b7163aSPing-Ke Shih if (dma_ch_mask & BIT(ch)) 1021a1b7163aSPing-Ke Shih continue; 1022e3ec7017SPing-Ke Shih ret = hfc_ch_ctrl(rtwdev, ch); 1023e3ec7017SPing-Ke Shih if (ret) 1024e3ec7017SPing-Ke Shih return ret; 1025e3ec7017SPing-Ke Shih } 1026e3ec7017SPing-Ke Shih 1027e3ec7017SPing-Ke Shih ret = hfc_pub_ctrl(rtwdev); 1028e3ec7017SPing-Ke Shih if (ret) 1029e3ec7017SPing-Ke Shih return ret; 1030e3ec7017SPing-Ke Shih 1031e3ec7017SPing-Ke Shih hfc_mix_cfg(rtwdev); 1032e3ec7017SPing-Ke Shih if (en || h2c_en) { 1033e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, en, h2c_en); 1034e3ec7017SPing-Ke Shih udelay(10); 1035e3ec7017SPing-Ke Shih } 1036e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1037a1b7163aSPing-Ke Shih if (dma_ch_mask & BIT(ch)) 1038a1b7163aSPing-Ke Shih continue; 1039e3ec7017SPing-Ke Shih ret = hfc_upd_ch_info(rtwdev, ch); 1040e3ec7017SPing-Ke Shih if (ret) 1041e3ec7017SPing-Ke Shih return ret; 1042e3ec7017SPing-Ke Shih } 1043e3ec7017SPing-Ke Shih ret = hfc_upd_mix_info(rtwdev); 1044e3ec7017SPing-Ke Shih 1045e3ec7017SPing-Ke Shih return ret; 1046e3ec7017SPing-Ke Shih } 1047e3ec7017SPing-Ke Shih 1048e3ec7017SPing-Ke Shih #define PWR_POLL_CNT 2000 1049e3ec7017SPing-Ke Shih static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1050e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cfg) 1051e3ec7017SPing-Ke Shih { 1052e3ec7017SPing-Ke Shih u8 val = 0; 1053e3ec7017SPing-Ke Shih int ret; 1054e3ec7017SPing-Ke Shih u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1055e3ec7017SPing-Ke Shih cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1056e3ec7017SPing-Ke Shih 1057e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1058e3ec7017SPing-Ke Shih 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1059e3ec7017SPing-Ke Shih 1060e3ec7017SPing-Ke Shih if (!ret) 1061e3ec7017SPing-Ke Shih return 0; 1062e3ec7017SPing-Ke Shih 1063e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1064e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1065e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1066e3ec7017SPing-Ke Shih 1067e3ec7017SPing-Ke Shih return -EBUSY; 1068e3ec7017SPing-Ke Shih } 1069e3ec7017SPing-Ke Shih 1070e3ec7017SPing-Ke Shih static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1071e3ec7017SPing-Ke Shih u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1072e3ec7017SPing-Ke Shih { 1073e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cur_cfg; 1074e3ec7017SPing-Ke Shih u32 addr; 1075e3ec7017SPing-Ke Shih u8 val; 1076e3ec7017SPing-Ke Shih 1077e3ec7017SPing-Ke Shih for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1078e3ec7017SPing-Ke Shih if (!(cur_cfg->intf_msk & intf_msk) || 1079e3ec7017SPing-Ke Shih !(cur_cfg->cv_msk & cv_msk)) 1080e3ec7017SPing-Ke Shih continue; 1081e3ec7017SPing-Ke Shih 1082e3ec7017SPing-Ke Shih switch (cur_cfg->cmd) { 1083e3ec7017SPing-Ke Shih case PWR_CMD_WRITE: 1084e3ec7017SPing-Ke Shih addr = cur_cfg->addr; 1085e3ec7017SPing-Ke Shih 1086e3ec7017SPing-Ke Shih if (cur_cfg->base == PWR_BASE_SDIO) 1087e3ec7017SPing-Ke Shih addr |= SDIO_LOCAL_BASE_ADDR; 1088e3ec7017SPing-Ke Shih 1089e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, addr); 1090e3ec7017SPing-Ke Shih val &= ~(cur_cfg->msk); 1091e3ec7017SPing-Ke Shih val |= (cur_cfg->val & cur_cfg->msk); 1092e3ec7017SPing-Ke Shih 1093e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, addr, val); 1094e3ec7017SPing-Ke Shih break; 1095e3ec7017SPing-Ke Shih case PWR_CMD_POLL: 1096e3ec7017SPing-Ke Shih if (pwr_cmd_poll(rtwdev, cur_cfg)) 1097e3ec7017SPing-Ke Shih return -EBUSY; 1098e3ec7017SPing-Ke Shih break; 1099e3ec7017SPing-Ke Shih case PWR_CMD_DELAY: 1100e3ec7017SPing-Ke Shih if (cur_cfg->val == PWR_DELAY_US) 1101e3ec7017SPing-Ke Shih udelay(cur_cfg->addr); 1102e3ec7017SPing-Ke Shih else 1103e3ec7017SPing-Ke Shih fsleep(cur_cfg->addr * 1000); 1104e3ec7017SPing-Ke Shih break; 1105e3ec7017SPing-Ke Shih default: 1106e3ec7017SPing-Ke Shih return -EINVAL; 1107e3ec7017SPing-Ke Shih } 1108e3ec7017SPing-Ke Shih } 1109e3ec7017SPing-Ke Shih 1110e3ec7017SPing-Ke Shih return 0; 1111e3ec7017SPing-Ke Shih } 1112e3ec7017SPing-Ke Shih 1113e3ec7017SPing-Ke Shih static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1114e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq) 1115e3ec7017SPing-Ke Shih { 1116e3ec7017SPing-Ke Shih int ret; 1117e3ec7017SPing-Ke Shih 1118e3ec7017SPing-Ke Shih for (; *cfg_seq; cfg_seq++) { 1119e3ec7017SPing-Ke Shih ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1120e3ec7017SPing-Ke Shih PWR_INTF_MSK_PCIE, *cfg_seq); 1121e3ec7017SPing-Ke Shih if (ret) 1122e3ec7017SPing-Ke Shih return -EBUSY; 1123e3ec7017SPing-Ke Shih } 1124e3ec7017SPing-Ke Shih 1125e3ec7017SPing-Ke Shih return 0; 1126e3ec7017SPing-Ke Shih } 1127e3ec7017SPing-Ke Shih 1128e3ec7017SPing-Ke Shih static enum rtw89_rpwm_req_pwr_state 1129e3ec7017SPing-Ke Shih rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1130e3ec7017SPing-Ke Shih { 1131e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 1132e3ec7017SPing-Ke Shih 1133e3ec7017SPing-Ke Shih switch (rtwdev->ps_mode) { 1134e3ec7017SPing-Ke Shih case RTW89_PS_MODE_RFOFF: 1135e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1136e3ec7017SPing-Ke Shih break; 1137e3ec7017SPing-Ke Shih case RTW89_PS_MODE_CLK_GATED: 1138e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1139e3ec7017SPing-Ke Shih break; 1140e3ec7017SPing-Ke Shih case RTW89_PS_MODE_PWR_GATED: 1141e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1142e3ec7017SPing-Ke Shih break; 1143e3ec7017SPing-Ke Shih default: 1144e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1145e3ec7017SPing-Ke Shih break; 1146e3ec7017SPing-Ke Shih } 1147e3ec7017SPing-Ke Shih return state; 1148e3ec7017SPing-Ke Shih } 1149e3ec7017SPing-Ke Shih 1150e3ec7017SPing-Ke Shih static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 11517bfd05ffSChin-Yen Lee enum rtw89_rpwm_req_pwr_state req_pwr_state, 11527bfd05ffSChin-Yen Lee bool notify_wake) 1153e3ec7017SPing-Ke Shih { 1154e3ec7017SPing-Ke Shih u16 request; 1155e3ec7017SPing-Ke Shih 11567bfd05ffSChin-Yen Lee spin_lock_bh(&rtwdev->rpwm_lock); 11577bfd05ffSChin-Yen Lee 1158e3ec7017SPing-Ke Shih request = rtw89_read16(rtwdev, R_AX_RPWM); 1159e3ec7017SPing-Ke Shih request ^= request | PS_RPWM_TOGGLE; 11607bfd05ffSChin-Yen Lee request |= req_pwr_state; 1161e3ec7017SPing-Ke Shih 11627bfd05ffSChin-Yen Lee if (notify_wake) { 11637bfd05ffSChin-Yen Lee request |= PS_RPWM_NOTIFY_WAKE; 11647bfd05ffSChin-Yen Lee } else { 1165e3ec7017SPing-Ke Shih rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1166e3ec7017SPing-Ke Shih RPWM_SEQ_NUM_MAX; 11677bfd05ffSChin-Yen Lee request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 11687bfd05ffSChin-Yen Lee rtwdev->mac.rpwm_seq_num); 1169e3ec7017SPing-Ke Shih 1170e3ec7017SPing-Ke Shih if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1171e3ec7017SPing-Ke Shih request |= PS_RPWM_ACK; 11727bfd05ffSChin-Yen Lee } 1173e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 11747bfd05ffSChin-Yen Lee 11757bfd05ffSChin-Yen Lee spin_unlock_bh(&rtwdev->rpwm_lock); 1176e3ec7017SPing-Ke Shih } 1177e3ec7017SPing-Ke Shih 1178e3ec7017SPing-Ke Shih static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1179e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state req_pwr_state) 1180e3ec7017SPing-Ke Shih { 1181e3ec7017SPing-Ke Shih bool request_deep_mode; 1182e3ec7017SPing-Ke Shih bool in_deep_mode; 1183e3ec7017SPing-Ke Shih u8 rpwm_req_num; 1184e3ec7017SPing-Ke Shih u8 cpwm_rsp_seq; 1185e3ec7017SPing-Ke Shih u8 cpwm_seq; 1186e3ec7017SPing-Ke Shih u8 cpwm_status; 1187e3ec7017SPing-Ke Shih 1188e3ec7017SPing-Ke Shih if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1189e3ec7017SPing-Ke Shih request_deep_mode = true; 1190e3ec7017SPing-Ke Shih else 1191e3ec7017SPing-Ke Shih request_deep_mode = false; 1192e3ec7017SPing-Ke Shih 1193e3ec7017SPing-Ke Shih if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1194e3ec7017SPing-Ke Shih in_deep_mode = true; 1195e3ec7017SPing-Ke Shih else 1196e3ec7017SPing-Ke Shih in_deep_mode = false; 1197e3ec7017SPing-Ke Shih 1198e3ec7017SPing-Ke Shih if (request_deep_mode != in_deep_mode) 1199e3ec7017SPing-Ke Shih return -EPERM; 1200e3ec7017SPing-Ke Shih 1201e3ec7017SPing-Ke Shih if (request_deep_mode) 1202e3ec7017SPing-Ke Shih return 0; 1203e3ec7017SPing-Ke Shih 1204e3ec7017SPing-Ke Shih rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1205e1757e80SPing-Ke Shih cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1206e3ec7017SPing-Ke Shih PS_CPWM_RSP_SEQ_NUM); 1207e3ec7017SPing-Ke Shih 1208e3ec7017SPing-Ke Shih if (rpwm_req_num != cpwm_rsp_seq) 1209e3ec7017SPing-Ke Shih return -EPERM; 1210e3ec7017SPing-Ke Shih 1211e3ec7017SPing-Ke Shih rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1212e3ec7017SPing-Ke Shih CPWM_SEQ_NUM_MAX; 1213e3ec7017SPing-Ke Shih 1214e1757e80SPing-Ke Shih cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1215e3ec7017SPing-Ke Shih if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1216e3ec7017SPing-Ke Shih return -EPERM; 1217e3ec7017SPing-Ke Shih 1218e1757e80SPing-Ke Shih cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1219e3ec7017SPing-Ke Shih if (cpwm_status != req_pwr_state) 1220e3ec7017SPing-Ke Shih return -EPERM; 1221e3ec7017SPing-Ke Shih 1222e3ec7017SPing-Ke Shih return 0; 1223e3ec7017SPing-Ke Shih } 1224e3ec7017SPing-Ke Shih 1225e3ec7017SPing-Ke Shih void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1226e3ec7017SPing-Ke Shih { 1227e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 122839a76521SPing-Ke Shih unsigned long delay = enter ? 10 : 150; 1229e3ec7017SPing-Ke Shih int ret; 123048c0e347SChin-Yen Lee int i; 1231e3ec7017SPing-Ke Shih 1232e3ec7017SPing-Ke Shih if (enter) 1233e3ec7017SPing-Ke Shih state = rtw89_mac_get_req_pwr_state(rtwdev); 1234e3ec7017SPing-Ke Shih else 1235e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1236e3ec7017SPing-Ke Shih 123748c0e347SChin-Yen Lee for (i = 0; i < RPWM_TRY_CNT; i++) { 12387bfd05ffSChin-Yen Lee rtw89_mac_send_rpwm(rtwdev, state, false); 123948c0e347SChin-Yen Lee ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 124048c0e347SChin-Yen Lee !ret, delay, 15000, false, 124148c0e347SChin-Yen Lee rtwdev, state); 124248c0e347SChin-Yen Lee if (!ret) 124348c0e347SChin-Yen Lee break; 124448c0e347SChin-Yen Lee 124548c0e347SChin-Yen Lee if (i == RPWM_TRY_CNT - 1) 1246e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1247e3ec7017SPing-Ke Shih enter ? "entering" : "leaving"); 124848c0e347SChin-Yen Lee else 124948c0e347SChin-Yen Lee rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 125048c0e347SChin-Yen Lee "%d time firmware failed to ack for %s ps mode\n", 125148c0e347SChin-Yen Lee i + 1, enter ? "entering" : "leaving"); 125248c0e347SChin-Yen Lee } 1253e3ec7017SPing-Ke Shih } 1254e3ec7017SPing-Ke Shih 12557bfd05ffSChin-Yen Lee void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 12567bfd05ffSChin-Yen Lee { 12577bfd05ffSChin-Yen Lee enum rtw89_rpwm_req_pwr_state state; 12587bfd05ffSChin-Yen Lee 12597bfd05ffSChin-Yen Lee state = rtw89_mac_get_req_pwr_state(rtwdev); 12607bfd05ffSChin-Yen Lee rtw89_mac_send_rpwm(rtwdev, state, true); 12617bfd05ffSChin-Yen Lee } 12627bfd05ffSChin-Yen Lee 1263e3ec7017SPing-Ke Shih static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1264e3ec7017SPing-Ke Shih { 1265e3ec7017SPing-Ke Shih #define PWR_ACT 1 1266e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1267e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq; 12682a7e54dbSPing-Ke Shih int (*cfg_func)(struct rtw89_dev *rtwdev); 1269e3ec7017SPing-Ke Shih int ret; 1270e3ec7017SPing-Ke Shih u8 val; 1271e3ec7017SPing-Ke Shih 12722a7e54dbSPing-Ke Shih if (on) { 1273e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_on_seq; 12742a7e54dbSPing-Ke Shih cfg_func = chip->ops->pwr_on_func; 12752a7e54dbSPing-Ke Shih } else { 1276e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_off_seq; 12772a7e54dbSPing-Ke Shih cfg_func = chip->ops->pwr_off_func; 12782a7e54dbSPing-Ke Shih } 1279e3ec7017SPing-Ke Shih 1280e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1281e3ec7017SPing-Ke Shih __rtw89_leave_ps_mode(rtwdev); 1282e3ec7017SPing-Ke Shih 1283e3ec7017SPing-Ke Shih val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1284e3ec7017SPing-Ke Shih if (on && val == PWR_ACT) { 1285e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC has already powered on\n"); 1286e3ec7017SPing-Ke Shih return -EBUSY; 1287e3ec7017SPing-Ke Shih } 1288e3ec7017SPing-Ke Shih 12892a7e54dbSPing-Ke Shih ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1290e3ec7017SPing-Ke Shih if (ret) 1291e3ec7017SPing-Ke Shih return ret; 1292e3ec7017SPing-Ke Shih 1293e3ec7017SPing-Ke Shih if (on) { 1294e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1295e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1296e3ec7017SPing-Ke Shih } else { 1297e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1298e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1299e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1300967439c7SZong-Zhe Yang rtw89_set_entity_state(rtwdev, false); 1301e3ec7017SPing-Ke Shih } 1302e3ec7017SPing-Ke Shih 1303e3ec7017SPing-Ke Shih return 0; 1304e3ec7017SPing-Ke Shih #undef PWR_ACT 1305e3ec7017SPing-Ke Shih } 1306e3ec7017SPing-Ke Shih 1307e3ec7017SPing-Ke Shih void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1308e3ec7017SPing-Ke Shih { 1309e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 1310e3ec7017SPing-Ke Shih } 1311e3ec7017SPing-Ke Shih 1312e3ec7017SPing-Ke Shih static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1313e3ec7017SPing-Ke Shih { 1314e3ec7017SPing-Ke Shih u32 func_en = 0; 1315e3ec7017SPing-Ke Shih u32 ck_en = 0; 1316e3ec7017SPing-Ke Shih u32 c1pc_en = 0; 1317e3ec7017SPing-Ke Shih u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1318e3ec7017SPing-Ke Shih u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1319e3ec7017SPing-Ke Shih 1320e3ec7017SPing-Ke Shih func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1321e3ec7017SPing-Ke Shih B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 13225cb5562dSPing-Ke Shih B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 13235cb5562dSPing-Ke Shih B_AX_CMAC_CRPRT; 1324e3ec7017SPing-Ke Shih ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1325e3ec7017SPing-Ke Shih B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1326e3ec7017SPing-Ke Shih B_AX_RMAC_CKEN; 1327e3ec7017SPing-Ke Shih c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1328e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1329e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1330e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1331e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1332e3ec7017SPing-Ke Shih 1333e3ec7017SPing-Ke Shih if (en) { 1334e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1335e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1336e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1337e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1338e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1339e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1340e3ec7017SPing-Ke Shih } 1341e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1342e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1343e3ec7017SPing-Ke Shih } else { 1344e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1345e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1346e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1347e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1348e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1349e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1350e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1351e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1352e3ec7017SPing-Ke Shih } 1353e3ec7017SPing-Ke Shih } 1354e3ec7017SPing-Ke Shih 1355e3ec7017SPing-Ke Shih return 0; 1356e3ec7017SPing-Ke Shih } 1357e3ec7017SPing-Ke Shih 1358e3ec7017SPing-Ke Shih static int dmac_func_en(struct rtw89_dev *rtwdev) 1359e3ec7017SPing-Ke Shih { 1360828a4396SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1361e3ec7017SPing-Ke Shih u32 val32; 1362e3ec7017SPing-Ke Shih 1363828a4396SChia-Yuan Li if (chip_id == RTL8852C) 1364828a4396SChia-Yuan Li val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1365828a4396SChia-Yuan Li B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1366828a4396SChia-Yuan Li B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1367828a4396SChia-Yuan Li B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1368828a4396SChia-Yuan Li B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1369828a4396SChia-Yuan Li B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1370828a4396SChia-Yuan Li B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1371828a4396SChia-Yuan Li else 1372828a4396SChia-Yuan Li val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1373828a4396SChia-Yuan Li B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1374828a4396SChia-Yuan Li B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1375828a4396SChia-Yuan Li B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1376828a4396SChia-Yuan Li B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1377828a4396SChia-Yuan Li B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1378828a4396SChia-Yuan Li B_AX_DMAC_CRPRT); 1379e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1380e3ec7017SPing-Ke Shih 1381e3ec7017SPing-Ke Shih val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1382e3ec7017SPing-Ke Shih B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1383e3ec7017SPing-Ke Shih B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1384828a4396SChia-Yuan Li B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1385e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1386e3ec7017SPing-Ke Shih 138743863efeSChangcheng Deng return 0; 1388e3ec7017SPing-Ke Shih } 1389e3ec7017SPing-Ke Shih 1390e3ec7017SPing-Ke Shih static int chip_func_en(struct rtw89_dev *rtwdev) 1391e3ec7017SPing-Ke Shih { 1392828a4396SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1393828a4396SChia-Yuan Li 139414b6e9f4SPing-Ke Shih if (chip_id == RTL8852A || chip_id == RTL8852B) 139514b6e9f4SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1396828a4396SChia-Yuan Li B_AX_OCP_L1_MASK); 1397e3ec7017SPing-Ke Shih 1398e3ec7017SPing-Ke Shih return 0; 1399e3ec7017SPing-Ke Shih } 1400e3ec7017SPing-Ke Shih 1401e3ec7017SPing-Ke Shih static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1402e3ec7017SPing-Ke Shih { 1403e3ec7017SPing-Ke Shih int ret; 1404e3ec7017SPing-Ke Shih 1405e3ec7017SPing-Ke Shih ret = dmac_func_en(rtwdev); 1406e3ec7017SPing-Ke Shih if (ret) 1407e3ec7017SPing-Ke Shih return ret; 1408e3ec7017SPing-Ke Shih 1409e3ec7017SPing-Ke Shih ret = cmac_func_en(rtwdev, 0, true); 1410e3ec7017SPing-Ke Shih if (ret) 1411e3ec7017SPing-Ke Shih return ret; 1412e3ec7017SPing-Ke Shih 1413e3ec7017SPing-Ke Shih ret = chip_func_en(rtwdev); 1414e3ec7017SPing-Ke Shih if (ret) 1415e3ec7017SPing-Ke Shih return ret; 1416e3ec7017SPing-Ke Shih 1417e3ec7017SPing-Ke Shih return ret; 1418e3ec7017SPing-Ke Shih } 1419e3ec7017SPing-Ke Shih 142030645118SPing-Ke Shih const struct rtw89_mac_size_set rtw89_mac_size = { 142130645118SPing-Ke Shih .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1422e3ec7017SPing-Ke Shih /* PCIE 64 */ 142330645118SPing-Ke Shih .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1424e3ec7017SPing-Ke Shih /* DLFW */ 142530645118SPing-Ke Shih .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1426a1cb0971SPing-Ke Shih /* PCIE 64 */ 1427a1cb0971SPing-Ke Shih .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1428a1cb0971SPing-Ke Shih /* DLFW */ 1429a1cb0971SPing-Ke Shih .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 143079d099e0SPing-Ke Shih /* 8852C DLFW */ 143130645118SPing-Ke Shih .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 143279d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 143330645118SPing-Ke Shih .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1434e3ec7017SPing-Ke Shih /* PCIE */ 143530645118SPing-Ke Shih .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1436e3ec7017SPing-Ke Shih /* DLFW */ 143730645118SPing-Ke Shih .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1438a1cb0971SPing-Ke Shih /* PCIE 64 */ 1439a1cb0971SPing-Ke Shih .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1440a1cb0971SPing-Ke Shih /* DLFW */ 1441a1cb0971SPing-Ke Shih .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 144279d099e0SPing-Ke Shih /* 8852C DLFW */ 144330645118SPing-Ke Shih .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 144479d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 144530645118SPing-Ke Shih .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1446e3ec7017SPing-Ke Shih /* PCIE 64 */ 144730645118SPing-Ke Shih .wde_qt0 = {3792, 196, 0, 107,}, 1448e3ec7017SPing-Ke Shih /* DLFW */ 144930645118SPing-Ke Shih .wde_qt4 = {0, 0, 0, 0,}, 1450a1cb0971SPing-Ke Shih /* PCIE 64 */ 1451a1cb0971SPing-Ke Shih .wde_qt6 = {448, 48, 0, 16,}, 145279d099e0SPing-Ke Shih /* 8852C DLFW */ 145330645118SPing-Ke Shih .wde_qt17 = {0, 0, 0, 0,}, 145479d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 145530645118SPing-Ke Shih .wde_qt18 = {3228, 60, 0, 40,}, 1456e3ec7017SPing-Ke Shih /* PCIE SCC */ 145730645118SPing-Ke Shih .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1458e3ec7017SPing-Ke Shih /* PCIE SCC */ 145930645118SPing-Ke Shih .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1460e3ec7017SPing-Ke Shih /* DLFW */ 146130645118SPing-Ke Shih .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1462a1cb0971SPing-Ke Shih /* PCIE 64 */ 1463a1cb0971SPing-Ke Shih .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 146479d099e0SPing-Ke Shih /* DLFW 52C */ 146530645118SPing-Ke Shih .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 146679d099e0SPing-Ke Shih /* DLFW 52C */ 146730645118SPing-Ke Shih .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 146879d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 146930645118SPing-Ke Shih .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 147079d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 147130645118SPing-Ke Shih .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1472a1cb0971SPing-Ke Shih /* PCIE 64 */ 1473a1cb0971SPing-Ke Shih .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 14747a68ec3dSChih-Kang Chang /* 8852A PCIE WOW */ 14757a68ec3dSChih-Kang Chang .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 14766863ad91SChin-Yen Lee /* 8852B PCIE WOW */ 14776863ad91SChin-Yen Lee .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 147879d099e0SPing-Ke Shih }; 147930645118SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_size); 148079d099e0SPing-Ke Shih 1481e3ec7017SPing-Ke Shih static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1482e3ec7017SPing-Ke Shih enum rtw89_qta_mode mode) 1483e3ec7017SPing-Ke Shih { 1484e3ec7017SPing-Ke Shih struct rtw89_mac_info *mac = &rtwdev->mac; 1485e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 1486e3ec7017SPing-Ke Shih 1487e3ec7017SPing-Ke Shih cfg = &rtwdev->chip->dle_mem[mode]; 1488e3ec7017SPing-Ke Shih if (!cfg) 1489e3ec7017SPing-Ke Shih return NULL; 1490e3ec7017SPing-Ke Shih 1491e3ec7017SPing-Ke Shih if (cfg->mode != mode) { 1492e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1493e3ec7017SPing-Ke Shih return NULL; 1494e3ec7017SPing-Ke Shih } 1495e3ec7017SPing-Ke Shih 1496e3ec7017SPing-Ke Shih mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; 1497e3ec7017SPing-Ke Shih mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1498e3ec7017SPing-Ke Shih mac->dle_info.qta_mode = mode; 1499e3ec7017SPing-Ke Shih mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1500e3ec7017SPing-Ke Shih mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1501e3ec7017SPing-Ke Shih 1502e3ec7017SPing-Ke Shih return cfg; 1503e3ec7017SPing-Ke Shih } 1504e3ec7017SPing-Ke Shih 150541d56769SChih-Kang Chang static bool mac_is_txq_empty(struct rtw89_dev *rtwdev) 150641d56769SChih-Kang Chang { 150741d56769SChih-Kang Chang struct rtw89_mac_dle_dfi_qempty qempty; 150841d56769SChih-Kang Chang u32 qnum, qtmp, val32, msk32; 150941d56769SChih-Kang Chang int i, j, ret; 151041d56769SChih-Kang Chang 151141d56769SChih-Kang Chang qnum = rtwdev->chip->wde_qempty_acq_num; 151241d56769SChih-Kang Chang qempty.dle_type = DLE_CTRL_TYPE_WDE; 151341d56769SChih-Kang Chang 151441d56769SChih-Kang Chang for (i = 0; i < qnum; i++) { 151541d56769SChih-Kang Chang qempty.grpsel = i; 151641d56769SChih-Kang Chang ret = dle_dfi_qempty(rtwdev, &qempty); 151741d56769SChih-Kang Chang if (ret) { 151841d56769SChih-Kang Chang rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 151941d56769SChih-Kang Chang return false; 152041d56769SChih-Kang Chang } 152141d56769SChih-Kang Chang qtmp = qempty.qempty; 152241d56769SChih-Kang Chang for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 152341d56769SChih-Kang Chang val32 = FIELD_GET(QEMP_ACQ_GRP_QSEL_MASK, qtmp); 152441d56769SChih-Kang Chang if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 152541d56769SChih-Kang Chang return false; 152641d56769SChih-Kang Chang qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 152741d56769SChih-Kang Chang } 152841d56769SChih-Kang Chang } 152941d56769SChih-Kang Chang 153041d56769SChih-Kang Chang qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel; 153141d56769SChih-Kang Chang ret = dle_dfi_qempty(rtwdev, &qempty); 153241d56769SChih-Kang Chang if (ret) { 153341d56769SChih-Kang Chang rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 153441d56769SChih-Kang Chang return false; 153541d56769SChih-Kang Chang } 153641d56769SChih-Kang Chang msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 153741d56769SChih-Kang Chang if ((qempty.qempty & msk32) != msk32) 153841d56769SChih-Kang Chang return false; 153941d56769SChih-Kang Chang 154041d56769SChih-Kang Chang if (rtwdev->dbcc_en) { 154141d56769SChih-Kang Chang msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 154241d56769SChih-Kang Chang if ((qempty.qempty & msk32) != msk32) 154341d56769SChih-Kang Chang return false; 154441d56769SChih-Kang Chang } 154541d56769SChih-Kang Chang 154641d56769SChih-Kang Chang msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 154741d56769SChih-Kang Chang B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 154841d56769SChih-Kang Chang B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 154941d56769SChih-Kang Chang B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 155041d56769SChih-Kang Chang B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 155141d56769SChih-Kang Chang B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 155241d56769SChih-Kang Chang B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 155341d56769SChih-Kang Chang B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 155441d56769SChih-Kang Chang val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 155541d56769SChih-Kang Chang 155641d56769SChih-Kang Chang return (val32 & msk32) == msk32; 155741d56769SChih-Kang Chang } 155841d56769SChih-Kang Chang 1559e3ec7017SPing-Ke Shih static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1560e3ec7017SPing-Ke Shih const struct rtw89_dle_size *ple) 1561e3ec7017SPing-Ke Shih { 1562e3ec7017SPing-Ke Shih return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1563e3ec7017SPing-Ke Shih ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1564e3ec7017SPing-Ke Shih } 1565e3ec7017SPing-Ke Shih 15665f8c35b9SPing-Ke Shih static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 15675f8c35b9SPing-Ke Shih enum rtw89_qta_mode mode) 15685f8c35b9SPing-Ke Shih { 15695f8c35b9SPing-Ke Shih u32 size = rtwdev->chip->fifo_size; 15705f8c35b9SPing-Ke Shih 15715f8c35b9SPing-Ke Shih if (mode == RTW89_QTA_SCC) 15725f8c35b9SPing-Ke Shih size -= rtwdev->chip->dle_scc_rsvd_size; 15735f8c35b9SPing-Ke Shih 15745f8c35b9SPing-Ke Shih return size; 15755f8c35b9SPing-Ke Shih } 15765f8c35b9SPing-Ke Shih 1577e3ec7017SPing-Ke Shih static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1578e3ec7017SPing-Ke Shih { 1579e3ec7017SPing-Ke Shih if (enable) 1580e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1581e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1582e3ec7017SPing-Ke Shih else 1583e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1584e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1585e3ec7017SPing-Ke Shih } 1586e3ec7017SPing-Ke Shih 1587e3ec7017SPing-Ke Shih static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1588e3ec7017SPing-Ke Shih { 15895c3afcbaSPing-Ke Shih u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 15905c3afcbaSPing-Ke Shih 15915c3afcbaSPing-Ke Shih if (enable) { 15925c3afcbaSPing-Ke Shih if (rtwdev->chip->chip_id == RTL8851B) 15935c3afcbaSPing-Ke Shih val |= B_AX_AXIDMA_CLK_EN; 15945c3afcbaSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 15955c3afcbaSPing-Ke Shih } else { 15965c3afcbaSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 15975c3afcbaSPing-Ke Shih } 1598e3ec7017SPing-Ke Shih } 1599e3ec7017SPing-Ke Shih 1600e3ec7017SPing-Ke Shih static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1601e3ec7017SPing-Ke Shih { 1602e3ec7017SPing-Ke Shih const struct rtw89_dle_size *size_cfg; 1603e3ec7017SPing-Ke Shih u32 val; 1604e3ec7017SPing-Ke Shih u8 bound = 0; 1605e3ec7017SPing-Ke Shih 1606e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1607e3ec7017SPing-Ke Shih size_cfg = cfg->wde_size; 1608e3ec7017SPing-Ke Shih 1609e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1610e3ec7017SPing-Ke Shih default: 1611e3ec7017SPing-Ke Shih case RTW89_WDE_PG_64: 1612e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1613e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1614e3ec7017SPing-Ke Shih break; 1615e3ec7017SPing-Ke Shih case RTW89_WDE_PG_128: 1616e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1617e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1618e3ec7017SPing-Ke Shih break; 1619e3ec7017SPing-Ke Shih case RTW89_WDE_PG_256: 1620e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1621e3ec7017SPing-Ke Shih return -EINVAL; 1622e3ec7017SPing-Ke Shih } 1623e3ec7017SPing-Ke Shih 1624e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1625e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1626e3ec7017SPing-Ke Shih B_AX_WDE_FREE_PAGE_NUM_MASK); 1627e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1628e3ec7017SPing-Ke Shih 1629e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1630e3ec7017SPing-Ke Shih bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1631e3ec7017SPing-Ke Shih * size_cfg->pge_size / DLE_BOUND_UNIT; 1632e3ec7017SPing-Ke Shih size_cfg = cfg->ple_size; 1633e3ec7017SPing-Ke Shih 1634e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1635e3ec7017SPing-Ke Shih default: 1636e3ec7017SPing-Ke Shih case RTW89_PLE_PG_64: 1637e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1638e3ec7017SPing-Ke Shih return -EINVAL; 1639e3ec7017SPing-Ke Shih case RTW89_PLE_PG_128: 1640e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1641e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1642e3ec7017SPing-Ke Shih break; 1643e3ec7017SPing-Ke Shih case RTW89_PLE_PG_256: 1644e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1645e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1646e3ec7017SPing-Ke Shih break; 1647e3ec7017SPing-Ke Shih } 1648e3ec7017SPing-Ke Shih 1649e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1650e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1651e3ec7017SPing-Ke Shih B_AX_PLE_FREE_PAGE_NUM_MASK); 1652e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1653e3ec7017SPing-Ke Shih 1654e3ec7017SPing-Ke Shih return 0; 1655e3ec7017SPing-Ke Shih } 1656e3ec7017SPing-Ke Shih 1657e3ec7017SPing-Ke Shih #define INVALID_QT_WCPU U16_MAX 1658e3ec7017SPing-Ke Shih #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1659e3ec7017SPing-Ke Shih do { \ 1660525c06c8SPing-Ke Shih val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1661525c06c8SPing-Ke Shih u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1662e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, \ 1663e3ec7017SPing-Ke Shih R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1664e3ec7017SPing-Ke Shih val); \ 1665e3ec7017SPing-Ke Shih } while (0) 1666e3ec7017SPing-Ke Shih #define SET_QUOTA(_x, _module, _idx) \ 1667e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1668e3ec7017SPing-Ke Shih 1669e3ec7017SPing-Ke Shih static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1670e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *min_cfg, 1671e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *max_cfg, 1672e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 1673e3ec7017SPing-Ke Shih { 1674e3ec7017SPing-Ke Shih u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1675e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu : min_cfg->wcpu; 1676e3ec7017SPing-Ke Shih u32 val; 1677e3ec7017SPing-Ke Shih 1678e3ec7017SPing-Ke Shih SET_QUOTA(hif, WDE, 0); 1679e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1680e3ec7017SPing-Ke Shih SET_QUOTA(pkt_in, WDE, 3); 1681e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, WDE, 4); 1682e3ec7017SPing-Ke Shih } 1683e3ec7017SPing-Ke Shih 1684e3ec7017SPing-Ke Shih static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1685e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *min_cfg, 1686e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *max_cfg) 1687e3ec7017SPing-Ke Shih { 1688e3ec7017SPing-Ke Shih u32 val; 1689e3ec7017SPing-Ke Shih 1690e3ec7017SPing-Ke Shih SET_QUOTA(cma0_tx, PLE, 0); 1691e3ec7017SPing-Ke Shih SET_QUOTA(cma1_tx, PLE, 1); 1692e3ec7017SPing-Ke Shih SET_QUOTA(c2h, PLE, 2); 1693e3ec7017SPing-Ke Shih SET_QUOTA(h2c, PLE, 3); 1694e3ec7017SPing-Ke Shih SET_QUOTA(wcpu, PLE, 4); 1695e3ec7017SPing-Ke Shih SET_QUOTA(mpdu_proc, PLE, 5); 1696e3ec7017SPing-Ke Shih SET_QUOTA(cma0_dma, PLE, 6); 1697e3ec7017SPing-Ke Shih SET_QUOTA(cma1_dma, PLE, 7); 1698e3ec7017SPing-Ke Shih SET_QUOTA(bb_rpt, PLE, 8); 1699e3ec7017SPing-Ke Shih SET_QUOTA(wd_rel, PLE, 9); 1700e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, PLE, 10); 170179d099e0SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852C) 170279d099e0SPing-Ke Shih SET_QUOTA(tx_rpt, PLE, 11); 1703e3ec7017SPing-Ke Shih } 1704e3ec7017SPing-Ke Shih 17057a68ec3dSChih-Kang Chang int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 17067a68ec3dSChih-Kang Chang { 17077a68ec3dSChih-Kang Chang const struct rtw89_ple_quota *min_cfg, *max_cfg; 17087a68ec3dSChih-Kang Chang const struct rtw89_dle_mem *cfg; 17097a68ec3dSChih-Kang Chang u32 val; 17107a68ec3dSChih-Kang Chang 17117a68ec3dSChih-Kang Chang if (rtwdev->chip->chip_id == RTL8852C) 17127a68ec3dSChih-Kang Chang return 0; 17137a68ec3dSChih-Kang Chang 17147a68ec3dSChih-Kang Chang if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 17157a68ec3dSChih-Kang Chang rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 17167a68ec3dSChih-Kang Chang return -EINVAL; 17177a68ec3dSChih-Kang Chang } 17187a68ec3dSChih-Kang Chang 17197a68ec3dSChih-Kang Chang if (wow) 17207a68ec3dSChih-Kang Chang cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 17217a68ec3dSChih-Kang Chang else 17227a68ec3dSChih-Kang Chang cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 17237a68ec3dSChih-Kang Chang if (!cfg) { 17247a68ec3dSChih-Kang Chang rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 17257a68ec3dSChih-Kang Chang return -EINVAL; 17267a68ec3dSChih-Kang Chang } 17277a68ec3dSChih-Kang Chang 17287a68ec3dSChih-Kang Chang min_cfg = cfg->ple_min_qt; 17297a68ec3dSChih-Kang Chang max_cfg = cfg->ple_max_qt; 17307a68ec3dSChih-Kang Chang SET_QUOTA(cma0_dma, PLE, 6); 17317a68ec3dSChih-Kang Chang SET_QUOTA(cma1_dma, PLE, 7); 17327a68ec3dSChih-Kang Chang 17337a68ec3dSChih-Kang Chang return 0; 17347a68ec3dSChih-Kang Chang } 1735e3ec7017SPing-Ke Shih #undef SET_QUOTA 1736e3ec7017SPing-Ke Shih 173719e28c7fSChin-Yen Lee void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 173819e28c7fSChin-Yen Lee { 173919e28c7fSChin-Yen Lee u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 174019e28c7fSChin-Yen Lee 174119e28c7fSChin-Yen Lee if (enable) 174219e28c7fSChin-Yen Lee rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 174319e28c7fSChin-Yen Lee else 174419e28c7fSChin-Yen Lee rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 174519e28c7fSChin-Yen Lee } 174619e28c7fSChin-Yen Lee 1747e3ec7017SPing-Ke Shih static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1748e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, 1749e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 1750e3ec7017SPing-Ke Shih { 1751e3ec7017SPing-Ke Shih wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1752e3ec7017SPing-Ke Shih ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1753e3ec7017SPing-Ke Shih } 1754e3ec7017SPing-Ke Shih 1755e3ec7017SPing-Ke Shih static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1756e3ec7017SPing-Ke Shih enum rtw89_qta_mode ext_mode) 1757e3ec7017SPing-Ke Shih { 1758e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, *ext_cfg; 1759e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1760e3ec7017SPing-Ke Shih int ret = 0; 1761e3ec7017SPing-Ke Shih u32 ini; 1762e3ec7017SPing-Ke Shih 1763e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1764e3ec7017SPing-Ke Shih if (ret) 1765e3ec7017SPing-Ke Shih return ret; 1766e3ec7017SPing-Ke Shih 1767e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 1768e3ec7017SPing-Ke Shih if (!cfg) { 1769e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1770e3ec7017SPing-Ke Shih ret = -EINVAL; 1771e3ec7017SPing-Ke Shih goto error; 1772e3ec7017SPing-Ke Shih } 1773e3ec7017SPing-Ke Shih 1774e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_DLFW) { 1775e3ec7017SPing-Ke Shih ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1776e3ec7017SPing-Ke Shih if (!ext_cfg) { 1777e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1778e3ec7017SPing-Ke Shih ext_mode); 1779e3ec7017SPing-Ke Shih ret = -EINVAL; 1780e3ec7017SPing-Ke Shih goto error; 1781e3ec7017SPing-Ke Shih } 1782e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1783e3ec7017SPing-Ke Shih } 1784e3ec7017SPing-Ke Shih 17855f8c35b9SPing-Ke Shih if (dle_used_size(cfg->wde_size, cfg->ple_size) != 17865f8c35b9SPing-Ke Shih dle_expected_used_size(rtwdev, mode)) { 1787e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1788e3ec7017SPing-Ke Shih ret = -EINVAL; 1789e3ec7017SPing-Ke Shih goto error; 1790e3ec7017SPing-Ke Shih } 1791e3ec7017SPing-Ke Shih 1792e3ec7017SPing-Ke Shih dle_func_en(rtwdev, false); 1793e3ec7017SPing-Ke Shih dle_clk_en(rtwdev, true); 1794e3ec7017SPing-Ke Shih 1795e3ec7017SPing-Ke Shih ret = dle_mix_cfg(rtwdev, cfg); 1796e3ec7017SPing-Ke Shih if (ret) { 1797e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1798e3ec7017SPing-Ke Shih goto error; 1799e3ec7017SPing-Ke Shih } 1800e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1801e3ec7017SPing-Ke Shih 1802e3ec7017SPing-Ke Shih dle_func_en(rtwdev, true); 1803e3ec7017SPing-Ke Shih 1804e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, ini, 1805e3ec7017SPing-Ke Shih (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1806e3ec7017SPing-Ke Shih 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1807e3ec7017SPing-Ke Shih if (ret) { 1808e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1809e3ec7017SPing-Ke Shih return ret; 1810e3ec7017SPing-Ke Shih } 1811e3ec7017SPing-Ke Shih 1812e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, ini, 1813e3ec7017SPing-Ke Shih (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1814e3ec7017SPing-Ke Shih 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1815e3ec7017SPing-Ke Shih if (ret) { 1816e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1817e3ec7017SPing-Ke Shih return ret; 1818e3ec7017SPing-Ke Shih } 1819e3ec7017SPing-Ke Shih 1820e3ec7017SPing-Ke Shih return 0; 1821e3ec7017SPing-Ke Shih error: 1822e3ec7017SPing-Ke Shih dle_func_en(rtwdev, false); 1823e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1824e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1825e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1826e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1827e3ec7017SPing-Ke Shih 1828e3ec7017SPing-Ke Shih return ret; 1829e3ec7017SPing-Ke Shih } 1830e3ec7017SPing-Ke Shih 1831e07a9968SPing-Ke Shih static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1832e07a9968SPing-Ke Shih enum rtw89_qta_mode mode) 1833e07a9968SPing-Ke Shih { 1834e07a9968SPing-Ke Shih u32 reg, max_preld_size, min_rsvd_size; 1835e07a9968SPing-Ke Shih 1836e07a9968SPing-Ke Shih max_preld_size = (mac_idx == RTW89_MAC_0 ? 1837e07a9968SPing-Ke Shih PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1838e07a9968SPing-Ke Shih reg = mac_idx == RTW89_MAC_0 ? 1839e07a9968SPing-Ke Shih R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1840e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1841e07a9968SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1842e07a9968SPing-Ke Shih 1843e07a9968SPing-Ke Shih min_rsvd_size = PRELD_AMSDU_SIZE; 1844e07a9968SPing-Ke Shih reg = mac_idx == RTW89_MAC_0 ? 1845e07a9968SPing-Ke Shih R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1846e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1847e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1848e07a9968SPing-Ke Shih 1849e07a9968SPing-Ke Shih return 0; 1850e07a9968SPing-Ke Shih } 1851e07a9968SPing-Ke Shih 1852e07a9968SPing-Ke Shih static bool is_qta_poh(struct rtw89_dev *rtwdev) 1853e07a9968SPing-Ke Shih { 1854e07a9968SPing-Ke Shih return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1855e07a9968SPing-Ke Shih } 1856e07a9968SPing-Ke Shih 1857e07a9968SPing-Ke Shih static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1858e07a9968SPing-Ke Shih enum rtw89_qta_mode mode) 1859e07a9968SPing-Ke Shih { 1860e07a9968SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1861e07a9968SPing-Ke Shih 18625c3afcbaSPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 18635c3afcbaSPing-Ke Shih chip->chip_id == RTL8851B || !is_qta_poh(rtwdev)) 1864e07a9968SPing-Ke Shih return 0; 1865e07a9968SPing-Ke Shih 1866e07a9968SPing-Ke Shih return preload_init_set(rtwdev, mac_idx, mode); 1867e07a9968SPing-Ke Shih } 1868e07a9968SPing-Ke Shih 1869e3ec7017SPing-Ke Shih static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1870e3ec7017SPing-Ke Shih { 1871e3ec7017SPing-Ke Shih u32 msk32; 1872e3ec7017SPing-Ke Shih u32 val32; 1873e3ec7017SPing-Ke Shih 1874e3ec7017SPing-Ke Shih msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1875e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1876e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1877e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1878e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1879e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1880e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1881e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1882e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1883e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1884e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1885e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1886e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1887e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1888e3ec7017SPing-Ke Shih 1889e3ec7017SPing-Ke Shih if ((val32 & msk32) == msk32) 1890e3ec7017SPing-Ke Shih return true; 1891e3ec7017SPing-Ke Shih 1892e3ec7017SPing-Ke Shih return false; 1893e3ec7017SPing-Ke Shih } 1894e3ec7017SPing-Ke Shih 1895cf7b8b80SPing-Ke Shih static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 1896cf7b8b80SPing-Ke Shih { 1897cf7b8b80SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1898cf7b8b80SPing-Ke Shih 18995c3afcbaSPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 19005c3afcbaSPing-Ke Shih chip->chip_id == RTL8851B) 1901cf7b8b80SPing-Ke Shih return; 1902cf7b8b80SPing-Ke Shih 1903cf7b8b80SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 1904cf7b8b80SPing-Ke Shih SS2F_PATH_WLCPU); 1905cf7b8b80SPing-Ke Shih } 1906cf7b8b80SPing-Ke Shih 1907e3ec7017SPing-Ke Shih static int sta_sch_init(struct rtw89_dev *rtwdev) 1908e3ec7017SPing-Ke Shih { 1909e3ec7017SPing-Ke Shih u32 p_val; 1910e3ec7017SPing-Ke Shih u8 val; 1911e3ec7017SPing-Ke Shih int ret; 1912e3ec7017SPing-Ke Shih 1913e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1914e3ec7017SPing-Ke Shih if (ret) 1915e3ec7017SPing-Ke Shih return ret; 1916e3ec7017SPing-Ke Shih 1917e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1918e3ec7017SPing-Ke Shih val |= B_AX_SS_EN; 1919e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1920e3ec7017SPing-Ke Shih 1921e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1922e3ec7017SPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1923e3ec7017SPing-Ke Shih if (ret) { 1924e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1925e3ec7017SPing-Ke Shih return ret; 1926e3ec7017SPing-Ke Shih } 1927e3ec7017SPing-Ke Shih 19289a1ab283SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 19299a1ab283SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 1930cf7b8b80SPing-Ke Shih 1931cf7b8b80SPing-Ke Shih _patch_ss2f_path(rtwdev); 1932e3ec7017SPing-Ke Shih 1933e3ec7017SPing-Ke Shih return 0; 1934e3ec7017SPing-Ke Shih } 1935e3ec7017SPing-Ke Shih 1936e3ec7017SPing-Ke Shih static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1937e3ec7017SPing-Ke Shih { 1938e3ec7017SPing-Ke Shih int ret; 1939e3ec7017SPing-Ke Shih 1940e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1941e3ec7017SPing-Ke Shih if (ret) 1942e3ec7017SPing-Ke Shih return ret; 1943e3ec7017SPing-Ke Shih 1944e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1945e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1946e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1947e3ec7017SPing-Ke Shih B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1948e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1949e3ec7017SPing-Ke Shih 1950e3ec7017SPing-Ke Shih return 0; 1951e3ec7017SPing-Ke Shih } 1952e3ec7017SPing-Ke Shih 1953e3ec7017SPing-Ke Shih static int sec_eng_init(struct rtw89_dev *rtwdev) 1954e3ec7017SPing-Ke Shih { 1955b61adeedSPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1956e3ec7017SPing-Ke Shih u32 val = 0; 1957e3ec7017SPing-Ke Shih int ret; 1958e3ec7017SPing-Ke Shih 1959e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1960e3ec7017SPing-Ke Shih if (ret) 1961e3ec7017SPing-Ke Shih return ret; 1962e3ec7017SPing-Ke Shih 1963e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 1964e3ec7017SPing-Ke Shih /* init clock */ 1965e3ec7017SPing-Ke Shih val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 1966e3ec7017SPing-Ke Shih /* init TX encryption */ 1967e3ec7017SPing-Ke Shih val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 1968e3ec7017SPing-Ke Shih val |= (B_AX_MC_DEC | B_AX_BC_DEC); 19695c3afcbaSPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 19705c3afcbaSPing-Ke Shih chip->chip_id == RTL8851B) 1971e3ec7017SPing-Ke Shih val &= ~B_AX_TX_PARTIAL_MODE; 1972e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 1973e3ec7017SPing-Ke Shih 1974e3ec7017SPing-Ke Shih /* init MIC ICV append */ 1975e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 1976e3ec7017SPing-Ke Shih val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 1977e3ec7017SPing-Ke Shih 1978e3ec7017SPing-Ke Shih /* option init */ 1979e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 1980e3ec7017SPing-Ke Shih 1981b61adeedSPing-Ke Shih if (chip->chip_id == RTL8852C) 1982b61adeedSPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 1983b61adeedSPing-Ke Shih B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 1984b61adeedSPing-Ke Shih 1985e3ec7017SPing-Ke Shih return 0; 1986e3ec7017SPing-Ke Shih } 1987e3ec7017SPing-Ke Shih 1988e3ec7017SPing-Ke Shih static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1989e3ec7017SPing-Ke Shih { 1990e3ec7017SPing-Ke Shih int ret; 1991e3ec7017SPing-Ke Shih 1992e3ec7017SPing-Ke Shih ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 1993e3ec7017SPing-Ke Shih if (ret) { 1994e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 1995e3ec7017SPing-Ke Shih return ret; 1996e3ec7017SPing-Ke Shih } 1997e3ec7017SPing-Ke Shih 1998e07a9968SPing-Ke Shih ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 1999e07a9968SPing-Ke Shih if (ret) { 2000e07a9968SPing-Ke Shih rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2001e07a9968SPing-Ke Shih return ret; 2002e07a9968SPing-Ke Shih } 2003e07a9968SPing-Ke Shih 2004e3ec7017SPing-Ke Shih ret = hfc_init(rtwdev, true, true, true); 2005e3ec7017SPing-Ke Shih if (ret) { 2006e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2007e3ec7017SPing-Ke Shih return ret; 2008e3ec7017SPing-Ke Shih } 2009e3ec7017SPing-Ke Shih 2010e3ec7017SPing-Ke Shih ret = sta_sch_init(rtwdev); 2011e3ec7017SPing-Ke Shih if (ret) { 2012e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2013e3ec7017SPing-Ke Shih return ret; 2014e3ec7017SPing-Ke Shih } 2015e3ec7017SPing-Ke Shih 2016e3ec7017SPing-Ke Shih ret = mpdu_proc_init(rtwdev); 2017e3ec7017SPing-Ke Shih if (ret) { 2018e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2019e3ec7017SPing-Ke Shih return ret; 2020e3ec7017SPing-Ke Shih } 2021e3ec7017SPing-Ke Shih 2022e3ec7017SPing-Ke Shih ret = sec_eng_init(rtwdev); 2023e3ec7017SPing-Ke Shih if (ret) { 2024e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2025e3ec7017SPing-Ke Shih return ret; 2026e3ec7017SPing-Ke Shih } 2027e3ec7017SPing-Ke Shih 2028e3ec7017SPing-Ke Shih return ret; 2029e3ec7017SPing-Ke Shih } 2030e3ec7017SPing-Ke Shih 2031e3ec7017SPing-Ke Shih static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2032e3ec7017SPing-Ke Shih { 2033e3ec7017SPing-Ke Shih u32 val, reg; 2034e3ec7017SPing-Ke Shih u16 p_val; 2035e3ec7017SPing-Ke Shih int ret; 2036e3ec7017SPing-Ke Shih 2037e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2038e3ec7017SPing-Ke Shih if (ret) 2039e3ec7017SPing-Ke Shih return ret; 2040e3ec7017SPing-Ke Shih 2041e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); 2042e3ec7017SPing-Ke Shih 2043e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2044e3ec7017SPing-Ke Shih val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2045e3ec7017SPing-Ke Shih B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2046e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2047e3ec7017SPing-Ke Shih 2048e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2049ad275d0aSPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2050e3ec7017SPing-Ke Shih if (ret) { 2051e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2052e3ec7017SPing-Ke Shih return ret; 2053e3ec7017SPing-Ke Shih } 2054e3ec7017SPing-Ke Shih 2055e3ec7017SPing-Ke Shih return 0; 2056e3ec7017SPing-Ke Shih } 2057e3ec7017SPing-Ke Shih 2058e3ec7017SPing-Ke Shih static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2059e3ec7017SPing-Ke Shih { 2060e3ec7017SPing-Ke Shih u32 ret; 2061e3ec7017SPing-Ke Shih u32 reg; 206260b2ede9SChia-Yuan Li u32 val; 2063e3ec7017SPing-Ke Shih 2064e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2065e3ec7017SPing-Ke Shih if (ret) 2066e3ec7017SPing-Ke Shih return ret; 2067e3ec7017SPing-Ke Shih 2068c49154ffSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx); 2069ee546904SChia-Yuan Li if (rtwdev->chip->chip_id == RTL8852C) 2070ee546904SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2071ee546904SChia-Yuan Li SIFS_MACTXEN_T1_V1); 2072ee546904SChia-Yuan Li else 2073ee546904SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2074ee546904SChia-Yuan Li SIFS_MACTXEN_T1); 2075c49154ffSPing-Ke Shih 20765c3afcbaSPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) { 2077c49154ffSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx); 2078c49154ffSPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2079c49154ffSPing-Ke Shih } 2080c49154ffSPing-Ke Shih 2081c49154ffSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx); 2082c49154ffSPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2083c49154ffSPing-Ke Shih 2084e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); 208560b2ede9SChia-Yuan Li if (rtwdev->chip->chip_id == RTL8852C) { 208660b2ede9SChia-Yuan Li val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 208760b2ede9SChia-Yuan Li B_AX_TX_PARTIAL_MODE); 208860b2ede9SChia-Yuan Li if (!val) 208960b2ede9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 209060b2ede9SChia-Yuan Li SCH_PREBKF_24US); 209160b2ede9SChia-Yuan Li } else { 209260b2ede9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 209360b2ede9SChia-Yuan Li SCH_PREBKF_24US); 209460b2ede9SChia-Yuan Li } 2095e3ec7017SPing-Ke Shih 2096e3ec7017SPing-Ke Shih return 0; 2097e3ec7017SPing-Ke Shih } 2098e3ec7017SPing-Ke Shih 209919e28c7fSChin-Yen Lee int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 2100e3ec7017SPing-Ke Shih enum rtw89_machdr_frame_type type, 2101e3ec7017SPing-Ke Shih enum rtw89_mac_fwd_target fwd_target, 2102e3ec7017SPing-Ke Shih u8 mac_idx) 2103e3ec7017SPing-Ke Shih { 2104e3ec7017SPing-Ke Shih u32 reg; 2105e3ec7017SPing-Ke Shih u32 val; 2106e3ec7017SPing-Ke Shih 2107e3ec7017SPing-Ke Shih switch (fwd_target) { 2108e3ec7017SPing-Ke Shih case RTW89_FWD_DONT_CARE: 2109e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_DROP; 2110e3ec7017SPing-Ke Shih break; 2111e3ec7017SPing-Ke Shih case RTW89_FWD_TO_HOST: 2112e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_HOST; 2113e3ec7017SPing-Ke Shih break; 2114e3ec7017SPing-Ke Shih case RTW89_FWD_TO_WLAN_CPU: 2115e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_WLCPU; 2116e3ec7017SPing-Ke Shih break; 2117e3ec7017SPing-Ke Shih default: 2118e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2119e3ec7017SPing-Ke Shih return -EINVAL; 2120e3ec7017SPing-Ke Shih } 2121e3ec7017SPing-Ke Shih 2122e3ec7017SPing-Ke Shih switch (type) { 2123e3ec7017SPing-Ke Shih case RTW89_MGNT: 2124e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); 2125e3ec7017SPing-Ke Shih break; 2126e3ec7017SPing-Ke Shih case RTW89_CTRL: 2127e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); 2128e3ec7017SPing-Ke Shih break; 2129e3ec7017SPing-Ke Shih case RTW89_DATA: 2130e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); 2131e3ec7017SPing-Ke Shih break; 2132e3ec7017SPing-Ke Shih default: 2133e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2134e3ec7017SPing-Ke Shih return -EINVAL; 2135e3ec7017SPing-Ke Shih } 2136e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2137e3ec7017SPing-Ke Shih 2138e3ec7017SPing-Ke Shih return 0; 2139e3ec7017SPing-Ke Shih } 2140e3ec7017SPing-Ke Shih 2141e3ec7017SPing-Ke Shih static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2142e3ec7017SPing-Ke Shih { 2143e3ec7017SPing-Ke Shih int ret, i; 2144e3ec7017SPing-Ke Shih u32 mac_ftlr, plcp_ftlr; 2145e3ec7017SPing-Ke Shih 2146e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2147e3ec7017SPing-Ke Shih if (ret) 2148e3ec7017SPing-Ke Shih return ret; 2149e3ec7017SPing-Ke Shih 2150e3ec7017SPing-Ke Shih for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2151e3ec7017SPing-Ke Shih ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 2152e3ec7017SPing-Ke Shih mac_idx); 2153e3ec7017SPing-Ke Shih if (ret) 2154e3ec7017SPing-Ke Shih return ret; 2155e3ec7017SPing-Ke Shih } 2156e3ec7017SPing-Ke Shih mac_ftlr = rtwdev->hal.rx_fltr; 2157e3ec7017SPing-Ke Shih plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2158e3ec7017SPing-Ke Shih B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2159e3ec7017SPing-Ke Shih B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2160e3ec7017SPing-Ke Shih B_AX_HE_SIGB_CRC_CHK; 2161e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), 2162e3ec7017SPing-Ke Shih mac_ftlr); 2163e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), 2164e3ec7017SPing-Ke Shih plcp_ftlr); 2165e3ec7017SPing-Ke Shih 2166e3ec7017SPing-Ke Shih return 0; 2167e3ec7017SPing-Ke Shih } 2168e3ec7017SPing-Ke Shih 2169e3ec7017SPing-Ke Shih static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2170e3ec7017SPing-Ke Shih { 2171e3ec7017SPing-Ke Shih u32 reg, val32; 2172e3ec7017SPing-Ke Shih u32 b_rsp_chk_nav, b_rsp_chk_cca; 2173e3ec7017SPing-Ke Shih 2174e3ec7017SPing-Ke Shih b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2175e3ec7017SPing-Ke Shih B_AX_RSP_CHK_BASIC_NAV; 2176e3ec7017SPing-Ke Shih b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2177e3ec7017SPing-Ke Shih B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2178e3ec7017SPing-Ke Shih B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2179e3ec7017SPing-Ke Shih 2180e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 2181e3ec7017SPing-Ke Shih case RTL8852A: 2182e3ec7017SPing-Ke Shih case RTL8852B: 2183e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2184e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2185e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2186e3ec7017SPing-Ke Shih 2187e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2188e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2189e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2190e3ec7017SPing-Ke Shih break; 2191e3ec7017SPing-Ke Shih default: 2192e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2193e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2194e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2195e3ec7017SPing-Ke Shih 2196e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2197e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2198e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2199e3ec7017SPing-Ke Shih break; 2200e3ec7017SPing-Ke Shih } 2201e3ec7017SPing-Ke Shih } 2202e3ec7017SPing-Ke Shih 2203e3ec7017SPing-Ke Shih static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2204e3ec7017SPing-Ke Shih { 2205e3ec7017SPing-Ke Shih u32 val, reg; 2206e3ec7017SPing-Ke Shih int ret; 2207e3ec7017SPing-Ke Shih 2208e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2209e3ec7017SPing-Ke Shih if (ret) 2210e3ec7017SPing-Ke Shih return ret; 2211e3ec7017SPing-Ke Shih 2212e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); 2213e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2214e3ec7017SPing-Ke Shih val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2215e3ec7017SPing-Ke Shih B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2216e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2217e3ec7017SPing-Ke Shih B_AX_CTN_CHK_INTRA_NAV | 2218e3ec7017SPing-Ke Shih B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2219e3ec7017SPing-Ke Shih B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2220e3ec7017SPing-Ke Shih B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 222198ed6159SPing-Ke Shih B_AX_CTN_CHK_CCA_P20); 2222e3ec7017SPing-Ke Shih val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2223e3ec7017SPing-Ke Shih B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2224e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 222598ed6159SPing-Ke Shih B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 222698ed6159SPing-Ke Shih B_AX_SIFS_CHK_EDCCA); 2227e3ec7017SPing-Ke Shih 2228e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2229e3ec7017SPing-Ke Shih 2230e3ec7017SPing-Ke Shih _patch_dis_resp_chk(rtwdev, mac_idx); 2231e3ec7017SPing-Ke Shih 2232e3ec7017SPing-Ke Shih return 0; 2233e3ec7017SPing-Ke Shih } 2234e3ec7017SPing-Ke Shih 223519cb9427SPing-Ke Shih static int nav_ctrl_init(struct rtw89_dev *rtwdev) 223619cb9427SPing-Ke Shih { 223719cb9427SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 223819cb9427SPing-Ke Shih B_AX_WMAC_TF_UP_NAV_EN | 223919cb9427SPing-Ke Shih B_AX_WMAC_NAV_UPPER_EN); 2240c060dc51SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 224119cb9427SPing-Ke Shih 224219cb9427SPing-Ke Shih return 0; 224319cb9427SPing-Ke Shih } 224419cb9427SPing-Ke Shih 2245e3ec7017SPing-Ke Shih static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2246e3ec7017SPing-Ke Shih { 2247e3ec7017SPing-Ke Shih u32 reg; 2248e3ec7017SPing-Ke Shih int ret; 2249e3ec7017SPing-Ke Shih 2250e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2251e3ec7017SPing-Ke Shih if (ret) 2252e3ec7017SPing-Ke Shih return ret; 2253e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); 2254e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2255e3ec7017SPing-Ke Shih 2256e3ec7017SPing-Ke Shih return 0; 2257e3ec7017SPing-Ke Shih } 2258e3ec7017SPing-Ke Shih 2259e3ec7017SPing-Ke Shih static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2260e3ec7017SPing-Ke Shih { 2261e3ec7017SPing-Ke Shih u32 reg; 2262e3ec7017SPing-Ke Shih int ret; 2263e3ec7017SPing-Ke Shih 2264e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2265e3ec7017SPing-Ke Shih if (ret) 2266e3ec7017SPing-Ke Shih return ret; 2267e3ec7017SPing-Ke Shih 2268e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); 2269e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2270e3ec7017SPing-Ke Shih 227175fd91aaSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx); 227275fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 227375fd91aaSPing-Ke Shih 227475fd91aaSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx); 227575fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 227675fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 227775fd91aaSPing-Ke Shih 2278e3ec7017SPing-Ke Shih return 0; 2279e3ec7017SPing-Ke Shih } 2280e3ec7017SPing-Ke Shih 2281e3ec7017SPing-Ke Shih static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2282e3ec7017SPing-Ke Shih { 22839ef9edb9SChia-Yuan Li const struct rtw89_chip_info *chip = rtwdev->chip; 22849ef9edb9SChia-Yuan Li const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2285e3ec7017SPing-Ke Shih u32 reg, val, sifs; 2286e3ec7017SPing-Ke Shih int ret; 2287e3ec7017SPing-Ke Shih 2288e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2289e3ec7017SPing-Ke Shih if (ret) 2290e3ec7017SPing-Ke Shih return ret; 2291e3ec7017SPing-Ke Shih 2292e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2293e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2294e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2295e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2296e3ec7017SPing-Ke Shih 2297e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 2298e3ec7017SPing-Ke Shih case RTL8852A: 2299e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52A; 2300e3ec7017SPing-Ke Shih break; 2301e3ec7017SPing-Ke Shih case RTL8852B: 2302e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52B; 2303e3ec7017SPing-Ke Shih break; 2304e3ec7017SPing-Ke Shih default: 2305e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52C; 2306e3ec7017SPing-Ke Shih break; 2307e3ec7017SPing-Ke Shih } 2308e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2309e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2310e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2311e3ec7017SPing-Ke Shih 2312e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); 2313e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2314e3ec7017SPing-Ke Shih 23159ef9edb9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx); 23169ef9edb9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 23179ef9edb9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx); 23189ef9edb9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 23199ef9edb9SChia-Yuan Li 2320e3ec7017SPing-Ke Shih return 0; 2321e3ec7017SPing-Ke Shih } 2322e3ec7017SPing-Ke Shih 232318175197SPing-Ke Shih static void rst_bacam(struct rtw89_dev *rtwdev) 232418175197SPing-Ke Shih { 232518175197SPing-Ke Shih u32 val32; 232618175197SPing-Ke Shih int ret; 232718175197SPing-Ke Shih 232818175197SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 232918175197SPing-Ke Shih S_AX_BACAM_RST_ALL); 233018175197SPing-Ke Shih 233118175197SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 233218175197SPing-Ke Shih 1, 1000, false, 233318175197SPing-Ke Shih rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 233418175197SPing-Ke Shih if (ret) 233518175197SPing-Ke Shih rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 233618175197SPing-Ke Shih } 233718175197SPing-Ke Shih 2338e3ec7017SPing-Ke Shih static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2339e3ec7017SPing-Ke Shih { 2340e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_CCA_TO 32 2341e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_DATA_TO 15 2342e3ec7017SPing-Ke Shih #define RX_MAX_LEN_UNIT 512 2343e3ec7017SPing-Ke Shih #define PLD_RLS_MAX_PG 127 23444b0d341bSPing-Ke Shih #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2345e3ec7017SPing-Ke Shih int ret; 2346e3ec7017SPing-Ke Shih u32 reg, rx_max_len, rx_qta; 2347e3ec7017SPing-Ke Shih u16 val; 2348e3ec7017SPing-Ke Shih 2349e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2350e3ec7017SPing-Ke Shih if (ret) 2351e3ec7017SPing-Ke Shih return ret; 2352e3ec7017SPing-Ke Shih 235318175197SPing-Ke Shih if (mac_idx == RTW89_MAC_0) 235418175197SPing-Ke Shih rst_bacam(rtwdev); 235518175197SPing-Ke Shih 2356e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); 2357e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2358e3ec7017SPing-Ke Shih 2359e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); 2360e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 2361e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2362e3ec7017SPing-Ke Shih B_AX_RX_DLK_DATA_TIME_MASK); 2363e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2364e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK); 2365e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 2366e3ec7017SPing-Ke Shih 2367e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); 2368e3ec7017SPing-Ke Shih rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2369e3ec7017SPing-Ke Shih 2370e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); 2371e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_0) 2372e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2373e3ec7017SPing-Ke Shih else 2374e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 23754b0d341bSPing-Ke Shih rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 23764b0d341bSPing-Ke Shih rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 23774b0d341bSPing-Ke Shih rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 23784b0d341bSPing-Ke Shih rx_max_len /= RX_MAX_LEN_UNIT; 2379e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2380e3ec7017SPing-Ke Shih 2381e3ec7017SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852A && 2382e3ec7017SPing-Ke Shih rtwdev->hal.cv == CHIP_CBV) { 2383e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, 2384e3ec7017SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), 2385e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK, 0); 2386e3ec7017SPing-Ke Shih rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), 2387e3ec7017SPing-Ke Shih BIT(12)); 2388e3ec7017SPing-Ke Shih } 2389e3ec7017SPing-Ke Shih 2390e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); 2391e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2392e3ec7017SPing-Ke Shih 2393e3ec7017SPing-Ke Shih return ret; 2394e3ec7017SPing-Ke Shih } 2395e3ec7017SPing-Ke Shih 2396e3ec7017SPing-Ke Shih static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2397e3ec7017SPing-Ke Shih { 23989ef9edb9SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2399e3ec7017SPing-Ke Shih u32 val, reg; 2400e3ec7017SPing-Ke Shih int ret; 2401e3ec7017SPing-Ke Shih 2402e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2403e3ec7017SPing-Ke Shih if (ret) 2404e3ec7017SPing-Ke Shih return ret; 2405e3ec7017SPing-Ke Shih 2406e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2407e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2408e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2409e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2410e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2411e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2412e3ec7017SPing-Ke Shih 24139ef9edb9SChia-Yuan Li if (chip_id == RTL8852A || chip_id == RTL8852B) { 24149ef9edb9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx); 24159ef9edb9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 24169ef9edb9SChia-Yuan Li } 24179ef9edb9SChia-Yuan Li 2418e3ec7017SPing-Ke Shih return 0; 2419e3ec7017SPing-Ke Shih } 2420e3ec7017SPing-Ke Shih 2421e3ec7017SPing-Ke Shih static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2422e3ec7017SPing-Ke Shih { 2423e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 2424e3ec7017SPing-Ke Shih 2425e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 2426e3ec7017SPing-Ke Shih if (!cfg) { 2427e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2428e3ec7017SPing-Ke Shih return false; 2429e3ec7017SPing-Ke Shih } 2430e3ec7017SPing-Ke Shih 2431e3ec7017SPing-Ke Shih return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2432e3ec7017SPing-Ke Shih } 2433e3ec7017SPing-Ke Shih 2434e3ec7017SPing-Ke Shih static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2435e3ec7017SPing-Ke Shih { 2436e3ec7017SPing-Ke Shih u32 val, reg; 2437e3ec7017SPing-Ke Shih int ret; 2438e3ec7017SPing-Ke Shih 2439e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2440e3ec7017SPing-Ke Shih if (ret) 2441e3ec7017SPing-Ke Shih return ret; 2442e3ec7017SPing-Ke Shih 2443e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2444e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2445e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2446e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2447e3ec7017SPing-Ke Shih B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 24489fb4862eSPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 24499fb4862eSPing-Ke Shih B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2450e3ec7017SPing-Ke Shih val |= B_AX_HW_CTS2SELF_EN; 2451e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2452e3ec7017SPing-Ke Shih 2453e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); 2454e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2455e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2456e3ec7017SPing-Ke Shih val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2457e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2458e3ec7017SPing-Ke Shih } 2459e3ec7017SPing-Ke Shih 24609fb4862eSPing-Ke Shih if (mac_idx == RTW89_MAC_0) { 24619fb4862eSPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 24629fb4862eSPing-Ke Shih B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 24639fb4862eSPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 24649fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_0 | 24659fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_1 | 24669fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_UL); 24679fb4862eSPing-Ke Shih rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 24689fb4862eSPing-Ke Shih B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 24699fb4862eSPing-Ke Shih } else if (mac_idx == RTW89_MAC_1) { 24709fb4862eSPing-Ke Shih rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 24719fb4862eSPing-Ke Shih B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 24729fb4862eSPing-Ke Shih } 2473e3ec7017SPing-Ke Shih 2474e3ec7017SPing-Ke Shih return 0; 2475e3ec7017SPing-Ke Shih } 2476e3ec7017SPing-Ke Shih 2477a0d99ebbSPing-Ke Shih static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2478a0d99ebbSPing-Ke Shih { 2479a0d99ebbSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2480a0d99ebbSPing-Ke Shih u32 reg; 2481a0d99ebbSPing-Ke Shih int ret; 2482a0d99ebbSPing-Ke Shih 2483a0d99ebbSPing-Ke Shih if (chip_id != RTL8852A && chip_id != RTL8852B) 2484a0d99ebbSPing-Ke Shih return 0; 2485a0d99ebbSPing-Ke Shih 2486a0d99ebbSPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2487a0d99ebbSPing-Ke Shih if (ret) 2488a0d99ebbSPing-Ke Shih return ret; 2489a0d99ebbSPing-Ke Shih 2490a0d99ebbSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RXDMA_CTRL_0, mac_idx); 2491a0d99ebbSPing-Ke Shih rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2492a0d99ebbSPing-Ke Shih 2493a0d99ebbSPing-Ke Shih return 0; 2494a0d99ebbSPing-Ke Shih } 2495a0d99ebbSPing-Ke Shih 2496e3ec7017SPing-Ke Shih static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2497e3ec7017SPing-Ke Shih { 2498e3ec7017SPing-Ke Shih int ret; 2499e3ec7017SPing-Ke Shih 2500e3ec7017SPing-Ke Shih ret = scheduler_init(rtwdev, mac_idx); 2501e3ec7017SPing-Ke Shih if (ret) { 2502e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2503e3ec7017SPing-Ke Shih return ret; 2504e3ec7017SPing-Ke Shih } 2505e3ec7017SPing-Ke Shih 2506e3ec7017SPing-Ke Shih ret = addr_cam_init(rtwdev, mac_idx); 2507e3ec7017SPing-Ke Shih if (ret) { 2508e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2509e3ec7017SPing-Ke Shih ret); 2510e3ec7017SPing-Ke Shih return ret; 2511e3ec7017SPing-Ke Shih } 2512e3ec7017SPing-Ke Shih 2513e3ec7017SPing-Ke Shih ret = rx_fltr_init(rtwdev, mac_idx); 2514e3ec7017SPing-Ke Shih if (ret) { 2515e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2516e3ec7017SPing-Ke Shih ret); 2517e3ec7017SPing-Ke Shih return ret; 2518e3ec7017SPing-Ke Shih } 2519e3ec7017SPing-Ke Shih 2520e3ec7017SPing-Ke Shih ret = cca_ctrl_init(rtwdev, mac_idx); 2521e3ec7017SPing-Ke Shih if (ret) { 2522e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2523e3ec7017SPing-Ke Shih ret); 2524e3ec7017SPing-Ke Shih return ret; 2525e3ec7017SPing-Ke Shih } 2526e3ec7017SPing-Ke Shih 252719cb9427SPing-Ke Shih ret = nav_ctrl_init(rtwdev); 252819cb9427SPing-Ke Shih if (ret) { 252919cb9427SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 253019cb9427SPing-Ke Shih ret); 253119cb9427SPing-Ke Shih return ret; 253219cb9427SPing-Ke Shih } 253319cb9427SPing-Ke Shih 2534e3ec7017SPing-Ke Shih ret = spatial_reuse_init(rtwdev, mac_idx); 2535e3ec7017SPing-Ke Shih if (ret) { 2536e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2537e3ec7017SPing-Ke Shih mac_idx, ret); 2538e3ec7017SPing-Ke Shih return ret; 2539e3ec7017SPing-Ke Shih } 2540e3ec7017SPing-Ke Shih 2541e3ec7017SPing-Ke Shih ret = tmac_init(rtwdev, mac_idx); 2542e3ec7017SPing-Ke Shih if (ret) { 2543e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2544e3ec7017SPing-Ke Shih return ret; 2545e3ec7017SPing-Ke Shih } 2546e3ec7017SPing-Ke Shih 2547e3ec7017SPing-Ke Shih ret = trxptcl_init(rtwdev, mac_idx); 2548e3ec7017SPing-Ke Shih if (ret) { 2549e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2550e3ec7017SPing-Ke Shih return ret; 2551e3ec7017SPing-Ke Shih } 2552e3ec7017SPing-Ke Shih 2553e3ec7017SPing-Ke Shih ret = rmac_init(rtwdev, mac_idx); 2554e3ec7017SPing-Ke Shih if (ret) { 2555e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2556e3ec7017SPing-Ke Shih return ret; 2557e3ec7017SPing-Ke Shih } 2558e3ec7017SPing-Ke Shih 2559e3ec7017SPing-Ke Shih ret = cmac_com_init(rtwdev, mac_idx); 2560e3ec7017SPing-Ke Shih if (ret) { 2561e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2562e3ec7017SPing-Ke Shih return ret; 2563e3ec7017SPing-Ke Shih } 2564e3ec7017SPing-Ke Shih 2565e3ec7017SPing-Ke Shih ret = ptcl_init(rtwdev, mac_idx); 2566e3ec7017SPing-Ke Shih if (ret) { 2567e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2568e3ec7017SPing-Ke Shih return ret; 2569e3ec7017SPing-Ke Shih } 2570e3ec7017SPing-Ke Shih 2571a0d99ebbSPing-Ke Shih ret = cmac_dma_init(rtwdev, mac_idx); 2572a0d99ebbSPing-Ke Shih if (ret) { 2573a0d99ebbSPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2574a0d99ebbSPing-Ke Shih return ret; 2575a0d99ebbSPing-Ke Shih } 2576a0d99ebbSPing-Ke Shih 2577e3ec7017SPing-Ke Shih return ret; 2578e3ec7017SPing-Ke Shih } 2579e3ec7017SPing-Ke Shih 2580e3ec7017SPing-Ke Shih static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2581e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info *c2h_info) 2582e3ec7017SPing-Ke Shih { 2583e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 2584e3ec7017SPing-Ke Shih u32 ret; 2585e3ec7017SPing-Ke Shih 2586e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2587e3ec7017SPing-Ke Shih h2c_info.content_len = 0; 2588e3ec7017SPing-Ke Shih 2589e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2590e3ec7017SPing-Ke Shih if (ret) 2591e3ec7017SPing-Ke Shih return ret; 2592e3ec7017SPing-Ke Shih 2593e3ec7017SPing-Ke Shih if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2594e3ec7017SPing-Ke Shih return -EINVAL; 2595e3ec7017SPing-Ke Shih 2596e3ec7017SPing-Ke Shih return 0; 2597e3ec7017SPing-Ke Shih } 2598e3ec7017SPing-Ke Shih 2599e3ec7017SPing-Ke Shih int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2600e3ec7017SPing-Ke Shih { 2601*f48453e0SPing-Ke Shih struct rtw89_efuse *efuse = &rtwdev->efuse; 2602e3ec7017SPing-Ke Shih struct rtw89_hal *hal = &rtwdev->hal; 2603e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2604e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 2605c7ad08c6SPing-Ke Shih u8 tx_nss; 2606c7ad08c6SPing-Ke Shih u8 rx_nss; 2607dc229d94SPing-Ke Shih u8 tx_ant; 2608dc229d94SPing-Ke Shih u8 rx_ant; 2609e3ec7017SPing-Ke Shih u32 ret; 2610e3ec7017SPing-Ke Shih 2611e3ec7017SPing-Ke Shih ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2612e3ec7017SPing-Ke Shih if (ret) 2613e3ec7017SPing-Ke Shih return ret; 2614e3ec7017SPing-Ke Shih 2615c7ad08c6SPing-Ke Shih tx_nss = RTW89_GET_C2H_PHYCAP_TX_NSS(c2h_info.c2hreg); 2616c7ad08c6SPing-Ke Shih rx_nss = RTW89_GET_C2H_PHYCAP_RX_NSS(c2h_info.c2hreg); 2617dc229d94SPing-Ke Shih tx_ant = RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(c2h_info.c2hreg); 2618dc229d94SPing-Ke Shih rx_ant = RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(c2h_info.c2hreg); 2619c7ad08c6SPing-Ke Shih 2620c7ad08c6SPing-Ke Shih hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2621c7ad08c6SPing-Ke Shih hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2622e3ec7017SPing-Ke Shih 2623dc229d94SPing-Ke Shih if (tx_ant == 1) 2624dc229d94SPing-Ke Shih hal->antenna_tx = RF_B; 2625dc229d94SPing-Ke Shih if (rx_ant == 1) 2626dc229d94SPing-Ke Shih hal->antenna_rx = RF_B; 2627dc229d94SPing-Ke Shih 2628dc229d94SPing-Ke Shih if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2629dc229d94SPing-Ke Shih hal->antenna_tx = RF_B; 2630dc229d94SPing-Ke Shih hal->tx_path_diversity = true; 2631dc229d94SPing-Ke Shih } 2632dc229d94SPing-Ke Shih 2633*f48453e0SPing-Ke Shih if (chip->rf_path_num == 1) { 2634*f48453e0SPing-Ke Shih hal->antenna_tx = RF_A; 2635*f48453e0SPing-Ke Shih hal->antenna_rx = RF_A; 2636*f48453e0SPing-Ke Shih if ((efuse->rfe_type % 3) == 2) 2637*f48453e0SPing-Ke Shih hal->ant_diversity = true; 2638*f48453e0SPing-Ke Shih } 2639*f48453e0SPing-Ke Shih 2640e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 2641e3ec7017SPing-Ke Shih "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2642c7ad08c6SPing-Ke Shih hal->tx_nss, tx_nss, chip->tx_nss, 2643c7ad08c6SPing-Ke Shih hal->rx_nss, rx_nss, chip->rx_nss); 2644dc229d94SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 2645dc229d94SPing-Ke Shih "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2646dc229d94SPing-Ke Shih tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2647dc229d94SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2648*f48453e0SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2649e3ec7017SPing-Ke Shih 2650e3ec7017SPing-Ke Shih return 0; 2651e3ec7017SPing-Ke Shih } 2652e3ec7017SPing-Ke Shih 2653e3ec7017SPing-Ke Shih static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2654e3ec7017SPing-Ke Shih u16 tx_en_u16, u16 mask_u16) 2655e3ec7017SPing-Ke Shih { 2656e3ec7017SPing-Ke Shih u32 ret; 2657e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 2658e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 2659e3ec7017SPing-Ke Shih struct rtw89_h2creg_sch_tx_en *h2creg = 2660e3ec7017SPing-Ke Shih (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; 2661e3ec7017SPing-Ke Shih 2662e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2663e3ec7017SPing-Ke Shih h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; 2664e3ec7017SPing-Ke Shih h2creg->tx_en = tx_en_u16; 2665e3ec7017SPing-Ke Shih h2creg->mask = mask_u16; 2666e3ec7017SPing-Ke Shih h2creg->band = band; 2667e3ec7017SPing-Ke Shih 2668e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2669e3ec7017SPing-Ke Shih if (ret) 2670e3ec7017SPing-Ke Shih return ret; 2671e3ec7017SPing-Ke Shih 2672e3ec7017SPing-Ke Shih if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2673e3ec7017SPing-Ke Shih return -EINVAL; 2674e3ec7017SPing-Ke Shih 2675e3ec7017SPing-Ke Shih return 0; 2676e3ec7017SPing-Ke Shih } 2677e3ec7017SPing-Ke Shih 2678e3ec7017SPing-Ke Shih static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2679e3ec7017SPing-Ke Shih u16 tx_en, u16 tx_en_mask) 2680e3ec7017SPing-Ke Shih { 2681e3ec7017SPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); 2682e3ec7017SPing-Ke Shih u16 val; 2683e3ec7017SPing-Ke Shih int ret; 2684e3ec7017SPing-Ke Shih 2685e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2686e3ec7017SPing-Ke Shih if (ret) 2687e3ec7017SPing-Ke Shih return ret; 2688e3ec7017SPing-Ke Shih 2689e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2690e3ec7017SPing-Ke Shih return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2691e3ec7017SPing-Ke Shih tx_en, tx_en_mask); 2692e3ec7017SPing-Ke Shih 2693e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 2694e3ec7017SPing-Ke Shih val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2695e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 2696e3ec7017SPing-Ke Shih 2697e3ec7017SPing-Ke Shih return 0; 2698e3ec7017SPing-Ke Shih } 2699e3ec7017SPing-Ke Shih 2700de7ba639SPing-Ke Shih static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2701de7ba639SPing-Ke Shih u32 tx_en, u32 tx_en_mask) 2702de7ba639SPing-Ke Shih { 2703de7ba639SPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx); 2704de7ba639SPing-Ke Shih u32 val; 2705de7ba639SPing-Ke Shih int ret; 2706de7ba639SPing-Ke Shih 2707de7ba639SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2708de7ba639SPing-Ke Shih if (ret) 2709de7ba639SPing-Ke Shih return ret; 2710de7ba639SPing-Ke Shih 2711de7ba639SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2712de7ba639SPing-Ke Shih val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2713de7ba639SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2714de7ba639SPing-Ke Shih 2715de7ba639SPing-Ke Shih return 0; 2716de7ba639SPing-Ke Shih } 2717de7ba639SPing-Ke Shih 2718e3ec7017SPing-Ke Shih int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2719d780f926SPing-Ke Shih u32 *tx_en, enum rtw89_sch_tx_sel sel) 2720e3ec7017SPing-Ke Shih { 2721e3ec7017SPing-Ke Shih int ret; 2722e3ec7017SPing-Ke Shih 2723e3ec7017SPing-Ke Shih *tx_en = rtw89_read16(rtwdev, 2724e3ec7017SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); 2725e3ec7017SPing-Ke Shih 2726e3ec7017SPing-Ke Shih switch (sel) { 2727e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_ALL: 2728de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2729de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK); 2730e3ec7017SPing-Ke Shih if (ret) 2731e3ec7017SPing-Ke Shih return ret; 2732e3ec7017SPing-Ke Shih break; 2733e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_HIQ: 2734e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2735e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_HGQ); 2736e3ec7017SPing-Ke Shih if (ret) 2737e3ec7017SPing-Ke Shih return ret; 2738e3ec7017SPing-Ke Shih break; 2739e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MG0: 2740e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2741e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_MGQ); 2742e3ec7017SPing-Ke Shih if (ret) 2743e3ec7017SPing-Ke Shih return ret; 2744e3ec7017SPing-Ke Shih break; 2745e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MACID: 2746de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2747de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK); 2748e3ec7017SPing-Ke Shih if (ret) 2749e3ec7017SPing-Ke Shih return ret; 2750e3ec7017SPing-Ke Shih break; 2751e3ec7017SPing-Ke Shih default: 2752e3ec7017SPing-Ke Shih return 0; 2753e3ec7017SPing-Ke Shih } 2754e3ec7017SPing-Ke Shih 2755e3ec7017SPing-Ke Shih return 0; 2756e3ec7017SPing-Ke Shih } 2757861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2758e3ec7017SPing-Ke Shih 2759de7ba639SPing-Ke Shih int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2760de7ba639SPing-Ke Shih u32 *tx_en, enum rtw89_sch_tx_sel sel) 2761de7ba639SPing-Ke Shih { 2762de7ba639SPing-Ke Shih int ret; 2763de7ba639SPing-Ke Shih 2764de7ba639SPing-Ke Shih *tx_en = rtw89_read32(rtwdev, 2765de7ba639SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx)); 2766de7ba639SPing-Ke Shih 2767de7ba639SPing-Ke Shih switch (sel) { 2768de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_ALL: 2769de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2770de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 2771de7ba639SPing-Ke Shih if (ret) 2772de7ba639SPing-Ke Shih return ret; 2773de7ba639SPing-Ke Shih break; 2774de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_HIQ: 2775de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2776de7ba639SPing-Ke Shih 0, B_AX_CTN_TXEN_HGQ); 2777de7ba639SPing-Ke Shih if (ret) 2778de7ba639SPing-Ke Shih return ret; 2779de7ba639SPing-Ke Shih break; 2780de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_MG0: 2781de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2782de7ba639SPing-Ke Shih 0, B_AX_CTN_TXEN_MGQ); 2783de7ba639SPing-Ke Shih if (ret) 2784de7ba639SPing-Ke Shih return ret; 2785de7ba639SPing-Ke Shih break; 2786de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_MACID: 2787de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2788de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 2789de7ba639SPing-Ke Shih if (ret) 2790de7ba639SPing-Ke Shih return ret; 2791de7ba639SPing-Ke Shih break; 2792de7ba639SPing-Ke Shih default: 2793de7ba639SPing-Ke Shih return 0; 2794de7ba639SPing-Ke Shih } 2795de7ba639SPing-Ke Shih 2796de7ba639SPing-Ke Shih return 0; 2797de7ba639SPing-Ke Shih } 2798de7ba639SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2799de7ba639SPing-Ke Shih 2800d780f926SPing-Ke Shih int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2801e3ec7017SPing-Ke Shih { 2802e3ec7017SPing-Ke Shih int ret; 2803e3ec7017SPing-Ke Shih 2804de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2805e3ec7017SPing-Ke Shih if (ret) 2806e3ec7017SPing-Ke Shih return ret; 2807e3ec7017SPing-Ke Shih 2808e3ec7017SPing-Ke Shih return 0; 2809e3ec7017SPing-Ke Shih } 2810861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2811e3ec7017SPing-Ke Shih 2812de7ba639SPing-Ke Shih int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2813de7ba639SPing-Ke Shih { 2814de7ba639SPing-Ke Shih int ret; 2815de7ba639SPing-Ke Shih 2816de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2817de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 2818de7ba639SPing-Ke Shih if (ret) 2819de7ba639SPing-Ke Shih return ret; 2820de7ba639SPing-Ke Shih 2821de7ba639SPing-Ke Shih return 0; 2822de7ba639SPing-Ke Shih } 2823de7ba639SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2824de7ba639SPing-Ke Shih 2825eaddda24SPing-Ke Shih int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 2826e3ec7017SPing-Ke Shih { 2827e3ec7017SPing-Ke Shih u32 val, reg; 2828e3ec7017SPing-Ke Shih int ret; 2829e3ec7017SPing-Ke Shih 2830e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2831e3ec7017SPing-Ke Shih val = buf_len; 2832e3ec7017SPing-Ke Shih val |= B_AX_WD_BUF_REQ_EXEC; 2833e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2834e3ec7017SPing-Ke Shih 2835e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2836e3ec7017SPing-Ke Shih 2837e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2838e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 2839e3ec7017SPing-Ke Shih if (ret) 2840eaddda24SPing-Ke Shih return ret; 2841e3ec7017SPing-Ke Shih 2842eaddda24SPing-Ke Shih *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2843eaddda24SPing-Ke Shih if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 2844eaddda24SPing-Ke Shih return -ENOENT; 2845eaddda24SPing-Ke Shih 2846eaddda24SPing-Ke Shih return 0; 2847e3ec7017SPing-Ke Shih } 2848e3ec7017SPing-Ke Shih 28498a1f6c88SZong-Zhe Yang int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 28508a1f6c88SZong-Zhe Yang struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 2851e3ec7017SPing-Ke Shih { 2852e3ec7017SPing-Ke Shih u32 val, cmd_type, reg; 2853e3ec7017SPing-Ke Shih int ret; 2854e3ec7017SPing-Ke Shih 2855e3ec7017SPing-Ke Shih cmd_type = ctrl_para->cmd_type; 2856e3ec7017SPing-Ke Shih 2857e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2858e3ec7017SPing-Ke Shih val = 0; 2859e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->start_pktid, 2860e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2861e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->end_pktid, 2862e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2863e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2864e3ec7017SPing-Ke Shih 2865e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2866e3ec7017SPing-Ke Shih val = 0; 2867e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_pid, 2868e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_PID_MASK); 2869e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_qid, 2870e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_QID_MASK); 2871e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_pid, 2872e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_PID_MASK); 2873e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_qid, 2874e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_QID_MASK); 2875e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2876e3ec7017SPing-Ke Shih 2877e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2878e3ec7017SPing-Ke Shih val = 0; 2879e3ec7017SPing-Ke Shih val = u32_replace_bits(val, cmd_type, 2880e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_CMD_TYPE_MASK); 2881e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->macid, 2882e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_MACID_MASK); 2883e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->pkt_num, 2884e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_PKTNUM_MASK); 2885e3ec7017SPing-Ke Shih val |= B_AX_WD_CPUQ_OP_EXEC; 2886e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2887e3ec7017SPing-Ke Shih 2888e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2889e3ec7017SPing-Ke Shih 2890e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2891e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 2892e3ec7017SPing-Ke Shih if (ret) 2893e3ec7017SPing-Ke Shih return ret; 2894e3ec7017SPing-Ke Shih 2895e3ec7017SPing-Ke Shih if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2896e3ec7017SPing-Ke Shih cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2897e3ec7017SPing-Ke Shih ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2898e3ec7017SPing-Ke Shih 2899e3ec7017SPing-Ke Shih return 0; 2900e3ec7017SPing-Ke Shih } 2901e3ec7017SPing-Ke Shih 2902e3ec7017SPing-Ke Shih static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2903e3ec7017SPing-Ke Shih { 2904e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 2905e3ec7017SPing-Ke Shih struct rtw89_cpuio_ctrl ctrl_para = {0}; 2906e3ec7017SPing-Ke Shih u16 pkt_id; 2907e3ec7017SPing-Ke Shih int ret; 2908e3ec7017SPing-Ke Shih 2909e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 2910e3ec7017SPing-Ke Shih if (!cfg) { 2911e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2912e3ec7017SPing-Ke Shih return -EINVAL; 2913e3ec7017SPing-Ke Shih } 2914e3ec7017SPing-Ke Shih 29155f8c35b9SPing-Ke Shih if (dle_used_size(cfg->wde_size, cfg->ple_size) != 29165f8c35b9SPing-Ke Shih dle_expected_used_size(rtwdev, mode)) { 2917e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2918e3ec7017SPing-Ke Shih return -EINVAL; 2919e3ec7017SPing-Ke Shih } 2920e3ec7017SPing-Ke Shih 2921e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2922e3ec7017SPing-Ke Shih 2923eaddda24SPing-Ke Shih ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id); 2924eaddda24SPing-Ke Shih if (ret) { 2925e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2926eaddda24SPing-Ke Shih return ret; 2927e3ec7017SPing-Ke Shih } 2928e3ec7017SPing-Ke Shih 2929e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2930e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 2931e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 2932e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 2933e3ec7017SPing-Ke Shih ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2934e3ec7017SPing-Ke Shih ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2935e3ec7017SPing-Ke Shih ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2936e3ec7017SPing-Ke Shih if (ret) { 2937e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2938e3ec7017SPing-Ke Shih return -EFAULT; 2939e3ec7017SPing-Ke Shih } 2940e3ec7017SPing-Ke Shih 2941eaddda24SPing-Ke Shih ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, false, &pkt_id); 2942eaddda24SPing-Ke Shih if (ret) { 2943e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2944eaddda24SPing-Ke Shih return ret; 2945e3ec7017SPing-Ke Shih } 2946e3ec7017SPing-Ke Shih 2947e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2948e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 2949e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 2950e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 2951e3ec7017SPing-Ke Shih ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 2952e3ec7017SPing-Ke Shih ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 2953e3ec7017SPing-Ke Shih ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 2954e3ec7017SPing-Ke Shih if (ret) { 2955e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 2956e3ec7017SPing-Ke Shih return -EFAULT; 2957e3ec7017SPing-Ke Shih } 2958e3ec7017SPing-Ke Shih 2959e3ec7017SPing-Ke Shih return 0; 2960e3ec7017SPing-Ke Shih } 2961e3ec7017SPing-Ke Shih 2962e3ec7017SPing-Ke Shih static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 2963e3ec7017SPing-Ke Shih { 2964e3ec7017SPing-Ke Shih int ret; 2965e3ec7017SPing-Ke Shih u32 reg; 2966e3ec7017SPing-Ke Shih u8 val; 2967e3ec7017SPing-Ke Shih 2968e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2969e3ec7017SPing-Ke Shih if (ret) 2970e3ec7017SPing-Ke Shih return ret; 2971e3ec7017SPing-Ke Shih 2972e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); 2973e3ec7017SPing-Ke Shih 2974e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, 2975e3ec7017SPing-Ke Shih (val & B_AX_PTCL_TX_ON_STAT) == 0, 2976e3ec7017SPing-Ke Shih SW_CVR_DUR_US, 2977e3ec7017SPing-Ke Shih SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 2978e3ec7017SPing-Ke Shih false, rtwdev, reg); 2979e3ec7017SPing-Ke Shih if (ret) 2980e3ec7017SPing-Ke Shih return ret; 2981e3ec7017SPing-Ke Shih 2982e3ec7017SPing-Ke Shih return 0; 2983e3ec7017SPing-Ke Shih } 2984e3ec7017SPing-Ke Shih 2985e3ec7017SPing-Ke Shih static int band1_enable(struct rtw89_dev *rtwdev) 2986e3ec7017SPing-Ke Shih { 2987e3ec7017SPing-Ke Shih int ret, i; 2988e3ec7017SPing-Ke Shih u32 sleep_bak[4] = {0}; 2989e3ec7017SPing-Ke Shih u32 pause_bak[4] = {0}; 2990d780f926SPing-Ke Shih u32 tx_en; 2991e3ec7017SPing-Ke Shih 2992de7ba639SPing-Ke Shih ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 2993e3ec7017SPing-Ke Shih if (ret) { 2994e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 2995e3ec7017SPing-Ke Shih return ret; 2996e3ec7017SPing-Ke Shih } 2997e3ec7017SPing-Ke Shih 2998e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 2999e3ec7017SPing-Ke Shih sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3000e3ec7017SPing-Ke Shih pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3001e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3002e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3003e3ec7017SPing-Ke Shih } 3004e3ec7017SPing-Ke Shih 3005e3ec7017SPing-Ke Shih ret = band_idle_ck_b(rtwdev, 0); 3006e3ec7017SPing-Ke Shih if (ret) { 3007e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3008e3ec7017SPing-Ke Shih return ret; 3009e3ec7017SPing-Ke Shih } 3010e3ec7017SPing-Ke Shih 3011e3ec7017SPing-Ke Shih ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 3012e3ec7017SPing-Ke Shih if (ret) { 3013e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3014e3ec7017SPing-Ke Shih return ret; 3015e3ec7017SPing-Ke Shih } 3016e3ec7017SPing-Ke Shih 3017e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 3018e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3019e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3020e3ec7017SPing-Ke Shih } 3021e3ec7017SPing-Ke Shih 3022de7ba639SPing-Ke Shih ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3023e3ec7017SPing-Ke Shih if (ret) { 3024e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3025e3ec7017SPing-Ke Shih return ret; 3026e3ec7017SPing-Ke Shih } 3027e3ec7017SPing-Ke Shih 3028e3ec7017SPing-Ke Shih ret = cmac_func_en(rtwdev, 1, true); 3029e3ec7017SPing-Ke Shih if (ret) { 3030e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3031e3ec7017SPing-Ke Shih return ret; 3032e3ec7017SPing-Ke Shih } 3033e3ec7017SPing-Ke Shih 3034e3ec7017SPing-Ke Shih ret = cmac_init(rtwdev, 1); 3035e3ec7017SPing-Ke Shih if (ret) { 3036e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3037e3ec7017SPing-Ke Shih return ret; 3038e3ec7017SPing-Ke Shih } 3039e3ec7017SPing-Ke Shih 3040e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3041e3ec7017SPing-Ke Shih B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3042e3ec7017SPing-Ke Shih 3043e3ec7017SPing-Ke Shih return 0; 3044e3ec7017SPing-Ke Shih } 3045e3ec7017SPing-Ke Shih 3046eeadcd2aSChia-Yuan Li static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3047eeadcd2aSChia-Yuan Li { 3048eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3049eeadcd2aSChia-Yuan Li 3050eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3051eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3052eeadcd2aSChia-Yuan Li } 3053eeadcd2aSChia-Yuan Li 3054eeadcd2aSChia-Yuan Li static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3055eeadcd2aSChia-Yuan Li { 3056eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3057eeadcd2aSChia-Yuan Li 3058eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3059eeadcd2aSChia-Yuan Li } 3060eeadcd2aSChia-Yuan Li 3061eeadcd2aSChia-Yuan Li static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3062eeadcd2aSChia-Yuan Li { 3063eeadcd2aSChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3064eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3065eeadcd2aSChia-Yuan Li 3066eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3067eeadcd2aSChia-Yuan Li B_AX_TX_GET_ERRPKTID_INT_EN | 3068eeadcd2aSChia-Yuan Li B_AX_TX_NXT_ERRPKTID_INT_EN | 3069eeadcd2aSChia-Yuan Li B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3070eeadcd2aSChia-Yuan Li B_AX_TX_OFFSET_ERR_INT_EN | 3071eeadcd2aSChia-Yuan Li B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3072eeadcd2aSChia-Yuan Li if (chip_id == RTL8852C) 3073eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3074eeadcd2aSChia-Yuan Li B_AX_TX_ETH_TYPE_ERR_EN | 3075eeadcd2aSChia-Yuan Li B_AX_TX_LLC_PRE_ERR_EN | 3076eeadcd2aSChia-Yuan Li B_AX_TX_NW_TYPE_ERR_EN | 3077eeadcd2aSChia-Yuan Li B_AX_TX_KSRCH_ERR_EN); 3078eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3079eeadcd2aSChia-Yuan Li imr->mpdu_tx_imr_set); 3080eeadcd2aSChia-Yuan Li 3081eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3082eeadcd2aSChia-Yuan Li B_AX_GETPKTID_ERR_INT_EN | 3083eeadcd2aSChia-Yuan Li B_AX_MHDRLEN_ERR_INT_EN | 3084eeadcd2aSChia-Yuan Li B_AX_RPT_ERR_INT_EN); 3085eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3086eeadcd2aSChia-Yuan Li imr->mpdu_rx_imr_set); 3087eeadcd2aSChia-Yuan Li } 3088eeadcd2aSChia-Yuan Li 3089eeadcd2aSChia-Yuan Li static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3090eeadcd2aSChia-Yuan Li { 3091eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3092eeadcd2aSChia-Yuan Li 3093eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3094eeadcd2aSChia-Yuan Li B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3095eeadcd2aSChia-Yuan Li B_AX_RPT_HANG_TIMEOUT_INT_EN | 3096eeadcd2aSChia-Yuan Li B_AX_PLE_B_PKTID_ERR_INT_EN); 3097eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3098eeadcd2aSChia-Yuan Li imr->sta_sch_imr_set); 3099eeadcd2aSChia-Yuan Li } 3100eeadcd2aSChia-Yuan Li 3101eeadcd2aSChia-Yuan Li static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3102eeadcd2aSChia-Yuan Li { 3103eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3104eeadcd2aSChia-Yuan Li 3105eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3106eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b0_clr); 3107eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3108eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b0_set); 3109eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3110eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b1_clr); 3111eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3112eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b1_set); 3113eeadcd2aSChia-Yuan Li } 3114eeadcd2aSChia-Yuan Li 3115eeadcd2aSChia-Yuan Li static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3116eeadcd2aSChia-Yuan Li { 3117eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3118eeadcd2aSChia-Yuan Li 3119eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3120eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3121eeadcd2aSChia-Yuan Li } 3122eeadcd2aSChia-Yuan Li 3123eeadcd2aSChia-Yuan Li static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3124eeadcd2aSChia-Yuan Li { 3125eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3126eeadcd2aSChia-Yuan Li 3127eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3128eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3129eeadcd2aSChia-Yuan Li } 3130eeadcd2aSChia-Yuan Li 3131eeadcd2aSChia-Yuan Li static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3132eeadcd2aSChia-Yuan Li { 3133eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3134eeadcd2aSChia-Yuan Li B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3135eeadcd2aSChia-Yuan Li } 3136eeadcd2aSChia-Yuan Li 3137eeadcd2aSChia-Yuan Li static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3138eeadcd2aSChia-Yuan Li { 3139eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3140eeadcd2aSChia-Yuan Li 3141eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3142eeadcd2aSChia-Yuan Li imr->host_disp_imr_clr); 3143eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3144eeadcd2aSChia-Yuan Li imr->host_disp_imr_set); 3145eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3146eeadcd2aSChia-Yuan Li imr->cpu_disp_imr_clr); 3147eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3148eeadcd2aSChia-Yuan Li imr->cpu_disp_imr_set); 3149eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3150eeadcd2aSChia-Yuan Li imr->other_disp_imr_clr); 3151eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3152eeadcd2aSChia-Yuan Li imr->other_disp_imr_set); 3153eeadcd2aSChia-Yuan Li } 3154eeadcd2aSChia-Yuan Li 3155eeadcd2aSChia-Yuan Li static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3156eeadcd2aSChia-Yuan Li { 3157eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3158eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3159eeadcd2aSChia-Yuan Li } 3160eeadcd2aSChia-Yuan Li 3161eeadcd2aSChia-Yuan Li static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3162eeadcd2aSChia-Yuan Li { 3163eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3164eeadcd2aSChia-Yuan Li 316575f1ed29SPing-Ke Shih rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3166eeadcd2aSChia-Yuan Li B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3167eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3168eeadcd2aSChia-Yuan Li B_AX_BBRPT_CHINFO_IMR_CLR); 3169eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3170eeadcd2aSChia-Yuan Li imr->bbrpt_err_imr_set); 3171eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3172eeadcd2aSChia-Yuan Li B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3173eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3174eeadcd2aSChia-Yuan Li } 3175eeadcd2aSChia-Yuan Li 3176d86369e9SChia-Yuan Li static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3177d86369e9SChia-Yuan Li { 3178d86369e9SChia-Yuan Li u32 reg; 3179d86369e9SChia-Yuan Li 3180d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); 3181d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3182d86369e9SChia-Yuan Li B_AX_FSM_TIMEOUT_ERR_INT_EN); 3183d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3184d86369e9SChia-Yuan Li } 3185d86369e9SChia-Yuan Li 3186d86369e9SChia-Yuan Li static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3187d86369e9SChia-Yuan Li { 3188d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3189d86369e9SChia-Yuan Li u32 reg; 3190d86369e9SChia-Yuan Li 3191d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); 3192d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3193d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3194d86369e9SChia-Yuan Li } 3195d86369e9SChia-Yuan Li 3196d86369e9SChia-Yuan Li static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3197d86369e9SChia-Yuan Li { 3198d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3199d86369e9SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3200d86369e9SChia-Yuan Li u32 reg; 3201d86369e9SChia-Yuan Li 3202d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx); 3203d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3204d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3205d86369e9SChia-Yuan Li 3206d86369e9SChia-Yuan Li if (chip_id == RTL8852C) { 3207d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx); 3208d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3209d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3210d86369e9SChia-Yuan Li } 3211d86369e9SChia-Yuan Li } 3212d86369e9SChia-Yuan Li 3213d86369e9SChia-Yuan Li static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3214d86369e9SChia-Yuan Li { 3215d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3216d86369e9SChia-Yuan Li u32 reg; 3217d86369e9SChia-Yuan Li 3218d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx); 3219d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3220d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3221d86369e9SChia-Yuan Li } 3222d86369e9SChia-Yuan Li 3223d86369e9SChia-Yuan Li static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3224d86369e9SChia-Yuan Li { 3225d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3226d86369e9SChia-Yuan Li u32 reg; 3227d86369e9SChia-Yuan Li 3228d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx); 3229d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3230d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3231d86369e9SChia-Yuan Li } 3232d86369e9SChia-Yuan Li 3233d86369e9SChia-Yuan Li static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3234d86369e9SChia-Yuan Li { 3235d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3236d86369e9SChia-Yuan Li u32 reg; 3237d86369e9SChia-Yuan Li 3238d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx); 3239d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3240d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3241d86369e9SChia-Yuan Li } 3242d86369e9SChia-Yuan Li 3243e3ec7017SPing-Ke Shih static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 3244e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 3245e3ec7017SPing-Ke Shih { 3246e3ec7017SPing-Ke Shih int ret; 3247e3ec7017SPing-Ke Shih 3248e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3249e3ec7017SPing-Ke Shih if (ret) { 3250e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3251e3ec7017SPing-Ke Shih sel, mac_idx); 3252e3ec7017SPing-Ke Shih return ret; 3253e3ec7017SPing-Ke Shih } 3254e3ec7017SPing-Ke Shih 3255e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 3256eeadcd2aSChia-Yuan Li rtw89_wdrls_imr_enable(rtwdev); 3257eeadcd2aSChia-Yuan Li rtw89_wsec_imr_enable(rtwdev); 3258eeadcd2aSChia-Yuan Li rtw89_mpdu_trx_imr_enable(rtwdev); 3259eeadcd2aSChia-Yuan Li rtw89_sta_sch_imr_enable(rtwdev); 3260eeadcd2aSChia-Yuan Li rtw89_txpktctl_imr_enable(rtwdev); 3261eeadcd2aSChia-Yuan Li rtw89_wde_imr_enable(rtwdev); 3262eeadcd2aSChia-Yuan Li rtw89_ple_imr_enable(rtwdev); 3263eeadcd2aSChia-Yuan Li rtw89_pktin_imr_enable(rtwdev); 3264eeadcd2aSChia-Yuan Li rtw89_dispatcher_imr_enable(rtwdev); 3265eeadcd2aSChia-Yuan Li rtw89_cpuio_imr_enable(rtwdev); 3266eeadcd2aSChia-Yuan Li rtw89_bbrpt_imr_enable(rtwdev); 3267e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL) { 3268d86369e9SChia-Yuan Li rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3269d86369e9SChia-Yuan Li rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3270d86369e9SChia-Yuan Li rtw89_cdma_imr_enable(rtwdev, mac_idx); 3271d86369e9SChia-Yuan Li rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3272d86369e9SChia-Yuan Li rtw89_rmac_imr_enable(rtwdev, mac_idx); 3273d86369e9SChia-Yuan Li rtw89_tmac_imr_enable(rtwdev, mac_idx); 3274e3ec7017SPing-Ke Shih } else { 3275e3ec7017SPing-Ke Shih return -EINVAL; 3276e3ec7017SPing-Ke Shih } 3277e3ec7017SPing-Ke Shih 3278e3ec7017SPing-Ke Shih return 0; 3279e3ec7017SPing-Ke Shih } 3280e3ec7017SPing-Ke Shih 32819f405b01SPing-Ke Shih static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) 32829f405b01SPing-Ke Shih { 32839f405b01SPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 32849f405b01SPing-Ke Shih 32859f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 32869f405b01SPing-Ke Shih en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 32879f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 32889f405b01SPing-Ke Shih en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 32899f405b01SPing-Ke Shih if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 32909f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 32919f405b01SPing-Ke Shih en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 32929f405b01SPing-Ke Shih } 32939f405b01SPing-Ke Shih 3294e3ec7017SPing-Ke Shih static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 3295e3ec7017SPing-Ke Shih { 3296e3ec7017SPing-Ke Shih int ret = 0; 3297e3ec7017SPing-Ke Shih 3298e3ec7017SPing-Ke Shih if (enable) { 3299e3ec7017SPing-Ke Shih ret = band1_enable(rtwdev); 3300e3ec7017SPing-Ke Shih if (ret) { 3301e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3302e3ec7017SPing-Ke Shih return ret; 3303e3ec7017SPing-Ke Shih } 3304e3ec7017SPing-Ke Shih 3305e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3306e3ec7017SPing-Ke Shih if (ret) { 3307e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3308e3ec7017SPing-Ke Shih return ret; 3309e3ec7017SPing-Ke Shih } 3310e3ec7017SPing-Ke Shih } else { 3311e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3312e3ec7017SPing-Ke Shih return -EINVAL; 3313e3ec7017SPing-Ke Shih } 3314e3ec7017SPing-Ke Shih 3315e3ec7017SPing-Ke Shih return 0; 3316e3ec7017SPing-Ke Shih } 3317e3ec7017SPing-Ke Shih 3318e3ec7017SPing-Ke Shih static int set_host_rpr(struct rtw89_dev *rtwdev) 3319e3ec7017SPing-Ke Shih { 3320e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3321e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3322e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3323e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3324e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 3325e3ec7017SPing-Ke Shih } else { 3326e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3327e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3328e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3329e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 3330e3ec7017SPing-Ke Shih } 3331e3ec7017SPing-Ke Shih 3332e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3333e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3334e3ec7017SPing-Ke Shih 3335e3ec7017SPing-Ke Shih return 0; 3336e3ec7017SPing-Ke Shih } 3337e3ec7017SPing-Ke Shih 3338e3ec7017SPing-Ke Shih static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 3339e3ec7017SPing-Ke Shih { 3340e3ec7017SPing-Ke Shih enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3341e3ec7017SPing-Ke Shih int ret; 3342e3ec7017SPing-Ke Shih 3343e3ec7017SPing-Ke Shih ret = dmac_init(rtwdev, 0); 3344e3ec7017SPing-Ke Shih if (ret) { 3345e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3346e3ec7017SPing-Ke Shih return ret; 3347e3ec7017SPing-Ke Shih } 3348e3ec7017SPing-Ke Shih 3349e3ec7017SPing-Ke Shih ret = cmac_init(rtwdev, 0); 3350e3ec7017SPing-Ke Shih if (ret) { 3351e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3352e3ec7017SPing-Ke Shih return ret; 3353e3ec7017SPing-Ke Shih } 3354e3ec7017SPing-Ke Shih 3355e3ec7017SPing-Ke Shih if (is_qta_dbcc(rtwdev, qta_mode)) { 3356e3ec7017SPing-Ke Shih ret = rtw89_mac_dbcc_enable(rtwdev, true); 3357e3ec7017SPing-Ke Shih if (ret) { 3358e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3359e3ec7017SPing-Ke Shih return ret; 3360e3ec7017SPing-Ke Shih } 3361e3ec7017SPing-Ke Shih } 3362e3ec7017SPing-Ke Shih 3363e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3364e3ec7017SPing-Ke Shih if (ret) { 3365e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3366e3ec7017SPing-Ke Shih return ret; 3367e3ec7017SPing-Ke Shih } 3368e3ec7017SPing-Ke Shih 3369e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3370e3ec7017SPing-Ke Shih if (ret) { 3371e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3372e3ec7017SPing-Ke Shih return ret; 3373e3ec7017SPing-Ke Shih } 3374e3ec7017SPing-Ke Shih 33759f405b01SPing-Ke Shih rtw89_mac_err_imr_ctrl(rtwdev, true); 33769f405b01SPing-Ke Shih 3377e3ec7017SPing-Ke Shih ret = set_host_rpr(rtwdev); 3378e3ec7017SPing-Ke Shih if (ret) { 3379e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3380e3ec7017SPing-Ke Shih return ret; 3381e3ec7017SPing-Ke Shih } 3382e3ec7017SPing-Ke Shih 3383e3ec7017SPing-Ke Shih return 0; 3384e3ec7017SPing-Ke Shih } 3385e3ec7017SPing-Ke Shih 3386ec356ffbSChia-Yuan Li static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3387ec356ffbSChia-Yuan Li { 33885c3afcbaSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3389ec356ffbSChia-Yuan Li u32 val32; 3390ec356ffbSChia-Yuan Li 33915c3afcbaSPing-Ke Shih if (chip_id == RTL8852B || chip_id == RTL8851B) { 33925c3afcbaSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 33935c3afcbaSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 33945c3afcbaSPing-Ke Shih return; 33955c3afcbaSPing-Ke Shih } 33965c3afcbaSPing-Ke Shih 3397ec356ffbSChia-Yuan Li rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3398ec356ffbSChia-Yuan Li WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3399ec356ffbSChia-Yuan Li 3400ec356ffbSChia-Yuan Li val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3401ec356ffbSChia-Yuan Li val32 |= B_AX_FS_WDT_INT; 3402ec356ffbSChia-Yuan Li val32 &= ~B_AX_FS_WDT_INT_MSK; 3403ec356ffbSChia-Yuan Li rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3404ec356ffbSChia-Yuan Li } 3405ec356ffbSChia-Yuan Li 34065f05bdb0SChih-Kang Chang void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) 3407e3ec7017SPing-Ke Shih { 3408e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3409e3ec7017SPing-Ke Shih 3410e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3411de78869dSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3412de78869dSChia-Yuan Li B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3413e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3414ec356ffbSChia-Yuan Li 3415ec356ffbSChia-Yuan Li rtw89_disable_fw_watchdog(rtwdev); 3416ec356ffbSChia-Yuan Li 3417de78869dSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3418de78869dSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3419e3ec7017SPing-Ke Shih } 3420e3ec7017SPing-Ke Shih 34215f05bdb0SChih-Kang Chang int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw) 3422e3ec7017SPing-Ke Shih { 3423e3ec7017SPing-Ke Shih u32 val; 3424e3ec7017SPing-Ke Shih int ret; 3425e3ec7017SPing-Ke Shih 3426e3ec7017SPing-Ke Shih if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3427e3ec7017SPing-Ke Shih return -EFAULT; 3428e3ec7017SPing-Ke Shih 3429e749ef96SPing-Ke Shih rtw89_write32(rtwdev, R_AX_UDM1, 0); 3430e749ef96SPing-Ke Shih rtw89_write32(rtwdev, R_AX_UDM2, 0); 3431e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3432e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3433a63ae673SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3434a63ae673SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3435e3ec7017SPing-Ke Shih 3436e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3437e3ec7017SPing-Ke Shih 3438e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3439e3ec7017SPing-Ke Shih val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3440e3ec7017SPing-Ke Shih val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3441e3ec7017SPing-Ke Shih B_AX_WCPU_FWDL_STS_MASK); 3442e3ec7017SPing-Ke Shih 3443e3ec7017SPing-Ke Shih if (dlfw) 3444e3ec7017SPing-Ke Shih val |= B_AX_WCPU_FWDL_EN; 3445e3ec7017SPing-Ke Shih 3446e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 34472e5a65f5SPing-Ke Shih 34482e5a65f5SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852B) 34492e5a65f5SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 34502e5a65f5SPing-Ke Shih B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 34512e5a65f5SPing-Ke Shih 3452e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3453e3ec7017SPing-Ke Shih boot_reason); 3454e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3455e3ec7017SPing-Ke Shih 3456e3ec7017SPing-Ke Shih if (!dlfw) { 3457e3ec7017SPing-Ke Shih mdelay(5); 3458e3ec7017SPing-Ke Shih 3459e3ec7017SPing-Ke Shih ret = rtw89_fw_check_rdy(rtwdev); 3460e3ec7017SPing-Ke Shih if (ret) 3461e3ec7017SPing-Ke Shih return ret; 3462e3ec7017SPing-Ke Shih } 3463e3ec7017SPing-Ke Shih 3464e3ec7017SPing-Ke Shih return 0; 3465e3ec7017SPing-Ke Shih } 3466e3ec7017SPing-Ke Shih 3467a7d82a7aSPing-Ke Shih static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3468e3ec7017SPing-Ke Shih { 3469a7d82a7aSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3470e3ec7017SPing-Ke Shih u32 val; 3471e3ec7017SPing-Ke Shih int ret; 3472e3ec7017SPing-Ke Shih 3473a7d82a7aSPing-Ke Shih if (chip_id == RTL8852C) 3474a7d82a7aSPing-Ke Shih val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3475a7d82a7aSPing-Ke Shih B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3476a7d82a7aSPing-Ke Shih else 3477e3ec7017SPing-Ke Shih val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3478e3ec7017SPing-Ke Shih B_AX_PKT_BUF_EN; 3479e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3480e3ec7017SPing-Ke Shih 34815c3afcbaSPing-Ke Shih if (chip_id == RTL8851B) 34825c3afcbaSPing-Ke Shih val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 34835c3afcbaSPing-Ke Shih else 3484e3ec7017SPing-Ke Shih val = B_AX_DISPATCHER_CLK_EN; 3485e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3486e3ec7017SPing-Ke Shih 3487a7d82a7aSPing-Ke Shih if (chip_id != RTL8852C) 3488a7d82a7aSPing-Ke Shih goto dle; 3489a7d82a7aSPing-Ke Shih 3490a7d82a7aSPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3491a7d82a7aSPing-Ke Shih val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3492a7d82a7aSPing-Ke Shih val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3493a7d82a7aSPing-Ke Shih B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3494a7d82a7aSPing-Ke Shih rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3495a7d82a7aSPing-Ke Shih 3496a7d82a7aSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3497a7d82a7aSPing-Ke Shih B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3498a7d82a7aSPing-Ke Shih B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3499a7d82a7aSPing-Ke Shih B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3500a7d82a7aSPing-Ke Shih B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3501a7d82a7aSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3502a7d82a7aSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3503a7d82a7aSPing-Ke Shih 3504a7d82a7aSPing-Ke Shih dle: 3505e3ec7017SPing-Ke Shih ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3506e3ec7017SPing-Ke Shih if (ret) { 3507e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3508e3ec7017SPing-Ke Shih return ret; 3509e3ec7017SPing-Ke Shih } 3510e3ec7017SPing-Ke Shih 3511e3ec7017SPing-Ke Shih ret = hfc_init(rtwdev, true, false, true); 3512e3ec7017SPing-Ke Shih if (ret) { 3513e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3514e3ec7017SPing-Ke Shih return ret; 3515e3ec7017SPing-Ke Shih } 3516e3ec7017SPing-Ke Shih 3517e3ec7017SPing-Ke Shih return ret; 3518e3ec7017SPing-Ke Shih } 3519e3ec7017SPing-Ke Shih 352061ebeecbSPing-Ke Shih int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3521e3ec7017SPing-Ke Shih { 3522e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3523e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3524e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3525e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3526e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3527e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 352861ebeecbSPing-Ke Shih 352961ebeecbSPing-Ke Shih return 0; 3530e3ec7017SPing-Ke Shih } 353161ebeecbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3532e3ec7017SPing-Ke Shih 353314b6e9f4SPing-Ke Shih int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3534e3ec7017SPing-Ke Shih { 3535e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3536e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3537e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3538e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3539e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3540e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 354114b6e9f4SPing-Ke Shih 354214b6e9f4SPing-Ke Shih return 0; 3543e3ec7017SPing-Ke Shih } 354461ebeecbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3545e3ec7017SPing-Ke Shih 3546e3ec7017SPing-Ke Shih int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) 3547e3ec7017SPing-Ke Shih { 3548e3ec7017SPing-Ke Shih int ret; 3549e3ec7017SPing-Ke Shih 3550e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 3551e3ec7017SPing-Ke Shih if (ret) { 3552e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 3553e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 3554e3ec7017SPing-Ke Shih if (ret) 3555e3ec7017SPing-Ke Shih return ret; 3556e3ec7017SPing-Ke Shih } 3557e3ec7017SPing-Ke Shih 355852f12705SChin-Yen Lee rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3559e3ec7017SPing-Ke Shih 3560a7d82a7aSPing-Ke Shih ret = rtw89_mac_dmac_pre_init(rtwdev); 3561a7d82a7aSPing-Ke Shih if (ret) 3562a7d82a7aSPing-Ke Shih return ret; 3563a7d82a7aSPing-Ke Shih 3564e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_pre_init) { 3565e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3566e3ec7017SPing-Ke Shih if (ret) 3567e3ec7017SPing-Ke Shih return ret; 3568e3ec7017SPing-Ke Shih } 3569e3ec7017SPing-Ke Shih 3570e3ec7017SPing-Ke Shih ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); 3571e3ec7017SPing-Ke Shih if (ret) 3572e3ec7017SPing-Ke Shih return ret; 3573e3ec7017SPing-Ke Shih 3574e3ec7017SPing-Ke Shih return 0; 3575e3ec7017SPing-Ke Shih } 3576e3ec7017SPing-Ke Shih 3577e3ec7017SPing-Ke Shih int rtw89_mac_init(struct rtw89_dev *rtwdev) 3578e3ec7017SPing-Ke Shih { 3579e3ec7017SPing-Ke Shih int ret; 3580e3ec7017SPing-Ke Shih 3581e3ec7017SPing-Ke Shih ret = rtw89_mac_partial_init(rtwdev); 3582e3ec7017SPing-Ke Shih if (ret) 3583e3ec7017SPing-Ke Shih goto fail; 3584e3ec7017SPing-Ke Shih 358561ebeecbSPing-Ke Shih ret = rtw89_chip_enable_bb_rf(rtwdev); 358661ebeecbSPing-Ke Shih if (ret) 358761ebeecbSPing-Ke Shih goto fail; 3588e3ec7017SPing-Ke Shih 3589e3ec7017SPing-Ke Shih ret = rtw89_mac_sys_init(rtwdev); 3590e3ec7017SPing-Ke Shih if (ret) 3591e3ec7017SPing-Ke Shih goto fail; 3592e3ec7017SPing-Ke Shih 3593e3ec7017SPing-Ke Shih ret = rtw89_mac_trx_init(rtwdev); 3594e3ec7017SPing-Ke Shih if (ret) 3595e3ec7017SPing-Ke Shih goto fail; 3596e3ec7017SPing-Ke Shih 3597e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_post_init) { 3598e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3599e3ec7017SPing-Ke Shih if (ret) 3600e3ec7017SPing-Ke Shih goto fail; 3601e3ec7017SPing-Ke Shih } 3602e3ec7017SPing-Ke Shih 3603e3ec7017SPing-Ke Shih rtw89_fw_send_all_early_h2c(rtwdev); 3604e3ec7017SPing-Ke Shih rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3605e3ec7017SPing-Ke Shih 3606e3ec7017SPing-Ke Shih return ret; 3607e3ec7017SPing-Ke Shih fail: 3608e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 3609e3ec7017SPing-Ke Shih 3610e3ec7017SPing-Ke Shih return ret; 3611e3ec7017SPing-Ke Shih } 3612e3ec7017SPing-Ke Shih 3613e3ec7017SPing-Ke Shih static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3614e3ec7017SPing-Ke Shih { 3615e3ec7017SPing-Ke Shih u8 i; 3616e3ec7017SPing-Ke Shih 3617e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 3618e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3619e3ec7017SPing-Ke Shih DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3620e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3621e3ec7017SPing-Ke Shih } 3622e3ec7017SPing-Ke Shih } 3623e3ec7017SPing-Ke Shih 3624e3ec7017SPing-Ke Shih static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3625e3ec7017SPing-Ke Shih { 3626e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3627e3ec7017SPing-Ke Shih CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3628e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3629e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3630e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3631e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3632e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3633e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3634e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3635e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3636e3ec7017SPing-Ke Shih } 3637e3ec7017SPing-Ke Shih 36381b73e77dSPing-Ke Shih int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3639e3ec7017SPing-Ke Shih { 3640e3ec7017SPing-Ke Shih u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3641e3ec7017SPing-Ke Shih u8 grp = macid >> 5; 3642e3ec7017SPing-Ke Shih int ret; 3643e3ec7017SPing-Ke Shih 3644ac3a9f18SPing-Ke Shih /* If this is called by change_interface() in the case of P2P, it could 3645ac3a9f18SPing-Ke Shih * be power-off, so ignore this operation. 3646ac3a9f18SPing-Ke Shih */ 3647ac3a9f18SPing-Ke Shih if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 3648ac3a9f18SPing-Ke Shih !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3649ac3a9f18SPing-Ke Shih return 0; 3650ac3a9f18SPing-Ke Shih 3651e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3652e3ec7017SPing-Ke Shih if (ret) 3653e3ec7017SPing-Ke Shih return ret; 3654e3ec7017SPing-Ke Shih 3655e3ec7017SPing-Ke Shih rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3656e3ec7017SPing-Ke Shih 3657e3ec7017SPing-Ke Shih return 0; 3658e3ec7017SPing-Ke Shih } 3659e3ec7017SPing-Ke Shih 3660e3ec7017SPing-Ke Shih static const struct rtw89_port_reg rtw_port_base = { 3661e3ec7017SPing-Ke Shih .port_cfg = R_AX_PORT_CFG_P0, 3662e3ec7017SPing-Ke Shih .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3663e3ec7017SPing-Ke Shih .bcn_area = R_AX_BCN_AREA_P0, 3664e3ec7017SPing-Ke Shih .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3665e3ec7017SPing-Ke Shih .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3666e3ec7017SPing-Ke Shih .tbtt_agg = R_AX_TBTT_AGG_P0, 3667e3ec7017SPing-Ke Shih .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3668e3ec7017SPing-Ke Shih .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3669e3ec7017SPing-Ke Shih .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3670e3ec7017SPing-Ke Shih .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3671e3ec7017SPing-Ke Shih .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3672e3ec7017SPing-Ke Shih .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3673e3ec7017SPing-Ke Shih .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3674e3ec7017SPing-Ke Shih .tsftr_l = R_AX_TSFTR_LOW_P0, 3675e3ec7017SPing-Ke Shih .tsftr_h = R_AX_TSFTR_HIGH_P0 3676e3ec7017SPing-Ke Shih }; 3677e3ec7017SPing-Ke Shih 3678e3ec7017SPing-Ke Shih #define BCN_INTERVAL 100 3679e3ec7017SPing-Ke Shih #define BCN_ERLY_DEF 160 3680e3ec7017SPing-Ke Shih #define BCN_SETUP_DEF 2 3681e3ec7017SPing-Ke Shih #define BCN_HOLD_DEF 200 3682e3ec7017SPing-Ke Shih #define BCN_MASK_DEF 0 3683e3ec7017SPing-Ke Shih #define TBTT_ERLY_DEF 5 3684e3ec7017SPing-Ke Shih #define BCN_SET_UNIT 32 3685e3ec7017SPing-Ke Shih #define BCN_ERLY_SET_DLY (10 * 2) 3686e3ec7017SPing-Ke Shih 3687e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3688e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3689e3ec7017SPing-Ke Shih { 3690e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3691e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3692e3ec7017SPing-Ke Shih 3693e3ec7017SPing-Ke Shih if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3694e3ec7017SPing-Ke Shih return; 3695e3ec7017SPing-Ke Shih 3696e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3697e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3698e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3699e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3700e3ec7017SPing-Ke Shih 3701e3ec7017SPing-Ke Shih msleep(vif->bss_conf.beacon_int + 1); 3702e3ec7017SPing-Ke Shih 3703e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3704e3ec7017SPing-Ke Shih B_AX_BRK_SETUP); 3705e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3706e3ec7017SPing-Ke Shih rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3707e3ec7017SPing-Ke Shih } 3708e3ec7017SPing-Ke Shih 3709e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3710e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 3711e3ec7017SPing-Ke Shih { 3712e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3713e3ec7017SPing-Ke Shih 3714e3ec7017SPing-Ke Shih if (en) 3715e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3716e3ec7017SPing-Ke Shih else 3717e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3718e3ec7017SPing-Ke Shih } 3719e3ec7017SPing-Ke Shih 3720e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3721e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 3722e3ec7017SPing-Ke Shih { 3723e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3724e3ec7017SPing-Ke Shih 3725e3ec7017SPing-Ke Shih if (en) 3726e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3727e3ec7017SPing-Ke Shih else 3728e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3729e3ec7017SPing-Ke Shih } 3730e3ec7017SPing-Ke Shih 3731e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3732e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3733e3ec7017SPing-Ke Shih { 3734e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3735e3ec7017SPing-Ke Shih 3736e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3737e3ec7017SPing-Ke Shih rtwvif->net_type); 3738e3ec7017SPing-Ke Shih } 3739e3ec7017SPing-Ke Shih 3740e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3741e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3742e3ec7017SPing-Ke Shih { 3743e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3744e3ec7017SPing-Ke Shih bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3745e3ec7017SPing-Ke Shih u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3746e3ec7017SPing-Ke Shih 3747e3ec7017SPing-Ke Shih if (en) 3748e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3749e3ec7017SPing-Ke Shih else 3750e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3751e3ec7017SPing-Ke Shih } 3752e3ec7017SPing-Ke Shih 3753e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3754e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3755e3ec7017SPing-Ke Shih { 3756e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3757e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3758e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3759e3ec7017SPing-Ke Shih u32 bit = B_AX_RX_BSSID_FIT_EN; 3760e3ec7017SPing-Ke Shih 3761e3ec7017SPing-Ke Shih if (en) 3762e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3763e3ec7017SPing-Ke Shih else 3764e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3765e3ec7017SPing-Ke Shih } 3766e3ec7017SPing-Ke Shih 3767e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3768e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3769e3ec7017SPing-Ke Shih { 3770e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3771e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3772e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3773e3ec7017SPing-Ke Shih 3774e3ec7017SPing-Ke Shih if (en) 3775e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3776e3ec7017SPing-Ke Shih else 3777e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3778e3ec7017SPing-Ke Shih } 3779e3ec7017SPing-Ke Shih 3780e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3781e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3782e3ec7017SPing-Ke Shih { 3783e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3784e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3785e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3786e3ec7017SPing-Ke Shih 3787e3ec7017SPing-Ke Shih if (en) 3788e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3789e3ec7017SPing-Ke Shih else 3790e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3791e3ec7017SPing-Ke Shih } 3792e3ec7017SPing-Ke Shih 3793e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3794e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3795e3ec7017SPing-Ke Shih { 3796e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3797e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3798e3ec7017SPing-Ke Shih u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3799e3ec7017SPing-Ke Shih 3800e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3801e3ec7017SPing-Ke Shih bcn_int); 3802e3ec7017SPing-Ke Shih } 3803e3ec7017SPing-Ke Shih 3804283c3d88SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3805283c3d88SPing-Ke Shih struct rtw89_vif *rtwvif) 3806283c3d88SPing-Ke Shih { 3807283c3d88SPing-Ke Shih static const u32 hiq_win_addr[RTW89_PORT_NUM] = { 3808283c3d88SPing-Ke Shih R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3809283c3d88SPing-Ke Shih R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3810283c3d88SPing-Ke Shih R_AX_PORT_HGQ_WINDOW_CFG + 3, 3811283c3d88SPing-Ke Shih }; 3812283c3d88SPing-Ke Shih u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3813283c3d88SPing-Ke Shih u8 port = rtwvif->port; 3814283c3d88SPing-Ke Shih u32 reg; 3815283c3d88SPing-Ke Shih 3816283c3d88SPing-Ke Shih reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx); 3817283c3d88SPing-Ke Shih rtw89_write8(rtwdev, reg, win); 3818283c3d88SPing-Ke Shih } 3819283c3d88SPing-Ke Shih 3820283c3d88SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3821283c3d88SPing-Ke Shih struct rtw89_vif *rtwvif) 3822283c3d88SPing-Ke Shih { 3823283c3d88SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3824283c3d88SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3825283c3d88SPing-Ke Shih u32 addr; 3826283c3d88SPing-Ke Shih 3827283c3d88SPing-Ke Shih addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); 3828283c3d88SPing-Ke Shih rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3829283c3d88SPing-Ke Shih 3830283c3d88SPing-Ke Shih rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3831283c3d88SPing-Ke Shih vif->bss_conf.dtim_period); 3832283c3d88SPing-Ke Shih } 3833283c3d88SPing-Ke Shih 3834e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3835e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3836e3ec7017SPing-Ke Shih { 3837e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3838e3ec7017SPing-Ke Shih 3839e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3840e3ec7017SPing-Ke Shih B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3841e3ec7017SPing-Ke Shih } 3842e3ec7017SPing-Ke Shih 3843e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3844e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3845e3ec7017SPing-Ke Shih { 3846e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3847e3ec7017SPing-Ke Shih 3848e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3849e3ec7017SPing-Ke Shih B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3850e3ec7017SPing-Ke Shih } 3851e3ec7017SPing-Ke Shih 3852e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3853e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3854e3ec7017SPing-Ke Shih { 3855e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3856e3ec7017SPing-Ke Shih 3857e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3858e3ec7017SPing-Ke Shih B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3859e3ec7017SPing-Ke Shih } 3860e3ec7017SPing-Ke Shih 3861e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3862e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3863e3ec7017SPing-Ke Shih { 3864e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3865e3ec7017SPing-Ke Shih 3866e3ec7017SPing-Ke Shih rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3867e3ec7017SPing-Ke Shih B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3868e3ec7017SPing-Ke Shih } 3869e3ec7017SPing-Ke Shih 3870e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3871e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3872e3ec7017SPing-Ke Shih { 3873e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3874e3ec7017SPing-Ke Shih static const u32 masks[RTW89_PORT_NUM] = { 3875e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3876e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3877e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_4_MASK, 3878e3ec7017SPing-Ke Shih }; 3879e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3880e3ec7017SPing-Ke Shih u32 reg_base; 3881e3ec7017SPing-Ke Shih u32 reg; 3882e3ec7017SPing-Ke Shih u8 bss_color; 3883e3ec7017SPing-Ke Shih 3884e3ec7017SPing-Ke Shih bss_color = vif->bss_conf.he_bss_color.color; 3885e3ec7017SPing-Ke Shih reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; 3886e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); 3887e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3888e3ec7017SPing-Ke Shih } 3889e3ec7017SPing-Ke Shih 3890e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3891e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3892e3ec7017SPing-Ke Shih { 3893e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3894e3ec7017SPing-Ke Shih u32 reg; 3895e3ec7017SPing-Ke Shih 3896e3ec7017SPing-Ke Shih if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3897e3ec7017SPing-Ke Shih return; 3898e3ec7017SPing-Ke Shih 3899e3ec7017SPing-Ke Shih if (port == 0) { 3900e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); 3901e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3902e3ec7017SPing-Ke Shih } 3903e3ec7017SPing-Ke Shih } 3904e3ec7017SPing-Ke Shih 3905e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3906e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3907e3ec7017SPing-Ke Shih { 3908e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3909e3ec7017SPing-Ke Shih u32 reg; 3910e3ec7017SPing-Ke Shih u32 val; 3911e3ec7017SPing-Ke Shih 3912e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); 3913e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 3914e3ec7017SPing-Ke Shih val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 3915e3ec7017SPing-Ke Shih if (port == 0) 3916e3ec7017SPing-Ke Shih val &= ~BIT(0); 3917e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 3918e3ec7017SPing-Ke Shih } 3919e3ec7017SPing-Ke Shih 3920e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 3921d592b9f7SPo-Hao Huang struct rtw89_vif *rtwvif, bool enable) 3922e3ec7017SPing-Ke Shih { 3923e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3924e3ec7017SPing-Ke Shih 3925d592b9f7SPo-Hao Huang if (enable) 3926d592b9f7SPo-Hao Huang rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 3927d592b9f7SPo-Hao Huang B_AX_PORT_FUNC_EN); 3928d592b9f7SPo-Hao Huang else 3929d592b9f7SPo-Hao Huang rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 3930d592b9f7SPo-Hao Huang B_AX_PORT_FUNC_EN); 3931e3ec7017SPing-Ke Shih } 3932e3ec7017SPing-Ke Shih 3933e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 3934e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3935e3ec7017SPing-Ke Shih { 3936e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3937e3ec7017SPing-Ke Shih 3938e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 3939e3ec7017SPing-Ke Shih BCN_ERLY_DEF); 3940e3ec7017SPing-Ke Shih } 3941e3ec7017SPing-Ke Shih 3942704052f5SChia-Yuan Li static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 3943704052f5SChia-Yuan Li struct rtw89_vif *rtwvif) 3944704052f5SChia-Yuan Li { 3945704052f5SChia-Yuan Li const struct rtw89_port_reg *p = &rtw_port_base; 3946704052f5SChia-Yuan Li u16 val; 3947704052f5SChia-Yuan Li 3948704052f5SChia-Yuan Li if (rtwdev->chip->chip_id != RTL8852C) 3949704052f5SChia-Yuan Li return; 3950704052f5SChia-Yuan Li 3951704052f5SChia-Yuan Li if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 3952704052f5SChia-Yuan Li rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 3953704052f5SChia-Yuan Li return; 3954704052f5SChia-Yuan Li 3955704052f5SChia-Yuan Li val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 3956704052f5SChia-Yuan Li B_AX_TBTT_SHIFT_OFST_SIGN; 3957704052f5SChia-Yuan Li 3958704052f5SChia-Yuan Li rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 3959704052f5SChia-Yuan Li B_AX_TBTT_SHIFT_OFST_MASK, val); 3960704052f5SChia-Yuan Li } 3961704052f5SChia-Yuan Li 396242db7eddSZong-Zhe Yang void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 3963fb2b8cecSPo-Hao Huang struct rtw89_vif *rtwvif, 396442db7eddSZong-Zhe Yang struct rtw89_vif *rtwvif_src, 396542db7eddSZong-Zhe Yang u16 offset_tu) 3966fb2b8cecSPo-Hao Huang { 3967fb2b8cecSPo-Hao Huang u32 val, reg; 3968fb2b8cecSPo-Hao Huang 396942db7eddSZong-Zhe Yang val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 397042db7eddSZong-Zhe Yang reg = rtw89_mac_reg_by_idx(R_AX_PORT0_TSF_SYNC + rtwvif->port * 4, 397142db7eddSZong-Zhe Yang rtwvif->mac_idx); 397242db7eddSZong-Zhe Yang 397342db7eddSZong-Zhe Yang rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 397442db7eddSZong-Zhe Yang rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 397542db7eddSZong-Zhe Yang rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 397642db7eddSZong-Zhe Yang } 397742db7eddSZong-Zhe Yang 397842db7eddSZong-Zhe Yang static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 397942db7eddSZong-Zhe Yang struct rtw89_vif *rtwvif, 398042db7eddSZong-Zhe Yang struct rtw89_vif *rtwvif_src, 398142db7eddSZong-Zhe Yang u8 offset, int *n_offset) 398242db7eddSZong-Zhe Yang { 3983fb2b8cecSPo-Hao Huang if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 3984fb2b8cecSPo-Hao Huang return; 3985fb2b8cecSPo-Hao Huang 3986fb2b8cecSPo-Hao Huang /* adjust offset randomly to avoid beacon conflict */ 3987fb2b8cecSPo-Hao Huang offset = offset - offset / 4 + get_random_u32() % (offset / 2); 398842db7eddSZong-Zhe Yang rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 398942db7eddSZong-Zhe Yang (*n_offset) * offset); 3990fb2b8cecSPo-Hao Huang 39911120e6a6SZong-Zhe Yang (*n_offset)++; 3992fb2b8cecSPo-Hao Huang } 3993fb2b8cecSPo-Hao Huang 3994fb2b8cecSPo-Hao Huang static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 3995fb2b8cecSPo-Hao Huang { 3996fb2b8cecSPo-Hao Huang struct rtw89_vif *src = NULL, *tmp; 3997fb2b8cecSPo-Hao Huang u8 offset = 100, vif_aps = 0; 3998fb2b8cecSPo-Hao Huang int n_offset = 1; 3999fb2b8cecSPo-Hao Huang 4000fb2b8cecSPo-Hao Huang rtw89_for_each_rtwvif(rtwdev, tmp) { 4001fb2b8cecSPo-Hao Huang if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4002fb2b8cecSPo-Hao Huang src = tmp; 4003fb2b8cecSPo-Hao Huang if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4004fb2b8cecSPo-Hao Huang vif_aps++; 4005fb2b8cecSPo-Hao Huang } 4006fb2b8cecSPo-Hao Huang 4007fb2b8cecSPo-Hao Huang if (vif_aps == 0) 4008fb2b8cecSPo-Hao Huang return; 4009fb2b8cecSPo-Hao Huang 4010fb2b8cecSPo-Hao Huang offset /= (vif_aps + 1); 4011fb2b8cecSPo-Hao Huang 4012fb2b8cecSPo-Hao Huang rtw89_for_each_rtwvif(rtwdev, tmp) 401342db7eddSZong-Zhe Yang rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4014fb2b8cecSPo-Hao Huang } 4015fb2b8cecSPo-Hao Huang 4016e3ec7017SPing-Ke Shih int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4017e3ec7017SPing-Ke Shih { 4018e3ec7017SPing-Ke Shih int ret; 4019e3ec7017SPing-Ke Shih 4020e3ec7017SPing-Ke Shih ret = rtw89_mac_port_update(rtwdev, rtwvif); 4021e3ec7017SPing-Ke Shih if (ret) 4022e3ec7017SPing-Ke Shih return ret; 4023e3ec7017SPing-Ke Shih 4024e3ec7017SPing-Ke Shih rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4025e3ec7017SPing-Ke Shih rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4026e3ec7017SPing-Ke Shih 40271b73e77dSPing-Ke Shih ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4028e3ec7017SPing-Ke Shih if (ret) 4029e3ec7017SPing-Ke Shih return ret; 4030e3ec7017SPing-Ke Shih 4031ff66964aSPing-Ke Shih ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4032e3ec7017SPing-Ke Shih if (ret) 4033e3ec7017SPing-Ke Shih return ret; 4034e3ec7017SPing-Ke Shih 4035a0e78d5cSPo-Hao Huang ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4036a0e78d5cSPo-Hao Huang if (ret) 4037a0e78d5cSPo-Hao Huang return ret; 4038a0e78d5cSPo-Hao Huang 4039e3ec7017SPing-Ke Shih ret = rtw89_cam_init(rtwdev, rtwvif); 4040e3ec7017SPing-Ke Shih if (ret) 4041e3ec7017SPing-Ke Shih return ret; 4042e3ec7017SPing-Ke Shih 404340822e07SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4044e3ec7017SPing-Ke Shih if (ret) 4045e3ec7017SPing-Ke Shih return ret; 4046e3ec7017SPing-Ke Shih 4047742c470bSPing-Ke Shih ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 4048e3ec7017SPing-Ke Shih if (ret) 4049e3ec7017SPing-Ke Shih return ret; 4050e3ec7017SPing-Ke Shih 4051e3ec7017SPing-Ke Shih return 0; 4052e3ec7017SPing-Ke Shih } 4053e3ec7017SPing-Ke Shih 4054e3ec7017SPing-Ke Shih int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4055e3ec7017SPing-Ke Shih { 4056e3ec7017SPing-Ke Shih int ret; 4057e3ec7017SPing-Ke Shih 4058ff66964aSPing-Ke Shih ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4059e3ec7017SPing-Ke Shih if (ret) 4060e3ec7017SPing-Ke Shih return ret; 4061e3ec7017SPing-Ke Shih 4062e3ec7017SPing-Ke Shih rtw89_cam_deinit(rtwdev, rtwvif); 4063e3ec7017SPing-Ke Shih 406440822e07SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4065e3ec7017SPing-Ke Shih if (ret) 4066e3ec7017SPing-Ke Shih return ret; 4067e3ec7017SPing-Ke Shih 4068e3ec7017SPing-Ke Shih return 0; 4069e3ec7017SPing-Ke Shih } 4070e3ec7017SPing-Ke Shih 4071e3ec7017SPing-Ke Shih int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4072e3ec7017SPing-Ke Shih { 4073e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 4074e3ec7017SPing-Ke Shih 4075e3ec7017SPing-Ke Shih if (port >= RTW89_PORT_NUM) 4076e3ec7017SPing-Ke Shih return -EINVAL; 4077e3ec7017SPing-Ke Shih 4078e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4079e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4080e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4081e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4082e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4083e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4084e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 4085e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 4086e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4087283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4088283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4089283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4090e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4091e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4092e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4093e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4094704052f5SChia-Yuan Li rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4095e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4096e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4097d592b9f7SPo-Hao Huang rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4098fb2b8cecSPo-Hao Huang rtw89_mac_port_tsf_resync_all(rtwdev); 4099e3ec7017SPing-Ke Shih fsleep(BCN_ERLY_SET_DLY); 4100e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4101e3ec7017SPing-Ke Shih 4102e3ec7017SPing-Ke Shih return 0; 4103e3ec7017SPing-Ke Shih } 4104e3ec7017SPing-Ke Shih 410576f478a3SZong-Zhe Yang int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 410676f478a3SZong-Zhe Yang u64 *tsf) 410776f478a3SZong-Zhe Yang { 410876f478a3SZong-Zhe Yang const struct rtw89_port_reg *p = &rtw_port_base; 410976f478a3SZong-Zhe Yang u32 tsf_low, tsf_high; 411076f478a3SZong-Zhe Yang int ret; 411176f478a3SZong-Zhe Yang 411276f478a3SZong-Zhe Yang ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 411376f478a3SZong-Zhe Yang if (ret) 411476f478a3SZong-Zhe Yang return ret; 411576f478a3SZong-Zhe Yang 411676f478a3SZong-Zhe Yang tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 411776f478a3SZong-Zhe Yang tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 411876f478a3SZong-Zhe Yang *tsf = (u64)tsf_high << 32 | tsf_low; 411976f478a3SZong-Zhe Yang 412076f478a3SZong-Zhe Yang return 0; 412176f478a3SZong-Zhe Yang } 412276f478a3SZong-Zhe Yang 41238d540f9dSKuan-Chung Chen static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 41248d540f9dSKuan-Chung Chen struct cfg80211_bss *bss, 41258d540f9dSKuan-Chung Chen void *data) 41268d540f9dSKuan-Chung Chen { 41278d540f9dSKuan-Chung Chen const struct cfg80211_bss_ies *ies; 41288d540f9dSKuan-Chung Chen const struct element *elem; 41298d540f9dSKuan-Chung Chen bool *tolerated = data; 41308d540f9dSKuan-Chung Chen 41318d540f9dSKuan-Chung Chen rcu_read_lock(); 41328d540f9dSKuan-Chung Chen ies = rcu_dereference(bss->ies); 41338d540f9dSKuan-Chung Chen elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 41348d540f9dSKuan-Chung Chen ies->len); 41358d540f9dSKuan-Chung Chen 41368d540f9dSKuan-Chung Chen if (!elem || elem->datalen < 10 || 41378d540f9dSKuan-Chung Chen !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 41388d540f9dSKuan-Chung Chen *tolerated = false; 41398d540f9dSKuan-Chung Chen rcu_read_unlock(); 41408d540f9dSKuan-Chung Chen } 41418d540f9dSKuan-Chung Chen 41428d540f9dSKuan-Chung Chen void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 41438d540f9dSKuan-Chung Chen struct ieee80211_vif *vif) 41448d540f9dSKuan-Chung Chen { 41458d540f9dSKuan-Chung Chen struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 41468d540f9dSKuan-Chung Chen struct ieee80211_hw *hw = rtwdev->hw; 41478d540f9dSKuan-Chung Chen bool tolerated = true; 41488d540f9dSKuan-Chung Chen u32 reg; 41498d540f9dSKuan-Chung Chen 41508d540f9dSKuan-Chung Chen if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 41518d540f9dSKuan-Chung Chen return; 41528d540f9dSKuan-Chung Chen 41538d540f9dSKuan-Chung Chen if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR)) 41548d540f9dSKuan-Chung Chen return; 41558d540f9dSKuan-Chung Chen 41568d540f9dSKuan-Chung Chen cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef, 41578d540f9dSKuan-Chung Chen rtw89_mac_check_he_obss_narrow_bw_ru_iter, 41588d540f9dSKuan-Chung Chen &tolerated); 41598d540f9dSKuan-Chung Chen 41608d540f9dSKuan-Chung Chen reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); 41618d540f9dSKuan-Chung Chen if (tolerated) 41628d540f9dSKuan-Chung Chen rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 41638d540f9dSKuan-Chung Chen else 41648d540f9dSKuan-Chung Chen rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 41658d540f9dSKuan-Chung Chen } 41668d540f9dSKuan-Chung Chen 4167d592b9f7SPo-Hao Huang void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4168d592b9f7SPo-Hao Huang { 4169d592b9f7SPo-Hao Huang rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false); 4170d592b9f7SPo-Hao Huang } 4171d592b9f7SPo-Hao Huang 4172e3ec7017SPing-Ke Shih int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4173e3ec7017SPing-Ke Shih { 4174e3ec7017SPing-Ke Shih int ret; 4175e3ec7017SPing-Ke Shih 4176e3ec7017SPing-Ke Shih rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 4177e3ec7017SPing-Ke Shih RTW89_MAX_MAC_ID_NUM); 4178e3ec7017SPing-Ke Shih if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4179e3ec7017SPing-Ke Shih return -ENOSPC; 4180e3ec7017SPing-Ke Shih 4181e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4182e3ec7017SPing-Ke Shih if (ret) 4183e3ec7017SPing-Ke Shih goto release_mac_id; 4184e3ec7017SPing-Ke Shih 4185e3ec7017SPing-Ke Shih return 0; 4186e3ec7017SPing-Ke Shih 4187e3ec7017SPing-Ke Shih release_mac_id: 4188e3ec7017SPing-Ke Shih rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4189e3ec7017SPing-Ke Shih 4190e3ec7017SPing-Ke Shih return ret; 4191e3ec7017SPing-Ke Shih } 4192e3ec7017SPing-Ke Shih 4193e3ec7017SPing-Ke Shih int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4194e3ec7017SPing-Ke Shih { 4195e3ec7017SPing-Ke Shih int ret; 4196e3ec7017SPing-Ke Shih 4197e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4198e3ec7017SPing-Ke Shih rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4199e3ec7017SPing-Ke Shih 4200e3ec7017SPing-Ke Shih return ret; 4201e3ec7017SPing-Ke Shih } 4202e3ec7017SPing-Ke Shih 4203e3ec7017SPing-Ke Shih static void 4204e3ec7017SPing-Ke Shih rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4205e3ec7017SPing-Ke Shih { 4206e3ec7017SPing-Ke Shih } 4207e3ec7017SPing-Ke Shih 420889590777SPo Hao Huang static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 420989590777SPo Hao Huang { 4210e7399db2SPo-Hao Huang const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 421189590777SPo Hao Huang 4212e7399db2SPo-Hao Huang return band == op->band_type && channel == op->primary_channel; 421389590777SPo Hao Huang } 421489590777SPo Hao Huang 421589590777SPo Hao Huang static void 421689590777SPo Hao Huang rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 421789590777SPo Hao Huang u32 len) 421889590777SPo Hao Huang { 421989590777SPo Hao Huang struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4220bd1056d4SPo-Hao Huang struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4221cbb145b9SZong-Zhe Yang struct rtw89_chan new; 42223a1e7cb1SPo-Hao Huang u8 reason, status, tx_fail, band, actual_period; 4223bd1056d4SPo-Hao Huang u32 last_chan = rtwdev->scan_info.last_chan_idx; 422489590777SPo Hao Huang u16 chan; 4225bd1056d4SPo-Hao Huang int ret; 422689590777SPo Hao Huang 4227a0e97ae3SPo-Hao Huang if (!rtwvif) 4228a0e97ae3SPo-Hao Huang return; 4229a0e97ae3SPo-Hao Huang 423089590777SPo Hao Huang tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 423189590777SPo Hao Huang status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 423289590777SPo Hao Huang chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 423389590777SPo Hao Huang reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 423489590777SPo Hao Huang band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 42353a1e7cb1SPo-Hao Huang actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data); 423689590777SPo Hao Huang 423789590777SPo Hao Huang if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 423889590777SPo Hao Huang band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 423989590777SPo Hao Huang 424089590777SPo Hao Huang rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 42413a1e7cb1SPo-Hao Huang "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 42423a1e7cb1SPo-Hao Huang band, chan, reason, status, tx_fail, actual_period); 424389590777SPo Hao Huang 424489590777SPo Hao Huang switch (reason) { 424589590777SPo Hao Huang case RTW89_SCAN_LEAVE_CH_NOTIFY: 424689590777SPo Hao Huang if (rtw89_is_op_chan(rtwdev, band, chan)) 424789590777SPo Hao Huang ieee80211_stop_queues(rtwdev->hw); 424889590777SPo Hao Huang return; 424989590777SPo Hao Huang case RTW89_SCAN_END_SCAN_NOTIFY: 4250bd1056d4SPo-Hao Huang if (rtwvif && rtwvif->scan_req && 4251bd1056d4SPo-Hao Huang last_chan < rtwvif->scan_req->n_channels) { 4252bd1056d4SPo-Hao Huang ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4253bd1056d4SPo-Hao Huang if (ret) { 4254bd1056d4SPo-Hao Huang rtw89_hw_scan_abort(rtwdev, vif); 4255bd1056d4SPo-Hao Huang rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4256bd1056d4SPo-Hao Huang } 4257bd1056d4SPo-Hao Huang } else { 425889590777SPo Hao Huang rtw89_hw_scan_complete(rtwdev, vif, false); 4259bd1056d4SPo-Hao Huang } 426089590777SPo Hao Huang break; 426189590777SPo Hao Huang case RTW89_SCAN_ENTER_CH_NOTIFY: 426228000f7bSPo Hao Huang if (rtw89_is_op_chan(rtwdev, band, chan)) { 4263e7399db2SPo-Hao Huang rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4264e7399db2SPo-Hao Huang &rtwdev->scan_info.op_chan); 426589590777SPo Hao Huang ieee80211_wake_queues(rtwdev->hw); 4266e7399db2SPo-Hao Huang } else { 4267e7399db2SPo-Hao Huang rtw89_chan_create(&new, chan, chan, band, 4268e7399db2SPo-Hao Huang RTW89_CHANNEL_WIDTH_20); 4269e7399db2SPo-Hao Huang rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4270e7399db2SPo-Hao Huang &new); 427128000f7bSPo Hao Huang } 427289590777SPo Hao Huang break; 427389590777SPo Hao Huang default: 427489590777SPo Hao Huang return; 427589590777SPo Hao Huang } 427689590777SPo Hao Huang } 427789590777SPo Hao Huang 4278e3ec7017SPing-Ke Shih static void 4279d2b6da24SPo-Hao Huang rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4280d2b6da24SPo-Hao Huang struct sk_buff *skb) 4281d2b6da24SPo-Hao Huang { 4282d2b6da24SPo-Hao Huang struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4283d2b6da24SPo-Hao Huang enum nl80211_cqm_rssi_threshold_event nl_event; 4284d2b6da24SPo-Hao Huang const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4285d2b6da24SPo-Hao Huang (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4286d2b6da24SPo-Hao Huang u8 type, event, mac_id; 4287d2b6da24SPo-Hao Huang s8 sig; 4288d2b6da24SPo-Hao Huang 4289d2b6da24SPo-Hao Huang type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4290d2b6da24SPo-Hao Huang sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4291d2b6da24SPo-Hao Huang event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4292d2b6da24SPo-Hao Huang mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4293d2b6da24SPo-Hao Huang 4294d2b6da24SPo-Hao Huang if (mac_id != rtwvif->mac_id) 4295d2b6da24SPo-Hao Huang return; 4296d2b6da24SPo-Hao Huang 4297d2b6da24SPo-Hao Huang rtw89_debug(rtwdev, RTW89_DBG_FW, 4298d2b6da24SPo-Hao Huang "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4299d2b6da24SPo-Hao Huang mac_id, type, sig, event); 4300d2b6da24SPo-Hao Huang 4301d2b6da24SPo-Hao Huang switch (type) { 4302d2b6da24SPo-Hao Huang case RTW89_BCN_FLTR_BEACON_LOSS: 4303a0e97ae3SPo-Hao Huang if (!rtwdev->scanning && !rtwvif->offchan) 4304d2b6da24SPo-Hao Huang ieee80211_connection_loss(vif); 4305d2b6da24SPo-Hao Huang else 4306d2b6da24SPo-Hao Huang rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4307d2b6da24SPo-Hao Huang return; 4308d2b6da24SPo-Hao Huang case RTW89_BCN_FLTR_NOTIFY: 4309d2b6da24SPo-Hao Huang nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4310d2b6da24SPo-Hao Huang break; 4311d2b6da24SPo-Hao Huang case RTW89_BCN_FLTR_RSSI: 4312d2b6da24SPo-Hao Huang if (event == RTW89_BCN_FLTR_RSSI_LOW) 4313d2b6da24SPo-Hao Huang nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4314d2b6da24SPo-Hao Huang else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4315d2b6da24SPo-Hao Huang nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4316d2b6da24SPo-Hao Huang else 4317d2b6da24SPo-Hao Huang return; 4318d2b6da24SPo-Hao Huang break; 4319d2b6da24SPo-Hao Huang default: 4320d2b6da24SPo-Hao Huang return; 4321d2b6da24SPo-Hao Huang } 4322d2b6da24SPo-Hao Huang 4323d2b6da24SPo-Hao Huang ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4324d2b6da24SPo-Hao Huang } 4325d2b6da24SPo-Hao Huang 4326d2b6da24SPo-Hao Huang static void 4327d2b6da24SPo-Hao Huang rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4328d2b6da24SPo-Hao Huang u32 len) 4329d2b6da24SPo-Hao Huang { 4330d2b6da24SPo-Hao Huang struct rtw89_vif *rtwvif; 4331d2b6da24SPo-Hao Huang 4332d2b6da24SPo-Hao Huang rtw89_for_each_rtwvif(rtwdev, rtwvif) 4333d2b6da24SPo-Hao Huang rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4334d2b6da24SPo-Hao Huang } 4335d2b6da24SPo-Hao Huang 4336d2b6da24SPo-Hao Huang static void 4337e3ec7017SPing-Ke Shih rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4338e3ec7017SPing-Ke Shih { 4339e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 4340e3ec7017SPing-Ke Shih "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4341e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4342e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4343e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4344e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4345e3ec7017SPing-Ke Shih } 4346e3ec7017SPing-Ke Shih 4347e3ec7017SPing-Ke Shih static void 4348e3ec7017SPing-Ke Shih rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4349e3ec7017SPing-Ke Shih { 4350e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 4351e3ec7017SPing-Ke Shih "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4352e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data), 4353e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data), 4354e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data), 4355e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data), 4356e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data)); 4357e3ec7017SPing-Ke Shih } 4358e3ec7017SPing-Ke Shih 4359e3ec7017SPing-Ke Shih static void 4360e3ec7017SPing-Ke Shih rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4361e3ec7017SPing-Ke Shih { 4362e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), 4363e3ec7017SPing-Ke Shih RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); 4364e3ec7017SPing-Ke Shih } 4365e3ec7017SPing-Ke Shih 4366fccca934SPing-Ke Shih static void 4367fccca934SPing-Ke Shih rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4368fccca934SPing-Ke Shih { 4369fccca934SPing-Ke Shih } 4370fccca934SPing-Ke Shih 43712b8219e9SPo Hao Huang static void 43722b8219e9SPo Hao Huang rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 43732b8219e9SPo Hao Huang u32 len) 43742b8219e9SPo Hao Huang { 43752b8219e9SPo Hao Huang } 43762b8219e9SPo Hao Huang 4377f4a43c3bSDian-Syuan Yang static void 4378f4a43c3bSDian-Syuan Yang rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4379f4a43c3bSDian-Syuan Yang u32 len) 4380f4a43c3bSDian-Syuan Yang { 4381f4a43c3bSDian-Syuan Yang } 4382f4a43c3bSDian-Syuan Yang 4383ef9dff4cSZong-Zhe Yang static void 4384ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4385ef9dff4cSZong-Zhe Yang { 4386ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4387ef9dff4cSZong-Zhe Yang u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4388ef9dff4cSZong-Zhe Yang 4389ef9dff4cSZong-Zhe Yang switch (func) { 4390ef9dff4cSZong-Zhe Yang case H2C_FUNC_ADD_MCC: 4391ef9dff4cSZong-Zhe Yang case H2C_FUNC_START_MCC: 4392ef9dff4cSZong-Zhe Yang case H2C_FUNC_STOP_MCC: 4393ef9dff4cSZong-Zhe Yang case H2C_FUNC_DEL_MCC_GROUP: 4394ef9dff4cSZong-Zhe Yang case H2C_FUNC_RESET_MCC_GROUP: 4395ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_REQ_TSF: 4396ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_MACID_BITMAP: 4397ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SYNC: 4398ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SET_DURATION: 4399ef9dff4cSZong-Zhe Yang break; 4400ef9dff4cSZong-Zhe Yang default: 4401214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4402ef9dff4cSZong-Zhe Yang "invalid MCC C2H RCV ACK: func %d\n", func); 4403ef9dff4cSZong-Zhe Yang return; 4404ef9dff4cSZong-Zhe Yang } 4405ef9dff4cSZong-Zhe Yang 4406214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4407ef9dff4cSZong-Zhe Yang "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4408ef9dff4cSZong-Zhe Yang } 4409ef9dff4cSZong-Zhe Yang 4410ef9dff4cSZong-Zhe Yang static void 4411ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4412ef9dff4cSZong-Zhe Yang { 4413ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4414ef9dff4cSZong-Zhe Yang u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4415ef9dff4cSZong-Zhe Yang u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4416ef9dff4cSZong-Zhe Yang struct rtw89_completion_data data = {}; 4417ef9dff4cSZong-Zhe Yang unsigned int cond; 4418ef9dff4cSZong-Zhe Yang bool next = false; 4419ef9dff4cSZong-Zhe Yang 4420ef9dff4cSZong-Zhe Yang switch (func) { 4421ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_REQ_TSF: 4422ef9dff4cSZong-Zhe Yang next = true; 4423ef9dff4cSZong-Zhe Yang break; 4424ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_MACID_BITMAP: 4425ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SYNC: 4426ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SET_DURATION: 4427ef9dff4cSZong-Zhe Yang break; 4428ef9dff4cSZong-Zhe Yang case H2C_FUNC_ADD_MCC: 4429ef9dff4cSZong-Zhe Yang case H2C_FUNC_START_MCC: 4430ef9dff4cSZong-Zhe Yang case H2C_FUNC_STOP_MCC: 4431ef9dff4cSZong-Zhe Yang case H2C_FUNC_DEL_MCC_GROUP: 4432ef9dff4cSZong-Zhe Yang case H2C_FUNC_RESET_MCC_GROUP: 4433ef9dff4cSZong-Zhe Yang default: 4434214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4435ef9dff4cSZong-Zhe Yang "invalid MCC C2H REQ ACK: func %d\n", func); 4436ef9dff4cSZong-Zhe Yang return; 4437ef9dff4cSZong-Zhe Yang } 4438ef9dff4cSZong-Zhe Yang 4439214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4440ef9dff4cSZong-Zhe Yang "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 4441ef9dff4cSZong-Zhe Yang group, func, retcode); 4442ef9dff4cSZong-Zhe Yang 4443ef9dff4cSZong-Zhe Yang if (!retcode && next) 4444ef9dff4cSZong-Zhe Yang return; 4445ef9dff4cSZong-Zhe Yang 4446ef9dff4cSZong-Zhe Yang data.err = !!retcode; 4447ef9dff4cSZong-Zhe Yang cond = RTW89_MCC_WAIT_COND(group, func); 4448ef9dff4cSZong-Zhe Yang rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4449ef9dff4cSZong-Zhe Yang } 4450ef9dff4cSZong-Zhe Yang 4451ef9dff4cSZong-Zhe Yang static void 4452ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4453ef9dff4cSZong-Zhe Yang { 4454ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 4455ef9dff4cSZong-Zhe Yang struct rtw89_completion_data data = {}; 4456ef9dff4cSZong-Zhe Yang struct rtw89_mac_mcc_tsf_rpt *rpt; 4457ef9dff4cSZong-Zhe Yang unsigned int cond; 4458ef9dff4cSZong-Zhe Yang 4459ef9dff4cSZong-Zhe Yang rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 4460ef9dff4cSZong-Zhe Yang rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 4461ef9dff4cSZong-Zhe Yang rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 4462ef9dff4cSZong-Zhe Yang rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 4463ef9dff4cSZong-Zhe Yang rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 4464ef9dff4cSZong-Zhe Yang rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 4465ef9dff4cSZong-Zhe Yang rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 4466ef9dff4cSZong-Zhe Yang 4467214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4468214a98b1SZong-Zhe Yang "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 4469214a98b1SZong-Zhe Yang rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 4470214a98b1SZong-Zhe Yang rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 4471214a98b1SZong-Zhe Yang 4472ef9dff4cSZong-Zhe Yang cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 4473ef9dff4cSZong-Zhe Yang rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4474ef9dff4cSZong-Zhe Yang } 4475ef9dff4cSZong-Zhe Yang 4476ef9dff4cSZong-Zhe Yang static void 4477ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4478ef9dff4cSZong-Zhe Yang { 4479ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 4480ef9dff4cSZong-Zhe Yang u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 4481ef9dff4cSZong-Zhe Yang u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 4482ef9dff4cSZong-Zhe Yang u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 4483ef9dff4cSZong-Zhe Yang u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 4484ef9dff4cSZong-Zhe Yang struct rtw89_completion_data data = {}; 4485ef9dff4cSZong-Zhe Yang unsigned int cond; 4486ef9dff4cSZong-Zhe Yang bool rsp = true; 4487ef9dff4cSZong-Zhe Yang bool err; 4488ef9dff4cSZong-Zhe Yang u8 func; 4489ef9dff4cSZong-Zhe Yang 4490ef9dff4cSZong-Zhe Yang switch (status) { 4491ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_ADD_ROLE_OK: 4492ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_ADD_ROLE_FAIL: 4493ef9dff4cSZong-Zhe Yang func = H2C_FUNC_ADD_MCC; 4494ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 4495ef9dff4cSZong-Zhe Yang break; 4496ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_START_GROUP_OK: 4497ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_START_GROUP_FAIL: 4498ef9dff4cSZong-Zhe Yang func = H2C_FUNC_START_MCC; 4499ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 4500ef9dff4cSZong-Zhe Yang break; 4501ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_STOP_GROUP_OK: 4502ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_STOP_GROUP_FAIL: 4503ef9dff4cSZong-Zhe Yang func = H2C_FUNC_STOP_MCC; 4504ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 4505ef9dff4cSZong-Zhe Yang break; 4506ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DEL_GROUP_OK: 4507ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DEL_GROUP_FAIL: 4508ef9dff4cSZong-Zhe Yang func = H2C_FUNC_DEL_MCC_GROUP; 4509ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 4510ef9dff4cSZong-Zhe Yang break; 4511ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_RESET_GROUP_OK: 4512ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_RESET_GROUP_FAIL: 4513ef9dff4cSZong-Zhe Yang func = H2C_FUNC_RESET_MCC_GROUP; 4514ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 4515ef9dff4cSZong-Zhe Yang break; 4516ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_SWITCH_CH_OK: 4517ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_SWITCH_CH_FAIL: 4518ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL0_OK: 4519ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL0_FAIL: 4520ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL1_OK: 4521ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL1_FAIL: 4522ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_SWITCH_EARLY: 4523ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TBTT: 4524ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DURATION_START: 4525ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DURATION_END: 4526ef9dff4cSZong-Zhe Yang rsp = false; 4527ef9dff4cSZong-Zhe Yang break; 4528ef9dff4cSZong-Zhe Yang default: 4529214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4530ef9dff4cSZong-Zhe Yang "invalid MCC C2H STS RPT: status %d\n", status); 4531ef9dff4cSZong-Zhe Yang return; 4532ef9dff4cSZong-Zhe Yang } 4533ef9dff4cSZong-Zhe Yang 4534214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4535214a98b1SZong-Zhe Yang "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 4536214a98b1SZong-Zhe Yang group, macid, status, (u64)tsf_high << 32 | tsf_low); 4537ef9dff4cSZong-Zhe Yang 4538ef9dff4cSZong-Zhe Yang if (!rsp) 4539ef9dff4cSZong-Zhe Yang return; 4540ef9dff4cSZong-Zhe Yang 4541ef9dff4cSZong-Zhe Yang data.err = err; 4542ef9dff4cSZong-Zhe Yang cond = RTW89_MCC_WAIT_COND(group, func); 4543ef9dff4cSZong-Zhe Yang rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4544ef9dff4cSZong-Zhe Yang } 4545ef9dff4cSZong-Zhe Yang 4546e3ec7017SPing-Ke Shih static 4547e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 4548e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 4549e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 4550e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 45512b8219e9SPo Hao Huang [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 4552e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 4553e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 455489590777SPo Hao Huang [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 4555f4a43c3bSDian-Syuan Yang [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 4556d2b6da24SPo-Hao Huang [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 4557e3ec7017SPing-Ke Shih }; 4558e3ec7017SPing-Ke Shih 4559e3ec7017SPing-Ke Shih static 4560e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 4561e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 4562e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 4563e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 4564e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 4565fccca934SPing-Ke Shih [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 4566e3ec7017SPing-Ke Shih }; 4567e3ec7017SPing-Ke Shih 4568ef9dff4cSZong-Zhe Yang static 4569ef9dff4cSZong-Zhe Yang void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 4570ef9dff4cSZong-Zhe Yang struct sk_buff *c2h, u32 len) = { 4571ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 4572ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 4573ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 4574ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 4575ef9dff4cSZong-Zhe Yang }; 4576ef9dff4cSZong-Zhe Yang 4577860e8263SZong-Zhe Yang bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 4578860e8263SZong-Zhe Yang { 4579860e8263SZong-Zhe Yang switch (class) { 4580860e8263SZong-Zhe Yang default: 4581860e8263SZong-Zhe Yang return false; 4582860e8263SZong-Zhe Yang case RTW89_MAC_C2H_CLASS_MCC: 4583860e8263SZong-Zhe Yang return true; 4584860e8263SZong-Zhe Yang } 4585860e8263SZong-Zhe Yang } 4586860e8263SZong-Zhe Yang 4587e3ec7017SPing-Ke Shih void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4588e3ec7017SPing-Ke Shih u32 len, u8 class, u8 func) 4589e3ec7017SPing-Ke Shih { 4590e3ec7017SPing-Ke Shih void (*handler)(struct rtw89_dev *rtwdev, 4591e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = NULL; 4592e3ec7017SPing-Ke Shih 4593e3ec7017SPing-Ke Shih switch (class) { 4594e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_INFO: 4595e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 4596e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_info_handler[func]; 4597e3ec7017SPing-Ke Shih break; 4598e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_OFLD: 4599e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 4600e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_ofld_handler[func]; 4601e3ec7017SPing-Ke Shih break; 4602ef9dff4cSZong-Zhe Yang case RTW89_MAC_C2H_CLASS_MCC: 4603ef9dff4cSZong-Zhe Yang if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 4604ef9dff4cSZong-Zhe Yang handler = rtw89_mac_c2h_mcc_handler[func]; 4605ef9dff4cSZong-Zhe Yang break; 4606e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_FWDBG: 4607e3ec7017SPing-Ke Shih return; 4608e3ec7017SPing-Ke Shih default: 4609e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d not support\n", class); 4610e3ec7017SPing-Ke Shih return; 4611e3ec7017SPing-Ke Shih } 4612e3ec7017SPing-Ke Shih if (!handler) { 4613e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 4614e3ec7017SPing-Ke Shih func); 4615e3ec7017SPing-Ke Shih return; 4616e3ec7017SPing-Ke Shih } 4617e3ec7017SPing-Ke Shih handler(rtwdev, skb, len); 4618e3ec7017SPing-Ke Shih } 4619e3ec7017SPing-Ke Shih 4620e3ec7017SPing-Ke Shih bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 4621e3ec7017SPing-Ke Shih enum rtw89_phy_idx phy_idx, 4622e3ec7017SPing-Ke Shih u32 reg_base, u32 *cr) 4623e3ec7017SPing-Ke Shih { 4624e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 4625e3ec7017SPing-Ke Shih enum rtw89_qta_mode mode = dle_mem->mode; 4626e3ec7017SPing-Ke Shih u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); 4627e3ec7017SPing-Ke Shih 4628e3ec7017SPing-Ke Shih if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { 4629e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 4630e3ec7017SPing-Ke Shih addr); 4631e3ec7017SPing-Ke Shih goto error; 4632e3ec7017SPing-Ke Shih } 4633e3ec7017SPing-Ke Shih 4634e3ec7017SPing-Ke Shih if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) 4635e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_SCC) { 4636e3ec7017SPing-Ke Shih rtw89_err(rtwdev, 4637e3ec7017SPing-Ke Shih "[TXPWR] addr=0x%x but hw not enable\n", 4638e3ec7017SPing-Ke Shih addr); 4639e3ec7017SPing-Ke Shih goto error; 4640e3ec7017SPing-Ke Shih } 4641e3ec7017SPing-Ke Shih 4642e3ec7017SPing-Ke Shih *cr = addr; 4643e3ec7017SPing-Ke Shih return true; 4644e3ec7017SPing-Ke Shih 4645e3ec7017SPing-Ke Shih error: 4646e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 4647e3ec7017SPing-Ke Shih addr, phy_idx); 4648e3ec7017SPing-Ke Shih 4649e3ec7017SPing-Ke Shih return false; 4650e3ec7017SPing-Ke Shih } 4651861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); 4652e3ec7017SPing-Ke Shih 4653e3ec7017SPing-Ke Shih int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 4654e3ec7017SPing-Ke Shih { 4655e3ec7017SPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); 465621087188SPing-Ke Shih int ret; 4657e3ec7017SPing-Ke Shih 4658e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4659e3ec7017SPing-Ke Shih if (ret) 4660e3ec7017SPing-Ke Shih return ret; 4661e3ec7017SPing-Ke Shih 4662e3ec7017SPing-Ke Shih if (!enable) { 4663e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 466421087188SPing-Ke Shih return 0; 4665e3ec7017SPing-Ke Shih } 4666e3ec7017SPing-Ke Shih 4667e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 4668e3ec7017SPing-Ke Shih B_AX_APP_MAC_INFO_RPT | 4669e3ec7017SPing-Ke Shih B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 4670e3ec7017SPing-Ke Shih B_AX_PPDU_STAT_RPT_CRC32); 4671e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 4672e3ec7017SPing-Ke Shih RTW89_PRPT_DEST_HOST); 4673e3ec7017SPing-Ke Shih 467421087188SPing-Ke Shih return 0; 4675e3ec7017SPing-Ke Shih } 4676861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 4677e3ec7017SPing-Ke Shih 4678e3ec7017SPing-Ke Shih void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 4679e3ec7017SPing-Ke Shih { 4680e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_SH 5 4681e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_SH 4 4682e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_MAX 255 4683e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_MAX 255 4684e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_DEF 88 4685e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_DEF 4080 4686e3ec7017SPing-Ke Shih struct ieee80211_hw *hw = rtwdev->hw; 4687e3ec7017SPing-Ke Shih u32 rts_threshold = hw->wiphy->rts_threshold; 4688e3ec7017SPing-Ke Shih u32 time_th, len_th; 4689e3ec7017SPing-Ke Shih u32 reg; 4690e3ec7017SPing-Ke Shih 4691e3ec7017SPing-Ke Shih if (rts_threshold == (u32)-1) { 4692e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_DEF; 4693e3ec7017SPing-Ke Shih len_th = MAC_AX_LEN_TH_DEF; 4694e3ec7017SPing-Ke Shih } else { 4695e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 4696e3ec7017SPing-Ke Shih len_th = rts_threshold; 4697e3ec7017SPing-Ke Shih } 4698e3ec7017SPing-Ke Shih 4699e3ec7017SPing-Ke Shih time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 4700e3ec7017SPing-Ke Shih len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 4701e3ec7017SPing-Ke Shih 4702e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); 4703e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 4704e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 4705e3ec7017SPing-Ke Shih } 4706e3ec7017SPing-Ke Shih 4707e3ec7017SPing-Ke Shih void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 4708e3ec7017SPing-Ke Shih { 4709e3ec7017SPing-Ke Shih bool empty; 4710e3ec7017SPing-Ke Shih int ret; 4711e3ec7017SPing-Ke Shih 4712e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4713e3ec7017SPing-Ke Shih return; 4714e3ec7017SPing-Ke Shih 4715e3ec7017SPing-Ke Shih ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 4716e3ec7017SPing-Ke Shih 10000, 200000, false, rtwdev); 4717e3ec7017SPing-Ke Shih if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 4718e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "timed out to flush queues\n"); 4719e3ec7017SPing-Ke Shih } 4720e3ec7017SPing-Ke Shih 4721e3ec7017SPing-Ke Shih int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 4722e3ec7017SPing-Ke Shih { 4723e3ec7017SPing-Ke Shih u8 val; 4724e3ec7017SPing-Ke Shih u16 val16; 4725e3ec7017SPing-Ke Shih u32 val32; 4726e3ec7017SPing-Ke Shih int ret; 4727e3ec7017SPing-Ke Shih 4728e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 47295c3afcbaSPing-Ke Shih if (rtwdev->chip->chip_id != RTL8851B) 4730e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 4731e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 4732e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 4733e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 47345c3afcbaSPing-Ke Shih if (rtwdev->chip->chip_id != RTL8851B) 4735e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 4736e3ec7017SPing-Ke Shih 4737e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 4738e3ec7017SPing-Ke Shih val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 4739e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 4740e3ec7017SPing-Ke Shih 4741e3ec7017SPing-Ke Shih ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 4742e3ec7017SPing-Ke Shih if (ret) { 4743e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 4744e3ec7017SPing-Ke Shih return ret; 4745e3ec7017SPing-Ke Shih } 4746e3ec7017SPing-Ke Shih val32 = val32 & B_AX_WL_RX_CTRL; 4747e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 4748e3ec7017SPing-Ke Shih if (ret) { 4749e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 4750e3ec7017SPing-Ke Shih return ret; 4751e3ec7017SPing-Ke Shih } 4752e3ec7017SPing-Ke Shih 4753e3ec7017SPing-Ke Shih switch (coex->pta_mode) { 4754e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_RTK_MODE: 4755e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4756e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 4757e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 4758e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4759e3ec7017SPing-Ke Shih 4760e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 4761e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 4762e3ec7017SPing-Ke Shih 4763e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 4764e3ec7017SPing-Ke Shih val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 4765e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 4766e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 4767e3ec7017SPing-Ke Shih break; 4768e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_CSR_MODE: 4769e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4770e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 4771e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 4772e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4773e3ec7017SPing-Ke Shih 4774e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 4775e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 4776e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 4777e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 4778e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 4779e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_STAT_DELAY_MASK; 4780e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 4781e3ec7017SPing-Ke Shih val16 |= B_AX_ENHANCED_BT; 4782e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 4783e3ec7017SPing-Ke Shih 4784e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 4785e3ec7017SPing-Ke Shih break; 4786e3ec7017SPing-Ke Shih default: 4787e3ec7017SPing-Ke Shih return -EINVAL; 4788e3ec7017SPing-Ke Shih } 4789e3ec7017SPing-Ke Shih 4790e3ec7017SPing-Ke Shih switch (coex->direction) { 4791e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INNER: 4792e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4793e3ec7017SPing-Ke Shih val = (val & ~BIT(2)) | BIT(1); 4794e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4795e3ec7017SPing-Ke Shih break; 4796e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_OUTPUT: 4797e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4798e3ec7017SPing-Ke Shih val = val | BIT(1) | BIT(0); 4799e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4800e3ec7017SPing-Ke Shih break; 4801e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INPUT: 4802e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4803e3ec7017SPing-Ke Shih val = val & ~(BIT(2) | BIT(1)); 4804e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4805e3ec7017SPing-Ke Shih break; 4806e3ec7017SPing-Ke Shih default: 4807e3ec7017SPing-Ke Shih return -EINVAL; 4808e3ec7017SPing-Ke Shih } 4809e3ec7017SPing-Ke Shih 4810e3ec7017SPing-Ke Shih return 0; 4811e3ec7017SPing-Ke Shih } 4812861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_coex_init); 4813e3ec7017SPing-Ke Shih 4814065cf8f9SChia-Yuan Li int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 4815065cf8f9SChia-Yuan Li const struct rtw89_mac_ax_coex *coex) 4816065cf8f9SChia-Yuan Li { 4817065cf8f9SChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 4818065cf8f9SChia-Yuan Li B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 4819065cf8f9SChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 4820065cf8f9SChia-Yuan Li rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 4821065cf8f9SChia-Yuan Li rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 4822065cf8f9SChia-Yuan Li 4823065cf8f9SChia-Yuan Li switch (coex->pta_mode) { 4824065cf8f9SChia-Yuan Li case RTW89_MAC_AX_COEX_RTK_MODE: 4825065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4826065cf8f9SChia-Yuan Li MAC_AX_RTK_MODE); 4827065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 4828065cf8f9SChia-Yuan Li B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 4829065cf8f9SChia-Yuan Li break; 4830065cf8f9SChia-Yuan Li case RTW89_MAC_AX_COEX_CSR_MODE: 4831065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4832065cf8f9SChia-Yuan Li MAC_AX_CSR_MODE); 4833065cf8f9SChia-Yuan Li break; 4834065cf8f9SChia-Yuan Li default: 4835065cf8f9SChia-Yuan Li return -EINVAL; 4836065cf8f9SChia-Yuan Li } 4837065cf8f9SChia-Yuan Li 4838065cf8f9SChia-Yuan Li return 0; 4839065cf8f9SChia-Yuan Li } 4840065cf8f9SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 4841065cf8f9SChia-Yuan Li 4842e3ec7017SPing-Ke Shih int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4843e3ec7017SPing-Ke Shih const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4844e3ec7017SPing-Ke Shih { 48458001c741SPing-Ke Shih u32 val = 0, ret; 4846e3ec7017SPing-Ke Shih 48478001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_bt) 48488001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 48498001c741SPing-Ke Shih 48508001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_bt_sw_en) 48518001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 48528001c741SPing-Ke Shih 48538001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_wl) 48548001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 48558001c741SPing-Ke Shih 48568001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_wl_sw_en) 48578001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 48588001c741SPing-Ke Shih 48598001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_bt) 48608001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 48618001c741SPing-Ke Shih 48628001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_bt_sw_en) 48638001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 48648001c741SPing-Ke Shih 48658001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_wl) 48668001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 48678001c741SPing-Ke Shih 48688001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_wl_sw_en) 48698001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 48708001c741SPing-Ke Shih 4871e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 4872e3ec7017SPing-Ke Shih if (ret) { 4873e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write LTE fail!\n"); 4874e3ec7017SPing-Ke Shih return ret; 4875e3ec7017SPing-Ke Shih } 4876e3ec7017SPing-Ke Shih 4877e3ec7017SPing-Ke Shih return 0; 4878e3ec7017SPing-Ke Shih } 4879feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 4880feed6541SChia-Yuan Li 4881feed6541SChia-Yuan Li int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 4882feed6541SChia-Yuan Li const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4883feed6541SChia-Yuan Li { 4884feed6541SChia-Yuan Li u32 val = 0; 4885feed6541SChia-Yuan Li 4886feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_bt) 4887feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 4888feed6541SChia-Yuan Li B_AX_GNT_BT_TX_VAL; 4889feed6541SChia-Yuan Li else 4890feed6541SChia-Yuan Li val |= B_AX_WL_ACT_VAL; 4891feed6541SChia-Yuan Li 4892feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_bt_sw_en) 4893feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4894feed6541SChia-Yuan Li B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4895feed6541SChia-Yuan Li 4896feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_wl) 4897feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 4898feed6541SChia-Yuan Li B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4899feed6541SChia-Yuan Li 4900feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_wl_sw_en) 4901feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4902feed6541SChia-Yuan Li B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4903feed6541SChia-Yuan Li 4904feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_bt) 4905feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 4906feed6541SChia-Yuan Li B_AX_GNT_BT_TX_VAL; 4907feed6541SChia-Yuan Li else 4908feed6541SChia-Yuan Li val |= B_AX_WL_ACT_VAL; 4909feed6541SChia-Yuan Li 4910feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_bt_sw_en) 4911feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4912feed6541SChia-Yuan Li B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4913feed6541SChia-Yuan Li 4914feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_wl) 4915feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 4916feed6541SChia-Yuan Li B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4917feed6541SChia-Yuan Li 4918feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_wl_sw_en) 4919feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4920feed6541SChia-Yuan Li B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4921feed6541SChia-Yuan Li 4922feed6541SChia-Yuan Li rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 4923feed6541SChia-Yuan Li 4924feed6541SChia-Yuan Li return 0; 4925feed6541SChia-Yuan Li } 4926feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 4927e3ec7017SPing-Ke Shih 4928e3ec7017SPing-Ke Shih int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 4929e3ec7017SPing-Ke Shih { 4930e3ec7017SPing-Ke Shih u32 reg; 493128e7ea8aSPing-Ke Shih u16 val; 4932e3ec7017SPing-Ke Shih int ret; 4933e3ec7017SPing-Ke Shih 4934e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 4935e3ec7017SPing-Ke Shih if (ret) 4936e3ec7017SPing-Ke Shih return ret; 4937e3ec7017SPing-Ke Shih 4938e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); 4939e3ec7017SPing-Ke Shih val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 4940e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 4941e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 4942e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 4943e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 4944e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 4945e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 494628e7ea8aSPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 494728e7ea8aSPing-Ke Shih B_AX_PLT_EN; 494828e7ea8aSPing-Ke Shih rtw89_write16(rtwdev, reg, val); 4949e3ec7017SPing-Ke Shih 4950e3ec7017SPing-Ke Shih return 0; 4951e3ec7017SPing-Ke Shih } 4952e3ec7017SPing-Ke Shih 4953e3ec7017SPing-Ke Shih void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 4954e3ec7017SPing-Ke Shih { 4955e3ec7017SPing-Ke Shih u32 fw_sb; 4956e3ec7017SPing-Ke Shih 4957e3ec7017SPing-Ke Shih fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4958e3ec7017SPing-Ke Shih fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 4959e3ec7017SPing-Ke Shih fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 4960e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4961e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 4962e3ec7017SPing-Ke Shih else 4963e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 4964e3ec7017SPing-Ke Shih val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 4965e3ec7017SPing-Ke Shih val = B_AX_TOGGLE | 4966e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 4967e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 4968e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 4969e3ec7017SPing-Ke Shih fsleep(1000); /* avoid BT FW loss information */ 4970e3ec7017SPing-Ke Shih } 4971e3ec7017SPing-Ke Shih 4972e3ec7017SPing-Ke Shih u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 4973e3ec7017SPing-Ke Shih { 4974e3ec7017SPing-Ke Shih return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4975e3ec7017SPing-Ke Shih } 4976e3ec7017SPing-Ke Shih 4977e3ec7017SPing-Ke Shih int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4978e3ec7017SPing-Ke Shih { 4979e3ec7017SPing-Ke Shih u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 4980e3ec7017SPing-Ke Shih 4981e3ec7017SPing-Ke Shih val = wl ? val | BIT(2) : val & ~BIT(2); 4982e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 4983e3ec7017SPing-Ke Shih 4984e3ec7017SPing-Ke Shih return 0; 4985e3ec7017SPing-Ke Shih } 4986feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 4987feed6541SChia-Yuan Li 4988feed6541SChia-Yuan Li int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 4989feed6541SChia-Yuan Li { 4990feed6541SChia-Yuan Li struct rtw89_btc *btc = &rtwdev->btc; 4991feed6541SChia-Yuan Li struct rtw89_btc_dm *dm = &btc->dm; 4992feed6541SChia-Yuan Li struct rtw89_mac_ax_gnt *g = dm->gnt.band; 4993feed6541SChia-Yuan Li int i; 4994feed6541SChia-Yuan Li 4995feed6541SChia-Yuan Li if (wl) 4996feed6541SChia-Yuan Li return 0; 4997feed6541SChia-Yuan Li 4998feed6541SChia-Yuan Li for (i = 0; i < RTW89_PHY_MAX; i++) { 4999feed6541SChia-Yuan Li g[i].gnt_bt_sw_en = 1; 5000feed6541SChia-Yuan Li g[i].gnt_bt = 1; 5001feed6541SChia-Yuan Li g[i].gnt_wl_sw_en = 1; 5002feed6541SChia-Yuan Li g[i].gnt_wl = 0; 5003feed6541SChia-Yuan Li } 5004feed6541SChia-Yuan Li 5005feed6541SChia-Yuan Li return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5006feed6541SChia-Yuan Li } 5007feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5008e3ec7017SPing-Ke Shih 5009e3ec7017SPing-Ke Shih bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5010e3ec7017SPing-Ke Shih { 5011ae4e1adbSChing-Te Ku const struct rtw89_chip_info *chip = rtwdev->chip; 5012ae4e1adbSChing-Te Ku u8 val = 0; 5013e3ec7017SPing-Ke Shih 5014ae4e1adbSChing-Te Ku if (chip->chip_id == RTL8852C) 5015ae4e1adbSChing-Te Ku return false; 5016ae4e1adbSChing-Te Ku else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 5017ae4e1adbSChing-Te Ku val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5018ae4e1adbSChing-Te Ku B_AX_LTE_MUX_CTRL_PATH >> 24); 5019ae4e1adbSChing-Te Ku 5020ae4e1adbSChing-Te Ku return !!val; 5021e3ec7017SPing-Ke Shih } 5022e3ec7017SPing-Ke Shih 50238c7e9cebSChing-Te Ku u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 50248c7e9cebSChing-Te Ku { 50258c7e9cebSChing-Te Ku u32 reg; 50268c7e9cebSChing-Te Ku u16 cnt; 50278c7e9cebSChing-Te Ku 50288c7e9cebSChing-Te Ku reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); 50298c7e9cebSChing-Te Ku cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 50308c7e9cebSChing-Te Ku rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 50318c7e9cebSChing-Te Ku 50328c7e9cebSChing-Te Ku return cnt; 50338c7e9cebSChing-Te Ku } 50348c7e9cebSChing-Te Ku 50358a66293eSPing-Ke Shih static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 50368a66293eSPing-Ke Shih bool keep) 50378a66293eSPing-Ke Shih { 50388a66293eSPing-Ke Shih u32 reg; 50398a66293eSPing-Ke Shih 50408a66293eSPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 50418a66293eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 50428a66293eSPing-Ke Shih if (keep) { 50438a66293eSPing-Ke Shih set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 50448a66293eSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 50458a66293eSPing-Ke Shih BFRP_RX_STANDBY_TIMER_KEEP); 50468a66293eSPing-Ke Shih } else { 50478a66293eSPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 50488a66293eSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 50498a66293eSPing-Ke Shih BFRP_RX_STANDBY_TIMER_RELEASE); 50508a66293eSPing-Ke Shih } 50518a66293eSPing-Ke Shih } 50528a66293eSPing-Ke Shih 5053e3ec7017SPing-Ke Shih static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5054e3ec7017SPing-Ke Shih { 5055e3ec7017SPing-Ke Shih u32 reg; 5056e3ec7017SPing-Ke Shih u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 5057e3ec7017SPing-Ke Shih B_AX_BFMEE_HE_NDPA_EN; 5058e3ec7017SPing-Ke Shih 5059e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5060e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 5061e3ec7017SPing-Ke Shih if (en) { 5062e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5063e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, mask); 5064e3ec7017SPing-Ke Shih } else { 5065e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5066e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, mask); 5067e3ec7017SPing-Ke Shih } 5068e3ec7017SPing-Ke Shih } 5069e3ec7017SPing-Ke Shih 5070e3ec7017SPing-Ke Shih static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 5071e3ec7017SPing-Ke Shih { 5072e3ec7017SPing-Ke Shih u32 reg; 5073e3ec7017SPing-Ke Shih u32 val32; 5074e3ec7017SPing-Ke Shih int ret; 5075e3ec7017SPing-Ke Shih 5076e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5077e3ec7017SPing-Ke Shih if (ret) 5078e3ec7017SPing-Ke Shih return ret; 5079e3ec7017SPing-Ke Shih 5080e3ec7017SPing-Ke Shih /* AP mode set tx gid to 63 */ 5081e3ec7017SPing-Ke Shih /* STA mode set tx gid to 0(default) */ 5082e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); 5083e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5084e3ec7017SPing-Ke Shih 5085e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5086e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5087e3ec7017SPing-Ke Shih 5088e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 50898a66293eSPing-Ke Shih val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5090e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 50918a66293eSPing-Ke Shih rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5092e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5093e3ec7017SPing-Ke Shih 5094e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5095e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5096e3ec7017SPing-Ke Shih B_AX_BFMEE_USE_NSTS | 5097e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_GID_SEL | 5098e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_FORCE_RETE_EN); 5099e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5100e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, 5101e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5102e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5103e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5104e3ec7017SPing-Ke Shih 510562440fbeSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_CSIRPT_OPTION, mac_idx); 510662440fbeSPing-Ke Shih rtw89_write32_set(rtwdev, reg, 510762440fbeSPing-Ke Shih B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 510862440fbeSPing-Ke Shih 5109e3ec7017SPing-Ke Shih return 0; 5110e3ec7017SPing-Ke Shih } 5111e3ec7017SPing-Ke Shih 5112e3ec7017SPing-Ke Shih static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 5113e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 5114e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5115e3ec7017SPing-Ke Shih { 5116e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5117e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 5118e3ec7017SPing-Ke Shih u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5119e3ec7017SPing-Ke Shih u8 port_sel = rtwvif->port; 5120e3ec7017SPing-Ke Shih u8 sound_dim = 3, t; 5121046d2e7cSSriram R u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5122e3ec7017SPing-Ke Shih u32 reg; 5123e3ec7017SPing-Ke Shih u16 val; 5124e3ec7017SPing-Ke Shih int ret; 5125e3ec7017SPing-Ke Shih 5126e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5127e3ec7017SPing-Ke Shih if (ret) 5128e3ec7017SPing-Ke Shih return ret; 5129e3ec7017SPing-Ke Shih 5130e3ec7017SPing-Ke Shih if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5131e3ec7017SPing-Ke Shih (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5132e3ec7017SPing-Ke Shih ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5133e3ec7017SPing-Ke Shih stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5134e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5135e3ec7017SPing-Ke Shih phy_cap[5]); 5136e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 5137e3ec7017SPing-Ke Shih } 5138046d2e7cSSriram R if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5139046d2e7cSSriram R (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5140046d2e7cSSriram R ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5141046d2e7cSSriram R stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5142e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5143046d2e7cSSriram R sta->deflink.vht_cap.cap); 5144e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 5145e3ec7017SPing-Ke Shih } 5146e3ec7017SPing-Ke Shih nc = min(nc, sound_dim); 5147e3ec7017SPing-Ke Shih nr = min(nr, sound_dim); 5148e3ec7017SPing-Ke Shih 5149e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5150e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5151e3ec7017SPing-Ke Shih 5152e3ec7017SPing-Ke Shih val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5153e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5154e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5155e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5156e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5157e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5158e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5159e3ec7017SPing-Ke Shih 5160e3ec7017SPing-Ke Shih if (port_sel == 0) 5161e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5162e3ec7017SPing-Ke Shih else 5163e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5164e3ec7017SPing-Ke Shih 5165e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 5166e3ec7017SPing-Ke Shih 5167e3ec7017SPing-Ke Shih return 0; 5168e3ec7017SPing-Ke Shih } 5169e3ec7017SPing-Ke Shih 5170e3ec7017SPing-Ke Shih static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 5171e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 5172e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5173e3ec7017SPing-Ke Shih { 5174e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5175e3ec7017SPing-Ke Shih u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5176e3ec7017SPing-Ke Shih u32 reg; 5177e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 5178e3ec7017SPing-Ke Shih int ret; 5179e3ec7017SPing-Ke Shih 5180e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5181e3ec7017SPing-Ke Shih if (ret) 5182e3ec7017SPing-Ke Shih return ret; 5183e3ec7017SPing-Ke Shih 5184046d2e7cSSriram R if (sta->deflink.he_cap.has_he) { 5185e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5186e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5187e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5188e3ec7017SPing-Ke Shih } 5189046d2e7cSSriram R if (sta->deflink.vht_cap.vht_supported) { 5190e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5191e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5192e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5193e3ec7017SPing-Ke Shih } 5194046d2e7cSSriram R if (sta->deflink.ht_cap.ht_supported) { 5195e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5196e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5197e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5198e3ec7017SPing-Ke Shih } 5199e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5200e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5201e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5202e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, 5203e3ec7017SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5204e3ec7017SPing-Ke Shih rrsc); 5205e3ec7017SPing-Ke Shih 5206e3ec7017SPing-Ke Shih return 0; 5207e3ec7017SPing-Ke Shih } 5208e3ec7017SPing-Ke Shih 5209e3ec7017SPing-Ke Shih void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5210e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5211e3ec7017SPing-Ke Shih { 5212e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5213e3ec7017SPing-Ke Shih 5214e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) { 5215e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, 5216e3ec7017SPing-Ke Shih "initialize bfee for new association\n"); 5217e3ec7017SPing-Ke Shih rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 5218e3ec7017SPing-Ke Shih rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 5219e3ec7017SPing-Ke Shih rtw89_mac_csi_rrsc(rtwdev, vif, sta); 5220e3ec7017SPing-Ke Shih } 5221e3ec7017SPing-Ke Shih } 5222e3ec7017SPing-Ke Shih 5223e3ec7017SPing-Ke Shih void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5224e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5225e3ec7017SPing-Ke Shih { 5226e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5227e3ec7017SPing-Ke Shih 5228e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 5229e3ec7017SPing-Ke Shih } 5230e3ec7017SPing-Ke Shih 5231e3ec7017SPing-Ke Shih void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5232e3ec7017SPing-Ke Shih struct ieee80211_bss_conf *conf) 5233e3ec7017SPing-Ke Shih { 5234e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5235e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 5236e3ec7017SPing-Ke Shih __le32 *p; 5237e3ec7017SPing-Ke Shih 5238e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 5239e3ec7017SPing-Ke Shih 5240e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.membership; 5241e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), 5242e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 5243e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), 5244e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 5245e3ec7017SPing-Ke Shih 5246e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.position; 5247e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), 5248e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 5249e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), 5250e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 5251e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), 5252e3ec7017SPing-Ke Shih le32_to_cpu(p[2])); 5253e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), 5254e3ec7017SPing-Ke Shih le32_to_cpu(p[3])); 5255e3ec7017SPing-Ke Shih } 5256e3ec7017SPing-Ke Shih 5257e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data { 5258e3ec7017SPing-Ke Shih struct rtw89_dev *rtwdev; 5259e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta; 5260e3ec7017SPing-Ke Shih int count; 5261e3ec7017SPing-Ke Shih }; 5262e3ec7017SPing-Ke Shih 5263e3ec7017SPing-Ke Shih static 5264e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 5265e3ec7017SPing-Ke Shih { 5266e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data *iter_data = 5267e3ec7017SPing-Ke Shih (struct rtw89_mac_bf_monitor_iter_data *)data; 5268e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta = iter_data->down_sta; 5269e3ec7017SPing-Ke Shih int *count = &iter_data->count; 5270e3ec7017SPing-Ke Shih 5271e3ec7017SPing-Ke Shih if (down_sta == sta) 5272e3ec7017SPing-Ke Shih return; 5273e3ec7017SPing-Ke Shih 5274e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) 5275e3ec7017SPing-Ke Shih (*count)++; 5276e3ec7017SPing-Ke Shih } 5277e3ec7017SPing-Ke Shih 5278e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 5279e3ec7017SPing-Ke Shih struct ieee80211_sta *sta, bool disconnect) 5280e3ec7017SPing-Ke Shih { 5281e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data data; 5282e3ec7017SPing-Ke Shih 5283e3ec7017SPing-Ke Shih data.rtwdev = rtwdev; 5284e3ec7017SPing-Ke Shih data.down_sta = disconnect ? sta : NULL; 5285e3ec7017SPing-Ke Shih data.count = 0; 5286e3ec7017SPing-Ke Shih ieee80211_iterate_stations_atomic(rtwdev->hw, 5287e3ec7017SPing-Ke Shih rtw89_mac_bf_monitor_calc_iter, 5288e3ec7017SPing-Ke Shih &data); 5289e3ec7017SPing-Ke Shih 5290e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 5291e3ec7017SPing-Ke Shih if (data.count) 5292e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5293e3ec7017SPing-Ke Shih else 5294e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5295e3ec7017SPing-Ke Shih } 5296e3ec7017SPing-Ke Shih 5297e3ec7017SPing-Ke Shih void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 5298e3ec7017SPing-Ke Shih { 5299e3ec7017SPing-Ke Shih struct rtw89_traffic_stats *stats = &rtwdev->stats; 5300e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif; 53011646ce8fSYe Guojin bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 5302e3ec7017SPing-Ke Shih bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 53038a66293eSPing-Ke Shih bool keep_timer = true; 53048a66293eSPing-Ke Shih bool old_keep_timer; 53058a66293eSPing-Ke Shih 53068a66293eSPing-Ke Shih old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 53078a66293eSPing-Ke Shih 53088a66293eSPing-Ke Shih if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 53098a66293eSPing-Ke Shih keep_timer = false; 53108a66293eSPing-Ke Shih 53118a66293eSPing-Ke Shih if (keep_timer != old_keep_timer) { 53128a66293eSPing-Ke Shih rtw89_for_each_rtwvif(rtwdev, rtwvif) 53138a66293eSPing-Ke Shih rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 53148a66293eSPing-Ke Shih keep_timer); 53158a66293eSPing-Ke Shih } 5316e3ec7017SPing-Ke Shih 5317e3ec7017SPing-Ke Shih if (en == old) 5318e3ec7017SPing-Ke Shih return; 5319e3ec7017SPing-Ke Shih 5320e3ec7017SPing-Ke Shih rtw89_for_each_rtwvif(rtwdev, rtwvif) 5321e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 5322e3ec7017SPing-Ke Shih } 5323e3ec7017SPing-Ke Shih 5324e3ec7017SPing-Ke Shih static int 5325e3ec7017SPing-Ke Shih __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5326e3ec7017SPing-Ke Shih u32 tx_time) 5327e3ec7017SPing-Ke Shih { 5328e3ec7017SPing-Ke Shih #define MAC_AX_DFLT_TX_TIME 5280 5329e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 5330e3ec7017SPing-Ke Shih u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 5331e3ec7017SPing-Ke Shih u32 reg; 5332e3ec7017SPing-Ke Shih int ret = 0; 5333e3ec7017SPing-Ke Shih 5334e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 5335e3ec7017SPing-Ke Shih rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 5336e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5337e3ec7017SPing-Ke Shih } else { 5338e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5339e3ec7017SPing-Ke Shih if (ret) { 5340e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 5341e3ec7017SPing-Ke Shih return ret; 5342e3ec7017SPing-Ke Shih } 5343e3ec7017SPing-Ke Shih 5344e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5345e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 5346e3ec7017SPing-Ke Shih max_tx_time >> 5); 5347e3ec7017SPing-Ke Shih } 5348e3ec7017SPing-Ke Shih 5349e3ec7017SPing-Ke Shih return ret; 5350e3ec7017SPing-Ke Shih } 5351e3ec7017SPing-Ke Shih 5352e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5353e3ec7017SPing-Ke Shih bool resume, u32 tx_time) 5354e3ec7017SPing-Ke Shih { 5355e3ec7017SPing-Ke Shih int ret = 0; 5356e3ec7017SPing-Ke Shih 5357e3ec7017SPing-Ke Shih if (!resume) { 5358e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = true; 5359e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5360e3ec7017SPing-Ke Shih } else { 5361e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5362e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = false; 5363e3ec7017SPing-Ke Shih } 5364e3ec7017SPing-Ke Shih 5365e3ec7017SPing-Ke Shih return ret; 5366e3ec7017SPing-Ke Shih } 5367e3ec7017SPing-Ke Shih 5368e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5369e3ec7017SPing-Ke Shih u32 *tx_time) 5370e3ec7017SPing-Ke Shih { 5371e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 5372e3ec7017SPing-Ke Shih u32 reg; 5373e3ec7017SPing-Ke Shih int ret = 0; 5374e3ec7017SPing-Ke Shih 5375e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 5376e3ec7017SPing-Ke Shih *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 5377e3ec7017SPing-Ke Shih } else { 5378e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5379e3ec7017SPing-Ke Shih if (ret) { 5380e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 5381e3ec7017SPing-Ke Shih return ret; 5382e3ec7017SPing-Ke Shih } 5383e3ec7017SPing-Ke Shih 5384e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5385e3ec7017SPing-Ke Shih *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 5386e3ec7017SPing-Ke Shih } 5387e3ec7017SPing-Ke Shih 5388e3ec7017SPing-Ke Shih return ret; 5389e3ec7017SPing-Ke Shih } 5390e3ec7017SPing-Ke Shih 5391e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 5392e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, 5393e3ec7017SPing-Ke Shih bool resume, u8 tx_retry) 5394e3ec7017SPing-Ke Shih { 5395e3ec7017SPing-Ke Shih int ret = 0; 5396e3ec7017SPing-Ke Shih 5397e3ec7017SPing-Ke Shih rtwsta->data_tx_cnt_lmt = tx_retry; 5398e3ec7017SPing-Ke Shih 5399e3ec7017SPing-Ke Shih if (!resume) { 5400e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = true; 5401e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5402e3ec7017SPing-Ke Shih } else { 5403e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5404e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = false; 5405e3ec7017SPing-Ke Shih } 5406e3ec7017SPing-Ke Shih 5407e3ec7017SPing-Ke Shih return ret; 5408e3ec7017SPing-Ke Shih } 5409e3ec7017SPing-Ke Shih 5410e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 5411e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, u8 *tx_retry) 5412e3ec7017SPing-Ke Shih { 5413e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 5414e3ec7017SPing-Ke Shih u32 reg; 5415e3ec7017SPing-Ke Shih int ret = 0; 5416e3ec7017SPing-Ke Shih 5417e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_retry_limit) { 5418e3ec7017SPing-Ke Shih *tx_retry = rtwsta->data_tx_cnt_lmt; 5419e3ec7017SPing-Ke Shih } else { 5420e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5421e3ec7017SPing-Ke Shih if (ret) { 5422e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 5423e3ec7017SPing-Ke Shih return ret; 5424e3ec7017SPing-Ke Shih } 5425e3ec7017SPing-Ke Shih 5426e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); 5427e3ec7017SPing-Ke Shih *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 5428e3ec7017SPing-Ke Shih } 5429e3ec7017SPing-Ke Shih 5430e3ec7017SPing-Ke Shih return ret; 5431e3ec7017SPing-Ke Shih } 5432e3ec7017SPing-Ke Shih 5433e3ec7017SPing-Ke Shih int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 5434e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 5435e3ec7017SPing-Ke Shih { 5436e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 5437e3ec7017SPing-Ke Shih u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; 5438e3ec7017SPing-Ke Shih u32 reg; 5439e3ec7017SPing-Ke Shih u32 ret; 5440e3ec7017SPing-Ke Shih 5441e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5442e3ec7017SPing-Ke Shih if (ret) 5443e3ec7017SPing-Ke Shih return ret; 5444e3ec7017SPing-Ke Shih 5445e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); 5446e3ec7017SPing-Ke Shih if (en) 5447e3ec7017SPing-Ke Shih rtw89_write16_set(rtwdev, reg, set); 5448e3ec7017SPing-Ke Shih else 5449e3ec7017SPing-Ke Shih rtw89_write16_clr(rtwdev, reg, set); 5450e3ec7017SPing-Ke Shih 5451e3ec7017SPing-Ke Shih return 0; 5452e3ec7017SPing-Ke Shih } 54532a7e54dbSPing-Ke Shih 54542a7e54dbSPing-Ke Shih int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 54552a7e54dbSPing-Ke Shih { 54562a7e54dbSPing-Ke Shih u32 val32; 54572a7e54dbSPing-Ke Shih int ret; 54582a7e54dbSPing-Ke Shih 54592a7e54dbSPing-Ke Shih val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 54602a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 54612a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 54622a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 54632a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 54642a7e54dbSPing-Ke Shih rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 54652a7e54dbSPing-Ke Shih 54662a7e54dbSPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 54672a7e54dbSPing-Ke Shih 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 54682a7e54dbSPing-Ke Shih if (ret) { 54692a7e54dbSPing-Ke Shih rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 54702a7e54dbSPing-Ke Shih offset, val, mask); 54712a7e54dbSPing-Ke Shih return ret; 54722a7e54dbSPing-Ke Shih } 54732a7e54dbSPing-Ke Shih 54742a7e54dbSPing-Ke Shih return 0; 54752a7e54dbSPing-Ke Shih } 54762a7e54dbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 5477bdfbf06cSPing-Ke Shih 5478bdfbf06cSPing-Ke Shih int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 5479bdfbf06cSPing-Ke Shih { 5480bdfbf06cSPing-Ke Shih u32 val32; 5481bdfbf06cSPing-Ke Shih int ret; 5482bdfbf06cSPing-Ke Shih 5483bdfbf06cSPing-Ke Shih val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5484bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 5485bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 5486bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 5487bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5488bdfbf06cSPing-Ke Shih rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5489bdfbf06cSPing-Ke Shih 5490bdfbf06cSPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5491bdfbf06cSPing-Ke Shih 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5492bdfbf06cSPing-Ke Shih if (ret) { 5493bdfbf06cSPing-Ke Shih rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 5494bdfbf06cSPing-Ke Shih return ret; 5495bdfbf06cSPing-Ke Shih } 5496bdfbf06cSPing-Ke Shih 5497bdfbf06cSPing-Ke Shih *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 5498bdfbf06cSPing-Ke Shih 5499bdfbf06cSPing-Ke Shih return 0; 5500bdfbf06cSPing-Ke Shih } 550108484e1fSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_read_xtal_si); 55029a785583SZong-Zhe Yang 55039a785583SZong-Zhe Yang static 55049a785583SZong-Zhe Yang void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 55059a785583SZong-Zhe Yang { 55069a785583SZong-Zhe Yang static const enum rtw89_pkt_drop_sel sels[] = { 55079a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 55089a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 55099a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 55109a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 55119a785583SZong-Zhe Yang }; 55129a785583SZong-Zhe Yang struct rtw89_vif *rtwvif = rtwsta->rtwvif; 55139a785583SZong-Zhe Yang struct rtw89_pkt_drop_params params = {0}; 55149a785583SZong-Zhe Yang int i; 55159a785583SZong-Zhe Yang 55169a785583SZong-Zhe Yang params.mac_band = RTW89_MAC_0; 55179a785583SZong-Zhe Yang params.macid = rtwsta->mac_id; 55189a785583SZong-Zhe Yang params.port = rtwvif->port; 55199a785583SZong-Zhe Yang params.mbssid = 0; 55209a785583SZong-Zhe Yang params.tf_trs = rtwvif->trigger; 55219a785583SZong-Zhe Yang 55229a785583SZong-Zhe Yang for (i = 0; i < ARRAY_SIZE(sels); i++) { 55239a785583SZong-Zhe Yang params.sel = sels[i]; 55249a785583SZong-Zhe Yang rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 55259a785583SZong-Zhe Yang } 55269a785583SZong-Zhe Yang } 55279a785583SZong-Zhe Yang 55289a785583SZong-Zhe Yang static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 55299a785583SZong-Zhe Yang { 55309a785583SZong-Zhe Yang struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 55319a785583SZong-Zhe Yang struct rtw89_vif *rtwvif = rtwsta->rtwvif; 55329a785583SZong-Zhe Yang struct rtw89_dev *rtwdev = rtwvif->rtwdev; 55339a785583SZong-Zhe Yang struct rtw89_vif *target = data; 55349a785583SZong-Zhe Yang 55359a785583SZong-Zhe Yang if (rtwvif != target) 55369a785583SZong-Zhe Yang return; 55379a785583SZong-Zhe Yang 55389a785583SZong-Zhe Yang rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 55399a785583SZong-Zhe Yang } 55409a785583SZong-Zhe Yang 55419a785583SZong-Zhe Yang void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 55429a785583SZong-Zhe Yang { 55439a785583SZong-Zhe Yang ieee80211_iterate_stations_atomic(rtwdev->hw, 55449a785583SZong-Zhe Yang rtw89_mac_pkt_drop_vif_iter, 55459a785583SZong-Zhe Yang rtwvif); 55469a785583SZong-Zhe Yang } 554741d56769SChih-Kang Chang 554841d56769SChih-Kang Chang int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 554941d56769SChih-Kang Chang enum rtw89_mac_idx band) 555041d56769SChih-Kang Chang { 555141d56769SChih-Kang Chang struct rtw89_pkt_drop_params params = {0}; 555241d56769SChih-Kang Chang bool empty; 555341d56769SChih-Kang Chang int i, ret = 0, try_cnt = 3; 555441d56769SChih-Kang Chang 555541d56769SChih-Kang Chang params.mac_band = band; 555641d56769SChih-Kang Chang params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 555741d56769SChih-Kang Chang 555841d56769SChih-Kang Chang for (i = 0; i < try_cnt; i++) { 555941d56769SChih-Kang Chang ret = read_poll_timeout(mac_is_txq_empty, empty, empty, 50, 556041d56769SChih-Kang Chang 50000, false, rtwdev); 55610d1f7ff1SZong-Zhe Yang if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 556241d56769SChih-Kang Chang rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 556341d56769SChih-Kang Chang else 556441d56769SChih-Kang Chang return 0; 556541d56769SChih-Kang Chang } 556641d56769SChih-Kang Chang return ret; 556741d56769SChih-Kang Chang } 5568