1e3ec7017SPing-Ke Shih // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2e3ec7017SPing-Ke Shih /* Copyright(c) 2019-2020 Realtek Corporation 3e3ec7017SPing-Ke Shih */ 4e3ec7017SPing-Ke Shih 5e3ec7017SPing-Ke Shih #include "cam.h" 6967439c7SZong-Zhe Yang #include "chan.h" 7e3ec7017SPing-Ke Shih #include "debug.h" 888e6a923SPing-Ke Shih #include "efuse.h" 9e3ec7017SPing-Ke Shih #include "fw.h" 10e3ec7017SPing-Ke Shih #include "mac.h" 11f7333fc2SChia-Yuan Li #include "pci.h" 12e3ec7017SPing-Ke Shih #include "ps.h" 13e3ec7017SPing-Ke Shih #include "reg.h" 14e3ec7017SPing-Ke Shih #include "util.h" 15e3ec7017SPing-Ke Shih 1660168f6cSPing-Ke Shih static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 17e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 18e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 19e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 20e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 21e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 22e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 23e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 24e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 25e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 26e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 27e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 28e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 29e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 30e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 31e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 32e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 33e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 34ec356ffbSChia-Yuan Li [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 35dadb2086SPing-Ke Shih [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 36732dd91dSPing-Ke Shih [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 37732dd91dSPing-Ke Shih [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 38e1400b11SZong-Zhe Yang }; 39e1400b11SZong-Zhe Yang 40ec356ffbSChia-Yuan Li static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 41ec356ffbSChia-Yuan Li u32 val, enum rtw89_mac_mem_sel sel) 42ec356ffbSChia-Yuan Li { 4360168f6cSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4460168f6cSPing-Ke Shih u32 addr = mac->mem_base_addrs[sel] + offset; 45ec356ffbSChia-Yuan Li 4660168f6cSPing-Ke Shih rtw89_write32(rtwdev, mac->filter_model_addr, addr); 4760168f6cSPing-Ke Shih rtw89_write32(rtwdev, mac->indir_access_addr, val); 48ec356ffbSChia-Yuan Li } 49ec356ffbSChia-Yuan Li 50ec356ffbSChia-Yuan Li static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 51ec356ffbSChia-Yuan Li enum rtw89_mac_mem_sel sel) 52ec356ffbSChia-Yuan Li { 5360168f6cSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5460168f6cSPing-Ke Shih u32 addr = mac->mem_base_addrs[sel] + offset; 55ec356ffbSChia-Yuan Li 5660168f6cSPing-Ke Shih rtw89_write32(rtwdev, mac->filter_model_addr, addr); 5760168f6cSPing-Ke Shih return rtw89_read32(rtwdev, mac->indir_access_addr); 58ec356ffbSChia-Yuan Li } 59ec356ffbSChia-Yuan Li 60cfb99433SPing-Ke Shih static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 61e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 62e3ec7017SPing-Ke Shih { 63e3ec7017SPing-Ke Shih u32 val, r_val; 64e3ec7017SPing-Ke Shih 65e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 66e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 67e3ec7017SPing-Ke Shih val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 68e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 69e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 70e3ec7017SPing-Ke Shih val = B_AX_CMAC_EN; 71e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 72e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 73e3ec7017SPing-Ke Shih val = B_AX_CMAC1_FEN; 74e3ec7017SPing-Ke Shih } else { 75e3ec7017SPing-Ke Shih return -EINVAL; 76e3ec7017SPing-Ke Shih } 77e3ec7017SPing-Ke Shih if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 78e3ec7017SPing-Ke Shih (val & r_val) != val) 79e3ec7017SPing-Ke Shih return -EFAULT; 80e3ec7017SPing-Ke Shih 81e3ec7017SPing-Ke Shih return 0; 82e3ec7017SPing-Ke Shih } 83e3ec7017SPing-Ke Shih 84e3ec7017SPing-Ke Shih int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 85e3ec7017SPing-Ke Shih { 86e3ec7017SPing-Ke Shih u8 lte_ctrl; 87e3ec7017SPing-Ke Shih int ret; 88e3ec7017SPing-Ke Shih 89e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 90e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 91e3ec7017SPing-Ke Shih if (ret) 92e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 93e3ec7017SPing-Ke Shih 94e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 95e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 96e3ec7017SPing-Ke Shih 97e3ec7017SPing-Ke Shih return ret; 98e3ec7017SPing-Ke Shih } 99e3ec7017SPing-Ke Shih 100e3ec7017SPing-Ke Shih int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 101e3ec7017SPing-Ke Shih { 102e3ec7017SPing-Ke Shih u8 lte_ctrl; 103e3ec7017SPing-Ke Shih int ret; 104e3ec7017SPing-Ke Shih 105e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 106e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 107e3ec7017SPing-Ke Shih if (ret) 108e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 109e3ec7017SPing-Ke Shih 110e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 111e3ec7017SPing-Ke Shih *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 112e3ec7017SPing-Ke Shih 113e3ec7017SPing-Ke Shih return ret; 114e3ec7017SPing-Ke Shih } 115e3ec7017SPing-Ke Shih 1166f8d3655SChia-Yuan Li int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 117e3ec7017SPing-Ke Shih { 118e3ec7017SPing-Ke Shih u32 ctrl_reg, data_reg, ctrl_data; 119e3ec7017SPing-Ke Shih u32 val; 120e3ec7017SPing-Ke Shih int ret; 121e3ec7017SPing-Ke Shih 122e3ec7017SPing-Ke Shih switch (ctrl->type) { 123e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_WDE: 124e3ec7017SPing-Ke Shih ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 125e3ec7017SPing-Ke Shih data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 126e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 127e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 128e3ec7017SPing-Ke Shih B_AX_WDE_DFI_ACTIVE; 129e3ec7017SPing-Ke Shih break; 130e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_PLE: 131e3ec7017SPing-Ke Shih ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 132e3ec7017SPing-Ke Shih data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 133e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 134e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 135e3ec7017SPing-Ke Shih B_AX_PLE_DFI_ACTIVE; 136e3ec7017SPing-Ke Shih break; 137e3ec7017SPing-Ke Shih default: 138e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 139e3ec7017SPing-Ke Shih return -EINVAL; 140e3ec7017SPing-Ke Shih } 141e3ec7017SPing-Ke Shih 142e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 143e3ec7017SPing-Ke Shih 144e3ec7017SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 145e3ec7017SPing-Ke Shih 1, 1000, false, rtwdev, ctrl_reg); 146e3ec7017SPing-Ke Shih if (ret) { 147e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 148e3ec7017SPing-Ke Shih ctrl_reg, ctrl_data); 149e3ec7017SPing-Ke Shih return ret; 150e3ec7017SPing-Ke Shih } 151e3ec7017SPing-Ke Shih 152e3ec7017SPing-Ke Shih ctrl->out_data = rtw89_read32(rtwdev, data_reg); 153e3ec7017SPing-Ke Shih return 0; 154e3ec7017SPing-Ke Shih } 155e3ec7017SPing-Ke Shih 1566f8d3655SChia-Yuan Li int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 157e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota *quota) 158e3ec7017SPing-Ke Shih { 159e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 160e3ec7017SPing-Ke Shih int ret; 161e3ec7017SPing-Ke Shih 162e3ec7017SPing-Ke Shih ctrl.type = quota->dle_type; 163e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QUOTA; 164e3ec7017SPing-Ke Shih ctrl.addr = quota->qtaid; 1656f8d3655SChia-Yuan Li ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 166e3ec7017SPing-Ke Shih if (ret) { 1676f8d3655SChia-Yuan Li rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 168e3ec7017SPing-Ke Shih return ret; 169e3ec7017SPing-Ke Shih } 170e3ec7017SPing-Ke Shih 171e3ec7017SPing-Ke Shih quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 172e3ec7017SPing-Ke Shih quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 173e3ec7017SPing-Ke Shih return 0; 174e3ec7017SPing-Ke Shih } 175e3ec7017SPing-Ke Shih 17627ea6be9SZong-Zhe Yang int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 177e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty *qempty) 178e3ec7017SPing-Ke Shih { 179e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 180e3ec7017SPing-Ke Shih u32 ret; 181e3ec7017SPing-Ke Shih 182e3ec7017SPing-Ke Shih ctrl.type = qempty->dle_type; 183e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QEMPTY; 184e3ec7017SPing-Ke Shih ctrl.addr = qempty->grpsel; 1856f8d3655SChia-Yuan Li ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 186e3ec7017SPing-Ke Shih if (ret) { 1876f8d3655SChia-Yuan Li rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 188e3ec7017SPing-Ke Shih return ret; 189e3ec7017SPing-Ke Shih } 190e3ec7017SPing-Ke Shih 191e3ec7017SPing-Ke Shih qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 192e3ec7017SPing-Ke Shih return 0; 193e3ec7017SPing-Ke Shih } 194e3ec7017SPing-Ke Shih 1956f8d3655SChia-Yuan Li static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 196e3ec7017SPing-Ke Shih { 197e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 198e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 199e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 200e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 201e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 202e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 203e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 204e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 205e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 206e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 207e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 208e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 209e3ec7017SPing-Ke Shih } 210e3ec7017SPing-Ke Shih 2116f8d3655SChia-Yuan Li static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 212e3ec7017SPing-Ke Shih { 213e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty qempty; 214e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota quota; 215e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 216e3ec7017SPing-Ke Shih u32 val, not_empty, i; 217e3ec7017SPing-Ke Shih int ret; 218e3ec7017SPing-Ke Shih 219e3ec7017SPing-Ke Shih qempty.dle_type = DLE_CTRL_TYPE_PLE; 220e3ec7017SPing-Ke Shih qempty.grpsel = 0; 22189e4a00fSÍñigo Huguet qempty.qempty = ~(u32)0; 22227ea6be9SZong-Zhe Yang ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 223e3ec7017SPing-Ke Shih if (ret) 224e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 225e3ec7017SPing-Ke Shih else 226e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 227e3ec7017SPing-Ke Shih 228e3ec7017SPing-Ke Shih for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 229e3ec7017SPing-Ke Shih if (!(not_empty & BIT(0))) 230e3ec7017SPing-Ke Shih continue; 231e3ec7017SPing-Ke Shih ctrl.type = DLE_CTRL_TYPE_PLE; 232e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QLNKTBL; 233e3ec7017SPing-Ke Shih ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 2346f8d3655SChia-Yuan Li u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 2356f8d3655SChia-Yuan Li ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 236e3ec7017SPing-Ke Shih if (ret) 237e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 238e3ec7017SPing-Ke Shih else 2396f8d3655SChia-Yuan Li rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 2406f8d3655SChia-Yuan Li u32_get_bits(ctrl.out_data, 2416f8d3655SChia-Yuan Li QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 242e3ec7017SPing-Ke Shih } 243e3ec7017SPing-Ke Shih 244e3ec7017SPing-Ke Shih quota.dle_type = DLE_CTRL_TYPE_PLE; 245e3ec7017SPing-Ke Shih quota.qtaid = 6; 2466f8d3655SChia-Yuan Li ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 247e3ec7017SPing-Ke Shih if (ret) 248e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 249e3ec7017SPing-Ke Shih else 250e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 251e3ec7017SPing-Ke Shih quota.rsv_pgnum, quota.use_pgnum); 252e3ec7017SPing-Ke Shih 253e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 2546f8d3655SChia-Yuan Li rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 2556f8d3655SChia-Yuan Li u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 2566f8d3655SChia-Yuan Li rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 2576f8d3655SChia-Yuan Li u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 2586f8d3655SChia-Yuan Li val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 2596f8d3655SChia-Yuan Li rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 2606f8d3655SChia-Yuan Li u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 2616f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 2626f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 2636f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 2646f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 2656f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 2666f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 267e3ec7017SPing-Ke Shih 2686f8d3655SChia-Yuan Li if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 2696f8d3655SChia-Yuan Li quota.dle_type = DLE_CTRL_TYPE_PLE; 2706f8d3655SChia-Yuan Li quota.qtaid = 7; 2716f8d3655SChia-Yuan Li ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 2726f8d3655SChia-Yuan Li if (ret) 2736f8d3655SChia-Yuan Li rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 2746f8d3655SChia-Yuan Li else 2756f8d3655SChia-Yuan Li rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 2766f8d3655SChia-Yuan Li quota.rsv_pgnum, quota.use_pgnum); 2776f8d3655SChia-Yuan Li 2786f8d3655SChia-Yuan Li val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 2796f8d3655SChia-Yuan Li rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 2806f8d3655SChia-Yuan Li u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 2816f8d3655SChia-Yuan Li rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 2826f8d3655SChia-Yuan Li u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 2836f8d3655SChia-Yuan Li val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 2846f8d3655SChia-Yuan Li rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 2856f8d3655SChia-Yuan Li u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 2866f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 2876f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 2886f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 2896f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 2906f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 2916f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 292e3ec7017SPing-Ke Shih } 293e3ec7017SPing-Ke Shih 2946f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 2956f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 2966f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 2976f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 2986f8d3655SChia-Yuan Li 2996f8d3655SChia-Yuan Li dump_err_status_dispatcher_ax(rtwdev); 3006f8d3655SChia-Yuan Li } 3016f8d3655SChia-Yuan Li 3026f8d3655SChia-Yuan Li void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 303e3ec7017SPing-Ke Shih enum mac_ax_err_info err) 304e3ec7017SPing-Ke Shih { 3056f8d3655SChia-Yuan Li const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 306e3ec7017SPing-Ke Shih u32 dbg, event; 307e3ec7017SPing-Ke Shih 308e3ec7017SPing-Ke Shih dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 3096f8d3655SChia-Yuan Li event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 310e3ec7017SPing-Ke Shih 311e3ec7017SPing-Ke Shih switch (event) { 312e3ec7017SPing-Ke Shih case MAC_AX_L0_TO_L1_RX_QTA_LOST: 313e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota lost!\n"); 3146f8d3655SChia-Yuan Li mac->dump_qta_lost(rtwdev); 315e3ec7017SPing-Ke Shih break; 316e3ec7017SPing-Ke Shih default: 317e3ec7017SPing-Ke Shih break; 318e3ec7017SPing-Ke Shih } 319e3ec7017SPing-Ke Shih } 320e3ec7017SPing-Ke Shih 3216f8d3655SChia-Yuan Li void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 322e3ec7017SPing-Ke Shih { 323f7333fc2SChia-Yuan Li const struct rtw89_chip_info *chip = rtwdev->chip; 324f7333fc2SChia-Yuan Li u32 dmac_err; 325f7333fc2SChia-Yuan Li int i, ret; 326e3ec7017SPing-Ke Shih 327f7333fc2SChia-Yuan Li ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 328f7333fc2SChia-Yuan Li if (ret) { 329f7333fc2SChia-Yuan Li rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 330e3ec7017SPing-Ke Shih return; 331f7333fc2SChia-Yuan Li } 332e3ec7017SPing-Ke Shih 333e3ec7017SPing-Ke Shih dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 334e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 335f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 336f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 337e3ec7017SPing-Ke Shih 338e3ec7017SPing-Ke Shih if (dmac_err) { 339f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 340f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 341e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 342f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 343f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 344f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 345f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 346f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 347f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 348f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 349f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 350f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 351f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 352f7333fc2SChia-Yuan Li } 353e3ec7017SPing-Ke Shih } 354e3ec7017SPing-Ke Shih 355e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 356f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 357e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 358e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 359e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 360f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) 361f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 362f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 363f7333fc2SChia-Yuan Li else 364f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 365f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 366e3ec7017SPing-Ke Shih } 367e3ec7017SPing-Ke Shih 368e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WSEC_ERR_FLAG) { 369f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 370f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 371f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 372f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 373f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 374f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 375f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 376f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 377f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 378f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 379f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 380f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 381f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 382f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 383f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 384f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 385f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 386f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 387f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 388f7333fc2SChia-Yuan Li 389f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 390f7333fc2SChia-Yuan Li B_AX_DBG_SEL0, 0x8B); 391f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392f7333fc2SChia-Yuan Li B_AX_DBG_SEL1, 0x8B); 393f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 394f7333fc2SChia-Yuan Li B_AX_SEL_0XC0_MASK, 1); 395f7333fc2SChia-Yuan Li for (i = 0; i < 0x10; i++) { 396f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 397f7333fc2SChia-Yuan Li B_AX_SEC_DBG_PORT_FIELD_MASK, i); 398f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 399f7333fc2SChia-Yuan Li i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 400f7333fc2SChia-Yuan Li } 4016f8d3655SChia-Yuan Li } else if (chip->chip_id == RTL8922A) { 4026f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 4036f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 4046f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 4056f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 4066f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 4076f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 4086f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 4096f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 4106f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 4116f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 4126f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 4136f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 4146f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 4156f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 416f7333fc2SChia-Yuan Li } else { 417e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 418e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 419f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 420e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 421f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 422e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 423f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 424e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 425f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 426e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 427f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 428e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 429f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 430e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 431f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 432e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 433f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 434e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 435f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 436e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 437e3ec7017SPing-Ke Shih } 438f7333fc2SChia-Yuan Li } 439e3ec7017SPing-Ke Shih 440e3ec7017SPing-Ke Shih if (dmac_err & B_AX_MPDU_ERR_FLAG) { 441f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 442e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 443e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 444e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 445f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 446e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 447e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 448e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 449e3ec7017SPing-Ke Shih } 450e3ec7017SPing-Ke Shih 451e3ec7017SPing-Ke Shih if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 4526f8d3655SChia-Yuan Li if (chip->chip_id == RTL8922A) { 4536f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 4546f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 4556f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 4566f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 4576f8d3655SChia-Yuan Li } else { 458f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 459e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 460e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 461e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 462e3ec7017SPing-Ke Shih } 4636f8d3655SChia-Yuan Li } 464e3ec7017SPing-Ke Shih 465e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 466f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 467e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 468e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 469e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 470f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 471e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 472e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 473e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 474e3ec7017SPing-Ke Shih } 475e3ec7017SPing-Ke Shih 476e3ec7017SPing-Ke Shih if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 4776f8d3655SChia-Yuan Li if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 478f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 479f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 480f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 481f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 482f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 483f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 484f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 485f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 486f7333fc2SChia-Yuan Li } else { 487e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 488e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 489e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 490e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 491e3ec7017SPing-Ke Shih } 492f7333fc2SChia-Yuan Li } 493e3ec7017SPing-Ke Shih 494e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 495f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 496e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 497e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 498e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 499f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 500e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 501e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 502e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 503e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 504e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 505e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 506e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 507e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 508e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 509e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 510e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 511e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 512e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 513e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 514e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 5156f8d3655SChia-Yuan Li if (chip->chip_id == RTL8922A) { 5166f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 5176f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 5186f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 5196f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 5206f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 5216f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 5226f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 5236f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 5246f8d3655SChia-Yuan Li } else { 5256f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 5266f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 527e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 528e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 529f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 530f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 531f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 532f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 533f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 534f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 535f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 536f7333fc2SChia-Yuan Li } else { 537e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 538e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 539e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 540e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 541e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 542e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 543f7333fc2SChia-Yuan Li } 544e3ec7017SPing-Ke Shih } 5456f8d3655SChia-Yuan Li } 546e3ec7017SPing-Ke Shih 547e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 548f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 549e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 550e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 551e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 552e3ec7017SPing-Ke Shih } 553e3ec7017SPing-Ke Shih 554f7333fc2SChia-Yuan Li if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 5556f8d3655SChia-Yuan Li if (chip->chip_id == RTL8922A) { 5566f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 5576f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 5586f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 5596f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 5606f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 5616f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 5626f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 5636f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 5646f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 5656f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 5666f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 5676f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 5686f8d3655SChia-Yuan Li } else { 569f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 570f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 571f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 572f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 573f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 574f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 575f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 576f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 577f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 578f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 579f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 580f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 581e3ec7017SPing-Ke Shih } 5826f8d3655SChia-Yuan Li } 583e3ec7017SPing-Ke Shih 584f7333fc2SChia-Yuan Li if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 5856f8d3655SChia-Yuan Li if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 586f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 587f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 588f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 589f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 590f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 591f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 592f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 593f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 594f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 595f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 596f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 597f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 598f7333fc2SChia-Yuan Li } else { 599e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 600e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 601f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 602f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 603f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 604f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 605f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 606f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 607f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 608f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 609f7333fc2SChia-Yuan Li } 6106f8d3655SChia-Yuan Li if (chip->chip_id == RTL8922A) { 6116f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 6126f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 6136f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 6146f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 6156f8d3655SChia-Yuan Li } 616e3ec7017SPing-Ke Shih } 617e3ec7017SPing-Ke Shih 6186f8d3655SChia-Yuan Li if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 6196f8d3655SChia-Yuan Li if (chip->chip_id == RTL8922A) { 6206f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 6216f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 6226f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 6236f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 6246f8d3655SChia-Yuan Li } else if (chip->chip_id == RTL8852C) { 625f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 626f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 627f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 628f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 629f7333fc2SChia-Yuan Li } 630f7333fc2SChia-Yuan Li } 631f7333fc2SChia-Yuan Li 6326f8d3655SChia-Yuan Li if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 6336f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 6346f8d3655SChia-Yuan Li rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 6356f8d3655SChia-Yuan Li RTW89_MAC_MEM_AXIDMA)); 6366f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 6376f8d3655SChia-Yuan Li rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 6386f8d3655SChia-Yuan Li RTW89_MAC_MEM_AXIDMA)); 6396f8d3655SChia-Yuan Li } 6406f8d3655SChia-Yuan Li 6416f8d3655SChia-Yuan Li if (dmac_err & B_BE_MLO_ERR_INT) { 6426f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 6436f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 6446f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 6456f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 6466f8d3655SChia-Yuan Li } 6476f8d3655SChia-Yuan Li 6486f8d3655SChia-Yuan Li if (dmac_err & B_BE_PLRLS_ERR_INT) { 6496f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 6506f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 6516f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 6526f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 6536f8d3655SChia-Yuan Li } 6546f8d3655SChia-Yuan Li } 6556f8d3655SChia-Yuan Li 6566f8d3655SChia-Yuan Li static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 657f7333fc2SChia-Yuan Li u8 band) 658f7333fc2SChia-Yuan Li { 659f7333fc2SChia-Yuan Li const struct rtw89_chip_info *chip = rtwdev->chip; 660f7333fc2SChia-Yuan Li u32 offset = 0; 661f7333fc2SChia-Yuan Li u32 cmac_err; 662f7333fc2SChia-Yuan Li int ret; 663f7333fc2SChia-Yuan Li 664f7333fc2SChia-Yuan Li ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 665f7333fc2SChia-Yuan Li if (ret) { 666f7333fc2SChia-Yuan Li if (band) 667f7333fc2SChia-Yuan Li rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 668f7333fc2SChia-Yuan Li else 669f7333fc2SChia-Yuan Li rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 670f7333fc2SChia-Yuan Li return; 671f7333fc2SChia-Yuan Li } 672f7333fc2SChia-Yuan Li 673f7333fc2SChia-Yuan Li if (band) 674f7333fc2SChia-Yuan Li offset = RTW89_MAC_AX_BAND_REG_OFFSET; 675f7333fc2SChia-Yuan Li 676f7333fc2SChia-Yuan Li cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 677f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 678f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 679f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 680f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 681f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 682f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 683f7333fc2SChia-Yuan Li 684e3ec7017SPing-Ke Shih if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 685f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 686f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 687f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 688f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 689e3ec7017SPing-Ke Shih } 690e3ec7017SPing-Ke Shih 691e3ec7017SPing-Ke Shih if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 692f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 693f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 694f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 695f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 696e3ec7017SPing-Ke Shih } 697e3ec7017SPing-Ke Shih 698e3ec7017SPing-Ke Shih if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 699f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 700f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 701f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 702f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 703f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 704f7333fc2SChia-Yuan Li } else { 705f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 706f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 707f7333fc2SChia-Yuan Li } 708e3ec7017SPing-Ke Shih } 709e3ec7017SPing-Ke Shih 710f7333fc2SChia-Yuan Li if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 711f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 712f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 713f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 714f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 715f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 716f7333fc2SChia-Yuan Li } else { 717f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 718f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 719f7333fc2SChia-Yuan Li } 720e3ec7017SPing-Ke Shih } 721e3ec7017SPing-Ke Shih 722e3ec7017SPing-Ke Shih if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 723f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 724f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 725f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 726f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 727e3ec7017SPing-Ke Shih } 728e3ec7017SPing-Ke Shih 729e3ec7017SPing-Ke Shih if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 730f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 731f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 732f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 733f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 734f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 735f7333fc2SChia-Yuan Li } else { 736f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 737f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 738e3ec7017SPing-Ke Shih } 739f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 740f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 741f7333fc2SChia-Yuan Li } 742f7333fc2SChia-Yuan Li 743f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 744f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 745f7333fc2SChia-Yuan Li } 746f7333fc2SChia-Yuan Li 7476f8d3655SChia-Yuan Li static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 748f7333fc2SChia-Yuan Li enum mac_ax_err_info err) 749f7333fc2SChia-Yuan Li { 750f7333fc2SChia-Yuan Li if (err != MAC_AX_ERR_L1_ERR_DMAC && 751f7333fc2SChia-Yuan Li err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 752f7333fc2SChia-Yuan Li err != MAC_AX_ERR_L0_ERR_CMAC0 && 753f5d98831SZong-Zhe Yang err != MAC_AX_ERR_L0_ERR_CMAC1 && 754f5d98831SZong-Zhe Yang err != MAC_AX_ERR_RXI300) 755f7333fc2SChia-Yuan Li return; 756f7333fc2SChia-Yuan Li 757f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 758f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 759f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 7606f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 7616f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 7626f8d3655SChia-Yuan Li rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 7636f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 7646f8d3655SChia-Yuan Li rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 7656f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 766f7333fc2SChia-Yuan Li 767f7333fc2SChia-Yuan Li rtw89_mac_dump_dmac_err_status(rtwdev); 7686f8d3655SChia-Yuan Li rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 7696f8d3655SChia-Yuan Li rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 770e3ec7017SPing-Ke Shih 771e3ec7017SPing-Ke Shih rtwdev->hci.ops->dump_err_status(rtwdev); 772e3ec7017SPing-Ke Shih 773e3ec7017SPing-Ke Shih if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 774e3ec7017SPing-Ke Shih rtw89_mac_dump_l0_to_l1(rtwdev, err); 775e3ec7017SPing-Ke Shih 776e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "<---\n"); 777e3ec7017SPing-Ke Shih } 778e3ec7017SPing-Ke Shih 7798130e94eSChin-Yen Lee static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 7808130e94eSChin-Yen Lee { 7818130e94eSChin-Yen Lee struct rtw89_ser *ser = &rtwdev->ser; 7828130e94eSChin-Yen Lee u32 dmac_err, imr, isr; 7838130e94eSChin-Yen Lee int ret; 7848130e94eSChin-Yen Lee 7858130e94eSChin-Yen Lee if (rtwdev->chip->chip_id == RTL8852C) { 7868130e94eSChin-Yen Lee ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 7878130e94eSChin-Yen Lee if (ret) 7888130e94eSChin-Yen Lee return true; 7898130e94eSChin-Yen Lee 7908130e94eSChin-Yen Lee if (err == MAC_AX_ERR_L1_ERR_DMAC) { 7918130e94eSChin-Yen Lee dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 7928130e94eSChin-Yen Lee imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 7938130e94eSChin-Yen Lee isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 7948130e94eSChin-Yen Lee 7958130e94eSChin-Yen Lee if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 7968130e94eSChin-Yen Lee ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 7978130e94eSChin-Yen Lee set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 7988130e94eSChin-Yen Lee return true; 7998130e94eSChin-Yen Lee } 8008130e94eSChin-Yen Lee } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 8018130e94eSChin-Yen Lee if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 8028130e94eSChin-Yen Lee return true; 8038130e94eSChin-Yen Lee } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 8048130e94eSChin-Yen Lee if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 8058130e94eSChin-Yen Lee return true; 8068130e94eSChin-Yen Lee } 8078130e94eSChin-Yen Lee } 8088130e94eSChin-Yen Lee 8098130e94eSChin-Yen Lee return false; 8108130e94eSChin-Yen Lee } 8118130e94eSChin-Yen Lee 812e3ec7017SPing-Ke Shih u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 813e3ec7017SPing-Ke Shih { 8146f8d3655SChia-Yuan Li const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 815198b6cf7SZong-Zhe Yang u32 err, err_scnr; 816e3ec7017SPing-Ke Shih int ret; 817e3ec7017SPing-Ke Shih 818e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 819e3ec7017SPing-Ke Shih false, rtwdev, R_AX_HALT_C2H_CTRL); 820e3ec7017SPing-Ke Shih if (ret) { 821e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "Polling FW err status fail\n"); 822e3ec7017SPing-Ke Shih return ret; 823e3ec7017SPing-Ke Shih } 824e3ec7017SPing-Ke Shih 825e3ec7017SPing-Ke Shih err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 826e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 827e3ec7017SPing-Ke Shih 828198b6cf7SZong-Zhe Yang err_scnr = RTW89_ERROR_SCENARIO(err); 829198b6cf7SZong-Zhe Yang if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 830198b6cf7SZong-Zhe Yang err = MAC_AX_ERR_CPU_EXCEPTION; 831198b6cf7SZong-Zhe Yang else if (err_scnr == RTW89_WCPU_ASSERTION) 832198b6cf7SZong-Zhe Yang err = MAC_AX_ERR_ASSERTION; 833f5d98831SZong-Zhe Yang else if (err_scnr == RTW89_RXI300_ERROR) 834f5d98831SZong-Zhe Yang err = MAC_AX_ERR_RXI300; 835198b6cf7SZong-Zhe Yang 8368130e94eSChin-Yen Lee if (rtw89_mac_suppress_log(rtwdev, err)) 8378130e94eSChin-Yen Lee return err; 8388130e94eSChin-Yen Lee 839e3ec7017SPing-Ke Shih rtw89_fw_st_dbg_dump(rtwdev); 8406f8d3655SChia-Yuan Li mac->dump_err_status(rtwdev, err); 841e3ec7017SPing-Ke Shih 842e3ec7017SPing-Ke Shih return err; 843e3ec7017SPing-Ke Shih } 844e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_get_err_status); 845e3ec7017SPing-Ke Shih 846e3ec7017SPing-Ke Shih int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 847e3ec7017SPing-Ke Shih { 84856617fd0SZong-Zhe Yang struct rtw89_ser *ser = &rtwdev->ser; 849e3ec7017SPing-Ke Shih u32 halt; 850e3ec7017SPing-Ke Shih int ret = 0; 851e3ec7017SPing-Ke Shih 852e3ec7017SPing-Ke Shih if (err > MAC_AX_SET_ERR_MAX) { 853e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 854e3ec7017SPing-Ke Shih return -EINVAL; 855e3ec7017SPing-Ke Shih } 856e3ec7017SPing-Ke Shih 857e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 858e3ec7017SPing-Ke Shih 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 859e3ec7017SPing-Ke Shih if (ret) { 860e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 861e3ec7017SPing-Ke Shih return -EFAULT; 862e3ec7017SPing-Ke Shih } 863e3ec7017SPing-Ke Shih 864e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 86556617fd0SZong-Zhe Yang 86656617fd0SZong-Zhe Yang if (ser->prehandle_l1 && 86756617fd0SZong-Zhe Yang (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 86856617fd0SZong-Zhe Yang return 0; 86956617fd0SZong-Zhe Yang 870e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 871e3ec7017SPing-Ke Shih 872e3ec7017SPing-Ke Shih return 0; 873e3ec7017SPing-Ke Shih } 874e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_set_err_status); 875e3ec7017SPing-Ke Shih 876e3ec7017SPing-Ke Shih static int hfc_reset_param(struct rtw89_dev *rtwdev) 877e3ec7017SPing-Ke Shih { 878e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 879e3ec7017SPing-Ke Shih struct rtw89_hfc_param_ini param_ini = {NULL}; 880e3ec7017SPing-Ke Shih u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 881e3ec7017SPing-Ke Shih 882e3ec7017SPing-Ke Shih switch (rtwdev->hci.type) { 883e3ec7017SPing-Ke Shih case RTW89_HCI_TYPE_PCIE: 884e3ec7017SPing-Ke Shih param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 885e3ec7017SPing-Ke Shih param->en = 0; 886e3ec7017SPing-Ke Shih break; 887e3ec7017SPing-Ke Shih default: 888e3ec7017SPing-Ke Shih return -EINVAL; 889e3ec7017SPing-Ke Shih } 890e3ec7017SPing-Ke Shih 891e3ec7017SPing-Ke Shih if (param_ini.pub_cfg) 892e3ec7017SPing-Ke Shih param->pub_cfg = *param_ini.pub_cfg; 893e3ec7017SPing-Ke Shih 89465a9140eSDmitry Antipov if (param_ini.prec_cfg) 895e3ec7017SPing-Ke Shih param->prec_cfg = *param_ini.prec_cfg; 896e3ec7017SPing-Ke Shih 897e3ec7017SPing-Ke Shih if (param_ini.ch_cfg) 898e3ec7017SPing-Ke Shih param->ch_cfg = param_ini.ch_cfg; 899e3ec7017SPing-Ke Shih 900e3ec7017SPing-Ke Shih memset(¶m->ch_info, 0, sizeof(param->ch_info)); 901e3ec7017SPing-Ke Shih memset(¶m->pub_info, 0, sizeof(param->pub_info)); 902e3ec7017SPing-Ke Shih param->mode = param_ini.mode; 903e3ec7017SPing-Ke Shih 904e3ec7017SPing-Ke Shih return 0; 905e3ec7017SPing-Ke Shih } 906e3ec7017SPing-Ke Shih 907e3ec7017SPing-Ke Shih static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 908e3ec7017SPing-Ke Shih { 909e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 910e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 911e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 912e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 913e3ec7017SPing-Ke Shih 914e3ec7017SPing-Ke Shih if (ch >= RTW89_DMA_CH_NUM) 915e3ec7017SPing-Ke Shih return -EINVAL; 916e3ec7017SPing-Ke Shih 917e3ec7017SPing-Ke Shih if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 918e3ec7017SPing-Ke Shih ch_cfg[ch].max > pub_cfg->pub_max) 919e3ec7017SPing-Ke Shih return -EINVAL; 920e3ec7017SPing-Ke Shih if (ch_cfg[ch].grp >= grp_num) 921e3ec7017SPing-Ke Shih return -EINVAL; 922e3ec7017SPing-Ke Shih 923e3ec7017SPing-Ke Shih return 0; 924e3ec7017SPing-Ke Shih } 925e3ec7017SPing-Ke Shih 926e3ec7017SPing-Ke Shih static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 927e3ec7017SPing-Ke Shih { 928e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 929e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 930e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 931e3ec7017SPing-Ke Shih 932e3ec7017SPing-Ke Shih if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 933e3ec7017SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852A) 934e3ec7017SPing-Ke Shih return 0; 935e3ec7017SPing-Ke Shih else 936e3ec7017SPing-Ke Shih return -EFAULT; 937e3ec7017SPing-Ke Shih } 938e3ec7017SPing-Ke Shih 939e3ec7017SPing-Ke Shih return 0; 940e3ec7017SPing-Ke Shih } 941e3ec7017SPing-Ke Shih 942e3ec7017SPing-Ke Shih static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 943e3ec7017SPing-Ke Shih { 944e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 945e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 946e3ec7017SPing-Ke Shih 947e3ec7017SPing-Ke Shih if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 948c6477cb2SKevin Lo return -EFAULT; 949e3ec7017SPing-Ke Shih 950e3ec7017SPing-Ke Shih return 0; 951e3ec7017SPing-Ke Shih } 952e3ec7017SPing-Ke Shih 953e3ec7017SPing-Ke Shih static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 954e3ec7017SPing-Ke Shih { 955ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 956ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 957e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 958e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 959e3ec7017SPing-Ke Shih int ret = 0; 960e3ec7017SPing-Ke Shih u32 val = 0; 961e3ec7017SPing-Ke Shih 962e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 963e3ec7017SPing-Ke Shih if (ret) 964e3ec7017SPing-Ke Shih return ret; 965e3ec7017SPing-Ke Shih 966e3ec7017SPing-Ke Shih ret = hfc_ch_cfg_chk(rtwdev, ch); 967e3ec7017SPing-Ke Shih if (ret) 968e3ec7017SPing-Ke Shih return ret; 969e3ec7017SPing-Ke Shih 970e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_B1HI) 971e3ec7017SPing-Ke Shih return -EINVAL; 972e3ec7017SPing-Ke Shih 973e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 974e3ec7017SPing-Ke Shih u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 975e3ec7017SPing-Ke Shih (cfg[ch].grp ? B_AX_GRP : 0); 976ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 977e3ec7017SPing-Ke Shih 978e3ec7017SPing-Ke Shih return 0; 979e3ec7017SPing-Ke Shih } 980e3ec7017SPing-Ke Shih 981e3ec7017SPing-Ke Shih static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 982e3ec7017SPing-Ke Shih { 983ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 984ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 985e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 986e3ec7017SPing-Ke Shih struct rtw89_hfc_ch_info *info = param->ch_info; 987e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 988e3ec7017SPing-Ke Shih u32 val; 989e3ec7017SPing-Ke Shih u32 ret; 990e3ec7017SPing-Ke Shih 991e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 992e3ec7017SPing-Ke Shih if (ret) 993e3ec7017SPing-Ke Shih return ret; 994e3ec7017SPing-Ke Shih 995e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_H2C) 996e3ec7017SPing-Ke Shih return -EINVAL; 997e3ec7017SPing-Ke Shih 998ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 999e3ec7017SPing-Ke Shih info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1000e3ec7017SPing-Ke Shih if (ch < RTW89_DMA_H2C) 1001e3ec7017SPing-Ke Shih info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1002e3ec7017SPing-Ke Shih else 1003e3ec7017SPing-Ke Shih info[ch].used = cfg[ch].min - info[ch].aval; 1004e3ec7017SPing-Ke Shih 1005e3ec7017SPing-Ke Shih return 0; 1006e3ec7017SPing-Ke Shih } 1007e3ec7017SPing-Ke Shih 1008e3ec7017SPing-Ke Shih static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1009e3ec7017SPing-Ke Shih { 1010ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1011ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 1012e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1013e3ec7017SPing-Ke Shih u32 val; 1014e3ec7017SPing-Ke Shih int ret; 1015e3ec7017SPing-Ke Shih 1016e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1017e3ec7017SPing-Ke Shih if (ret) 1018e3ec7017SPing-Ke Shih return ret; 1019e3ec7017SPing-Ke Shih 1020e3ec7017SPing-Ke Shih ret = hfc_pub_cfg_chk(rtwdev); 1021e3ec7017SPing-Ke Shih if (ret) 1022e3ec7017SPing-Ke Shih return ret; 1023e3ec7017SPing-Ke Shih 1024e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1025e3ec7017SPing-Ke Shih u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1026ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1027e3ec7017SPing-Ke Shih 1028e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1029ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1030e3ec7017SPing-Ke Shih 1031e3ec7017SPing-Ke Shih return 0; 1032e3ec7017SPing-Ke Shih } 1033e3ec7017SPing-Ke Shih 103439e9b569SPing-Ke Shih static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1035e3ec7017SPing-Ke Shih { 1036ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1037ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 1038e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1039e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1040e3ec7017SPing-Ke Shih struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1041e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1042e3ec7017SPing-Ke Shih u32 val; 1043e3ec7017SPing-Ke Shih 1044ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_info1); 1045e3ec7017SPing-Ke Shih info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1046e3ec7017SPing-Ke Shih info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1047ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_info3); 1048e3ec7017SPing-Ke Shih info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1049e3ec7017SPing-Ke Shih info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1050e3ec7017SPing-Ke Shih info->pub_aval = 1051ab8a5671SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1052e3ec7017SPing-Ke Shih B_AX_PUB_AVAL_PG_MASK); 1053e3ec7017SPing-Ke Shih info->wp_aval = 1054ab8a5671SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1055e3ec7017SPing-Ke Shih B_AX_WP_AVAL_PG_MASK); 1056e3ec7017SPing-Ke Shih 1057ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1058e3ec7017SPing-Ke Shih param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1059e3ec7017SPing-Ke Shih param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1060e3ec7017SPing-Ke Shih param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1061e3ec7017SPing-Ke Shih prec_cfg->ch011_full_cond = 1062e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1063e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond = 1064e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1065e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_full_cond = 1066e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1067e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_full_cond = 1068e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1069e3ec7017SPing-Ke Shih 1070ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1071e3ec7017SPing-Ke Shih prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1072e3ec7017SPing-Ke Shih prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1073e3ec7017SPing-Ke Shih 1074ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1075e3ec7017SPing-Ke Shih pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1076e3ec7017SPing-Ke Shih 1077ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1078e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1079e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1080e3ec7017SPing-Ke Shih 1081ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1082e3ec7017SPing-Ke Shih pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1083e3ec7017SPing-Ke Shih 1084ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1085e3ec7017SPing-Ke Shih pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1086e3ec7017SPing-Ke Shih pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 10870d16d8fbSPing-Ke Shih } 10880d16d8fbSPing-Ke Shih 10890d16d8fbSPing-Ke Shih static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 10900d16d8fbSPing-Ke Shih { 109139e9b569SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 10920d16d8fbSPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 10930d16d8fbSPing-Ke Shih int ret; 10940d16d8fbSPing-Ke Shih 10950d16d8fbSPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 10960d16d8fbSPing-Ke Shih if (ret) 10970d16d8fbSPing-Ke Shih return ret; 10980d16d8fbSPing-Ke Shih 109939e9b569SPing-Ke Shih mac->hfc_get_mix_info(rtwdev); 1100e3ec7017SPing-Ke Shih 1101e3ec7017SPing-Ke Shih ret = hfc_pub_info_chk(rtwdev); 1102e3ec7017SPing-Ke Shih if (param->en && ret) 1103e3ec7017SPing-Ke Shih return ret; 1104e3ec7017SPing-Ke Shih 1105e3ec7017SPing-Ke Shih return 0; 1106e3ec7017SPing-Ke Shih } 1107e3ec7017SPing-Ke Shih 110839e9b569SPing-Ke Shih static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1109e3ec7017SPing-Ke Shih { 1110ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1111ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 1112e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1113e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1114e3ec7017SPing-Ke Shih u32 val; 1115e3ec7017SPing-Ke Shih 1116e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1117ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1118e3ec7017SPing-Ke Shih 1119ab8a5671SPing-Ke Shih rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1120e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK, 1121e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond); 1122e3ec7017SPing-Ke Shih } 1123e3ec7017SPing-Ke Shih 112439e9b569SPing-Ke Shih static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1125e3ec7017SPing-Ke Shih { 1126ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1127ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 1128e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1129e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1130e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1131e3ec7017SPing-Ke Shih u32 val; 1132e3ec7017SPing-Ke Shih 1133e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1134e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1135ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1136e3ec7017SPing-Ke Shih 1137e3ec7017SPing-Ke Shih val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1138ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1139e3ec7017SPing-Ke Shih 1140e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1141e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH07_MASK) | 1142e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->wp_ch811_prec, 1143e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH811_MASK); 1144ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1145e3ec7017SPing-Ke Shih 1146ab8a5671SPing-Ke Shih val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1147e3ec7017SPing-Ke Shih param->mode, B_AX_HCI_FC_MODE_MASK); 1148e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1149e3ec7017SPing-Ke Shih B_AX_HCI_FC_WD_FULL_COND_MASK); 1150e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1151e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK); 1152e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1153e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1154e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1155e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1156ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1157e3ec7017SPing-Ke Shih } 1158e3ec7017SPing-Ke Shih 115939e9b569SPing-Ke Shih static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1160e3ec7017SPing-Ke Shih { 1161ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1162ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 1163e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1164e3ec7017SPing-Ke Shih u32 val; 1165e3ec7017SPing-Ke Shih 1166ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1167e3ec7017SPing-Ke Shih param->en = en; 1168e3ec7017SPing-Ke Shih param->h2c_en = h2c_en; 1169e3ec7017SPing-Ke Shih val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1170e3ec7017SPing-Ke Shih val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1171e3ec7017SPing-Ke Shih (val & ~B_AX_HCI_FC_CH12_EN); 1172ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1173e3ec7017SPing-Ke Shih } 1174e3ec7017SPing-Ke Shih 1175fc663fa0SPing-Ke Shih int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1176e3ec7017SPing-Ke Shih { 117739e9b569SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1178a1b7163aSPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1179a1b7163aSPing-Ke Shih u32 dma_ch_mask = chip->dma_ch_mask; 1180e3ec7017SPing-Ke Shih u8 ch; 1181e3ec7017SPing-Ke Shih u32 ret = 0; 1182e3ec7017SPing-Ke Shih 1183e3ec7017SPing-Ke Shih if (reset) 1184e3ec7017SPing-Ke Shih ret = hfc_reset_param(rtwdev); 1185e3ec7017SPing-Ke Shih if (ret) 1186e3ec7017SPing-Ke Shih return ret; 1187e3ec7017SPing-Ke Shih 1188e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1189e3ec7017SPing-Ke Shih if (ret) 1190e3ec7017SPing-Ke Shih return ret; 1191e3ec7017SPing-Ke Shih 119239e9b569SPing-Ke Shih mac->hfc_func_en(rtwdev, false, false); 1193e3ec7017SPing-Ke Shih 1194e3ec7017SPing-Ke Shih if (!en && h2c_en) { 119539e9b569SPing-Ke Shih mac->hfc_h2c_cfg(rtwdev); 119639e9b569SPing-Ke Shih mac->hfc_func_en(rtwdev, en, h2c_en); 1197e3ec7017SPing-Ke Shih return ret; 1198e3ec7017SPing-Ke Shih } 1199e3ec7017SPing-Ke Shih 1200e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1201a1b7163aSPing-Ke Shih if (dma_ch_mask & BIT(ch)) 1202a1b7163aSPing-Ke Shih continue; 1203e3ec7017SPing-Ke Shih ret = hfc_ch_ctrl(rtwdev, ch); 1204e3ec7017SPing-Ke Shih if (ret) 1205e3ec7017SPing-Ke Shih return ret; 1206e3ec7017SPing-Ke Shih } 1207e3ec7017SPing-Ke Shih 1208e3ec7017SPing-Ke Shih ret = hfc_pub_ctrl(rtwdev); 1209e3ec7017SPing-Ke Shih if (ret) 1210e3ec7017SPing-Ke Shih return ret; 1211e3ec7017SPing-Ke Shih 121239e9b569SPing-Ke Shih mac->hfc_mix_cfg(rtwdev); 1213e3ec7017SPing-Ke Shih if (en || h2c_en) { 121439e9b569SPing-Ke Shih mac->hfc_func_en(rtwdev, en, h2c_en); 1215e3ec7017SPing-Ke Shih udelay(10); 1216e3ec7017SPing-Ke Shih } 1217e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1218a1b7163aSPing-Ke Shih if (dma_ch_mask & BIT(ch)) 1219a1b7163aSPing-Ke Shih continue; 1220e3ec7017SPing-Ke Shih ret = hfc_upd_ch_info(rtwdev, ch); 1221e3ec7017SPing-Ke Shih if (ret) 1222e3ec7017SPing-Ke Shih return ret; 1223e3ec7017SPing-Ke Shih } 1224e3ec7017SPing-Ke Shih ret = hfc_upd_mix_info(rtwdev); 1225e3ec7017SPing-Ke Shih 1226e3ec7017SPing-Ke Shih return ret; 1227e3ec7017SPing-Ke Shih } 1228e3ec7017SPing-Ke Shih 1229e3ec7017SPing-Ke Shih #define PWR_POLL_CNT 2000 1230e3ec7017SPing-Ke Shih static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1231e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cfg) 1232e3ec7017SPing-Ke Shih { 1233e3ec7017SPing-Ke Shih u8 val = 0; 1234e3ec7017SPing-Ke Shih int ret; 1235e3ec7017SPing-Ke Shih u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1236e3ec7017SPing-Ke Shih cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1237e3ec7017SPing-Ke Shih 1238e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1239e3ec7017SPing-Ke Shih 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1240e3ec7017SPing-Ke Shih 1241e3ec7017SPing-Ke Shih if (!ret) 1242e3ec7017SPing-Ke Shih return 0; 1243e3ec7017SPing-Ke Shih 1244e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1245e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1246e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1247e3ec7017SPing-Ke Shih 1248e3ec7017SPing-Ke Shih return -EBUSY; 1249e3ec7017SPing-Ke Shih } 1250e3ec7017SPing-Ke Shih 1251e3ec7017SPing-Ke Shih static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1252e3ec7017SPing-Ke Shih u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1253e3ec7017SPing-Ke Shih { 1254e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cur_cfg; 1255e3ec7017SPing-Ke Shih u32 addr; 1256e3ec7017SPing-Ke Shih u8 val; 1257e3ec7017SPing-Ke Shih 1258e3ec7017SPing-Ke Shih for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1259e3ec7017SPing-Ke Shih if (!(cur_cfg->intf_msk & intf_msk) || 1260e3ec7017SPing-Ke Shih !(cur_cfg->cv_msk & cv_msk)) 1261e3ec7017SPing-Ke Shih continue; 1262e3ec7017SPing-Ke Shih 1263e3ec7017SPing-Ke Shih switch (cur_cfg->cmd) { 1264e3ec7017SPing-Ke Shih case PWR_CMD_WRITE: 1265e3ec7017SPing-Ke Shih addr = cur_cfg->addr; 1266e3ec7017SPing-Ke Shih 1267e3ec7017SPing-Ke Shih if (cur_cfg->base == PWR_BASE_SDIO) 1268e3ec7017SPing-Ke Shih addr |= SDIO_LOCAL_BASE_ADDR; 1269e3ec7017SPing-Ke Shih 1270e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, addr); 1271e3ec7017SPing-Ke Shih val &= ~(cur_cfg->msk); 1272e3ec7017SPing-Ke Shih val |= (cur_cfg->val & cur_cfg->msk); 1273e3ec7017SPing-Ke Shih 1274e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, addr, val); 1275e3ec7017SPing-Ke Shih break; 1276e3ec7017SPing-Ke Shih case PWR_CMD_POLL: 1277e3ec7017SPing-Ke Shih if (pwr_cmd_poll(rtwdev, cur_cfg)) 1278e3ec7017SPing-Ke Shih return -EBUSY; 1279e3ec7017SPing-Ke Shih break; 1280e3ec7017SPing-Ke Shih case PWR_CMD_DELAY: 1281e3ec7017SPing-Ke Shih if (cur_cfg->val == PWR_DELAY_US) 1282e3ec7017SPing-Ke Shih udelay(cur_cfg->addr); 1283e3ec7017SPing-Ke Shih else 1284e3ec7017SPing-Ke Shih fsleep(cur_cfg->addr * 1000); 1285e3ec7017SPing-Ke Shih break; 1286e3ec7017SPing-Ke Shih default: 1287e3ec7017SPing-Ke Shih return -EINVAL; 1288e3ec7017SPing-Ke Shih } 1289e3ec7017SPing-Ke Shih } 1290e3ec7017SPing-Ke Shih 1291e3ec7017SPing-Ke Shih return 0; 1292e3ec7017SPing-Ke Shih } 1293e3ec7017SPing-Ke Shih 1294e3ec7017SPing-Ke Shih static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1295e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq) 1296e3ec7017SPing-Ke Shih { 1297e3ec7017SPing-Ke Shih int ret; 1298e3ec7017SPing-Ke Shih 1299e3ec7017SPing-Ke Shih for (; *cfg_seq; cfg_seq++) { 1300e3ec7017SPing-Ke Shih ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1301e3ec7017SPing-Ke Shih PWR_INTF_MSK_PCIE, *cfg_seq); 1302e3ec7017SPing-Ke Shih if (ret) 1303e3ec7017SPing-Ke Shih return -EBUSY; 1304e3ec7017SPing-Ke Shih } 1305e3ec7017SPing-Ke Shih 1306e3ec7017SPing-Ke Shih return 0; 1307e3ec7017SPing-Ke Shih } 1308e3ec7017SPing-Ke Shih 1309e3ec7017SPing-Ke Shih static enum rtw89_rpwm_req_pwr_state 1310e3ec7017SPing-Ke Shih rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1311e3ec7017SPing-Ke Shih { 1312e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 1313e3ec7017SPing-Ke Shih 1314e3ec7017SPing-Ke Shih switch (rtwdev->ps_mode) { 1315e3ec7017SPing-Ke Shih case RTW89_PS_MODE_RFOFF: 1316e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1317e3ec7017SPing-Ke Shih break; 1318e3ec7017SPing-Ke Shih case RTW89_PS_MODE_CLK_GATED: 1319e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1320e3ec7017SPing-Ke Shih break; 1321e3ec7017SPing-Ke Shih case RTW89_PS_MODE_PWR_GATED: 1322e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1323e3ec7017SPing-Ke Shih break; 1324e3ec7017SPing-Ke Shih default: 1325e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1326e3ec7017SPing-Ke Shih break; 1327e3ec7017SPing-Ke Shih } 1328e3ec7017SPing-Ke Shih return state; 1329e3ec7017SPing-Ke Shih } 1330e3ec7017SPing-Ke Shih 1331e3ec7017SPing-Ke Shih static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 13327bfd05ffSChin-Yen Lee enum rtw89_rpwm_req_pwr_state req_pwr_state, 13337bfd05ffSChin-Yen Lee bool notify_wake) 1334e3ec7017SPing-Ke Shih { 1335e3ec7017SPing-Ke Shih u16 request; 1336e3ec7017SPing-Ke Shih 13377bfd05ffSChin-Yen Lee spin_lock_bh(&rtwdev->rpwm_lock); 13387bfd05ffSChin-Yen Lee 1339e3ec7017SPing-Ke Shih request = rtw89_read16(rtwdev, R_AX_RPWM); 1340e3ec7017SPing-Ke Shih request ^= request | PS_RPWM_TOGGLE; 13417bfd05ffSChin-Yen Lee request |= req_pwr_state; 1342e3ec7017SPing-Ke Shih 13437bfd05ffSChin-Yen Lee if (notify_wake) { 13447bfd05ffSChin-Yen Lee request |= PS_RPWM_NOTIFY_WAKE; 13457bfd05ffSChin-Yen Lee } else { 1346e3ec7017SPing-Ke Shih rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1347e3ec7017SPing-Ke Shih RPWM_SEQ_NUM_MAX; 13487bfd05ffSChin-Yen Lee request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 13497bfd05ffSChin-Yen Lee rtwdev->mac.rpwm_seq_num); 1350e3ec7017SPing-Ke Shih 1351e3ec7017SPing-Ke Shih if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1352e3ec7017SPing-Ke Shih request |= PS_RPWM_ACK; 13537bfd05ffSChin-Yen Lee } 1354e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 13557bfd05ffSChin-Yen Lee 13567bfd05ffSChin-Yen Lee spin_unlock_bh(&rtwdev->rpwm_lock); 1357e3ec7017SPing-Ke Shih } 1358e3ec7017SPing-Ke Shih 1359e3ec7017SPing-Ke Shih static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1360e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state req_pwr_state) 1361e3ec7017SPing-Ke Shih { 1362e3ec7017SPing-Ke Shih bool request_deep_mode; 1363e3ec7017SPing-Ke Shih bool in_deep_mode; 1364e3ec7017SPing-Ke Shih u8 rpwm_req_num; 1365e3ec7017SPing-Ke Shih u8 cpwm_rsp_seq; 1366e3ec7017SPing-Ke Shih u8 cpwm_seq; 1367e3ec7017SPing-Ke Shih u8 cpwm_status; 1368e3ec7017SPing-Ke Shih 1369e3ec7017SPing-Ke Shih if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1370e3ec7017SPing-Ke Shih request_deep_mode = true; 1371e3ec7017SPing-Ke Shih else 1372e3ec7017SPing-Ke Shih request_deep_mode = false; 1373e3ec7017SPing-Ke Shih 1374e3ec7017SPing-Ke Shih if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1375e3ec7017SPing-Ke Shih in_deep_mode = true; 1376e3ec7017SPing-Ke Shih else 1377e3ec7017SPing-Ke Shih in_deep_mode = false; 1378e3ec7017SPing-Ke Shih 1379e3ec7017SPing-Ke Shih if (request_deep_mode != in_deep_mode) 1380e3ec7017SPing-Ke Shih return -EPERM; 1381e3ec7017SPing-Ke Shih 1382e3ec7017SPing-Ke Shih if (request_deep_mode) 1383e3ec7017SPing-Ke Shih return 0; 1384e3ec7017SPing-Ke Shih 1385e3ec7017SPing-Ke Shih rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1386e1757e80SPing-Ke Shih cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1387e3ec7017SPing-Ke Shih PS_CPWM_RSP_SEQ_NUM); 1388e3ec7017SPing-Ke Shih 1389e3ec7017SPing-Ke Shih if (rpwm_req_num != cpwm_rsp_seq) 1390e3ec7017SPing-Ke Shih return -EPERM; 1391e3ec7017SPing-Ke Shih 1392e3ec7017SPing-Ke Shih rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1393e3ec7017SPing-Ke Shih CPWM_SEQ_NUM_MAX; 1394e3ec7017SPing-Ke Shih 1395e1757e80SPing-Ke Shih cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1396e3ec7017SPing-Ke Shih if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1397e3ec7017SPing-Ke Shih return -EPERM; 1398e3ec7017SPing-Ke Shih 1399e1757e80SPing-Ke Shih cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1400e3ec7017SPing-Ke Shih if (cpwm_status != req_pwr_state) 1401e3ec7017SPing-Ke Shih return -EPERM; 1402e3ec7017SPing-Ke Shih 1403e3ec7017SPing-Ke Shih return 0; 1404e3ec7017SPing-Ke Shih } 1405e3ec7017SPing-Ke Shih 1406e3ec7017SPing-Ke Shih void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1407e3ec7017SPing-Ke Shih { 1408e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 140939a76521SPing-Ke Shih unsigned long delay = enter ? 10 : 150; 1410e3ec7017SPing-Ke Shih int ret; 141148c0e347SChin-Yen Lee int i; 1412e3ec7017SPing-Ke Shih 1413e3ec7017SPing-Ke Shih if (enter) 1414e3ec7017SPing-Ke Shih state = rtw89_mac_get_req_pwr_state(rtwdev); 1415e3ec7017SPing-Ke Shih else 1416e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1417e3ec7017SPing-Ke Shih 141848c0e347SChin-Yen Lee for (i = 0; i < RPWM_TRY_CNT; i++) { 14197bfd05ffSChin-Yen Lee rtw89_mac_send_rpwm(rtwdev, state, false); 142048c0e347SChin-Yen Lee ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 142148c0e347SChin-Yen Lee !ret, delay, 15000, false, 142248c0e347SChin-Yen Lee rtwdev, state); 142348c0e347SChin-Yen Lee if (!ret) 142448c0e347SChin-Yen Lee break; 142548c0e347SChin-Yen Lee 142648c0e347SChin-Yen Lee if (i == RPWM_TRY_CNT - 1) 1427e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1428e3ec7017SPing-Ke Shih enter ? "entering" : "leaving"); 142948c0e347SChin-Yen Lee else 143048c0e347SChin-Yen Lee rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 143148c0e347SChin-Yen Lee "%d time firmware failed to ack for %s ps mode\n", 143248c0e347SChin-Yen Lee i + 1, enter ? "entering" : "leaving"); 143348c0e347SChin-Yen Lee } 1434e3ec7017SPing-Ke Shih } 1435e3ec7017SPing-Ke Shih 14367bfd05ffSChin-Yen Lee void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 14377bfd05ffSChin-Yen Lee { 14387bfd05ffSChin-Yen Lee enum rtw89_rpwm_req_pwr_state state; 14397bfd05ffSChin-Yen Lee 14407bfd05ffSChin-Yen Lee state = rtw89_mac_get_req_pwr_state(rtwdev); 14417bfd05ffSChin-Yen Lee rtw89_mac_send_rpwm(rtwdev, state, true); 14427bfd05ffSChin-Yen Lee } 14437bfd05ffSChin-Yen Lee 1444e3ec7017SPing-Ke Shih static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1445e3ec7017SPing-Ke Shih { 1446e3ec7017SPing-Ke Shih #define PWR_ACT 1 1447e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1448e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq; 14492a7e54dbSPing-Ke Shih int (*cfg_func)(struct rtw89_dev *rtwdev); 1450e3ec7017SPing-Ke Shih int ret; 1451e3ec7017SPing-Ke Shih u8 val; 1452e3ec7017SPing-Ke Shih 14532a7e54dbSPing-Ke Shih if (on) { 1454e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_on_seq; 14552a7e54dbSPing-Ke Shih cfg_func = chip->ops->pwr_on_func; 14562a7e54dbSPing-Ke Shih } else { 1457e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_off_seq; 14582a7e54dbSPing-Ke Shih cfg_func = chip->ops->pwr_off_func; 14592a7e54dbSPing-Ke Shih } 1460e3ec7017SPing-Ke Shih 1461e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1462e3ec7017SPing-Ke Shih __rtw89_leave_ps_mode(rtwdev); 1463e3ec7017SPing-Ke Shih 1464e3ec7017SPing-Ke Shih val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1465e3ec7017SPing-Ke Shih if (on && val == PWR_ACT) { 1466e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC has already powered on\n"); 1467e3ec7017SPing-Ke Shih return -EBUSY; 1468e3ec7017SPing-Ke Shih } 1469e3ec7017SPing-Ke Shih 14702a7e54dbSPing-Ke Shih ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1471e3ec7017SPing-Ke Shih if (ret) 1472e3ec7017SPing-Ke Shih return ret; 1473e3ec7017SPing-Ke Shih 1474e3ec7017SPing-Ke Shih if (on) { 1475e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1476cfb99433SPing-Ke Shih set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1477cfb99433SPing-Ke Shih set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1478e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1479e3ec7017SPing-Ke Shih } else { 1480e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1481cfb99433SPing-Ke Shih clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1482cfb99433SPing-Ke Shih clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1483cfb99433SPing-Ke Shih clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1484e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1485e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1486967439c7SZong-Zhe Yang rtw89_set_entity_state(rtwdev, false); 1487e3ec7017SPing-Ke Shih } 1488e3ec7017SPing-Ke Shih 1489e3ec7017SPing-Ke Shih return 0; 1490e3ec7017SPing-Ke Shih #undef PWR_ACT 1491e3ec7017SPing-Ke Shih } 1492e3ec7017SPing-Ke Shih 1493e3ec7017SPing-Ke Shih void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1494e3ec7017SPing-Ke Shih { 1495e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 1496e3ec7017SPing-Ke Shih } 1497e3ec7017SPing-Ke Shih 1498fc663fa0SPing-Ke Shih static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1499e3ec7017SPing-Ke Shih { 1500e3ec7017SPing-Ke Shih u32 func_en = 0; 1501e3ec7017SPing-Ke Shih u32 ck_en = 0; 1502e3ec7017SPing-Ke Shih u32 c1pc_en = 0; 1503e3ec7017SPing-Ke Shih u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1504e3ec7017SPing-Ke Shih u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1505e3ec7017SPing-Ke Shih 1506e3ec7017SPing-Ke Shih func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1507e3ec7017SPing-Ke Shih B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 15085cb5562dSPing-Ke Shih B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 15095cb5562dSPing-Ke Shih B_AX_CMAC_CRPRT; 1510e3ec7017SPing-Ke Shih ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1511e3ec7017SPing-Ke Shih B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1512e3ec7017SPing-Ke Shih B_AX_RMAC_CKEN; 1513e3ec7017SPing-Ke Shih c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1514e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1515e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1516e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1517e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1518e3ec7017SPing-Ke Shih 1519e3ec7017SPing-Ke Shih if (en) { 1520e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1521e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1522e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1523e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1524e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1525e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1526e3ec7017SPing-Ke Shih } 1527e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1528e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1529e3ec7017SPing-Ke Shih } else { 1530e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1531e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1532e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1533e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1534e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1535e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1536e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1537e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1538e3ec7017SPing-Ke Shih } 1539e3ec7017SPing-Ke Shih } 1540e3ec7017SPing-Ke Shih 1541e3ec7017SPing-Ke Shih return 0; 1542e3ec7017SPing-Ke Shih } 1543e3ec7017SPing-Ke Shih 1544fc663fa0SPing-Ke Shih static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1545e3ec7017SPing-Ke Shih { 1546828a4396SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1547e3ec7017SPing-Ke Shih u32 val32; 1548e3ec7017SPing-Ke Shih 1549828a4396SChia-Yuan Li if (chip_id == RTL8852C) 1550828a4396SChia-Yuan Li val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1551828a4396SChia-Yuan Li B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1552828a4396SChia-Yuan Li B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1553828a4396SChia-Yuan Li B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1554828a4396SChia-Yuan Li B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1555828a4396SChia-Yuan Li B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1556828a4396SChia-Yuan Li B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1557828a4396SChia-Yuan Li else 1558828a4396SChia-Yuan Li val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1559828a4396SChia-Yuan Li B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1560828a4396SChia-Yuan Li B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1561828a4396SChia-Yuan Li B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1562828a4396SChia-Yuan Li B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1563828a4396SChia-Yuan Li B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1564828a4396SChia-Yuan Li B_AX_DMAC_CRPRT); 1565e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1566e3ec7017SPing-Ke Shih 1567e3ec7017SPing-Ke Shih val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1568e3ec7017SPing-Ke Shih B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1569e3ec7017SPing-Ke Shih B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1570828a4396SChia-Yuan Li B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1571190dc12dSPing-Ke Shih if (chip_id == RTL8852BT) 1572190dc12dSPing-Ke Shih val32 |= B_AX_AXIDMA_CLK_EN; 1573e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1574e3ec7017SPing-Ke Shih 157543863efeSChangcheng Deng return 0; 1576e3ec7017SPing-Ke Shih } 1577e3ec7017SPing-Ke Shih 1578fc663fa0SPing-Ke Shih static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1579e3ec7017SPing-Ke Shih { 1580828a4396SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1581828a4396SChia-Yuan Li 1582190dc12dSPing-Ke Shih if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 158314b6e9f4SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1584828a4396SChia-Yuan Li B_AX_OCP_L1_MASK); 1585e3ec7017SPing-Ke Shih 1586e3ec7017SPing-Ke Shih return 0; 1587e3ec7017SPing-Ke Shih } 1588e3ec7017SPing-Ke Shih 1589fc663fa0SPing-Ke Shih static int sys_init_ax(struct rtw89_dev *rtwdev) 1590e3ec7017SPing-Ke Shih { 1591e3ec7017SPing-Ke Shih int ret; 1592e3ec7017SPing-Ke Shih 1593fc663fa0SPing-Ke Shih ret = dmac_func_en_ax(rtwdev); 1594e3ec7017SPing-Ke Shih if (ret) 1595e3ec7017SPing-Ke Shih return ret; 1596e3ec7017SPing-Ke Shih 1597fc663fa0SPing-Ke Shih ret = cmac_func_en_ax(rtwdev, 0, true); 1598e3ec7017SPing-Ke Shih if (ret) 1599e3ec7017SPing-Ke Shih return ret; 1600e3ec7017SPing-Ke Shih 1601fc663fa0SPing-Ke Shih ret = chip_func_en_ax(rtwdev); 1602e3ec7017SPing-Ke Shih if (ret) 1603e3ec7017SPing-Ke Shih return ret; 1604e3ec7017SPing-Ke Shih 1605e3ec7017SPing-Ke Shih return ret; 1606e3ec7017SPing-Ke Shih } 1607e3ec7017SPing-Ke Shih 160830645118SPing-Ke Shih const struct rtw89_mac_size_set rtw89_mac_size = { 160930645118SPing-Ke Shih .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1610fdb3bb0aSPing-Ke Shih .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0}, 1611fdb3bb0aSPing-Ke Shih .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0}, 1612e3ec7017SPing-Ke Shih /* PCIE 64 */ 161330645118SPing-Ke Shih .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1614fdb3bb0aSPing-Ke Shih .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1615e3ec7017SPing-Ke Shih /* DLFW */ 161630645118SPing-Ke Shih .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1617fdb3bb0aSPing-Ke Shih .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1618a1cb0971SPing-Ke Shih /* PCIE 64 */ 1619a1cb0971SPing-Ke Shih .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1620c0426c44SPing-Ke Shih /* 8852B PCIE SCC */ 1621c0426c44SPing-Ke Shih .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1622a1cb0971SPing-Ke Shih /* DLFW */ 1623a1cb0971SPing-Ke Shih .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 162479d099e0SPing-Ke Shih /* 8852C DLFW */ 162530645118SPing-Ke Shih .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 162679d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 162730645118SPing-Ke Shih .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1628c4dea048SPing-Ke Shih .wde_size23 = {RTW89_WDE_PG_64, 1022, 2,}, 1629e3ec7017SPing-Ke Shih /* PCIE */ 163030645118SPing-Ke Shih .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 16314ae8ac20SPing-Ke Shih .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1632fdb3bb0aSPing-Ke Shih .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1633e3ec7017SPing-Ke Shih /* DLFW */ 163430645118SPing-Ke Shih .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1635a1cb0971SPing-Ke Shih /* PCIE 64 */ 1636a1cb0971SPing-Ke Shih .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1637a1cb0971SPing-Ke Shih /* DLFW */ 1638a1cb0971SPing-Ke Shih .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1639c4dea048SPing-Ke Shih .ple_size9 = {RTW89_PLE_PG_128, 2288, 16,}, 164079d099e0SPing-Ke Shih /* 8852C DLFW */ 164130645118SPing-Ke Shih .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 164279d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 164330645118SPing-Ke Shih .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1644e3ec7017SPing-Ke Shih /* PCIE 64 */ 164530645118SPing-Ke Shih .wde_qt0 = {3792, 196, 0, 107,}, 1646fdb3bb0aSPing-Ke Shih .wde_qt0_v1 = {3302, 6, 0, 20,}, 1647e3ec7017SPing-Ke Shih /* DLFW */ 164830645118SPing-Ke Shih .wde_qt4 = {0, 0, 0, 0,}, 1649a1cb0971SPing-Ke Shih /* PCIE 64 */ 1650a1cb0971SPing-Ke Shih .wde_qt6 = {448, 48, 0, 16,}, 1651c0426c44SPing-Ke Shih /* 8852B PCIE SCC */ 1652c0426c44SPing-Ke Shih .wde_qt7 = {446, 48, 0, 16,}, 165379d099e0SPing-Ke Shih /* 8852C DLFW */ 165430645118SPing-Ke Shih .wde_qt17 = {0, 0, 0, 0,}, 165579d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 165630645118SPing-Ke Shih .wde_qt18 = {3228, 60, 0, 40,}, 1657c4dea048SPing-Ke Shih .wde_qt23 = {958, 48, 0, 16,}, 16584ae8ac20SPing-Ke Shih .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 16594ae8ac20SPing-Ke Shih .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1660e3ec7017SPing-Ke Shih /* PCIE SCC */ 166130645118SPing-Ke Shih .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1662e3ec7017SPing-Ke Shih /* PCIE SCC */ 166330645118SPing-Ke Shih .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1664fdb3bb0aSPing-Ke Shih .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1665e3ec7017SPing-Ke Shih /* DLFW */ 166630645118SPing-Ke Shih .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1667a1cb0971SPing-Ke Shih /* PCIE 64 */ 1668a1cb0971SPing-Ke Shih .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 166979d099e0SPing-Ke Shih /* DLFW 52C */ 167030645118SPing-Ke Shih .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 167179d099e0SPing-Ke Shih /* DLFW 52C */ 167230645118SPing-Ke Shih .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 167379d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 167430645118SPing-Ke Shih .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 167579d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 167630645118SPing-Ke Shih .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1677c4dea048SPing-Ke Shih .ple_qt57 = {147, 0, 16, 20, 13, 13, 178, 0, 32, 14, 8, 0,}, 1678a1cb0971SPing-Ke Shih /* PCIE 64 */ 1679a1cb0971SPing-Ke Shih .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1680c4dea048SPing-Ke Shih .ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,}, 16817a68ec3dSChih-Kang Chang /* 8852A PCIE WOW */ 16827a68ec3dSChih-Kang Chang .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 16836863ad91SChin-Yen Lee /* 8852B PCIE WOW */ 16846863ad91SChin-Yen Lee .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1685c4dea048SPing-Ke Shih /* 8852BT PCIE WOW */ 1686c4dea048SPing-Ke Shih .ple_qt_52bt_wow = {147, 0, 32, 20, 1860, 13, 1929, 0, 1879, 14, 24, 0,}, 168785d1539cSPing-Ke Shih /* 8851B PCIE WOW */ 168885d1539cSPing-Ke Shih .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 16894ae8ac20SPing-Ke Shih .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1690fdb3bb0aSPing-Ke Shih .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1691fdb3bb0aSPing-Ke Shih .rsvd0_size0 = {212992, 0,}, 1692fdb3bb0aSPing-Ke Shih .rsvd1_size0 = {587776, 2048,}, 169379d099e0SPing-Ke Shih }; 169430645118SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_size); 169579d099e0SPing-Ke Shih 1696e3ec7017SPing-Ke Shih static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1697e3ec7017SPing-Ke Shih enum rtw89_qta_mode mode) 1698e3ec7017SPing-Ke Shih { 1699e3ec7017SPing-Ke Shih struct rtw89_mac_info *mac = &rtwdev->mac; 1700e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 1701e3ec7017SPing-Ke Shih 1702e3ec7017SPing-Ke Shih cfg = &rtwdev->chip->dle_mem[mode]; 1703e3ec7017SPing-Ke Shih if (!cfg) 1704e3ec7017SPing-Ke Shih return NULL; 1705e3ec7017SPing-Ke Shih 1706e3ec7017SPing-Ke Shih if (cfg->mode != mode) { 1707e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1708e3ec7017SPing-Ke Shih return NULL; 1709e3ec7017SPing-Ke Shih } 1710e3ec7017SPing-Ke Shih 1711cecf1643SPing-Ke Shih mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1712e3ec7017SPing-Ke Shih mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1713cecf1643SPing-Ke Shih mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1714e3ec7017SPing-Ke Shih mac->dle_info.qta_mode = mode; 1715e3ec7017SPing-Ke Shih mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1716e3ec7017SPing-Ke Shih mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1717e3ec7017SPing-Ke Shih 1718e3ec7017SPing-Ke Shih return cfg; 1719e3ec7017SPing-Ke Shih } 1720e3ec7017SPing-Ke Shih 1721cecf1643SPing-Ke Shih int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1722cecf1643SPing-Ke Shih enum rtw89_mac_dle_rsvd_qt_type type, 1723cecf1643SPing-Ke Shih struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1724cecf1643SPing-Ke Shih { 1725cecf1643SPing-Ke Shih struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1726cecf1643SPing-Ke Shih const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1727cecf1643SPing-Ke Shih 1728cecf1643SPing-Ke Shih switch (type) { 1729cecf1643SPing-Ke Shih case DLE_RSVD_QT_MPDU_INFO: 1730cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg; 1731cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1732cecf1643SPing-Ke Shih break; 1733cecf1643SPing-Ke Shih case DLE_RSVD_QT_B0_CSI: 1734cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1735cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->b0_csi; 1736cecf1643SPing-Ke Shih break; 1737cecf1643SPing-Ke Shih case DLE_RSVD_QT_B1_CSI: 1738cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg + 1739cecf1643SPing-Ke Shih rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1740cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->b1_csi; 1741cecf1643SPing-Ke Shih break; 1742cecf1643SPing-Ke Shih case DLE_RSVD_QT_B0_LMR: 1743cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg + 1744cecf1643SPing-Ke Shih rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1745cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->b0_lmr; 1746cecf1643SPing-Ke Shih break; 1747cecf1643SPing-Ke Shih case DLE_RSVD_QT_B1_LMR: 1748cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg + 1749cecf1643SPing-Ke Shih rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1750cecf1643SPing-Ke Shih rsvd_qt->b0_lmr; 1751cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->b1_lmr; 1752cecf1643SPing-Ke Shih break; 1753cecf1643SPing-Ke Shih case DLE_RSVD_QT_B0_FTM: 1754cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg + 1755cecf1643SPing-Ke Shih rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1756cecf1643SPing-Ke Shih rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1757cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->b0_ftm; 1758cecf1643SPing-Ke Shih break; 1759cecf1643SPing-Ke Shih case DLE_RSVD_QT_B1_FTM: 1760cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg + 1761cecf1643SPing-Ke Shih rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1762cecf1643SPing-Ke Shih rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1763cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->b1_ftm; 1764cecf1643SPing-Ke Shih break; 1765cecf1643SPing-Ke Shih default: 1766cecf1643SPing-Ke Shih return -EINVAL; 1767cecf1643SPing-Ke Shih } 1768cecf1643SPing-Ke Shih 1769cecf1643SPing-Ke Shih cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1770cecf1643SPing-Ke Shih 1771cecf1643SPing-Ke Shih return 0; 1772cecf1643SPing-Ke Shih } 1773cecf1643SPing-Ke Shih 177427ea6be9SZong-Zhe Yang static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 177541d56769SChih-Kang Chang { 177641d56769SChih-Kang Chang struct rtw89_mac_dle_dfi_qempty qempty; 17772706cb25SZong-Zhe Yang u32 grpnum, qtmp, val32, msk32; 177841d56769SChih-Kang Chang int i, j, ret; 177941d56769SChih-Kang Chang 17802706cb25SZong-Zhe Yang grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 178141d56769SChih-Kang Chang qempty.dle_type = DLE_CTRL_TYPE_WDE; 178241d56769SChih-Kang Chang 17832706cb25SZong-Zhe Yang for (i = 0; i < grpnum; i++) { 178441d56769SChih-Kang Chang qempty.grpsel = i; 178527ea6be9SZong-Zhe Yang ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 178641d56769SChih-Kang Chang if (ret) { 178741d56769SChih-Kang Chang rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 178841d56769SChih-Kang Chang return false; 178941d56769SChih-Kang Chang } 179041d56769SChih-Kang Chang qtmp = qempty.qempty; 179141d56769SChih-Kang Chang for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 17926f8d3655SChia-Yuan Li val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 179341d56769SChih-Kang Chang if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 179441d56769SChih-Kang Chang return false; 179541d56769SChih-Kang Chang qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 179641d56769SChih-Kang Chang } 179741d56769SChih-Kang Chang } 179841d56769SChih-Kang Chang 17992706cb25SZong-Zhe Yang qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 180027ea6be9SZong-Zhe Yang ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 180141d56769SChih-Kang Chang if (ret) { 180241d56769SChih-Kang Chang rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 180341d56769SChih-Kang Chang return false; 180441d56769SChih-Kang Chang } 180541d56769SChih-Kang Chang msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 180641d56769SChih-Kang Chang if ((qempty.qempty & msk32) != msk32) 180741d56769SChih-Kang Chang return false; 180841d56769SChih-Kang Chang 180941d56769SChih-Kang Chang if (rtwdev->dbcc_en) { 181041d56769SChih-Kang Chang msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 181141d56769SChih-Kang Chang if ((qempty.qempty & msk32) != msk32) 181241d56769SChih-Kang Chang return false; 181341d56769SChih-Kang Chang } 181441d56769SChih-Kang Chang 181541d56769SChih-Kang Chang msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 181641d56769SChih-Kang Chang B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 181741d56769SChih-Kang Chang B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 181841d56769SChih-Kang Chang B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 181941d56769SChih-Kang Chang B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 182041d56769SChih-Kang Chang B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 182141d56769SChih-Kang Chang B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 182241d56769SChih-Kang Chang B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 182341d56769SChih-Kang Chang val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 182441d56769SChih-Kang Chang 182541d56769SChih-Kang Chang return (val32 & msk32) == msk32; 182641d56769SChih-Kang Chang } 182741d56769SChih-Kang Chang 1828aabe741eSPing-Ke Shih static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1829e3ec7017SPing-Ke Shih { 1830aabe741eSPing-Ke Shih const struct rtw89_dle_size *wde = cfg->wde_size; 1831aabe741eSPing-Ke Shih const struct rtw89_dle_size *ple = cfg->ple_size; 1832aabe741eSPing-Ke Shih u32 used; 1833aabe741eSPing-Ke Shih 1834aabe741eSPing-Ke Shih used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1835e3ec7017SPing-Ke Shih ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1836aabe741eSPing-Ke Shih 1837aabe741eSPing-Ke Shih if (cfg->rsvd0_size && cfg->rsvd1_size) { 1838aabe741eSPing-Ke Shih used += cfg->rsvd0_size->size; 1839aabe741eSPing-Ke Shih used += cfg->rsvd1_size->size; 1840aabe741eSPing-Ke Shih } 1841aabe741eSPing-Ke Shih 1842aabe741eSPing-Ke Shih return used; 1843e3ec7017SPing-Ke Shih } 1844e3ec7017SPing-Ke Shih 18455f8c35b9SPing-Ke Shih static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 18465f8c35b9SPing-Ke Shih enum rtw89_qta_mode mode) 18475f8c35b9SPing-Ke Shih { 18485f8c35b9SPing-Ke Shih u32 size = rtwdev->chip->fifo_size; 18495f8c35b9SPing-Ke Shih 18505f8c35b9SPing-Ke Shih if (mode == RTW89_QTA_SCC) 18515f8c35b9SPing-Ke Shih size -= rtwdev->chip->dle_scc_rsvd_size; 18525f8c35b9SPing-Ke Shih 18535f8c35b9SPing-Ke Shih return size; 18545f8c35b9SPing-Ke Shih } 18555f8c35b9SPing-Ke Shih 185639e9b569SPing-Ke Shih static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 1857e3ec7017SPing-Ke Shih { 1858e3ec7017SPing-Ke Shih if (enable) 1859e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1860e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1861e3ec7017SPing-Ke Shih else 1862e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1863e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1864e3ec7017SPing-Ke Shih } 1865e3ec7017SPing-Ke Shih 186639e9b569SPing-Ke Shih static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 1867e3ec7017SPing-Ke Shih { 18685c3afcbaSPing-Ke Shih u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 18695c3afcbaSPing-Ke Shih 18705c3afcbaSPing-Ke Shih if (enable) { 18715c3afcbaSPing-Ke Shih if (rtwdev->chip->chip_id == RTL8851B) 18725c3afcbaSPing-Ke Shih val |= B_AX_AXIDMA_CLK_EN; 18735c3afcbaSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 18745c3afcbaSPing-Ke Shih } else { 18755c3afcbaSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 18765c3afcbaSPing-Ke Shih } 1877e3ec7017SPing-Ke Shih } 1878e3ec7017SPing-Ke Shih 187939e9b569SPing-Ke Shih static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1880e3ec7017SPing-Ke Shih { 1881e3ec7017SPing-Ke Shih const struct rtw89_dle_size *size_cfg; 1882e3ec7017SPing-Ke Shih u32 val; 1883e3ec7017SPing-Ke Shih u8 bound = 0; 1884e3ec7017SPing-Ke Shih 1885e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1886e3ec7017SPing-Ke Shih size_cfg = cfg->wde_size; 1887e3ec7017SPing-Ke Shih 1888e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1889e3ec7017SPing-Ke Shih default: 1890e3ec7017SPing-Ke Shih case RTW89_WDE_PG_64: 1891e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1892e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1893e3ec7017SPing-Ke Shih break; 1894e3ec7017SPing-Ke Shih case RTW89_WDE_PG_128: 1895e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1896e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1897e3ec7017SPing-Ke Shih break; 1898e3ec7017SPing-Ke Shih case RTW89_WDE_PG_256: 1899e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1900e3ec7017SPing-Ke Shih return -EINVAL; 1901e3ec7017SPing-Ke Shih } 1902e3ec7017SPing-Ke Shih 1903e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1904e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1905e3ec7017SPing-Ke Shih B_AX_WDE_FREE_PAGE_NUM_MASK); 1906e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1907e3ec7017SPing-Ke Shih 1908e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1909e3ec7017SPing-Ke Shih bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1910e3ec7017SPing-Ke Shih * size_cfg->pge_size / DLE_BOUND_UNIT; 1911e3ec7017SPing-Ke Shih size_cfg = cfg->ple_size; 1912e3ec7017SPing-Ke Shih 1913e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1914e3ec7017SPing-Ke Shih default: 1915e3ec7017SPing-Ke Shih case RTW89_PLE_PG_64: 1916e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1917e3ec7017SPing-Ke Shih return -EINVAL; 1918e3ec7017SPing-Ke Shih case RTW89_PLE_PG_128: 1919e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1920e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1921e3ec7017SPing-Ke Shih break; 1922e3ec7017SPing-Ke Shih case RTW89_PLE_PG_256: 1923e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1924e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1925e3ec7017SPing-Ke Shih break; 1926e3ec7017SPing-Ke Shih } 1927e3ec7017SPing-Ke Shih 1928e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1929e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1930e3ec7017SPing-Ke Shih B_AX_PLE_FREE_PAGE_NUM_MASK); 1931e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1932e3ec7017SPing-Ke Shih 1933e3ec7017SPing-Ke Shih return 0; 1934e3ec7017SPing-Ke Shih } 1935e3ec7017SPing-Ke Shih 193639e9b569SPing-Ke Shih static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 19370d16d8fbSPing-Ke Shih { 19380d16d8fbSPing-Ke Shih u32 reg, mask; 19390d16d8fbSPing-Ke Shih u32 ini; 19400d16d8fbSPing-Ke Shih 19410d16d8fbSPing-Ke Shih if (wde_or_ple) { 19420d16d8fbSPing-Ke Shih reg = R_AX_WDE_INI_STATUS; 19430d16d8fbSPing-Ke Shih mask = WDE_MGN_INI_RDY; 19440d16d8fbSPing-Ke Shih } else { 19450d16d8fbSPing-Ke Shih reg = R_AX_PLE_INI_STATUS; 19460d16d8fbSPing-Ke Shih mask = PLE_MGN_INI_RDY; 19470d16d8fbSPing-Ke Shih } 19480d16d8fbSPing-Ke Shih 19490d16d8fbSPing-Ke Shih return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 19500d16d8fbSPing-Ke Shih 2000, false, rtwdev, reg); 19510d16d8fbSPing-Ke Shih } 19520d16d8fbSPing-Ke Shih 1953e3ec7017SPing-Ke Shih #define INVALID_QT_WCPU U16_MAX 1954e3ec7017SPing-Ke Shih #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1955e3ec7017SPing-Ke Shih do { \ 1956525c06c8SPing-Ke Shih val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1957525c06c8SPing-Ke Shih u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1958e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, \ 1959e3ec7017SPing-Ke Shih R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1960e3ec7017SPing-Ke Shih val); \ 1961e3ec7017SPing-Ke Shih } while (0) 1962e3ec7017SPing-Ke Shih #define SET_QUOTA(_x, _module, _idx) \ 1963e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1964e3ec7017SPing-Ke Shih 196539e9b569SPing-Ke Shih static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 1966e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *min_cfg, 1967e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *max_cfg, 1968e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 1969e3ec7017SPing-Ke Shih { 1970e3ec7017SPing-Ke Shih u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1971e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu : min_cfg->wcpu; 1972e3ec7017SPing-Ke Shih u32 val; 1973e3ec7017SPing-Ke Shih 1974e3ec7017SPing-Ke Shih SET_QUOTA(hif, WDE, 0); 1975e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1976e3ec7017SPing-Ke Shih SET_QUOTA(pkt_in, WDE, 3); 1977e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, WDE, 4); 1978e3ec7017SPing-Ke Shih } 1979e3ec7017SPing-Ke Shih 198039e9b569SPing-Ke Shih static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 1981e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *min_cfg, 1982e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *max_cfg) 1983e3ec7017SPing-Ke Shih { 1984e3ec7017SPing-Ke Shih u32 val; 1985e3ec7017SPing-Ke Shih 1986e3ec7017SPing-Ke Shih SET_QUOTA(cma0_tx, PLE, 0); 1987e3ec7017SPing-Ke Shih SET_QUOTA(cma1_tx, PLE, 1); 1988e3ec7017SPing-Ke Shih SET_QUOTA(c2h, PLE, 2); 1989e3ec7017SPing-Ke Shih SET_QUOTA(h2c, PLE, 3); 1990e3ec7017SPing-Ke Shih SET_QUOTA(wcpu, PLE, 4); 1991e3ec7017SPing-Ke Shih SET_QUOTA(mpdu_proc, PLE, 5); 1992e3ec7017SPing-Ke Shih SET_QUOTA(cma0_dma, PLE, 6); 1993e3ec7017SPing-Ke Shih SET_QUOTA(cma1_dma, PLE, 7); 1994e3ec7017SPing-Ke Shih SET_QUOTA(bb_rpt, PLE, 8); 1995e3ec7017SPing-Ke Shih SET_QUOTA(wd_rel, PLE, 9); 1996e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, PLE, 10); 199779d099e0SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852C) 199879d099e0SPing-Ke Shih SET_QUOTA(tx_rpt, PLE, 11); 1999e3ec7017SPing-Ke Shih } 2000e3ec7017SPing-Ke Shih 20017a68ec3dSChih-Kang Chang int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 20027a68ec3dSChih-Kang Chang { 20037a68ec3dSChih-Kang Chang const struct rtw89_ple_quota *min_cfg, *max_cfg; 20047a68ec3dSChih-Kang Chang const struct rtw89_dle_mem *cfg; 20057a68ec3dSChih-Kang Chang u32 val; 20067a68ec3dSChih-Kang Chang 20077a68ec3dSChih-Kang Chang if (rtwdev->chip->chip_id == RTL8852C) 20087a68ec3dSChih-Kang Chang return 0; 20097a68ec3dSChih-Kang Chang 20107a68ec3dSChih-Kang Chang if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 20117a68ec3dSChih-Kang Chang rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 20127a68ec3dSChih-Kang Chang return -EINVAL; 20137a68ec3dSChih-Kang Chang } 20147a68ec3dSChih-Kang Chang 20157a68ec3dSChih-Kang Chang if (wow) 20167a68ec3dSChih-Kang Chang cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 20177a68ec3dSChih-Kang Chang else 20187a68ec3dSChih-Kang Chang cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 20197a68ec3dSChih-Kang Chang if (!cfg) { 20207a68ec3dSChih-Kang Chang rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 20217a68ec3dSChih-Kang Chang return -EINVAL; 20227a68ec3dSChih-Kang Chang } 20237a68ec3dSChih-Kang Chang 20247a68ec3dSChih-Kang Chang min_cfg = cfg->ple_min_qt; 20257a68ec3dSChih-Kang Chang max_cfg = cfg->ple_max_qt; 20267a68ec3dSChih-Kang Chang SET_QUOTA(cma0_dma, PLE, 6); 20277a68ec3dSChih-Kang Chang SET_QUOTA(cma1_dma, PLE, 7); 20287a68ec3dSChih-Kang Chang 20297a68ec3dSChih-Kang Chang return 0; 20307a68ec3dSChih-Kang Chang } 2031e3ec7017SPing-Ke Shih #undef SET_QUOTA 2032e3ec7017SPing-Ke Shih 203319e28c7fSChin-Yen Lee void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 203419e28c7fSChin-Yen Lee { 203550961f88SKuan-Chung Chen const struct rtw89_chip_info *chip = rtwdev->chip; 203619e28c7fSChin-Yen Lee u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 203719e28c7fSChin-Yen Lee 2038d12d3df8SChin-Yen Lee if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2039d12d3df8SChin-Yen Lee return; 2040d12d3df8SChin-Yen Lee 204150961f88SKuan-Chung Chen /* 8852C enable B_AX_UC_MGNT_DEC by default */ 204250961f88SKuan-Chung Chen if (chip->chip_id == RTL8852C) 204350961f88SKuan-Chung Chen msk32 = B_AX_BMC_MGNT_DEC; 204450961f88SKuan-Chung Chen 204519e28c7fSChin-Yen Lee if (enable) 204619e28c7fSChin-Yen Lee rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 204719e28c7fSChin-Yen Lee else 204819e28c7fSChin-Yen Lee rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 204919e28c7fSChin-Yen Lee } 205019e28c7fSChin-Yen Lee 2051e3ec7017SPing-Ke Shih static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2052e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, 2053e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 2054e3ec7017SPing-Ke Shih { 205539e9b569SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 205639e9b569SPing-Ke Shih 205739e9b569SPing-Ke Shih mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 205839e9b569SPing-Ke Shih mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2059e3ec7017SPing-Ke Shih } 2060e3ec7017SPing-Ke Shih 2061fc663fa0SPing-Ke Shih int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2062e3ec7017SPing-Ke Shih enum rtw89_qta_mode ext_mode) 2063e3ec7017SPing-Ke Shih { 206439e9b569SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2065e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, *ext_cfg; 2066e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 206739e9b569SPing-Ke Shih int ret; 2068e3ec7017SPing-Ke Shih 2069e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2070e3ec7017SPing-Ke Shih if (ret) 2071e3ec7017SPing-Ke Shih return ret; 2072e3ec7017SPing-Ke Shih 2073e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 2074e3ec7017SPing-Ke Shih if (!cfg) { 2075e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2076e3ec7017SPing-Ke Shih ret = -EINVAL; 2077e3ec7017SPing-Ke Shih goto error; 2078e3ec7017SPing-Ke Shih } 2079e3ec7017SPing-Ke Shih 2080e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_DLFW) { 2081e3ec7017SPing-Ke Shih ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2082e3ec7017SPing-Ke Shih if (!ext_cfg) { 2083e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2084e3ec7017SPing-Ke Shih ext_mode); 2085e3ec7017SPing-Ke Shih ret = -EINVAL; 2086e3ec7017SPing-Ke Shih goto error; 2087e3ec7017SPing-Ke Shih } 2088e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2089e3ec7017SPing-Ke Shih } 2090e3ec7017SPing-Ke Shih 2091aabe741eSPing-Ke Shih if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2092e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2093e3ec7017SPing-Ke Shih ret = -EINVAL; 2094e3ec7017SPing-Ke Shih goto error; 2095e3ec7017SPing-Ke Shih } 2096e3ec7017SPing-Ke Shih 209739e9b569SPing-Ke Shih mac->dle_func_en(rtwdev, false); 209839e9b569SPing-Ke Shih mac->dle_clk_en(rtwdev, true); 2099e3ec7017SPing-Ke Shih 210039e9b569SPing-Ke Shih ret = mac->dle_mix_cfg(rtwdev, cfg); 2101e3ec7017SPing-Ke Shih if (ret) { 2102e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2103e3ec7017SPing-Ke Shih goto error; 2104e3ec7017SPing-Ke Shih } 2105e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2106e3ec7017SPing-Ke Shih 210739e9b569SPing-Ke Shih mac->dle_func_en(rtwdev, true); 2108e3ec7017SPing-Ke Shih 210939e9b569SPing-Ke Shih ret = mac->chk_dle_rdy(rtwdev, true); 2110e3ec7017SPing-Ke Shih if (ret) { 2111e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2112e3ec7017SPing-Ke Shih return ret; 2113e3ec7017SPing-Ke Shih } 2114e3ec7017SPing-Ke Shih 211539e9b569SPing-Ke Shih ret = mac->chk_dle_rdy(rtwdev, false); 2116e3ec7017SPing-Ke Shih if (ret) { 2117e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2118e3ec7017SPing-Ke Shih return ret; 2119e3ec7017SPing-Ke Shih } 2120e3ec7017SPing-Ke Shih 2121e3ec7017SPing-Ke Shih return 0; 2122e3ec7017SPing-Ke Shih error: 212339e9b569SPing-Ke Shih mac->dle_func_en(rtwdev, false); 2124e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2125e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2126e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2127e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2128e3ec7017SPing-Ke Shih 2129e3ec7017SPing-Ke Shih return ret; 2130e3ec7017SPing-Ke Shih } 2131e3ec7017SPing-Ke Shih 2132e07a9968SPing-Ke Shih static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2133e07a9968SPing-Ke Shih enum rtw89_qta_mode mode) 2134e07a9968SPing-Ke Shih { 2135e07a9968SPing-Ke Shih u32 reg, max_preld_size, min_rsvd_size; 2136e07a9968SPing-Ke Shih 2137e07a9968SPing-Ke Shih max_preld_size = (mac_idx == RTW89_MAC_0 ? 2138e07a9968SPing-Ke Shih PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2139e07a9968SPing-Ke Shih reg = mac_idx == RTW89_MAC_0 ? 2140e07a9968SPing-Ke Shih R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2141e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2142e07a9968SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2143e07a9968SPing-Ke Shih 2144e07a9968SPing-Ke Shih min_rsvd_size = PRELD_AMSDU_SIZE; 2145e07a9968SPing-Ke Shih reg = mac_idx == RTW89_MAC_0 ? 2146e07a9968SPing-Ke Shih R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2147e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2148e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2149e07a9968SPing-Ke Shih 2150e07a9968SPing-Ke Shih return 0; 2151e07a9968SPing-Ke Shih } 2152e07a9968SPing-Ke Shih 2153e07a9968SPing-Ke Shih static bool is_qta_poh(struct rtw89_dev *rtwdev) 2154e07a9968SPing-Ke Shih { 2155e07a9968SPing-Ke Shih return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2156e07a9968SPing-Ke Shih } 2157e07a9968SPing-Ke Shih 2158fc663fa0SPing-Ke Shih int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2159e07a9968SPing-Ke Shih enum rtw89_qta_mode mode) 2160e07a9968SPing-Ke Shih { 2161e07a9968SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2162e07a9968SPing-Ke Shih 2163190dc12dSPing-Ke Shih if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) || 2164190dc12dSPing-Ke Shih !is_qta_poh(rtwdev)) 2165e07a9968SPing-Ke Shih return 0; 2166e07a9968SPing-Ke Shih 2167e07a9968SPing-Ke Shih return preload_init_set(rtwdev, mac_idx, mode); 2168e07a9968SPing-Ke Shih } 2169e07a9968SPing-Ke Shih 2170e3ec7017SPing-Ke Shih static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2171e3ec7017SPing-Ke Shih { 2172e3ec7017SPing-Ke Shih u32 msk32; 2173e3ec7017SPing-Ke Shih u32 val32; 2174e3ec7017SPing-Ke Shih 2175e3ec7017SPing-Ke Shih msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2176e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2177e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2178e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2179e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2180e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2181e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2182e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2183e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2184e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2185e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2186e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2187e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2188e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2189e3ec7017SPing-Ke Shih 2190e3ec7017SPing-Ke Shih if ((val32 & msk32) == msk32) 2191e3ec7017SPing-Ke Shih return true; 2192e3ec7017SPing-Ke Shih 2193e3ec7017SPing-Ke Shih return false; 2194e3ec7017SPing-Ke Shih } 2195e3ec7017SPing-Ke Shih 2196cf7b8b80SPing-Ke Shih static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2197cf7b8b80SPing-Ke Shih { 2198cf7b8b80SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2199cf7b8b80SPing-Ke Shih 2200190dc12dSPing-Ke Shih if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2201cf7b8b80SPing-Ke Shih return; 2202cf7b8b80SPing-Ke Shih 2203cf7b8b80SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2204cf7b8b80SPing-Ke Shih SS2F_PATH_WLCPU); 2205cf7b8b80SPing-Ke Shih } 2206cf7b8b80SPing-Ke Shih 2207fc663fa0SPing-Ke Shih static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2208e3ec7017SPing-Ke Shih { 2209e3ec7017SPing-Ke Shih u32 p_val; 2210e3ec7017SPing-Ke Shih u8 val; 2211e3ec7017SPing-Ke Shih int ret; 2212e3ec7017SPing-Ke Shih 2213e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2214e3ec7017SPing-Ke Shih if (ret) 2215e3ec7017SPing-Ke Shih return ret; 2216e3ec7017SPing-Ke Shih 2217e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2218e3ec7017SPing-Ke Shih val |= B_AX_SS_EN; 2219e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2220e3ec7017SPing-Ke Shih 2221e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2222e3ec7017SPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2223e3ec7017SPing-Ke Shih if (ret) { 2224e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2225e3ec7017SPing-Ke Shih return ret; 2226e3ec7017SPing-Ke Shih } 2227e3ec7017SPing-Ke Shih 22289a1ab283SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 22299a1ab283SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2230cf7b8b80SPing-Ke Shih 2231cf7b8b80SPing-Ke Shih _patch_ss2f_path(rtwdev); 2232e3ec7017SPing-Ke Shih 2233e3ec7017SPing-Ke Shih return 0; 2234e3ec7017SPing-Ke Shih } 2235e3ec7017SPing-Ke Shih 2236fc663fa0SPing-Ke Shih static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2237e3ec7017SPing-Ke Shih { 2238e3ec7017SPing-Ke Shih int ret; 2239e3ec7017SPing-Ke Shih 2240e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2241e3ec7017SPing-Ke Shih if (ret) 2242e3ec7017SPing-Ke Shih return ret; 2243e3ec7017SPing-Ke Shih 2244e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2245e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2246e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2247e3ec7017SPing-Ke Shih B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2248e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2249e3ec7017SPing-Ke Shih 2250e3ec7017SPing-Ke Shih return 0; 2251e3ec7017SPing-Ke Shih } 2252e3ec7017SPing-Ke Shih 2253fc663fa0SPing-Ke Shih static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2254e3ec7017SPing-Ke Shih { 2255b61adeedSPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2256e3ec7017SPing-Ke Shih u32 val = 0; 2257e3ec7017SPing-Ke Shih int ret; 2258e3ec7017SPing-Ke Shih 2259e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2260e3ec7017SPing-Ke Shih if (ret) 2261e3ec7017SPing-Ke Shih return ret; 2262e3ec7017SPing-Ke Shih 2263e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2264e3ec7017SPing-Ke Shih /* init clock */ 2265e3ec7017SPing-Ke Shih val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2266e3ec7017SPing-Ke Shih /* init TX encryption */ 2267e3ec7017SPing-Ke Shih val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2268e3ec7017SPing-Ke Shih val |= (B_AX_MC_DEC | B_AX_BC_DEC); 226950961f88SKuan-Chung Chen if (chip->chip_id == RTL8852C) 227050961f88SKuan-Chung Chen val |= B_AX_UC_MGNT_DEC; 22715c3afcbaSPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 22725c3afcbaSPing-Ke Shih chip->chip_id == RTL8851B) 2273e3ec7017SPing-Ke Shih val &= ~B_AX_TX_PARTIAL_MODE; 2274e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2275e3ec7017SPing-Ke Shih 2276e3ec7017SPing-Ke Shih /* init MIC ICV append */ 2277e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2278e3ec7017SPing-Ke Shih val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2279e3ec7017SPing-Ke Shih 2280e3ec7017SPing-Ke Shih /* option init */ 2281e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2282e3ec7017SPing-Ke Shih 2283b61adeedSPing-Ke Shih if (chip->chip_id == RTL8852C) 2284b61adeedSPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2285b61adeedSPing-Ke Shih B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2286b61adeedSPing-Ke Shih 2287e3ec7017SPing-Ke Shih return 0; 2288e3ec7017SPing-Ke Shih } 2289e3ec7017SPing-Ke Shih 2290fc663fa0SPing-Ke Shih static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2291e3ec7017SPing-Ke Shih { 2292e3ec7017SPing-Ke Shih int ret; 2293e3ec7017SPing-Ke Shih 2294fc663fa0SPing-Ke Shih ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2295e3ec7017SPing-Ke Shih if (ret) { 2296e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2297e3ec7017SPing-Ke Shih return ret; 2298e3ec7017SPing-Ke Shih } 2299e3ec7017SPing-Ke Shih 2300fc663fa0SPing-Ke Shih ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2301e07a9968SPing-Ke Shih if (ret) { 2302e07a9968SPing-Ke Shih rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2303e07a9968SPing-Ke Shih return ret; 2304e07a9968SPing-Ke Shih } 2305e07a9968SPing-Ke Shih 2306fc663fa0SPing-Ke Shih ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2307e3ec7017SPing-Ke Shih if (ret) { 2308e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2309e3ec7017SPing-Ke Shih return ret; 2310e3ec7017SPing-Ke Shih } 2311e3ec7017SPing-Ke Shih 2312fc663fa0SPing-Ke Shih ret = sta_sch_init_ax(rtwdev); 2313e3ec7017SPing-Ke Shih if (ret) { 2314e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2315e3ec7017SPing-Ke Shih return ret; 2316e3ec7017SPing-Ke Shih } 2317e3ec7017SPing-Ke Shih 2318fc663fa0SPing-Ke Shih ret = mpdu_proc_init_ax(rtwdev); 2319e3ec7017SPing-Ke Shih if (ret) { 2320e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2321e3ec7017SPing-Ke Shih return ret; 2322e3ec7017SPing-Ke Shih } 2323e3ec7017SPing-Ke Shih 2324fc663fa0SPing-Ke Shih ret = sec_eng_init_ax(rtwdev); 2325e3ec7017SPing-Ke Shih if (ret) { 2326e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2327e3ec7017SPing-Ke Shih return ret; 2328e3ec7017SPing-Ke Shih } 2329e3ec7017SPing-Ke Shih 2330e3ec7017SPing-Ke Shih return ret; 2331e3ec7017SPing-Ke Shih } 2332e3ec7017SPing-Ke Shih 2333fc663fa0SPing-Ke Shih static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2334e3ec7017SPing-Ke Shih { 2335e3ec7017SPing-Ke Shih u32 val, reg; 2336e3ec7017SPing-Ke Shih u16 p_val; 2337e3ec7017SPing-Ke Shih int ret; 2338e3ec7017SPing-Ke Shih 2339e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2340e3ec7017SPing-Ke Shih if (ret) 2341e3ec7017SPing-Ke Shih return ret; 2342e3ec7017SPing-Ke Shih 2343c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2344e3ec7017SPing-Ke Shih 2345e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2346e3ec7017SPing-Ke Shih val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2347e3ec7017SPing-Ke Shih B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2348e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2349e3ec7017SPing-Ke Shih 2350e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2351ad275d0aSPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2352e3ec7017SPing-Ke Shih if (ret) { 2353e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2354e3ec7017SPing-Ke Shih return ret; 2355e3ec7017SPing-Ke Shih } 2356e3ec7017SPing-Ke Shih 2357e3ec7017SPing-Ke Shih return 0; 2358e3ec7017SPing-Ke Shih } 2359e3ec7017SPing-Ke Shih 2360fc663fa0SPing-Ke Shih static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2361e3ec7017SPing-Ke Shih { 2362e3ec7017SPing-Ke Shih u32 ret; 2363e3ec7017SPing-Ke Shih u32 reg; 236460b2ede9SChia-Yuan Li u32 val; 2365e3ec7017SPing-Ke Shih 2366e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2367e3ec7017SPing-Ke Shih if (ret) 2368e3ec7017SPing-Ke Shih return ret; 2369e3ec7017SPing-Ke Shih 2370c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2371ee546904SChia-Yuan Li if (rtwdev->chip->chip_id == RTL8852C) 2372ee546904SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2373ee546904SChia-Yuan Li SIFS_MACTXEN_T1_V1); 2374ee546904SChia-Yuan Li else 2375ee546904SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2376ee546904SChia-Yuan Li SIFS_MACTXEN_T1); 2377c49154ffSPing-Ke Shih 2378190dc12dSPing-Ke Shih if (rtw89_is_rtl885xb(rtwdev)) { 2379c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2380c49154ffSPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2381c49154ffSPing-Ke Shih } 2382c49154ffSPing-Ke Shih 2383c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2384c49154ffSPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2385c49154ffSPing-Ke Shih 2386c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 238760b2ede9SChia-Yuan Li if (rtwdev->chip->chip_id == RTL8852C) { 238860b2ede9SChia-Yuan Li val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 238960b2ede9SChia-Yuan Li B_AX_TX_PARTIAL_MODE); 239060b2ede9SChia-Yuan Li if (!val) 239160b2ede9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 239260b2ede9SChia-Yuan Li SCH_PREBKF_24US); 239360b2ede9SChia-Yuan Li } else { 239460b2ede9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 239560b2ede9SChia-Yuan Li SCH_PREBKF_24US); 239660b2ede9SChia-Yuan Li } 2397e3ec7017SPing-Ke Shih 2398e3ec7017SPing-Ke Shih return 0; 2399e3ec7017SPing-Ke Shih } 2400e3ec7017SPing-Ke Shih 2401fc663fa0SPing-Ke Shih static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2402e3ec7017SPing-Ke Shih enum rtw89_machdr_frame_type type, 2403e3ec7017SPing-Ke Shih enum rtw89_mac_fwd_target fwd_target, 2404e3ec7017SPing-Ke Shih u8 mac_idx) 2405e3ec7017SPing-Ke Shih { 2406e3ec7017SPing-Ke Shih u32 reg; 2407e3ec7017SPing-Ke Shih u32 val; 2408e3ec7017SPing-Ke Shih 2409e3ec7017SPing-Ke Shih switch (fwd_target) { 2410e3ec7017SPing-Ke Shih case RTW89_FWD_DONT_CARE: 2411e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_DROP; 2412e3ec7017SPing-Ke Shih break; 2413e3ec7017SPing-Ke Shih case RTW89_FWD_TO_HOST: 2414e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_HOST; 2415e3ec7017SPing-Ke Shih break; 2416e3ec7017SPing-Ke Shih case RTW89_FWD_TO_WLAN_CPU: 2417e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_WLCPU; 2418e3ec7017SPing-Ke Shih break; 2419e3ec7017SPing-Ke Shih default: 2420e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2421e3ec7017SPing-Ke Shih return -EINVAL; 2422e3ec7017SPing-Ke Shih } 2423e3ec7017SPing-Ke Shih 2424e3ec7017SPing-Ke Shih switch (type) { 2425e3ec7017SPing-Ke Shih case RTW89_MGNT: 2426c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2427e3ec7017SPing-Ke Shih break; 2428e3ec7017SPing-Ke Shih case RTW89_CTRL: 2429c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2430e3ec7017SPing-Ke Shih break; 2431e3ec7017SPing-Ke Shih case RTW89_DATA: 2432c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2433e3ec7017SPing-Ke Shih break; 2434e3ec7017SPing-Ke Shih default: 2435e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2436e3ec7017SPing-Ke Shih return -EINVAL; 2437e3ec7017SPing-Ke Shih } 2438e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2439e3ec7017SPing-Ke Shih 2440e3ec7017SPing-Ke Shih return 0; 2441e3ec7017SPing-Ke Shih } 2442e3ec7017SPing-Ke Shih 2443fc663fa0SPing-Ke Shih static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2444e3ec7017SPing-Ke Shih { 2445e3ec7017SPing-Ke Shih int ret, i; 2446e3ec7017SPing-Ke Shih u32 mac_ftlr, plcp_ftlr; 2447e3ec7017SPing-Ke Shih 2448e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2449e3ec7017SPing-Ke Shih if (ret) 2450e3ec7017SPing-Ke Shih return ret; 2451e3ec7017SPing-Ke Shih 2452e3ec7017SPing-Ke Shih for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2453fc663fa0SPing-Ke Shih ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2454e3ec7017SPing-Ke Shih mac_idx); 2455e3ec7017SPing-Ke Shih if (ret) 2456e3ec7017SPing-Ke Shih return ret; 2457e3ec7017SPing-Ke Shih } 2458e3ec7017SPing-Ke Shih mac_ftlr = rtwdev->hal.rx_fltr; 2459e3ec7017SPing-Ke Shih plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2460e3ec7017SPing-Ke Shih B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2461e3ec7017SPing-Ke Shih B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2462e3ec7017SPing-Ke Shih B_AX_HE_SIGB_CRC_CHK; 2463c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2464e3ec7017SPing-Ke Shih mac_ftlr); 2465c220d08eSPing-Ke Shih rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2466e3ec7017SPing-Ke Shih plcp_ftlr); 2467e3ec7017SPing-Ke Shih 2468e3ec7017SPing-Ke Shih return 0; 2469e3ec7017SPing-Ke Shih } 2470e3ec7017SPing-Ke Shih 2471e3ec7017SPing-Ke Shih static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2472e3ec7017SPing-Ke Shih { 2473e3ec7017SPing-Ke Shih u32 reg, val32; 2474e3ec7017SPing-Ke Shih u32 b_rsp_chk_nav, b_rsp_chk_cca; 2475e3ec7017SPing-Ke Shih 2476e3ec7017SPing-Ke Shih b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2477e3ec7017SPing-Ke Shih B_AX_RSP_CHK_BASIC_NAV; 2478e3ec7017SPing-Ke Shih b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2479e3ec7017SPing-Ke Shih B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2480e3ec7017SPing-Ke Shih B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2481e3ec7017SPing-Ke Shih 2482e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 2483e3ec7017SPing-Ke Shih case RTL8852A: 2484e3ec7017SPing-Ke Shih case RTL8852B: 2485c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2486e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2487e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2488e3ec7017SPing-Ke Shih 2489c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2490e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2491e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2492e3ec7017SPing-Ke Shih break; 2493e3ec7017SPing-Ke Shih default: 2494c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2495e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2496e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2497e3ec7017SPing-Ke Shih 2498c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2499e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2500e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2501e3ec7017SPing-Ke Shih break; 2502e3ec7017SPing-Ke Shih } 2503e3ec7017SPing-Ke Shih } 2504e3ec7017SPing-Ke Shih 2505fc663fa0SPing-Ke Shih static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2506e3ec7017SPing-Ke Shih { 2507e3ec7017SPing-Ke Shih u32 val, reg; 2508e3ec7017SPing-Ke Shih int ret; 2509e3ec7017SPing-Ke Shih 2510e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2511e3ec7017SPing-Ke Shih if (ret) 2512e3ec7017SPing-Ke Shih return ret; 2513e3ec7017SPing-Ke Shih 2514c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2515e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2516e3ec7017SPing-Ke Shih val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2517e3ec7017SPing-Ke Shih B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2518e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2519e3ec7017SPing-Ke Shih B_AX_CTN_CHK_INTRA_NAV | 2520e3ec7017SPing-Ke Shih B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2521e3ec7017SPing-Ke Shih B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2522e3ec7017SPing-Ke Shih B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 252398ed6159SPing-Ke Shih B_AX_CTN_CHK_CCA_P20); 2524e3ec7017SPing-Ke Shih val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2525e3ec7017SPing-Ke Shih B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2526e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 252798ed6159SPing-Ke Shih B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 252898ed6159SPing-Ke Shih B_AX_SIFS_CHK_EDCCA); 2529e3ec7017SPing-Ke Shih 2530e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2531e3ec7017SPing-Ke Shih 2532e3ec7017SPing-Ke Shih _patch_dis_resp_chk(rtwdev, mac_idx); 2533e3ec7017SPing-Ke Shih 2534e3ec7017SPing-Ke Shih return 0; 2535e3ec7017SPing-Ke Shih } 2536e3ec7017SPing-Ke Shih 2537fc663fa0SPing-Ke Shih static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 253819cb9427SPing-Ke Shih { 253919cb9427SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 254019cb9427SPing-Ke Shih B_AX_WMAC_TF_UP_NAV_EN | 254119cb9427SPing-Ke Shih B_AX_WMAC_NAV_UPPER_EN); 2542c060dc51SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 254319cb9427SPing-Ke Shih 254419cb9427SPing-Ke Shih return 0; 254519cb9427SPing-Ke Shih } 254619cb9427SPing-Ke Shih 2547fc663fa0SPing-Ke Shih static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2548e3ec7017SPing-Ke Shih { 2549e3ec7017SPing-Ke Shih u32 reg; 2550e3ec7017SPing-Ke Shih int ret; 2551e3ec7017SPing-Ke Shih 2552e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2553e3ec7017SPing-Ke Shih if (ret) 2554e3ec7017SPing-Ke Shih return ret; 2555c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2556e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2557e3ec7017SPing-Ke Shih 2558505b57d0SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2559505b57d0SPing-Ke Shih rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2560505b57d0SPing-Ke Shih 2561e3ec7017SPing-Ke Shih return 0; 2562e3ec7017SPing-Ke Shih } 2563e3ec7017SPing-Ke Shih 2564fc663fa0SPing-Ke Shih static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2565e3ec7017SPing-Ke Shih { 2566e3ec7017SPing-Ke Shih u32 reg; 2567e3ec7017SPing-Ke Shih int ret; 2568e3ec7017SPing-Ke Shih 2569e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2570e3ec7017SPing-Ke Shih if (ret) 2571e3ec7017SPing-Ke Shih return ret; 2572e3ec7017SPing-Ke Shih 2573c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2574e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2575e3ec7017SPing-Ke Shih 2576c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 257775fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 257875fd91aaSPing-Ke Shih 2579c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 258075fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 258175fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 258275fd91aaSPing-Ke Shih 2583e3ec7017SPing-Ke Shih return 0; 2584e3ec7017SPing-Ke Shih } 2585e3ec7017SPing-Ke Shih 2586fc663fa0SPing-Ke Shih static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2587e3ec7017SPing-Ke Shih { 25889ef9edb9SChia-Yuan Li const struct rtw89_chip_info *chip = rtwdev->chip; 25899ef9edb9SChia-Yuan Li const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2590e3ec7017SPing-Ke Shih u32 reg, val, sifs; 2591e3ec7017SPing-Ke Shih int ret; 2592e3ec7017SPing-Ke Shih 2593e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2594e3ec7017SPing-Ke Shih if (ret) 2595e3ec7017SPing-Ke Shih return ret; 2596e3ec7017SPing-Ke Shih 2597c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2598e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2599e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2600e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2601e3ec7017SPing-Ke Shih 2602e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 2603e3ec7017SPing-Ke Shih case RTL8852A: 2604e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52A; 2605e3ec7017SPing-Ke Shih break; 2606190dc12dSPing-Ke Shih case RTL8851B: 2607e3ec7017SPing-Ke Shih case RTL8852B: 2608190dc12dSPing-Ke Shih case RTL8852BT: 2609e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52B; 2610e3ec7017SPing-Ke Shih break; 2611e3ec7017SPing-Ke Shih default: 2612e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52C; 2613e3ec7017SPing-Ke Shih break; 2614e3ec7017SPing-Ke Shih } 2615e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2616e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2617e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2618e3ec7017SPing-Ke Shih 2619c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2620e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2621e3ec7017SPing-Ke Shih 2622c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 26239ef9edb9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2624c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 26259ef9edb9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 26269ef9edb9SChia-Yuan Li 2627e3ec7017SPing-Ke Shih return 0; 2628e3ec7017SPing-Ke Shih } 2629e3ec7017SPing-Ke Shih 263018175197SPing-Ke Shih static void rst_bacam(struct rtw89_dev *rtwdev) 263118175197SPing-Ke Shih { 263218175197SPing-Ke Shih u32 val32; 263318175197SPing-Ke Shih int ret; 263418175197SPing-Ke Shih 263518175197SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 263618175197SPing-Ke Shih S_AX_BACAM_RST_ALL); 263718175197SPing-Ke Shih 263818175197SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 263918175197SPing-Ke Shih 1, 1000, false, 264018175197SPing-Ke Shih rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 264118175197SPing-Ke Shih if (ret) 264218175197SPing-Ke Shih rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 264318175197SPing-Ke Shih } 264418175197SPing-Ke Shih 2645fc663fa0SPing-Ke Shih static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2646e3ec7017SPing-Ke Shih { 2647e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_CCA_TO 32 2648e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_DATA_TO 15 2649e3ec7017SPing-Ke Shih #define RX_MAX_LEN_UNIT 512 2650e3ec7017SPing-Ke Shih #define PLD_RLS_MAX_PG 127 26514b0d341bSPing-Ke Shih #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2652190dc12dSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2653e3ec7017SPing-Ke Shih int ret; 2654e3ec7017SPing-Ke Shih u32 reg, rx_max_len, rx_qta; 2655e3ec7017SPing-Ke Shih u16 val; 2656e3ec7017SPing-Ke Shih 2657e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2658e3ec7017SPing-Ke Shih if (ret) 2659e3ec7017SPing-Ke Shih return ret; 2660e3ec7017SPing-Ke Shih 266118175197SPing-Ke Shih if (mac_idx == RTW89_MAC_0) 266218175197SPing-Ke Shih rst_bacam(rtwdev); 266318175197SPing-Ke Shih 2664c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2665e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2666e3ec7017SPing-Ke Shih 2667c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2668e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 2669e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2670e3ec7017SPing-Ke Shih B_AX_RX_DLK_DATA_TIME_MASK); 2671e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2672e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK); 2673190dc12dSPing-Ke Shih if (chip_id == RTL8852BT) 2674190dc12dSPing-Ke Shih val |= B_AX_RX_DLK_RST_EN; 2675e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 2676e3ec7017SPing-Ke Shih 2677c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2678e3ec7017SPing-Ke Shih rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2679e3ec7017SPing-Ke Shih 2680c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2681e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_0) 2682e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2683e3ec7017SPing-Ke Shih else 2684e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 26854b0d341bSPing-Ke Shih rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 26864b0d341bSPing-Ke Shih rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 26874b0d341bSPing-Ke Shih rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 26884b0d341bSPing-Ke Shih rx_max_len /= RX_MAX_LEN_UNIT; 2689e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2690e3ec7017SPing-Ke Shih 2691190dc12dSPing-Ke Shih if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) { 2692e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, 2693c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2694e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK, 0); 2695c220d08eSPing-Ke Shih rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2696e3ec7017SPing-Ke Shih BIT(12)); 2697e3ec7017SPing-Ke Shih } 2698e3ec7017SPing-Ke Shih 2699c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2700e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2701e3ec7017SPing-Ke Shih 2702e3ec7017SPing-Ke Shih return ret; 2703e3ec7017SPing-Ke Shih } 2704e3ec7017SPing-Ke Shih 2705fc663fa0SPing-Ke Shih static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2706e3ec7017SPing-Ke Shih { 27079ef9edb9SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2708e3ec7017SPing-Ke Shih u32 val, reg; 2709e3ec7017SPing-Ke Shih int ret; 2710e3ec7017SPing-Ke Shih 2711e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2712e3ec7017SPing-Ke Shih if (ret) 2713e3ec7017SPing-Ke Shih return ret; 2714e3ec7017SPing-Ke Shih 2715c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2716e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2717e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2718e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2719e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2720e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2721e3ec7017SPing-Ke Shih 2722190dc12dSPing-Ke Shih if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2723c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 27249ef9edb9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 27259ef9edb9SChia-Yuan Li } 27269ef9edb9SChia-Yuan Li 2727e3ec7017SPing-Ke Shih return 0; 2728e3ec7017SPing-Ke Shih } 2729e3ec7017SPing-Ke Shih 2730fc663fa0SPing-Ke Shih bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2731e3ec7017SPing-Ke Shih { 2732e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 2733e3ec7017SPing-Ke Shih 2734e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 2735e3ec7017SPing-Ke Shih if (!cfg) { 2736e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2737e3ec7017SPing-Ke Shih return false; 2738e3ec7017SPing-Ke Shih } 2739e3ec7017SPing-Ke Shih 2740e3ec7017SPing-Ke Shih return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2741e3ec7017SPing-Ke Shih } 2742e3ec7017SPing-Ke Shih 2743fc663fa0SPing-Ke Shih static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2744e3ec7017SPing-Ke Shih { 274512441097SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2746e3ec7017SPing-Ke Shih u32 val, reg; 2747e3ec7017SPing-Ke Shih int ret; 2748e3ec7017SPing-Ke Shih 2749e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2750e3ec7017SPing-Ke Shih if (ret) 2751e3ec7017SPing-Ke Shih return ret; 2752e3ec7017SPing-Ke Shih 2753e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2754c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2755e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2756e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2757e3ec7017SPing-Ke Shih B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 27589fb4862eSPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 27599fb4862eSPing-Ke Shih B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2760e3ec7017SPing-Ke Shih val |= B_AX_HW_CTS2SELF_EN; 2761e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2762e3ec7017SPing-Ke Shih 2763c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2764e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2765e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2766e3ec7017SPing-Ke Shih val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2767e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2768e3ec7017SPing-Ke Shih } 2769e3ec7017SPing-Ke Shih 27709fb4862eSPing-Ke Shih if (mac_idx == RTW89_MAC_0) { 27719fb4862eSPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 27729fb4862eSPing-Ke Shih B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 27739fb4862eSPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 27749fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_0 | 27759fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_1 | 27769fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_UL); 27779fb4862eSPing-Ke Shih rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 27789fb4862eSPing-Ke Shih B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 27799fb4862eSPing-Ke Shih } else if (mac_idx == RTW89_MAC_1) { 27809fb4862eSPing-Ke Shih rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 27819fb4862eSPing-Ke Shih B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 27829fb4862eSPing-Ke Shih } 2783e3ec7017SPing-Ke Shih 278412441097SChia-Yuan Li if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 278512441097SChia-Yuan Li reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_VHT_0, mac_idx); 278612441097SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, 278712441097SChia-Yuan Li B_AX_AMPDU_MAX_LEN_VHT_MASK, 0x3FF80); 278812441097SChia-Yuan Li } 278912441097SChia-Yuan Li 2790e3ec7017SPing-Ke Shih return 0; 2791e3ec7017SPing-Ke Shih } 2792e3ec7017SPing-Ke Shih 2793fc663fa0SPing-Ke Shih static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2794a0d99ebbSPing-Ke Shih { 2795a0d99ebbSPing-Ke Shih u32 reg; 2796a0d99ebbSPing-Ke Shih int ret; 2797a0d99ebbSPing-Ke Shih 2798190dc12dSPing-Ke Shih if (!rtw89_is_rtl885xb(rtwdev)) 2799a0d99ebbSPing-Ke Shih return 0; 2800a0d99ebbSPing-Ke Shih 2801a0d99ebbSPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2802a0d99ebbSPing-Ke Shih if (ret) 2803a0d99ebbSPing-Ke Shih return ret; 2804a0d99ebbSPing-Ke Shih 2805c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2806a0d99ebbSPing-Ke Shih rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2807a0d99ebbSPing-Ke Shih 2808a0d99ebbSPing-Ke Shih return 0; 2809a0d99ebbSPing-Ke Shih } 2810a0d99ebbSPing-Ke Shih 2811fc663fa0SPing-Ke Shih static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2812e3ec7017SPing-Ke Shih { 2813e3ec7017SPing-Ke Shih int ret; 2814e3ec7017SPing-Ke Shih 2815fc663fa0SPing-Ke Shih ret = scheduler_init_ax(rtwdev, mac_idx); 2816e3ec7017SPing-Ke Shih if (ret) { 2817e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2818e3ec7017SPing-Ke Shih return ret; 2819e3ec7017SPing-Ke Shih } 2820e3ec7017SPing-Ke Shih 2821fc663fa0SPing-Ke Shih ret = addr_cam_init_ax(rtwdev, mac_idx); 2822e3ec7017SPing-Ke Shih if (ret) { 2823e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2824e3ec7017SPing-Ke Shih ret); 2825e3ec7017SPing-Ke Shih return ret; 2826e3ec7017SPing-Ke Shih } 2827e3ec7017SPing-Ke Shih 2828fc663fa0SPing-Ke Shih ret = rx_fltr_init_ax(rtwdev, mac_idx); 2829e3ec7017SPing-Ke Shih if (ret) { 2830e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2831e3ec7017SPing-Ke Shih ret); 2832e3ec7017SPing-Ke Shih return ret; 2833e3ec7017SPing-Ke Shih } 2834e3ec7017SPing-Ke Shih 2835fc663fa0SPing-Ke Shih ret = cca_ctrl_init_ax(rtwdev, mac_idx); 2836e3ec7017SPing-Ke Shih if (ret) { 2837e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2838e3ec7017SPing-Ke Shih ret); 2839e3ec7017SPing-Ke Shih return ret; 2840e3ec7017SPing-Ke Shih } 2841e3ec7017SPing-Ke Shih 2842fc663fa0SPing-Ke Shih ret = nav_ctrl_init_ax(rtwdev); 284319cb9427SPing-Ke Shih if (ret) { 284419cb9427SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 284519cb9427SPing-Ke Shih ret); 284619cb9427SPing-Ke Shih return ret; 284719cb9427SPing-Ke Shih } 284819cb9427SPing-Ke Shih 2849fc663fa0SPing-Ke Shih ret = spatial_reuse_init_ax(rtwdev, mac_idx); 2850e3ec7017SPing-Ke Shih if (ret) { 2851e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2852e3ec7017SPing-Ke Shih mac_idx, ret); 2853e3ec7017SPing-Ke Shih return ret; 2854e3ec7017SPing-Ke Shih } 2855e3ec7017SPing-Ke Shih 2856fc663fa0SPing-Ke Shih ret = tmac_init_ax(rtwdev, mac_idx); 2857e3ec7017SPing-Ke Shih if (ret) { 2858e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2859e3ec7017SPing-Ke Shih return ret; 2860e3ec7017SPing-Ke Shih } 2861e3ec7017SPing-Ke Shih 2862fc663fa0SPing-Ke Shih ret = trxptcl_init_ax(rtwdev, mac_idx); 2863e3ec7017SPing-Ke Shih if (ret) { 2864e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2865e3ec7017SPing-Ke Shih return ret; 2866e3ec7017SPing-Ke Shih } 2867e3ec7017SPing-Ke Shih 2868fc663fa0SPing-Ke Shih ret = rmac_init_ax(rtwdev, mac_idx); 2869e3ec7017SPing-Ke Shih if (ret) { 2870e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2871e3ec7017SPing-Ke Shih return ret; 2872e3ec7017SPing-Ke Shih } 2873e3ec7017SPing-Ke Shih 2874fc663fa0SPing-Ke Shih ret = cmac_com_init_ax(rtwdev, mac_idx); 2875e3ec7017SPing-Ke Shih if (ret) { 2876e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2877e3ec7017SPing-Ke Shih return ret; 2878e3ec7017SPing-Ke Shih } 2879e3ec7017SPing-Ke Shih 2880fc663fa0SPing-Ke Shih ret = ptcl_init_ax(rtwdev, mac_idx); 2881e3ec7017SPing-Ke Shih if (ret) { 2882e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2883e3ec7017SPing-Ke Shih return ret; 2884e3ec7017SPing-Ke Shih } 2885e3ec7017SPing-Ke Shih 2886fc663fa0SPing-Ke Shih ret = cmac_dma_init_ax(rtwdev, mac_idx); 2887a0d99ebbSPing-Ke Shih if (ret) { 2888a0d99ebbSPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2889a0d99ebbSPing-Ke Shih return ret; 2890a0d99ebbSPing-Ke Shih } 2891a0d99ebbSPing-Ke Shih 2892e3ec7017SPing-Ke Shih return ret; 2893e3ec7017SPing-Ke Shih } 2894e3ec7017SPing-Ke Shih 2895e3ec7017SPing-Ke Shih static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2896e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info *c2h_info) 2897e3ec7017SPing-Ke Shih { 289888e6a923SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2899e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 2900e3ec7017SPing-Ke Shih u32 ret; 2901e3ec7017SPing-Ke Shih 290288e6a923SPing-Ke Shih mac->cnv_efuse_state(rtwdev, false); 290388e6a923SPing-Ke Shih 2904e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2905e3ec7017SPing-Ke Shih h2c_info.content_len = 0; 2906e3ec7017SPing-Ke Shih 2907e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2908e3ec7017SPing-Ke Shih if (ret) 290988e6a923SPing-Ke Shih goto out; 2910e3ec7017SPing-Ke Shih 2911e3ec7017SPing-Ke Shih if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 291288e6a923SPing-Ke Shih ret = -EINVAL; 2913e3ec7017SPing-Ke Shih 291488e6a923SPing-Ke Shih out: 291588e6a923SPing-Ke Shih mac->cnv_efuse_state(rtwdev, true); 291688e6a923SPing-Ke Shih 291788e6a923SPing-Ke Shih return ret; 2918e3ec7017SPing-Ke Shih } 2919e3ec7017SPing-Ke Shih 2920e3ec7017SPing-Ke Shih int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2921e3ec7017SPing-Ke Shih { 2922f48453e0SPing-Ke Shih struct rtw89_efuse *efuse = &rtwdev->efuse; 2923e3ec7017SPing-Ke Shih struct rtw89_hal *hal = &rtwdev->hal; 2924e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2925e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 292668012b44SPing-Ke Shih const struct rtw89_c2hreg_phycap *phycap; 2927c7ad08c6SPing-Ke Shih u8 tx_nss; 2928c7ad08c6SPing-Ke Shih u8 rx_nss; 2929dc229d94SPing-Ke Shih u8 tx_ant; 2930dc229d94SPing-Ke Shih u8 rx_ant; 2931e3ec7017SPing-Ke Shih u32 ret; 2932e3ec7017SPing-Ke Shih 2933e3ec7017SPing-Ke Shih ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2934e3ec7017SPing-Ke Shih if (ret) 2935e3ec7017SPing-Ke Shih return ret; 2936e3ec7017SPing-Ke Shih 293768012b44SPing-Ke Shih phycap = &c2h_info.u.phycap; 293868012b44SPing-Ke Shih 293968012b44SPing-Ke Shih tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 294068012b44SPing-Ke Shih rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 294168012b44SPing-Ke Shih tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 294268012b44SPing-Ke Shih rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2943c7ad08c6SPing-Ke Shih 2944c7ad08c6SPing-Ke Shih hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2945c7ad08c6SPing-Ke Shih hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2946e3ec7017SPing-Ke Shih 2947dc229d94SPing-Ke Shih if (tx_ant == 1) 2948dc229d94SPing-Ke Shih hal->antenna_tx = RF_B; 2949dc229d94SPing-Ke Shih if (rx_ant == 1) 2950dc229d94SPing-Ke Shih hal->antenna_rx = RF_B; 2951dc229d94SPing-Ke Shih 2952dc229d94SPing-Ke Shih if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2953dc229d94SPing-Ke Shih hal->antenna_tx = RF_B; 2954dc229d94SPing-Ke Shih hal->tx_path_diversity = true; 2955dc229d94SPing-Ke Shih } 2956dc229d94SPing-Ke Shih 2957f48453e0SPing-Ke Shih if (chip->rf_path_num == 1) { 2958f48453e0SPing-Ke Shih hal->antenna_tx = RF_A; 2959f48453e0SPing-Ke Shih hal->antenna_rx = RF_A; 2960f48453e0SPing-Ke Shih if ((efuse->rfe_type % 3) == 2) 2961f48453e0SPing-Ke Shih hal->ant_diversity = true; 2962f48453e0SPing-Ke Shih } 2963f48453e0SPing-Ke Shih 2964e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 2965e3ec7017SPing-Ke Shih "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2966c7ad08c6SPing-Ke Shih hal->tx_nss, tx_nss, chip->tx_nss, 2967c7ad08c6SPing-Ke Shih hal->rx_nss, rx_nss, chip->rx_nss); 2968dc229d94SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 2969dc229d94SPing-Ke Shih "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2970dc229d94SPing-Ke Shih tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2971dc229d94SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2972f48453e0SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2973e3ec7017SPing-Ke Shih 2974e3ec7017SPing-Ke Shih return 0; 2975e3ec7017SPing-Ke Shih } 2976e3ec7017SPing-Ke Shih 2977e3ec7017SPing-Ke Shih static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2978e3ec7017SPing-Ke Shih u16 tx_en_u16, u16 mask_u16) 2979e3ec7017SPing-Ke Shih { 2980e3ec7017SPing-Ke Shih u32 ret; 2981e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 2982e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 298368012b44SPing-Ke Shih struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 2984e3ec7017SPing-Ke Shih 2985e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 298668012b44SPing-Ke Shih h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 298768012b44SPing-Ke Shih 298868012b44SPing-Ke Shih u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 298968012b44SPing-Ke Shih u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 299068012b44SPing-Ke Shih u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 2991e3ec7017SPing-Ke Shih 2992e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2993e3ec7017SPing-Ke Shih if (ret) 2994e3ec7017SPing-Ke Shih return ret; 2995e3ec7017SPing-Ke Shih 2996e3ec7017SPing-Ke Shih if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2997e3ec7017SPing-Ke Shih return -EINVAL; 2998e3ec7017SPing-Ke Shih 2999e3ec7017SPing-Ke Shih return 0; 3000e3ec7017SPing-Ke Shih } 3001e3ec7017SPing-Ke Shih 3002e3ec7017SPing-Ke Shih static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 3003e3ec7017SPing-Ke Shih u16 tx_en, u16 tx_en_mask) 3004e3ec7017SPing-Ke Shih { 3005c220d08eSPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 3006e3ec7017SPing-Ke Shih u16 val; 3007e3ec7017SPing-Ke Shih int ret; 3008e3ec7017SPing-Ke Shih 3009e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3010e3ec7017SPing-Ke Shih if (ret) 3011e3ec7017SPing-Ke Shih return ret; 3012e3ec7017SPing-Ke Shih 3013e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3014e3ec7017SPing-Ke Shih return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 3015e3ec7017SPing-Ke Shih tx_en, tx_en_mask); 3016e3ec7017SPing-Ke Shih 3017e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 3018e3ec7017SPing-Ke Shih val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3019e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 3020e3ec7017SPing-Ke Shih 3021e3ec7017SPing-Ke Shih return 0; 3022e3ec7017SPing-Ke Shih } 3023e3ec7017SPing-Ke Shih 3024de7ba639SPing-Ke Shih static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3025de7ba639SPing-Ke Shih u32 tx_en, u32 tx_en_mask) 3026de7ba639SPing-Ke Shih { 3027c220d08eSPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3028de7ba639SPing-Ke Shih u32 val; 3029de7ba639SPing-Ke Shih int ret; 3030de7ba639SPing-Ke Shih 3031de7ba639SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3032de7ba639SPing-Ke Shih if (ret) 3033de7ba639SPing-Ke Shih return ret; 3034de7ba639SPing-Ke Shih 3035de7ba639SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 3036de7ba639SPing-Ke Shih val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3037de7ba639SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 3038de7ba639SPing-Ke Shih 3039de7ba639SPing-Ke Shih return 0; 3040de7ba639SPing-Ke Shih } 3041de7ba639SPing-Ke Shih 3042e3ec7017SPing-Ke Shih int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3043d780f926SPing-Ke Shih u32 *tx_en, enum rtw89_sch_tx_sel sel) 3044e3ec7017SPing-Ke Shih { 3045e3ec7017SPing-Ke Shih int ret; 3046e3ec7017SPing-Ke Shih 3047e3ec7017SPing-Ke Shih *tx_en = rtw89_read16(rtwdev, 3048c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3049e3ec7017SPing-Ke Shih 3050e3ec7017SPing-Ke Shih switch (sel) { 3051e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_ALL: 3052de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3053de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK); 3054e3ec7017SPing-Ke Shih if (ret) 3055e3ec7017SPing-Ke Shih return ret; 3056e3ec7017SPing-Ke Shih break; 3057e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_HIQ: 3058e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3059e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_HGQ); 3060e3ec7017SPing-Ke Shih if (ret) 3061e3ec7017SPing-Ke Shih return ret; 3062e3ec7017SPing-Ke Shih break; 3063e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MG0: 3064e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3065e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_MGQ); 3066e3ec7017SPing-Ke Shih if (ret) 3067e3ec7017SPing-Ke Shih return ret; 3068e3ec7017SPing-Ke Shih break; 3069e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MACID: 3070de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3071de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK); 3072e3ec7017SPing-Ke Shih if (ret) 3073e3ec7017SPing-Ke Shih return ret; 3074e3ec7017SPing-Ke Shih break; 3075e3ec7017SPing-Ke Shih default: 3076e3ec7017SPing-Ke Shih return 0; 3077e3ec7017SPing-Ke Shih } 3078e3ec7017SPing-Ke Shih 3079e3ec7017SPing-Ke Shih return 0; 3080e3ec7017SPing-Ke Shih } 3081861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3082e3ec7017SPing-Ke Shih 3083de7ba639SPing-Ke Shih int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3084de7ba639SPing-Ke Shih u32 *tx_en, enum rtw89_sch_tx_sel sel) 3085de7ba639SPing-Ke Shih { 3086de7ba639SPing-Ke Shih int ret; 3087de7ba639SPing-Ke Shih 3088de7ba639SPing-Ke Shih *tx_en = rtw89_read32(rtwdev, 3089c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3090de7ba639SPing-Ke Shih 3091de7ba639SPing-Ke Shih switch (sel) { 3092de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_ALL: 3093de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3094de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 3095de7ba639SPing-Ke Shih if (ret) 3096de7ba639SPing-Ke Shih return ret; 3097de7ba639SPing-Ke Shih break; 3098de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_HIQ: 3099de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3100de7ba639SPing-Ke Shih 0, B_AX_CTN_TXEN_HGQ); 3101de7ba639SPing-Ke Shih if (ret) 3102de7ba639SPing-Ke Shih return ret; 3103de7ba639SPing-Ke Shih break; 3104de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_MG0: 3105de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3106de7ba639SPing-Ke Shih 0, B_AX_CTN_TXEN_MGQ); 3107de7ba639SPing-Ke Shih if (ret) 3108de7ba639SPing-Ke Shih return ret; 3109de7ba639SPing-Ke Shih break; 3110de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_MACID: 3111de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3112de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 3113de7ba639SPing-Ke Shih if (ret) 3114de7ba639SPing-Ke Shih return ret; 3115de7ba639SPing-Ke Shih break; 3116de7ba639SPing-Ke Shih default: 3117de7ba639SPing-Ke Shih return 0; 3118de7ba639SPing-Ke Shih } 3119de7ba639SPing-Ke Shih 3120de7ba639SPing-Ke Shih return 0; 3121de7ba639SPing-Ke Shih } 3122de7ba639SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3123de7ba639SPing-Ke Shih 3124d780f926SPing-Ke Shih int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3125e3ec7017SPing-Ke Shih { 3126e3ec7017SPing-Ke Shih int ret; 3127e3ec7017SPing-Ke Shih 3128de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3129e3ec7017SPing-Ke Shih if (ret) 3130e3ec7017SPing-Ke Shih return ret; 3131e3ec7017SPing-Ke Shih 3132e3ec7017SPing-Ke Shih return 0; 3133e3ec7017SPing-Ke Shih } 3134861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3135e3ec7017SPing-Ke Shih 3136de7ba639SPing-Ke Shih int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3137de7ba639SPing-Ke Shih { 3138de7ba639SPing-Ke Shih int ret; 3139de7ba639SPing-Ke Shih 3140de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3141de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 3142de7ba639SPing-Ke Shih if (ret) 3143de7ba639SPing-Ke Shih return ret; 3144de7ba639SPing-Ke Shih 3145de7ba639SPing-Ke Shih return 0; 3146de7ba639SPing-Ke Shih } 3147de7ba639SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3148de7ba639SPing-Ke Shih 314939e9b569SPing-Ke Shih static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3150e3ec7017SPing-Ke Shih { 3151e3ec7017SPing-Ke Shih u32 val, reg; 3152e3ec7017SPing-Ke Shih int ret; 3153e3ec7017SPing-Ke Shih 3154e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3155e3ec7017SPing-Ke Shih val = buf_len; 3156e3ec7017SPing-Ke Shih val |= B_AX_WD_BUF_REQ_EXEC; 3157e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 3158e3ec7017SPing-Ke Shih 3159e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3160e3ec7017SPing-Ke Shih 3161e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3162e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 3163e3ec7017SPing-Ke Shih if (ret) 3164eaddda24SPing-Ke Shih return ret; 3165e3ec7017SPing-Ke Shih 3166eaddda24SPing-Ke Shih *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3167eaddda24SPing-Ke Shih if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3168eaddda24SPing-Ke Shih return -ENOENT; 3169eaddda24SPing-Ke Shih 3170eaddda24SPing-Ke Shih return 0; 3171e3ec7017SPing-Ke Shih } 3172e3ec7017SPing-Ke Shih 317339e9b569SPing-Ke Shih static int set_cpuio_ax(struct rtw89_dev *rtwdev, 31748a1f6c88SZong-Zhe Yang struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3175e3ec7017SPing-Ke Shih { 3176e3ec7017SPing-Ke Shih u32 val, cmd_type, reg; 3177e3ec7017SPing-Ke Shih int ret; 3178e3ec7017SPing-Ke Shih 3179e3ec7017SPing-Ke Shih cmd_type = ctrl_para->cmd_type; 3180e3ec7017SPing-Ke Shih 3181e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3182e3ec7017SPing-Ke Shih val = 0; 3183e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->start_pktid, 3184e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3185e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->end_pktid, 3186e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3187e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 3188e3ec7017SPing-Ke Shih 3189e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3190e3ec7017SPing-Ke Shih val = 0; 3191e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_pid, 3192e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_PID_MASK); 3193e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_qid, 3194e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_QID_MASK); 3195e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_pid, 3196e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_PID_MASK); 3197e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_qid, 3198e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_QID_MASK); 3199e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 3200e3ec7017SPing-Ke Shih 3201e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3202e3ec7017SPing-Ke Shih val = 0; 3203e3ec7017SPing-Ke Shih val = u32_replace_bits(val, cmd_type, 3204e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_CMD_TYPE_MASK); 3205e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->macid, 3206e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_MACID_MASK); 3207e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->pkt_num, 3208e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_PKTNUM_MASK); 3209e3ec7017SPing-Ke Shih val |= B_AX_WD_CPUQ_OP_EXEC; 3210e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 3211e3ec7017SPing-Ke Shih 3212e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3213e3ec7017SPing-Ke Shih 3214e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3215e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 3216e3ec7017SPing-Ke Shih if (ret) 3217e3ec7017SPing-Ke Shih return ret; 3218e3ec7017SPing-Ke Shih 3219e3ec7017SPing-Ke Shih if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3220e3ec7017SPing-Ke Shih cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3221e3ec7017SPing-Ke Shih ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3222e3ec7017SPing-Ke Shih 3223e3ec7017SPing-Ke Shih return 0; 3224e3ec7017SPing-Ke Shih } 3225e3ec7017SPing-Ke Shih 3226b6e65d18SPing-Ke Shih int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3227b6e65d18SPing-Ke Shih bool band1_en) 3228e3ec7017SPing-Ke Shih { 322939e9b569SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3230e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 3231e3ec7017SPing-Ke Shih 3232e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 3233e3ec7017SPing-Ke Shih if (!cfg) { 3234e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3235e3ec7017SPing-Ke Shih return -EINVAL; 3236e3ec7017SPing-Ke Shih } 3237e3ec7017SPing-Ke Shih 3238aabe741eSPing-Ke Shih if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3239e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3240e3ec7017SPing-Ke Shih return -EINVAL; 3241e3ec7017SPing-Ke Shih } 3242e3ec7017SPing-Ke Shih 3243e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3244e3ec7017SPing-Ke Shih 3245b6e65d18SPing-Ke Shih return mac->dle_quota_change(rtwdev, band1_en); 3246b6e65d18SPing-Ke Shih } 3247b6e65d18SPing-Ke Shih 3248b6e65d18SPing-Ke Shih static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3249b6e65d18SPing-Ke Shih { 3250b6e65d18SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3251b6e65d18SPing-Ke Shih struct rtw89_cpuio_ctrl ctrl_para = {0}; 3252b6e65d18SPing-Ke Shih u16 pkt_id; 3253b6e65d18SPing-Ke Shih int ret; 3254b6e65d18SPing-Ke Shih 325539e9b569SPing-Ke Shih ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3256eaddda24SPing-Ke Shih if (ret) { 3257e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3258eaddda24SPing-Ke Shih return ret; 3259e3ec7017SPing-Ke Shih } 3260e3ec7017SPing-Ke Shih 3261e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3262e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 3263e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 3264e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 3265e3ec7017SPing-Ke Shih ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3266e3ec7017SPing-Ke Shih ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 326739e9b569SPing-Ke Shih ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3268e3ec7017SPing-Ke Shih if (ret) { 3269e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3270e3ec7017SPing-Ke Shih return -EFAULT; 3271e3ec7017SPing-Ke Shih } 3272e3ec7017SPing-Ke Shih 327339e9b569SPing-Ke Shih ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3274eaddda24SPing-Ke Shih if (ret) { 3275e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3276eaddda24SPing-Ke Shih return ret; 3277e3ec7017SPing-Ke Shih } 3278e3ec7017SPing-Ke Shih 3279e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3280e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 3281e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 3282e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 3283e3ec7017SPing-Ke Shih ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3284e3ec7017SPing-Ke Shih ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 328539e9b569SPing-Ke Shih ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3286e3ec7017SPing-Ke Shih if (ret) { 3287e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3288e3ec7017SPing-Ke Shih return -EFAULT; 3289e3ec7017SPing-Ke Shih } 3290e3ec7017SPing-Ke Shih 3291e3ec7017SPing-Ke Shih return 0; 3292e3ec7017SPing-Ke Shih } 3293e3ec7017SPing-Ke Shih 3294e3ec7017SPing-Ke Shih static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3295e3ec7017SPing-Ke Shih { 3296e3ec7017SPing-Ke Shih int ret; 3297e3ec7017SPing-Ke Shih u32 reg; 3298e3ec7017SPing-Ke Shih u8 val; 3299e3ec7017SPing-Ke Shih 3300e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3301e3ec7017SPing-Ke Shih if (ret) 3302e3ec7017SPing-Ke Shih return ret; 3303e3ec7017SPing-Ke Shih 3304c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3305e3ec7017SPing-Ke Shih 3306e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, 3307e3ec7017SPing-Ke Shih (val & B_AX_PTCL_TX_ON_STAT) == 0, 3308e3ec7017SPing-Ke Shih SW_CVR_DUR_US, 3309e3ec7017SPing-Ke Shih SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3310e3ec7017SPing-Ke Shih false, rtwdev, reg); 3311e3ec7017SPing-Ke Shih if (ret) 3312e3ec7017SPing-Ke Shih return ret; 3313e3ec7017SPing-Ke Shih 3314e3ec7017SPing-Ke Shih return 0; 3315e3ec7017SPing-Ke Shih } 3316e3ec7017SPing-Ke Shih 3317fc663fa0SPing-Ke Shih static int band1_enable_ax(struct rtw89_dev *rtwdev) 3318e3ec7017SPing-Ke Shih { 3319e3ec7017SPing-Ke Shih int ret, i; 3320e3ec7017SPing-Ke Shih u32 sleep_bak[4] = {0}; 3321e3ec7017SPing-Ke Shih u32 pause_bak[4] = {0}; 3322d780f926SPing-Ke Shih u32 tx_en; 3323e3ec7017SPing-Ke Shih 3324de7ba639SPing-Ke Shih ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3325e3ec7017SPing-Ke Shih if (ret) { 3326e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3327e3ec7017SPing-Ke Shih return ret; 3328e3ec7017SPing-Ke Shih } 3329e3ec7017SPing-Ke Shih 3330e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 3331e3ec7017SPing-Ke Shih sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3332e3ec7017SPing-Ke Shih pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3333e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3334e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3335e3ec7017SPing-Ke Shih } 3336e3ec7017SPing-Ke Shih 3337e3ec7017SPing-Ke Shih ret = band_idle_ck_b(rtwdev, 0); 3338e3ec7017SPing-Ke Shih if (ret) { 3339e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3340e3ec7017SPing-Ke Shih return ret; 3341e3ec7017SPing-Ke Shih } 3342e3ec7017SPing-Ke Shih 3343b6e65d18SPing-Ke Shih ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3344e3ec7017SPing-Ke Shih if (ret) { 3345e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3346e3ec7017SPing-Ke Shih return ret; 3347e3ec7017SPing-Ke Shih } 3348e3ec7017SPing-Ke Shih 3349e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 3350e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3351e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3352e3ec7017SPing-Ke Shih } 3353e3ec7017SPing-Ke Shih 3354de7ba639SPing-Ke Shih ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3355e3ec7017SPing-Ke Shih if (ret) { 3356e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3357e3ec7017SPing-Ke Shih return ret; 3358e3ec7017SPing-Ke Shih } 3359e3ec7017SPing-Ke Shih 3360fc663fa0SPing-Ke Shih ret = cmac_func_en_ax(rtwdev, 1, true); 3361e3ec7017SPing-Ke Shih if (ret) { 3362e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3363e3ec7017SPing-Ke Shih return ret; 3364e3ec7017SPing-Ke Shih } 3365e3ec7017SPing-Ke Shih 3366fc663fa0SPing-Ke Shih ret = cmac_init_ax(rtwdev, 1); 3367e3ec7017SPing-Ke Shih if (ret) { 3368e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3369e3ec7017SPing-Ke Shih return ret; 3370e3ec7017SPing-Ke Shih } 3371e3ec7017SPing-Ke Shih 3372e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3373e3ec7017SPing-Ke Shih B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3374e3ec7017SPing-Ke Shih 3375e3ec7017SPing-Ke Shih return 0; 3376e3ec7017SPing-Ke Shih } 3377e3ec7017SPing-Ke Shih 3378eeadcd2aSChia-Yuan Li static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3379eeadcd2aSChia-Yuan Li { 3380eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3381eeadcd2aSChia-Yuan Li 3382eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3383eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3384eeadcd2aSChia-Yuan Li } 3385eeadcd2aSChia-Yuan Li 3386eeadcd2aSChia-Yuan Li static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3387eeadcd2aSChia-Yuan Li { 3388eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3389eeadcd2aSChia-Yuan Li 3390eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3391eeadcd2aSChia-Yuan Li } 3392eeadcd2aSChia-Yuan Li 3393eeadcd2aSChia-Yuan Li static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3394eeadcd2aSChia-Yuan Li { 3395eeadcd2aSChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3396eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3397eeadcd2aSChia-Yuan Li 3398eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3399eeadcd2aSChia-Yuan Li B_AX_TX_GET_ERRPKTID_INT_EN | 3400eeadcd2aSChia-Yuan Li B_AX_TX_NXT_ERRPKTID_INT_EN | 3401eeadcd2aSChia-Yuan Li B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3402eeadcd2aSChia-Yuan Li B_AX_TX_OFFSET_ERR_INT_EN | 3403eeadcd2aSChia-Yuan Li B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3404eeadcd2aSChia-Yuan Li if (chip_id == RTL8852C) 3405eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3406eeadcd2aSChia-Yuan Li B_AX_TX_ETH_TYPE_ERR_EN | 3407eeadcd2aSChia-Yuan Li B_AX_TX_LLC_PRE_ERR_EN | 3408eeadcd2aSChia-Yuan Li B_AX_TX_NW_TYPE_ERR_EN | 3409eeadcd2aSChia-Yuan Li B_AX_TX_KSRCH_ERR_EN); 3410eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3411eeadcd2aSChia-Yuan Li imr->mpdu_tx_imr_set); 3412eeadcd2aSChia-Yuan Li 3413eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3414eeadcd2aSChia-Yuan Li B_AX_GETPKTID_ERR_INT_EN | 3415eeadcd2aSChia-Yuan Li B_AX_MHDRLEN_ERR_INT_EN | 3416eeadcd2aSChia-Yuan Li B_AX_RPT_ERR_INT_EN); 3417eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3418eeadcd2aSChia-Yuan Li imr->mpdu_rx_imr_set); 3419eeadcd2aSChia-Yuan Li } 3420eeadcd2aSChia-Yuan Li 3421eeadcd2aSChia-Yuan Li static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3422eeadcd2aSChia-Yuan Li { 3423eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3424eeadcd2aSChia-Yuan Li 3425eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3426eeadcd2aSChia-Yuan Li B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3427eeadcd2aSChia-Yuan Li B_AX_RPT_HANG_TIMEOUT_INT_EN | 3428eeadcd2aSChia-Yuan Li B_AX_PLE_B_PKTID_ERR_INT_EN); 3429eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3430eeadcd2aSChia-Yuan Li imr->sta_sch_imr_set); 3431eeadcd2aSChia-Yuan Li } 3432eeadcd2aSChia-Yuan Li 3433eeadcd2aSChia-Yuan Li static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3434eeadcd2aSChia-Yuan Li { 3435eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3436eeadcd2aSChia-Yuan Li 3437eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3438eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b0_clr); 3439eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3440eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b0_set); 3441eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3442eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b1_clr); 3443eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3444eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b1_set); 3445eeadcd2aSChia-Yuan Li } 3446eeadcd2aSChia-Yuan Li 3447eeadcd2aSChia-Yuan Li static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3448eeadcd2aSChia-Yuan Li { 3449eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3450eeadcd2aSChia-Yuan Li 3451eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3452eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3453eeadcd2aSChia-Yuan Li } 3454eeadcd2aSChia-Yuan Li 3455eeadcd2aSChia-Yuan Li static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3456eeadcd2aSChia-Yuan Li { 3457eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3458eeadcd2aSChia-Yuan Li 3459eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3460eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3461eeadcd2aSChia-Yuan Li } 3462eeadcd2aSChia-Yuan Li 3463eeadcd2aSChia-Yuan Li static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3464eeadcd2aSChia-Yuan Li { 3465eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3466eeadcd2aSChia-Yuan Li B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3467eeadcd2aSChia-Yuan Li } 3468eeadcd2aSChia-Yuan Li 3469eeadcd2aSChia-Yuan Li static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3470eeadcd2aSChia-Yuan Li { 3471eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3472eeadcd2aSChia-Yuan Li 3473eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3474eeadcd2aSChia-Yuan Li imr->host_disp_imr_clr); 3475eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3476eeadcd2aSChia-Yuan Li imr->host_disp_imr_set); 3477eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3478eeadcd2aSChia-Yuan Li imr->cpu_disp_imr_clr); 3479eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3480eeadcd2aSChia-Yuan Li imr->cpu_disp_imr_set); 3481eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3482eeadcd2aSChia-Yuan Li imr->other_disp_imr_clr); 3483eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3484eeadcd2aSChia-Yuan Li imr->other_disp_imr_set); 3485eeadcd2aSChia-Yuan Li } 3486eeadcd2aSChia-Yuan Li 3487eeadcd2aSChia-Yuan Li static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3488eeadcd2aSChia-Yuan Li { 3489eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3490eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3491eeadcd2aSChia-Yuan Li } 3492eeadcd2aSChia-Yuan Li 3493eeadcd2aSChia-Yuan Li static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3494eeadcd2aSChia-Yuan Li { 3495eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3496eeadcd2aSChia-Yuan Li 349775f1ed29SPing-Ke Shih rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3498eeadcd2aSChia-Yuan Li B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3499eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3500eeadcd2aSChia-Yuan Li B_AX_BBRPT_CHINFO_IMR_CLR); 3501eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3502eeadcd2aSChia-Yuan Li imr->bbrpt_err_imr_set); 3503eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3504eeadcd2aSChia-Yuan Li B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3505eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3506eeadcd2aSChia-Yuan Li } 3507eeadcd2aSChia-Yuan Li 3508d86369e9SChia-Yuan Li static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3509d86369e9SChia-Yuan Li { 3510d86369e9SChia-Yuan Li u32 reg; 3511d86369e9SChia-Yuan Li 3512c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3513d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3514d86369e9SChia-Yuan Li B_AX_FSM_TIMEOUT_ERR_INT_EN); 3515d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3516d86369e9SChia-Yuan Li } 3517d86369e9SChia-Yuan Li 3518d86369e9SChia-Yuan Li static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3519d86369e9SChia-Yuan Li { 3520d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3521d86369e9SChia-Yuan Li u32 reg; 3522d86369e9SChia-Yuan Li 3523c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3524d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3525d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3526d86369e9SChia-Yuan Li } 3527d86369e9SChia-Yuan Li 3528d86369e9SChia-Yuan Li static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3529d86369e9SChia-Yuan Li { 3530d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3531d86369e9SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3532d86369e9SChia-Yuan Li u32 reg; 3533d86369e9SChia-Yuan Li 3534c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3535d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3536d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3537d86369e9SChia-Yuan Li 3538d86369e9SChia-Yuan Li if (chip_id == RTL8852C) { 3539c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3540d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3541d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3542d86369e9SChia-Yuan Li } 3543d86369e9SChia-Yuan Li } 3544d86369e9SChia-Yuan Li 3545d86369e9SChia-Yuan Li static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3546d86369e9SChia-Yuan Li { 3547d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3548d86369e9SChia-Yuan Li u32 reg; 3549d86369e9SChia-Yuan Li 3550c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3551d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3552d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3553d86369e9SChia-Yuan Li } 3554d86369e9SChia-Yuan Li 3555d86369e9SChia-Yuan Li static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3556d86369e9SChia-Yuan Li { 3557d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3558d86369e9SChia-Yuan Li u32 reg; 3559d86369e9SChia-Yuan Li 3560c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3561d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3562d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3563d86369e9SChia-Yuan Li } 3564d86369e9SChia-Yuan Li 3565d86369e9SChia-Yuan Li static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3566d86369e9SChia-Yuan Li { 3567d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3568d86369e9SChia-Yuan Li u32 reg; 3569d86369e9SChia-Yuan Li 3570c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3571d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3572d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3573d86369e9SChia-Yuan Li } 3574d86369e9SChia-Yuan Li 3575fc663fa0SPing-Ke Shih static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3576e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 3577e3ec7017SPing-Ke Shih { 3578e3ec7017SPing-Ke Shih int ret; 3579e3ec7017SPing-Ke Shih 3580e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3581e3ec7017SPing-Ke Shih if (ret) { 3582e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3583e3ec7017SPing-Ke Shih sel, mac_idx); 3584e3ec7017SPing-Ke Shih return ret; 3585e3ec7017SPing-Ke Shih } 3586e3ec7017SPing-Ke Shih 3587e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 3588eeadcd2aSChia-Yuan Li rtw89_wdrls_imr_enable(rtwdev); 3589eeadcd2aSChia-Yuan Li rtw89_wsec_imr_enable(rtwdev); 3590eeadcd2aSChia-Yuan Li rtw89_mpdu_trx_imr_enable(rtwdev); 3591eeadcd2aSChia-Yuan Li rtw89_sta_sch_imr_enable(rtwdev); 3592eeadcd2aSChia-Yuan Li rtw89_txpktctl_imr_enable(rtwdev); 3593eeadcd2aSChia-Yuan Li rtw89_wde_imr_enable(rtwdev); 3594eeadcd2aSChia-Yuan Li rtw89_ple_imr_enable(rtwdev); 3595eeadcd2aSChia-Yuan Li rtw89_pktin_imr_enable(rtwdev); 3596eeadcd2aSChia-Yuan Li rtw89_dispatcher_imr_enable(rtwdev); 3597eeadcd2aSChia-Yuan Li rtw89_cpuio_imr_enable(rtwdev); 3598eeadcd2aSChia-Yuan Li rtw89_bbrpt_imr_enable(rtwdev); 3599e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL) { 3600d86369e9SChia-Yuan Li rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3601d86369e9SChia-Yuan Li rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3602d86369e9SChia-Yuan Li rtw89_cdma_imr_enable(rtwdev, mac_idx); 3603d86369e9SChia-Yuan Li rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3604d86369e9SChia-Yuan Li rtw89_rmac_imr_enable(rtwdev, mac_idx); 3605d86369e9SChia-Yuan Li rtw89_tmac_imr_enable(rtwdev, mac_idx); 3606e3ec7017SPing-Ke Shih } else { 3607e3ec7017SPing-Ke Shih return -EINVAL; 3608e3ec7017SPing-Ke Shih } 3609e3ec7017SPing-Ke Shih 3610e3ec7017SPing-Ke Shih return 0; 3611e3ec7017SPing-Ke Shih } 3612e3ec7017SPing-Ke Shih 3613fc663fa0SPing-Ke Shih static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 36149f405b01SPing-Ke Shih { 36159f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 36169f405b01SPing-Ke Shih en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 36179f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 36189f405b01SPing-Ke Shih en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3619190dc12dSPing-Ke Shih if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta) 36209f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 36219f405b01SPing-Ke Shih en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 36229f405b01SPing-Ke Shih } 36239f405b01SPing-Ke Shih 3624fc663fa0SPing-Ke Shih static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3625e3ec7017SPing-Ke Shih { 3626e3ec7017SPing-Ke Shih int ret = 0; 3627e3ec7017SPing-Ke Shih 3628e3ec7017SPing-Ke Shih if (enable) { 3629fc663fa0SPing-Ke Shih ret = band1_enable_ax(rtwdev); 3630e3ec7017SPing-Ke Shih if (ret) { 3631e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3632e3ec7017SPing-Ke Shih return ret; 3633e3ec7017SPing-Ke Shih } 3634e3ec7017SPing-Ke Shih 3635fc663fa0SPing-Ke Shih ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3636e3ec7017SPing-Ke Shih if (ret) { 3637e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3638e3ec7017SPing-Ke Shih return ret; 3639e3ec7017SPing-Ke Shih } 3640e3ec7017SPing-Ke Shih } else { 3641e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3642e3ec7017SPing-Ke Shih return -EINVAL; 3643e3ec7017SPing-Ke Shih } 3644e3ec7017SPing-Ke Shih 3645e3ec7017SPing-Ke Shih return 0; 3646e3ec7017SPing-Ke Shih } 3647e3ec7017SPing-Ke Shih 3648fc663fa0SPing-Ke Shih static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3649e3ec7017SPing-Ke Shih { 3650e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3651e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3652e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3653e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3654e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 3655e3ec7017SPing-Ke Shih } else { 3656e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3657e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3658e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3659e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 3660e3ec7017SPing-Ke Shih } 3661e3ec7017SPing-Ke Shih 3662e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3663e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3664e3ec7017SPing-Ke Shih 3665e3ec7017SPing-Ke Shih return 0; 3666e3ec7017SPing-Ke Shih } 3667e3ec7017SPing-Ke Shih 3668fc663fa0SPing-Ke Shih static int trx_init_ax(struct rtw89_dev *rtwdev) 3669e3ec7017SPing-Ke Shih { 36707be73dc1SKuan-Chung Chen enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3671e3ec7017SPing-Ke Shih enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3672e3ec7017SPing-Ke Shih int ret; 3673e3ec7017SPing-Ke Shih 3674fc663fa0SPing-Ke Shih ret = dmac_init_ax(rtwdev, 0); 3675e3ec7017SPing-Ke Shih if (ret) { 3676e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3677e3ec7017SPing-Ke Shih return ret; 3678e3ec7017SPing-Ke Shih } 3679e3ec7017SPing-Ke Shih 3680fc663fa0SPing-Ke Shih ret = cmac_init_ax(rtwdev, 0); 3681e3ec7017SPing-Ke Shih if (ret) { 3682e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3683e3ec7017SPing-Ke Shih return ret; 3684e3ec7017SPing-Ke Shih } 3685e3ec7017SPing-Ke Shih 3686fc663fa0SPing-Ke Shih if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3687fc663fa0SPing-Ke Shih ret = dbcc_enable_ax(rtwdev, true); 3688e3ec7017SPing-Ke Shih if (ret) { 3689e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3690e3ec7017SPing-Ke Shih return ret; 3691e3ec7017SPing-Ke Shih } 3692e3ec7017SPing-Ke Shih } 3693e3ec7017SPing-Ke Shih 3694fc663fa0SPing-Ke Shih ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3695e3ec7017SPing-Ke Shih if (ret) { 3696e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3697e3ec7017SPing-Ke Shih return ret; 3698e3ec7017SPing-Ke Shih } 3699e3ec7017SPing-Ke Shih 3700fc663fa0SPing-Ke Shih ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3701e3ec7017SPing-Ke Shih if (ret) { 3702e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3703e3ec7017SPing-Ke Shih return ret; 3704e3ec7017SPing-Ke Shih } 3705e3ec7017SPing-Ke Shih 3706fc663fa0SPing-Ke Shih err_imr_ctrl_ax(rtwdev, true); 37079f405b01SPing-Ke Shih 3708fc663fa0SPing-Ke Shih ret = set_host_rpr_ax(rtwdev); 3709e3ec7017SPing-Ke Shih if (ret) { 3710e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3711e3ec7017SPing-Ke Shih return ret; 3712e3ec7017SPing-Ke Shih } 3713e3ec7017SPing-Ke Shih 37147be73dc1SKuan-Chung Chen if (chip_id == RTL8852C) 37157be73dc1SKuan-Chung Chen rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG, 37167be73dc1SKuan-Chung Chen B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN); 37177be73dc1SKuan-Chung Chen 3718e3ec7017SPing-Ke Shih return 0; 3719e3ec7017SPing-Ke Shih } 3720e3ec7017SPing-Ke Shih 37213b96833aSPing-Ke Shih static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 37223b96833aSPing-Ke Shih { 37233b96833aSPing-Ke Shih #define BACAM_1024BMP_OCC_ENTRY 4 37243b96833aSPing-Ke Shih #define BACAM_MAX_RU_SUPPORT_B0_STA 1 37253b96833aSPing-Ke Shih #define BACAM_MAX_RU_SUPPORT_B1_STA 1 37263b96833aSPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 37273b96833aSPing-Ke Shih u8 users, offset; 37283b96833aSPing-Ke Shih 37293b96833aSPing-Ke Shih if (chip->bacam_ver != RTW89_BACAM_V1) 37303b96833aSPing-Ke Shih return 0; 37313b96833aSPing-Ke Shih 37323b96833aSPing-Ke Shih offset = 0; 37333b96833aSPing-Ke Shih users = BACAM_MAX_RU_SUPPORT_B0_STA; 37343b96833aSPing-Ke Shih rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 37353b96833aSPing-Ke Shih 37363b96833aSPing-Ke Shih offset += users * BACAM_1024BMP_OCC_ENTRY; 37373b96833aSPing-Ke Shih users = BACAM_MAX_RU_SUPPORT_B1_STA; 37383b96833aSPing-Ke Shih rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 37393b96833aSPing-Ke Shih 37403b96833aSPing-Ke Shih return 0; 37413b96833aSPing-Ke Shih } 37423b96833aSPing-Ke Shih 3743ec356ffbSChia-Yuan Li static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3744ec356ffbSChia-Yuan Li { 3745ec356ffbSChia-Yuan Li u32 val32; 3746ec356ffbSChia-Yuan Li 3747190dc12dSPing-Ke Shih if (rtw89_is_rtl885xb(rtwdev)) { 37485c3afcbaSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 37495c3afcbaSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 37505c3afcbaSPing-Ke Shih return; 37515c3afcbaSPing-Ke Shih } 37525c3afcbaSPing-Ke Shih 3753ec356ffbSChia-Yuan Li rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3754ec356ffbSChia-Yuan Li WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3755ec356ffbSChia-Yuan Li 3756ec356ffbSChia-Yuan Li val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3757ec356ffbSChia-Yuan Li val32 |= B_AX_FS_WDT_INT; 3758ec356ffbSChia-Yuan Li val32 &= ~B_AX_FS_WDT_INT_MSK; 3759ec356ffbSChia-Yuan Li rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3760ec356ffbSChia-Yuan Li } 3761ec356ffbSChia-Yuan Li 3762ae4dc23dSPing-Ke Shih static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3763e3ec7017SPing-Ke Shih { 3764e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3765e3ec7017SPing-Ke Shih 3766e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3767de78869dSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3768de78869dSChia-Yuan Li B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3769e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3770ec356ffbSChia-Yuan Li 3771ec356ffbSChia-Yuan Li rtw89_disable_fw_watchdog(rtwdev); 3772ec356ffbSChia-Yuan Li 3773de78869dSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3774de78869dSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3775e3ec7017SPing-Ke Shih } 3776e3ec7017SPing-Ke Shih 3777a712eef6SPing-Ke Shih static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3778a712eef6SPing-Ke Shih bool dlfw, bool include_bb) 3779e3ec7017SPing-Ke Shih { 3780e3ec7017SPing-Ke Shih u32 val; 3781e3ec7017SPing-Ke Shih int ret; 3782e3ec7017SPing-Ke Shih 3783e3ec7017SPing-Ke Shih if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3784e3ec7017SPing-Ke Shih return -EFAULT; 3785e3ec7017SPing-Ke Shih 3786e749ef96SPing-Ke Shih rtw89_write32(rtwdev, R_AX_UDM1, 0); 3787e749ef96SPing-Ke Shih rtw89_write32(rtwdev, R_AX_UDM2, 0); 3788e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3789e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3790a63ae673SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3791a63ae673SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3792e3ec7017SPing-Ke Shih 3793e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3794e3ec7017SPing-Ke Shih 3795e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3796e3ec7017SPing-Ke Shih val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3797e3ec7017SPing-Ke Shih val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3798e3ec7017SPing-Ke Shih B_AX_WCPU_FWDL_STS_MASK); 3799e3ec7017SPing-Ke Shih 3800e3ec7017SPing-Ke Shih if (dlfw) 3801e3ec7017SPing-Ke Shih val |= B_AX_WCPU_FWDL_EN; 3802e3ec7017SPing-Ke Shih 3803e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 38042e5a65f5SPing-Ke Shih 380580fb81bbSPing-Ke Shih if (rtw89_is_rtl885xb(rtwdev)) 38062e5a65f5SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 38072e5a65f5SPing-Ke Shih B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 38082e5a65f5SPing-Ke Shih 3809e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3810e3ec7017SPing-Ke Shih boot_reason); 3811e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3812e3ec7017SPing-Ke Shih 3813e3ec7017SPing-Ke Shih if (!dlfw) { 3814e3ec7017SPing-Ke Shih mdelay(5); 3815e3ec7017SPing-Ke Shih 3816fa31a8c5SPing-Ke Shih ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3817e3ec7017SPing-Ke Shih if (ret) 3818e3ec7017SPing-Ke Shih return ret; 3819e3ec7017SPing-Ke Shih } 3820e3ec7017SPing-Ke Shih 3821e3ec7017SPing-Ke Shih return 0; 3822e3ec7017SPing-Ke Shih } 3823e3ec7017SPing-Ke Shih 382439e9b569SPing-Ke Shih static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 3825e3ec7017SPing-Ke Shih { 3826a7d82a7aSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3827e3ec7017SPing-Ke Shih u32 val; 3828e3ec7017SPing-Ke Shih 3829a7d82a7aSPing-Ke Shih if (chip_id == RTL8852C) 3830a7d82a7aSPing-Ke Shih val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3831a7d82a7aSPing-Ke Shih B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3832a7d82a7aSPing-Ke Shih else 3833e3ec7017SPing-Ke Shih val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3834e3ec7017SPing-Ke Shih B_AX_PKT_BUF_EN; 3835e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 38360d16d8fbSPing-Ke Shih } 38370d16d8fbSPing-Ke Shih 383839e9b569SPing-Ke Shih static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 38390d16d8fbSPing-Ke Shih { 38400d16d8fbSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 38410d16d8fbSPing-Ke Shih u32 val; 3842e3ec7017SPing-Ke Shih 3843190dc12dSPing-Ke Shih if (chip_id == RTL8851B || chip_id == RTL8852BT) 38445c3afcbaSPing-Ke Shih val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 38455c3afcbaSPing-Ke Shih else 3846e3ec7017SPing-Ke Shih val = B_AX_DISPATCHER_CLK_EN; 3847e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3848e3ec7017SPing-Ke Shih 3849a7d82a7aSPing-Ke Shih if (chip_id != RTL8852C) 38500d16d8fbSPing-Ke Shih return; 3851a7d82a7aSPing-Ke Shih 3852a7d82a7aSPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3853a7d82a7aSPing-Ke Shih val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3854a7d82a7aSPing-Ke Shih val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3855a7d82a7aSPing-Ke Shih B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3856a7d82a7aSPing-Ke Shih rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3857a7d82a7aSPing-Ke Shih 3858a7d82a7aSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3859a7d82a7aSPing-Ke Shih B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3860a7d82a7aSPing-Ke Shih B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3861a7d82a7aSPing-Ke Shih B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3862a7d82a7aSPing-Ke Shih B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3863a7d82a7aSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3864a7d82a7aSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 38650d16d8fbSPing-Ke Shih } 3866a7d82a7aSPing-Ke Shih 38670d16d8fbSPing-Ke Shih static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 38680d16d8fbSPing-Ke Shih { 386939e9b569SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 38700d16d8fbSPing-Ke Shih int ret; 38710d16d8fbSPing-Ke Shih 387239e9b569SPing-Ke Shih mac->hci_func_en(rtwdev); 387339e9b569SPing-Ke Shih mac->dmac_func_pre_en(rtwdev); 38740d16d8fbSPing-Ke Shih 3875fc663fa0SPing-Ke Shih ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3876e3ec7017SPing-Ke Shih if (ret) { 3877e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3878e3ec7017SPing-Ke Shih return ret; 3879e3ec7017SPing-Ke Shih } 3880e3ec7017SPing-Ke Shih 3881fc663fa0SPing-Ke Shih ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 3882e3ec7017SPing-Ke Shih if (ret) { 3883e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3884e3ec7017SPing-Ke Shih return ret; 3885e3ec7017SPing-Ke Shih } 3886e3ec7017SPing-Ke Shih 3887e3ec7017SPing-Ke Shih return ret; 3888e3ec7017SPing-Ke Shih } 3889e3ec7017SPing-Ke Shih 389061ebeecbSPing-Ke Shih int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3891e3ec7017SPing-Ke Shih { 3892e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3893e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3894e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3895e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3896e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3897e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 389861ebeecbSPing-Ke Shih 389961ebeecbSPing-Ke Shih return 0; 3900e3ec7017SPing-Ke Shih } 390161ebeecbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3902e3ec7017SPing-Ke Shih 390314b6e9f4SPing-Ke Shih int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3904e3ec7017SPing-Ke Shih { 3905e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3906e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3907e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3908e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3909e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3910e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 391114b6e9f4SPing-Ke Shih 391214b6e9f4SPing-Ke Shih return 0; 3913e3ec7017SPing-Ke Shih } 391461ebeecbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3915e3ec7017SPing-Ke Shih 3916a712eef6SPing-Ke Shih int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 3917e3ec7017SPing-Ke Shih { 3918e3ec7017SPing-Ke Shih int ret; 3919e3ec7017SPing-Ke Shih 3920e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 3921e3ec7017SPing-Ke Shih if (ret) { 3922e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 3923e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 3924e3ec7017SPing-Ke Shih if (ret) 3925e3ec7017SPing-Ke Shih return ret; 3926e3ec7017SPing-Ke Shih } 3927e3ec7017SPing-Ke Shih 392852f12705SChin-Yen Lee rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3929e3ec7017SPing-Ke Shih 3930c6ea2a83SPing-Ke Shih if (include_bb) { 3931c6ea2a83SPing-Ke Shih rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 3932c6ea2a83SPing-Ke Shih if (rtwdev->dbcc_en) 3933c6ea2a83SPing-Ke Shih rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 3934c6ea2a83SPing-Ke Shih } 3935c6ea2a83SPing-Ke Shih 3936a7d82a7aSPing-Ke Shih ret = rtw89_mac_dmac_pre_init(rtwdev); 3937a7d82a7aSPing-Ke Shih if (ret) 3938a7d82a7aSPing-Ke Shih return ret; 3939a7d82a7aSPing-Ke Shih 3940e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_pre_init) { 3941e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3942e3ec7017SPing-Ke Shih if (ret) 3943e3ec7017SPing-Ke Shih return ret; 3944e3ec7017SPing-Ke Shih } 3945e3ec7017SPing-Ke Shih 3946a712eef6SPing-Ke Shih ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 3947e3ec7017SPing-Ke Shih if (ret) 3948e3ec7017SPing-Ke Shih return ret; 3949e3ec7017SPing-Ke Shih 3950e3ec7017SPing-Ke Shih return 0; 3951e3ec7017SPing-Ke Shih } 3952e3ec7017SPing-Ke Shih 3953e3ec7017SPing-Ke Shih int rtw89_mac_init(struct rtw89_dev *rtwdev) 3954e3ec7017SPing-Ke Shih { 3955fc663fa0SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3956a712eef6SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 3957a712eef6SPing-Ke Shih bool include_bb = !!chip->bbmcu_nr; 3958e3ec7017SPing-Ke Shih int ret; 3959e3ec7017SPing-Ke Shih 3960a712eef6SPing-Ke Shih ret = rtw89_mac_partial_init(rtwdev, include_bb); 3961e3ec7017SPing-Ke Shih if (ret) 3962e3ec7017SPing-Ke Shih goto fail; 3963e3ec7017SPing-Ke Shih 396461ebeecbSPing-Ke Shih ret = rtw89_chip_enable_bb_rf(rtwdev); 396561ebeecbSPing-Ke Shih if (ret) 396661ebeecbSPing-Ke Shih goto fail; 3967e3ec7017SPing-Ke Shih 3968fc663fa0SPing-Ke Shih ret = mac->sys_init(rtwdev); 3969e3ec7017SPing-Ke Shih if (ret) 3970e3ec7017SPing-Ke Shih goto fail; 3971e3ec7017SPing-Ke Shih 3972fc663fa0SPing-Ke Shih ret = mac->trx_init(rtwdev); 3973e3ec7017SPing-Ke Shih if (ret) 3974e3ec7017SPing-Ke Shih goto fail; 3975e3ec7017SPing-Ke Shih 39763b96833aSPing-Ke Shih ret = rtw89_mac_feat_init(rtwdev); 39773b96833aSPing-Ke Shih if (ret) 39783b96833aSPing-Ke Shih goto fail; 39793b96833aSPing-Ke Shih 3980e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_post_init) { 3981e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3982e3ec7017SPing-Ke Shih if (ret) 3983e3ec7017SPing-Ke Shih goto fail; 3984e3ec7017SPing-Ke Shih } 3985e3ec7017SPing-Ke Shih 3986e3ec7017SPing-Ke Shih rtw89_fw_send_all_early_h2c(rtwdev); 3987e3ec7017SPing-Ke Shih rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3988e3ec7017SPing-Ke Shih 3989e3ec7017SPing-Ke Shih return ret; 3990e3ec7017SPing-Ke Shih fail: 3991e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 3992e3ec7017SPing-Ke Shih 3993e3ec7017SPing-Ke Shih return ret; 3994e3ec7017SPing-Ke Shih } 3995e3ec7017SPing-Ke Shih 3996e3ec7017SPing-Ke Shih static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3997e3ec7017SPing-Ke Shih { 3998e3ec7017SPing-Ke Shih u8 i; 3999e3ec7017SPing-Ke Shih 400060168f6cSPing-Ke Shih if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 400160168f6cSPing-Ke Shih return; 400260168f6cSPing-Ke Shih 4003e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 4004e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4005e3ec7017SPing-Ke Shih DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 4006e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 4007e3ec7017SPing-Ke Shih } 4008e3ec7017SPing-Ke Shih } 4009e3ec7017SPing-Ke Shih 4010e3ec7017SPing-Ke Shih static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4011e3ec7017SPing-Ke Shih { 401260168f6cSPing-Ke Shih if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 401360168f6cSPing-Ke Shih return; 401460168f6cSPing-Ke Shih 4015e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4016e3ec7017SPing-Ke Shih CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 4017e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 4018e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 4019e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 4020e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 4021e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 4022e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 4023e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 4024e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 4025e3ec7017SPing-Ke Shih } 4026e3ec7017SPing-Ke Shih 40271b73e77dSPing-Ke Shih int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4028e3ec7017SPing-Ke Shih { 4029e3ec7017SPing-Ke Shih u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4030e3ec7017SPing-Ke Shih u8 grp = macid >> 5; 4031e3ec7017SPing-Ke Shih int ret; 4032e3ec7017SPing-Ke Shih 4033ac3a9f18SPing-Ke Shih /* If this is called by change_interface() in the case of P2P, it could 4034ac3a9f18SPing-Ke Shih * be power-off, so ignore this operation. 4035ac3a9f18SPing-Ke Shih */ 4036ac3a9f18SPing-Ke Shih if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4037ac3a9f18SPing-Ke Shih !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4038ac3a9f18SPing-Ke Shih return 0; 4039ac3a9f18SPing-Ke Shih 4040e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4041e3ec7017SPing-Ke Shih if (ret) 4042e3ec7017SPing-Ke Shih return ret; 4043e3ec7017SPing-Ke Shih 4044e3ec7017SPing-Ke Shih rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4045e3ec7017SPing-Ke Shih 4046e3ec7017SPing-Ke Shih return 0; 4047e3ec7017SPing-Ke Shih } 4048e3ec7017SPing-Ke Shih 40497c8a55ddSPing-Ke Shih static const struct rtw89_port_reg rtw89_port_base_ax = { 4050e3ec7017SPing-Ke Shih .port_cfg = R_AX_PORT_CFG_P0, 4051e3ec7017SPing-Ke Shih .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4052e3ec7017SPing-Ke Shih .bcn_area = R_AX_BCN_AREA_P0, 4053e3ec7017SPing-Ke Shih .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4054e3ec7017SPing-Ke Shih .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4055e3ec7017SPing-Ke Shih .tbtt_agg = R_AX_TBTT_AGG_P0, 4056e3ec7017SPing-Ke Shih .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4057e3ec7017SPing-Ke Shih .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4058e3ec7017SPing-Ke Shih .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4059e3ec7017SPing-Ke Shih .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4060e3ec7017SPing-Ke Shih .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4061e3ec7017SPing-Ke Shih .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4062e3ec7017SPing-Ke Shih .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4063e3ec7017SPing-Ke Shih .tsftr_l = R_AX_TSFTR_LOW_P0, 406465129813SPing-Ke Shih .tsftr_h = R_AX_TSFTR_HIGH_P0, 406565129813SPing-Ke Shih .md_tsft = R_AX_MD_TSFT_STMP_CTL, 406665129813SPing-Ke Shih .bss_color = R_AX_PTCL_BSS_COLOR_0, 406765129813SPing-Ke Shih .mbssid = R_AX_MBSSID_CTRL, 406865129813SPing-Ke Shih .mbssid_drop = R_AX_MBSSID_DROP_0, 406965129813SPing-Ke Shih .tsf_sync = R_AX_PORT0_TSF_SYNC, 4070598481c6SChih-Kang Chang .ptcl_dbg = R_AX_PTCL_DBG, 4071598481c6SChih-Kang Chang .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4072598481c6SChih-Kang Chang .bcn_drop_all = R_AX_BCN_DROP_ALL0, 407365129813SPing-Ke Shih .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 407465129813SPing-Ke Shih R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 407565129813SPing-Ke Shih R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4076e3ec7017SPing-Ke Shih }; 4077e3ec7017SPing-Ke Shih 40780052b3c4SPo-Hao Huang static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 40790052b3c4SPo-Hao Huang struct rtw89_vif *rtwvif, u8 type) 40800052b3c4SPo-Hao Huang { 4081598481c6SChih-Kang Chang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4082598481c6SChih-Kang Chang const struct rtw89_port_reg *p = mac->port_base; 40830052b3c4SPo-Hao Huang u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif->port); 40840052b3c4SPo-Hao Huang u32 reg_info, reg_ctrl; 40850052b3c4SPo-Hao Huang u32 val; 40860052b3c4SPo-Hao Huang int ret; 40870052b3c4SPo-Hao Huang 4088598481c6SChih-Kang Chang reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif->mac_idx); 4089598481c6SChih-Kang Chang reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif->mac_idx); 40900052b3c4SPo-Hao Huang 40910052b3c4SPo-Hao Huang rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 40920052b3c4SPo-Hao Huang rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 40930052b3c4SPo-Hao Huang fsleep(100); 40940052b3c4SPo-Hao Huang 40950052b3c4SPo-Hao Huang ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 40960052b3c4SPo-Hao Huang true, rtwdev, reg_info, mask); 40970052b3c4SPo-Hao Huang if (ret) 40980052b3c4SPo-Hao Huang rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 40990052b3c4SPo-Hao Huang } 41000052b3c4SPo-Hao Huang 41010052b3c4SPo-Hao Huang static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 41020052b3c4SPo-Hao Huang { 41030052b3c4SPo-Hao Huang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 41040052b3c4SPo-Hao Huang const struct rtw89_port_reg *p = mac->port_base; 41050052b3c4SPo-Hao Huang 4106598481c6SChih-Kang Chang rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif->port)); 41070052b3c4SPo-Hao Huang rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 1); 41080052b3c4SPo-Hao Huang rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 0); 41090052b3c4SPo-Hao Huang rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 0); 41100052b3c4SPo-Hao Huang rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 2); 41110052b3c4SPo-Hao Huang rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK, 1); 41120052b3c4SPo-Hao Huang rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 1); 41130052b3c4SPo-Hao Huang rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 41140052b3c4SPo-Hao Huang 41150052b3c4SPo-Hao Huang rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM0); 41160052b3c4SPo-Hao Huang if (rtwvif->port == RTW89_PORT_0) 41170052b3c4SPo-Hao Huang rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM1); 41180052b3c4SPo-Hao Huang 4119598481c6SChih-Kang Chang rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif->port)); 41200052b3c4SPo-Hao Huang rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TBTT_PROHIB_EN); 41215ba45ba7SChih-Kang Chang fsleep(2000); 41220052b3c4SPo-Hao Huang } 41230052b3c4SPo-Hao Huang 4124e3ec7017SPing-Ke Shih #define BCN_INTERVAL 100 4125e3ec7017SPing-Ke Shih #define BCN_ERLY_DEF 160 4126e3ec7017SPing-Ke Shih #define BCN_SETUP_DEF 2 4127e3ec7017SPing-Ke Shih #define BCN_HOLD_DEF 200 4128e3ec7017SPing-Ke Shih #define BCN_MASK_DEF 0 4129e3ec7017SPing-Ke Shih #define TBTT_ERLY_DEF 5 4130e3ec7017SPing-Ke Shih #define BCN_SET_UNIT 32 4131e3ec7017SPing-Ke Shih #define BCN_ERLY_SET_DLY (10 * 2) 4132e3ec7017SPing-Ke Shih 4133e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4134e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4135e3ec7017SPing-Ke Shih { 41367c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 41377c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4138e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 41390052b3c4SPo-Hao Huang const struct rtw89_chip_info *chip = rtwdev->chip; 41400052b3c4SPo-Hao Huang bool need_backup = false; 41410052b3c4SPo-Hao Huang u32 backup_val; 4142e3ec7017SPing-Ke Shih 4143e3ec7017SPing-Ke Shih if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 4144e3ec7017SPing-Ke Shih return; 4145e3ec7017SPing-Ke Shih 41460052b3c4SPo-Hao Huang if (chip->chip_id == RTL8852A && rtwvif->port != RTW89_PORT_0) { 41470052b3c4SPo-Hao Huang need_backup = true; 41480052b3c4SPo-Hao Huang backup_val = rtw89_read32_port(rtwdev, rtwvif, p->tbtt_prohib); 41490052b3c4SPo-Hao Huang } 41500052b3c4SPo-Hao Huang 41510052b3c4SPo-Hao Huang if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 41520052b3c4SPo-Hao Huang rtw89_mac_bcn_drop(rtwdev, rtwvif); 41530052b3c4SPo-Hao Huang 41540052b3c4SPo-Hao Huang if (chip->chip_id == RTL8852A) { 4155e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 4156e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 4157e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 4158e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 41590052b3c4SPo-Hao Huang } 4160e3ec7017SPing-Ke Shih 4161e3ec7017SPing-Ke Shih msleep(vif->bss_conf.beacon_int + 1); 4162e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 4163e3ec7017SPing-Ke Shih B_AX_BRK_SETUP); 4164e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 4165e3ec7017SPing-Ke Shih rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 41660052b3c4SPo-Hao Huang 41670052b3c4SPo-Hao Huang if (need_backup) 41680052b3c4SPo-Hao Huang rtw89_write32_port(rtwdev, rtwvif, p->tbtt_prohib, backup_val); 4169e3ec7017SPing-Ke Shih } 4170e3ec7017SPing-Ke Shih 4171e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4172e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 4173e3ec7017SPing-Ke Shih { 41747c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 41757c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4176e3ec7017SPing-Ke Shih 4177e3ec7017SPing-Ke Shih if (en) 4178e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4179e3ec7017SPing-Ke Shih else 4180e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4181e3ec7017SPing-Ke Shih } 4182e3ec7017SPing-Ke Shih 4183e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4184e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 4185e3ec7017SPing-Ke Shih { 41867c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 41877c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4188e3ec7017SPing-Ke Shih 4189e3ec7017SPing-Ke Shih if (en) 4190e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4191e3ec7017SPing-Ke Shih else 4192e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4193e3ec7017SPing-Ke Shih } 4194e3ec7017SPing-Ke Shih 4195e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4196e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4197e3ec7017SPing-Ke Shih { 41987c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 41997c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4200e3ec7017SPing-Ke Shih 4201e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 4202e3ec7017SPing-Ke Shih rtwvif->net_type); 4203e3ec7017SPing-Ke Shih } 4204e3ec7017SPing-Ke Shih 4205e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4206e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4207e3ec7017SPing-Ke Shih { 42087c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 42097c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4210e3ec7017SPing-Ke Shih bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 4211e3ec7017SPing-Ke Shih u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4212e3ec7017SPing-Ke Shih 4213e3ec7017SPing-Ke Shih if (en) 4214e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 4215e3ec7017SPing-Ke Shih else 4216e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 4217e3ec7017SPing-Ke Shih } 4218e3ec7017SPing-Ke Shih 4219e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4220e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4221e3ec7017SPing-Ke Shih { 42227c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 42237c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4224e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4225e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4226e3ec7017SPing-Ke Shih u32 bit = B_AX_RX_BSSID_FIT_EN; 4227e3ec7017SPing-Ke Shih 4228e3ec7017SPing-Ke Shih if (en) 4229e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 4230e3ec7017SPing-Ke Shih else 4231e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 4232e3ec7017SPing-Ke Shih } 4233e3ec7017SPing-Ke Shih 4234f59a98c8SChih-Kang Chang void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4235f59a98c8SChih-Kang Chang struct rtw89_vif *rtwvif, bool en) 4236e3ec7017SPing-Ke Shih { 42377c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 42387c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4239e3ec7017SPing-Ke Shih 4240e3ec7017SPing-Ke Shih if (en) 4241e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4242e3ec7017SPing-Ke Shih else 4243e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4244e3ec7017SPing-Ke Shih } 4245e3ec7017SPing-Ke Shih 4246f59a98c8SChih-Kang Chang static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4247f59a98c8SChih-Kang Chang struct rtw89_vif *rtwvif) 4248f59a98c8SChih-Kang Chang { 4249f59a98c8SChih-Kang Chang bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4250f59a98c8SChih-Kang Chang rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4251f59a98c8SChih-Kang Chang 4252f59a98c8SChih-Kang Chang rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif, en); 4253f59a98c8SChih-Kang Chang } 4254f59a98c8SChih-Kang Chang 4255e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4256756b3120SChih-Kang Chang struct rtw89_vif *rtwvif, bool en) 4257e3ec7017SPing-Ke Shih { 42587c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 42597c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4260e3ec7017SPing-Ke Shih 4261e3ec7017SPing-Ke Shih if (en) 4262e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4263e3ec7017SPing-Ke Shih else 4264e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4265e3ec7017SPing-Ke Shih } 4266e3ec7017SPing-Ke Shih 4267756b3120SChih-Kang Chang static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4268756b3120SChih-Kang Chang struct rtw89_vif *rtwvif) 4269756b3120SChih-Kang Chang { 4270756b3120SChih-Kang Chang bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 4271756b3120SChih-Kang Chang rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4272756b3120SChih-Kang Chang 4273756b3120SChih-Kang Chang rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4274756b3120SChih-Kang Chang } 4275756b3120SChih-Kang Chang 4276756b3120SChih-Kang Chang void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4277756b3120SChih-Kang Chang { 4278756b3120SChih-Kang Chang struct rtw89_vif *rtwvif; 4279756b3120SChih-Kang Chang 4280756b3120SChih-Kang Chang rtw89_for_each_rtwvif(rtwdev, rtwvif) 4281756b3120SChih-Kang Chang if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4282756b3120SChih-Kang Chang rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4283756b3120SChih-Kang Chang } 4284756b3120SChih-Kang Chang 4285e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4286e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4287e3ec7017SPing-Ke Shih { 42887c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 42897c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4290e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4291e3ec7017SPing-Ke Shih u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 4292e3ec7017SPing-Ke Shih 4293e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 4294e3ec7017SPing-Ke Shih bcn_int); 4295e3ec7017SPing-Ke Shih } 4296e3ec7017SPing-Ke Shih 4297283c3d88SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4298283c3d88SPing-Ke Shih struct rtw89_vif *rtwvif) 4299283c3d88SPing-Ke Shih { 4300283c3d88SPing-Ke Shih u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 43017c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43027c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4303283c3d88SPing-Ke Shih u8 port = rtwvif->port; 4304283c3d88SPing-Ke Shih u32 reg; 4305283c3d88SPing-Ke Shih 430665129813SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif->mac_idx); 4307283c3d88SPing-Ke Shih rtw89_write8(rtwdev, reg, win); 4308283c3d88SPing-Ke Shih } 4309283c3d88SPing-Ke Shih 4310283c3d88SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4311283c3d88SPing-Ke Shih struct rtw89_vif *rtwvif) 4312283c3d88SPing-Ke Shih { 43137c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43147c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4315283c3d88SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4316283c3d88SPing-Ke Shih u32 addr; 4317283c3d88SPing-Ke Shih 431865129813SPing-Ke Shih addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif->mac_idx); 4319283c3d88SPing-Ke Shih rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4320283c3d88SPing-Ke Shih 4321283c3d88SPing-Ke Shih rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4322283c3d88SPing-Ke Shih vif->bss_conf.dtim_period); 4323283c3d88SPing-Ke Shih } 4324283c3d88SPing-Ke Shih 4325e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4326e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4327e3ec7017SPing-Ke Shih { 43287c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43297c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4330e3ec7017SPing-Ke Shih 4331e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4332e3ec7017SPing-Ke Shih B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4333e3ec7017SPing-Ke Shih } 4334e3ec7017SPing-Ke Shih 4335e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4336e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4337e3ec7017SPing-Ke Shih { 43387c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43397c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4340e3ec7017SPing-Ke Shih 4341e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4342e3ec7017SPing-Ke Shih B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4343e3ec7017SPing-Ke Shih } 4344e3ec7017SPing-Ke Shih 4345e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4346e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4347e3ec7017SPing-Ke Shih { 43487c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43497c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4350e3ec7017SPing-Ke Shih 4351e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 4352e3ec7017SPing-Ke Shih B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4353e3ec7017SPing-Ke Shih } 4354e3ec7017SPing-Ke Shih 4355e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4356e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4357e3ec7017SPing-Ke Shih { 43587c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43597c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4360e3ec7017SPing-Ke Shih 4361e3ec7017SPing-Ke Shih rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 4362e3ec7017SPing-Ke Shih B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4363e3ec7017SPing-Ke Shih } 4364e3ec7017SPing-Ke Shih 4365e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4366e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4367e3ec7017SPing-Ke Shih { 43687c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43697c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4370e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4371e3ec7017SPing-Ke Shih static const u32 masks[RTW89_PORT_NUM] = { 4372e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4373e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4374e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_4_MASK, 4375e3ec7017SPing-Ke Shih }; 4376e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 4377e3ec7017SPing-Ke Shih u32 reg_base; 4378e3ec7017SPing-Ke Shih u32 reg; 4379e3ec7017SPing-Ke Shih u8 bss_color; 4380e3ec7017SPing-Ke Shih 4381e3ec7017SPing-Ke Shih bss_color = vif->bss_conf.he_bss_color.color; 438265129813SPing-Ke Shih reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4383c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx); 4384e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4385e3ec7017SPing-Ke Shih } 4386e3ec7017SPing-Ke Shih 4387e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4388e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4389e3ec7017SPing-Ke Shih { 43907c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43917c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4392e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 4393e3ec7017SPing-Ke Shih u32 reg; 4394e3ec7017SPing-Ke Shih 4395e3ec7017SPing-Ke Shih if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4396e3ec7017SPing-Ke Shih return; 4397e3ec7017SPing-Ke Shih 4398e3ec7017SPing-Ke Shih if (port == 0) { 439965129813SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif->mac_idx); 4400e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4401e3ec7017SPing-Ke Shih } 4402e3ec7017SPing-Ke Shih } 4403e3ec7017SPing-Ke Shih 4404e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4405e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4406e3ec7017SPing-Ke Shih { 44077c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44087c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4409e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 4410e3ec7017SPing-Ke Shih u32 reg; 4411e3ec7017SPing-Ke Shih u32 val; 4412e3ec7017SPing-Ke Shih 441365129813SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif->mac_idx); 4414e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 4415e3ec7017SPing-Ke Shih val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4416e3ec7017SPing-Ke Shih if (port == 0) 4417e3ec7017SPing-Ke Shih val &= ~BIT(0); 4418e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 4419e3ec7017SPing-Ke Shih } 4420e3ec7017SPing-Ke Shih 4421e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4422d592b9f7SPo-Hao Huang struct rtw89_vif *rtwvif, bool enable) 4423e3ec7017SPing-Ke Shih { 44247c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44257c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4426e3ec7017SPing-Ke Shih 4427d592b9f7SPo-Hao Huang if (enable) 4428d592b9f7SPo-Hao Huang rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 4429d592b9f7SPo-Hao Huang B_AX_PORT_FUNC_EN); 4430d592b9f7SPo-Hao Huang else 4431d592b9f7SPo-Hao Huang rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 4432d592b9f7SPo-Hao Huang B_AX_PORT_FUNC_EN); 4433e3ec7017SPing-Ke Shih } 4434e3ec7017SPing-Ke Shih 4435e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4436e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4437e3ec7017SPing-Ke Shih { 44387c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44397c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4440e3ec7017SPing-Ke Shih 4441e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 4442e3ec7017SPing-Ke Shih BCN_ERLY_DEF); 4443e3ec7017SPing-Ke Shih } 4444e3ec7017SPing-Ke Shih 4445704052f5SChia-Yuan Li static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4446704052f5SChia-Yuan Li struct rtw89_vif *rtwvif) 4447704052f5SChia-Yuan Li { 44487c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44497c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4450704052f5SChia-Yuan Li u16 val; 4451704052f5SChia-Yuan Li 4452704052f5SChia-Yuan Li if (rtwdev->chip->chip_id != RTL8852C) 4453704052f5SChia-Yuan Li return; 4454704052f5SChia-Yuan Li 4455704052f5SChia-Yuan Li if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4456704052f5SChia-Yuan Li rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4457704052f5SChia-Yuan Li return; 4458704052f5SChia-Yuan Li 4459704052f5SChia-Yuan Li val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4460704052f5SChia-Yuan Li B_AX_TBTT_SHIFT_OFST_SIGN; 4461704052f5SChia-Yuan Li 4462704052f5SChia-Yuan Li rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 4463704052f5SChia-Yuan Li B_AX_TBTT_SHIFT_OFST_MASK, val); 4464704052f5SChia-Yuan Li } 4465704052f5SChia-Yuan Li 446642db7eddSZong-Zhe Yang void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4467fb2b8cecSPo-Hao Huang struct rtw89_vif *rtwvif, 446842db7eddSZong-Zhe Yang struct rtw89_vif *rtwvif_src, 446942db7eddSZong-Zhe Yang u16 offset_tu) 4470fb2b8cecSPo-Hao Huang { 44717c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44727c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4473fb2b8cecSPo-Hao Huang u32 val, reg; 4474fb2b8cecSPo-Hao Huang 447542db7eddSZong-Zhe Yang val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 447665129813SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif->port * 4, 447742db7eddSZong-Zhe Yang rtwvif->mac_idx); 447842db7eddSZong-Zhe Yang 447942db7eddSZong-Zhe Yang rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 448042db7eddSZong-Zhe Yang rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 448142db7eddSZong-Zhe Yang rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 448242db7eddSZong-Zhe Yang } 448342db7eddSZong-Zhe Yang 448442db7eddSZong-Zhe Yang static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 448542db7eddSZong-Zhe Yang struct rtw89_vif *rtwvif, 448642db7eddSZong-Zhe Yang struct rtw89_vif *rtwvif_src, 448742db7eddSZong-Zhe Yang u8 offset, int *n_offset) 448842db7eddSZong-Zhe Yang { 4489fb2b8cecSPo-Hao Huang if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 4490fb2b8cecSPo-Hao Huang return; 4491fb2b8cecSPo-Hao Huang 4492fb2b8cecSPo-Hao Huang /* adjust offset randomly to avoid beacon conflict */ 4493fb2b8cecSPo-Hao Huang offset = offset - offset / 4 + get_random_u32() % (offset / 2); 449442db7eddSZong-Zhe Yang rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 449542db7eddSZong-Zhe Yang (*n_offset) * offset); 4496fb2b8cecSPo-Hao Huang 44971120e6a6SZong-Zhe Yang (*n_offset)++; 4498fb2b8cecSPo-Hao Huang } 4499fb2b8cecSPo-Hao Huang 4500fb2b8cecSPo-Hao Huang static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4501fb2b8cecSPo-Hao Huang { 4502fb2b8cecSPo-Hao Huang struct rtw89_vif *src = NULL, *tmp; 4503fb2b8cecSPo-Hao Huang u8 offset = 100, vif_aps = 0; 4504fb2b8cecSPo-Hao Huang int n_offset = 1; 4505fb2b8cecSPo-Hao Huang 4506fb2b8cecSPo-Hao Huang rtw89_for_each_rtwvif(rtwdev, tmp) { 4507fb2b8cecSPo-Hao Huang if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4508fb2b8cecSPo-Hao Huang src = tmp; 4509fb2b8cecSPo-Hao Huang if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4510fb2b8cecSPo-Hao Huang vif_aps++; 4511fb2b8cecSPo-Hao Huang } 4512fb2b8cecSPo-Hao Huang 4513fb2b8cecSPo-Hao Huang if (vif_aps == 0) 4514fb2b8cecSPo-Hao Huang return; 4515fb2b8cecSPo-Hao Huang 4516fb2b8cecSPo-Hao Huang offset /= (vif_aps + 1); 4517fb2b8cecSPo-Hao Huang 4518fb2b8cecSPo-Hao Huang rtw89_for_each_rtwvif(rtwdev, tmp) 451942db7eddSZong-Zhe Yang rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4520fb2b8cecSPo-Hao Huang } 4521fb2b8cecSPo-Hao Huang 4522e3ec7017SPing-Ke Shih int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4523e3ec7017SPing-Ke Shih { 4524e3ec7017SPing-Ke Shih int ret; 4525e3ec7017SPing-Ke Shih 4526e3ec7017SPing-Ke Shih ret = rtw89_mac_port_update(rtwdev, rtwvif); 4527e3ec7017SPing-Ke Shih if (ret) 4528e3ec7017SPing-Ke Shih return ret; 4529e3ec7017SPing-Ke Shih 4530e3ec7017SPing-Ke Shih rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4531e3ec7017SPing-Ke Shih rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4532e3ec7017SPing-Ke Shih 45331b73e77dSPing-Ke Shih ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4534e3ec7017SPing-Ke Shih if (ret) 4535e3ec7017SPing-Ke Shih return ret; 4536e3ec7017SPing-Ke Shih 4537ff66964aSPing-Ke Shih ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4538e3ec7017SPing-Ke Shih if (ret) 4539e3ec7017SPing-Ke Shih return ret; 4540e3ec7017SPing-Ke Shih 4541a0e78d5cSPo-Hao Huang ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4542a0e78d5cSPo-Hao Huang if (ret) 4543a0e78d5cSPo-Hao Huang return ret; 4544a0e78d5cSPo-Hao Huang 4545e3ec7017SPing-Ke Shih ret = rtw89_cam_init(rtwdev, rtwvif); 4546e3ec7017SPing-Ke Shih if (ret) 4547e3ec7017SPing-Ke Shih return ret; 4548e3ec7017SPing-Ke Shih 454940822e07SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4550e3ec7017SPing-Ke Shih if (ret) 4551e3ec7017SPing-Ke Shih return ret; 4552e3ec7017SPing-Ke Shih 45533d49ed07SPing-Ke Shih ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, NULL); 4554e3ec7017SPing-Ke Shih if (ret) 4555e3ec7017SPing-Ke Shih return ret; 4556e3ec7017SPing-Ke Shih 4557011e2768SPing-Ke Shih ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, NULL); 4558011e2768SPing-Ke Shih if (ret) 4559011e2768SPing-Ke Shih return ret; 4560011e2768SPing-Ke Shih 4561e3ec7017SPing-Ke Shih return 0; 4562e3ec7017SPing-Ke Shih } 4563e3ec7017SPing-Ke Shih 4564e3ec7017SPing-Ke Shih int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4565e3ec7017SPing-Ke Shih { 4566e3ec7017SPing-Ke Shih int ret; 4567e3ec7017SPing-Ke Shih 4568ff66964aSPing-Ke Shih ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4569e3ec7017SPing-Ke Shih if (ret) 4570e3ec7017SPing-Ke Shih return ret; 4571e3ec7017SPing-Ke Shih 4572e3ec7017SPing-Ke Shih rtw89_cam_deinit(rtwdev, rtwvif); 4573e3ec7017SPing-Ke Shih 457440822e07SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4575e3ec7017SPing-Ke Shih if (ret) 4576e3ec7017SPing-Ke Shih return ret; 4577e3ec7017SPing-Ke Shih 4578e3ec7017SPing-Ke Shih return 0; 4579e3ec7017SPing-Ke Shih } 4580e3ec7017SPing-Ke Shih 4581e3ec7017SPing-Ke Shih int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4582e3ec7017SPing-Ke Shih { 4583e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 4584e3ec7017SPing-Ke Shih 4585e3ec7017SPing-Ke Shih if (port >= RTW89_PORT_NUM) 4586e3ec7017SPing-Ke Shih return -EINVAL; 4587e3ec7017SPing-Ke Shih 4588e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4589e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4590e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4591e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4592e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4593e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4594f59a98c8SChih-Kang Chang rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif); 4595756b3120SChih-Kang Chang rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif); 4596e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4597283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4598283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4599283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4600e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4601e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4602e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4603e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4604704052f5SChia-Yuan Li rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4605e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4606e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4607d592b9f7SPo-Hao Huang rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4608fb2b8cecSPo-Hao Huang rtw89_mac_port_tsf_resync_all(rtwdev); 4609e3ec7017SPing-Ke Shih fsleep(BCN_ERLY_SET_DLY); 4610e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4611e3ec7017SPing-Ke Shih 4612e3ec7017SPing-Ke Shih return 0; 4613e3ec7017SPing-Ke Shih } 4614e3ec7017SPing-Ke Shih 461576f478a3SZong-Zhe Yang int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 461676f478a3SZong-Zhe Yang u64 *tsf) 461776f478a3SZong-Zhe Yang { 46187c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 46197c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 462076f478a3SZong-Zhe Yang u32 tsf_low, tsf_high; 462176f478a3SZong-Zhe Yang int ret; 462276f478a3SZong-Zhe Yang 462376f478a3SZong-Zhe Yang ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 462476f478a3SZong-Zhe Yang if (ret) 462576f478a3SZong-Zhe Yang return ret; 462676f478a3SZong-Zhe Yang 462776f478a3SZong-Zhe Yang tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 462876f478a3SZong-Zhe Yang tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 462976f478a3SZong-Zhe Yang *tsf = (u64)tsf_high << 32 | tsf_low; 463076f478a3SZong-Zhe Yang 463176f478a3SZong-Zhe Yang return 0; 463276f478a3SZong-Zhe Yang } 463376f478a3SZong-Zhe Yang 46348d540f9dSKuan-Chung Chen static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 46358d540f9dSKuan-Chung Chen struct cfg80211_bss *bss, 46368d540f9dSKuan-Chung Chen void *data) 46378d540f9dSKuan-Chung Chen { 46388d540f9dSKuan-Chung Chen const struct cfg80211_bss_ies *ies; 46398d540f9dSKuan-Chung Chen const struct element *elem; 46408d540f9dSKuan-Chung Chen bool *tolerated = data; 46418d540f9dSKuan-Chung Chen 46428d540f9dSKuan-Chung Chen rcu_read_lock(); 46438d540f9dSKuan-Chung Chen ies = rcu_dereference(bss->ies); 46448d540f9dSKuan-Chung Chen elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 46458d540f9dSKuan-Chung Chen ies->len); 46468d540f9dSKuan-Chung Chen 46478d540f9dSKuan-Chung Chen if (!elem || elem->datalen < 10 || 46488d540f9dSKuan-Chung Chen !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 46498d540f9dSKuan-Chung Chen *tolerated = false; 46508d540f9dSKuan-Chung Chen rcu_read_unlock(); 46518d540f9dSKuan-Chung Chen } 46528d540f9dSKuan-Chung Chen 46538d540f9dSKuan-Chung Chen void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 46548d540f9dSKuan-Chung Chen struct ieee80211_vif *vif) 46558d540f9dSKuan-Chung Chen { 46568d540f9dSKuan-Chung Chen struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 465749ea9823SZong-Zhe Yang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 46588d540f9dSKuan-Chung Chen struct ieee80211_hw *hw = rtwdev->hw; 46598d540f9dSKuan-Chung Chen bool tolerated = true; 46608d540f9dSKuan-Chung Chen u32 reg; 46618d540f9dSKuan-Chung Chen 46628d540f9dSKuan-Chung Chen if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 46638d540f9dSKuan-Chung Chen return; 46648d540f9dSKuan-Chung Chen 46656092077aSJohannes Berg if (!(vif->bss_conf.chanreq.oper.chan->flags & IEEE80211_CHAN_RADAR)) 46668d540f9dSKuan-Chung Chen return; 46678d540f9dSKuan-Chung Chen 46686092077aSJohannes Berg cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chanreq.oper, 46698d540f9dSKuan-Chung Chen rtw89_mac_check_he_obss_narrow_bw_ru_iter, 46708d540f9dSKuan-Chung Chen &tolerated); 46718d540f9dSKuan-Chung Chen 467249ea9823SZong-Zhe Yang reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 467349ea9823SZong-Zhe Yang rtwvif->mac_idx); 46748d540f9dSKuan-Chung Chen if (tolerated) 467549ea9823SZong-Zhe Yang rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 46768d540f9dSKuan-Chung Chen else 467749ea9823SZong-Zhe Yang rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 46788d540f9dSKuan-Chung Chen } 46798d540f9dSKuan-Chung Chen 4680d592b9f7SPo-Hao Huang void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4681d592b9f7SPo-Hao Huang { 46820052b3c4SPo-Hao Huang rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4683d592b9f7SPo-Hao Huang } 4684d592b9f7SPo-Hao Huang 4685e3ec7017SPing-Ke Shih int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4686e3ec7017SPing-Ke Shih { 4687e3ec7017SPing-Ke Shih int ret; 4688e3ec7017SPing-Ke Shih 4689578bdd98SZong-Zhe Yang rtwvif->mac_id = rtw89_acquire_mac_id(rtwdev); 4690e3ec7017SPing-Ke Shih if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4691e3ec7017SPing-Ke Shih return -ENOSPC; 4692e3ec7017SPing-Ke Shih 4693e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4694e3ec7017SPing-Ke Shih if (ret) 4695e3ec7017SPing-Ke Shih goto release_mac_id; 4696e3ec7017SPing-Ke Shih 4697e3ec7017SPing-Ke Shih return 0; 4698e3ec7017SPing-Ke Shih 4699e3ec7017SPing-Ke Shih release_mac_id: 4700578bdd98SZong-Zhe Yang rtw89_release_mac_id(rtwdev, rtwvif->mac_id); 4701e3ec7017SPing-Ke Shih 4702e3ec7017SPing-Ke Shih return ret; 4703e3ec7017SPing-Ke Shih } 4704e3ec7017SPing-Ke Shih 4705e3ec7017SPing-Ke Shih int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4706e3ec7017SPing-Ke Shih { 4707e3ec7017SPing-Ke Shih int ret; 4708e3ec7017SPing-Ke Shih 4709e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4710578bdd98SZong-Zhe Yang rtw89_release_mac_id(rtwdev, rtwvif->mac_id); 4711e3ec7017SPing-Ke Shih 4712e3ec7017SPing-Ke Shih return ret; 4713e3ec7017SPing-Ke Shih } 4714e3ec7017SPing-Ke Shih 4715e3ec7017SPing-Ke Shih static void 4716e3ec7017SPing-Ke Shih rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4717e3ec7017SPing-Ke Shih { 4718e3ec7017SPing-Ke Shih } 4719e3ec7017SPing-Ke Shih 472089590777SPo Hao Huang static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 472189590777SPo Hao Huang { 4722e7399db2SPo-Hao Huang const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 472389590777SPo Hao Huang 4724e7399db2SPo-Hao Huang return band == op->band_type && channel == op->primary_channel; 472589590777SPo Hao Huang } 472689590777SPo Hao Huang 472789590777SPo Hao Huang static void 4728b9979843SPo-Hao Huang rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 472989590777SPo Hao Huang u32 len) 473089590777SPo Hao Huang { 4731b9979843SPo-Hao Huang const struct rtw89_c2h_scanofld *c2h = 4732b9979843SPo-Hao Huang (const struct rtw89_c2h_scanofld *)skb->data; 473389590777SPo Hao Huang struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4734bd1056d4SPo-Hao Huang struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4735cbb145b9SZong-Zhe Yang struct rtw89_chan new; 4736b5d70201SPo-Hao Huang u8 reason, status, tx_fail, band, actual_period, expect_period; 4737b5d70201SPo-Hao Huang u32 last_chan = rtwdev->scan_info.last_chan_idx, report_tsf; 4738b5d70201SPo-Hao Huang u8 mac_idx, sw_def, fw_def; 473989590777SPo Hao Huang u16 chan; 4740bd1056d4SPo-Hao Huang int ret; 474189590777SPo Hao Huang 4742a0e97ae3SPo-Hao Huang if (!rtwvif) 4743a0e97ae3SPo-Hao Huang return; 4744a0e97ae3SPo-Hao Huang 4745b9979843SPo-Hao Huang tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 4746b9979843SPo-Hao Huang status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 4747b9979843SPo-Hao Huang chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 4748b9979843SPo-Hao Huang reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 4749b9979843SPo-Hao Huang band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 4750b9979843SPo-Hao Huang actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 4751b5d70201SPo-Hao Huang mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 4752b5d70201SPo-Hao Huang 475389590777SPo Hao Huang 475489590777SPo Hao Huang if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 475589590777SPo Hao Huang band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 475689590777SPo Hao Huang 475789590777SPo Hao Huang rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4758b5d70201SPo-Hao Huang "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4759b5d70201SPo-Hao Huang mac_idx, band, chan, reason, status, tx_fail, actual_period); 4760b5d70201SPo-Hao Huang 4761b5d70201SPo-Hao Huang if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4762b5d70201SPo-Hao Huang sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 4763b5d70201SPo-Hao Huang expect_period = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 4764b5d70201SPo-Hao Huang fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 4765b5d70201SPo-Hao Huang report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 4766b5d70201SPo-Hao Huang 4767b5d70201SPo-Hao Huang rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4768b5d70201SPo-Hao Huang "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 4769b5d70201SPo-Hao Huang sw_def, fw_def, report_tsf, expect_period); 4770b5d70201SPo-Hao Huang } 477189590777SPo Hao Huang 477289590777SPo Hao Huang switch (reason) { 4773b5d70201SPo-Hao Huang case RTW89_SCAN_LEAVE_OP_NOTIFY: 477489590777SPo Hao Huang case RTW89_SCAN_LEAVE_CH_NOTIFY: 4775756b3120SChih-Kang Chang if (rtw89_is_op_chan(rtwdev, band, chan)) { 4776756b3120SChih-Kang Chang rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, false); 477789590777SPo Hao Huang ieee80211_stop_queues(rtwdev->hw); 4778756b3120SChih-Kang Chang } 477989590777SPo Hao Huang return; 478089590777SPo Hao Huang case RTW89_SCAN_END_SCAN_NOTIFY: 4781669b6922SPo-Hao Huang if (rtwdev->scan_info.abort) 4782669b6922SPo-Hao Huang return; 4783669b6922SPo-Hao Huang 4784bd1056d4SPo-Hao Huang if (rtwvif && rtwvif->scan_req && 4785bd1056d4SPo-Hao Huang last_chan < rtwvif->scan_req->n_channels) { 4786bd1056d4SPo-Hao Huang ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4787bd1056d4SPo-Hao Huang if (ret) { 4788bd1056d4SPo-Hao Huang rtw89_hw_scan_abort(rtwdev, vif); 4789bd1056d4SPo-Hao Huang rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4790bd1056d4SPo-Hao Huang } 4791bd1056d4SPo-Hao Huang } else { 4792669b6922SPo-Hao Huang rtw89_hw_scan_complete(rtwdev, vif, false); 4793bd1056d4SPo-Hao Huang } 479489590777SPo Hao Huang break; 4795b5d70201SPo-Hao Huang case RTW89_SCAN_ENTER_OP_NOTIFY: 479689590777SPo Hao Huang case RTW89_SCAN_ENTER_CH_NOTIFY: 479728000f7bSPo Hao Huang if (rtw89_is_op_chan(rtwdev, band, chan)) { 4798583e998eSZong-Zhe Yang rtw89_assign_entity_chan(rtwdev, rtwvif->chanctx_idx, 4799e7399db2SPo-Hao Huang &rtwdev->scan_info.op_chan); 4800756b3120SChih-Kang Chang rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, true); 480189590777SPo Hao Huang ieee80211_wake_queues(rtwdev->hw); 4802e7399db2SPo-Hao Huang } else { 4803e7399db2SPo-Hao Huang rtw89_chan_create(&new, chan, chan, band, 4804e7399db2SPo-Hao Huang RTW89_CHANNEL_WIDTH_20); 4805583e998eSZong-Zhe Yang rtw89_assign_entity_chan(rtwdev, rtwvif->chanctx_idx, 4806e7399db2SPo-Hao Huang &new); 480728000f7bSPo Hao Huang } 480889590777SPo Hao Huang break; 480989590777SPo Hao Huang default: 481089590777SPo Hao Huang return; 481189590777SPo Hao Huang } 481289590777SPo Hao Huang } 481389590777SPo Hao Huang 4814e3ec7017SPing-Ke Shih static void 4815d2b6da24SPo-Hao Huang rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4816d2b6da24SPo-Hao Huang struct sk_buff *skb) 4817d2b6da24SPo-Hao Huang { 4818d2b6da24SPo-Hao Huang struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4819d2b6da24SPo-Hao Huang enum nl80211_cqm_rssi_threshold_event nl_event; 4820d2b6da24SPo-Hao Huang const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4821d2b6da24SPo-Hao Huang (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4822d2b6da24SPo-Hao Huang u8 type, event, mac_id; 4823d2b6da24SPo-Hao Huang s8 sig; 4824d2b6da24SPo-Hao Huang 4825d2b6da24SPo-Hao Huang type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4826d2b6da24SPo-Hao Huang sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4827d2b6da24SPo-Hao Huang event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4828d2b6da24SPo-Hao Huang mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4829d2b6da24SPo-Hao Huang 4830d2b6da24SPo-Hao Huang if (mac_id != rtwvif->mac_id) 4831d2b6da24SPo-Hao Huang return; 4832d2b6da24SPo-Hao Huang 4833d2b6da24SPo-Hao Huang rtw89_debug(rtwdev, RTW89_DBG_FW, 4834d2b6da24SPo-Hao Huang "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4835d2b6da24SPo-Hao Huang mac_id, type, sig, event); 4836d2b6da24SPo-Hao Huang 4837d2b6da24SPo-Hao Huang switch (type) { 4838d2b6da24SPo-Hao Huang case RTW89_BCN_FLTR_BEACON_LOSS: 4839a0e97ae3SPo-Hao Huang if (!rtwdev->scanning && !rtwvif->offchan) 4840d2b6da24SPo-Hao Huang ieee80211_connection_loss(vif); 4841d2b6da24SPo-Hao Huang else 4842d2b6da24SPo-Hao Huang rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4843d2b6da24SPo-Hao Huang return; 4844d2b6da24SPo-Hao Huang case RTW89_BCN_FLTR_NOTIFY: 4845d2b6da24SPo-Hao Huang nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4846d2b6da24SPo-Hao Huang break; 4847d2b6da24SPo-Hao Huang case RTW89_BCN_FLTR_RSSI: 4848d2b6da24SPo-Hao Huang if (event == RTW89_BCN_FLTR_RSSI_LOW) 4849d2b6da24SPo-Hao Huang nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4850d2b6da24SPo-Hao Huang else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4851d2b6da24SPo-Hao Huang nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4852d2b6da24SPo-Hao Huang else 4853d2b6da24SPo-Hao Huang return; 4854d2b6da24SPo-Hao Huang break; 4855d2b6da24SPo-Hao Huang default: 4856d2b6da24SPo-Hao Huang return; 4857d2b6da24SPo-Hao Huang } 4858d2b6da24SPo-Hao Huang 4859d2b6da24SPo-Hao Huang ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4860d2b6da24SPo-Hao Huang } 4861d2b6da24SPo-Hao Huang 4862d2b6da24SPo-Hao Huang static void 4863d2b6da24SPo-Hao Huang rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4864d2b6da24SPo-Hao Huang u32 len) 4865d2b6da24SPo-Hao Huang { 4866d2b6da24SPo-Hao Huang struct rtw89_vif *rtwvif; 4867d2b6da24SPo-Hao Huang 4868d2b6da24SPo-Hao Huang rtw89_for_each_rtwvif(rtwdev, rtwvif) 4869d2b6da24SPo-Hao Huang rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4870d2b6da24SPo-Hao Huang } 4871d2b6da24SPo-Hao Huang 4872d2b6da24SPo-Hao Huang static void 4873e3ec7017SPing-Ke Shih rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4874e3ec7017SPing-Ke Shih { 487532bb12ebSZong-Zhe Yang /* N.B. This will run in interrupt context. */ 487632bb12ebSZong-Zhe Yang 4877e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 4878e3ec7017SPing-Ke Shih "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4879e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4880e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4881e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4882e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4883e3ec7017SPing-Ke Shih } 4884e3ec7017SPing-Ke Shih 4885e3ec7017SPing-Ke Shih static void 4886b9b632f4SZong-Zhe Yang rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4887e3ec7017SPing-Ke Shih { 488832bb12ebSZong-Zhe Yang /* N.B. This will run in interrupt context. */ 4889b9b632f4SZong-Zhe Yang struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4890b9b632f4SZong-Zhe Yang const struct rtw89_c2h_done_ack *c2h = 4891b9b632f4SZong-Zhe Yang (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4892b9b632f4SZong-Zhe Yang u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4893b9b632f4SZong-Zhe Yang u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4894b9b632f4SZong-Zhe Yang u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4895b9b632f4SZong-Zhe Yang u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4896b9b632f4SZong-Zhe Yang u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4897b9b632f4SZong-Zhe Yang struct rtw89_completion_data data = {}; 4898b9b632f4SZong-Zhe Yang unsigned int cond; 489932bb12ebSZong-Zhe Yang 4900e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 4901e3ec7017SPing-Ke Shih "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4902b9b632f4SZong-Zhe Yang h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4903b9b632f4SZong-Zhe Yang 4904b9b632f4SZong-Zhe Yang if (h2c_cat != H2C_CAT_MAC) 4905b9b632f4SZong-Zhe Yang return; 4906b9b632f4SZong-Zhe Yang 4907b9b632f4SZong-Zhe Yang switch (h2c_class) { 4908b9b632f4SZong-Zhe Yang default: 4909b9b632f4SZong-Zhe Yang return; 4910b9b632f4SZong-Zhe Yang case H2C_CL_MAC_FW_OFLD: 4911b9b632f4SZong-Zhe Yang switch (h2c_func) { 4912b9b632f4SZong-Zhe Yang default: 4913b9b632f4SZong-Zhe Yang return; 4914b9b632f4SZong-Zhe Yang case H2C_FUNC_ADD_SCANOFLD_CH: 4915bcbefbd0SPo-Hao Huang cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 4916bcbefbd0SPo-Hao Huang break; 4917b9b632f4SZong-Zhe Yang case H2C_FUNC_SCANOFLD: 4918bcbefbd0SPo-Hao Huang cond = RTW89_SCANOFLD_WAIT_COND_START; 4919b9b632f4SZong-Zhe Yang break; 49204ba24331SPo-Hao Huang case H2C_FUNC_SCANOFLD_BE: 49214ba24331SPo-Hao Huang cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 49224ba24331SPo-Hao Huang break; 4923b9b632f4SZong-Zhe Yang } 4924b9b632f4SZong-Zhe Yang 4925b9b632f4SZong-Zhe Yang data.err = !!h2c_return; 4926b9b632f4SZong-Zhe Yang rtw89_complete_cond(fw_ofld_wait, cond, &data); 4927b9b632f4SZong-Zhe Yang return; 4928b9b632f4SZong-Zhe Yang } 4929e3ec7017SPing-Ke Shih } 4930e3ec7017SPing-Ke Shih 4931e3ec7017SPing-Ke Shih static void 4932e3ec7017SPing-Ke Shih rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4933e3ec7017SPing-Ke Shih { 4934cad2bd8aSChin-Yen Lee rtw89_fw_log_dump(rtwdev, c2h->data, len); 4935e3ec7017SPing-Ke Shih } 4936e3ec7017SPing-Ke Shih 4937fccca934SPing-Ke Shih static void 4938fccca934SPing-Ke Shih rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4939fccca934SPing-Ke Shih { 4940fccca934SPing-Ke Shih } 4941fccca934SPing-Ke Shih 49422b8219e9SPo Hao Huang static void 49438febd68bSZong-Zhe Yang rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 49442b8219e9SPo Hao Huang u32 len) 49452b8219e9SPo Hao Huang { 49468febd68bSZong-Zhe Yang struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 49478febd68bSZong-Zhe Yang const struct rtw89_c2h_pkt_ofld_rsp *c2h = 49488febd68bSZong-Zhe Yang (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 49498febd68bSZong-Zhe Yang u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 49508febd68bSZong-Zhe Yang u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 49518febd68bSZong-Zhe Yang u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 49528febd68bSZong-Zhe Yang struct rtw89_completion_data data = {}; 49538febd68bSZong-Zhe Yang unsigned int cond; 49548febd68bSZong-Zhe Yang 49558b21c08eSZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 49568b21c08eSZong-Zhe Yang pkt_id, pkt_op, pkt_len); 49578b21c08eSZong-Zhe Yang 49588febd68bSZong-Zhe Yang data.err = !pkt_len; 49598febd68bSZong-Zhe Yang cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 49608febd68bSZong-Zhe Yang 49618febd68bSZong-Zhe Yang rtw89_complete_cond(wait, cond, &data); 49622b8219e9SPo Hao Huang } 49632b8219e9SPo Hao Huang 4964f4a43c3bSDian-Syuan Yang static void 4965f4a43c3bSDian-Syuan Yang rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4966f4a43c3bSDian-Syuan Yang u32 len) 4967f4a43c3bSDian-Syuan Yang { 496897211e02SZong-Zhe Yang rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 4969f4a43c3bSDian-Syuan Yang } 4970f4a43c3bSDian-Syuan Yang 4971ef9dff4cSZong-Zhe Yang static void 4972ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4973ef9dff4cSZong-Zhe Yang { 4974ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4975ef9dff4cSZong-Zhe Yang u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4976ef9dff4cSZong-Zhe Yang 4977ef9dff4cSZong-Zhe Yang switch (func) { 4978ef9dff4cSZong-Zhe Yang case H2C_FUNC_ADD_MCC: 4979ef9dff4cSZong-Zhe Yang case H2C_FUNC_START_MCC: 4980ef9dff4cSZong-Zhe Yang case H2C_FUNC_STOP_MCC: 4981ef9dff4cSZong-Zhe Yang case H2C_FUNC_DEL_MCC_GROUP: 4982ef9dff4cSZong-Zhe Yang case H2C_FUNC_RESET_MCC_GROUP: 4983ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_REQ_TSF: 4984ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_MACID_BITMAP: 4985ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SYNC: 4986ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SET_DURATION: 4987ef9dff4cSZong-Zhe Yang break; 4988ef9dff4cSZong-Zhe Yang default: 4989214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4990ef9dff4cSZong-Zhe Yang "invalid MCC C2H RCV ACK: func %d\n", func); 4991ef9dff4cSZong-Zhe Yang return; 4992ef9dff4cSZong-Zhe Yang } 4993ef9dff4cSZong-Zhe Yang 4994214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4995ef9dff4cSZong-Zhe Yang "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4996ef9dff4cSZong-Zhe Yang } 4997ef9dff4cSZong-Zhe Yang 4998ef9dff4cSZong-Zhe Yang static void 4999ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5000ef9dff4cSZong-Zhe Yang { 5001ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 5002ef9dff4cSZong-Zhe Yang u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 5003ef9dff4cSZong-Zhe Yang u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 5004ef9dff4cSZong-Zhe Yang struct rtw89_completion_data data = {}; 5005ef9dff4cSZong-Zhe Yang unsigned int cond; 5006ef9dff4cSZong-Zhe Yang bool next = false; 5007ef9dff4cSZong-Zhe Yang 5008ef9dff4cSZong-Zhe Yang switch (func) { 5009ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_REQ_TSF: 5010ef9dff4cSZong-Zhe Yang next = true; 5011ef9dff4cSZong-Zhe Yang break; 5012ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_MACID_BITMAP: 5013ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SYNC: 5014ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SET_DURATION: 5015ef9dff4cSZong-Zhe Yang break; 5016ef9dff4cSZong-Zhe Yang case H2C_FUNC_ADD_MCC: 5017ef9dff4cSZong-Zhe Yang case H2C_FUNC_START_MCC: 5018ef9dff4cSZong-Zhe Yang case H2C_FUNC_STOP_MCC: 5019ef9dff4cSZong-Zhe Yang case H2C_FUNC_DEL_MCC_GROUP: 5020ef9dff4cSZong-Zhe Yang case H2C_FUNC_RESET_MCC_GROUP: 5021ef9dff4cSZong-Zhe Yang default: 5022214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5023ef9dff4cSZong-Zhe Yang "invalid MCC C2H REQ ACK: func %d\n", func); 5024ef9dff4cSZong-Zhe Yang return; 5025ef9dff4cSZong-Zhe Yang } 5026ef9dff4cSZong-Zhe Yang 5027214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5028ef9dff4cSZong-Zhe Yang "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5029ef9dff4cSZong-Zhe Yang group, func, retcode); 5030ef9dff4cSZong-Zhe Yang 5031ef9dff4cSZong-Zhe Yang if (!retcode && next) 5032ef9dff4cSZong-Zhe Yang return; 5033ef9dff4cSZong-Zhe Yang 5034ef9dff4cSZong-Zhe Yang data.err = !!retcode; 5035ef9dff4cSZong-Zhe Yang cond = RTW89_MCC_WAIT_COND(group, func); 5036ef9dff4cSZong-Zhe Yang rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5037ef9dff4cSZong-Zhe Yang } 5038ef9dff4cSZong-Zhe Yang 5039ef9dff4cSZong-Zhe Yang static void 5040ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5041ef9dff4cSZong-Zhe Yang { 5042ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5043ef9dff4cSZong-Zhe Yang struct rtw89_completion_data data = {}; 5044ef9dff4cSZong-Zhe Yang struct rtw89_mac_mcc_tsf_rpt *rpt; 5045ef9dff4cSZong-Zhe Yang unsigned int cond; 5046ef9dff4cSZong-Zhe Yang 5047ef9dff4cSZong-Zhe Yang rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5048ef9dff4cSZong-Zhe Yang rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5049ef9dff4cSZong-Zhe Yang rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5050ef9dff4cSZong-Zhe Yang rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5051ef9dff4cSZong-Zhe Yang rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5052ef9dff4cSZong-Zhe Yang rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5053ef9dff4cSZong-Zhe Yang rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5054ef9dff4cSZong-Zhe Yang 5055214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5056214a98b1SZong-Zhe Yang "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5057214a98b1SZong-Zhe Yang rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5058214a98b1SZong-Zhe Yang rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5059214a98b1SZong-Zhe Yang 5060ef9dff4cSZong-Zhe Yang cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5061ef9dff4cSZong-Zhe Yang rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5062ef9dff4cSZong-Zhe Yang } 5063ef9dff4cSZong-Zhe Yang 5064ef9dff4cSZong-Zhe Yang static void 5065ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5066ef9dff4cSZong-Zhe Yang { 5067ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5068ef9dff4cSZong-Zhe Yang u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5069ef9dff4cSZong-Zhe Yang u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5070ef9dff4cSZong-Zhe Yang u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5071ef9dff4cSZong-Zhe Yang u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5072ef9dff4cSZong-Zhe Yang struct rtw89_completion_data data = {}; 5073ef9dff4cSZong-Zhe Yang unsigned int cond; 5074ef9dff4cSZong-Zhe Yang bool rsp = true; 5075ef9dff4cSZong-Zhe Yang bool err; 5076ef9dff4cSZong-Zhe Yang u8 func; 5077ef9dff4cSZong-Zhe Yang 5078ef9dff4cSZong-Zhe Yang switch (status) { 5079ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_ADD_ROLE_OK: 5080ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5081ef9dff4cSZong-Zhe Yang func = H2C_FUNC_ADD_MCC; 5082ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5083ef9dff4cSZong-Zhe Yang break; 5084ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_START_GROUP_OK: 5085ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_START_GROUP_FAIL: 5086ef9dff4cSZong-Zhe Yang func = H2C_FUNC_START_MCC; 5087ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5088ef9dff4cSZong-Zhe Yang break; 5089ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_STOP_GROUP_OK: 5090ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5091ef9dff4cSZong-Zhe Yang func = H2C_FUNC_STOP_MCC; 5092ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5093ef9dff4cSZong-Zhe Yang break; 5094ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DEL_GROUP_OK: 5095ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5096ef9dff4cSZong-Zhe Yang func = H2C_FUNC_DEL_MCC_GROUP; 5097ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5098ef9dff4cSZong-Zhe Yang break; 5099ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_RESET_GROUP_OK: 5100ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5101ef9dff4cSZong-Zhe Yang func = H2C_FUNC_RESET_MCC_GROUP; 5102ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5103ef9dff4cSZong-Zhe Yang break; 5104ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_SWITCH_CH_OK: 5105ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5106ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL0_OK: 5107ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL0_FAIL: 5108ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL1_OK: 5109ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL1_FAIL: 5110ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_SWITCH_EARLY: 5111ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TBTT: 5112ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DURATION_START: 5113ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DURATION_END: 5114ef9dff4cSZong-Zhe Yang rsp = false; 5115ef9dff4cSZong-Zhe Yang break; 5116ef9dff4cSZong-Zhe Yang default: 5117214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5118ef9dff4cSZong-Zhe Yang "invalid MCC C2H STS RPT: status %d\n", status); 5119ef9dff4cSZong-Zhe Yang return; 5120ef9dff4cSZong-Zhe Yang } 5121ef9dff4cSZong-Zhe Yang 5122214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5123214a98b1SZong-Zhe Yang "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5124214a98b1SZong-Zhe Yang group, macid, status, (u64)tsf_high << 32 | tsf_low); 5125ef9dff4cSZong-Zhe Yang 5126ef9dff4cSZong-Zhe Yang if (!rsp) 5127ef9dff4cSZong-Zhe Yang return; 5128ef9dff4cSZong-Zhe Yang 5129ef9dff4cSZong-Zhe Yang data.err = err; 5130ef9dff4cSZong-Zhe Yang cond = RTW89_MCC_WAIT_COND(group, func); 5131ef9dff4cSZong-Zhe Yang rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5132ef9dff4cSZong-Zhe Yang } 5133ef9dff4cSZong-Zhe Yang 5134b8e59e55SZong-Zhe Yang static void 5135b8e59e55SZong-Zhe Yang rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5136b8e59e55SZong-Zhe Yang { 5137b8e59e55SZong-Zhe Yang struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5138b8e59e55SZong-Zhe Yang const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5139b8e59e55SZong-Zhe Yang struct rtw89_completion_data data = {}; 5140b8e59e55SZong-Zhe Yang struct rtw89_mac_mrc_tsf_rpt *rpt; 5141b8e59e55SZong-Zhe Yang unsigned int i; 5142b8e59e55SZong-Zhe Yang 5143b8e59e55SZong-Zhe Yang c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5144b8e59e55SZong-Zhe Yang rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5145b8e59e55SZong-Zhe Yang rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5146b8e59e55SZong-Zhe Yang le32_get_bits(c2h_rpt->w2, 5147b8e59e55SZong-Zhe Yang RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5148b8e59e55SZong-Zhe Yang 5149b8e59e55SZong-Zhe Yang for (i = 0; i < rpt->num; i++) { 5150b8e59e55SZong-Zhe Yang u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5151b8e59e55SZong-Zhe Yang u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5152b8e59e55SZong-Zhe Yang 5153b8e59e55SZong-Zhe Yang rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5154b8e59e55SZong-Zhe Yang 5155b8e59e55SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5156b8e59e55SZong-Zhe Yang "MRC C2H TSF RPT: index %u> %llu\n", 5157b8e59e55SZong-Zhe Yang i, rpt->tsfs[i]); 5158b8e59e55SZong-Zhe Yang } 5159b8e59e55SZong-Zhe Yang 5160b8e59e55SZong-Zhe Yang rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5161b8e59e55SZong-Zhe Yang } 5162b8e59e55SZong-Zhe Yang 5163b8e59e55SZong-Zhe Yang static void 5164ff53fce5SChih-Kang Chang rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5165ff53fce5SChih-Kang Chang { 5166ff53fce5SChih-Kang Chang struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 5167ff53fce5SChih-Kang Chang struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 5168*d9dd3ac7SZong-Zhe Yang struct rtw89_wait_info *wait = &rtw_wow->wait; 5169ff53fce5SChih-Kang Chang const struct rtw89_c2h_wow_aoac_report *c2h = 5170ff53fce5SChih-Kang Chang (const struct rtw89_c2h_wow_aoac_report *)skb->data; 5171ff53fce5SChih-Kang Chang struct rtw89_completion_data data = {}; 5172ff53fce5SChih-Kang Chang 5173ff53fce5SChih-Kang Chang aoac_rpt->rpt_ver = c2h->rpt_ver; 5174ff53fce5SChih-Kang Chang aoac_rpt->sec_type = c2h->sec_type; 5175ff53fce5SChih-Kang Chang aoac_rpt->key_idx = c2h->key_idx; 5176ff53fce5SChih-Kang Chang aoac_rpt->pattern_idx = c2h->pattern_idx; 5177ff53fce5SChih-Kang Chang aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok, 5178ff53fce5SChih-Kang Chang RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX); 5179ff53fce5SChih-Kang Chang memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv)); 5180ff53fce5SChih-Kang Chang memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count, 5181ff53fce5SChih-Kang Chang sizeof(aoac_rpt->eapol_key_replay_count)); 5182ff53fce5SChih-Kang Chang memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk)); 5183ff53fce5SChih-Kang Chang memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv)); 5184ff53fce5SChih-Kang Chang memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv)); 5185940cd996SChih-Kang Chang aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id); 5186940cd996SChih-Kang Chang aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn); 5187940cd996SChih-Kang Chang memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk)); 5188ff53fce5SChih-Kang Chang 5189*d9dd3ac7SZong-Zhe Yang rtw89_complete_cond(wait, RTW89_WOW_WAIT_COND_AOAC, &data); 5190ff53fce5SChih-Kang Chang } 5191ff53fce5SChih-Kang Chang 5192ff53fce5SChih-Kang Chang static void 5193b8e59e55SZong-Zhe Yang rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5194b8e59e55SZong-Zhe Yang { 5195b8e59e55SZong-Zhe Yang struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5196b8e59e55SZong-Zhe Yang const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5197b8e59e55SZong-Zhe Yang struct rtw89_completion_data data = {}; 5198b8e59e55SZong-Zhe Yang enum rtw89_mac_mrc_status status; 5199b8e59e55SZong-Zhe Yang unsigned int cond; 5200b8e59e55SZong-Zhe Yang bool next = false; 5201b8e59e55SZong-Zhe Yang u32 tsf_high; 5202b8e59e55SZong-Zhe Yang u32 tsf_low; 5203b8e59e55SZong-Zhe Yang u8 sch_idx; 5204b8e59e55SZong-Zhe Yang u8 func; 5205b8e59e55SZong-Zhe Yang 5206b8e59e55SZong-Zhe Yang c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5207b8e59e55SZong-Zhe Yang sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5208b8e59e55SZong-Zhe Yang status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5209b8e59e55SZong-Zhe Yang tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5210b8e59e55SZong-Zhe Yang tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5211b8e59e55SZong-Zhe Yang 5212b8e59e55SZong-Zhe Yang switch (status) { 5213b8e59e55SZong-Zhe Yang case RTW89_MAC_MRC_START_SCH_OK: 5214b8e59e55SZong-Zhe Yang func = H2C_FUNC_START_MRC; 5215b8e59e55SZong-Zhe Yang break; 5216b8e59e55SZong-Zhe Yang case RTW89_MAC_MRC_STOP_SCH_OK: 5217b8e59e55SZong-Zhe Yang /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5218b8e59e55SZong-Zhe Yang func = H2C_FUNC_DEL_MRC; 5219b8e59e55SZong-Zhe Yang next = true; 5220b8e59e55SZong-Zhe Yang break; 5221b8e59e55SZong-Zhe Yang case RTW89_MAC_MRC_DEL_SCH_OK: 5222b8e59e55SZong-Zhe Yang func = H2C_FUNC_DEL_MRC; 5223b8e59e55SZong-Zhe Yang break; 52241e71be6aSZong-Zhe Yang case RTW89_MAC_MRC_EMPTY_SCH_FAIL: 52251e71be6aSZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 52261e71be6aSZong-Zhe Yang "MRC C2H STS RPT: empty sch fail\n"); 52271e71be6aSZong-Zhe Yang return; 52281e71be6aSZong-Zhe Yang case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL: 52291e71be6aSZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 52301e71be6aSZong-Zhe Yang "MRC C2H STS RPT: role not exist fail\n"); 52311e71be6aSZong-Zhe Yang return; 52321e71be6aSZong-Zhe Yang case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL: 52331e71be6aSZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 52341e71be6aSZong-Zhe Yang "MRC C2H STS RPT: data not found fail\n"); 52351e71be6aSZong-Zhe Yang return; 52361e71be6aSZong-Zhe Yang case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL: 52371e71be6aSZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 52381e71be6aSZong-Zhe Yang "MRC C2H STS RPT: get next slot fail\n"); 52391e71be6aSZong-Zhe Yang return; 52401e71be6aSZong-Zhe Yang case RTW89_MAC_MRC_ALT_ROLE_FAIL: 52411e71be6aSZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 52421e71be6aSZong-Zhe Yang "MRC C2H STS RPT: alt role fail\n"); 52431e71be6aSZong-Zhe Yang return; 52441e71be6aSZong-Zhe Yang case RTW89_MAC_MRC_ADD_PSTIMER_FAIL: 52451e71be6aSZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 52461e71be6aSZong-Zhe Yang "MRC C2H STS RPT: add ps timer fail\n"); 52471e71be6aSZong-Zhe Yang return; 52481e71be6aSZong-Zhe Yang case RTW89_MAC_MRC_MALLOC_FAIL: 52491e71be6aSZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 52501e71be6aSZong-Zhe Yang "MRC C2H STS RPT: malloc fail\n"); 52511e71be6aSZong-Zhe Yang return; 52521e71be6aSZong-Zhe Yang case RTW89_MAC_MRC_SWITCH_CH_FAIL: 52531e71be6aSZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 52541e71be6aSZong-Zhe Yang "MRC C2H STS RPT: switch ch fail\n"); 52551e71be6aSZong-Zhe Yang return; 52561e71be6aSZong-Zhe Yang case RTW89_MAC_MRC_TXNULL0_FAIL: 52571e71be6aSZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 52581e71be6aSZong-Zhe Yang "MRC C2H STS RPT: tx null-0 fail\n"); 52591e71be6aSZong-Zhe Yang return; 52601e71be6aSZong-Zhe Yang case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL: 52611e71be6aSZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 52621e71be6aSZong-Zhe Yang "MRC C2H STS RPT: port func en fail\n"); 52631e71be6aSZong-Zhe Yang return; 5264b8e59e55SZong-Zhe Yang default: 5265b8e59e55SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5266b8e59e55SZong-Zhe Yang "invalid MRC C2H STS RPT: status %d\n", status); 5267b8e59e55SZong-Zhe Yang return; 5268b8e59e55SZong-Zhe Yang } 5269b8e59e55SZong-Zhe Yang 5270b8e59e55SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5271b8e59e55SZong-Zhe Yang "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 5272b8e59e55SZong-Zhe Yang sch_idx, status, (u64)tsf_high << 32 | tsf_low); 5273b8e59e55SZong-Zhe Yang 5274b8e59e55SZong-Zhe Yang if (next) 5275b8e59e55SZong-Zhe Yang return; 5276b8e59e55SZong-Zhe Yang 5277b8e59e55SZong-Zhe Yang cond = RTW89_MRC_WAIT_COND(sch_idx, func); 5278b8e59e55SZong-Zhe Yang rtw89_complete_cond(wait, cond, &data); 5279b8e59e55SZong-Zhe Yang } 5280b8e59e55SZong-Zhe Yang 5281e3ec7017SPing-Ke Shih static 5282e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5283e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 5284e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5285e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 52862b8219e9SPo Hao Huang [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5287e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 5288e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 528989590777SPo Hao Huang [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5290f4a43c3bSDian-Syuan Yang [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5291d2b6da24SPo-Hao Huang [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5292e3ec7017SPing-Ke Shih }; 5293e3ec7017SPing-Ke Shih 5294e3ec7017SPing-Ke Shih static 5295e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5296e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 5297e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5298e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5299e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5300fccca934SPing-Ke Shih [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5301e3ec7017SPing-Ke Shih }; 5302e3ec7017SPing-Ke Shih 5303ef9dff4cSZong-Zhe Yang static 5304ef9dff4cSZong-Zhe Yang void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5305ef9dff4cSZong-Zhe Yang struct sk_buff *c2h, u32 len) = { 5306ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5307ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5308ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5309ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5310ef9dff4cSZong-Zhe Yang }; 5311ef9dff4cSZong-Zhe Yang 5312b8e59e55SZong-Zhe Yang static 5313b8e59e55SZong-Zhe Yang void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 5314b8e59e55SZong-Zhe Yang struct sk_buff *c2h, u32 len) = { 5315b8e59e55SZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 5316b8e59e55SZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 5317b8e59e55SZong-Zhe Yang }; 5318b8e59e55SZong-Zhe Yang 5319ff53fce5SChih-Kang Chang static 5320ff53fce5SChih-Kang Chang void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev, 5321ff53fce5SChih-Kang Chang struct sk_buff *c2h, u32 len) = { 5322ff53fce5SChih-Kang Chang [RTW89_MAC_C2H_FUNC_AOAC_REPORT] = rtw89_mac_c2h_wow_aoac_rpt, 5323ff53fce5SChih-Kang Chang }; 5324ff53fce5SChih-Kang Chang 5325bcbefbd0SPo-Hao Huang static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 5326bcbefbd0SPo-Hao Huang struct sk_buff *skb) 5327bcbefbd0SPo-Hao Huang { 5328bcbefbd0SPo-Hao Huang const struct rtw89_c2h_scanofld *c2h = 5329bcbefbd0SPo-Hao Huang (const struct rtw89_c2h_scanofld *)skb->data; 5330bcbefbd0SPo-Hao Huang struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5331bcbefbd0SPo-Hao Huang struct rtw89_completion_data data = {}; 53324ba24331SPo-Hao Huang unsigned int cond; 5333bcbefbd0SPo-Hao Huang u8 status, reason; 5334bcbefbd0SPo-Hao Huang 5335bcbefbd0SPo-Hao Huang status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5336bcbefbd0SPo-Hao Huang reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5337bcbefbd0SPo-Hao Huang data.err = status != RTW89_SCAN_STATUS_SUCCESS; 5338bcbefbd0SPo-Hao Huang 53394ba24331SPo-Hao Huang if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 53404ba24331SPo-Hao Huang if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 53414ba24331SPo-Hao Huang cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 53424ba24331SPo-Hao Huang else 53434ba24331SPo-Hao Huang cond = RTW89_SCANOFLD_WAIT_COND_STOP; 53444ba24331SPo-Hao Huang 53454ba24331SPo-Hao Huang rtw89_complete_cond(fw_ofld_wait, cond, &data); 53464ba24331SPo-Hao Huang } 5347bcbefbd0SPo-Hao Huang } 5348bcbefbd0SPo-Hao Huang 5349bcbefbd0SPo-Hao Huang bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5350bcbefbd0SPo-Hao Huang u8 class, u8 func) 5351860e8263SZong-Zhe Yang { 5352860e8263SZong-Zhe Yang switch (class) { 5353860e8263SZong-Zhe Yang default: 5354860e8263SZong-Zhe Yang return false; 535532bb12ebSZong-Zhe Yang case RTW89_MAC_C2H_CLASS_INFO: 535632bb12ebSZong-Zhe Yang switch (func) { 535732bb12ebSZong-Zhe Yang default: 535832bb12ebSZong-Zhe Yang return false; 535932bb12ebSZong-Zhe Yang case RTW89_MAC_C2H_FUNC_REC_ACK: 536032bb12ebSZong-Zhe Yang case RTW89_MAC_C2H_FUNC_DONE_ACK: 536132bb12ebSZong-Zhe Yang return true; 536232bb12ebSZong-Zhe Yang } 53638febd68bSZong-Zhe Yang case RTW89_MAC_C2H_CLASS_OFLD: 53648febd68bSZong-Zhe Yang switch (func) { 53658febd68bSZong-Zhe Yang default: 53668febd68bSZong-Zhe Yang return false; 5367bcbefbd0SPo-Hao Huang case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 5368bcbefbd0SPo-Hao Huang rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 5369bcbefbd0SPo-Hao Huang return false; 53708febd68bSZong-Zhe Yang case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 53718febd68bSZong-Zhe Yang return true; 53728febd68bSZong-Zhe Yang } 5373860e8263SZong-Zhe Yang case RTW89_MAC_C2H_CLASS_MCC: 5374860e8263SZong-Zhe Yang return true; 5375b8e59e55SZong-Zhe Yang case RTW89_MAC_C2H_CLASS_MRC: 5376b8e59e55SZong-Zhe Yang return true; 5377ff53fce5SChih-Kang Chang case RTW89_MAC_C2H_CLASS_WOW: 5378ff53fce5SChih-Kang Chang return true; 5379860e8263SZong-Zhe Yang } 5380860e8263SZong-Zhe Yang } 5381860e8263SZong-Zhe Yang 5382e3ec7017SPing-Ke Shih void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5383e3ec7017SPing-Ke Shih u32 len, u8 class, u8 func) 5384e3ec7017SPing-Ke Shih { 5385e3ec7017SPing-Ke Shih void (*handler)(struct rtw89_dev *rtwdev, 5386e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = NULL; 5387e3ec7017SPing-Ke Shih 5388e3ec7017SPing-Ke Shih switch (class) { 5389e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_INFO: 5390e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 5391e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_info_handler[func]; 5392e3ec7017SPing-Ke Shih break; 5393e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_OFLD: 5394e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 5395e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_ofld_handler[func]; 5396e3ec7017SPing-Ke Shih break; 5397ef9dff4cSZong-Zhe Yang case RTW89_MAC_C2H_CLASS_MCC: 5398ef9dff4cSZong-Zhe Yang if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 5399ef9dff4cSZong-Zhe Yang handler = rtw89_mac_c2h_mcc_handler[func]; 5400ef9dff4cSZong-Zhe Yang break; 5401b8e59e55SZong-Zhe Yang case RTW89_MAC_C2H_CLASS_MRC: 5402b8e59e55SZong-Zhe Yang if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 5403b8e59e55SZong-Zhe Yang handler = rtw89_mac_c2h_mrc_handler[func]; 5404b8e59e55SZong-Zhe Yang break; 5405ff53fce5SChih-Kang Chang case RTW89_MAC_C2H_CLASS_WOW: 5406ff53fce5SChih-Kang Chang if (func < NUM_OF_RTW89_MAC_C2H_FUNC_WOW) 5407ff53fce5SChih-Kang Chang handler = rtw89_mac_c2h_wow_handler[func]; 5408ff53fce5SChih-Kang Chang break; 5409e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_FWDBG: 5410e3ec7017SPing-Ke Shih return; 5411e3ec7017SPing-Ke Shih default: 5412e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d not support\n", class); 5413e3ec7017SPing-Ke Shih return; 5414e3ec7017SPing-Ke Shih } 5415e3ec7017SPing-Ke Shih if (!handler) { 5416e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 5417e3ec7017SPing-Ke Shih func); 5418e3ec7017SPing-Ke Shih return; 5419e3ec7017SPing-Ke Shih } 5420e3ec7017SPing-Ke Shih handler(rtwdev, skb, len); 5421e3ec7017SPing-Ke Shih } 5422e3ec7017SPing-Ke Shih 542306b26738SZong-Zhe Yang static 542406b26738SZong-Zhe Yang bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 5425e3ec7017SPing-Ke Shih enum rtw89_phy_idx phy_idx, 5426e3ec7017SPing-Ke Shih u32 reg_base, u32 *cr) 5427e3ec7017SPing-Ke Shih { 54285f9c264fSPo-Hao Huang enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 5429c220d08eSPing-Ke Shih u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 5430e3ec7017SPing-Ke Shih 543106b26738SZong-Zhe Yang if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 5432e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 5433e3ec7017SPing-Ke Shih addr); 5434e3ec7017SPing-Ke Shih goto error; 5435e3ec7017SPing-Ke Shih } 5436e3ec7017SPing-Ke Shih 543706b26738SZong-Zhe Yang if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 5438e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_SCC) { 5439e3ec7017SPing-Ke Shih rtw89_err(rtwdev, 5440e3ec7017SPing-Ke Shih "[TXPWR] addr=0x%x but hw not enable\n", 5441e3ec7017SPing-Ke Shih addr); 5442e3ec7017SPing-Ke Shih goto error; 5443e3ec7017SPing-Ke Shih } 5444e3ec7017SPing-Ke Shih 5445e3ec7017SPing-Ke Shih *cr = addr; 5446e3ec7017SPing-Ke Shih return true; 5447e3ec7017SPing-Ke Shih 5448e3ec7017SPing-Ke Shih error: 5449e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 5450e3ec7017SPing-Ke Shih addr, phy_idx); 5451e3ec7017SPing-Ke Shih 5452e3ec7017SPing-Ke Shih return false; 5453e3ec7017SPing-Ke Shih } 5454e3ec7017SPing-Ke Shih 5455b16daa62SPing-Ke Shih static 5456b16daa62SPing-Ke Shih int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 5457e3ec7017SPing-Ke Shih { 5458c220d08eSPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 545921087188SPing-Ke Shih int ret; 5460e3ec7017SPing-Ke Shih 5461e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5462e3ec7017SPing-Ke Shih if (ret) 5463e3ec7017SPing-Ke Shih return ret; 5464e3ec7017SPing-Ke Shih 5465e3ec7017SPing-Ke Shih if (!enable) { 5466e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 546721087188SPing-Ke Shih return 0; 5468e3ec7017SPing-Ke Shih } 5469e3ec7017SPing-Ke Shih 5470e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 5471e3ec7017SPing-Ke Shih B_AX_APP_MAC_INFO_RPT | 5472e3ec7017SPing-Ke Shih B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 5473e3ec7017SPing-Ke Shih B_AX_PPDU_STAT_RPT_CRC32); 5474e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 5475e3ec7017SPing-Ke Shih RTW89_PRPT_DEST_HOST); 5476e3ec7017SPing-Ke Shih 547721087188SPing-Ke Shih return 0; 5478e3ec7017SPing-Ke Shih } 5479e3ec7017SPing-Ke Shih 5480e3ec7017SPing-Ke Shih void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 5481e3ec7017SPing-Ke Shih { 5482e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_SH 5 5483e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_SH 4 5484e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_MAX 255 5485e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_MAX 255 5486e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_DEF 88 5487e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_DEF 4080 5488fbd1829dSZong-Zhe Yang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5489e3ec7017SPing-Ke Shih struct ieee80211_hw *hw = rtwdev->hw; 5490e3ec7017SPing-Ke Shih u32 rts_threshold = hw->wiphy->rts_threshold; 5491e3ec7017SPing-Ke Shih u32 time_th, len_th; 5492e3ec7017SPing-Ke Shih u32 reg; 5493e3ec7017SPing-Ke Shih 5494e3ec7017SPing-Ke Shih if (rts_threshold == (u32)-1) { 5495e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_DEF; 5496e3ec7017SPing-Ke Shih len_th = MAC_AX_LEN_TH_DEF; 5497e3ec7017SPing-Ke Shih } else { 5498e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 5499e3ec7017SPing-Ke Shih len_th = rts_threshold; 5500e3ec7017SPing-Ke Shih } 5501e3ec7017SPing-Ke Shih 5502e3ec7017SPing-Ke Shih time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 5503e3ec7017SPing-Ke Shih len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 5504e3ec7017SPing-Ke Shih 5505fbd1829dSZong-Zhe Yang reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 5506e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 5507e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 5508e3ec7017SPing-Ke Shih } 5509e3ec7017SPing-Ke Shih 5510e3ec7017SPing-Ke Shih void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 5511e3ec7017SPing-Ke Shih { 5512e3ec7017SPing-Ke Shih bool empty; 5513e3ec7017SPing-Ke Shih int ret; 5514e3ec7017SPing-Ke Shih 5515e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5516e3ec7017SPing-Ke Shih return; 5517e3ec7017SPing-Ke Shih 5518e3ec7017SPing-Ke Shih ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 5519e3ec7017SPing-Ke Shih 10000, 200000, false, rtwdev); 5520e3ec7017SPing-Ke Shih if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 5521e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "timed out to flush queues\n"); 5522e3ec7017SPing-Ke Shih } 5523e3ec7017SPing-Ke Shih 5524e3ec7017SPing-Ke Shih int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 5525e3ec7017SPing-Ke Shih { 5526190dc12dSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 5527e3ec7017SPing-Ke Shih u8 val; 5528e3ec7017SPing-Ke Shih u16 val16; 5529e3ec7017SPing-Ke Shih u32 val32; 5530e3ec7017SPing-Ke Shih int ret; 5531e3ec7017SPing-Ke Shih 5532e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 5533190dc12dSPing-Ke Shih if (chip_id != RTL8851B && chip_id != RTL8852BT) 5534e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 5535e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 5536e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 5537e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 5538190dc12dSPing-Ke Shih if (chip_id != RTL8851B && chip_id != RTL8852BT) 5539e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 5540e3ec7017SPing-Ke Shih 5541e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 5542e3ec7017SPing-Ke Shih val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 5543e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 5544e3ec7017SPing-Ke Shih 5545e3ec7017SPing-Ke Shih ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 5546e3ec7017SPing-Ke Shih if (ret) { 5547e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 5548e3ec7017SPing-Ke Shih return ret; 5549e3ec7017SPing-Ke Shih } 5550e3ec7017SPing-Ke Shih val32 = val32 & B_AX_WL_RX_CTRL; 5551e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 5552e3ec7017SPing-Ke Shih if (ret) { 5553e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 5554e3ec7017SPing-Ke Shih return ret; 5555e3ec7017SPing-Ke Shih } 5556e3ec7017SPing-Ke Shih 5557e3ec7017SPing-Ke Shih switch (coex->pta_mode) { 5558e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_RTK_MODE: 5559e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5560e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 5561e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 5562e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5563e3ec7017SPing-Ke Shih 5564e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 5565e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 5566e3ec7017SPing-Ke Shih 5567e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 5568e3ec7017SPing-Ke Shih val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 5569e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 5570e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 5571e3ec7017SPing-Ke Shih break; 5572e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_CSR_MODE: 5573e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5574e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 5575e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 5576e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5577e3ec7017SPing-Ke Shih 5578e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 5579e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 5580e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 5581e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 5582e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 5583e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_STAT_DELAY_MASK; 5584e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 5585e3ec7017SPing-Ke Shih val16 |= B_AX_ENHANCED_BT; 5586e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 5587e3ec7017SPing-Ke Shih 5588e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 5589e3ec7017SPing-Ke Shih break; 5590e3ec7017SPing-Ke Shih default: 5591e3ec7017SPing-Ke Shih return -EINVAL; 5592e3ec7017SPing-Ke Shih } 5593e3ec7017SPing-Ke Shih 5594e3ec7017SPing-Ke Shih switch (coex->direction) { 5595e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INNER: 5596e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5597e3ec7017SPing-Ke Shih val = (val & ~BIT(2)) | BIT(1); 5598e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5599e3ec7017SPing-Ke Shih break; 5600e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_OUTPUT: 5601e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5602e3ec7017SPing-Ke Shih val = val | BIT(1) | BIT(0); 5603e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5604e3ec7017SPing-Ke Shih break; 5605e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INPUT: 5606e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5607e3ec7017SPing-Ke Shih val = val & ~(BIT(2) | BIT(1)); 5608e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5609e3ec7017SPing-Ke Shih break; 5610e3ec7017SPing-Ke Shih default: 5611e3ec7017SPing-Ke Shih return -EINVAL; 5612e3ec7017SPing-Ke Shih } 5613e3ec7017SPing-Ke Shih 5614e3ec7017SPing-Ke Shih return 0; 5615e3ec7017SPing-Ke Shih } 5616861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_coex_init); 5617e3ec7017SPing-Ke Shih 5618065cf8f9SChia-Yuan Li int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 5619065cf8f9SChia-Yuan Li const struct rtw89_mac_ax_coex *coex) 5620065cf8f9SChia-Yuan Li { 5621065cf8f9SChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 5622065cf8f9SChia-Yuan Li B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 5623065cf8f9SChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 5624065cf8f9SChia-Yuan Li rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 5625065cf8f9SChia-Yuan Li rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 5626065cf8f9SChia-Yuan Li 5627065cf8f9SChia-Yuan Li switch (coex->pta_mode) { 5628065cf8f9SChia-Yuan Li case RTW89_MAC_AX_COEX_RTK_MODE: 5629065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5630065cf8f9SChia-Yuan Li MAC_AX_RTK_MODE); 5631065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 5632065cf8f9SChia-Yuan Li B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 5633065cf8f9SChia-Yuan Li break; 5634065cf8f9SChia-Yuan Li case RTW89_MAC_AX_COEX_CSR_MODE: 5635065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5636065cf8f9SChia-Yuan Li MAC_AX_CSR_MODE); 5637065cf8f9SChia-Yuan Li break; 5638065cf8f9SChia-Yuan Li default: 5639065cf8f9SChia-Yuan Li return -EINVAL; 5640065cf8f9SChia-Yuan Li } 5641065cf8f9SChia-Yuan Li 5642065cf8f9SChia-Yuan Li return 0; 5643065cf8f9SChia-Yuan Li } 5644065cf8f9SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 5645065cf8f9SChia-Yuan Li 5646e3ec7017SPing-Ke Shih int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5647e3ec7017SPing-Ke Shih const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5648e3ec7017SPing-Ke Shih { 56498001c741SPing-Ke Shih u32 val = 0, ret; 5650e3ec7017SPing-Ke Shih 56518001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_bt) 56528001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 56538001c741SPing-Ke Shih 56548001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_bt_sw_en) 56558001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 56568001c741SPing-Ke Shih 56578001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_wl) 56588001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 56598001c741SPing-Ke Shih 56608001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_wl_sw_en) 56618001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 56628001c741SPing-Ke Shih 56638001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_bt) 56648001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 56658001c741SPing-Ke Shih 56668001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_bt_sw_en) 56678001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 56688001c741SPing-Ke Shih 56698001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_wl) 56708001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 56718001c741SPing-Ke Shih 56728001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_wl_sw_en) 56738001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 56748001c741SPing-Ke Shih 5675e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 5676e3ec7017SPing-Ke Shih if (ret) { 5677e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write LTE fail!\n"); 5678e3ec7017SPing-Ke Shih return ret; 5679e3ec7017SPing-Ke Shih } 5680e3ec7017SPing-Ke Shih 5681e3ec7017SPing-Ke Shih return 0; 5682e3ec7017SPing-Ke Shih } 5683feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 5684feed6541SChia-Yuan Li 5685feed6541SChia-Yuan Li int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 5686feed6541SChia-Yuan Li const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5687feed6541SChia-Yuan Li { 5688feed6541SChia-Yuan Li u32 val = 0; 5689feed6541SChia-Yuan Li 5690feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_bt) 5691feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5692feed6541SChia-Yuan Li B_AX_GNT_BT_TX_VAL; 5693feed6541SChia-Yuan Li else 5694feed6541SChia-Yuan Li val |= B_AX_WL_ACT_VAL; 5695feed6541SChia-Yuan Li 5696feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_bt_sw_en) 5697feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5698feed6541SChia-Yuan Li B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5699feed6541SChia-Yuan Li 5700feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_wl) 5701feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5702feed6541SChia-Yuan Li B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5703feed6541SChia-Yuan Li 5704feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_wl_sw_en) 5705feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5706feed6541SChia-Yuan Li B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5707feed6541SChia-Yuan Li 5708feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_bt) 5709feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5710feed6541SChia-Yuan Li B_AX_GNT_BT_TX_VAL; 5711feed6541SChia-Yuan Li else 5712feed6541SChia-Yuan Li val |= B_AX_WL_ACT_VAL; 5713feed6541SChia-Yuan Li 5714feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_bt_sw_en) 5715feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5716feed6541SChia-Yuan Li B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5717feed6541SChia-Yuan Li 5718feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_wl) 5719feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5720feed6541SChia-Yuan Li B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5721feed6541SChia-Yuan Li 5722feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_wl_sw_en) 5723feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5724feed6541SChia-Yuan Li B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5725feed6541SChia-Yuan Li 5726feed6541SChia-Yuan Li rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5727feed6541SChia-Yuan Li 5728feed6541SChia-Yuan Li return 0; 5729feed6541SChia-Yuan Li } 5730feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5731e3ec7017SPing-Ke Shih 57320cb01e0eSPing-Ke Shih static 57330cb01e0eSPing-Ke Shih int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5734e3ec7017SPing-Ke Shih { 5735e3ec7017SPing-Ke Shih u32 reg; 573628e7ea8aSPing-Ke Shih u16 val; 5737e3ec7017SPing-Ke Shih int ret; 5738e3ec7017SPing-Ke Shih 5739e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5740e3ec7017SPing-Ke Shih if (ret) 5741e3ec7017SPing-Ke Shih return ret; 5742e3ec7017SPing-Ke Shih 5743c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 5744e3ec7017SPing-Ke Shih val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5745e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5746e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5747e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5748e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5749e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5750e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 575128e7ea8aSPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 575228e7ea8aSPing-Ke Shih B_AX_PLT_EN; 575328e7ea8aSPing-Ke Shih rtw89_write16(rtwdev, reg, val); 5754e3ec7017SPing-Ke Shih 5755e3ec7017SPing-Ke Shih return 0; 5756e3ec7017SPing-Ke Shih } 5757e3ec7017SPing-Ke Shih 5758e3ec7017SPing-Ke Shih void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5759e3ec7017SPing-Ke Shih { 5760e3ec7017SPing-Ke Shih u32 fw_sb; 5761e3ec7017SPing-Ke Shih 5762e3ec7017SPing-Ke Shih fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5763e3ec7017SPing-Ke Shih fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5764e3ec7017SPing-Ke Shih fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5765e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5766e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5767e3ec7017SPing-Ke Shih else 5768e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5769e3ec7017SPing-Ke Shih val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5770e3ec7017SPing-Ke Shih val = B_AX_TOGGLE | 5771e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5772e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5773e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5774e3ec7017SPing-Ke Shih fsleep(1000); /* avoid BT FW loss information */ 5775e3ec7017SPing-Ke Shih } 5776e3ec7017SPing-Ke Shih 5777e3ec7017SPing-Ke Shih u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5778e3ec7017SPing-Ke Shih { 5779e3ec7017SPing-Ke Shih return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5780e3ec7017SPing-Ke Shih } 5781e3ec7017SPing-Ke Shih 5782e3ec7017SPing-Ke Shih int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5783e3ec7017SPing-Ke Shih { 5784e3ec7017SPing-Ke Shih u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5785e3ec7017SPing-Ke Shih 5786e3ec7017SPing-Ke Shih val = wl ? val | BIT(2) : val & ~BIT(2); 5787e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5788e3ec7017SPing-Ke Shih 5789e3ec7017SPing-Ke Shih return 0; 5790e3ec7017SPing-Ke Shih } 5791feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5792feed6541SChia-Yuan Li 5793feed6541SChia-Yuan Li int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5794feed6541SChia-Yuan Li { 5795feed6541SChia-Yuan Li struct rtw89_btc *btc = &rtwdev->btc; 5796feed6541SChia-Yuan Li struct rtw89_btc_dm *dm = &btc->dm; 5797feed6541SChia-Yuan Li struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5798feed6541SChia-Yuan Li int i; 5799feed6541SChia-Yuan Li 5800feed6541SChia-Yuan Li if (wl) 5801feed6541SChia-Yuan Li return 0; 5802feed6541SChia-Yuan Li 5803feed6541SChia-Yuan Li for (i = 0; i < RTW89_PHY_MAX; i++) { 5804feed6541SChia-Yuan Li g[i].gnt_bt_sw_en = 1; 5805feed6541SChia-Yuan Li g[i].gnt_bt = 1; 5806feed6541SChia-Yuan Li g[i].gnt_wl_sw_en = 1; 5807feed6541SChia-Yuan Li g[i].gnt_wl = 0; 5808feed6541SChia-Yuan Li } 5809feed6541SChia-Yuan Li 5810feed6541SChia-Yuan Li return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5811feed6541SChia-Yuan Li } 5812feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5813e3ec7017SPing-Ke Shih 5814e3ec7017SPing-Ke Shih bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5815e3ec7017SPing-Ke Shih { 5816ae4e1adbSChing-Te Ku const struct rtw89_chip_info *chip = rtwdev->chip; 5817ae4e1adbSChing-Te Ku u8 val = 0; 5818e3ec7017SPing-Ke Shih 581989d06325SChing-Te Ku if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) 5820ae4e1adbSChing-Te Ku return false; 5821190dc12dSPing-Ke Shih else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 5822ae4e1adbSChing-Te Ku val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5823ae4e1adbSChing-Te Ku B_AX_LTE_MUX_CTRL_PATH >> 24); 5824ae4e1adbSChing-Te Ku 5825ae4e1adbSChing-Te Ku return !!val; 5826e3ec7017SPing-Ke Shih } 5827e3ec7017SPing-Ke Shih 58280cb01e0eSPing-Ke Shih static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 58298c7e9cebSChing-Te Ku { 58308c7e9cebSChing-Te Ku u32 reg; 58318c7e9cebSChing-Te Ku u16 cnt; 58328c7e9cebSChing-Te Ku 5833c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 58348c7e9cebSChing-Te Ku cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 58358c7e9cebSChing-Te Ku rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 58368c7e9cebSChing-Te Ku 58378c7e9cebSChing-Te Ku return cnt; 58388c7e9cebSChing-Te Ku } 58398c7e9cebSChing-Te Ku 58408a66293eSPing-Ke Shih static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 58418a66293eSPing-Ke Shih bool keep) 58428a66293eSPing-Ke Shih { 58438a66293eSPing-Ke Shih u32 reg; 58448a66293eSPing-Ke Shih 5845b6509815SZong-Zhe Yang if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 5846b6509815SZong-Zhe Yang return; 5847b6509815SZong-Zhe Yang 58488a66293eSPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5849c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 58508a66293eSPing-Ke Shih if (keep) { 58518a66293eSPing-Ke Shih set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 58528a66293eSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 58538a66293eSPing-Ke Shih BFRP_RX_STANDBY_TIMER_KEEP); 58548a66293eSPing-Ke Shih } else { 58558a66293eSPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 58568a66293eSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 58578a66293eSPing-Ke Shih BFRP_RX_STANDBY_TIMER_RELEASE); 58588a66293eSPing-Ke Shih } 58598a66293eSPing-Ke Shih } 58608a66293eSPing-Ke Shih 586131b7cd19SZong-Zhe Yang void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5862e3ec7017SPing-Ke Shih { 58635fa1c5d4SZong-Zhe Yang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5864e3ec7017SPing-Ke Shih u32 reg; 58655fa1c5d4SZong-Zhe Yang u32 mask = mac->bfee_ctrl.mask; 5866e3ec7017SPing-Ke Shih 5867e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 58685fa1c5d4SZong-Zhe Yang reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 5869e3ec7017SPing-Ke Shih if (en) { 5870e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5871e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, mask); 5872e3ec7017SPing-Ke Shih } else { 5873e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5874e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, mask); 5875e3ec7017SPing-Ke Shih } 5876e3ec7017SPing-Ke Shih } 5877e3ec7017SPing-Ke Shih 587831b7cd19SZong-Zhe Yang static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 5879e3ec7017SPing-Ke Shih { 5880e3ec7017SPing-Ke Shih u32 reg; 5881e3ec7017SPing-Ke Shih u32 val32; 5882e3ec7017SPing-Ke Shih int ret; 5883e3ec7017SPing-Ke Shih 5884e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5885e3ec7017SPing-Ke Shih if (ret) 5886e3ec7017SPing-Ke Shih return ret; 5887e3ec7017SPing-Ke Shih 5888e3ec7017SPing-Ke Shih /* AP mode set tx gid to 63 */ 5889e3ec7017SPing-Ke Shih /* STA mode set tx gid to 0(default) */ 5890c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 5891e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5892e3ec7017SPing-Ke Shih 5893c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5894e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5895e3ec7017SPing-Ke Shih 5896c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 58978a66293eSPing-Ke Shih val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5898e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 58998a66293eSPing-Ke Shih rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5900e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5901e3ec7017SPing-Ke Shih 5902c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5903e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5904e3ec7017SPing-Ke Shih B_AX_BFMEE_USE_NSTS | 5905e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_GID_SEL | 5906e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_FORCE_RETE_EN); 5907c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5908e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, 5909e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5910e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5911e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5912e3ec7017SPing-Ke Shih 5913c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 591462440fbeSPing-Ke Shih rtw89_write32_set(rtwdev, reg, 591562440fbeSPing-Ke Shih B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 591662440fbeSPing-Ke Shih 5917e3ec7017SPing-Ke Shih return 0; 5918e3ec7017SPing-Ke Shih } 5919e3ec7017SPing-Ke Shih 592031b7cd19SZong-Zhe Yang static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 5921e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 5922e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5923e3ec7017SPing-Ke Shih { 5924e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5925e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 5926e3ec7017SPing-Ke Shih u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5927e3ec7017SPing-Ke Shih u8 port_sel = rtwvif->port; 5928e3ec7017SPing-Ke Shih u8 sound_dim = 3, t; 5929046d2e7cSSriram R u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5930e3ec7017SPing-Ke Shih u32 reg; 5931e3ec7017SPing-Ke Shih u16 val; 5932e3ec7017SPing-Ke Shih int ret; 5933e3ec7017SPing-Ke Shih 5934e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5935e3ec7017SPing-Ke Shih if (ret) 5936e3ec7017SPing-Ke Shih return ret; 5937e3ec7017SPing-Ke Shih 5938e3ec7017SPing-Ke Shih if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5939e3ec7017SPing-Ke Shih (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5940e3ec7017SPing-Ke Shih ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5941e3ec7017SPing-Ke Shih stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5942e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5943e3ec7017SPing-Ke Shih phy_cap[5]); 5944e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 5945e3ec7017SPing-Ke Shih } 5946046d2e7cSSriram R if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5947046d2e7cSSriram R (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5948046d2e7cSSriram R ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5949046d2e7cSSriram R stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5950e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5951046d2e7cSSriram R sta->deflink.vht_cap.cap); 5952e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 5953e3ec7017SPing-Ke Shih } 5954e3ec7017SPing-Ke Shih nc = min(nc, sound_dim); 5955e3ec7017SPing-Ke Shih nr = min(nr, sound_dim); 5956e3ec7017SPing-Ke Shih 5957c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5958e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5959e3ec7017SPing-Ke Shih 5960e3ec7017SPing-Ke Shih val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5961e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5962e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5963e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5964e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5965e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5966e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5967e3ec7017SPing-Ke Shih 5968e3ec7017SPing-Ke Shih if (port_sel == 0) 5969c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5970e3ec7017SPing-Ke Shih else 5971c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5972e3ec7017SPing-Ke Shih 5973e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 5974e3ec7017SPing-Ke Shih 5975e3ec7017SPing-Ke Shih return 0; 5976e3ec7017SPing-Ke Shih } 5977e3ec7017SPing-Ke Shih 597831b7cd19SZong-Zhe Yang static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 5979e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 5980e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5981e3ec7017SPing-Ke Shih { 5982e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5983e3ec7017SPing-Ke Shih u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5984e3ec7017SPing-Ke Shih u32 reg; 5985e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 5986e3ec7017SPing-Ke Shih int ret; 5987e3ec7017SPing-Ke Shih 5988e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5989e3ec7017SPing-Ke Shih if (ret) 5990e3ec7017SPing-Ke Shih return ret; 5991e3ec7017SPing-Ke Shih 5992046d2e7cSSriram R if (sta->deflink.he_cap.has_he) { 5993e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5994e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5995e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5996e3ec7017SPing-Ke Shih } 5997046d2e7cSSriram R if (sta->deflink.vht_cap.vht_supported) { 5998e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5999e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 6000e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 6001e3ec7017SPing-Ke Shih } 6002046d2e7cSSriram R if (sta->deflink.ht_cap.ht_supported) { 6003e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 6004e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 6005e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 6006e3ec7017SPing-Ke Shih } 6007c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6008e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6009e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 6010e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, 6011c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 6012e3ec7017SPing-Ke Shih rrsc); 6013e3ec7017SPing-Ke Shih 6014e3ec7017SPing-Ke Shih return 0; 6015e3ec7017SPing-Ke Shih } 6016e3ec7017SPing-Ke Shih 601731b7cd19SZong-Zhe Yang static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 601831b7cd19SZong-Zhe Yang struct ieee80211_vif *vif, 6019e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 6020e3ec7017SPing-Ke Shih { 6021e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6022e3ec7017SPing-Ke Shih 6023e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) { 6024e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, 6025e3ec7017SPing-Ke Shih "initialize bfee for new association\n"); 602631b7cd19SZong-Zhe Yang rtw89_mac_init_bfee_ax(rtwdev, rtwvif->mac_idx); 602731b7cd19SZong-Zhe Yang rtw89_mac_set_csi_para_reg_ax(rtwdev, vif, sta); 602831b7cd19SZong-Zhe Yang rtw89_mac_csi_rrsc_ax(rtwdev, vif, sta); 6029e3ec7017SPing-Ke Shih } 6030e3ec7017SPing-Ke Shih } 6031e3ec7017SPing-Ke Shih 6032e3ec7017SPing-Ke Shih void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6033e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 6034e3ec7017SPing-Ke Shih { 6035e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6036e3ec7017SPing-Ke Shih 6037e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 6038e3ec7017SPing-Ke Shih } 6039e3ec7017SPing-Ke Shih 6040e3ec7017SPing-Ke Shih void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6041e3ec7017SPing-Ke Shih struct ieee80211_bss_conf *conf) 6042e3ec7017SPing-Ke Shih { 6043e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6044e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 6045e3ec7017SPing-Ke Shih __le32 *p; 6046e3ec7017SPing-Ke Shih 6047e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 6048e3ec7017SPing-Ke Shih 6049e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.membership; 6050c220d08eSPing-Ke Shih rtw89_write32(rtwdev, 6051c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 6052e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 6053c220d08eSPing-Ke Shih rtw89_write32(rtwdev, 6054c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 6055e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 6056e3ec7017SPing-Ke Shih 6057e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.position; 6058c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 6059e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 6060c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 6061e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 6062c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 6063e3ec7017SPing-Ke Shih le32_to_cpu(p[2])); 6064c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 6065e3ec7017SPing-Ke Shih le32_to_cpu(p[3])); 6066e3ec7017SPing-Ke Shih } 6067e3ec7017SPing-Ke Shih 6068e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data { 6069e3ec7017SPing-Ke Shih struct rtw89_dev *rtwdev; 6070e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta; 6071e3ec7017SPing-Ke Shih int count; 6072e3ec7017SPing-Ke Shih }; 6073e3ec7017SPing-Ke Shih 6074e3ec7017SPing-Ke Shih static 6075e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 6076e3ec7017SPing-Ke Shih { 6077e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data *iter_data = 6078e3ec7017SPing-Ke Shih (struct rtw89_mac_bf_monitor_iter_data *)data; 6079e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta = iter_data->down_sta; 6080e3ec7017SPing-Ke Shih int *count = &iter_data->count; 6081e3ec7017SPing-Ke Shih 6082e3ec7017SPing-Ke Shih if (down_sta == sta) 6083e3ec7017SPing-Ke Shih return; 6084e3ec7017SPing-Ke Shih 6085e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) 6086e3ec7017SPing-Ke Shih (*count)++; 6087e3ec7017SPing-Ke Shih } 6088e3ec7017SPing-Ke Shih 6089e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 6090e3ec7017SPing-Ke Shih struct ieee80211_sta *sta, bool disconnect) 6091e3ec7017SPing-Ke Shih { 6092e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data data; 6093e3ec7017SPing-Ke Shih 6094e3ec7017SPing-Ke Shih data.rtwdev = rtwdev; 6095e3ec7017SPing-Ke Shih data.down_sta = disconnect ? sta : NULL; 6096e3ec7017SPing-Ke Shih data.count = 0; 6097e3ec7017SPing-Ke Shih ieee80211_iterate_stations_atomic(rtwdev->hw, 6098e3ec7017SPing-Ke Shih rtw89_mac_bf_monitor_calc_iter, 6099e3ec7017SPing-Ke Shih &data); 6100e3ec7017SPing-Ke Shih 6101e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 6102e3ec7017SPing-Ke Shih if (data.count) 6103e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6104e3ec7017SPing-Ke Shih else 6105e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6106e3ec7017SPing-Ke Shih } 6107e3ec7017SPing-Ke Shih 6108e3ec7017SPing-Ke Shih void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 6109e3ec7017SPing-Ke Shih { 6110e3ec7017SPing-Ke Shih struct rtw89_traffic_stats *stats = &rtwdev->stats; 6111e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif; 61121646ce8fSYe Guojin bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 6113e3ec7017SPing-Ke Shih bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 61148a66293eSPing-Ke Shih bool keep_timer = true; 61158a66293eSPing-Ke Shih bool old_keep_timer; 61168a66293eSPing-Ke Shih 61178a66293eSPing-Ke Shih old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 61188a66293eSPing-Ke Shih 61198a66293eSPing-Ke Shih if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 61208a66293eSPing-Ke Shih keep_timer = false; 61218a66293eSPing-Ke Shih 61228a66293eSPing-Ke Shih if (keep_timer != old_keep_timer) { 61238a66293eSPing-Ke Shih rtw89_for_each_rtwvif(rtwdev, rtwvif) 61248a66293eSPing-Ke Shih rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 61258a66293eSPing-Ke Shih keep_timer); 61268a66293eSPing-Ke Shih } 6127e3ec7017SPing-Ke Shih 6128e3ec7017SPing-Ke Shih if (en == old) 6129e3ec7017SPing-Ke Shih return; 6130e3ec7017SPing-Ke Shih 6131e3ec7017SPing-Ke Shih rtw89_for_each_rtwvif(rtwdev, rtwvif) 6132e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 6133e3ec7017SPing-Ke Shih } 6134e3ec7017SPing-Ke Shih 6135e3ec7017SPing-Ke Shih static int 6136e3ec7017SPing-Ke Shih __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6137e3ec7017SPing-Ke Shih u32 tx_time) 6138e3ec7017SPing-Ke Shih { 6139e3ec7017SPing-Ke Shih #define MAC_AX_DFLT_TX_TIME 5280 6140e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 6141e3ec7017SPing-Ke Shih u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 6142e3ec7017SPing-Ke Shih u32 reg; 6143e3ec7017SPing-Ke Shih int ret = 0; 6144e3ec7017SPing-Ke Shih 6145e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 6146e3ec7017SPing-Ke Shih rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 6147e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6148e3ec7017SPing-Ke Shih } else { 6149e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6150e3ec7017SPing-Ke Shih if (ret) { 6151e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 6152e3ec7017SPing-Ke Shih return ret; 6153e3ec7017SPing-Ke Shih } 6154e3ec7017SPing-Ke Shih 6155c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6156e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 6157e3ec7017SPing-Ke Shih max_tx_time >> 5); 6158e3ec7017SPing-Ke Shih } 6159e3ec7017SPing-Ke Shih 6160e3ec7017SPing-Ke Shih return ret; 6161e3ec7017SPing-Ke Shih } 6162e3ec7017SPing-Ke Shih 6163e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6164e3ec7017SPing-Ke Shih bool resume, u32 tx_time) 6165e3ec7017SPing-Ke Shih { 6166e3ec7017SPing-Ke Shih int ret = 0; 6167e3ec7017SPing-Ke Shih 6168e3ec7017SPing-Ke Shih if (!resume) { 6169e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = true; 6170e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 6171e3ec7017SPing-Ke Shih } else { 6172e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 6173e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = false; 6174e3ec7017SPing-Ke Shih } 6175e3ec7017SPing-Ke Shih 6176e3ec7017SPing-Ke Shih return ret; 6177e3ec7017SPing-Ke Shih } 6178e3ec7017SPing-Ke Shih 6179e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6180e3ec7017SPing-Ke Shih u32 *tx_time) 6181e3ec7017SPing-Ke Shih { 6182e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 6183e3ec7017SPing-Ke Shih u32 reg; 6184e3ec7017SPing-Ke Shih int ret = 0; 6185e3ec7017SPing-Ke Shih 6186e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 6187e3ec7017SPing-Ke Shih *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 6188e3ec7017SPing-Ke Shih } else { 6189e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6190e3ec7017SPing-Ke Shih if (ret) { 6191e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 6192e3ec7017SPing-Ke Shih return ret; 6193e3ec7017SPing-Ke Shih } 6194e3ec7017SPing-Ke Shih 6195c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6196e3ec7017SPing-Ke Shih *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 6197e3ec7017SPing-Ke Shih } 6198e3ec7017SPing-Ke Shih 6199e3ec7017SPing-Ke Shih return ret; 6200e3ec7017SPing-Ke Shih } 6201e3ec7017SPing-Ke Shih 6202e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 6203e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, 6204e3ec7017SPing-Ke Shih bool resume, u8 tx_retry) 6205e3ec7017SPing-Ke Shih { 6206e3ec7017SPing-Ke Shih int ret = 0; 6207e3ec7017SPing-Ke Shih 6208e3ec7017SPing-Ke Shih rtwsta->data_tx_cnt_lmt = tx_retry; 6209e3ec7017SPing-Ke Shih 6210e3ec7017SPing-Ke Shih if (!resume) { 6211e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = true; 6212e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6213e3ec7017SPing-Ke Shih } else { 6214e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6215e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = false; 6216e3ec7017SPing-Ke Shih } 6217e3ec7017SPing-Ke Shih 6218e3ec7017SPing-Ke Shih return ret; 6219e3ec7017SPing-Ke Shih } 6220e3ec7017SPing-Ke Shih 6221e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 6222e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, u8 *tx_retry) 6223e3ec7017SPing-Ke Shih { 6224e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 6225e3ec7017SPing-Ke Shih u32 reg; 6226e3ec7017SPing-Ke Shih int ret = 0; 6227e3ec7017SPing-Ke Shih 6228e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_retry_limit) { 6229e3ec7017SPing-Ke Shih *tx_retry = rtwsta->data_tx_cnt_lmt; 6230e3ec7017SPing-Ke Shih } else { 6231e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6232e3ec7017SPing-Ke Shih if (ret) { 6233e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 6234e3ec7017SPing-Ke Shih return ret; 6235e3ec7017SPing-Ke Shih } 6236e3ec7017SPing-Ke Shih 6237c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); 6238e3ec7017SPing-Ke Shih *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 6239e3ec7017SPing-Ke Shih } 6240e3ec7017SPing-Ke Shih 6241e3ec7017SPing-Ke Shih return ret; 6242e3ec7017SPing-Ke Shih } 6243e3ec7017SPing-Ke Shih 6244e3ec7017SPing-Ke Shih int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 6245e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 6246e3ec7017SPing-Ke Shih { 62477f69cd42SZong-Zhe Yang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6248e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 62497f69cd42SZong-Zhe Yang u16 set = mac->muedca_ctrl.mask; 6250e3ec7017SPing-Ke Shih u32 reg; 6251e3ec7017SPing-Ke Shih u32 ret; 6252e3ec7017SPing-Ke Shih 6253e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6254e3ec7017SPing-Ke Shih if (ret) 6255e3ec7017SPing-Ke Shih return ret; 6256e3ec7017SPing-Ke Shih 62577f69cd42SZong-Zhe Yang reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 6258e3ec7017SPing-Ke Shih if (en) 6259e3ec7017SPing-Ke Shih rtw89_write16_set(rtwdev, reg, set); 6260e3ec7017SPing-Ke Shih else 6261e3ec7017SPing-Ke Shih rtw89_write16_clr(rtwdev, reg, set); 6262e3ec7017SPing-Ke Shih 6263e3ec7017SPing-Ke Shih return 0; 6264e3ec7017SPing-Ke Shih } 62652a7e54dbSPing-Ke Shih 6266efde4f6dSPing-Ke Shih static 6267efde4f6dSPing-Ke Shih int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 62682a7e54dbSPing-Ke Shih { 62692a7e54dbSPing-Ke Shih u32 val32; 62702a7e54dbSPing-Ke Shih int ret; 62712a7e54dbSPing-Ke Shih 62722a7e54dbSPing-Ke Shih val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 62732a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 62742a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 62752a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 62762a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 62772a7e54dbSPing-Ke Shih rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 62782a7e54dbSPing-Ke Shih 62792a7e54dbSPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 62802a7e54dbSPing-Ke Shih 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 62812a7e54dbSPing-Ke Shih if (ret) { 62822a7e54dbSPing-Ke Shih rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 62832a7e54dbSPing-Ke Shih offset, val, mask); 62842a7e54dbSPing-Ke Shih return ret; 62852a7e54dbSPing-Ke Shih } 62862a7e54dbSPing-Ke Shih 62872a7e54dbSPing-Ke Shih return 0; 62882a7e54dbSPing-Ke Shih } 6289bdfbf06cSPing-Ke Shih 6290efde4f6dSPing-Ke Shih static 6291efde4f6dSPing-Ke Shih int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 6292bdfbf06cSPing-Ke Shih { 6293bdfbf06cSPing-Ke Shih u32 val32; 6294bdfbf06cSPing-Ke Shih int ret; 6295bdfbf06cSPing-Ke Shih 6296bdfbf06cSPing-Ke Shih val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6297bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 6298bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 6299bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 6300bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6301bdfbf06cSPing-Ke Shih rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6302bdfbf06cSPing-Ke Shih 6303bdfbf06cSPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6304bdfbf06cSPing-Ke Shih 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6305bdfbf06cSPing-Ke Shih if (ret) { 6306bdfbf06cSPing-Ke Shih rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 6307bdfbf06cSPing-Ke Shih return ret; 6308bdfbf06cSPing-Ke Shih } 6309bdfbf06cSPing-Ke Shih 6310bdfbf06cSPing-Ke Shih *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 6311bdfbf06cSPing-Ke Shih 6312bdfbf06cSPing-Ke Shih return 0; 6313bdfbf06cSPing-Ke Shih } 63149a785583SZong-Zhe Yang 63159a785583SZong-Zhe Yang static 63169a785583SZong-Zhe Yang void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 63179a785583SZong-Zhe Yang { 63189a785583SZong-Zhe Yang static const enum rtw89_pkt_drop_sel sels[] = { 63199a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 63209a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 63219a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 63229a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 63239a785583SZong-Zhe Yang }; 63249a785583SZong-Zhe Yang struct rtw89_vif *rtwvif = rtwsta->rtwvif; 63259a785583SZong-Zhe Yang struct rtw89_pkt_drop_params params = {0}; 63269a785583SZong-Zhe Yang int i; 63279a785583SZong-Zhe Yang 63289a785583SZong-Zhe Yang params.mac_band = RTW89_MAC_0; 63299a785583SZong-Zhe Yang params.macid = rtwsta->mac_id; 63309a785583SZong-Zhe Yang params.port = rtwvif->port; 63319a785583SZong-Zhe Yang params.mbssid = 0; 63329a785583SZong-Zhe Yang params.tf_trs = rtwvif->trigger; 63339a785583SZong-Zhe Yang 63349a785583SZong-Zhe Yang for (i = 0; i < ARRAY_SIZE(sels); i++) { 63359a785583SZong-Zhe Yang params.sel = sels[i]; 63369a785583SZong-Zhe Yang rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 63379a785583SZong-Zhe Yang } 63389a785583SZong-Zhe Yang } 63399a785583SZong-Zhe Yang 63409a785583SZong-Zhe Yang static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 63419a785583SZong-Zhe Yang { 63429a785583SZong-Zhe Yang struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 63439a785583SZong-Zhe Yang struct rtw89_vif *rtwvif = rtwsta->rtwvif; 63449a785583SZong-Zhe Yang struct rtw89_dev *rtwdev = rtwvif->rtwdev; 63459a785583SZong-Zhe Yang struct rtw89_vif *target = data; 63469a785583SZong-Zhe Yang 63479a785583SZong-Zhe Yang if (rtwvif != target) 63489a785583SZong-Zhe Yang return; 63499a785583SZong-Zhe Yang 63509a785583SZong-Zhe Yang rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 63519a785583SZong-Zhe Yang } 63529a785583SZong-Zhe Yang 63539a785583SZong-Zhe Yang void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 63549a785583SZong-Zhe Yang { 63559a785583SZong-Zhe Yang ieee80211_iterate_stations_atomic(rtwdev->hw, 63569a785583SZong-Zhe Yang rtw89_mac_pkt_drop_vif_iter, 63579a785583SZong-Zhe Yang rtwvif); 63589a785583SZong-Zhe Yang } 635941d56769SChih-Kang Chang 636041d56769SChih-Kang Chang int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 636141d56769SChih-Kang Chang enum rtw89_mac_idx band) 636241d56769SChih-Kang Chang { 636327ea6be9SZong-Zhe Yang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 636441d56769SChih-Kang Chang struct rtw89_pkt_drop_params params = {0}; 636541d56769SChih-Kang Chang bool empty; 636641d56769SChih-Kang Chang int i, ret = 0, try_cnt = 3; 636741d56769SChih-Kang Chang 636841d56769SChih-Kang Chang params.mac_band = band; 636941d56769SChih-Kang Chang params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 637041d56769SChih-Kang Chang 637141d56769SChih-Kang Chang for (i = 0; i < try_cnt; i++) { 637227ea6be9SZong-Zhe Yang ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 637341d56769SChih-Kang Chang 50000, false, rtwdev); 63740d1f7ff1SZong-Zhe Yang if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 637541d56769SChih-Kang Chang rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 637641d56769SChih-Kang Chang else 637741d56769SChih-Kang Chang return 0; 637841d56769SChih-Kang Chang } 637941d56769SChih-Kang Chang return ret; 638041d56769SChih-Kang Chang } 6381c220d08eSPing-Ke Shih 63826a03a349SChih-Kang Chang int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 63836a03a349SChih-Kang Chang { 63846a03a349SChih-Kang Chang struct rtw89_mac_h2c_info h2c_info = {}; 63856a03a349SChih-Kang Chang struct rtw89_mac_c2h_info c2h_info = {}; 63866a03a349SChih-Kang Chang u32 ret; 63876a03a349SChih-Kang Chang 63886a03a349SChih-Kang Chang h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; 63896a03a349SChih-Kang Chang h2c_info.content_len = sizeof(h2c_info.u.hdr); 63906a03a349SChih-Kang Chang h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); 63916a03a349SChih-Kang Chang 63926a03a349SChih-Kang Chang ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 63936a03a349SChih-Kang Chang if (ret) 63946a03a349SChih-Kang Chang return ret; 63956a03a349SChih-Kang Chang 63966a03a349SChih-Kang Chang if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) 63976a03a349SChih-Kang Chang ret = -EINVAL; 63986a03a349SChih-Kang Chang 63996a03a349SChih-Kang Chang return ret; 64006a03a349SChih-Kang Chang } 64016a03a349SChih-Kang Chang 6402fff82128SChin-Yen Lee static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 6403fff82128SChin-Yen Lee { 6404fff82128SChin-Yen Lee const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 64056a03a349SChih-Kang Chang const struct rtw89_chip_info *chip = rtwdev->chip; 6406fff82128SChin-Yen Lee int ret; 6407fff82128SChin-Yen Lee 6408fff82128SChin-Yen Lee if (enable_wow) { 6409fff82128SChin-Yen Lee ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 6410fff82128SChin-Yen Lee if (ret) { 6411fff82128SChin-Yen Lee rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6412fff82128SChin-Yen Lee return ret; 6413fff82128SChin-Yen Lee } 6414fff82128SChin-Yen Lee 6415fff82128SChin-Yen Lee rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 64166a03a349SChih-Kang Chang rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6417fff82128SChin-Yen Lee rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 6418fff82128SChin-Yen Lee rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 6419fff82128SChin-Yen Lee rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 6420fff82128SChin-Yen Lee rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 6421fff82128SChin-Yen Lee rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 6422fff82128SChin-Yen Lee rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 64236a03a349SChih-Kang Chang 64246a03a349SChih-Kang Chang if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 64256a03a349SChih-Kang Chang rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 64266a03a349SChih-Kang Chang else 64276a03a349SChih-Kang Chang rtw89_write32_set(rtwdev, R_AX_DBG_WOW, 64286a03a349SChih-Kang Chang B_AX_DBG_WOW_CPU_IO_RX_EN); 6429fff82128SChin-Yen Lee } else { 6430fff82128SChin-Yen Lee ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 6431fff82128SChin-Yen Lee if (ret) { 6432fff82128SChin-Yen Lee rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6433fff82128SChin-Yen Lee return ret; 6434fff82128SChin-Yen Lee } 6435fff82128SChin-Yen Lee 64366a03a349SChih-Kang Chang rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6437fff82128SChin-Yen Lee rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6438fff82128SChin-Yen Lee rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 6439fff82128SChin-Yen Lee rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 6440fff82128SChin-Yen Lee rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 6441fff82128SChin-Yen Lee } 6442fff82128SChin-Yen Lee 6443fff82128SChin-Yen Lee return 0; 6444fff82128SChin-Yen Lee } 6445fff82128SChin-Yen Lee 6446fa31a8c5SPing-Ke Shih static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 6447ae4dc23dSPing-Ke Shih { 6448ae4dc23dSPing-Ke Shih u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 6449ae4dc23dSPing-Ke Shih 6450ae4dc23dSPing-Ke Shih return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 6451ae4dc23dSPing-Ke Shih } 6452ae4dc23dSPing-Ke Shih 6453ae4dc23dSPing-Ke Shih static 645480e706a8SPing-Ke Shih int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 645580e706a8SPing-Ke Shih bool h2c_or_fwdl) 645680e706a8SPing-Ke Shih { 645780e706a8SPing-Ke Shih u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 645880e706a8SPing-Ke Shih u8 val; 645980e706a8SPing-Ke Shih 646080e706a8SPing-Ke Shih return read_poll_timeout_atomic(rtw89_read8, val, val & check, 646180e706a8SPing-Ke Shih 1, FWDL_WAIT_CNT, false, 646280e706a8SPing-Ke Shih rtwdev, R_AX_WCPU_FW_CTRL); 646380e706a8SPing-Ke Shih } 646480e706a8SPing-Ke Shih 6465c220d08eSPing-Ke Shih const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 6466c220d08eSPing-Ke Shih .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 646760168f6cSPing-Ke Shih .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 646860168f6cSPing-Ke Shih .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 646960168f6cSPing-Ke Shih .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 64709d87e7dcSPing-Ke Shih .rx_fltr = R_AX_RX_FLTR_OPT, 64717c8a55ddSPing-Ke Shih .port_base = &rtw89_port_base_ax, 6472fbd1829dSZong-Zhe Yang .agg_len_ht = R_AX_AGG_LEN_HT_0, 6473f651300cSChin-Yen Lee .ps_status = R_AX_PPWRBIT_SETTING, 6474ae4dc23dSPing-Ke Shih 64757f69cd42SZong-Zhe Yang .muedca_ctrl = { 64767f69cd42SZong-Zhe Yang .addr = R_AX_MUEDCA_EN, 64777f69cd42SZong-Zhe Yang .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 64787f69cd42SZong-Zhe Yang }, 64795fa1c5d4SZong-Zhe Yang .bfee_ctrl = { 64805fa1c5d4SZong-Zhe Yang .addr = R_AX_BFMEE_RESP_OPTION, 64815fa1c5d4SZong-Zhe Yang .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 64825fa1c5d4SZong-Zhe Yang B_AX_BFMEE_HE_NDPA_EN, 64835fa1c5d4SZong-Zhe Yang }, 648449ea9823SZong-Zhe Yang .narrow_bw_ru_dis = { 648549ea9823SZong-Zhe Yang .addr = R_AX_RXTRIG_TEST_USER_2, 648649ea9823SZong-Zhe Yang .mask = B_AX_RXTRIG_RU26_DIS, 648749ea9823SZong-Zhe Yang }, 6488a0f00465SChin-Yen Lee .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 64897f69cd42SZong-Zhe Yang 6490cfb99433SPing-Ke Shih .check_mac_en = rtw89_mac_check_mac_en_ax, 6491fc663fa0SPing-Ke Shih .sys_init = sys_init_ax, 6492fc663fa0SPing-Ke Shih .trx_init = trx_init_ax, 649339e9b569SPing-Ke Shih .hci_func_en = rtw89_mac_hci_func_en_ax, 649439e9b569SPing-Ke Shih .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 649539e9b569SPing-Ke Shih .dle_func_en = dle_func_en_ax, 649639e9b569SPing-Ke Shih .dle_clk_en = dle_clk_en_ax, 649731b7cd19SZong-Zhe Yang .bf_assoc = rtw89_mac_bf_assoc_ax, 649831b7cd19SZong-Zhe Yang 6499fc663fa0SPing-Ke Shih .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 6500b16daa62SPing-Ke Shih .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 6501fc663fa0SPing-Ke Shih 650239e9b569SPing-Ke Shih .dle_mix_cfg = dle_mix_cfg_ax, 650339e9b569SPing-Ke Shih .chk_dle_rdy = chk_dle_rdy_ax, 650439e9b569SPing-Ke Shih .dle_buf_req = dle_buf_req_ax, 650539e9b569SPing-Ke Shih .hfc_func_en = hfc_func_en_ax, 650639e9b569SPing-Ke Shih .hfc_h2c_cfg = hfc_h2c_cfg_ax, 650739e9b569SPing-Ke Shih .hfc_mix_cfg = hfc_mix_cfg_ax, 650839e9b569SPing-Ke Shih .hfc_get_mix_info = hfc_get_mix_info_ax, 650939e9b569SPing-Ke Shih .wde_quota_cfg = wde_quota_cfg_ax, 651039e9b569SPing-Ke Shih .ple_quota_cfg = ple_quota_cfg_ax, 651139e9b569SPing-Ke Shih .set_cpuio = set_cpuio_ax, 6512b6e65d18SPing-Ke Shih .dle_quota_change = dle_quota_change_ax, 651339e9b569SPing-Ke Shih 6514ae4dc23dSPing-Ke Shih .disable_cpu = rtw89_mac_disable_cpu_ax, 6515ae4dc23dSPing-Ke Shih .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 6516ae4dc23dSPing-Ke Shih .fwdl_get_status = rtw89_fw_get_rdy_ax, 6517ae4dc23dSPing-Ke Shih .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 651888e6a923SPing-Ke Shih .parse_efuse_map = rtw89_parse_efuse_map_ax, 651988e6a923SPing-Ke Shih .parse_phycap_map = rtw89_parse_phycap_map_ax, 652088e6a923SPing-Ke Shih .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 652106b26738SZong-Zhe Yang 65220cb01e0eSPing-Ke Shih .cfg_plt = rtw89_mac_cfg_plt_ax, 65230cb01e0eSPing-Ke Shih .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 65240cb01e0eSPing-Ke Shih 652506b26738SZong-Zhe Yang .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 652627ea6be9SZong-Zhe Yang 6527efde4f6dSPing-Ke Shih .write_xtal_si = rtw89_mac_write_xtal_si_ax, 6528efde4f6dSPing-Ke Shih .read_xtal_si = rtw89_mac_read_xtal_si_ax, 6529efde4f6dSPing-Ke Shih 65306f8d3655SChia-Yuan Li .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 65316f8d3655SChia-Yuan Li .dump_err_status = rtw89_mac_dump_err_status_ax, 65326f8d3655SChia-Yuan Li 653327ea6be9SZong-Zhe Yang .is_txq_empty = mac_is_txq_empty_ax, 6534a412920bSPo-Hao Huang 6535c0bc1bceSChin-Yen Lee .add_chan_list = rtw89_hw_scan_add_chan_list_ax, 6536c0bc1bceSChin-Yen Lee .add_chan_list_pno = rtw89_pno_scan_add_chan_list_ax, 6537c0bc1bceSChin-Yen Lee .scan_offload = rtw89_fw_h2c_scan_offload_ax, 6538fff82128SChin-Yen Lee 6539fff82128SChin-Yen Lee .wow_config_mac = rtw89_wow_config_mac_ax, 6540c220d08eSPing-Ke Shih }; 6541c220d08eSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_gen_ax); 6542