1e3ec7017SPing-Ke Shih // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2e3ec7017SPing-Ke Shih /* Copyright(c) 2019-2020 Realtek Corporation 3e3ec7017SPing-Ke Shih */ 4e3ec7017SPing-Ke Shih 5e3ec7017SPing-Ke Shih #include "cam.h" 6e3ec7017SPing-Ke Shih #include "debug.h" 7e3ec7017SPing-Ke Shih #include "fw.h" 8e3ec7017SPing-Ke Shih #include "mac.h" 9e3ec7017SPing-Ke Shih #include "ps.h" 10e3ec7017SPing-Ke Shih #include "reg.h" 11e3ec7017SPing-Ke Shih #include "util.h" 12e3ec7017SPing-Ke Shih 13e1400b11SZong-Zhe Yang const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_MAX] = { 14e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 15e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 16e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 17e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 18e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 19e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 20e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 21e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 22e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 23e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 24e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 25e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 26e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 27e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 28e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 29e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 30e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 31e1400b11SZong-Zhe Yang }; 32e1400b11SZong-Zhe Yang 33e3ec7017SPing-Ke Shih int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 34e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 35e3ec7017SPing-Ke Shih { 36e3ec7017SPing-Ke Shih u32 val, r_val; 37e3ec7017SPing-Ke Shih 38e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 39e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 40e3ec7017SPing-Ke Shih val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 41e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 42e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 43e3ec7017SPing-Ke Shih val = B_AX_CMAC_EN; 44e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 45e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 46e3ec7017SPing-Ke Shih val = B_AX_CMAC1_FEN; 47e3ec7017SPing-Ke Shih } else { 48e3ec7017SPing-Ke Shih return -EINVAL; 49e3ec7017SPing-Ke Shih } 50e3ec7017SPing-Ke Shih if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 51e3ec7017SPing-Ke Shih (val & r_val) != val) 52e3ec7017SPing-Ke Shih return -EFAULT; 53e3ec7017SPing-Ke Shih 54e3ec7017SPing-Ke Shih return 0; 55e3ec7017SPing-Ke Shih } 56e3ec7017SPing-Ke Shih 57e3ec7017SPing-Ke Shih int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 58e3ec7017SPing-Ke Shih { 59e3ec7017SPing-Ke Shih u8 lte_ctrl; 60e3ec7017SPing-Ke Shih int ret; 61e3ec7017SPing-Ke Shih 62e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 63e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 64e3ec7017SPing-Ke Shih if (ret) 65e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 66e3ec7017SPing-Ke Shih 67e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 68e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 69e3ec7017SPing-Ke Shih 70e3ec7017SPing-Ke Shih return ret; 71e3ec7017SPing-Ke Shih } 72e3ec7017SPing-Ke Shih 73e3ec7017SPing-Ke Shih int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 74e3ec7017SPing-Ke Shih { 75e3ec7017SPing-Ke Shih u8 lte_ctrl; 76e3ec7017SPing-Ke Shih int ret; 77e3ec7017SPing-Ke Shih 78e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 79e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 80e3ec7017SPing-Ke Shih if (ret) 81e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 82e3ec7017SPing-Ke Shih 83e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 84e3ec7017SPing-Ke Shih *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 85e3ec7017SPing-Ke Shih 86e3ec7017SPing-Ke Shih return ret; 87e3ec7017SPing-Ke Shih } 88e3ec7017SPing-Ke Shih 89e3ec7017SPing-Ke Shih static 90e3ec7017SPing-Ke Shih int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 91e3ec7017SPing-Ke Shih { 92e3ec7017SPing-Ke Shih u32 ctrl_reg, data_reg, ctrl_data; 93e3ec7017SPing-Ke Shih u32 val; 94e3ec7017SPing-Ke Shih int ret; 95e3ec7017SPing-Ke Shih 96e3ec7017SPing-Ke Shih switch (ctrl->type) { 97e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_WDE: 98e3ec7017SPing-Ke Shih ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 99e3ec7017SPing-Ke Shih data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 100e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 101e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 102e3ec7017SPing-Ke Shih B_AX_WDE_DFI_ACTIVE; 103e3ec7017SPing-Ke Shih break; 104e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_PLE: 105e3ec7017SPing-Ke Shih ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 106e3ec7017SPing-Ke Shih data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 107e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 108e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 109e3ec7017SPing-Ke Shih B_AX_PLE_DFI_ACTIVE; 110e3ec7017SPing-Ke Shih break; 111e3ec7017SPing-Ke Shih default: 112e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 113e3ec7017SPing-Ke Shih return -EINVAL; 114e3ec7017SPing-Ke Shih } 115e3ec7017SPing-Ke Shih 116e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 117e3ec7017SPing-Ke Shih 118e3ec7017SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 119e3ec7017SPing-Ke Shih 1, 1000, false, rtwdev, ctrl_reg); 120e3ec7017SPing-Ke Shih if (ret) { 121e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 122e3ec7017SPing-Ke Shih ctrl_reg, ctrl_data); 123e3ec7017SPing-Ke Shih return ret; 124e3ec7017SPing-Ke Shih } 125e3ec7017SPing-Ke Shih 126e3ec7017SPing-Ke Shih ctrl->out_data = rtw89_read32(rtwdev, data_reg); 127e3ec7017SPing-Ke Shih return 0; 128e3ec7017SPing-Ke Shih } 129e3ec7017SPing-Ke Shih 130e3ec7017SPing-Ke Shih static int dle_dfi_quota(struct rtw89_dev *rtwdev, 131e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota *quota) 132e3ec7017SPing-Ke Shih { 133e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 134e3ec7017SPing-Ke Shih int ret; 135e3ec7017SPing-Ke Shih 136e3ec7017SPing-Ke Shih ctrl.type = quota->dle_type; 137e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QUOTA; 138e3ec7017SPing-Ke Shih ctrl.addr = quota->qtaid; 139e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 140e3ec7017SPing-Ke Shih if (ret) { 141e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 142e3ec7017SPing-Ke Shih return ret; 143e3ec7017SPing-Ke Shih } 144e3ec7017SPing-Ke Shih 145e3ec7017SPing-Ke Shih quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 146e3ec7017SPing-Ke Shih quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 147e3ec7017SPing-Ke Shih return 0; 148e3ec7017SPing-Ke Shih } 149e3ec7017SPing-Ke Shih 150e3ec7017SPing-Ke Shih static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 151e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty *qempty) 152e3ec7017SPing-Ke Shih { 153e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 154e3ec7017SPing-Ke Shih u32 ret; 155e3ec7017SPing-Ke Shih 156e3ec7017SPing-Ke Shih ctrl.type = qempty->dle_type; 157e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QEMPTY; 158e3ec7017SPing-Ke Shih ctrl.addr = qempty->grpsel; 159e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 160e3ec7017SPing-Ke Shih if (ret) { 161e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 162e3ec7017SPing-Ke Shih return ret; 163e3ec7017SPing-Ke Shih } 164e3ec7017SPing-Ke Shih 165e3ec7017SPing-Ke Shih qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 166e3ec7017SPing-Ke Shih return 0; 167e3ec7017SPing-Ke Shih } 168e3ec7017SPing-Ke Shih 169e3ec7017SPing-Ke Shih static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 170e3ec7017SPing-Ke Shih { 171e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 172e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 173e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 174e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 175e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 176e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 177e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 178e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 179e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 180e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 181e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 182e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 183e3ec7017SPing-Ke Shih } 184e3ec7017SPing-Ke Shih 185e3ec7017SPing-Ke Shih static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 186e3ec7017SPing-Ke Shih { 187e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty qempty; 188e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota quota; 189e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 190e3ec7017SPing-Ke Shih u32 val, not_empty, i; 191e3ec7017SPing-Ke Shih int ret; 192e3ec7017SPing-Ke Shih 193e3ec7017SPing-Ke Shih qempty.dle_type = DLE_CTRL_TYPE_PLE; 194e3ec7017SPing-Ke Shih qempty.grpsel = 0; 19589e4a00fSÍñigo Huguet qempty.qempty = ~(u32)0; 196e3ec7017SPing-Ke Shih ret = dle_dfi_qempty(rtwdev, &qempty); 197e3ec7017SPing-Ke Shih if (ret) 198e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 199e3ec7017SPing-Ke Shih else 200e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 201e3ec7017SPing-Ke Shih 202e3ec7017SPing-Ke Shih for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 203e3ec7017SPing-Ke Shih if (!(not_empty & BIT(0))) 204e3ec7017SPing-Ke Shih continue; 205e3ec7017SPing-Ke Shih ctrl.type = DLE_CTRL_TYPE_PLE; 206e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QLNKTBL; 207e3ec7017SPing-Ke Shih ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 208e3ec7017SPing-Ke Shih FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 209e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 210e3ec7017SPing-Ke Shih if (ret) 211e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 212e3ec7017SPing-Ke Shih else 213e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 214e3ec7017SPing-Ke Shih FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 215e3ec7017SPing-Ke Shih ctrl.out_data)); 216e3ec7017SPing-Ke Shih } 217e3ec7017SPing-Ke Shih 218e3ec7017SPing-Ke Shih quota.dle_type = DLE_CTRL_TYPE_PLE; 219e3ec7017SPing-Ke Shih quota.qtaid = 6; 220e3ec7017SPing-Ke Shih ret = dle_dfi_quota(rtwdev, "a); 221e3ec7017SPing-Ke Shih if (ret) 222e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 223e3ec7017SPing-Ke Shih else 224e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 225e3ec7017SPing-Ke Shih quota.rsv_pgnum, quota.use_pgnum); 226e3ec7017SPing-Ke Shih 227e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 228e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 229e3ec7017SPing-Ke Shih FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 230e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 231e3ec7017SPing-Ke Shih FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 232e3ec7017SPing-Ke Shih 233e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 234e3ec7017SPing-Ke Shih } 235e3ec7017SPing-Ke Shih 236e3ec7017SPing-Ke Shih static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 237e3ec7017SPing-Ke Shih enum mac_ax_err_info err) 238e3ec7017SPing-Ke Shih { 239e3ec7017SPing-Ke Shih u32 dbg, event; 240e3ec7017SPing-Ke Shih 241e3ec7017SPing-Ke Shih dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 242e3ec7017SPing-Ke Shih event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 243e3ec7017SPing-Ke Shih 244e3ec7017SPing-Ke Shih switch (event) { 245e3ec7017SPing-Ke Shih case MAC_AX_L0_TO_L1_RX_QTA_LOST: 246e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota lost!\n"); 247e3ec7017SPing-Ke Shih rtw89_mac_dump_qta_lost(rtwdev); 248e3ec7017SPing-Ke Shih break; 249e3ec7017SPing-Ke Shih default: 250e3ec7017SPing-Ke Shih break; 251e3ec7017SPing-Ke Shih } 252e3ec7017SPing-Ke Shih } 253e3ec7017SPing-Ke Shih 254e3ec7017SPing-Ke Shih static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 255e3ec7017SPing-Ke Shih enum mac_ax_err_info err) 256e3ec7017SPing-Ke Shih { 257e3ec7017SPing-Ke Shih u32 dmac_err, cmac_err; 258e3ec7017SPing-Ke Shih 259e3ec7017SPing-Ke Shih if (err != MAC_AX_ERR_L1_ERR_DMAC && 260198b6cf7SZong-Zhe Yang err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 261198b6cf7SZong-Zhe Yang err != MAC_AX_ERR_L0_ERR_CMAC0 && 262198b6cf7SZong-Zhe Yang err != MAC_AX_ERR_L0_ERR_CMAC1) 263e3ec7017SPing-Ke Shih return; 264e3ec7017SPing-Ke Shih 265e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 266e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 267e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 268e3ec7017SPing-Ke Shih 269e3ec7017SPing-Ke Shih cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR); 270e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err); 271e3ec7017SPing-Ke Shih dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 272e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err); 273e3ec7017SPing-Ke Shih 274e3ec7017SPing-Ke Shih if (dmac_err) { 275e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ", 276e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG)); 277e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n", 278e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG)); 279e3ec7017SPing-Ke Shih } 280e3ec7017SPing-Ke Shih 281e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 282e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ", 283e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 284e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n", 285e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 286e3ec7017SPing-Ke Shih } 287e3ec7017SPing-Ke Shih 288e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WSEC_ERR_FLAG) { 289e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n", 290e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 291e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n", 292e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 293e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n", 294e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 295e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n", 296e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 297e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n", 298e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 299e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n", 300e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 301e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n", 302e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 303e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n", 304e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 305e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n", 306e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 307e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n", 308e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 309e3ec7017SPing-Ke Shih } 310e3ec7017SPing-Ke Shih 311e3ec7017SPing-Ke Shih if (dmac_err & B_AX_MPDU_ERR_FLAG) { 312e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ", 313e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 314e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n", 315e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 316e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ", 317e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 318e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n", 319e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 320e3ec7017SPing-Ke Shih } 321e3ec7017SPing-Ke Shih 322e3ec7017SPing-Ke Shih if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 323e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ", 324e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 325e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n", 326e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 327e3ec7017SPing-Ke Shih } 328e3ec7017SPing-Ke Shih 329e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 330e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", 331e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 332e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 333e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 334e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", 335e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 336e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 337e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 338e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 339e3ec7017SPing-Ke Shih } 340e3ec7017SPing-Ke Shih 341e3ec7017SPing-Ke Shih if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 342e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 343e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 344e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 345e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 346e3ec7017SPing-Ke Shih } 347e3ec7017SPing-Ke Shih 348e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 349e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", 350e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 351e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 352e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 353e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", 354e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 355e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 356e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 357e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 358e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 359e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 360e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 361e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 362e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 363e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 364e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 365e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 366e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 367e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 368e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 369e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 370e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 371e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 372e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 373e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 374e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 375e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 376e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 377e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 378e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 379e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 380e3ec7017SPing-Ke Shih } 381e3ec7017SPing-Ke Shih 382e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 383e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", 384e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 385e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", 386e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 387e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", 388e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 389e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", 390e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 391e3ec7017SPing-Ke Shih } 392e3ec7017SPing-Ke Shih 393e3ec7017SPing-Ke Shih if (dmac_err & B_AX_DISPATCH_ERR_FLAG) 394e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 395e3ec7017SPing-Ke Shih 396e3ec7017SPing-Ke Shih if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) { 397e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ", 398e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR)); 399e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n", 400e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); 401e3ec7017SPing-Ke Shih } 402e3ec7017SPing-Ke Shih 403e3ec7017SPing-Ke Shih if (dmac_err & BIT(11)) { 404e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 405e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 406e3ec7017SPing-Ke Shih } 407e3ec7017SPing-Ke Shih 408e3ec7017SPing-Ke Shih if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 409e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ", 410e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR)); 411e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n", 412e3ec7017SPing-Ke Shih rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR)); 413e3ec7017SPing-Ke Shih } 414e3ec7017SPing-Ke Shih 415e3ec7017SPing-Ke Shih if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 416e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ", 417e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PTCL_IMR0)); 418e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n", 419e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); 420e3ec7017SPing-Ke Shih } 421e3ec7017SPing-Ke Shih 422e3ec7017SPing-Ke Shih if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 423e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n", 424e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_DLE_CTRL)); 425e3ec7017SPing-Ke Shih } 426e3ec7017SPing-Ke Shih 427e3ec7017SPing-Ke Shih if (cmac_err & B_AX_PHYINTF_ERR_IND) { 428e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n", 429e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR)); 430e3ec7017SPing-Ke Shih } 431e3ec7017SPing-Ke Shih 432e3ec7017SPing-Ke Shih if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 433e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ", 434e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPWR_IMR)); 435e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n", 436e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); 437e3ec7017SPing-Ke Shih } 438e3ec7017SPing-Ke Shih 439e3ec7017SPing-Ke Shih if (cmac_err & B_AX_WMAC_RX_ERR_IND) { 440e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ", 441e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); 442e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n", 443e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); 444e3ec7017SPing-Ke Shih } 445e3ec7017SPing-Ke Shih 446e3ec7017SPing-Ke Shih if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 447e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ", 448e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); 449e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n", 450e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); 451e3ec7017SPing-Ke Shih } 452e3ec7017SPing-Ke Shih 453e3ec7017SPing-Ke Shih rtwdev->hci.ops->dump_err_status(rtwdev); 454e3ec7017SPing-Ke Shih 455e3ec7017SPing-Ke Shih if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 456e3ec7017SPing-Ke Shih rtw89_mac_dump_l0_to_l1(rtwdev, err); 457e3ec7017SPing-Ke Shih 458e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "<---\n"); 459e3ec7017SPing-Ke Shih } 460e3ec7017SPing-Ke Shih 461e3ec7017SPing-Ke Shih u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 462e3ec7017SPing-Ke Shih { 463198b6cf7SZong-Zhe Yang u32 err, err_scnr; 464e3ec7017SPing-Ke Shih int ret; 465e3ec7017SPing-Ke Shih 466e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 467e3ec7017SPing-Ke Shih false, rtwdev, R_AX_HALT_C2H_CTRL); 468e3ec7017SPing-Ke Shih if (ret) { 469e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "Polling FW err status fail\n"); 470e3ec7017SPing-Ke Shih return ret; 471e3ec7017SPing-Ke Shih } 472e3ec7017SPing-Ke Shih 473e3ec7017SPing-Ke Shih err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 474e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 475e3ec7017SPing-Ke Shih 476198b6cf7SZong-Zhe Yang err_scnr = RTW89_ERROR_SCENARIO(err); 477198b6cf7SZong-Zhe Yang if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 478198b6cf7SZong-Zhe Yang err = MAC_AX_ERR_CPU_EXCEPTION; 479198b6cf7SZong-Zhe Yang else if (err_scnr == RTW89_WCPU_ASSERTION) 480198b6cf7SZong-Zhe Yang err = MAC_AX_ERR_ASSERTION; 481198b6cf7SZong-Zhe Yang 482e3ec7017SPing-Ke Shih rtw89_fw_st_dbg_dump(rtwdev); 483e3ec7017SPing-Ke Shih rtw89_mac_dump_err_status(rtwdev, err); 484e3ec7017SPing-Ke Shih 485e3ec7017SPing-Ke Shih return err; 486e3ec7017SPing-Ke Shih } 487e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_get_err_status); 488e3ec7017SPing-Ke Shih 489e3ec7017SPing-Ke Shih int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 490e3ec7017SPing-Ke Shih { 491e3ec7017SPing-Ke Shih u32 halt; 492e3ec7017SPing-Ke Shih int ret = 0; 493e3ec7017SPing-Ke Shih 494e3ec7017SPing-Ke Shih if (err > MAC_AX_SET_ERR_MAX) { 495e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 496e3ec7017SPing-Ke Shih return -EINVAL; 497e3ec7017SPing-Ke Shih } 498e3ec7017SPing-Ke Shih 499e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 500e3ec7017SPing-Ke Shih 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 501e3ec7017SPing-Ke Shih if (ret) { 502e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 503e3ec7017SPing-Ke Shih return -EFAULT; 504e3ec7017SPing-Ke Shih } 505e3ec7017SPing-Ke Shih 506e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 507e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 508e3ec7017SPing-Ke Shih 509e3ec7017SPing-Ke Shih return 0; 510e3ec7017SPing-Ke Shih } 511e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_set_err_status); 512e3ec7017SPing-Ke Shih 513e3ec7017SPing-Ke Shih static int hfc_reset_param(struct rtw89_dev *rtwdev) 514e3ec7017SPing-Ke Shih { 515e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 516e3ec7017SPing-Ke Shih struct rtw89_hfc_param_ini param_ini = {NULL}; 517e3ec7017SPing-Ke Shih u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 518e3ec7017SPing-Ke Shih 519e3ec7017SPing-Ke Shih switch (rtwdev->hci.type) { 520e3ec7017SPing-Ke Shih case RTW89_HCI_TYPE_PCIE: 521e3ec7017SPing-Ke Shih param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 522e3ec7017SPing-Ke Shih param->en = 0; 523e3ec7017SPing-Ke Shih break; 524e3ec7017SPing-Ke Shih default: 525e3ec7017SPing-Ke Shih return -EINVAL; 526e3ec7017SPing-Ke Shih } 527e3ec7017SPing-Ke Shih 528e3ec7017SPing-Ke Shih if (param_ini.pub_cfg) 529e3ec7017SPing-Ke Shih param->pub_cfg = *param_ini.pub_cfg; 530e3ec7017SPing-Ke Shih 531e3ec7017SPing-Ke Shih if (param_ini.prec_cfg) { 532e3ec7017SPing-Ke Shih param->prec_cfg = *param_ini.prec_cfg; 533e3ec7017SPing-Ke Shih rtwdev->hal.sw_amsdu_max_size = 534e3ec7017SPing-Ke Shih param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; 535e3ec7017SPing-Ke Shih } 536e3ec7017SPing-Ke Shih 537e3ec7017SPing-Ke Shih if (param_ini.ch_cfg) 538e3ec7017SPing-Ke Shih param->ch_cfg = param_ini.ch_cfg; 539e3ec7017SPing-Ke Shih 540e3ec7017SPing-Ke Shih memset(¶m->ch_info, 0, sizeof(param->ch_info)); 541e3ec7017SPing-Ke Shih memset(¶m->pub_info, 0, sizeof(param->pub_info)); 542e3ec7017SPing-Ke Shih param->mode = param_ini.mode; 543e3ec7017SPing-Ke Shih 544e3ec7017SPing-Ke Shih return 0; 545e3ec7017SPing-Ke Shih } 546e3ec7017SPing-Ke Shih 547e3ec7017SPing-Ke Shih static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 548e3ec7017SPing-Ke Shih { 549e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 550e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 551e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 552e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 553e3ec7017SPing-Ke Shih 554e3ec7017SPing-Ke Shih if (ch >= RTW89_DMA_CH_NUM) 555e3ec7017SPing-Ke Shih return -EINVAL; 556e3ec7017SPing-Ke Shih 557e3ec7017SPing-Ke Shih if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 558e3ec7017SPing-Ke Shih ch_cfg[ch].max > pub_cfg->pub_max) 559e3ec7017SPing-Ke Shih return -EINVAL; 560e3ec7017SPing-Ke Shih if (ch_cfg[ch].grp >= grp_num) 561e3ec7017SPing-Ke Shih return -EINVAL; 562e3ec7017SPing-Ke Shih 563e3ec7017SPing-Ke Shih return 0; 564e3ec7017SPing-Ke Shih } 565e3ec7017SPing-Ke Shih 566e3ec7017SPing-Ke Shih static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 567e3ec7017SPing-Ke Shih { 568e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 569e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 570e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 571e3ec7017SPing-Ke Shih 572e3ec7017SPing-Ke Shih if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 573e3ec7017SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852A) 574e3ec7017SPing-Ke Shih return 0; 575e3ec7017SPing-Ke Shih else 576e3ec7017SPing-Ke Shih return -EFAULT; 577e3ec7017SPing-Ke Shih } 578e3ec7017SPing-Ke Shih 579e3ec7017SPing-Ke Shih return 0; 580e3ec7017SPing-Ke Shih } 581e3ec7017SPing-Ke Shih 582e3ec7017SPing-Ke Shih static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 583e3ec7017SPing-Ke Shih { 584e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 585e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 586e3ec7017SPing-Ke Shih 587e3ec7017SPing-Ke Shih if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 588c6477cb2SKevin Lo return -EFAULT; 589e3ec7017SPing-Ke Shih 590e3ec7017SPing-Ke Shih return 0; 591e3ec7017SPing-Ke Shih } 592e3ec7017SPing-Ke Shih 593e3ec7017SPing-Ke Shih static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 594e3ec7017SPing-Ke Shih { 595ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 596ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 597e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 598e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 599e3ec7017SPing-Ke Shih int ret = 0; 600e3ec7017SPing-Ke Shih u32 val = 0; 601e3ec7017SPing-Ke Shih 602e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 603e3ec7017SPing-Ke Shih if (ret) 604e3ec7017SPing-Ke Shih return ret; 605e3ec7017SPing-Ke Shih 606e3ec7017SPing-Ke Shih ret = hfc_ch_cfg_chk(rtwdev, ch); 607e3ec7017SPing-Ke Shih if (ret) 608e3ec7017SPing-Ke Shih return ret; 609e3ec7017SPing-Ke Shih 610e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_B1HI) 611e3ec7017SPing-Ke Shih return -EINVAL; 612e3ec7017SPing-Ke Shih 613e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 614e3ec7017SPing-Ke Shih u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 615e3ec7017SPing-Ke Shih (cfg[ch].grp ? B_AX_GRP : 0); 616ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 617e3ec7017SPing-Ke Shih 618e3ec7017SPing-Ke Shih return 0; 619e3ec7017SPing-Ke Shih } 620e3ec7017SPing-Ke Shih 621e3ec7017SPing-Ke Shih static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 622e3ec7017SPing-Ke Shih { 623ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 624ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 625e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 626e3ec7017SPing-Ke Shih struct rtw89_hfc_ch_info *info = param->ch_info; 627e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 628e3ec7017SPing-Ke Shih u32 val; 629e3ec7017SPing-Ke Shih u32 ret; 630e3ec7017SPing-Ke Shih 631e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 632e3ec7017SPing-Ke Shih if (ret) 633e3ec7017SPing-Ke Shih return ret; 634e3ec7017SPing-Ke Shih 635e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_H2C) 636e3ec7017SPing-Ke Shih return -EINVAL; 637e3ec7017SPing-Ke Shih 638ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 639e3ec7017SPing-Ke Shih info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 640e3ec7017SPing-Ke Shih if (ch < RTW89_DMA_H2C) 641e3ec7017SPing-Ke Shih info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 642e3ec7017SPing-Ke Shih else 643e3ec7017SPing-Ke Shih info[ch].used = cfg[ch].min - info[ch].aval; 644e3ec7017SPing-Ke Shih 645e3ec7017SPing-Ke Shih return 0; 646e3ec7017SPing-Ke Shih } 647e3ec7017SPing-Ke Shih 648e3ec7017SPing-Ke Shih static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 649e3ec7017SPing-Ke Shih { 650ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 651ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 652e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 653e3ec7017SPing-Ke Shih u32 val; 654e3ec7017SPing-Ke Shih int ret; 655e3ec7017SPing-Ke Shih 656e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 657e3ec7017SPing-Ke Shih if (ret) 658e3ec7017SPing-Ke Shih return ret; 659e3ec7017SPing-Ke Shih 660e3ec7017SPing-Ke Shih ret = hfc_pub_cfg_chk(rtwdev); 661e3ec7017SPing-Ke Shih if (ret) 662e3ec7017SPing-Ke Shih return ret; 663e3ec7017SPing-Ke Shih 664e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 665e3ec7017SPing-Ke Shih u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 666ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 667e3ec7017SPing-Ke Shih 668e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 669ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 670e3ec7017SPing-Ke Shih 671e3ec7017SPing-Ke Shih return 0; 672e3ec7017SPing-Ke Shih } 673e3ec7017SPing-Ke Shih 674e3ec7017SPing-Ke Shih static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 675e3ec7017SPing-Ke Shih { 676ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 677ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 678e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 679e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 680e3ec7017SPing-Ke Shih struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 681e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 682e3ec7017SPing-Ke Shih u32 val; 683e3ec7017SPing-Ke Shih int ret; 684e3ec7017SPing-Ke Shih 685e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 686e3ec7017SPing-Ke Shih if (ret) 687e3ec7017SPing-Ke Shih return ret; 688e3ec7017SPing-Ke Shih 689ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_info1); 690e3ec7017SPing-Ke Shih info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 691e3ec7017SPing-Ke Shih info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 692ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_info3); 693e3ec7017SPing-Ke Shih info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 694e3ec7017SPing-Ke Shih info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 695e3ec7017SPing-Ke Shih info->pub_aval = 696ab8a5671SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 697e3ec7017SPing-Ke Shih B_AX_PUB_AVAL_PG_MASK); 698e3ec7017SPing-Ke Shih info->wp_aval = 699ab8a5671SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 700e3ec7017SPing-Ke Shih B_AX_WP_AVAL_PG_MASK); 701e3ec7017SPing-Ke Shih 702ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 703e3ec7017SPing-Ke Shih param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 704e3ec7017SPing-Ke Shih param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 705e3ec7017SPing-Ke Shih param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 706e3ec7017SPing-Ke Shih prec_cfg->ch011_full_cond = 707e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 708e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond = 709e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 710e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_full_cond = 711e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 712e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_full_cond = 713e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 714e3ec7017SPing-Ke Shih 715ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 716e3ec7017SPing-Ke Shih prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 717e3ec7017SPing-Ke Shih prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 718e3ec7017SPing-Ke Shih 719ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 720e3ec7017SPing-Ke Shih pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 721e3ec7017SPing-Ke Shih 722ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 723e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 724e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 725e3ec7017SPing-Ke Shih 726ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 727e3ec7017SPing-Ke Shih pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 728e3ec7017SPing-Ke Shih 729ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 730e3ec7017SPing-Ke Shih pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 731e3ec7017SPing-Ke Shih pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 732e3ec7017SPing-Ke Shih 733e3ec7017SPing-Ke Shih ret = hfc_pub_info_chk(rtwdev); 734e3ec7017SPing-Ke Shih if (param->en && ret) 735e3ec7017SPing-Ke Shih return ret; 736e3ec7017SPing-Ke Shih 737e3ec7017SPing-Ke Shih return 0; 738e3ec7017SPing-Ke Shih } 739e3ec7017SPing-Ke Shih 740e3ec7017SPing-Ke Shih static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 741e3ec7017SPing-Ke Shih { 742ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 743ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 744e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 745e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 746e3ec7017SPing-Ke Shih u32 val; 747e3ec7017SPing-Ke Shih 748e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 749ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 750e3ec7017SPing-Ke Shih 751ab8a5671SPing-Ke Shih rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 752e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK, 753e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond); 754e3ec7017SPing-Ke Shih } 755e3ec7017SPing-Ke Shih 756e3ec7017SPing-Ke Shih static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 757e3ec7017SPing-Ke Shih { 758ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 759ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 760e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 761e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 762e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 763e3ec7017SPing-Ke Shih u32 val; 764e3ec7017SPing-Ke Shih 765e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 766e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 767ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 768e3ec7017SPing-Ke Shih 769e3ec7017SPing-Ke Shih val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 770ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 771e3ec7017SPing-Ke Shih 772e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->wp_ch07_prec, 773e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH07_MASK) | 774e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->wp_ch811_prec, 775e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH811_MASK); 776ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 777e3ec7017SPing-Ke Shih 778ab8a5671SPing-Ke Shih val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 779e3ec7017SPing-Ke Shih param->mode, B_AX_HCI_FC_MODE_MASK); 780e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 781e3ec7017SPing-Ke Shih B_AX_HCI_FC_WD_FULL_COND_MASK); 782e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 783e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK); 784e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 785e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 786e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 787e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 788ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 789e3ec7017SPing-Ke Shih } 790e3ec7017SPing-Ke Shih 791e3ec7017SPing-Ke Shih static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 792e3ec7017SPing-Ke Shih { 793ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 794ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 795e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 796e3ec7017SPing-Ke Shih u32 val; 797e3ec7017SPing-Ke Shih 798ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 799e3ec7017SPing-Ke Shih param->en = en; 800e3ec7017SPing-Ke Shih param->h2c_en = h2c_en; 801e3ec7017SPing-Ke Shih val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 802e3ec7017SPing-Ke Shih val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 803e3ec7017SPing-Ke Shih (val & ~B_AX_HCI_FC_CH12_EN); 804ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 805e3ec7017SPing-Ke Shih } 806e3ec7017SPing-Ke Shih 807e3ec7017SPing-Ke Shih static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 808e3ec7017SPing-Ke Shih { 809e3ec7017SPing-Ke Shih u8 ch; 810e3ec7017SPing-Ke Shih u32 ret = 0; 811e3ec7017SPing-Ke Shih 812e3ec7017SPing-Ke Shih if (reset) 813e3ec7017SPing-Ke Shih ret = hfc_reset_param(rtwdev); 814e3ec7017SPing-Ke Shih if (ret) 815e3ec7017SPing-Ke Shih return ret; 816e3ec7017SPing-Ke Shih 817e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 818e3ec7017SPing-Ke Shih if (ret) 819e3ec7017SPing-Ke Shih return ret; 820e3ec7017SPing-Ke Shih 821e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, false, false); 822e3ec7017SPing-Ke Shih 823e3ec7017SPing-Ke Shih if (!en && h2c_en) { 824e3ec7017SPing-Ke Shih hfc_h2c_cfg(rtwdev); 825e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, en, h2c_en); 826e3ec7017SPing-Ke Shih return ret; 827e3ec7017SPing-Ke Shih } 828e3ec7017SPing-Ke Shih 829e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 830e3ec7017SPing-Ke Shih ret = hfc_ch_ctrl(rtwdev, ch); 831e3ec7017SPing-Ke Shih if (ret) 832e3ec7017SPing-Ke Shih return ret; 833e3ec7017SPing-Ke Shih } 834e3ec7017SPing-Ke Shih 835e3ec7017SPing-Ke Shih ret = hfc_pub_ctrl(rtwdev); 836e3ec7017SPing-Ke Shih if (ret) 837e3ec7017SPing-Ke Shih return ret; 838e3ec7017SPing-Ke Shih 839e3ec7017SPing-Ke Shih hfc_mix_cfg(rtwdev); 840e3ec7017SPing-Ke Shih if (en || h2c_en) { 841e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, en, h2c_en); 842e3ec7017SPing-Ke Shih udelay(10); 843e3ec7017SPing-Ke Shih } 844e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 845e3ec7017SPing-Ke Shih ret = hfc_upd_ch_info(rtwdev, ch); 846e3ec7017SPing-Ke Shih if (ret) 847e3ec7017SPing-Ke Shih return ret; 848e3ec7017SPing-Ke Shih } 849e3ec7017SPing-Ke Shih ret = hfc_upd_mix_info(rtwdev); 850e3ec7017SPing-Ke Shih 851e3ec7017SPing-Ke Shih return ret; 852e3ec7017SPing-Ke Shih } 853e3ec7017SPing-Ke Shih 854e3ec7017SPing-Ke Shih #define PWR_POLL_CNT 2000 855e3ec7017SPing-Ke Shih static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 856e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cfg) 857e3ec7017SPing-Ke Shih { 858e3ec7017SPing-Ke Shih u8 val = 0; 859e3ec7017SPing-Ke Shih int ret; 860e3ec7017SPing-Ke Shih u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 861e3ec7017SPing-Ke Shih cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 862e3ec7017SPing-Ke Shih 863e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 864e3ec7017SPing-Ke Shih 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 865e3ec7017SPing-Ke Shih 866e3ec7017SPing-Ke Shih if (!ret) 867e3ec7017SPing-Ke Shih return 0; 868e3ec7017SPing-Ke Shih 869e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 870e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 871e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 872e3ec7017SPing-Ke Shih 873e3ec7017SPing-Ke Shih return -EBUSY; 874e3ec7017SPing-Ke Shih } 875e3ec7017SPing-Ke Shih 876e3ec7017SPing-Ke Shih static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 877e3ec7017SPing-Ke Shih u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 878e3ec7017SPing-Ke Shih { 879e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cur_cfg; 880e3ec7017SPing-Ke Shih u32 addr; 881e3ec7017SPing-Ke Shih u8 val; 882e3ec7017SPing-Ke Shih 883e3ec7017SPing-Ke Shih for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 884e3ec7017SPing-Ke Shih if (!(cur_cfg->intf_msk & intf_msk) || 885e3ec7017SPing-Ke Shih !(cur_cfg->cv_msk & cv_msk)) 886e3ec7017SPing-Ke Shih continue; 887e3ec7017SPing-Ke Shih 888e3ec7017SPing-Ke Shih switch (cur_cfg->cmd) { 889e3ec7017SPing-Ke Shih case PWR_CMD_WRITE: 890e3ec7017SPing-Ke Shih addr = cur_cfg->addr; 891e3ec7017SPing-Ke Shih 892e3ec7017SPing-Ke Shih if (cur_cfg->base == PWR_BASE_SDIO) 893e3ec7017SPing-Ke Shih addr |= SDIO_LOCAL_BASE_ADDR; 894e3ec7017SPing-Ke Shih 895e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, addr); 896e3ec7017SPing-Ke Shih val &= ~(cur_cfg->msk); 897e3ec7017SPing-Ke Shih val |= (cur_cfg->val & cur_cfg->msk); 898e3ec7017SPing-Ke Shih 899e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, addr, val); 900e3ec7017SPing-Ke Shih break; 901e3ec7017SPing-Ke Shih case PWR_CMD_POLL: 902e3ec7017SPing-Ke Shih if (pwr_cmd_poll(rtwdev, cur_cfg)) 903e3ec7017SPing-Ke Shih return -EBUSY; 904e3ec7017SPing-Ke Shih break; 905e3ec7017SPing-Ke Shih case PWR_CMD_DELAY: 906e3ec7017SPing-Ke Shih if (cur_cfg->val == PWR_DELAY_US) 907e3ec7017SPing-Ke Shih udelay(cur_cfg->addr); 908e3ec7017SPing-Ke Shih else 909e3ec7017SPing-Ke Shih fsleep(cur_cfg->addr * 1000); 910e3ec7017SPing-Ke Shih break; 911e3ec7017SPing-Ke Shih default: 912e3ec7017SPing-Ke Shih return -EINVAL; 913e3ec7017SPing-Ke Shih } 914e3ec7017SPing-Ke Shih } 915e3ec7017SPing-Ke Shih 916e3ec7017SPing-Ke Shih return 0; 917e3ec7017SPing-Ke Shih } 918e3ec7017SPing-Ke Shih 919e3ec7017SPing-Ke Shih static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 920e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq) 921e3ec7017SPing-Ke Shih { 922e3ec7017SPing-Ke Shih int ret; 923e3ec7017SPing-Ke Shih 924e3ec7017SPing-Ke Shih for (; *cfg_seq; cfg_seq++) { 925e3ec7017SPing-Ke Shih ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 926e3ec7017SPing-Ke Shih PWR_INTF_MSK_PCIE, *cfg_seq); 927e3ec7017SPing-Ke Shih if (ret) 928e3ec7017SPing-Ke Shih return -EBUSY; 929e3ec7017SPing-Ke Shih } 930e3ec7017SPing-Ke Shih 931e3ec7017SPing-Ke Shih return 0; 932e3ec7017SPing-Ke Shih } 933e3ec7017SPing-Ke Shih 934e3ec7017SPing-Ke Shih static enum rtw89_rpwm_req_pwr_state 935e3ec7017SPing-Ke Shih rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 936e3ec7017SPing-Ke Shih { 937e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 938e3ec7017SPing-Ke Shih 939e3ec7017SPing-Ke Shih switch (rtwdev->ps_mode) { 940e3ec7017SPing-Ke Shih case RTW89_PS_MODE_RFOFF: 941e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 942e3ec7017SPing-Ke Shih break; 943e3ec7017SPing-Ke Shih case RTW89_PS_MODE_CLK_GATED: 944e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 945e3ec7017SPing-Ke Shih break; 946e3ec7017SPing-Ke Shih case RTW89_PS_MODE_PWR_GATED: 947e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 948e3ec7017SPing-Ke Shih break; 949e3ec7017SPing-Ke Shih default: 950e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 951e3ec7017SPing-Ke Shih break; 952e3ec7017SPing-Ke Shih } 953e3ec7017SPing-Ke Shih return state; 954e3ec7017SPing-Ke Shih } 955e3ec7017SPing-Ke Shih 956e3ec7017SPing-Ke Shih static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 9577bfd05ffSChin-Yen Lee enum rtw89_rpwm_req_pwr_state req_pwr_state, 9587bfd05ffSChin-Yen Lee bool notify_wake) 959e3ec7017SPing-Ke Shih { 960e3ec7017SPing-Ke Shih u16 request; 961e3ec7017SPing-Ke Shih 9627bfd05ffSChin-Yen Lee spin_lock_bh(&rtwdev->rpwm_lock); 9637bfd05ffSChin-Yen Lee 964e3ec7017SPing-Ke Shih request = rtw89_read16(rtwdev, R_AX_RPWM); 965e3ec7017SPing-Ke Shih request ^= request | PS_RPWM_TOGGLE; 9667bfd05ffSChin-Yen Lee request |= req_pwr_state; 967e3ec7017SPing-Ke Shih 9687bfd05ffSChin-Yen Lee if (notify_wake) { 9697bfd05ffSChin-Yen Lee request |= PS_RPWM_NOTIFY_WAKE; 9707bfd05ffSChin-Yen Lee } else { 971e3ec7017SPing-Ke Shih rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 972e3ec7017SPing-Ke Shih RPWM_SEQ_NUM_MAX; 9737bfd05ffSChin-Yen Lee request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 9747bfd05ffSChin-Yen Lee rtwdev->mac.rpwm_seq_num); 975e3ec7017SPing-Ke Shih 976e3ec7017SPing-Ke Shih if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 977e3ec7017SPing-Ke Shih request |= PS_RPWM_ACK; 9787bfd05ffSChin-Yen Lee } 979e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 9807bfd05ffSChin-Yen Lee 9817bfd05ffSChin-Yen Lee spin_unlock_bh(&rtwdev->rpwm_lock); 982e3ec7017SPing-Ke Shih } 983e3ec7017SPing-Ke Shih 984e3ec7017SPing-Ke Shih static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 985e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state req_pwr_state) 986e3ec7017SPing-Ke Shih { 987e3ec7017SPing-Ke Shih bool request_deep_mode; 988e3ec7017SPing-Ke Shih bool in_deep_mode; 989e3ec7017SPing-Ke Shih u8 rpwm_req_num; 990e3ec7017SPing-Ke Shih u8 cpwm_rsp_seq; 991e3ec7017SPing-Ke Shih u8 cpwm_seq; 992e3ec7017SPing-Ke Shih u8 cpwm_status; 993e3ec7017SPing-Ke Shih 994e3ec7017SPing-Ke Shih if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 995e3ec7017SPing-Ke Shih request_deep_mode = true; 996e3ec7017SPing-Ke Shih else 997e3ec7017SPing-Ke Shih request_deep_mode = false; 998e3ec7017SPing-Ke Shih 999e3ec7017SPing-Ke Shih if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1000e3ec7017SPing-Ke Shih in_deep_mode = true; 1001e3ec7017SPing-Ke Shih else 1002e3ec7017SPing-Ke Shih in_deep_mode = false; 1003e3ec7017SPing-Ke Shih 1004e3ec7017SPing-Ke Shih if (request_deep_mode != in_deep_mode) 1005e3ec7017SPing-Ke Shih return -EPERM; 1006e3ec7017SPing-Ke Shih 1007e3ec7017SPing-Ke Shih if (request_deep_mode) 1008e3ec7017SPing-Ke Shih return 0; 1009e3ec7017SPing-Ke Shih 1010e3ec7017SPing-Ke Shih rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1011e3ec7017SPing-Ke Shih cpwm_rsp_seq = rtw89_read16_mask(rtwdev, R_AX_CPWM, 1012e3ec7017SPing-Ke Shih PS_CPWM_RSP_SEQ_NUM); 1013e3ec7017SPing-Ke Shih 1014e3ec7017SPing-Ke Shih if (rpwm_req_num != cpwm_rsp_seq) 1015e3ec7017SPing-Ke Shih return -EPERM; 1016e3ec7017SPing-Ke Shih 1017e3ec7017SPing-Ke Shih rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1018e3ec7017SPing-Ke Shih CPWM_SEQ_NUM_MAX; 1019e3ec7017SPing-Ke Shih 1020e3ec7017SPing-Ke Shih cpwm_seq = rtw89_read16_mask(rtwdev, R_AX_CPWM, PS_CPWM_SEQ_NUM); 1021e3ec7017SPing-Ke Shih if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1022e3ec7017SPing-Ke Shih return -EPERM; 1023e3ec7017SPing-Ke Shih 1024e3ec7017SPing-Ke Shih cpwm_status = rtw89_read16_mask(rtwdev, R_AX_CPWM, PS_CPWM_STATE); 1025e3ec7017SPing-Ke Shih if (cpwm_status != req_pwr_state) 1026e3ec7017SPing-Ke Shih return -EPERM; 1027e3ec7017SPing-Ke Shih 1028e3ec7017SPing-Ke Shih return 0; 1029e3ec7017SPing-Ke Shih } 1030e3ec7017SPing-Ke Shih 1031e3ec7017SPing-Ke Shih void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1032e3ec7017SPing-Ke Shih { 1033e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 1034e3ec7017SPing-Ke Shih int ret; 1035e3ec7017SPing-Ke Shih 1036e3ec7017SPing-Ke Shih if (enter) 1037e3ec7017SPing-Ke Shih state = rtw89_mac_get_req_pwr_state(rtwdev); 1038e3ec7017SPing-Ke Shih else 1039e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1040e3ec7017SPing-Ke Shih 10417bfd05ffSChin-Yen Lee rtw89_mac_send_rpwm(rtwdev, state, false); 1042e3ec7017SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, !ret, 1043e3ec7017SPing-Ke Shih 1000, 15000, false, rtwdev, state); 1044e3ec7017SPing-Ke Shih if (ret) 1045e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1046e3ec7017SPing-Ke Shih enter ? "entering" : "leaving"); 1047e3ec7017SPing-Ke Shih } 1048e3ec7017SPing-Ke Shih 10497bfd05ffSChin-Yen Lee void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 10507bfd05ffSChin-Yen Lee { 10517bfd05ffSChin-Yen Lee enum rtw89_rpwm_req_pwr_state state; 10527bfd05ffSChin-Yen Lee 10537bfd05ffSChin-Yen Lee state = rtw89_mac_get_req_pwr_state(rtwdev); 10547bfd05ffSChin-Yen Lee rtw89_mac_send_rpwm(rtwdev, state, true); 10557bfd05ffSChin-Yen Lee } 10567bfd05ffSChin-Yen Lee 1057e3ec7017SPing-Ke Shih static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1058e3ec7017SPing-Ke Shih { 1059e3ec7017SPing-Ke Shih #define PWR_ACT 1 1060e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1061e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq; 10622a7e54dbSPing-Ke Shih int (*cfg_func)(struct rtw89_dev *rtwdev); 1063e3ec7017SPing-Ke Shih struct rtw89_hal *hal = &rtwdev->hal; 1064e3ec7017SPing-Ke Shih int ret; 1065e3ec7017SPing-Ke Shih u8 val; 1066e3ec7017SPing-Ke Shih 10672a7e54dbSPing-Ke Shih if (on) { 1068e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_on_seq; 10692a7e54dbSPing-Ke Shih cfg_func = chip->ops->pwr_on_func; 10702a7e54dbSPing-Ke Shih } else { 1071e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_off_seq; 10722a7e54dbSPing-Ke Shih cfg_func = chip->ops->pwr_off_func; 10732a7e54dbSPing-Ke Shih } 1074e3ec7017SPing-Ke Shih 1075e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1076e3ec7017SPing-Ke Shih __rtw89_leave_ps_mode(rtwdev); 1077e3ec7017SPing-Ke Shih 1078e3ec7017SPing-Ke Shih val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1079e3ec7017SPing-Ke Shih if (on && val == PWR_ACT) { 1080e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC has already powered on\n"); 1081e3ec7017SPing-Ke Shih return -EBUSY; 1082e3ec7017SPing-Ke Shih } 1083e3ec7017SPing-Ke Shih 10842a7e54dbSPing-Ke Shih ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1085e3ec7017SPing-Ke Shih if (ret) 1086e3ec7017SPing-Ke Shih return ret; 1087e3ec7017SPing-Ke Shih 1088e3ec7017SPing-Ke Shih if (on) { 1089e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1090e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1091e3ec7017SPing-Ke Shih } else { 1092e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1093e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1094e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1095e3ec7017SPing-Ke Shih hal->current_channel = 0; 1096e3ec7017SPing-Ke Shih } 1097e3ec7017SPing-Ke Shih 1098e3ec7017SPing-Ke Shih return 0; 1099e3ec7017SPing-Ke Shih #undef PWR_ACT 1100e3ec7017SPing-Ke Shih } 1101e3ec7017SPing-Ke Shih 1102e3ec7017SPing-Ke Shih void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1103e3ec7017SPing-Ke Shih { 1104e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 1105e3ec7017SPing-Ke Shih } 1106e3ec7017SPing-Ke Shih 1107e3ec7017SPing-Ke Shih static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1108e3ec7017SPing-Ke Shih { 1109e3ec7017SPing-Ke Shih u32 func_en = 0; 1110e3ec7017SPing-Ke Shih u32 ck_en = 0; 1111e3ec7017SPing-Ke Shih u32 c1pc_en = 0; 1112e3ec7017SPing-Ke Shih u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1113e3ec7017SPing-Ke Shih u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1114e3ec7017SPing-Ke Shih 1115e3ec7017SPing-Ke Shih func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1116e3ec7017SPing-Ke Shih B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1117e3ec7017SPing-Ke Shih B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN; 1118e3ec7017SPing-Ke Shih ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1119e3ec7017SPing-Ke Shih B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1120e3ec7017SPing-Ke Shih B_AX_RMAC_CKEN; 1121e3ec7017SPing-Ke Shih c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1122e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1123e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1124e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1125e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1126e3ec7017SPing-Ke Shih 1127e3ec7017SPing-Ke Shih if (en) { 1128e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1129e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1130e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1131e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1132e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1133e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1134e3ec7017SPing-Ke Shih } 1135e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1136e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1137e3ec7017SPing-Ke Shih } else { 1138e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1139e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1140e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1141e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1142e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1143e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1144e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1145e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1146e3ec7017SPing-Ke Shih } 1147e3ec7017SPing-Ke Shih } 1148e3ec7017SPing-Ke Shih 1149e3ec7017SPing-Ke Shih return 0; 1150e3ec7017SPing-Ke Shih } 1151e3ec7017SPing-Ke Shih 1152e3ec7017SPing-Ke Shih static int dmac_func_en(struct rtw89_dev *rtwdev) 1153e3ec7017SPing-Ke Shih { 1154828a4396SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1155e3ec7017SPing-Ke Shih u32 val32; 1156e3ec7017SPing-Ke Shih 1157828a4396SChia-Yuan Li if (chip_id == RTL8852C) 1158828a4396SChia-Yuan Li val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1159828a4396SChia-Yuan Li B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1160828a4396SChia-Yuan Li B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1161828a4396SChia-Yuan Li B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1162828a4396SChia-Yuan Li B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1163828a4396SChia-Yuan Li B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1164828a4396SChia-Yuan Li B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1165828a4396SChia-Yuan Li else 1166828a4396SChia-Yuan Li val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1167828a4396SChia-Yuan Li B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1168828a4396SChia-Yuan Li B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1169828a4396SChia-Yuan Li B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1170828a4396SChia-Yuan Li B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1171828a4396SChia-Yuan Li B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1172828a4396SChia-Yuan Li B_AX_DMAC_CRPRT); 1173e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1174e3ec7017SPing-Ke Shih 1175e3ec7017SPing-Ke Shih val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1176e3ec7017SPing-Ke Shih B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1177e3ec7017SPing-Ke Shih B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1178828a4396SChia-Yuan Li B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1179e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1180e3ec7017SPing-Ke Shih 118143863efeSChangcheng Deng return 0; 1182e3ec7017SPing-Ke Shih } 1183e3ec7017SPing-Ke Shih 1184e3ec7017SPing-Ke Shih static int chip_func_en(struct rtw89_dev *rtwdev) 1185e3ec7017SPing-Ke Shih { 1186828a4396SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1187828a4396SChia-Yuan Li 1188828a4396SChia-Yuan Li if (chip_id == RTL8852A) 1189828a4396SChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL0, 1190828a4396SChia-Yuan Li B_AX_OCP_L1_MASK); 1191e3ec7017SPing-Ke Shih 1192e3ec7017SPing-Ke Shih return 0; 1193e3ec7017SPing-Ke Shih } 1194e3ec7017SPing-Ke Shih 1195e3ec7017SPing-Ke Shih static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1196e3ec7017SPing-Ke Shih { 1197e3ec7017SPing-Ke Shih int ret; 1198e3ec7017SPing-Ke Shih 1199e3ec7017SPing-Ke Shih ret = dmac_func_en(rtwdev); 1200e3ec7017SPing-Ke Shih if (ret) 1201e3ec7017SPing-Ke Shih return ret; 1202e3ec7017SPing-Ke Shih 1203e3ec7017SPing-Ke Shih ret = cmac_func_en(rtwdev, 0, true); 1204e3ec7017SPing-Ke Shih if (ret) 1205e3ec7017SPing-Ke Shih return ret; 1206e3ec7017SPing-Ke Shih 1207e3ec7017SPing-Ke Shih ret = chip_func_en(rtwdev); 1208e3ec7017SPing-Ke Shih if (ret) 1209e3ec7017SPing-Ke Shih return ret; 1210e3ec7017SPing-Ke Shih 1211e3ec7017SPing-Ke Shih return ret; 1212e3ec7017SPing-Ke Shih } 1213e3ec7017SPing-Ke Shih 121430645118SPing-Ke Shih const struct rtw89_mac_size_set rtw89_mac_size = { 121530645118SPing-Ke Shih .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1216e3ec7017SPing-Ke Shih /* PCIE 64 */ 121730645118SPing-Ke Shih .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1218e3ec7017SPing-Ke Shih /* DLFW */ 121930645118SPing-Ke Shih .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 122079d099e0SPing-Ke Shih /* 8852C DLFW */ 122130645118SPing-Ke Shih .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 122279d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 122330645118SPing-Ke Shih .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1224e3ec7017SPing-Ke Shih /* PCIE */ 122530645118SPing-Ke Shih .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1226e3ec7017SPing-Ke Shih /* DLFW */ 122730645118SPing-Ke Shih .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 122879d099e0SPing-Ke Shih /* 8852C DLFW */ 122930645118SPing-Ke Shih .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 123079d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 123130645118SPing-Ke Shih .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1232e3ec7017SPing-Ke Shih /* PCIE 64 */ 123330645118SPing-Ke Shih .wde_qt0 = {3792, 196, 0, 107,}, 1234e3ec7017SPing-Ke Shih /* DLFW */ 123530645118SPing-Ke Shih .wde_qt4 = {0, 0, 0, 0,}, 123679d099e0SPing-Ke Shih /* 8852C DLFW */ 123730645118SPing-Ke Shih .wde_qt17 = {0, 0, 0, 0,}, 123879d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 123930645118SPing-Ke Shih .wde_qt18 = {3228, 60, 0, 40,}, 1240e3ec7017SPing-Ke Shih /* PCIE SCC */ 124130645118SPing-Ke Shih .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1242e3ec7017SPing-Ke Shih /* PCIE SCC */ 124330645118SPing-Ke Shih .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1244e3ec7017SPing-Ke Shih /* DLFW */ 124530645118SPing-Ke Shih .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 124679d099e0SPing-Ke Shih /* DLFW 52C */ 124730645118SPing-Ke Shih .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 124879d099e0SPing-Ke Shih /* DLFW 52C */ 124930645118SPing-Ke Shih .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 125079d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 125130645118SPing-Ke Shih .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 125279d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 125330645118SPing-Ke Shih .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 125479d099e0SPing-Ke Shih }; 125530645118SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_size); 125679d099e0SPing-Ke Shih 1257e3ec7017SPing-Ke Shih static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1258e3ec7017SPing-Ke Shih enum rtw89_qta_mode mode) 1259e3ec7017SPing-Ke Shih { 1260e3ec7017SPing-Ke Shih struct rtw89_mac_info *mac = &rtwdev->mac; 1261e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 1262e3ec7017SPing-Ke Shih 1263e3ec7017SPing-Ke Shih cfg = &rtwdev->chip->dle_mem[mode]; 1264e3ec7017SPing-Ke Shih if (!cfg) 1265e3ec7017SPing-Ke Shih return NULL; 1266e3ec7017SPing-Ke Shih 1267e3ec7017SPing-Ke Shih if (cfg->mode != mode) { 1268e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1269e3ec7017SPing-Ke Shih return NULL; 1270e3ec7017SPing-Ke Shih } 1271e3ec7017SPing-Ke Shih 1272e3ec7017SPing-Ke Shih mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; 1273e3ec7017SPing-Ke Shih mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1274e3ec7017SPing-Ke Shih mac->dle_info.qta_mode = mode; 1275e3ec7017SPing-Ke Shih mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1276e3ec7017SPing-Ke Shih mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1277e3ec7017SPing-Ke Shih 1278e3ec7017SPing-Ke Shih return cfg; 1279e3ec7017SPing-Ke Shih } 1280e3ec7017SPing-Ke Shih 1281e3ec7017SPing-Ke Shih static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1282e3ec7017SPing-Ke Shih const struct rtw89_dle_size *ple) 1283e3ec7017SPing-Ke Shih { 1284e3ec7017SPing-Ke Shih return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1285e3ec7017SPing-Ke Shih ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1286e3ec7017SPing-Ke Shih } 1287e3ec7017SPing-Ke Shih 1288e3ec7017SPing-Ke Shih static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1289e3ec7017SPing-Ke Shih { 1290e3ec7017SPing-Ke Shih if (enable) 1291e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1292e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1293e3ec7017SPing-Ke Shih else 1294e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1295e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1296e3ec7017SPing-Ke Shih } 1297e3ec7017SPing-Ke Shih 1298e3ec7017SPing-Ke Shih static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1299e3ec7017SPing-Ke Shih { 1300e3ec7017SPing-Ke Shih if (enable) 1301e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, 1302e3ec7017SPing-Ke Shih B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1303e3ec7017SPing-Ke Shih else 1304e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, 1305e3ec7017SPing-Ke Shih B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1306e3ec7017SPing-Ke Shih } 1307e3ec7017SPing-Ke Shih 1308e3ec7017SPing-Ke Shih static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1309e3ec7017SPing-Ke Shih { 1310e3ec7017SPing-Ke Shih const struct rtw89_dle_size *size_cfg; 1311e3ec7017SPing-Ke Shih u32 val; 1312e3ec7017SPing-Ke Shih u8 bound = 0; 1313e3ec7017SPing-Ke Shih 1314e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1315e3ec7017SPing-Ke Shih size_cfg = cfg->wde_size; 1316e3ec7017SPing-Ke Shih 1317e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1318e3ec7017SPing-Ke Shih default: 1319e3ec7017SPing-Ke Shih case RTW89_WDE_PG_64: 1320e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1321e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1322e3ec7017SPing-Ke Shih break; 1323e3ec7017SPing-Ke Shih case RTW89_WDE_PG_128: 1324e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1325e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1326e3ec7017SPing-Ke Shih break; 1327e3ec7017SPing-Ke Shih case RTW89_WDE_PG_256: 1328e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1329e3ec7017SPing-Ke Shih return -EINVAL; 1330e3ec7017SPing-Ke Shih } 1331e3ec7017SPing-Ke Shih 1332e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1333e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1334e3ec7017SPing-Ke Shih B_AX_WDE_FREE_PAGE_NUM_MASK); 1335e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1336e3ec7017SPing-Ke Shih 1337e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1338e3ec7017SPing-Ke Shih bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1339e3ec7017SPing-Ke Shih * size_cfg->pge_size / DLE_BOUND_UNIT; 1340e3ec7017SPing-Ke Shih size_cfg = cfg->ple_size; 1341e3ec7017SPing-Ke Shih 1342e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1343e3ec7017SPing-Ke Shih default: 1344e3ec7017SPing-Ke Shih case RTW89_PLE_PG_64: 1345e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1346e3ec7017SPing-Ke Shih return -EINVAL; 1347e3ec7017SPing-Ke Shih case RTW89_PLE_PG_128: 1348e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1349e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1350e3ec7017SPing-Ke Shih break; 1351e3ec7017SPing-Ke Shih case RTW89_PLE_PG_256: 1352e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1353e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1354e3ec7017SPing-Ke Shih break; 1355e3ec7017SPing-Ke Shih } 1356e3ec7017SPing-Ke Shih 1357e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1358e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1359e3ec7017SPing-Ke Shih B_AX_PLE_FREE_PAGE_NUM_MASK); 1360e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1361e3ec7017SPing-Ke Shih 1362e3ec7017SPing-Ke Shih return 0; 1363e3ec7017SPing-Ke Shih } 1364e3ec7017SPing-Ke Shih 1365e3ec7017SPing-Ke Shih #define INVALID_QT_WCPU U16_MAX 1366e3ec7017SPing-Ke Shih #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1367e3ec7017SPing-Ke Shih do { \ 1368e3ec7017SPing-Ke Shih val = ((_min_x) & \ 1369e3ec7017SPing-Ke Shih B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1370e3ec7017SPing-Ke Shih (((_max_x) << 16) & \ 1371e3ec7017SPing-Ke Shih B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1372e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, \ 1373e3ec7017SPing-Ke Shih R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1374e3ec7017SPing-Ke Shih val); \ 1375e3ec7017SPing-Ke Shih } while (0) 1376e3ec7017SPing-Ke Shih #define SET_QUOTA(_x, _module, _idx) \ 1377e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1378e3ec7017SPing-Ke Shih 1379e3ec7017SPing-Ke Shih static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1380e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *min_cfg, 1381e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *max_cfg, 1382e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 1383e3ec7017SPing-Ke Shih { 1384e3ec7017SPing-Ke Shih u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1385e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu : min_cfg->wcpu; 1386e3ec7017SPing-Ke Shih u32 val; 1387e3ec7017SPing-Ke Shih 1388e3ec7017SPing-Ke Shih SET_QUOTA(hif, WDE, 0); 1389e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1390e3ec7017SPing-Ke Shih SET_QUOTA(pkt_in, WDE, 3); 1391e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, WDE, 4); 1392e3ec7017SPing-Ke Shih } 1393e3ec7017SPing-Ke Shih 1394e3ec7017SPing-Ke Shih static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1395e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *min_cfg, 1396e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *max_cfg) 1397e3ec7017SPing-Ke Shih { 1398e3ec7017SPing-Ke Shih u32 val; 1399e3ec7017SPing-Ke Shih 1400e3ec7017SPing-Ke Shih SET_QUOTA(cma0_tx, PLE, 0); 1401e3ec7017SPing-Ke Shih SET_QUOTA(cma1_tx, PLE, 1); 1402e3ec7017SPing-Ke Shih SET_QUOTA(c2h, PLE, 2); 1403e3ec7017SPing-Ke Shih SET_QUOTA(h2c, PLE, 3); 1404e3ec7017SPing-Ke Shih SET_QUOTA(wcpu, PLE, 4); 1405e3ec7017SPing-Ke Shih SET_QUOTA(mpdu_proc, PLE, 5); 1406e3ec7017SPing-Ke Shih SET_QUOTA(cma0_dma, PLE, 6); 1407e3ec7017SPing-Ke Shih SET_QUOTA(cma1_dma, PLE, 7); 1408e3ec7017SPing-Ke Shih SET_QUOTA(bb_rpt, PLE, 8); 1409e3ec7017SPing-Ke Shih SET_QUOTA(wd_rel, PLE, 9); 1410e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, PLE, 10); 141179d099e0SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852C) 141279d099e0SPing-Ke Shih SET_QUOTA(tx_rpt, PLE, 11); 1413e3ec7017SPing-Ke Shih } 1414e3ec7017SPing-Ke Shih 1415e3ec7017SPing-Ke Shih #undef SET_QUOTA 1416e3ec7017SPing-Ke Shih 1417e3ec7017SPing-Ke Shih static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1418e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, 1419e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 1420e3ec7017SPing-Ke Shih { 1421e3ec7017SPing-Ke Shih wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1422e3ec7017SPing-Ke Shih ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1423e3ec7017SPing-Ke Shih } 1424e3ec7017SPing-Ke Shih 1425e3ec7017SPing-Ke Shih static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1426e3ec7017SPing-Ke Shih enum rtw89_qta_mode ext_mode) 1427e3ec7017SPing-Ke Shih { 1428e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, *ext_cfg; 1429e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1430e3ec7017SPing-Ke Shih int ret = 0; 1431e3ec7017SPing-Ke Shih u32 ini; 1432e3ec7017SPing-Ke Shih 1433e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1434e3ec7017SPing-Ke Shih if (ret) 1435e3ec7017SPing-Ke Shih return ret; 1436e3ec7017SPing-Ke Shih 1437e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 1438e3ec7017SPing-Ke Shih if (!cfg) { 1439e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1440e3ec7017SPing-Ke Shih ret = -EINVAL; 1441e3ec7017SPing-Ke Shih goto error; 1442e3ec7017SPing-Ke Shih } 1443e3ec7017SPing-Ke Shih 1444e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_DLFW) { 1445e3ec7017SPing-Ke Shih ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1446e3ec7017SPing-Ke Shih if (!ext_cfg) { 1447e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1448e3ec7017SPing-Ke Shih ext_mode); 1449e3ec7017SPing-Ke Shih ret = -EINVAL; 1450e3ec7017SPing-Ke Shih goto error; 1451e3ec7017SPing-Ke Shih } 1452e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1453e3ec7017SPing-Ke Shih } 1454e3ec7017SPing-Ke Shih 1455e3ec7017SPing-Ke Shih if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { 1456e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1457e3ec7017SPing-Ke Shih ret = -EINVAL; 1458e3ec7017SPing-Ke Shih goto error; 1459e3ec7017SPing-Ke Shih } 1460e3ec7017SPing-Ke Shih 1461e3ec7017SPing-Ke Shih dle_func_en(rtwdev, false); 1462e3ec7017SPing-Ke Shih dle_clk_en(rtwdev, true); 1463e3ec7017SPing-Ke Shih 1464e3ec7017SPing-Ke Shih ret = dle_mix_cfg(rtwdev, cfg); 1465e3ec7017SPing-Ke Shih if (ret) { 1466e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1467e3ec7017SPing-Ke Shih goto error; 1468e3ec7017SPing-Ke Shih } 1469e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1470e3ec7017SPing-Ke Shih 1471e3ec7017SPing-Ke Shih dle_func_en(rtwdev, true); 1472e3ec7017SPing-Ke Shih 1473e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, ini, 1474e3ec7017SPing-Ke Shih (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1475e3ec7017SPing-Ke Shih 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1476e3ec7017SPing-Ke Shih if (ret) { 1477e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1478e3ec7017SPing-Ke Shih return ret; 1479e3ec7017SPing-Ke Shih } 1480e3ec7017SPing-Ke Shih 1481e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, ini, 1482e3ec7017SPing-Ke Shih (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1483e3ec7017SPing-Ke Shih 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1484e3ec7017SPing-Ke Shih if (ret) { 1485e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1486e3ec7017SPing-Ke Shih return ret; 1487e3ec7017SPing-Ke Shih } 1488e3ec7017SPing-Ke Shih 1489e3ec7017SPing-Ke Shih return 0; 1490e3ec7017SPing-Ke Shih error: 1491e3ec7017SPing-Ke Shih dle_func_en(rtwdev, false); 1492e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1493e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1494e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1495e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1496e3ec7017SPing-Ke Shih 1497e3ec7017SPing-Ke Shih return ret; 1498e3ec7017SPing-Ke Shih } 1499e3ec7017SPing-Ke Shih 1500e07a9968SPing-Ke Shih static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1501e07a9968SPing-Ke Shih enum rtw89_qta_mode mode) 1502e07a9968SPing-Ke Shih { 1503e07a9968SPing-Ke Shih u32 reg, max_preld_size, min_rsvd_size; 1504e07a9968SPing-Ke Shih 1505e07a9968SPing-Ke Shih max_preld_size = (mac_idx == RTW89_MAC_0 ? 1506e07a9968SPing-Ke Shih PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1507e07a9968SPing-Ke Shih reg = mac_idx == RTW89_MAC_0 ? 1508e07a9968SPing-Ke Shih R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1509e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1510e07a9968SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1511e07a9968SPing-Ke Shih 1512e07a9968SPing-Ke Shih min_rsvd_size = PRELD_AMSDU_SIZE; 1513e07a9968SPing-Ke Shih reg = mac_idx == RTW89_MAC_0 ? 1514e07a9968SPing-Ke Shih R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1515e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1516e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1517e07a9968SPing-Ke Shih 1518e07a9968SPing-Ke Shih return 0; 1519e07a9968SPing-Ke Shih } 1520e07a9968SPing-Ke Shih 1521e07a9968SPing-Ke Shih static bool is_qta_poh(struct rtw89_dev *rtwdev) 1522e07a9968SPing-Ke Shih { 1523e07a9968SPing-Ke Shih return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1524e07a9968SPing-Ke Shih } 1525e07a9968SPing-Ke Shih 1526e07a9968SPing-Ke Shih static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1527e07a9968SPing-Ke Shih enum rtw89_qta_mode mode) 1528e07a9968SPing-Ke Shih { 1529e07a9968SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1530e07a9968SPing-Ke Shih 1531e07a9968SPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || !is_qta_poh(rtwdev)) 1532e07a9968SPing-Ke Shih return 0; 1533e07a9968SPing-Ke Shih 1534e07a9968SPing-Ke Shih return preload_init_set(rtwdev, mac_idx, mode); 1535e07a9968SPing-Ke Shih } 1536e07a9968SPing-Ke Shih 1537e3ec7017SPing-Ke Shih static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1538e3ec7017SPing-Ke Shih { 1539e3ec7017SPing-Ke Shih u32 msk32; 1540e3ec7017SPing-Ke Shih u32 val32; 1541e3ec7017SPing-Ke Shih 1542e3ec7017SPing-Ke Shih msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1543e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1544e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1545e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1546e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1547e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1548e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1549e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1550e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1551e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1552e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1553e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1554e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1555e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1556e3ec7017SPing-Ke Shih 1557e3ec7017SPing-Ke Shih if ((val32 & msk32) == msk32) 1558e3ec7017SPing-Ke Shih return true; 1559e3ec7017SPing-Ke Shih 1560e3ec7017SPing-Ke Shih return false; 1561e3ec7017SPing-Ke Shih } 1562e3ec7017SPing-Ke Shih 1563e3ec7017SPing-Ke Shih static int sta_sch_init(struct rtw89_dev *rtwdev) 1564e3ec7017SPing-Ke Shih { 1565e3ec7017SPing-Ke Shih u32 p_val; 1566e3ec7017SPing-Ke Shih u8 val; 1567e3ec7017SPing-Ke Shih int ret; 1568e3ec7017SPing-Ke Shih 1569e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1570e3ec7017SPing-Ke Shih if (ret) 1571e3ec7017SPing-Ke Shih return ret; 1572e3ec7017SPing-Ke Shih 1573e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1574e3ec7017SPing-Ke Shih val |= B_AX_SS_EN; 1575e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1576e3ec7017SPing-Ke Shih 1577e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1578e3ec7017SPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1579e3ec7017SPing-Ke Shih if (ret) { 1580e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1581e3ec7017SPing-Ke Shih return ret; 1582e3ec7017SPing-Ke Shih } 1583e3ec7017SPing-Ke Shih 1584e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 1585e3ec7017SPing-Ke Shih 1586e3ec7017SPing-Ke Shih return 0; 1587e3ec7017SPing-Ke Shih } 1588e3ec7017SPing-Ke Shih 1589e3ec7017SPing-Ke Shih static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1590e3ec7017SPing-Ke Shih { 1591e3ec7017SPing-Ke Shih int ret; 1592e3ec7017SPing-Ke Shih 1593e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1594e3ec7017SPing-Ke Shih if (ret) 1595e3ec7017SPing-Ke Shih return ret; 1596e3ec7017SPing-Ke Shih 1597e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1598e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1599e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1600e3ec7017SPing-Ke Shih B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1601e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1602e3ec7017SPing-Ke Shih 1603e3ec7017SPing-Ke Shih return 0; 1604e3ec7017SPing-Ke Shih } 1605e3ec7017SPing-Ke Shih 1606e3ec7017SPing-Ke Shih static int sec_eng_init(struct rtw89_dev *rtwdev) 1607e3ec7017SPing-Ke Shih { 1608e3ec7017SPing-Ke Shih u32 val = 0; 1609e3ec7017SPing-Ke Shih int ret; 1610e3ec7017SPing-Ke Shih 1611e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1612e3ec7017SPing-Ke Shih if (ret) 1613e3ec7017SPing-Ke Shih return ret; 1614e3ec7017SPing-Ke Shih 1615e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 1616e3ec7017SPing-Ke Shih /* init clock */ 1617e3ec7017SPing-Ke Shih val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 1618e3ec7017SPing-Ke Shih /* init TX encryption */ 1619e3ec7017SPing-Ke Shih val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 1620e3ec7017SPing-Ke Shih val |= (B_AX_MC_DEC | B_AX_BC_DEC); 1621e3ec7017SPing-Ke Shih val &= ~B_AX_TX_PARTIAL_MODE; 1622e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 1623e3ec7017SPing-Ke Shih 1624e3ec7017SPing-Ke Shih /* init MIC ICV append */ 1625e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 1626e3ec7017SPing-Ke Shih val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 1627e3ec7017SPing-Ke Shih 1628e3ec7017SPing-Ke Shih /* option init */ 1629e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 1630e3ec7017SPing-Ke Shih 1631e3ec7017SPing-Ke Shih return 0; 1632e3ec7017SPing-Ke Shih } 1633e3ec7017SPing-Ke Shih 1634e3ec7017SPing-Ke Shih static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1635e3ec7017SPing-Ke Shih { 1636e3ec7017SPing-Ke Shih int ret; 1637e3ec7017SPing-Ke Shih 1638e3ec7017SPing-Ke Shih ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 1639e3ec7017SPing-Ke Shih if (ret) { 1640e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 1641e3ec7017SPing-Ke Shih return ret; 1642e3ec7017SPing-Ke Shih } 1643e3ec7017SPing-Ke Shih 1644e07a9968SPing-Ke Shih ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 1645e07a9968SPing-Ke Shih if (ret) { 1646e07a9968SPing-Ke Shih rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 1647e07a9968SPing-Ke Shih return ret; 1648e07a9968SPing-Ke Shih } 1649e07a9968SPing-Ke Shih 1650e3ec7017SPing-Ke Shih ret = hfc_init(rtwdev, true, true, true); 1651e3ec7017SPing-Ke Shih if (ret) { 1652e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 1653e3ec7017SPing-Ke Shih return ret; 1654e3ec7017SPing-Ke Shih } 1655e3ec7017SPing-Ke Shih 1656e3ec7017SPing-Ke Shih ret = sta_sch_init(rtwdev); 1657e3ec7017SPing-Ke Shih if (ret) { 1658e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 1659e3ec7017SPing-Ke Shih return ret; 1660e3ec7017SPing-Ke Shih } 1661e3ec7017SPing-Ke Shih 1662e3ec7017SPing-Ke Shih ret = mpdu_proc_init(rtwdev); 1663e3ec7017SPing-Ke Shih if (ret) { 1664e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 1665e3ec7017SPing-Ke Shih return ret; 1666e3ec7017SPing-Ke Shih } 1667e3ec7017SPing-Ke Shih 1668e3ec7017SPing-Ke Shih ret = sec_eng_init(rtwdev); 1669e3ec7017SPing-Ke Shih if (ret) { 1670e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 1671e3ec7017SPing-Ke Shih return ret; 1672e3ec7017SPing-Ke Shih } 1673e3ec7017SPing-Ke Shih 1674e3ec7017SPing-Ke Shih return ret; 1675e3ec7017SPing-Ke Shih } 1676e3ec7017SPing-Ke Shih 1677e3ec7017SPing-Ke Shih static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1678e3ec7017SPing-Ke Shih { 1679e3ec7017SPing-Ke Shih u32 val, reg; 1680e3ec7017SPing-Ke Shih u16 p_val; 1681e3ec7017SPing-Ke Shih int ret; 1682e3ec7017SPing-Ke Shih 1683e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1684e3ec7017SPing-Ke Shih if (ret) 1685e3ec7017SPing-Ke Shih return ret; 1686e3ec7017SPing-Ke Shih 1687e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); 1688e3ec7017SPing-Ke Shih 1689e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1690e3ec7017SPing-Ke Shih val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 1691e3ec7017SPing-Ke Shih B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 1692e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1693e3ec7017SPing-Ke Shih 1694e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 1695e3ec7017SPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, B_AX_ADDR_CAM_CLR); 1696e3ec7017SPing-Ke Shih if (ret) { 1697e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 1698e3ec7017SPing-Ke Shih return ret; 1699e3ec7017SPing-Ke Shih } 1700e3ec7017SPing-Ke Shih 1701e3ec7017SPing-Ke Shih return 0; 1702e3ec7017SPing-Ke Shih } 1703e3ec7017SPing-Ke Shih 1704e3ec7017SPing-Ke Shih static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1705e3ec7017SPing-Ke Shih { 1706e3ec7017SPing-Ke Shih u32 ret; 1707e3ec7017SPing-Ke Shih u32 reg; 1708e3ec7017SPing-Ke Shih 1709e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1710e3ec7017SPing-Ke Shih if (ret) 1711e3ec7017SPing-Ke Shih return ret; 1712e3ec7017SPing-Ke Shih 1713e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); 1714e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, SCH_PREBKF_24US); 1715e3ec7017SPing-Ke Shih 1716e3ec7017SPing-Ke Shih return 0; 1717e3ec7017SPing-Ke Shih } 1718e3ec7017SPing-Ke Shih 1719e3ec7017SPing-Ke Shih static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 1720e3ec7017SPing-Ke Shih enum rtw89_machdr_frame_type type, 1721e3ec7017SPing-Ke Shih enum rtw89_mac_fwd_target fwd_target, 1722e3ec7017SPing-Ke Shih u8 mac_idx) 1723e3ec7017SPing-Ke Shih { 1724e3ec7017SPing-Ke Shih u32 reg; 1725e3ec7017SPing-Ke Shih u32 val; 1726e3ec7017SPing-Ke Shih 1727e3ec7017SPing-Ke Shih switch (fwd_target) { 1728e3ec7017SPing-Ke Shih case RTW89_FWD_DONT_CARE: 1729e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_DROP; 1730e3ec7017SPing-Ke Shih break; 1731e3ec7017SPing-Ke Shih case RTW89_FWD_TO_HOST: 1732e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_HOST; 1733e3ec7017SPing-Ke Shih break; 1734e3ec7017SPing-Ke Shih case RTW89_FWD_TO_WLAN_CPU: 1735e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_WLCPU; 1736e3ec7017SPing-Ke Shih break; 1737e3ec7017SPing-Ke Shih default: 1738e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 1739e3ec7017SPing-Ke Shih return -EINVAL; 1740e3ec7017SPing-Ke Shih } 1741e3ec7017SPing-Ke Shih 1742e3ec7017SPing-Ke Shih switch (type) { 1743e3ec7017SPing-Ke Shih case RTW89_MGNT: 1744e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); 1745e3ec7017SPing-Ke Shih break; 1746e3ec7017SPing-Ke Shih case RTW89_CTRL: 1747e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); 1748e3ec7017SPing-Ke Shih break; 1749e3ec7017SPing-Ke Shih case RTW89_DATA: 1750e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); 1751e3ec7017SPing-Ke Shih break; 1752e3ec7017SPing-Ke Shih default: 1753e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 1754e3ec7017SPing-Ke Shih return -EINVAL; 1755e3ec7017SPing-Ke Shih } 1756e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1757e3ec7017SPing-Ke Shih 1758e3ec7017SPing-Ke Shih return 0; 1759e3ec7017SPing-Ke Shih } 1760e3ec7017SPing-Ke Shih 1761e3ec7017SPing-Ke Shih static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1762e3ec7017SPing-Ke Shih { 1763e3ec7017SPing-Ke Shih int ret, i; 1764e3ec7017SPing-Ke Shih u32 mac_ftlr, plcp_ftlr; 1765e3ec7017SPing-Ke Shih 1766e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1767e3ec7017SPing-Ke Shih if (ret) 1768e3ec7017SPing-Ke Shih return ret; 1769e3ec7017SPing-Ke Shih 1770e3ec7017SPing-Ke Shih for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 1771e3ec7017SPing-Ke Shih ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 1772e3ec7017SPing-Ke Shih mac_idx); 1773e3ec7017SPing-Ke Shih if (ret) 1774e3ec7017SPing-Ke Shih return ret; 1775e3ec7017SPing-Ke Shih } 1776e3ec7017SPing-Ke Shih mac_ftlr = rtwdev->hal.rx_fltr; 1777e3ec7017SPing-Ke Shih plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 1778e3ec7017SPing-Ke Shih B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 1779e3ec7017SPing-Ke Shih B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 1780e3ec7017SPing-Ke Shih B_AX_HE_SIGB_CRC_CHK; 1781e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), 1782e3ec7017SPing-Ke Shih mac_ftlr); 1783e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), 1784e3ec7017SPing-Ke Shih plcp_ftlr); 1785e3ec7017SPing-Ke Shih 1786e3ec7017SPing-Ke Shih return 0; 1787e3ec7017SPing-Ke Shih } 1788e3ec7017SPing-Ke Shih 1789e3ec7017SPing-Ke Shih static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 1790e3ec7017SPing-Ke Shih { 1791e3ec7017SPing-Ke Shih u32 reg, val32; 1792e3ec7017SPing-Ke Shih u32 b_rsp_chk_nav, b_rsp_chk_cca; 1793e3ec7017SPing-Ke Shih 1794e3ec7017SPing-Ke Shih b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 1795e3ec7017SPing-Ke Shih B_AX_RSP_CHK_BASIC_NAV; 1796e3ec7017SPing-Ke Shih b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 1797e3ec7017SPing-Ke Shih B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 1798e3ec7017SPing-Ke Shih B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 1799e3ec7017SPing-Ke Shih 1800e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 1801e3ec7017SPing-Ke Shih case RTL8852A: 1802e3ec7017SPing-Ke Shih case RTL8852B: 1803e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 1804e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 1805e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 1806e3ec7017SPing-Ke Shih 1807e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1808e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 1809e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 1810e3ec7017SPing-Ke Shih break; 1811e3ec7017SPing-Ke Shih default: 1812e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 1813e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 1814e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 1815e3ec7017SPing-Ke Shih 1816e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1817e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 1818e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 1819e3ec7017SPing-Ke Shih break; 1820e3ec7017SPing-Ke Shih } 1821e3ec7017SPing-Ke Shih } 1822e3ec7017SPing-Ke Shih 1823e3ec7017SPing-Ke Shih static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1824e3ec7017SPing-Ke Shih { 1825e3ec7017SPing-Ke Shih u32 val, reg; 1826e3ec7017SPing-Ke Shih int ret; 1827e3ec7017SPing-Ke Shih 1828e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1829e3ec7017SPing-Ke Shih if (ret) 1830e3ec7017SPing-Ke Shih return ret; 1831e3ec7017SPing-Ke Shih 1832e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); 1833e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1834e3ec7017SPing-Ke Shih val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 1835e3ec7017SPing-Ke Shih B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 1836e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 1837e3ec7017SPing-Ke Shih B_AX_CTN_CHK_INTRA_NAV | 1838e3ec7017SPing-Ke Shih B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 1839e3ec7017SPing-Ke Shih B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 1840e3ec7017SPing-Ke Shih B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 1841e3ec7017SPing-Ke Shih B_AX_CTN_CHK_CCA_P20 | B_AX_SIFS_CHK_EDCCA); 1842e3ec7017SPing-Ke Shih val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 1843e3ec7017SPing-Ke Shih B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 1844e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 1845e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV); 1846e3ec7017SPing-Ke Shih 1847e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1848e3ec7017SPing-Ke Shih 1849e3ec7017SPing-Ke Shih _patch_dis_resp_chk(rtwdev, mac_idx); 1850e3ec7017SPing-Ke Shih 1851e3ec7017SPing-Ke Shih return 0; 1852e3ec7017SPing-Ke Shih } 1853e3ec7017SPing-Ke Shih 1854e3ec7017SPing-Ke Shih static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1855e3ec7017SPing-Ke Shih { 1856e3ec7017SPing-Ke Shih u32 reg; 1857e3ec7017SPing-Ke Shih int ret; 1858e3ec7017SPing-Ke Shih 1859e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1860e3ec7017SPing-Ke Shih if (ret) 1861e3ec7017SPing-Ke Shih return ret; 1862e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); 1863e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 1864e3ec7017SPing-Ke Shih 1865e3ec7017SPing-Ke Shih return 0; 1866e3ec7017SPing-Ke Shih } 1867e3ec7017SPing-Ke Shih 1868e3ec7017SPing-Ke Shih static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1869e3ec7017SPing-Ke Shih { 1870e3ec7017SPing-Ke Shih u32 reg; 1871e3ec7017SPing-Ke Shih int ret; 1872e3ec7017SPing-Ke Shih 1873e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1874e3ec7017SPing-Ke Shih if (ret) 1875e3ec7017SPing-Ke Shih return ret; 1876e3ec7017SPing-Ke Shih 1877e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); 1878e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 1879e3ec7017SPing-Ke Shih 1880e3ec7017SPing-Ke Shih return 0; 1881e3ec7017SPing-Ke Shih } 1882e3ec7017SPing-Ke Shih 1883e3ec7017SPing-Ke Shih static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1884e3ec7017SPing-Ke Shih { 1885e3ec7017SPing-Ke Shih u32 reg, val, sifs; 1886e3ec7017SPing-Ke Shih int ret; 1887e3ec7017SPing-Ke Shih 1888e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1889e3ec7017SPing-Ke Shih if (ret) 1890e3ec7017SPing-Ke Shih return ret; 1891e3ec7017SPing-Ke Shih 1892e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1893e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1894e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 1895e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 1896e3ec7017SPing-Ke Shih 1897e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 1898e3ec7017SPing-Ke Shih case RTL8852A: 1899e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52A; 1900e3ec7017SPing-Ke Shih break; 1901e3ec7017SPing-Ke Shih case RTL8852B: 1902e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52B; 1903e3ec7017SPing-Ke Shih break; 1904e3ec7017SPing-Ke Shih default: 1905e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52C; 1906e3ec7017SPing-Ke Shih break; 1907e3ec7017SPing-Ke Shih } 1908e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 1909e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 1910e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1911e3ec7017SPing-Ke Shih 1912e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); 1913e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 1914e3ec7017SPing-Ke Shih 1915e3ec7017SPing-Ke Shih return 0; 1916e3ec7017SPing-Ke Shih } 1917e3ec7017SPing-Ke Shih 1918e3ec7017SPing-Ke Shih static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1919e3ec7017SPing-Ke Shih { 1920e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_CCA_TO 32 1921e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_DATA_TO 15 1922e3ec7017SPing-Ke Shih #define RX_MAX_LEN_UNIT 512 1923e3ec7017SPing-Ke Shih #define PLD_RLS_MAX_PG 127 1924e3ec7017SPing-Ke Shih int ret; 1925e3ec7017SPing-Ke Shih u32 reg, rx_max_len, rx_qta; 1926e3ec7017SPing-Ke Shih u16 val; 1927e3ec7017SPing-Ke Shih 1928e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1929e3ec7017SPing-Ke Shih if (ret) 1930e3ec7017SPing-Ke Shih return ret; 1931e3ec7017SPing-Ke Shih 1932e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); 1933e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 1934e3ec7017SPing-Ke Shih 1935e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); 1936e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 1937e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 1938e3ec7017SPing-Ke Shih B_AX_RX_DLK_DATA_TIME_MASK); 1939e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 1940e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK); 1941e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 1942e3ec7017SPing-Ke Shih 1943e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); 1944e3ec7017SPing-Ke Shih rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 1945e3ec7017SPing-Ke Shih 1946e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); 1947e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_0) 1948e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 1949e3ec7017SPing-Ke Shih else 1950e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 1951e3ec7017SPing-Ke Shih rx_qta = rx_qta > PLD_RLS_MAX_PG ? PLD_RLS_MAX_PG : rx_qta; 1952e3ec7017SPing-Ke Shih rx_max_len = (rx_qta - 1) * rtwdev->mac.dle_info.ple_pg_size / 1953e3ec7017SPing-Ke Shih RX_MAX_LEN_UNIT; 1954e3ec7017SPing-Ke Shih rx_max_len = rx_max_len > B_AX_RX_MPDU_MAX_LEN_SIZE ? 1955e3ec7017SPing-Ke Shih B_AX_RX_MPDU_MAX_LEN_SIZE : rx_max_len; 1956e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 1957e3ec7017SPing-Ke Shih 1958e3ec7017SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852A && 1959e3ec7017SPing-Ke Shih rtwdev->hal.cv == CHIP_CBV) { 1960e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, 1961e3ec7017SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), 1962e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK, 0); 1963e3ec7017SPing-Ke Shih rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), 1964e3ec7017SPing-Ke Shih BIT(12)); 1965e3ec7017SPing-Ke Shih } 1966e3ec7017SPing-Ke Shih 1967e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); 1968e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 1969e3ec7017SPing-Ke Shih 1970e3ec7017SPing-Ke Shih return ret; 1971e3ec7017SPing-Ke Shih } 1972e3ec7017SPing-Ke Shih 1973e3ec7017SPing-Ke Shih static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1974e3ec7017SPing-Ke Shih { 1975e3ec7017SPing-Ke Shih u32 val, reg; 1976e3ec7017SPing-Ke Shih int ret; 1977e3ec7017SPing-Ke Shih 1978e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1979e3ec7017SPing-Ke Shih if (ret) 1980e3ec7017SPing-Ke Shih return ret; 1981e3ec7017SPing-Ke Shih 1982e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 1983e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1984e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 1985e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 1986e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 1987e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1988e3ec7017SPing-Ke Shih 1989e3ec7017SPing-Ke Shih return 0; 1990e3ec7017SPing-Ke Shih } 1991e3ec7017SPing-Ke Shih 1992e3ec7017SPing-Ke Shih static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 1993e3ec7017SPing-Ke Shih { 1994e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 1995e3ec7017SPing-Ke Shih 1996e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 1997e3ec7017SPing-Ke Shih if (!cfg) { 1998e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1999e3ec7017SPing-Ke Shih return false; 2000e3ec7017SPing-Ke Shih } 2001e3ec7017SPing-Ke Shih 2002e3ec7017SPing-Ke Shih return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2003e3ec7017SPing-Ke Shih } 2004e3ec7017SPing-Ke Shih 2005e3ec7017SPing-Ke Shih static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2006e3ec7017SPing-Ke Shih { 2007e3ec7017SPing-Ke Shih u32 val, reg; 2008e3ec7017SPing-Ke Shih int ret; 2009e3ec7017SPing-Ke Shih 2010e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2011e3ec7017SPing-Ke Shih if (ret) 2012e3ec7017SPing-Ke Shih return ret; 2013e3ec7017SPing-Ke Shih 2014e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2015e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2016e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2017e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2018e3ec7017SPing-Ke Shih B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2019e3ec7017SPing-Ke Shih val |= B_AX_HW_CTS2SELF_EN; 2020e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2021e3ec7017SPing-Ke Shih 2022e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); 2023e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2024e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2025e3ec7017SPing-Ke Shih val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2026e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2027e3ec7017SPing-Ke Shih } 2028e3ec7017SPing-Ke Shih 2029e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2030e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2031e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2032e3ec7017SPing-Ke Shih val |= B_AX_HW_CTS2SELF_EN; 2033e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2034e3ec7017SPing-Ke Shih 2035e3ec7017SPing-Ke Shih return 0; 2036e3ec7017SPing-Ke Shih } 2037e3ec7017SPing-Ke Shih 2038e3ec7017SPing-Ke Shih static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2039e3ec7017SPing-Ke Shih { 2040e3ec7017SPing-Ke Shih int ret; 2041e3ec7017SPing-Ke Shih 2042e3ec7017SPing-Ke Shih ret = scheduler_init(rtwdev, mac_idx); 2043e3ec7017SPing-Ke Shih if (ret) { 2044e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2045e3ec7017SPing-Ke Shih return ret; 2046e3ec7017SPing-Ke Shih } 2047e3ec7017SPing-Ke Shih 2048e3ec7017SPing-Ke Shih ret = addr_cam_init(rtwdev, mac_idx); 2049e3ec7017SPing-Ke Shih if (ret) { 2050e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2051e3ec7017SPing-Ke Shih ret); 2052e3ec7017SPing-Ke Shih return ret; 2053e3ec7017SPing-Ke Shih } 2054e3ec7017SPing-Ke Shih 2055e3ec7017SPing-Ke Shih ret = rx_fltr_init(rtwdev, mac_idx); 2056e3ec7017SPing-Ke Shih if (ret) { 2057e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2058e3ec7017SPing-Ke Shih ret); 2059e3ec7017SPing-Ke Shih return ret; 2060e3ec7017SPing-Ke Shih } 2061e3ec7017SPing-Ke Shih 2062e3ec7017SPing-Ke Shih ret = cca_ctrl_init(rtwdev, mac_idx); 2063e3ec7017SPing-Ke Shih if (ret) { 2064e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2065e3ec7017SPing-Ke Shih ret); 2066e3ec7017SPing-Ke Shih return ret; 2067e3ec7017SPing-Ke Shih } 2068e3ec7017SPing-Ke Shih 2069e3ec7017SPing-Ke Shih ret = spatial_reuse_init(rtwdev, mac_idx); 2070e3ec7017SPing-Ke Shih if (ret) { 2071e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2072e3ec7017SPing-Ke Shih mac_idx, ret); 2073e3ec7017SPing-Ke Shih return ret; 2074e3ec7017SPing-Ke Shih } 2075e3ec7017SPing-Ke Shih 2076e3ec7017SPing-Ke Shih ret = tmac_init(rtwdev, mac_idx); 2077e3ec7017SPing-Ke Shih if (ret) { 2078e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2079e3ec7017SPing-Ke Shih return ret; 2080e3ec7017SPing-Ke Shih } 2081e3ec7017SPing-Ke Shih 2082e3ec7017SPing-Ke Shih ret = trxptcl_init(rtwdev, mac_idx); 2083e3ec7017SPing-Ke Shih if (ret) { 2084e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2085e3ec7017SPing-Ke Shih return ret; 2086e3ec7017SPing-Ke Shih } 2087e3ec7017SPing-Ke Shih 2088e3ec7017SPing-Ke Shih ret = rmac_init(rtwdev, mac_idx); 2089e3ec7017SPing-Ke Shih if (ret) { 2090e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2091e3ec7017SPing-Ke Shih return ret; 2092e3ec7017SPing-Ke Shih } 2093e3ec7017SPing-Ke Shih 2094e3ec7017SPing-Ke Shih ret = cmac_com_init(rtwdev, mac_idx); 2095e3ec7017SPing-Ke Shih if (ret) { 2096e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2097e3ec7017SPing-Ke Shih return ret; 2098e3ec7017SPing-Ke Shih } 2099e3ec7017SPing-Ke Shih 2100e3ec7017SPing-Ke Shih ret = ptcl_init(rtwdev, mac_idx); 2101e3ec7017SPing-Ke Shih if (ret) { 2102e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2103e3ec7017SPing-Ke Shih return ret; 2104e3ec7017SPing-Ke Shih } 2105e3ec7017SPing-Ke Shih 2106e3ec7017SPing-Ke Shih return ret; 2107e3ec7017SPing-Ke Shih } 2108e3ec7017SPing-Ke Shih 2109e3ec7017SPing-Ke Shih static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2110e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info *c2h_info) 2111e3ec7017SPing-Ke Shih { 2112e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 2113e3ec7017SPing-Ke Shih u32 ret; 2114e3ec7017SPing-Ke Shih 2115e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2116e3ec7017SPing-Ke Shih h2c_info.content_len = 0; 2117e3ec7017SPing-Ke Shih 2118e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2119e3ec7017SPing-Ke Shih if (ret) 2120e3ec7017SPing-Ke Shih return ret; 2121e3ec7017SPing-Ke Shih 2122e3ec7017SPing-Ke Shih if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2123e3ec7017SPing-Ke Shih return -EINVAL; 2124e3ec7017SPing-Ke Shih 2125e3ec7017SPing-Ke Shih return 0; 2126e3ec7017SPing-Ke Shih } 2127e3ec7017SPing-Ke Shih 2128e3ec7017SPing-Ke Shih int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2129e3ec7017SPing-Ke Shih { 2130e3ec7017SPing-Ke Shih struct rtw89_hal *hal = &rtwdev->hal; 2131e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2132e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 2133e3ec7017SPing-Ke Shih struct rtw89_c2h_phy_cap *cap = 2134e3ec7017SPing-Ke Shih (struct rtw89_c2h_phy_cap *)&c2h_info.c2hreg[0]; 2135e3ec7017SPing-Ke Shih u32 ret; 2136e3ec7017SPing-Ke Shih 2137e3ec7017SPing-Ke Shih ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2138e3ec7017SPing-Ke Shih if (ret) 2139e3ec7017SPing-Ke Shih return ret; 2140e3ec7017SPing-Ke Shih 2141e3ec7017SPing-Ke Shih hal->tx_nss = cap->tx_nss ? 2142e3ec7017SPing-Ke Shih min_t(u8, cap->tx_nss, chip->tx_nss) : chip->tx_nss; 2143e3ec7017SPing-Ke Shih hal->rx_nss = cap->rx_nss ? 2144e3ec7017SPing-Ke Shih min_t(u8, cap->rx_nss, chip->rx_nss) : chip->rx_nss; 2145e3ec7017SPing-Ke Shih 2146e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 2147e3ec7017SPing-Ke Shih "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2148e3ec7017SPing-Ke Shih hal->tx_nss, cap->tx_nss, chip->tx_nss, 2149e3ec7017SPing-Ke Shih hal->rx_nss, cap->rx_nss, chip->rx_nss); 2150e3ec7017SPing-Ke Shih 2151e3ec7017SPing-Ke Shih return 0; 2152e3ec7017SPing-Ke Shih } 2153e3ec7017SPing-Ke Shih 2154e3ec7017SPing-Ke Shih static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2155e3ec7017SPing-Ke Shih u16 tx_en_u16, u16 mask_u16) 2156e3ec7017SPing-Ke Shih { 2157e3ec7017SPing-Ke Shih u32 ret; 2158e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 2159e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 2160e3ec7017SPing-Ke Shih struct rtw89_h2creg_sch_tx_en *h2creg = 2161e3ec7017SPing-Ke Shih (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; 2162e3ec7017SPing-Ke Shih 2163e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2164e3ec7017SPing-Ke Shih h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; 2165e3ec7017SPing-Ke Shih h2creg->tx_en = tx_en_u16; 2166e3ec7017SPing-Ke Shih h2creg->mask = mask_u16; 2167e3ec7017SPing-Ke Shih h2creg->band = band; 2168e3ec7017SPing-Ke Shih 2169e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2170e3ec7017SPing-Ke Shih if (ret) 2171e3ec7017SPing-Ke Shih return ret; 2172e3ec7017SPing-Ke Shih 2173e3ec7017SPing-Ke Shih if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2174e3ec7017SPing-Ke Shih return -EINVAL; 2175e3ec7017SPing-Ke Shih 2176e3ec7017SPing-Ke Shih return 0; 2177e3ec7017SPing-Ke Shih } 2178e3ec7017SPing-Ke Shih 2179e3ec7017SPing-Ke Shih static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2180e3ec7017SPing-Ke Shih u16 tx_en, u16 tx_en_mask) 2181e3ec7017SPing-Ke Shih { 2182e3ec7017SPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); 2183e3ec7017SPing-Ke Shih u16 val; 2184e3ec7017SPing-Ke Shih int ret; 2185e3ec7017SPing-Ke Shih 2186e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2187e3ec7017SPing-Ke Shih if (ret) 2188e3ec7017SPing-Ke Shih return ret; 2189e3ec7017SPing-Ke Shih 2190e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2191e3ec7017SPing-Ke Shih return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2192e3ec7017SPing-Ke Shih tx_en, tx_en_mask); 2193e3ec7017SPing-Ke Shih 2194e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 2195e3ec7017SPing-Ke Shih val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2196e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 2197e3ec7017SPing-Ke Shih 2198e3ec7017SPing-Ke Shih return 0; 2199e3ec7017SPing-Ke Shih } 2200e3ec7017SPing-Ke Shih 2201de7ba639SPing-Ke Shih static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2202de7ba639SPing-Ke Shih u32 tx_en, u32 tx_en_mask) 2203de7ba639SPing-Ke Shih { 2204de7ba639SPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx); 2205de7ba639SPing-Ke Shih u32 val; 2206de7ba639SPing-Ke Shih int ret; 2207de7ba639SPing-Ke Shih 2208de7ba639SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2209de7ba639SPing-Ke Shih if (ret) 2210de7ba639SPing-Ke Shih return ret; 2211de7ba639SPing-Ke Shih 2212de7ba639SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2213de7ba639SPing-Ke Shih val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2214de7ba639SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2215de7ba639SPing-Ke Shih 2216de7ba639SPing-Ke Shih return 0; 2217de7ba639SPing-Ke Shih } 2218de7ba639SPing-Ke Shih 2219e3ec7017SPing-Ke Shih int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2220d780f926SPing-Ke Shih u32 *tx_en, enum rtw89_sch_tx_sel sel) 2221e3ec7017SPing-Ke Shih { 2222e3ec7017SPing-Ke Shih int ret; 2223e3ec7017SPing-Ke Shih 2224e3ec7017SPing-Ke Shih *tx_en = rtw89_read16(rtwdev, 2225e3ec7017SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); 2226e3ec7017SPing-Ke Shih 2227e3ec7017SPing-Ke Shih switch (sel) { 2228e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_ALL: 2229de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2230de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK); 2231e3ec7017SPing-Ke Shih if (ret) 2232e3ec7017SPing-Ke Shih return ret; 2233e3ec7017SPing-Ke Shih break; 2234e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_HIQ: 2235e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2236e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_HGQ); 2237e3ec7017SPing-Ke Shih if (ret) 2238e3ec7017SPing-Ke Shih return ret; 2239e3ec7017SPing-Ke Shih break; 2240e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MG0: 2241e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2242e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_MGQ); 2243e3ec7017SPing-Ke Shih if (ret) 2244e3ec7017SPing-Ke Shih return ret; 2245e3ec7017SPing-Ke Shih break; 2246e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MACID: 2247de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2248de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK); 2249e3ec7017SPing-Ke Shih if (ret) 2250e3ec7017SPing-Ke Shih return ret; 2251e3ec7017SPing-Ke Shih break; 2252e3ec7017SPing-Ke Shih default: 2253e3ec7017SPing-Ke Shih return 0; 2254e3ec7017SPing-Ke Shih } 2255e3ec7017SPing-Ke Shih 2256e3ec7017SPing-Ke Shih return 0; 2257e3ec7017SPing-Ke Shih } 2258861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2259e3ec7017SPing-Ke Shih 2260de7ba639SPing-Ke Shih int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2261de7ba639SPing-Ke Shih u32 *tx_en, enum rtw89_sch_tx_sel sel) 2262de7ba639SPing-Ke Shih { 2263de7ba639SPing-Ke Shih int ret; 2264de7ba639SPing-Ke Shih 2265de7ba639SPing-Ke Shih *tx_en = rtw89_read32(rtwdev, 2266de7ba639SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx)); 2267de7ba639SPing-Ke Shih 2268de7ba639SPing-Ke Shih switch (sel) { 2269de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_ALL: 2270de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2271de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 2272de7ba639SPing-Ke Shih if (ret) 2273de7ba639SPing-Ke Shih return ret; 2274de7ba639SPing-Ke Shih break; 2275de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_HIQ: 2276de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2277de7ba639SPing-Ke Shih 0, B_AX_CTN_TXEN_HGQ); 2278de7ba639SPing-Ke Shih if (ret) 2279de7ba639SPing-Ke Shih return ret; 2280de7ba639SPing-Ke Shih break; 2281de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_MG0: 2282de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2283de7ba639SPing-Ke Shih 0, B_AX_CTN_TXEN_MGQ); 2284de7ba639SPing-Ke Shih if (ret) 2285de7ba639SPing-Ke Shih return ret; 2286de7ba639SPing-Ke Shih break; 2287de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_MACID: 2288de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2289de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 2290de7ba639SPing-Ke Shih if (ret) 2291de7ba639SPing-Ke Shih return ret; 2292de7ba639SPing-Ke Shih break; 2293de7ba639SPing-Ke Shih default: 2294de7ba639SPing-Ke Shih return 0; 2295de7ba639SPing-Ke Shih } 2296de7ba639SPing-Ke Shih 2297de7ba639SPing-Ke Shih return 0; 2298de7ba639SPing-Ke Shih } 2299de7ba639SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2300de7ba639SPing-Ke Shih 2301d780f926SPing-Ke Shih int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2302e3ec7017SPing-Ke Shih { 2303e3ec7017SPing-Ke Shih int ret; 2304e3ec7017SPing-Ke Shih 2305de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2306e3ec7017SPing-Ke Shih if (ret) 2307e3ec7017SPing-Ke Shih return ret; 2308e3ec7017SPing-Ke Shih 2309e3ec7017SPing-Ke Shih return 0; 2310e3ec7017SPing-Ke Shih } 2311861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2312e3ec7017SPing-Ke Shih 2313de7ba639SPing-Ke Shih int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2314de7ba639SPing-Ke Shih { 2315de7ba639SPing-Ke Shih int ret; 2316de7ba639SPing-Ke Shih 2317de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2318de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 2319de7ba639SPing-Ke Shih if (ret) 2320de7ba639SPing-Ke Shih return ret; 2321de7ba639SPing-Ke Shih 2322de7ba639SPing-Ke Shih return 0; 2323de7ba639SPing-Ke Shih } 2324de7ba639SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2325de7ba639SPing-Ke Shih 2326e3ec7017SPing-Ke Shih static u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, 2327e3ec7017SPing-Ke Shih bool wd) 2328e3ec7017SPing-Ke Shih { 2329e3ec7017SPing-Ke Shih u32 val, reg; 2330e3ec7017SPing-Ke Shih int ret; 2331e3ec7017SPing-Ke Shih 2332e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2333e3ec7017SPing-Ke Shih val = buf_len; 2334e3ec7017SPing-Ke Shih val |= B_AX_WD_BUF_REQ_EXEC; 2335e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2336e3ec7017SPing-Ke Shih 2337e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2338e3ec7017SPing-Ke Shih 2339e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2340e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 2341e3ec7017SPing-Ke Shih if (ret) 2342e3ec7017SPing-Ke Shih return 0xffff; 2343e3ec7017SPing-Ke Shih 2344e3ec7017SPing-Ke Shih return FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2345e3ec7017SPing-Ke Shih } 2346e3ec7017SPing-Ke Shih 2347e3ec7017SPing-Ke Shih static int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2348e3ec7017SPing-Ke Shih struct rtw89_cpuio_ctrl *ctrl_para, 2349e3ec7017SPing-Ke Shih bool wd) 2350e3ec7017SPing-Ke Shih { 2351e3ec7017SPing-Ke Shih u32 val, cmd_type, reg; 2352e3ec7017SPing-Ke Shih int ret; 2353e3ec7017SPing-Ke Shih 2354e3ec7017SPing-Ke Shih cmd_type = ctrl_para->cmd_type; 2355e3ec7017SPing-Ke Shih 2356e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2357e3ec7017SPing-Ke Shih val = 0; 2358e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->start_pktid, 2359e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2360e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->end_pktid, 2361e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2362e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2363e3ec7017SPing-Ke Shih 2364e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2365e3ec7017SPing-Ke Shih val = 0; 2366e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_pid, 2367e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_PID_MASK); 2368e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_qid, 2369e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_QID_MASK); 2370e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_pid, 2371e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_PID_MASK); 2372e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_qid, 2373e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_QID_MASK); 2374e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2375e3ec7017SPing-Ke Shih 2376e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2377e3ec7017SPing-Ke Shih val = 0; 2378e3ec7017SPing-Ke Shih val = u32_replace_bits(val, cmd_type, 2379e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_CMD_TYPE_MASK); 2380e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->macid, 2381e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_MACID_MASK); 2382e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->pkt_num, 2383e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_PKTNUM_MASK); 2384e3ec7017SPing-Ke Shih val |= B_AX_WD_CPUQ_OP_EXEC; 2385e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2386e3ec7017SPing-Ke Shih 2387e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2388e3ec7017SPing-Ke Shih 2389e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2390e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 2391e3ec7017SPing-Ke Shih if (ret) 2392e3ec7017SPing-Ke Shih return ret; 2393e3ec7017SPing-Ke Shih 2394e3ec7017SPing-Ke Shih if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2395e3ec7017SPing-Ke Shih cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2396e3ec7017SPing-Ke Shih ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2397e3ec7017SPing-Ke Shih 2398e3ec7017SPing-Ke Shih return 0; 2399e3ec7017SPing-Ke Shih } 2400e3ec7017SPing-Ke Shih 2401e3ec7017SPing-Ke Shih static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2402e3ec7017SPing-Ke Shih { 2403e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 2404e3ec7017SPing-Ke Shih struct rtw89_cpuio_ctrl ctrl_para = {0}; 2405e3ec7017SPing-Ke Shih u16 pkt_id; 2406e3ec7017SPing-Ke Shih int ret; 2407e3ec7017SPing-Ke Shih 2408e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 2409e3ec7017SPing-Ke Shih if (!cfg) { 2410e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2411e3ec7017SPing-Ke Shih return -EINVAL; 2412e3ec7017SPing-Ke Shih } 2413e3ec7017SPing-Ke Shih 2414e3ec7017SPing-Ke Shih if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { 2415e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2416e3ec7017SPing-Ke Shih return -EINVAL; 2417e3ec7017SPing-Ke Shih } 2418e3ec7017SPing-Ke Shih 2419e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2420e3ec7017SPing-Ke Shih 2421e3ec7017SPing-Ke Shih pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true); 2422e3ec7017SPing-Ke Shih if (pkt_id == 0xffff) { 2423e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2424e3ec7017SPing-Ke Shih return -ENOMEM; 2425e3ec7017SPing-Ke Shih } 2426e3ec7017SPing-Ke Shih 2427e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2428e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 2429e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 2430e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 2431e3ec7017SPing-Ke Shih ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2432e3ec7017SPing-Ke Shih ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2433e3ec7017SPing-Ke Shih ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2434e3ec7017SPing-Ke Shih if (ret) { 2435e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2436e3ec7017SPing-Ke Shih return -EFAULT; 2437e3ec7017SPing-Ke Shih } 2438e3ec7017SPing-Ke Shih 2439e3ec7017SPing-Ke Shih pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, false); 2440e3ec7017SPing-Ke Shih if (pkt_id == 0xffff) { 2441e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2442e3ec7017SPing-Ke Shih return -ENOMEM; 2443e3ec7017SPing-Ke Shih } 2444e3ec7017SPing-Ke Shih 2445e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2446e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 2447e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 2448e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 2449e3ec7017SPing-Ke Shih ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 2450e3ec7017SPing-Ke Shih ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 2451e3ec7017SPing-Ke Shih ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 2452e3ec7017SPing-Ke Shih if (ret) { 2453e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 2454e3ec7017SPing-Ke Shih return -EFAULT; 2455e3ec7017SPing-Ke Shih } 2456e3ec7017SPing-Ke Shih 2457e3ec7017SPing-Ke Shih return 0; 2458e3ec7017SPing-Ke Shih } 2459e3ec7017SPing-Ke Shih 2460e3ec7017SPing-Ke Shih static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 2461e3ec7017SPing-Ke Shih { 2462e3ec7017SPing-Ke Shih int ret; 2463e3ec7017SPing-Ke Shih u32 reg; 2464e3ec7017SPing-Ke Shih u8 val; 2465e3ec7017SPing-Ke Shih 2466e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2467e3ec7017SPing-Ke Shih if (ret) 2468e3ec7017SPing-Ke Shih return ret; 2469e3ec7017SPing-Ke Shih 2470e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); 2471e3ec7017SPing-Ke Shih 2472e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, 2473e3ec7017SPing-Ke Shih (val & B_AX_PTCL_TX_ON_STAT) == 0, 2474e3ec7017SPing-Ke Shih SW_CVR_DUR_US, 2475e3ec7017SPing-Ke Shih SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 2476e3ec7017SPing-Ke Shih false, rtwdev, reg); 2477e3ec7017SPing-Ke Shih if (ret) 2478e3ec7017SPing-Ke Shih return ret; 2479e3ec7017SPing-Ke Shih 2480e3ec7017SPing-Ke Shih return 0; 2481e3ec7017SPing-Ke Shih } 2482e3ec7017SPing-Ke Shih 2483e3ec7017SPing-Ke Shih static int band1_enable(struct rtw89_dev *rtwdev) 2484e3ec7017SPing-Ke Shih { 2485e3ec7017SPing-Ke Shih int ret, i; 2486e3ec7017SPing-Ke Shih u32 sleep_bak[4] = {0}; 2487e3ec7017SPing-Ke Shih u32 pause_bak[4] = {0}; 2488d780f926SPing-Ke Shih u32 tx_en; 2489e3ec7017SPing-Ke Shih 2490de7ba639SPing-Ke Shih ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 2491e3ec7017SPing-Ke Shih if (ret) { 2492e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 2493e3ec7017SPing-Ke Shih return ret; 2494e3ec7017SPing-Ke Shih } 2495e3ec7017SPing-Ke Shih 2496e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 2497e3ec7017SPing-Ke Shih sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 2498e3ec7017SPing-Ke Shih pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 2499e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 2500e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 2501e3ec7017SPing-Ke Shih } 2502e3ec7017SPing-Ke Shih 2503e3ec7017SPing-Ke Shih ret = band_idle_ck_b(rtwdev, 0); 2504e3ec7017SPing-Ke Shih if (ret) { 2505e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 2506e3ec7017SPing-Ke Shih return ret; 2507e3ec7017SPing-Ke Shih } 2508e3ec7017SPing-Ke Shih 2509e3ec7017SPing-Ke Shih ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 2510e3ec7017SPing-Ke Shih if (ret) { 2511e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 2512e3ec7017SPing-Ke Shih return ret; 2513e3ec7017SPing-Ke Shih } 2514e3ec7017SPing-Ke Shih 2515e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 2516e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 2517e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 2518e3ec7017SPing-Ke Shih } 2519e3ec7017SPing-Ke Shih 2520de7ba639SPing-Ke Shih ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 2521e3ec7017SPing-Ke Shih if (ret) { 2522e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 2523e3ec7017SPing-Ke Shih return ret; 2524e3ec7017SPing-Ke Shih } 2525e3ec7017SPing-Ke Shih 2526e3ec7017SPing-Ke Shih ret = cmac_func_en(rtwdev, 1, true); 2527e3ec7017SPing-Ke Shih if (ret) { 2528e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 2529e3ec7017SPing-Ke Shih return ret; 2530e3ec7017SPing-Ke Shih } 2531e3ec7017SPing-Ke Shih 2532e3ec7017SPing-Ke Shih ret = cmac_init(rtwdev, 1); 2533e3ec7017SPing-Ke Shih if (ret) { 2534e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 2535e3ec7017SPing-Ke Shih return ret; 2536e3ec7017SPing-Ke Shih } 2537e3ec7017SPing-Ke Shih 2538e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 2539e3ec7017SPing-Ke Shih B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 2540e3ec7017SPing-Ke Shih 2541e3ec7017SPing-Ke Shih return 0; 2542e3ec7017SPing-Ke Shih } 2543e3ec7017SPing-Ke Shih 2544e3ec7017SPing-Ke Shih static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 2545e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 2546e3ec7017SPing-Ke Shih { 2547e3ec7017SPing-Ke Shih u32 reg, val; 2548e3ec7017SPing-Ke Shih int ret; 2549e3ec7017SPing-Ke Shih 2550e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 2551e3ec7017SPing-Ke Shih if (ret) { 2552e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 2553e3ec7017SPing-Ke Shih sel, mac_idx); 2554e3ec7017SPing-Ke Shih return ret; 2555e3ec7017SPing-Ke Shih } 2556e3ec7017SPing-Ke Shih 2557e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 2558e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR, 2559e3ec7017SPing-Ke Shih B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | 2560e3ec7017SPing-Ke Shih B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | 2561e3ec7017SPing-Ke Shih B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN); 2562e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 2563e3ec7017SPing-Ke Shih B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | 2564e3ec7017SPing-Ke Shih B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN); 2565e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 2566e3ec7017SPing-Ke Shih B_AX_HDT_PKT_FAIL_DBG_INT_EN | 2567e3ec7017SPing-Ke Shih B_AX_HDT_OFFSET_UNMATCH_INT_EN); 2568e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 2569e3ec7017SPing-Ke Shih B_AX_CPU_SHIFT_EN_ERR_INT_EN); 2570e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, 2571e3ec7017SPing-Ke Shih B_AX_PLE_GETNPG_STRPG_ERR_INT_EN); 2572e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, 2573e3ec7017SPing-Ke Shih B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN); 2574e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_HD0IMR, B_AX_WDT_PTFM_INT_EN); 2575e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR, 2576e3ec7017SPing-Ke Shih B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN); 2577e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL) { 2578e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); 2579e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, 2580e3ec7017SPing-Ke Shih B_AX_SORT_NON_IDLE_ERR_INT_EN); 2581e3ec7017SPing-Ke Shih 2582e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_DLE_CTRL, mac_idx); 2583e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, 2584e3ec7017SPing-Ke Shih B_AX_NO_RESERVE_PAGE_ERR_IMR | 2585e3ec7017SPing-Ke Shih B_AX_RXDATA_FSM_HANG_ERROR_IMR); 2586e3ec7017SPing-Ke Shih 2587e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); 2588e3ec7017SPing-Ke Shih val = B_AX_F2PCMD_USER_ALLC_ERR_INT_EN | 2589e3ec7017SPing-Ke Shih B_AX_TX_RECORD_PKTID_ERR_INT_EN | 2590e3ec7017SPing-Ke Shih B_AX_FSM_TIMEOUT_ERR_INT_EN; 2591e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2592e3ec7017SPing-Ke Shih 2593e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PHYINFO_ERR_IMR, mac_idx); 2594e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, 2595e3ec7017SPing-Ke Shih B_AX_PHY_TXON_TIMEOUT_INT_EN | 2596e3ec7017SPing-Ke Shih B_AX_CCK_CCA_TIMEOUT_INT_EN | 2597e3ec7017SPing-Ke Shih B_AX_OFDM_CCA_TIMEOUT_INT_EN | 2598e3ec7017SPing-Ke Shih B_AX_DATA_ON_TIMEOUT_INT_EN | 2599e3ec7017SPing-Ke Shih B_AX_STS_ON_TIMEOUT_INT_EN | 2600e3ec7017SPing-Ke Shih B_AX_CSI_ON_TIMEOUT_INT_EN); 2601e3ec7017SPing-Ke Shih 2602e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RMAC_ERR_ISR, mac_idx); 2603e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2604e3ec7017SPing-Ke Shih val |= (B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN | 2605e3ec7017SPing-Ke Shih B_AX_RMAC_RX_TIMEOUT_INT_EN | 2606e3ec7017SPing-Ke Shih B_AX_RMAC_CSI_TIMEOUT_INT_EN); 2607e3ec7017SPing-Ke Shih val &= ~(B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN | 2608e3ec7017SPing-Ke Shih B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN | 2609e3ec7017SPing-Ke Shih B_AX_RMAC_CCA_TIMEOUT_INT_EN | 2610e3ec7017SPing-Ke Shih B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN); 2611e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2612e3ec7017SPing-Ke Shih } else { 2613e3ec7017SPing-Ke Shih return -EINVAL; 2614e3ec7017SPing-Ke Shih } 2615e3ec7017SPing-Ke Shih 2616e3ec7017SPing-Ke Shih return 0; 2617e3ec7017SPing-Ke Shih } 2618e3ec7017SPing-Ke Shih 2619e3ec7017SPing-Ke Shih static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 2620e3ec7017SPing-Ke Shih { 2621e3ec7017SPing-Ke Shih int ret = 0; 2622e3ec7017SPing-Ke Shih 2623e3ec7017SPing-Ke Shih if (enable) { 2624e3ec7017SPing-Ke Shih ret = band1_enable(rtwdev); 2625e3ec7017SPing-Ke Shih if (ret) { 2626e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 2627e3ec7017SPing-Ke Shih return ret; 2628e3ec7017SPing-Ke Shih } 2629e3ec7017SPing-Ke Shih 2630e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 2631e3ec7017SPing-Ke Shih if (ret) { 2632e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 2633e3ec7017SPing-Ke Shih return ret; 2634e3ec7017SPing-Ke Shih } 2635e3ec7017SPing-Ke Shih } else { 2636e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 2637e3ec7017SPing-Ke Shih return -EINVAL; 2638e3ec7017SPing-Ke Shih } 2639e3ec7017SPing-Ke Shih 2640e3ec7017SPing-Ke Shih return 0; 2641e3ec7017SPing-Ke Shih } 2642e3ec7017SPing-Ke Shih 2643e3ec7017SPing-Ke Shih static int set_host_rpr(struct rtw89_dev *rtwdev) 2644e3ec7017SPing-Ke Shih { 2645e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2646e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 2647e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 2648e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 2649e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 2650e3ec7017SPing-Ke Shih } else { 2651e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 2652e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 2653e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 2654e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 2655e3ec7017SPing-Ke Shih } 2656e3ec7017SPing-Ke Shih 2657e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 2658e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 2659e3ec7017SPing-Ke Shih 2660e3ec7017SPing-Ke Shih return 0; 2661e3ec7017SPing-Ke Shih } 2662e3ec7017SPing-Ke Shih 2663e3ec7017SPing-Ke Shih static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 2664e3ec7017SPing-Ke Shih { 2665e3ec7017SPing-Ke Shih enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 2666e3ec7017SPing-Ke Shih int ret; 2667e3ec7017SPing-Ke Shih 2668e3ec7017SPing-Ke Shih ret = dmac_init(rtwdev, 0); 2669e3ec7017SPing-Ke Shih if (ret) { 2670e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 2671e3ec7017SPing-Ke Shih return ret; 2672e3ec7017SPing-Ke Shih } 2673e3ec7017SPing-Ke Shih 2674e3ec7017SPing-Ke Shih ret = cmac_init(rtwdev, 0); 2675e3ec7017SPing-Ke Shih if (ret) { 2676e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 2677e3ec7017SPing-Ke Shih return ret; 2678e3ec7017SPing-Ke Shih } 2679e3ec7017SPing-Ke Shih 2680e3ec7017SPing-Ke Shih if (is_qta_dbcc(rtwdev, qta_mode)) { 2681e3ec7017SPing-Ke Shih ret = rtw89_mac_dbcc_enable(rtwdev, true); 2682e3ec7017SPing-Ke Shih if (ret) { 2683e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 2684e3ec7017SPing-Ke Shih return ret; 2685e3ec7017SPing-Ke Shih } 2686e3ec7017SPing-Ke Shih } 2687e3ec7017SPing-Ke Shih 2688e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2689e3ec7017SPing-Ke Shih if (ret) { 2690e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 2691e3ec7017SPing-Ke Shih return ret; 2692e3ec7017SPing-Ke Shih } 2693e3ec7017SPing-Ke Shih 2694e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 2695e3ec7017SPing-Ke Shih if (ret) { 2696e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 2697e3ec7017SPing-Ke Shih return ret; 2698e3ec7017SPing-Ke Shih } 2699e3ec7017SPing-Ke Shih 2700e3ec7017SPing-Ke Shih ret = set_host_rpr(rtwdev); 2701e3ec7017SPing-Ke Shih if (ret) { 2702e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 2703e3ec7017SPing-Ke Shih return ret; 2704e3ec7017SPing-Ke Shih } 2705e3ec7017SPing-Ke Shih 2706e3ec7017SPing-Ke Shih return 0; 2707e3ec7017SPing-Ke Shih } 2708e3ec7017SPing-Ke Shih 2709e3ec7017SPing-Ke Shih static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) 2710e3ec7017SPing-Ke Shih { 2711e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 2712e3ec7017SPing-Ke Shih 2713e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 2714de78869dSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 2715de78869dSChia-Yuan Li B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 2716e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 2717de78869dSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 2718de78869dSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 2719e3ec7017SPing-Ke Shih } 2720e3ec7017SPing-Ke Shih 2721e3ec7017SPing-Ke Shih static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, 2722e3ec7017SPing-Ke Shih bool dlfw) 2723e3ec7017SPing-Ke Shih { 2724e3ec7017SPing-Ke Shih u32 val; 2725e3ec7017SPing-Ke Shih int ret; 2726e3ec7017SPing-Ke Shih 2727e3ec7017SPing-Ke Shih if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 2728e3ec7017SPing-Ke Shih return -EFAULT; 2729e3ec7017SPing-Ke Shih 2730e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 2731e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 2732e3ec7017SPing-Ke Shih 2733e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 2734e3ec7017SPing-Ke Shih 2735e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 2736e3ec7017SPing-Ke Shih val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 2737e3ec7017SPing-Ke Shih val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 2738e3ec7017SPing-Ke Shih B_AX_WCPU_FWDL_STS_MASK); 2739e3ec7017SPing-Ke Shih 2740e3ec7017SPing-Ke Shih if (dlfw) 2741e3ec7017SPing-Ke Shih val |= B_AX_WCPU_FWDL_EN; 2742e3ec7017SPing-Ke Shih 2743e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 2744e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 2745e3ec7017SPing-Ke Shih boot_reason); 2746e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 2747e3ec7017SPing-Ke Shih 2748e3ec7017SPing-Ke Shih if (!dlfw) { 2749e3ec7017SPing-Ke Shih mdelay(5); 2750e3ec7017SPing-Ke Shih 2751e3ec7017SPing-Ke Shih ret = rtw89_fw_check_rdy(rtwdev); 2752e3ec7017SPing-Ke Shih if (ret) 2753e3ec7017SPing-Ke Shih return ret; 2754e3ec7017SPing-Ke Shih } 2755e3ec7017SPing-Ke Shih 2756e3ec7017SPing-Ke Shih return 0; 2757e3ec7017SPing-Ke Shih } 2758e3ec7017SPing-Ke Shih 2759*a7d82a7aSPing-Ke Shih static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 2760e3ec7017SPing-Ke Shih { 2761*a7d82a7aSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2762e3ec7017SPing-Ke Shih u32 val; 2763e3ec7017SPing-Ke Shih int ret; 2764e3ec7017SPing-Ke Shih 2765*a7d82a7aSPing-Ke Shih if (chip_id == RTL8852C) 2766*a7d82a7aSPing-Ke Shih val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 2767*a7d82a7aSPing-Ke Shih B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 2768*a7d82a7aSPing-Ke Shih else 2769e3ec7017SPing-Ke Shih val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 2770e3ec7017SPing-Ke Shih B_AX_PKT_BUF_EN; 2771e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 2772e3ec7017SPing-Ke Shih 2773e3ec7017SPing-Ke Shih val = B_AX_DISPATCHER_CLK_EN; 2774e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 2775e3ec7017SPing-Ke Shih 2776*a7d82a7aSPing-Ke Shih if (chip_id != RTL8852C) 2777*a7d82a7aSPing-Ke Shih goto dle; 2778*a7d82a7aSPing-Ke Shih 2779*a7d82a7aSPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 2780*a7d82a7aSPing-Ke Shih val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 2781*a7d82a7aSPing-Ke Shih val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 2782*a7d82a7aSPing-Ke Shih B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 2783*a7d82a7aSPing-Ke Shih rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 2784*a7d82a7aSPing-Ke Shih 2785*a7d82a7aSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 2786*a7d82a7aSPing-Ke Shih B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 2787*a7d82a7aSPing-Ke Shih B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 2788*a7d82a7aSPing-Ke Shih B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 2789*a7d82a7aSPing-Ke Shih B_AX_STOP_CH12 | B_AX_STOP_ACH2); 2790*a7d82a7aSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 2791*a7d82a7aSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 2792*a7d82a7aSPing-Ke Shih 2793*a7d82a7aSPing-Ke Shih dle: 2794e3ec7017SPing-Ke Shih ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 2795e3ec7017SPing-Ke Shih if (ret) { 2796e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 2797e3ec7017SPing-Ke Shih return ret; 2798e3ec7017SPing-Ke Shih } 2799e3ec7017SPing-Ke Shih 2800e3ec7017SPing-Ke Shih ret = hfc_init(rtwdev, true, false, true); 2801e3ec7017SPing-Ke Shih if (ret) { 2802e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 2803e3ec7017SPing-Ke Shih return ret; 2804e3ec7017SPing-Ke Shih } 2805e3ec7017SPing-Ke Shih 2806e3ec7017SPing-Ke Shih return ret; 2807e3ec7017SPing-Ke Shih } 2808e3ec7017SPing-Ke Shih 2809e3ec7017SPing-Ke Shih static void rtw89_mac_hci_func_en(struct rtw89_dev *rtwdev) 2810e3ec7017SPing-Ke Shih { 28112af64b4aSPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 28122af64b4aSPing-Ke Shih 28132af64b4aSPing-Ke Shih rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 2814e3ec7017SPing-Ke Shih B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 2815e3ec7017SPing-Ke Shih } 2816e3ec7017SPing-Ke Shih 2817e3ec7017SPing-Ke Shih void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2818e3ec7017SPing-Ke Shih { 2819e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2820e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2821e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 2822e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 2823e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 2824e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 2825e3ec7017SPing-Ke Shih } 2826e3ec7017SPing-Ke Shih 2827e3ec7017SPing-Ke Shih void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2828e3ec7017SPing-Ke Shih { 2829e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2830e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2831e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 2832e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 2833e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 2834e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 2835e3ec7017SPing-Ke Shih } 2836e3ec7017SPing-Ke Shih 2837e3ec7017SPing-Ke Shih int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) 2838e3ec7017SPing-Ke Shih { 2839e3ec7017SPing-Ke Shih int ret; 2840e3ec7017SPing-Ke Shih 2841e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 2842e3ec7017SPing-Ke Shih if (ret) { 2843e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 2844e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 2845e3ec7017SPing-Ke Shih if (ret) 2846e3ec7017SPing-Ke Shih return ret; 2847e3ec7017SPing-Ke Shih } 2848e3ec7017SPing-Ke Shih 2849e3ec7017SPing-Ke Shih rtw89_mac_hci_func_en(rtwdev); 2850e3ec7017SPing-Ke Shih 2851*a7d82a7aSPing-Ke Shih ret = rtw89_mac_dmac_pre_init(rtwdev); 2852*a7d82a7aSPing-Ke Shih if (ret) 2853*a7d82a7aSPing-Ke Shih return ret; 2854*a7d82a7aSPing-Ke Shih 2855e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_pre_init) { 2856e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 2857e3ec7017SPing-Ke Shih if (ret) 2858e3ec7017SPing-Ke Shih return ret; 2859e3ec7017SPing-Ke Shih } 2860e3ec7017SPing-Ke Shih 2861e3ec7017SPing-Ke Shih rtw89_mac_disable_cpu(rtwdev); 2862e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_cpu(rtwdev, 0, true); 2863e3ec7017SPing-Ke Shih if (ret) 2864e3ec7017SPing-Ke Shih return ret; 2865e3ec7017SPing-Ke Shih 2866e3ec7017SPing-Ke Shih ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); 2867e3ec7017SPing-Ke Shih if (ret) 2868e3ec7017SPing-Ke Shih return ret; 2869e3ec7017SPing-Ke Shih 2870e3ec7017SPing-Ke Shih return 0; 2871e3ec7017SPing-Ke Shih } 2872e3ec7017SPing-Ke Shih 2873e3ec7017SPing-Ke Shih int rtw89_mac_init(struct rtw89_dev *rtwdev) 2874e3ec7017SPing-Ke Shih { 2875e3ec7017SPing-Ke Shih int ret; 2876e3ec7017SPing-Ke Shih 2877e3ec7017SPing-Ke Shih ret = rtw89_mac_partial_init(rtwdev); 2878e3ec7017SPing-Ke Shih if (ret) 2879e3ec7017SPing-Ke Shih goto fail; 2880e3ec7017SPing-Ke Shih 2881e3ec7017SPing-Ke Shih rtw89_mac_enable_bb_rf(rtwdev); 2882e3ec7017SPing-Ke Shih 2883e3ec7017SPing-Ke Shih ret = rtw89_mac_sys_init(rtwdev); 2884e3ec7017SPing-Ke Shih if (ret) 2885e3ec7017SPing-Ke Shih goto fail; 2886e3ec7017SPing-Ke Shih 2887e3ec7017SPing-Ke Shih ret = rtw89_mac_trx_init(rtwdev); 2888e3ec7017SPing-Ke Shih if (ret) 2889e3ec7017SPing-Ke Shih goto fail; 2890e3ec7017SPing-Ke Shih 2891e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_post_init) { 2892e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_post_init(rtwdev); 2893e3ec7017SPing-Ke Shih if (ret) 2894e3ec7017SPing-Ke Shih goto fail; 2895e3ec7017SPing-Ke Shih } 2896e3ec7017SPing-Ke Shih 2897e3ec7017SPing-Ke Shih rtw89_fw_send_all_early_h2c(rtwdev); 2898e3ec7017SPing-Ke Shih rtw89_fw_h2c_set_ofld_cfg(rtwdev); 2899e3ec7017SPing-Ke Shih 2900e3ec7017SPing-Ke Shih return ret; 2901e3ec7017SPing-Ke Shih fail: 2902e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 2903e3ec7017SPing-Ke Shih 2904e3ec7017SPing-Ke Shih return ret; 2905e3ec7017SPing-Ke Shih } 2906e3ec7017SPing-Ke Shih 2907e3ec7017SPing-Ke Shih static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 2908e3ec7017SPing-Ke Shih { 2909e3ec7017SPing-Ke Shih u8 i; 2910e3ec7017SPing-Ke Shih 2911e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 2912e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 2913e3ec7017SPing-Ke Shih DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 2914e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 2915e3ec7017SPing-Ke Shih } 2916e3ec7017SPing-Ke Shih } 2917e3ec7017SPing-Ke Shih 2918e3ec7017SPing-Ke Shih static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 2919e3ec7017SPing-Ke Shih { 2920e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 2921e3ec7017SPing-Ke Shih CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 2922e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 2923e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 2924e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 2925e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 2926e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 2927e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 2928e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 2929e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 2930e3ec7017SPing-Ke Shih } 2931e3ec7017SPing-Ke Shih 29321b73e77dSPing-Ke Shih int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 2933e3ec7017SPing-Ke Shih { 2934e3ec7017SPing-Ke Shih u8 sh = FIELD_GET(GENMASK(4, 0), macid); 2935e3ec7017SPing-Ke Shih u8 grp = macid >> 5; 2936e3ec7017SPing-Ke Shih int ret; 2937e3ec7017SPing-Ke Shih 2938e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 2939e3ec7017SPing-Ke Shih if (ret) 2940e3ec7017SPing-Ke Shih return ret; 2941e3ec7017SPing-Ke Shih 2942e3ec7017SPing-Ke Shih rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 2943e3ec7017SPing-Ke Shih 2944e3ec7017SPing-Ke Shih return 0; 2945e3ec7017SPing-Ke Shih } 2946e3ec7017SPing-Ke Shih 2947e3ec7017SPing-Ke Shih static const struct rtw89_port_reg rtw_port_base = { 2948e3ec7017SPing-Ke Shih .port_cfg = R_AX_PORT_CFG_P0, 2949e3ec7017SPing-Ke Shih .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 2950e3ec7017SPing-Ke Shih .bcn_area = R_AX_BCN_AREA_P0, 2951e3ec7017SPing-Ke Shih .bcn_early = R_AX_BCNERLYINT_CFG_P0, 2952e3ec7017SPing-Ke Shih .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 2953e3ec7017SPing-Ke Shih .tbtt_agg = R_AX_TBTT_AGG_P0, 2954e3ec7017SPing-Ke Shih .bcn_space = R_AX_BCN_SPACE_CFG_P0, 2955e3ec7017SPing-Ke Shih .bcn_forcetx = R_AX_BCN_FORCETX_P0, 2956e3ec7017SPing-Ke Shih .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 2957e3ec7017SPing-Ke Shih .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 2958e3ec7017SPing-Ke Shih .dtim_ctrl = R_AX_DTIM_CTRL_P0, 2959e3ec7017SPing-Ke Shih .tbtt_shift = R_AX_TBTT_SHIFT_P0, 2960e3ec7017SPing-Ke Shih .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 2961e3ec7017SPing-Ke Shih .tsftr_l = R_AX_TSFTR_LOW_P0, 2962e3ec7017SPing-Ke Shih .tsftr_h = R_AX_TSFTR_HIGH_P0 2963e3ec7017SPing-Ke Shih }; 2964e3ec7017SPing-Ke Shih 2965e3ec7017SPing-Ke Shih #define BCN_INTERVAL 100 2966e3ec7017SPing-Ke Shih #define BCN_ERLY_DEF 160 2967e3ec7017SPing-Ke Shih #define BCN_SETUP_DEF 2 2968e3ec7017SPing-Ke Shih #define BCN_HOLD_DEF 200 2969e3ec7017SPing-Ke Shih #define BCN_MASK_DEF 0 2970e3ec7017SPing-Ke Shih #define TBTT_ERLY_DEF 5 2971e3ec7017SPing-Ke Shih #define BCN_SET_UNIT 32 2972e3ec7017SPing-Ke Shih #define BCN_ERLY_SET_DLY (10 * 2) 2973e3ec7017SPing-Ke Shih 2974e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 2975e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2976e3ec7017SPing-Ke Shih { 2977e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2978e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2979e3ec7017SPing-Ke Shih 2980e3ec7017SPing-Ke Shih if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 2981e3ec7017SPing-Ke Shih return; 2982e3ec7017SPing-Ke Shih 2983e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 2984e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 2985e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 2986e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 2987e3ec7017SPing-Ke Shih 2988e3ec7017SPing-Ke Shih msleep(vif->bss_conf.beacon_int + 1); 2989e3ec7017SPing-Ke Shih 2990e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 2991e3ec7017SPing-Ke Shih B_AX_BRK_SETUP); 2992e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 2993e3ec7017SPing-Ke Shih rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 2994e3ec7017SPing-Ke Shih } 2995e3ec7017SPing-Ke Shih 2996e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 2997e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 2998e3ec7017SPing-Ke Shih { 2999e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3000e3ec7017SPing-Ke Shih 3001e3ec7017SPing-Ke Shih if (en) 3002e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3003e3ec7017SPing-Ke Shih else 3004e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3005e3ec7017SPing-Ke Shih } 3006e3ec7017SPing-Ke Shih 3007e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3008e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 3009e3ec7017SPing-Ke Shih { 3010e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3011e3ec7017SPing-Ke Shih 3012e3ec7017SPing-Ke Shih if (en) 3013e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3014e3ec7017SPing-Ke Shih else 3015e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3016e3ec7017SPing-Ke Shih } 3017e3ec7017SPing-Ke Shih 3018e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3019e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3020e3ec7017SPing-Ke Shih { 3021e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3022e3ec7017SPing-Ke Shih 3023e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3024e3ec7017SPing-Ke Shih rtwvif->net_type); 3025e3ec7017SPing-Ke Shih } 3026e3ec7017SPing-Ke Shih 3027e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3028e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3029e3ec7017SPing-Ke Shih { 3030e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3031e3ec7017SPing-Ke Shih bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3032e3ec7017SPing-Ke Shih u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3033e3ec7017SPing-Ke Shih 3034e3ec7017SPing-Ke Shih if (en) 3035e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3036e3ec7017SPing-Ke Shih else 3037e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3038e3ec7017SPing-Ke Shih } 3039e3ec7017SPing-Ke Shih 3040e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3041e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3042e3ec7017SPing-Ke Shih { 3043e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3044e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3045e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3046e3ec7017SPing-Ke Shih u32 bit = B_AX_RX_BSSID_FIT_EN; 3047e3ec7017SPing-Ke Shih 3048e3ec7017SPing-Ke Shih if (en) 3049e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3050e3ec7017SPing-Ke Shih else 3051e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3052e3ec7017SPing-Ke Shih } 3053e3ec7017SPing-Ke Shih 3054e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3055e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3056e3ec7017SPing-Ke Shih { 3057e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3058e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3059e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3060e3ec7017SPing-Ke Shih 3061e3ec7017SPing-Ke Shih if (en) 3062e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3063e3ec7017SPing-Ke Shih else 3064e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3065e3ec7017SPing-Ke Shih } 3066e3ec7017SPing-Ke Shih 3067e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3068e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3069e3ec7017SPing-Ke Shih { 3070e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3071e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3072e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3073e3ec7017SPing-Ke Shih 3074e3ec7017SPing-Ke Shih if (en) 3075e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3076e3ec7017SPing-Ke Shih else 3077e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3078e3ec7017SPing-Ke Shih } 3079e3ec7017SPing-Ke Shih 3080e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3081e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3082e3ec7017SPing-Ke Shih { 3083e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3084e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3085e3ec7017SPing-Ke Shih u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3086e3ec7017SPing-Ke Shih 3087e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3088e3ec7017SPing-Ke Shih bcn_int); 3089e3ec7017SPing-Ke Shih } 3090e3ec7017SPing-Ke Shih 3091283c3d88SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3092283c3d88SPing-Ke Shih struct rtw89_vif *rtwvif) 3093283c3d88SPing-Ke Shih { 3094283c3d88SPing-Ke Shih static const u32 hiq_win_addr[RTW89_PORT_NUM] = { 3095283c3d88SPing-Ke Shih R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3096283c3d88SPing-Ke Shih R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3097283c3d88SPing-Ke Shih R_AX_PORT_HGQ_WINDOW_CFG + 3, 3098283c3d88SPing-Ke Shih }; 3099283c3d88SPing-Ke Shih u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3100283c3d88SPing-Ke Shih u8 port = rtwvif->port; 3101283c3d88SPing-Ke Shih u32 reg; 3102283c3d88SPing-Ke Shih 3103283c3d88SPing-Ke Shih reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx); 3104283c3d88SPing-Ke Shih rtw89_write8(rtwdev, reg, win); 3105283c3d88SPing-Ke Shih } 3106283c3d88SPing-Ke Shih 3107283c3d88SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3108283c3d88SPing-Ke Shih struct rtw89_vif *rtwvif) 3109283c3d88SPing-Ke Shih { 3110283c3d88SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3111283c3d88SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3112283c3d88SPing-Ke Shih u32 addr; 3113283c3d88SPing-Ke Shih 3114283c3d88SPing-Ke Shih addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); 3115283c3d88SPing-Ke Shih rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3116283c3d88SPing-Ke Shih 3117283c3d88SPing-Ke Shih rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3118283c3d88SPing-Ke Shih vif->bss_conf.dtim_period); 3119283c3d88SPing-Ke Shih } 3120283c3d88SPing-Ke Shih 3121e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3122e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3123e3ec7017SPing-Ke Shih { 3124e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3125e3ec7017SPing-Ke Shih 3126e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3127e3ec7017SPing-Ke Shih B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3128e3ec7017SPing-Ke Shih } 3129e3ec7017SPing-Ke Shih 3130e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3131e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3132e3ec7017SPing-Ke Shih { 3133e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3134e3ec7017SPing-Ke Shih 3135e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3136e3ec7017SPing-Ke Shih B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3137e3ec7017SPing-Ke Shih } 3138e3ec7017SPing-Ke Shih 3139e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3140e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3141e3ec7017SPing-Ke Shih { 3142e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3143e3ec7017SPing-Ke Shih 3144e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3145e3ec7017SPing-Ke Shih B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3146e3ec7017SPing-Ke Shih } 3147e3ec7017SPing-Ke Shih 3148e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3149e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3150e3ec7017SPing-Ke Shih { 3151e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3152e3ec7017SPing-Ke Shih 3153e3ec7017SPing-Ke Shih rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3154e3ec7017SPing-Ke Shih B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3155e3ec7017SPing-Ke Shih } 3156e3ec7017SPing-Ke Shih 3157e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3158e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3159e3ec7017SPing-Ke Shih { 3160e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3161e3ec7017SPing-Ke Shih static const u32 masks[RTW89_PORT_NUM] = { 3162e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3163e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3164e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_4_MASK, 3165e3ec7017SPing-Ke Shih }; 3166e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3167e3ec7017SPing-Ke Shih u32 reg_base; 3168e3ec7017SPing-Ke Shih u32 reg; 3169e3ec7017SPing-Ke Shih u8 bss_color; 3170e3ec7017SPing-Ke Shih 3171e3ec7017SPing-Ke Shih bss_color = vif->bss_conf.he_bss_color.color; 3172e3ec7017SPing-Ke Shih reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; 3173e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); 3174e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3175e3ec7017SPing-Ke Shih } 3176e3ec7017SPing-Ke Shih 3177e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3178e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3179e3ec7017SPing-Ke Shih { 3180e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3181e3ec7017SPing-Ke Shih u32 reg; 3182e3ec7017SPing-Ke Shih 3183e3ec7017SPing-Ke Shih if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3184e3ec7017SPing-Ke Shih return; 3185e3ec7017SPing-Ke Shih 3186e3ec7017SPing-Ke Shih if (port == 0) { 3187e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); 3188e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3189e3ec7017SPing-Ke Shih } 3190e3ec7017SPing-Ke Shih } 3191e3ec7017SPing-Ke Shih 3192e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3193e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3194e3ec7017SPing-Ke Shih { 3195e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3196e3ec7017SPing-Ke Shih u32 reg; 3197e3ec7017SPing-Ke Shih u32 val; 3198e3ec7017SPing-Ke Shih 3199e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); 3200e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 3201e3ec7017SPing-Ke Shih val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 3202e3ec7017SPing-Ke Shih if (port == 0) 3203e3ec7017SPing-Ke Shih val &= ~BIT(0); 3204e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 3205e3ec7017SPing-Ke Shih } 3206e3ec7017SPing-Ke Shih 3207e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 3208e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3209e3ec7017SPing-Ke Shih { 3210e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3211e3ec7017SPing-Ke Shih 3212e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN); 3213e3ec7017SPing-Ke Shih } 3214e3ec7017SPing-Ke Shih 3215e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 3216e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3217e3ec7017SPing-Ke Shih { 3218e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3219e3ec7017SPing-Ke Shih 3220e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 3221e3ec7017SPing-Ke Shih BCN_ERLY_DEF); 3222e3ec7017SPing-Ke Shih } 3223e3ec7017SPing-Ke Shih 3224e3ec7017SPing-Ke Shih int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3225e3ec7017SPing-Ke Shih { 3226e3ec7017SPing-Ke Shih int ret; 3227e3ec7017SPing-Ke Shih 3228e3ec7017SPing-Ke Shih ret = rtw89_mac_port_update(rtwdev, rtwvif); 3229e3ec7017SPing-Ke Shih if (ret) 3230e3ec7017SPing-Ke Shih return ret; 3231e3ec7017SPing-Ke Shih 3232e3ec7017SPing-Ke Shih rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 3233e3ec7017SPing-Ke Shih rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 3234e3ec7017SPing-Ke Shih 32351b73e77dSPing-Ke Shih ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 3236e3ec7017SPing-Ke Shih if (ret) 3237e3ec7017SPing-Ke Shih return ret; 3238e3ec7017SPing-Ke Shih 3239ff66964aSPing-Ke Shih ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 3240e3ec7017SPing-Ke Shih if (ret) 3241e3ec7017SPing-Ke Shih return ret; 3242e3ec7017SPing-Ke Shih 3243e3ec7017SPing-Ke Shih ret = rtw89_cam_init(rtwdev, rtwvif); 3244e3ec7017SPing-Ke Shih if (ret) 3245e3ec7017SPing-Ke Shih return ret; 3246e3ec7017SPing-Ke Shih 324740822e07SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3248e3ec7017SPing-Ke Shih if (ret) 3249e3ec7017SPing-Ke Shih return ret; 3250e3ec7017SPing-Ke Shih 3251742c470bSPing-Ke Shih ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 3252e3ec7017SPing-Ke Shih if (ret) 3253e3ec7017SPing-Ke Shih return ret; 3254e3ec7017SPing-Ke Shih 3255e3ec7017SPing-Ke Shih return 0; 3256e3ec7017SPing-Ke Shih } 3257e3ec7017SPing-Ke Shih 3258e3ec7017SPing-Ke Shih int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3259e3ec7017SPing-Ke Shih { 3260e3ec7017SPing-Ke Shih int ret; 3261e3ec7017SPing-Ke Shih 3262ff66964aSPing-Ke Shih ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 3263e3ec7017SPing-Ke Shih if (ret) 3264e3ec7017SPing-Ke Shih return ret; 3265e3ec7017SPing-Ke Shih 3266e3ec7017SPing-Ke Shih rtw89_cam_deinit(rtwdev, rtwvif); 3267e3ec7017SPing-Ke Shih 326840822e07SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3269e3ec7017SPing-Ke Shih if (ret) 3270e3ec7017SPing-Ke Shih return ret; 3271e3ec7017SPing-Ke Shih 3272e3ec7017SPing-Ke Shih return 0; 3273e3ec7017SPing-Ke Shih } 3274e3ec7017SPing-Ke Shih 3275e3ec7017SPing-Ke Shih int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3276e3ec7017SPing-Ke Shih { 3277e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3278e3ec7017SPing-Ke Shih 3279e3ec7017SPing-Ke Shih if (port >= RTW89_PORT_NUM) 3280e3ec7017SPing-Ke Shih return -EINVAL; 3281e3ec7017SPing-Ke Shih 3282e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 3283e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 3284e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 3285e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 3286e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 3287e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 3288e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 3289e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 3290e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 3291283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 3292283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 3293283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 3294e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 3295e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 3296e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 3297e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 3298e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 3299e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 3300e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_func_en(rtwdev, rtwvif); 3301e3ec7017SPing-Ke Shih fsleep(BCN_ERLY_SET_DLY); 3302e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 3303e3ec7017SPing-Ke Shih 3304e3ec7017SPing-Ke Shih return 0; 3305e3ec7017SPing-Ke Shih } 3306e3ec7017SPing-Ke Shih 3307e3ec7017SPing-Ke Shih int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3308e3ec7017SPing-Ke Shih { 3309e3ec7017SPing-Ke Shih int ret; 3310e3ec7017SPing-Ke Shih 3311e3ec7017SPing-Ke Shih rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 3312e3ec7017SPing-Ke Shih RTW89_MAX_MAC_ID_NUM); 3313e3ec7017SPing-Ke Shih if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 3314e3ec7017SPing-Ke Shih return -ENOSPC; 3315e3ec7017SPing-Ke Shih 3316e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_init(rtwdev, rtwvif); 3317e3ec7017SPing-Ke Shih if (ret) 3318e3ec7017SPing-Ke Shih goto release_mac_id; 3319e3ec7017SPing-Ke Shih 3320e3ec7017SPing-Ke Shih return 0; 3321e3ec7017SPing-Ke Shih 3322e3ec7017SPing-Ke Shih release_mac_id: 3323e3ec7017SPing-Ke Shih rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 3324e3ec7017SPing-Ke Shih 3325e3ec7017SPing-Ke Shih return ret; 3326e3ec7017SPing-Ke Shih } 3327e3ec7017SPing-Ke Shih 3328e3ec7017SPing-Ke Shih int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3329e3ec7017SPing-Ke Shih { 3330e3ec7017SPing-Ke Shih int ret; 3331e3ec7017SPing-Ke Shih 3332e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 3333e3ec7017SPing-Ke Shih rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 3334e3ec7017SPing-Ke Shih 3335e3ec7017SPing-Ke Shih return ret; 3336e3ec7017SPing-Ke Shih } 3337e3ec7017SPing-Ke Shih 3338e3ec7017SPing-Ke Shih static void 3339e3ec7017SPing-Ke Shih rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3340e3ec7017SPing-Ke Shih { 3341e3ec7017SPing-Ke Shih } 3342e3ec7017SPing-Ke Shih 334389590777SPo Hao Huang static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 334489590777SPo Hao Huang { 334589590777SPo Hao Huang struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 334689590777SPo Hao Huang 334789590777SPo Hao Huang return band == scan_info->op_band && channel == scan_info->op_pri_ch; 334889590777SPo Hao Huang } 334989590777SPo Hao Huang 335089590777SPo Hao Huang static void 335189590777SPo Hao Huang rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 335289590777SPo Hao Huang u32 len) 335389590777SPo Hao Huang { 335489590777SPo Hao Huang struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 335589590777SPo Hao Huang struct rtw89_hal *hal = &rtwdev->hal; 335689590777SPo Hao Huang u8 reason, status, tx_fail, band; 335789590777SPo Hao Huang u16 chan; 335889590777SPo Hao Huang 335989590777SPo Hao Huang tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 336089590777SPo Hao Huang status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 336189590777SPo Hao Huang chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 336289590777SPo Hao Huang reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 336389590777SPo Hao Huang band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 336489590777SPo Hao Huang 336589590777SPo Hao Huang if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 336689590777SPo Hao Huang band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 336789590777SPo Hao Huang 336889590777SPo Hao Huang rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 336989590777SPo Hao Huang "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d\n", 337089590777SPo Hao Huang band, chan, reason, status, tx_fail); 337189590777SPo Hao Huang 337289590777SPo Hao Huang switch (reason) { 337389590777SPo Hao Huang case RTW89_SCAN_LEAVE_CH_NOTIFY: 337489590777SPo Hao Huang if (rtw89_is_op_chan(rtwdev, band, chan)) 337589590777SPo Hao Huang ieee80211_stop_queues(rtwdev->hw); 337689590777SPo Hao Huang return; 337789590777SPo Hao Huang case RTW89_SCAN_END_SCAN_NOTIFY: 337889590777SPo Hao Huang rtw89_hw_scan_complete(rtwdev, vif, false); 337989590777SPo Hao Huang break; 338089590777SPo Hao Huang case RTW89_SCAN_ENTER_CH_NOTIFY: 338189590777SPo Hao Huang if (rtw89_is_op_chan(rtwdev, band, chan)) 338289590777SPo Hao Huang ieee80211_wake_queues(rtwdev->hw); 338389590777SPo Hao Huang break; 338489590777SPo Hao Huang default: 338589590777SPo Hao Huang return; 338689590777SPo Hao Huang } 338789590777SPo Hao Huang 338889590777SPo Hao Huang hal->prev_band_type = hal->current_band_type; 338989590777SPo Hao Huang hal->prev_primary_channel = hal->current_channel; 339089590777SPo Hao Huang hal->current_channel = chan; 339189590777SPo Hao Huang hal->current_band_type = band; 339289590777SPo Hao Huang } 339389590777SPo Hao Huang 3394e3ec7017SPing-Ke Shih static void 3395e3ec7017SPing-Ke Shih rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3396e3ec7017SPing-Ke Shih { 3397e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 3398e3ec7017SPing-Ke Shih "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 3399e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 3400e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 3401e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 3402e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 3403e3ec7017SPing-Ke Shih } 3404e3ec7017SPing-Ke Shih 3405e3ec7017SPing-Ke Shih static void 3406e3ec7017SPing-Ke Shih rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3407e3ec7017SPing-Ke Shih { 3408e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 3409e3ec7017SPing-Ke Shih "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 3410e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data), 3411e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data), 3412e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data), 3413e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data), 3414e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data)); 3415e3ec7017SPing-Ke Shih } 3416e3ec7017SPing-Ke Shih 3417e3ec7017SPing-Ke Shih static void 3418e3ec7017SPing-Ke Shih rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3419e3ec7017SPing-Ke Shih { 3420e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), 3421e3ec7017SPing-Ke Shih RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); 3422e3ec7017SPing-Ke Shih } 3423e3ec7017SPing-Ke Shih 3424fccca934SPing-Ke Shih static void 3425fccca934SPing-Ke Shih rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3426fccca934SPing-Ke Shih { 3427fccca934SPing-Ke Shih } 3428fccca934SPing-Ke Shih 3429e3ec7017SPing-Ke Shih static 3430e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 3431e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 3432e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 3433e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 3434e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = NULL, 3435e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 3436e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 343789590777SPo Hao Huang [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 3438e3ec7017SPing-Ke Shih }; 3439e3ec7017SPing-Ke Shih 3440e3ec7017SPing-Ke Shih static 3441e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 3442e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 3443e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 3444e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 3445e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 3446fccca934SPing-Ke Shih [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 3447e3ec7017SPing-Ke Shih }; 3448e3ec7017SPing-Ke Shih 3449e3ec7017SPing-Ke Shih void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3450e3ec7017SPing-Ke Shih u32 len, u8 class, u8 func) 3451e3ec7017SPing-Ke Shih { 3452e3ec7017SPing-Ke Shih void (*handler)(struct rtw89_dev *rtwdev, 3453e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = NULL; 3454e3ec7017SPing-Ke Shih 3455e3ec7017SPing-Ke Shih switch (class) { 3456e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_INFO: 3457e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 3458e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_info_handler[func]; 3459e3ec7017SPing-Ke Shih break; 3460e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_OFLD: 3461e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 3462e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_ofld_handler[func]; 3463e3ec7017SPing-Ke Shih break; 3464e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_FWDBG: 3465e3ec7017SPing-Ke Shih return; 3466e3ec7017SPing-Ke Shih default: 3467e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d not support\n", class); 3468e3ec7017SPing-Ke Shih return; 3469e3ec7017SPing-Ke Shih } 3470e3ec7017SPing-Ke Shih if (!handler) { 3471e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 3472e3ec7017SPing-Ke Shih func); 3473e3ec7017SPing-Ke Shih return; 3474e3ec7017SPing-Ke Shih } 3475e3ec7017SPing-Ke Shih handler(rtwdev, skb, len); 3476e3ec7017SPing-Ke Shih } 3477e3ec7017SPing-Ke Shih 3478e3ec7017SPing-Ke Shih bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 3479e3ec7017SPing-Ke Shih enum rtw89_phy_idx phy_idx, 3480e3ec7017SPing-Ke Shih u32 reg_base, u32 *cr) 3481e3ec7017SPing-Ke Shih { 3482e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 3483e3ec7017SPing-Ke Shih enum rtw89_qta_mode mode = dle_mem->mode; 3484e3ec7017SPing-Ke Shih u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); 3485e3ec7017SPing-Ke Shih 3486e3ec7017SPing-Ke Shih if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { 3487e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 3488e3ec7017SPing-Ke Shih addr); 3489e3ec7017SPing-Ke Shih goto error; 3490e3ec7017SPing-Ke Shih } 3491e3ec7017SPing-Ke Shih 3492e3ec7017SPing-Ke Shih if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) 3493e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_SCC) { 3494e3ec7017SPing-Ke Shih rtw89_err(rtwdev, 3495e3ec7017SPing-Ke Shih "[TXPWR] addr=0x%x but hw not enable\n", 3496e3ec7017SPing-Ke Shih addr); 3497e3ec7017SPing-Ke Shih goto error; 3498e3ec7017SPing-Ke Shih } 3499e3ec7017SPing-Ke Shih 3500e3ec7017SPing-Ke Shih *cr = addr; 3501e3ec7017SPing-Ke Shih return true; 3502e3ec7017SPing-Ke Shih 3503e3ec7017SPing-Ke Shih error: 3504e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 3505e3ec7017SPing-Ke Shih addr, phy_idx); 3506e3ec7017SPing-Ke Shih 3507e3ec7017SPing-Ke Shih return false; 3508e3ec7017SPing-Ke Shih } 3509861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); 3510e3ec7017SPing-Ke Shih 3511e3ec7017SPing-Ke Shih int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 3512e3ec7017SPing-Ke Shih { 3513e3ec7017SPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); 3514e3ec7017SPing-Ke Shih int ret = 0; 3515e3ec7017SPing-Ke Shih 3516e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3517e3ec7017SPing-Ke Shih if (ret) 3518e3ec7017SPing-Ke Shih return ret; 3519e3ec7017SPing-Ke Shih 3520e3ec7017SPing-Ke Shih if (!enable) { 3521e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 3522e3ec7017SPing-Ke Shih return ret; 3523e3ec7017SPing-Ke Shih } 3524e3ec7017SPing-Ke Shih 3525e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 3526e3ec7017SPing-Ke Shih B_AX_APP_MAC_INFO_RPT | 3527e3ec7017SPing-Ke Shih B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 3528e3ec7017SPing-Ke Shih B_AX_PPDU_STAT_RPT_CRC32); 3529e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 3530e3ec7017SPing-Ke Shih RTW89_PRPT_DEST_HOST); 3531e3ec7017SPing-Ke Shih 3532e3ec7017SPing-Ke Shih return ret; 3533e3ec7017SPing-Ke Shih } 3534861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 3535e3ec7017SPing-Ke Shih 3536e3ec7017SPing-Ke Shih void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 3537e3ec7017SPing-Ke Shih { 3538e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_SH 5 3539e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_SH 4 3540e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_MAX 255 3541e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_MAX 255 3542e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_DEF 88 3543e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_DEF 4080 3544e3ec7017SPing-Ke Shih struct ieee80211_hw *hw = rtwdev->hw; 3545e3ec7017SPing-Ke Shih u32 rts_threshold = hw->wiphy->rts_threshold; 3546e3ec7017SPing-Ke Shih u32 time_th, len_th; 3547e3ec7017SPing-Ke Shih u32 reg; 3548e3ec7017SPing-Ke Shih 3549e3ec7017SPing-Ke Shih if (rts_threshold == (u32)-1) { 3550e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_DEF; 3551e3ec7017SPing-Ke Shih len_th = MAC_AX_LEN_TH_DEF; 3552e3ec7017SPing-Ke Shih } else { 3553e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 3554e3ec7017SPing-Ke Shih len_th = rts_threshold; 3555e3ec7017SPing-Ke Shih } 3556e3ec7017SPing-Ke Shih 3557e3ec7017SPing-Ke Shih time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 3558e3ec7017SPing-Ke Shih len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 3559e3ec7017SPing-Ke Shih 3560e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); 3561e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 3562e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 3563e3ec7017SPing-Ke Shih } 3564e3ec7017SPing-Ke Shih 3565e3ec7017SPing-Ke Shih void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 3566e3ec7017SPing-Ke Shih { 3567e3ec7017SPing-Ke Shih bool empty; 3568e3ec7017SPing-Ke Shih int ret; 3569e3ec7017SPing-Ke Shih 3570e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3571e3ec7017SPing-Ke Shih return; 3572e3ec7017SPing-Ke Shih 3573e3ec7017SPing-Ke Shih ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 3574e3ec7017SPing-Ke Shih 10000, 200000, false, rtwdev); 3575e3ec7017SPing-Ke Shih if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 3576e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "timed out to flush queues\n"); 3577e3ec7017SPing-Ke Shih } 3578e3ec7017SPing-Ke Shih 3579e3ec7017SPing-Ke Shih int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 3580e3ec7017SPing-Ke Shih { 3581e3ec7017SPing-Ke Shih u8 val; 3582e3ec7017SPing-Ke Shih u16 val16; 3583e3ec7017SPing-Ke Shih u32 val32; 3584e3ec7017SPing-Ke Shih int ret; 3585e3ec7017SPing-Ke Shih 3586e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 3587e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 3588e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 3589e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 3590e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 3591e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 3592e3ec7017SPing-Ke Shih 3593e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 3594e3ec7017SPing-Ke Shih val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 3595e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 3596e3ec7017SPing-Ke Shih 3597e3ec7017SPing-Ke Shih ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 3598e3ec7017SPing-Ke Shih if (ret) { 3599e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 3600e3ec7017SPing-Ke Shih return ret; 3601e3ec7017SPing-Ke Shih } 3602e3ec7017SPing-Ke Shih val32 = val32 & B_AX_WL_RX_CTRL; 3603e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 3604e3ec7017SPing-Ke Shih if (ret) { 3605e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 3606e3ec7017SPing-Ke Shih return ret; 3607e3ec7017SPing-Ke Shih } 3608e3ec7017SPing-Ke Shih 3609e3ec7017SPing-Ke Shih switch (coex->pta_mode) { 3610e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_RTK_MODE: 3611e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 3612e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 3613e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 3614e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 3615e3ec7017SPing-Ke Shih 3616e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 3617e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 3618e3ec7017SPing-Ke Shih 3619e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 3620e3ec7017SPing-Ke Shih val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 3621e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 3622e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 3623e3ec7017SPing-Ke Shih break; 3624e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_CSR_MODE: 3625e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 3626e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 3627e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 3628e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 3629e3ec7017SPing-Ke Shih 3630e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 3631e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 3632e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 3633e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 3634e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 3635e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_STAT_DELAY_MASK; 3636e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 3637e3ec7017SPing-Ke Shih val16 |= B_AX_ENHANCED_BT; 3638e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 3639e3ec7017SPing-Ke Shih 3640e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 3641e3ec7017SPing-Ke Shih break; 3642e3ec7017SPing-Ke Shih default: 3643e3ec7017SPing-Ke Shih return -EINVAL; 3644e3ec7017SPing-Ke Shih } 3645e3ec7017SPing-Ke Shih 3646e3ec7017SPing-Ke Shih switch (coex->direction) { 3647e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INNER: 3648e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3649e3ec7017SPing-Ke Shih val = (val & ~BIT(2)) | BIT(1); 3650e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3651e3ec7017SPing-Ke Shih break; 3652e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_OUTPUT: 3653e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3654e3ec7017SPing-Ke Shih val = val | BIT(1) | BIT(0); 3655e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3656e3ec7017SPing-Ke Shih break; 3657e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INPUT: 3658e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3659e3ec7017SPing-Ke Shih val = val & ~(BIT(2) | BIT(1)); 3660e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3661e3ec7017SPing-Ke Shih break; 3662e3ec7017SPing-Ke Shih default: 3663e3ec7017SPing-Ke Shih return -EINVAL; 3664e3ec7017SPing-Ke Shih } 3665e3ec7017SPing-Ke Shih 3666e3ec7017SPing-Ke Shih return 0; 3667e3ec7017SPing-Ke Shih } 3668861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_coex_init); 3669e3ec7017SPing-Ke Shih 3670e3ec7017SPing-Ke Shih int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 3671e3ec7017SPing-Ke Shih const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 3672e3ec7017SPing-Ke Shih { 36738001c741SPing-Ke Shih u32 val = 0, ret; 3674e3ec7017SPing-Ke Shih 36758001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_bt) 36768001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 36778001c741SPing-Ke Shih 36788001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_bt_sw_en) 36798001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 36808001c741SPing-Ke Shih 36818001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_wl) 36828001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 36838001c741SPing-Ke Shih 36848001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_wl_sw_en) 36858001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 36868001c741SPing-Ke Shih 36878001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_bt) 36888001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 36898001c741SPing-Ke Shih 36908001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_bt_sw_en) 36918001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 36928001c741SPing-Ke Shih 36938001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_wl) 36948001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 36958001c741SPing-Ke Shih 36968001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_wl_sw_en) 36978001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 36988001c741SPing-Ke Shih 3699e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 3700e3ec7017SPing-Ke Shih if (ret) { 3701e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write LTE fail!\n"); 3702e3ec7017SPing-Ke Shih return ret; 3703e3ec7017SPing-Ke Shih } 3704e3ec7017SPing-Ke Shih 3705e3ec7017SPing-Ke Shih return 0; 3706e3ec7017SPing-Ke Shih } 3707feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 3708feed6541SChia-Yuan Li 3709feed6541SChia-Yuan Li int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 3710feed6541SChia-Yuan Li const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 3711feed6541SChia-Yuan Li { 3712feed6541SChia-Yuan Li u32 val = 0; 3713feed6541SChia-Yuan Li 3714feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_bt) 3715feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 3716feed6541SChia-Yuan Li B_AX_GNT_BT_TX_VAL; 3717feed6541SChia-Yuan Li else 3718feed6541SChia-Yuan Li val |= B_AX_WL_ACT_VAL; 3719feed6541SChia-Yuan Li 3720feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_bt_sw_en) 3721feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 3722feed6541SChia-Yuan Li B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 3723feed6541SChia-Yuan Li 3724feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_wl) 3725feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 3726feed6541SChia-Yuan Li B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 3727feed6541SChia-Yuan Li 3728feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_wl_sw_en) 3729feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 3730feed6541SChia-Yuan Li B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 3731feed6541SChia-Yuan Li 3732feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_bt) 3733feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 3734feed6541SChia-Yuan Li B_AX_GNT_BT_TX_VAL; 3735feed6541SChia-Yuan Li else 3736feed6541SChia-Yuan Li val |= B_AX_WL_ACT_VAL; 3737feed6541SChia-Yuan Li 3738feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_bt_sw_en) 3739feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 3740feed6541SChia-Yuan Li B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 3741feed6541SChia-Yuan Li 3742feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_wl) 3743feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 3744feed6541SChia-Yuan Li B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 3745feed6541SChia-Yuan Li 3746feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_wl_sw_en) 3747feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 3748feed6541SChia-Yuan Li B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 3749feed6541SChia-Yuan Li 3750feed6541SChia-Yuan Li rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 3751feed6541SChia-Yuan Li 3752feed6541SChia-Yuan Li return 0; 3753feed6541SChia-Yuan Li } 3754feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 3755e3ec7017SPing-Ke Shih 3756e3ec7017SPing-Ke Shih int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 3757e3ec7017SPing-Ke Shih { 3758e3ec7017SPing-Ke Shih u32 reg; 375928e7ea8aSPing-Ke Shih u16 val; 3760e3ec7017SPing-Ke Shih int ret; 3761e3ec7017SPing-Ke Shih 3762e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 3763e3ec7017SPing-Ke Shih if (ret) 3764e3ec7017SPing-Ke Shih return ret; 3765e3ec7017SPing-Ke Shih 3766e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); 3767e3ec7017SPing-Ke Shih val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 3768e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 3769e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 3770e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 3771e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 3772e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 3773e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 377428e7ea8aSPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 377528e7ea8aSPing-Ke Shih B_AX_PLT_EN; 377628e7ea8aSPing-Ke Shih rtw89_write16(rtwdev, reg, val); 3777e3ec7017SPing-Ke Shih 3778e3ec7017SPing-Ke Shih return 0; 3779e3ec7017SPing-Ke Shih } 3780e3ec7017SPing-Ke Shih 3781e3ec7017SPing-Ke Shih void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 3782e3ec7017SPing-Ke Shih { 3783e3ec7017SPing-Ke Shih u32 fw_sb; 3784e3ec7017SPing-Ke Shih 3785e3ec7017SPing-Ke Shih fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 3786e3ec7017SPing-Ke Shih fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 3787e3ec7017SPing-Ke Shih fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 3788e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3789e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 3790e3ec7017SPing-Ke Shih else 3791e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 3792e3ec7017SPing-Ke Shih val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 3793e3ec7017SPing-Ke Shih val = B_AX_TOGGLE | 3794e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 3795e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 3796e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 3797e3ec7017SPing-Ke Shih fsleep(1000); /* avoid BT FW loss information */ 3798e3ec7017SPing-Ke Shih } 3799e3ec7017SPing-Ke Shih 3800e3ec7017SPing-Ke Shih u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 3801e3ec7017SPing-Ke Shih { 3802e3ec7017SPing-Ke Shih return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 3803e3ec7017SPing-Ke Shih } 3804e3ec7017SPing-Ke Shih 3805e3ec7017SPing-Ke Shih int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 3806e3ec7017SPing-Ke Shih { 3807e3ec7017SPing-Ke Shih u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 3808e3ec7017SPing-Ke Shih 3809e3ec7017SPing-Ke Shih val = wl ? val | BIT(2) : val & ~BIT(2); 3810e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 3811e3ec7017SPing-Ke Shih 3812e3ec7017SPing-Ke Shih return 0; 3813e3ec7017SPing-Ke Shih } 3814feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 3815feed6541SChia-Yuan Li 3816feed6541SChia-Yuan Li int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 3817feed6541SChia-Yuan Li { 3818feed6541SChia-Yuan Li struct rtw89_btc *btc = &rtwdev->btc; 3819feed6541SChia-Yuan Li struct rtw89_btc_dm *dm = &btc->dm; 3820feed6541SChia-Yuan Li struct rtw89_mac_ax_gnt *g = dm->gnt.band; 3821feed6541SChia-Yuan Li int i; 3822feed6541SChia-Yuan Li 3823feed6541SChia-Yuan Li if (wl) 3824feed6541SChia-Yuan Li return 0; 3825feed6541SChia-Yuan Li 3826feed6541SChia-Yuan Li for (i = 0; i < RTW89_PHY_MAX; i++) { 3827feed6541SChia-Yuan Li g[i].gnt_bt_sw_en = 1; 3828feed6541SChia-Yuan Li g[i].gnt_bt = 1; 3829feed6541SChia-Yuan Li g[i].gnt_wl_sw_en = 1; 3830feed6541SChia-Yuan Li g[i].gnt_wl = 0; 3831feed6541SChia-Yuan Li } 3832feed6541SChia-Yuan Li 3833feed6541SChia-Yuan Li return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 3834feed6541SChia-Yuan Li } 3835feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 3836e3ec7017SPing-Ke Shih 3837e3ec7017SPing-Ke Shih bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 3838e3ec7017SPing-Ke Shih { 3839e3ec7017SPing-Ke Shih u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 3840e3ec7017SPing-Ke Shih 3841e3ec7017SPing-Ke Shih return FIELD_GET(B_AX_LTE_MUX_CTRL_PATH >> 24, val); 3842e3ec7017SPing-Ke Shih } 3843e3ec7017SPing-Ke Shih 38448c7e9cebSChing-Te Ku u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 38458c7e9cebSChing-Te Ku { 38468c7e9cebSChing-Te Ku u32 reg; 38478c7e9cebSChing-Te Ku u16 cnt; 38488c7e9cebSChing-Te Ku 38498c7e9cebSChing-Te Ku reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); 38508c7e9cebSChing-Te Ku cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 38518c7e9cebSChing-Te Ku rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 38528c7e9cebSChing-Te Ku 38538c7e9cebSChing-Te Ku return cnt; 38548c7e9cebSChing-Te Ku } 38558c7e9cebSChing-Te Ku 3856e3ec7017SPing-Ke Shih static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 3857e3ec7017SPing-Ke Shih { 3858e3ec7017SPing-Ke Shih u32 reg; 3859e3ec7017SPing-Ke Shih u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 3860e3ec7017SPing-Ke Shih B_AX_BFMEE_HE_NDPA_EN; 3861e3ec7017SPing-Ke Shih 3862e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 3863e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 3864e3ec7017SPing-Ke Shih if (en) { 3865e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 3866e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, mask); 3867e3ec7017SPing-Ke Shih } else { 3868e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 3869e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, mask); 3870e3ec7017SPing-Ke Shih } 3871e3ec7017SPing-Ke Shih } 3872e3ec7017SPing-Ke Shih 3873e3ec7017SPing-Ke Shih static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 3874e3ec7017SPing-Ke Shih { 3875e3ec7017SPing-Ke Shih u32 reg; 3876e3ec7017SPing-Ke Shih u32 val32; 3877e3ec7017SPing-Ke Shih int ret; 3878e3ec7017SPing-Ke Shih 3879e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3880e3ec7017SPing-Ke Shih if (ret) 3881e3ec7017SPing-Ke Shih return ret; 3882e3ec7017SPing-Ke Shih 3883e3ec7017SPing-Ke Shih /* AP mode set tx gid to 63 */ 3884e3ec7017SPing-Ke Shih /* STA mode set tx gid to 0(default) */ 3885e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); 3886e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 3887e3ec7017SPing-Ke Shih 3888e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 3889e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 3890e3ec7017SPing-Ke Shih 3891e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 3892e3ec7017SPing-Ke Shih val32 = FIELD_PREP(B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, BFRP_RX_STANDBY_TIMER); 3893e3ec7017SPing-Ke Shih val32 |= FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 3894e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 3895e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 3896e3ec7017SPing-Ke Shih 3897e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 3898e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 3899e3ec7017SPing-Ke Shih B_AX_BFMEE_USE_NSTS | 3900e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_GID_SEL | 3901e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_FORCE_RETE_EN); 3902e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 3903e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, 3904e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 3905e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 3906e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 3907e3ec7017SPing-Ke Shih 3908e3ec7017SPing-Ke Shih return 0; 3909e3ec7017SPing-Ke Shih } 3910e3ec7017SPing-Ke Shih 3911e3ec7017SPing-Ke Shih static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 3912e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 3913e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 3914e3ec7017SPing-Ke Shih { 3915e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3916e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 3917e3ec7017SPing-Ke Shih u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 3918e3ec7017SPing-Ke Shih u8 port_sel = rtwvif->port; 3919e3ec7017SPing-Ke Shih u8 sound_dim = 3, t; 3920e3ec7017SPing-Ke Shih u8 *phy_cap = sta->he_cap.he_cap_elem.phy_cap_info; 3921e3ec7017SPing-Ke Shih u32 reg; 3922e3ec7017SPing-Ke Shih u16 val; 3923e3ec7017SPing-Ke Shih int ret; 3924e3ec7017SPing-Ke Shih 3925e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3926e3ec7017SPing-Ke Shih if (ret) 3927e3ec7017SPing-Ke Shih return ret; 3928e3ec7017SPing-Ke Shih 3929e3ec7017SPing-Ke Shih if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 3930e3ec7017SPing-Ke Shih (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 3931e3ec7017SPing-Ke Shih ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 3932e3ec7017SPing-Ke Shih stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 3933e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 3934e3ec7017SPing-Ke Shih phy_cap[5]); 3935e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 3936e3ec7017SPing-Ke Shih } 3937e3ec7017SPing-Ke Shih if ((sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 3938e3ec7017SPing-Ke Shih (sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 3939e3ec7017SPing-Ke Shih ldpc_en &= !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 3940e3ec7017SPing-Ke Shih stbc_en &= !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 3941e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 3942e3ec7017SPing-Ke Shih sta->vht_cap.cap); 3943e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 3944e3ec7017SPing-Ke Shih } 3945e3ec7017SPing-Ke Shih nc = min(nc, sound_dim); 3946e3ec7017SPing-Ke Shih nr = min(nr, sound_dim); 3947e3ec7017SPing-Ke Shih 3948e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 3949e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 3950e3ec7017SPing-Ke Shih 3951e3ec7017SPing-Ke Shih val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 3952e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 3953e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 3954e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 3955e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 3956e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 3957e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 3958e3ec7017SPing-Ke Shih 3959e3ec7017SPing-Ke Shih if (port_sel == 0) 3960e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 3961e3ec7017SPing-Ke Shih else 3962e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 3963e3ec7017SPing-Ke Shih 3964e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 3965e3ec7017SPing-Ke Shih 3966e3ec7017SPing-Ke Shih return 0; 3967e3ec7017SPing-Ke Shih } 3968e3ec7017SPing-Ke Shih 3969e3ec7017SPing-Ke Shih static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 3970e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 3971e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 3972e3ec7017SPing-Ke Shih { 3973e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3974e3ec7017SPing-Ke Shih u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 3975e3ec7017SPing-Ke Shih u32 reg; 3976e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 3977e3ec7017SPing-Ke Shih int ret; 3978e3ec7017SPing-Ke Shih 3979e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3980e3ec7017SPing-Ke Shih if (ret) 3981e3ec7017SPing-Ke Shih return ret; 3982e3ec7017SPing-Ke Shih 3983e3ec7017SPing-Ke Shih if (sta->he_cap.has_he) { 3984e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 3985e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 3986e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 3987e3ec7017SPing-Ke Shih } 3988e3ec7017SPing-Ke Shih if (sta->vht_cap.vht_supported) { 3989e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 3990e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 3991e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 3992e3ec7017SPing-Ke Shih } 3993e3ec7017SPing-Ke Shih if (sta->ht_cap.ht_supported) { 3994e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 3995e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 3996e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 3997e3ec7017SPing-Ke Shih } 3998e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 3999e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 4000e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 4001e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, 4002e3ec7017SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 4003e3ec7017SPing-Ke Shih rrsc); 4004e3ec7017SPing-Ke Shih 4005e3ec7017SPing-Ke Shih return 0; 4006e3ec7017SPing-Ke Shih } 4007e3ec7017SPing-Ke Shih 4008e3ec7017SPing-Ke Shih void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4009e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 4010e3ec7017SPing-Ke Shih { 4011e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4012e3ec7017SPing-Ke Shih 4013e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) { 4014e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, 4015e3ec7017SPing-Ke Shih "initialize bfee for new association\n"); 4016e3ec7017SPing-Ke Shih rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 4017e3ec7017SPing-Ke Shih rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 4018e3ec7017SPing-Ke Shih rtw89_mac_csi_rrsc(rtwdev, vif, sta); 4019e3ec7017SPing-Ke Shih } 4020e3ec7017SPing-Ke Shih } 4021e3ec7017SPing-Ke Shih 4022e3ec7017SPing-Ke Shih void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4023e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 4024e3ec7017SPing-Ke Shih { 4025e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4026e3ec7017SPing-Ke Shih 4027e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 4028e3ec7017SPing-Ke Shih } 4029e3ec7017SPing-Ke Shih 4030e3ec7017SPing-Ke Shih void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4031e3ec7017SPing-Ke Shih struct ieee80211_bss_conf *conf) 4032e3ec7017SPing-Ke Shih { 4033e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4034e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 4035e3ec7017SPing-Ke Shih __le32 *p; 4036e3ec7017SPing-Ke Shih 4037e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 4038e3ec7017SPing-Ke Shih 4039e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.membership; 4040e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), 4041e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 4042e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), 4043e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 4044e3ec7017SPing-Ke Shih 4045e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.position; 4046e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), 4047e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 4048e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), 4049e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 4050e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), 4051e3ec7017SPing-Ke Shih le32_to_cpu(p[2])); 4052e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), 4053e3ec7017SPing-Ke Shih le32_to_cpu(p[3])); 4054e3ec7017SPing-Ke Shih } 4055e3ec7017SPing-Ke Shih 4056e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data { 4057e3ec7017SPing-Ke Shih struct rtw89_dev *rtwdev; 4058e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta; 4059e3ec7017SPing-Ke Shih int count; 4060e3ec7017SPing-Ke Shih }; 4061e3ec7017SPing-Ke Shih 4062e3ec7017SPing-Ke Shih static 4063e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 4064e3ec7017SPing-Ke Shih { 4065e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data *iter_data = 4066e3ec7017SPing-Ke Shih (struct rtw89_mac_bf_monitor_iter_data *)data; 4067e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta = iter_data->down_sta; 4068e3ec7017SPing-Ke Shih int *count = &iter_data->count; 4069e3ec7017SPing-Ke Shih 4070e3ec7017SPing-Ke Shih if (down_sta == sta) 4071e3ec7017SPing-Ke Shih return; 4072e3ec7017SPing-Ke Shih 4073e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) 4074e3ec7017SPing-Ke Shih (*count)++; 4075e3ec7017SPing-Ke Shih } 4076e3ec7017SPing-Ke Shih 4077e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 4078e3ec7017SPing-Ke Shih struct ieee80211_sta *sta, bool disconnect) 4079e3ec7017SPing-Ke Shih { 4080e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data data; 4081e3ec7017SPing-Ke Shih 4082e3ec7017SPing-Ke Shih data.rtwdev = rtwdev; 4083e3ec7017SPing-Ke Shih data.down_sta = disconnect ? sta : NULL; 4084e3ec7017SPing-Ke Shih data.count = 0; 4085e3ec7017SPing-Ke Shih ieee80211_iterate_stations_atomic(rtwdev->hw, 4086e3ec7017SPing-Ke Shih rtw89_mac_bf_monitor_calc_iter, 4087e3ec7017SPing-Ke Shih &data); 4088e3ec7017SPing-Ke Shih 4089e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 4090e3ec7017SPing-Ke Shih if (data.count) 4091e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 4092e3ec7017SPing-Ke Shih else 4093e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 4094e3ec7017SPing-Ke Shih } 4095e3ec7017SPing-Ke Shih 4096e3ec7017SPing-Ke Shih void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 4097e3ec7017SPing-Ke Shih { 4098e3ec7017SPing-Ke Shih struct rtw89_traffic_stats *stats = &rtwdev->stats; 4099e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif; 41001646ce8fSYe Guojin bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 4101e3ec7017SPing-Ke Shih bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4102e3ec7017SPing-Ke Shih 4103e3ec7017SPing-Ke Shih if (en == old) 4104e3ec7017SPing-Ke Shih return; 4105e3ec7017SPing-Ke Shih 4106e3ec7017SPing-Ke Shih rtw89_for_each_rtwvif(rtwdev, rtwvif) 4107e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 4108e3ec7017SPing-Ke Shih } 4109e3ec7017SPing-Ke Shih 4110e3ec7017SPing-Ke Shih static int 4111e3ec7017SPing-Ke Shih __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4112e3ec7017SPing-Ke Shih u32 tx_time) 4113e3ec7017SPing-Ke Shih { 4114e3ec7017SPing-Ke Shih #define MAC_AX_DFLT_TX_TIME 5280 4115e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 4116e3ec7017SPing-Ke Shih u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 4117e3ec7017SPing-Ke Shih u32 reg; 4118e3ec7017SPing-Ke Shih int ret = 0; 4119e3ec7017SPing-Ke Shih 4120e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 4121e3ec7017SPing-Ke Shih rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 4122e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4123e3ec7017SPing-Ke Shih } else { 4124e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4125e3ec7017SPing-Ke Shih if (ret) { 4126e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 4127e3ec7017SPing-Ke Shih return ret; 4128e3ec7017SPing-Ke Shih } 4129e3ec7017SPing-Ke Shih 4130e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 4131e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 4132e3ec7017SPing-Ke Shih max_tx_time >> 5); 4133e3ec7017SPing-Ke Shih } 4134e3ec7017SPing-Ke Shih 4135e3ec7017SPing-Ke Shih return ret; 4136e3ec7017SPing-Ke Shih } 4137e3ec7017SPing-Ke Shih 4138e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4139e3ec7017SPing-Ke Shih bool resume, u32 tx_time) 4140e3ec7017SPing-Ke Shih { 4141e3ec7017SPing-Ke Shih int ret = 0; 4142e3ec7017SPing-Ke Shih 4143e3ec7017SPing-Ke Shih if (!resume) { 4144e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = true; 4145e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 4146e3ec7017SPing-Ke Shih } else { 4147e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 4148e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = false; 4149e3ec7017SPing-Ke Shih } 4150e3ec7017SPing-Ke Shih 4151e3ec7017SPing-Ke Shih return ret; 4152e3ec7017SPing-Ke Shih } 4153e3ec7017SPing-Ke Shih 4154e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4155e3ec7017SPing-Ke Shih u32 *tx_time) 4156e3ec7017SPing-Ke Shih { 4157e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 4158e3ec7017SPing-Ke Shih u32 reg; 4159e3ec7017SPing-Ke Shih int ret = 0; 4160e3ec7017SPing-Ke Shih 4161e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 4162e3ec7017SPing-Ke Shih *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 4163e3ec7017SPing-Ke Shih } else { 4164e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4165e3ec7017SPing-Ke Shih if (ret) { 4166e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 4167e3ec7017SPing-Ke Shih return ret; 4168e3ec7017SPing-Ke Shih } 4169e3ec7017SPing-Ke Shih 4170e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 4171e3ec7017SPing-Ke Shih *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 4172e3ec7017SPing-Ke Shih } 4173e3ec7017SPing-Ke Shih 4174e3ec7017SPing-Ke Shih return ret; 4175e3ec7017SPing-Ke Shih } 4176e3ec7017SPing-Ke Shih 4177e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 4178e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, 4179e3ec7017SPing-Ke Shih bool resume, u8 tx_retry) 4180e3ec7017SPing-Ke Shih { 4181e3ec7017SPing-Ke Shih int ret = 0; 4182e3ec7017SPing-Ke Shih 4183e3ec7017SPing-Ke Shih rtwsta->data_tx_cnt_lmt = tx_retry; 4184e3ec7017SPing-Ke Shih 4185e3ec7017SPing-Ke Shih if (!resume) { 4186e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = true; 4187e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4188e3ec7017SPing-Ke Shih } else { 4189e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4190e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = false; 4191e3ec7017SPing-Ke Shih } 4192e3ec7017SPing-Ke Shih 4193e3ec7017SPing-Ke Shih return ret; 4194e3ec7017SPing-Ke Shih } 4195e3ec7017SPing-Ke Shih 4196e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 4197e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, u8 *tx_retry) 4198e3ec7017SPing-Ke Shih { 4199e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 4200e3ec7017SPing-Ke Shih u32 reg; 4201e3ec7017SPing-Ke Shih int ret = 0; 4202e3ec7017SPing-Ke Shih 4203e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_retry_limit) { 4204e3ec7017SPing-Ke Shih *tx_retry = rtwsta->data_tx_cnt_lmt; 4205e3ec7017SPing-Ke Shih } else { 4206e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4207e3ec7017SPing-Ke Shih if (ret) { 4208e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 4209e3ec7017SPing-Ke Shih return ret; 4210e3ec7017SPing-Ke Shih } 4211e3ec7017SPing-Ke Shih 4212e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); 4213e3ec7017SPing-Ke Shih *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 4214e3ec7017SPing-Ke Shih } 4215e3ec7017SPing-Ke Shih 4216e3ec7017SPing-Ke Shih return ret; 4217e3ec7017SPing-Ke Shih } 4218e3ec7017SPing-Ke Shih 4219e3ec7017SPing-Ke Shih int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 4220e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 4221e3ec7017SPing-Ke Shih { 4222e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 4223e3ec7017SPing-Ke Shih u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; 4224e3ec7017SPing-Ke Shih u32 reg; 4225e3ec7017SPing-Ke Shih u32 ret; 4226e3ec7017SPing-Ke Shih 4227e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4228e3ec7017SPing-Ke Shih if (ret) 4229e3ec7017SPing-Ke Shih return ret; 4230e3ec7017SPing-Ke Shih 4231e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); 4232e3ec7017SPing-Ke Shih if (en) 4233e3ec7017SPing-Ke Shih rtw89_write16_set(rtwdev, reg, set); 4234e3ec7017SPing-Ke Shih else 4235e3ec7017SPing-Ke Shih rtw89_write16_clr(rtwdev, reg, set); 4236e3ec7017SPing-Ke Shih 4237e3ec7017SPing-Ke Shih return 0; 4238e3ec7017SPing-Ke Shih } 42392a7e54dbSPing-Ke Shih 42402a7e54dbSPing-Ke Shih int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 42412a7e54dbSPing-Ke Shih { 42422a7e54dbSPing-Ke Shih u32 val32; 42432a7e54dbSPing-Ke Shih int ret; 42442a7e54dbSPing-Ke Shih 42452a7e54dbSPing-Ke Shih val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 42462a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 42472a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 42482a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 42492a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 42502a7e54dbSPing-Ke Shih rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 42512a7e54dbSPing-Ke Shih 42522a7e54dbSPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 42532a7e54dbSPing-Ke Shih 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 42542a7e54dbSPing-Ke Shih if (ret) { 42552a7e54dbSPing-Ke Shih rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 42562a7e54dbSPing-Ke Shih offset, val, mask); 42572a7e54dbSPing-Ke Shih return ret; 42582a7e54dbSPing-Ke Shih } 42592a7e54dbSPing-Ke Shih 42602a7e54dbSPing-Ke Shih return 0; 42612a7e54dbSPing-Ke Shih } 42622a7e54dbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 4263bdfbf06cSPing-Ke Shih 4264bdfbf06cSPing-Ke Shih int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 4265bdfbf06cSPing-Ke Shih { 4266bdfbf06cSPing-Ke Shih u32 val32; 4267bdfbf06cSPing-Ke Shih int ret; 4268bdfbf06cSPing-Ke Shih 4269bdfbf06cSPing-Ke Shih val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 4270bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 4271bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 4272bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 4273bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 4274bdfbf06cSPing-Ke Shih rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 4275bdfbf06cSPing-Ke Shih 4276bdfbf06cSPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 4277bdfbf06cSPing-Ke Shih 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 4278bdfbf06cSPing-Ke Shih if (ret) { 4279bdfbf06cSPing-Ke Shih rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 4280bdfbf06cSPing-Ke Shih return ret; 4281bdfbf06cSPing-Ke Shih } 4282bdfbf06cSPing-Ke Shih 4283bdfbf06cSPing-Ke Shih *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 4284bdfbf06cSPing-Ke Shih 4285bdfbf06cSPing-Ke Shih return 0; 4286bdfbf06cSPing-Ke Shih } 4287