1e3ec7017SPing-Ke Shih // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2e3ec7017SPing-Ke Shih /* Copyright(c) 2019-2020 Realtek Corporation 3e3ec7017SPing-Ke Shih */ 4e3ec7017SPing-Ke Shih 5e3ec7017SPing-Ke Shih #include "cam.h" 6e3ec7017SPing-Ke Shih #include "debug.h" 7e3ec7017SPing-Ke Shih #include "fw.h" 8e3ec7017SPing-Ke Shih #include "mac.h" 9e3ec7017SPing-Ke Shih #include "ps.h" 10e3ec7017SPing-Ke Shih #include "reg.h" 11e3ec7017SPing-Ke Shih #include "util.h" 12e3ec7017SPing-Ke Shih 13ec356ffbSChia-Yuan Li const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = { 14e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 15e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 16e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 17e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 18e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 19e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 20e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 21e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 22e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 23e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 24e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 25e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 26e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 27e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 28e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 29e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 30e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 31ec356ffbSChia-Yuan Li [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 32e1400b11SZong-Zhe Yang }; 33e1400b11SZong-Zhe Yang 34ec356ffbSChia-Yuan Li static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 35ec356ffbSChia-Yuan Li u32 val, enum rtw89_mac_mem_sel sel) 36ec356ffbSChia-Yuan Li { 37ec356ffbSChia-Yuan Li u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 38ec356ffbSChia-Yuan Li 39ec356ffbSChia-Yuan Li rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 40ec356ffbSChia-Yuan Li rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val); 41ec356ffbSChia-Yuan Li } 42ec356ffbSChia-Yuan Li 43ec356ffbSChia-Yuan Li static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 44ec356ffbSChia-Yuan Li enum rtw89_mac_mem_sel sel) 45ec356ffbSChia-Yuan Li { 46ec356ffbSChia-Yuan Li u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 47ec356ffbSChia-Yuan Li 48ec356ffbSChia-Yuan Li rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 49ec356ffbSChia-Yuan Li return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY); 50ec356ffbSChia-Yuan Li } 51ec356ffbSChia-Yuan Li 52e3ec7017SPing-Ke Shih int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 53e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 54e3ec7017SPing-Ke Shih { 55e3ec7017SPing-Ke Shih u32 val, r_val; 56e3ec7017SPing-Ke Shih 57e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 58e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 59e3ec7017SPing-Ke Shih val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 60e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 61e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 62e3ec7017SPing-Ke Shih val = B_AX_CMAC_EN; 63e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 64e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 65e3ec7017SPing-Ke Shih val = B_AX_CMAC1_FEN; 66e3ec7017SPing-Ke Shih } else { 67e3ec7017SPing-Ke Shih return -EINVAL; 68e3ec7017SPing-Ke Shih } 69e3ec7017SPing-Ke Shih if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 70e3ec7017SPing-Ke Shih (val & r_val) != val) 71e3ec7017SPing-Ke Shih return -EFAULT; 72e3ec7017SPing-Ke Shih 73e3ec7017SPing-Ke Shih return 0; 74e3ec7017SPing-Ke Shih } 75e3ec7017SPing-Ke Shih 76e3ec7017SPing-Ke Shih int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 77e3ec7017SPing-Ke Shih { 78e3ec7017SPing-Ke Shih u8 lte_ctrl; 79e3ec7017SPing-Ke Shih int ret; 80e3ec7017SPing-Ke Shih 81e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 82e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 83e3ec7017SPing-Ke Shih if (ret) 84e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 85e3ec7017SPing-Ke Shih 86e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 87e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 88e3ec7017SPing-Ke Shih 89e3ec7017SPing-Ke Shih return ret; 90e3ec7017SPing-Ke Shih } 91e3ec7017SPing-Ke Shih 92e3ec7017SPing-Ke Shih int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 93e3ec7017SPing-Ke Shih { 94e3ec7017SPing-Ke Shih u8 lte_ctrl; 95e3ec7017SPing-Ke Shih int ret; 96e3ec7017SPing-Ke Shih 97e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 98e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 99e3ec7017SPing-Ke Shih if (ret) 100e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 101e3ec7017SPing-Ke Shih 102e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 103e3ec7017SPing-Ke Shih *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 104e3ec7017SPing-Ke Shih 105e3ec7017SPing-Ke Shih return ret; 106e3ec7017SPing-Ke Shih } 107e3ec7017SPing-Ke Shih 108e3ec7017SPing-Ke Shih static 109e3ec7017SPing-Ke Shih int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 110e3ec7017SPing-Ke Shih { 111e3ec7017SPing-Ke Shih u32 ctrl_reg, data_reg, ctrl_data; 112e3ec7017SPing-Ke Shih u32 val; 113e3ec7017SPing-Ke Shih int ret; 114e3ec7017SPing-Ke Shih 115e3ec7017SPing-Ke Shih switch (ctrl->type) { 116e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_WDE: 117e3ec7017SPing-Ke Shih ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 118e3ec7017SPing-Ke Shih data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 119e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 120e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 121e3ec7017SPing-Ke Shih B_AX_WDE_DFI_ACTIVE; 122e3ec7017SPing-Ke Shih break; 123e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_PLE: 124e3ec7017SPing-Ke Shih ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 125e3ec7017SPing-Ke Shih data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 126e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 127e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 128e3ec7017SPing-Ke Shih B_AX_PLE_DFI_ACTIVE; 129e3ec7017SPing-Ke Shih break; 130e3ec7017SPing-Ke Shih default: 131e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 132e3ec7017SPing-Ke Shih return -EINVAL; 133e3ec7017SPing-Ke Shih } 134e3ec7017SPing-Ke Shih 135e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 136e3ec7017SPing-Ke Shih 137e3ec7017SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 138e3ec7017SPing-Ke Shih 1, 1000, false, rtwdev, ctrl_reg); 139e3ec7017SPing-Ke Shih if (ret) { 140e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 141e3ec7017SPing-Ke Shih ctrl_reg, ctrl_data); 142e3ec7017SPing-Ke Shih return ret; 143e3ec7017SPing-Ke Shih } 144e3ec7017SPing-Ke Shih 145e3ec7017SPing-Ke Shih ctrl->out_data = rtw89_read32(rtwdev, data_reg); 146e3ec7017SPing-Ke Shih return 0; 147e3ec7017SPing-Ke Shih } 148e3ec7017SPing-Ke Shih 149e3ec7017SPing-Ke Shih static int dle_dfi_quota(struct rtw89_dev *rtwdev, 150e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota *quota) 151e3ec7017SPing-Ke Shih { 152e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 153e3ec7017SPing-Ke Shih int ret; 154e3ec7017SPing-Ke Shih 155e3ec7017SPing-Ke Shih ctrl.type = quota->dle_type; 156e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QUOTA; 157e3ec7017SPing-Ke Shih ctrl.addr = quota->qtaid; 158e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 159e3ec7017SPing-Ke Shih if (ret) { 160e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 161e3ec7017SPing-Ke Shih return ret; 162e3ec7017SPing-Ke Shih } 163e3ec7017SPing-Ke Shih 164e3ec7017SPing-Ke Shih quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 165e3ec7017SPing-Ke Shih quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 166e3ec7017SPing-Ke Shih return 0; 167e3ec7017SPing-Ke Shih } 168e3ec7017SPing-Ke Shih 169e3ec7017SPing-Ke Shih static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 170e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty *qempty) 171e3ec7017SPing-Ke Shih { 172e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 173e3ec7017SPing-Ke Shih u32 ret; 174e3ec7017SPing-Ke Shih 175e3ec7017SPing-Ke Shih ctrl.type = qempty->dle_type; 176e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QEMPTY; 177e3ec7017SPing-Ke Shih ctrl.addr = qempty->grpsel; 178e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 179e3ec7017SPing-Ke Shih if (ret) { 180e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 181e3ec7017SPing-Ke Shih return ret; 182e3ec7017SPing-Ke Shih } 183e3ec7017SPing-Ke Shih 184e3ec7017SPing-Ke Shih qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 185e3ec7017SPing-Ke Shih return 0; 186e3ec7017SPing-Ke Shih } 187e3ec7017SPing-Ke Shih 188e3ec7017SPing-Ke Shih static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 189e3ec7017SPing-Ke Shih { 190e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 191e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 192e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 193e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 194e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 195e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 196e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 197e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 198e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 199e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 200e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 201e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 202e3ec7017SPing-Ke Shih } 203e3ec7017SPing-Ke Shih 204e3ec7017SPing-Ke Shih static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 205e3ec7017SPing-Ke Shih { 206e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty qempty; 207e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota quota; 208e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 209e3ec7017SPing-Ke Shih u32 val, not_empty, i; 210e3ec7017SPing-Ke Shih int ret; 211e3ec7017SPing-Ke Shih 212e3ec7017SPing-Ke Shih qempty.dle_type = DLE_CTRL_TYPE_PLE; 213e3ec7017SPing-Ke Shih qempty.grpsel = 0; 21489e4a00fSÍñigo Huguet qempty.qempty = ~(u32)0; 215e3ec7017SPing-Ke Shih ret = dle_dfi_qempty(rtwdev, &qempty); 216e3ec7017SPing-Ke Shih if (ret) 217e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 218e3ec7017SPing-Ke Shih else 219e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 220e3ec7017SPing-Ke Shih 221e3ec7017SPing-Ke Shih for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 222e3ec7017SPing-Ke Shih if (!(not_empty & BIT(0))) 223e3ec7017SPing-Ke Shih continue; 224e3ec7017SPing-Ke Shih ctrl.type = DLE_CTRL_TYPE_PLE; 225e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QLNKTBL; 226e3ec7017SPing-Ke Shih ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 227e3ec7017SPing-Ke Shih FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 228e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 229e3ec7017SPing-Ke Shih if (ret) 230e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 231e3ec7017SPing-Ke Shih else 232e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 233e3ec7017SPing-Ke Shih FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 234e3ec7017SPing-Ke Shih ctrl.out_data)); 235e3ec7017SPing-Ke Shih } 236e3ec7017SPing-Ke Shih 237e3ec7017SPing-Ke Shih quota.dle_type = DLE_CTRL_TYPE_PLE; 238e3ec7017SPing-Ke Shih quota.qtaid = 6; 239e3ec7017SPing-Ke Shih ret = dle_dfi_quota(rtwdev, "a); 240e3ec7017SPing-Ke Shih if (ret) 241e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 242e3ec7017SPing-Ke Shih else 243e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 244e3ec7017SPing-Ke Shih quota.rsv_pgnum, quota.use_pgnum); 245e3ec7017SPing-Ke Shih 246e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 247e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 248e3ec7017SPing-Ke Shih FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 249e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 250e3ec7017SPing-Ke Shih FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 251e3ec7017SPing-Ke Shih 252e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 253e3ec7017SPing-Ke Shih } 254e3ec7017SPing-Ke Shih 255e3ec7017SPing-Ke Shih static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 256e3ec7017SPing-Ke Shih enum mac_ax_err_info err) 257e3ec7017SPing-Ke Shih { 258e3ec7017SPing-Ke Shih u32 dbg, event; 259e3ec7017SPing-Ke Shih 260e3ec7017SPing-Ke Shih dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 261e3ec7017SPing-Ke Shih event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 262e3ec7017SPing-Ke Shih 263e3ec7017SPing-Ke Shih switch (event) { 264e3ec7017SPing-Ke Shih case MAC_AX_L0_TO_L1_RX_QTA_LOST: 265e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota lost!\n"); 266e3ec7017SPing-Ke Shih rtw89_mac_dump_qta_lost(rtwdev); 267e3ec7017SPing-Ke Shih break; 268e3ec7017SPing-Ke Shih default: 269e3ec7017SPing-Ke Shih break; 270e3ec7017SPing-Ke Shih } 271e3ec7017SPing-Ke Shih } 272e3ec7017SPing-Ke Shih 273e3ec7017SPing-Ke Shih static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 274e3ec7017SPing-Ke Shih enum mac_ax_err_info err) 275e3ec7017SPing-Ke Shih { 276e3ec7017SPing-Ke Shih u32 dmac_err, cmac_err; 277e3ec7017SPing-Ke Shih 278e3ec7017SPing-Ke Shih if (err != MAC_AX_ERR_L1_ERR_DMAC && 279198b6cf7SZong-Zhe Yang err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 280198b6cf7SZong-Zhe Yang err != MAC_AX_ERR_L0_ERR_CMAC0 && 281198b6cf7SZong-Zhe Yang err != MAC_AX_ERR_L0_ERR_CMAC1) 282e3ec7017SPing-Ke Shih return; 283e3ec7017SPing-Ke Shih 284e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 285e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 286e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 287e3ec7017SPing-Ke Shih 288e3ec7017SPing-Ke Shih cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR); 289e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err); 290e3ec7017SPing-Ke Shih dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 291e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err); 292e3ec7017SPing-Ke Shih 293e3ec7017SPing-Ke Shih if (dmac_err) { 294e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ", 295e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG)); 296e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n", 297e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG)); 298e3ec7017SPing-Ke Shih } 299e3ec7017SPing-Ke Shih 300e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 301e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ", 302e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 303e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n", 304e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 305e3ec7017SPing-Ke Shih } 306e3ec7017SPing-Ke Shih 307e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WSEC_ERR_FLAG) { 308e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n", 309e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 310e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n", 311e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 312e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n", 313e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 314e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n", 315e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 316e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n", 317e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 318e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n", 319e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 320e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n", 321e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 322e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n", 323e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 324e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n", 325e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 326e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n", 327e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 328e3ec7017SPing-Ke Shih } 329e3ec7017SPing-Ke Shih 330e3ec7017SPing-Ke Shih if (dmac_err & B_AX_MPDU_ERR_FLAG) { 331e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ", 332e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 333e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n", 334e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 335e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ", 336e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 337e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n", 338e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 339e3ec7017SPing-Ke Shih } 340e3ec7017SPing-Ke Shih 341e3ec7017SPing-Ke Shih if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 342e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ", 343e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 344e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n", 345e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 346e3ec7017SPing-Ke Shih } 347e3ec7017SPing-Ke Shih 348e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 349e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", 350e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 351e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 352e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 353e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", 354e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 355e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 356e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 357e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 358e3ec7017SPing-Ke Shih } 359e3ec7017SPing-Ke Shih 360e3ec7017SPing-Ke Shih if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 361e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 362e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 363e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 364e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 365e3ec7017SPing-Ke Shih } 366e3ec7017SPing-Ke Shih 367e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 368e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", 369e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 370e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 371e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 372e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", 373e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 374e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 375e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 376e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 377e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 378e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 379e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 380e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 381e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 382e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 383e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 384e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 385e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 386e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 387e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 388e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 389e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 390e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 391e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 392e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 393e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 394e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 395e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 396e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 397e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 398e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 399e3ec7017SPing-Ke Shih } 400e3ec7017SPing-Ke Shih 401e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 402e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", 403e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 404e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", 405e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 406e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", 407e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 408e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", 409e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 410e3ec7017SPing-Ke Shih } 411e3ec7017SPing-Ke Shih 412e3ec7017SPing-Ke Shih if (dmac_err & B_AX_DISPATCH_ERR_FLAG) 413e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 414e3ec7017SPing-Ke Shih 415e3ec7017SPing-Ke Shih if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) { 416e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ", 417e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR)); 418e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n", 419e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); 420e3ec7017SPing-Ke Shih } 421e3ec7017SPing-Ke Shih 422e3ec7017SPing-Ke Shih if (dmac_err & BIT(11)) { 423e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 424e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 425e3ec7017SPing-Ke Shih } 426e3ec7017SPing-Ke Shih 427e3ec7017SPing-Ke Shih if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 428e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ", 429e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR)); 430e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n", 431e3ec7017SPing-Ke Shih rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR)); 432e3ec7017SPing-Ke Shih } 433e3ec7017SPing-Ke Shih 434e3ec7017SPing-Ke Shih if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 435e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ", 436e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PTCL_IMR0)); 437e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n", 438e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); 439e3ec7017SPing-Ke Shih } 440e3ec7017SPing-Ke Shih 441e3ec7017SPing-Ke Shih if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 442e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n", 443e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_DLE_CTRL)); 444e3ec7017SPing-Ke Shih } 445e3ec7017SPing-Ke Shih 446e3ec7017SPing-Ke Shih if (cmac_err & B_AX_PHYINTF_ERR_IND) { 447e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n", 448e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR)); 449e3ec7017SPing-Ke Shih } 450e3ec7017SPing-Ke Shih 451e3ec7017SPing-Ke Shih if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 452e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ", 453e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPWR_IMR)); 454e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n", 455e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); 456e3ec7017SPing-Ke Shih } 457e3ec7017SPing-Ke Shih 458e3ec7017SPing-Ke Shih if (cmac_err & B_AX_WMAC_RX_ERR_IND) { 459e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ", 460e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); 461e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n", 462e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); 463e3ec7017SPing-Ke Shih } 464e3ec7017SPing-Ke Shih 465e3ec7017SPing-Ke Shih if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 466e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ", 467e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); 468e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n", 469e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); 470e3ec7017SPing-Ke Shih } 471e3ec7017SPing-Ke Shih 472e3ec7017SPing-Ke Shih rtwdev->hci.ops->dump_err_status(rtwdev); 473e3ec7017SPing-Ke Shih 474e3ec7017SPing-Ke Shih if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 475e3ec7017SPing-Ke Shih rtw89_mac_dump_l0_to_l1(rtwdev, err); 476e3ec7017SPing-Ke Shih 477e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "<---\n"); 478e3ec7017SPing-Ke Shih } 479e3ec7017SPing-Ke Shih 480e3ec7017SPing-Ke Shih u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 481e3ec7017SPing-Ke Shih { 482198b6cf7SZong-Zhe Yang u32 err, err_scnr; 483e3ec7017SPing-Ke Shih int ret; 484e3ec7017SPing-Ke Shih 485e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 486e3ec7017SPing-Ke Shih false, rtwdev, R_AX_HALT_C2H_CTRL); 487e3ec7017SPing-Ke Shih if (ret) { 488e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "Polling FW err status fail\n"); 489e3ec7017SPing-Ke Shih return ret; 490e3ec7017SPing-Ke Shih } 491e3ec7017SPing-Ke Shih 492e3ec7017SPing-Ke Shih err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 493e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 494e3ec7017SPing-Ke Shih 495198b6cf7SZong-Zhe Yang err_scnr = RTW89_ERROR_SCENARIO(err); 496198b6cf7SZong-Zhe Yang if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 497198b6cf7SZong-Zhe Yang err = MAC_AX_ERR_CPU_EXCEPTION; 498198b6cf7SZong-Zhe Yang else if (err_scnr == RTW89_WCPU_ASSERTION) 499198b6cf7SZong-Zhe Yang err = MAC_AX_ERR_ASSERTION; 500198b6cf7SZong-Zhe Yang 501e3ec7017SPing-Ke Shih rtw89_fw_st_dbg_dump(rtwdev); 502e3ec7017SPing-Ke Shih rtw89_mac_dump_err_status(rtwdev, err); 503e3ec7017SPing-Ke Shih 504e3ec7017SPing-Ke Shih return err; 505e3ec7017SPing-Ke Shih } 506e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_get_err_status); 507e3ec7017SPing-Ke Shih 508e3ec7017SPing-Ke Shih int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 509e3ec7017SPing-Ke Shih { 510e3ec7017SPing-Ke Shih u32 halt; 511e3ec7017SPing-Ke Shih int ret = 0; 512e3ec7017SPing-Ke Shih 513e3ec7017SPing-Ke Shih if (err > MAC_AX_SET_ERR_MAX) { 514e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 515e3ec7017SPing-Ke Shih return -EINVAL; 516e3ec7017SPing-Ke Shih } 517e3ec7017SPing-Ke Shih 518e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 519e3ec7017SPing-Ke Shih 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 520e3ec7017SPing-Ke Shih if (ret) { 521e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 522e3ec7017SPing-Ke Shih return -EFAULT; 523e3ec7017SPing-Ke Shih } 524e3ec7017SPing-Ke Shih 525e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 526e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 527e3ec7017SPing-Ke Shih 528e3ec7017SPing-Ke Shih return 0; 529e3ec7017SPing-Ke Shih } 530e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_set_err_status); 531e3ec7017SPing-Ke Shih 532e3ec7017SPing-Ke Shih static int hfc_reset_param(struct rtw89_dev *rtwdev) 533e3ec7017SPing-Ke Shih { 534e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 535e3ec7017SPing-Ke Shih struct rtw89_hfc_param_ini param_ini = {NULL}; 536e3ec7017SPing-Ke Shih u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 537e3ec7017SPing-Ke Shih 538e3ec7017SPing-Ke Shih switch (rtwdev->hci.type) { 539e3ec7017SPing-Ke Shih case RTW89_HCI_TYPE_PCIE: 540e3ec7017SPing-Ke Shih param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 541e3ec7017SPing-Ke Shih param->en = 0; 542e3ec7017SPing-Ke Shih break; 543e3ec7017SPing-Ke Shih default: 544e3ec7017SPing-Ke Shih return -EINVAL; 545e3ec7017SPing-Ke Shih } 546e3ec7017SPing-Ke Shih 547e3ec7017SPing-Ke Shih if (param_ini.pub_cfg) 548e3ec7017SPing-Ke Shih param->pub_cfg = *param_ini.pub_cfg; 549e3ec7017SPing-Ke Shih 550e3ec7017SPing-Ke Shih if (param_ini.prec_cfg) { 551e3ec7017SPing-Ke Shih param->prec_cfg = *param_ini.prec_cfg; 552e3ec7017SPing-Ke Shih rtwdev->hal.sw_amsdu_max_size = 553e3ec7017SPing-Ke Shih param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; 554e3ec7017SPing-Ke Shih } 555e3ec7017SPing-Ke Shih 556e3ec7017SPing-Ke Shih if (param_ini.ch_cfg) 557e3ec7017SPing-Ke Shih param->ch_cfg = param_ini.ch_cfg; 558e3ec7017SPing-Ke Shih 559e3ec7017SPing-Ke Shih memset(¶m->ch_info, 0, sizeof(param->ch_info)); 560e3ec7017SPing-Ke Shih memset(¶m->pub_info, 0, sizeof(param->pub_info)); 561e3ec7017SPing-Ke Shih param->mode = param_ini.mode; 562e3ec7017SPing-Ke Shih 563e3ec7017SPing-Ke Shih return 0; 564e3ec7017SPing-Ke Shih } 565e3ec7017SPing-Ke Shih 566e3ec7017SPing-Ke Shih static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 567e3ec7017SPing-Ke Shih { 568e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 569e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 570e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 571e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 572e3ec7017SPing-Ke Shih 573e3ec7017SPing-Ke Shih if (ch >= RTW89_DMA_CH_NUM) 574e3ec7017SPing-Ke Shih return -EINVAL; 575e3ec7017SPing-Ke Shih 576e3ec7017SPing-Ke Shih if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 577e3ec7017SPing-Ke Shih ch_cfg[ch].max > pub_cfg->pub_max) 578e3ec7017SPing-Ke Shih return -EINVAL; 579e3ec7017SPing-Ke Shih if (ch_cfg[ch].grp >= grp_num) 580e3ec7017SPing-Ke Shih return -EINVAL; 581e3ec7017SPing-Ke Shih 582e3ec7017SPing-Ke Shih return 0; 583e3ec7017SPing-Ke Shih } 584e3ec7017SPing-Ke Shih 585e3ec7017SPing-Ke Shih static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 586e3ec7017SPing-Ke Shih { 587e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 588e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 589e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 590e3ec7017SPing-Ke Shih 591e3ec7017SPing-Ke Shih if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 592e3ec7017SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852A) 593e3ec7017SPing-Ke Shih return 0; 594e3ec7017SPing-Ke Shih else 595e3ec7017SPing-Ke Shih return -EFAULT; 596e3ec7017SPing-Ke Shih } 597e3ec7017SPing-Ke Shih 598e3ec7017SPing-Ke Shih return 0; 599e3ec7017SPing-Ke Shih } 600e3ec7017SPing-Ke Shih 601e3ec7017SPing-Ke Shih static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 602e3ec7017SPing-Ke Shih { 603e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 604e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 605e3ec7017SPing-Ke Shih 606e3ec7017SPing-Ke Shih if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 607c6477cb2SKevin Lo return -EFAULT; 608e3ec7017SPing-Ke Shih 609e3ec7017SPing-Ke Shih return 0; 610e3ec7017SPing-Ke Shih } 611e3ec7017SPing-Ke Shih 612e3ec7017SPing-Ke Shih static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 613e3ec7017SPing-Ke Shih { 614ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 615ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 616e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 617e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 618e3ec7017SPing-Ke Shih int ret = 0; 619e3ec7017SPing-Ke Shih u32 val = 0; 620e3ec7017SPing-Ke Shih 621e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 622e3ec7017SPing-Ke Shih if (ret) 623e3ec7017SPing-Ke Shih return ret; 624e3ec7017SPing-Ke Shih 625e3ec7017SPing-Ke Shih ret = hfc_ch_cfg_chk(rtwdev, ch); 626e3ec7017SPing-Ke Shih if (ret) 627e3ec7017SPing-Ke Shih return ret; 628e3ec7017SPing-Ke Shih 629e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_B1HI) 630e3ec7017SPing-Ke Shih return -EINVAL; 631e3ec7017SPing-Ke Shih 632e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 633e3ec7017SPing-Ke Shih u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 634e3ec7017SPing-Ke Shih (cfg[ch].grp ? B_AX_GRP : 0); 635ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 636e3ec7017SPing-Ke Shih 637e3ec7017SPing-Ke Shih return 0; 638e3ec7017SPing-Ke Shih } 639e3ec7017SPing-Ke Shih 640e3ec7017SPing-Ke Shih static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 641e3ec7017SPing-Ke Shih { 642ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 643ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 644e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 645e3ec7017SPing-Ke Shih struct rtw89_hfc_ch_info *info = param->ch_info; 646e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 647e3ec7017SPing-Ke Shih u32 val; 648e3ec7017SPing-Ke Shih u32 ret; 649e3ec7017SPing-Ke Shih 650e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 651e3ec7017SPing-Ke Shih if (ret) 652e3ec7017SPing-Ke Shih return ret; 653e3ec7017SPing-Ke Shih 654e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_H2C) 655e3ec7017SPing-Ke Shih return -EINVAL; 656e3ec7017SPing-Ke Shih 657ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 658e3ec7017SPing-Ke Shih info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 659e3ec7017SPing-Ke Shih if (ch < RTW89_DMA_H2C) 660e3ec7017SPing-Ke Shih info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 661e3ec7017SPing-Ke Shih else 662e3ec7017SPing-Ke Shih info[ch].used = cfg[ch].min - info[ch].aval; 663e3ec7017SPing-Ke Shih 664e3ec7017SPing-Ke Shih return 0; 665e3ec7017SPing-Ke Shih } 666e3ec7017SPing-Ke Shih 667e3ec7017SPing-Ke Shih static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 668e3ec7017SPing-Ke Shih { 669ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 670ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 671e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 672e3ec7017SPing-Ke Shih u32 val; 673e3ec7017SPing-Ke Shih int ret; 674e3ec7017SPing-Ke Shih 675e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 676e3ec7017SPing-Ke Shih if (ret) 677e3ec7017SPing-Ke Shih return ret; 678e3ec7017SPing-Ke Shih 679e3ec7017SPing-Ke Shih ret = hfc_pub_cfg_chk(rtwdev); 680e3ec7017SPing-Ke Shih if (ret) 681e3ec7017SPing-Ke Shih return ret; 682e3ec7017SPing-Ke Shih 683e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 684e3ec7017SPing-Ke Shih u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 685ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 686e3ec7017SPing-Ke Shih 687e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 688ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 689e3ec7017SPing-Ke Shih 690e3ec7017SPing-Ke Shih return 0; 691e3ec7017SPing-Ke Shih } 692e3ec7017SPing-Ke Shih 693e3ec7017SPing-Ke Shih static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 694e3ec7017SPing-Ke Shih { 695ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 696ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 697e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 698e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 699e3ec7017SPing-Ke Shih struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 700e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 701e3ec7017SPing-Ke Shih u32 val; 702e3ec7017SPing-Ke Shih int ret; 703e3ec7017SPing-Ke Shih 704e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 705e3ec7017SPing-Ke Shih if (ret) 706e3ec7017SPing-Ke Shih return ret; 707e3ec7017SPing-Ke Shih 708ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_info1); 709e3ec7017SPing-Ke Shih info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 710e3ec7017SPing-Ke Shih info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 711ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_info3); 712e3ec7017SPing-Ke Shih info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 713e3ec7017SPing-Ke Shih info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 714e3ec7017SPing-Ke Shih info->pub_aval = 715ab8a5671SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 716e3ec7017SPing-Ke Shih B_AX_PUB_AVAL_PG_MASK); 717e3ec7017SPing-Ke Shih info->wp_aval = 718ab8a5671SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 719e3ec7017SPing-Ke Shih B_AX_WP_AVAL_PG_MASK); 720e3ec7017SPing-Ke Shih 721ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 722e3ec7017SPing-Ke Shih param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 723e3ec7017SPing-Ke Shih param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 724e3ec7017SPing-Ke Shih param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 725e3ec7017SPing-Ke Shih prec_cfg->ch011_full_cond = 726e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 727e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond = 728e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 729e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_full_cond = 730e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 731e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_full_cond = 732e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 733e3ec7017SPing-Ke Shih 734ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 735e3ec7017SPing-Ke Shih prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 736e3ec7017SPing-Ke Shih prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 737e3ec7017SPing-Ke Shih 738ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 739e3ec7017SPing-Ke Shih pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 740e3ec7017SPing-Ke Shih 741ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 742e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 743e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 744e3ec7017SPing-Ke Shih 745ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 746e3ec7017SPing-Ke Shih pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 747e3ec7017SPing-Ke Shih 748ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 749e3ec7017SPing-Ke Shih pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 750e3ec7017SPing-Ke Shih pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 751e3ec7017SPing-Ke Shih 752e3ec7017SPing-Ke Shih ret = hfc_pub_info_chk(rtwdev); 753e3ec7017SPing-Ke Shih if (param->en && ret) 754e3ec7017SPing-Ke Shih return ret; 755e3ec7017SPing-Ke Shih 756e3ec7017SPing-Ke Shih return 0; 757e3ec7017SPing-Ke Shih } 758e3ec7017SPing-Ke Shih 759e3ec7017SPing-Ke Shih static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 760e3ec7017SPing-Ke Shih { 761ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 762ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 763e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 764e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 765e3ec7017SPing-Ke Shih u32 val; 766e3ec7017SPing-Ke Shih 767e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 768ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 769e3ec7017SPing-Ke Shih 770ab8a5671SPing-Ke Shih rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 771e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK, 772e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond); 773e3ec7017SPing-Ke Shih } 774e3ec7017SPing-Ke Shih 775e3ec7017SPing-Ke Shih static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 776e3ec7017SPing-Ke Shih { 777ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 778ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 779e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 780e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 781e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 782e3ec7017SPing-Ke Shih u32 val; 783e3ec7017SPing-Ke Shih 784e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 785e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 786ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 787e3ec7017SPing-Ke Shih 788e3ec7017SPing-Ke Shih val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 789ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 790e3ec7017SPing-Ke Shih 791e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->wp_ch07_prec, 792e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH07_MASK) | 793e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->wp_ch811_prec, 794e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH811_MASK); 795ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 796e3ec7017SPing-Ke Shih 797ab8a5671SPing-Ke Shih val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 798e3ec7017SPing-Ke Shih param->mode, B_AX_HCI_FC_MODE_MASK); 799e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 800e3ec7017SPing-Ke Shih B_AX_HCI_FC_WD_FULL_COND_MASK); 801e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 802e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK); 803e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 804e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 805e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 806e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 807ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 808e3ec7017SPing-Ke Shih } 809e3ec7017SPing-Ke Shih 810e3ec7017SPing-Ke Shih static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 811e3ec7017SPing-Ke Shih { 812ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 813ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 814e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 815e3ec7017SPing-Ke Shih u32 val; 816e3ec7017SPing-Ke Shih 817ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 818e3ec7017SPing-Ke Shih param->en = en; 819e3ec7017SPing-Ke Shih param->h2c_en = h2c_en; 820e3ec7017SPing-Ke Shih val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 821e3ec7017SPing-Ke Shih val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 822e3ec7017SPing-Ke Shih (val & ~B_AX_HCI_FC_CH12_EN); 823ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 824e3ec7017SPing-Ke Shih } 825e3ec7017SPing-Ke Shih 826e3ec7017SPing-Ke Shih static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 827e3ec7017SPing-Ke Shih { 828e3ec7017SPing-Ke Shih u8 ch; 829e3ec7017SPing-Ke Shih u32 ret = 0; 830e3ec7017SPing-Ke Shih 831e3ec7017SPing-Ke Shih if (reset) 832e3ec7017SPing-Ke Shih ret = hfc_reset_param(rtwdev); 833e3ec7017SPing-Ke Shih if (ret) 834e3ec7017SPing-Ke Shih return ret; 835e3ec7017SPing-Ke Shih 836e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 837e3ec7017SPing-Ke Shih if (ret) 838e3ec7017SPing-Ke Shih return ret; 839e3ec7017SPing-Ke Shih 840e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, false, false); 841e3ec7017SPing-Ke Shih 842e3ec7017SPing-Ke Shih if (!en && h2c_en) { 843e3ec7017SPing-Ke Shih hfc_h2c_cfg(rtwdev); 844e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, en, h2c_en); 845e3ec7017SPing-Ke Shih return ret; 846e3ec7017SPing-Ke Shih } 847e3ec7017SPing-Ke Shih 848e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 849e3ec7017SPing-Ke Shih ret = hfc_ch_ctrl(rtwdev, ch); 850e3ec7017SPing-Ke Shih if (ret) 851e3ec7017SPing-Ke Shih return ret; 852e3ec7017SPing-Ke Shih } 853e3ec7017SPing-Ke Shih 854e3ec7017SPing-Ke Shih ret = hfc_pub_ctrl(rtwdev); 855e3ec7017SPing-Ke Shih if (ret) 856e3ec7017SPing-Ke Shih return ret; 857e3ec7017SPing-Ke Shih 858e3ec7017SPing-Ke Shih hfc_mix_cfg(rtwdev); 859e3ec7017SPing-Ke Shih if (en || h2c_en) { 860e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, en, h2c_en); 861e3ec7017SPing-Ke Shih udelay(10); 862e3ec7017SPing-Ke Shih } 863e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 864e3ec7017SPing-Ke Shih ret = hfc_upd_ch_info(rtwdev, ch); 865e3ec7017SPing-Ke Shih if (ret) 866e3ec7017SPing-Ke Shih return ret; 867e3ec7017SPing-Ke Shih } 868e3ec7017SPing-Ke Shih ret = hfc_upd_mix_info(rtwdev); 869e3ec7017SPing-Ke Shih 870e3ec7017SPing-Ke Shih return ret; 871e3ec7017SPing-Ke Shih } 872e3ec7017SPing-Ke Shih 873e3ec7017SPing-Ke Shih #define PWR_POLL_CNT 2000 874e3ec7017SPing-Ke Shih static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 875e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cfg) 876e3ec7017SPing-Ke Shih { 877e3ec7017SPing-Ke Shih u8 val = 0; 878e3ec7017SPing-Ke Shih int ret; 879e3ec7017SPing-Ke Shih u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 880e3ec7017SPing-Ke Shih cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 881e3ec7017SPing-Ke Shih 882e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 883e3ec7017SPing-Ke Shih 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 884e3ec7017SPing-Ke Shih 885e3ec7017SPing-Ke Shih if (!ret) 886e3ec7017SPing-Ke Shih return 0; 887e3ec7017SPing-Ke Shih 888e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 889e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 890e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 891e3ec7017SPing-Ke Shih 892e3ec7017SPing-Ke Shih return -EBUSY; 893e3ec7017SPing-Ke Shih } 894e3ec7017SPing-Ke Shih 895e3ec7017SPing-Ke Shih static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 896e3ec7017SPing-Ke Shih u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 897e3ec7017SPing-Ke Shih { 898e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cur_cfg; 899e3ec7017SPing-Ke Shih u32 addr; 900e3ec7017SPing-Ke Shih u8 val; 901e3ec7017SPing-Ke Shih 902e3ec7017SPing-Ke Shih for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 903e3ec7017SPing-Ke Shih if (!(cur_cfg->intf_msk & intf_msk) || 904e3ec7017SPing-Ke Shih !(cur_cfg->cv_msk & cv_msk)) 905e3ec7017SPing-Ke Shih continue; 906e3ec7017SPing-Ke Shih 907e3ec7017SPing-Ke Shih switch (cur_cfg->cmd) { 908e3ec7017SPing-Ke Shih case PWR_CMD_WRITE: 909e3ec7017SPing-Ke Shih addr = cur_cfg->addr; 910e3ec7017SPing-Ke Shih 911e3ec7017SPing-Ke Shih if (cur_cfg->base == PWR_BASE_SDIO) 912e3ec7017SPing-Ke Shih addr |= SDIO_LOCAL_BASE_ADDR; 913e3ec7017SPing-Ke Shih 914e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, addr); 915e3ec7017SPing-Ke Shih val &= ~(cur_cfg->msk); 916e3ec7017SPing-Ke Shih val |= (cur_cfg->val & cur_cfg->msk); 917e3ec7017SPing-Ke Shih 918e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, addr, val); 919e3ec7017SPing-Ke Shih break; 920e3ec7017SPing-Ke Shih case PWR_CMD_POLL: 921e3ec7017SPing-Ke Shih if (pwr_cmd_poll(rtwdev, cur_cfg)) 922e3ec7017SPing-Ke Shih return -EBUSY; 923e3ec7017SPing-Ke Shih break; 924e3ec7017SPing-Ke Shih case PWR_CMD_DELAY: 925e3ec7017SPing-Ke Shih if (cur_cfg->val == PWR_DELAY_US) 926e3ec7017SPing-Ke Shih udelay(cur_cfg->addr); 927e3ec7017SPing-Ke Shih else 928e3ec7017SPing-Ke Shih fsleep(cur_cfg->addr * 1000); 929e3ec7017SPing-Ke Shih break; 930e3ec7017SPing-Ke Shih default: 931e3ec7017SPing-Ke Shih return -EINVAL; 932e3ec7017SPing-Ke Shih } 933e3ec7017SPing-Ke Shih } 934e3ec7017SPing-Ke Shih 935e3ec7017SPing-Ke Shih return 0; 936e3ec7017SPing-Ke Shih } 937e3ec7017SPing-Ke Shih 938e3ec7017SPing-Ke Shih static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 939e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq) 940e3ec7017SPing-Ke Shih { 941e3ec7017SPing-Ke Shih int ret; 942e3ec7017SPing-Ke Shih 943e3ec7017SPing-Ke Shih for (; *cfg_seq; cfg_seq++) { 944e3ec7017SPing-Ke Shih ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 945e3ec7017SPing-Ke Shih PWR_INTF_MSK_PCIE, *cfg_seq); 946e3ec7017SPing-Ke Shih if (ret) 947e3ec7017SPing-Ke Shih return -EBUSY; 948e3ec7017SPing-Ke Shih } 949e3ec7017SPing-Ke Shih 950e3ec7017SPing-Ke Shih return 0; 951e3ec7017SPing-Ke Shih } 952e3ec7017SPing-Ke Shih 953e3ec7017SPing-Ke Shih static enum rtw89_rpwm_req_pwr_state 954e3ec7017SPing-Ke Shih rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 955e3ec7017SPing-Ke Shih { 956e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 957e3ec7017SPing-Ke Shih 958e3ec7017SPing-Ke Shih switch (rtwdev->ps_mode) { 959e3ec7017SPing-Ke Shih case RTW89_PS_MODE_RFOFF: 960e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 961e3ec7017SPing-Ke Shih break; 962e3ec7017SPing-Ke Shih case RTW89_PS_MODE_CLK_GATED: 963e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 964e3ec7017SPing-Ke Shih break; 965e3ec7017SPing-Ke Shih case RTW89_PS_MODE_PWR_GATED: 966e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 967e3ec7017SPing-Ke Shih break; 968e3ec7017SPing-Ke Shih default: 969e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 970e3ec7017SPing-Ke Shih break; 971e3ec7017SPing-Ke Shih } 972e3ec7017SPing-Ke Shih return state; 973e3ec7017SPing-Ke Shih } 974e3ec7017SPing-Ke Shih 975e3ec7017SPing-Ke Shih static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 9767bfd05ffSChin-Yen Lee enum rtw89_rpwm_req_pwr_state req_pwr_state, 9777bfd05ffSChin-Yen Lee bool notify_wake) 978e3ec7017SPing-Ke Shih { 979e3ec7017SPing-Ke Shih u16 request; 980e3ec7017SPing-Ke Shih 9817bfd05ffSChin-Yen Lee spin_lock_bh(&rtwdev->rpwm_lock); 9827bfd05ffSChin-Yen Lee 983e3ec7017SPing-Ke Shih request = rtw89_read16(rtwdev, R_AX_RPWM); 984e3ec7017SPing-Ke Shih request ^= request | PS_RPWM_TOGGLE; 9857bfd05ffSChin-Yen Lee request |= req_pwr_state; 986e3ec7017SPing-Ke Shih 9877bfd05ffSChin-Yen Lee if (notify_wake) { 9887bfd05ffSChin-Yen Lee request |= PS_RPWM_NOTIFY_WAKE; 9897bfd05ffSChin-Yen Lee } else { 990e3ec7017SPing-Ke Shih rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 991e3ec7017SPing-Ke Shih RPWM_SEQ_NUM_MAX; 9927bfd05ffSChin-Yen Lee request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 9937bfd05ffSChin-Yen Lee rtwdev->mac.rpwm_seq_num); 994e3ec7017SPing-Ke Shih 995e3ec7017SPing-Ke Shih if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 996e3ec7017SPing-Ke Shih request |= PS_RPWM_ACK; 9977bfd05ffSChin-Yen Lee } 998e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 9997bfd05ffSChin-Yen Lee 10007bfd05ffSChin-Yen Lee spin_unlock_bh(&rtwdev->rpwm_lock); 1001e3ec7017SPing-Ke Shih } 1002e3ec7017SPing-Ke Shih 1003e3ec7017SPing-Ke Shih static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1004e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state req_pwr_state) 1005e3ec7017SPing-Ke Shih { 1006e3ec7017SPing-Ke Shih bool request_deep_mode; 1007e3ec7017SPing-Ke Shih bool in_deep_mode; 1008e3ec7017SPing-Ke Shih u8 rpwm_req_num; 1009e3ec7017SPing-Ke Shih u8 cpwm_rsp_seq; 1010e3ec7017SPing-Ke Shih u8 cpwm_seq; 1011e3ec7017SPing-Ke Shih u8 cpwm_status; 1012e3ec7017SPing-Ke Shih 1013e3ec7017SPing-Ke Shih if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1014e3ec7017SPing-Ke Shih request_deep_mode = true; 1015e3ec7017SPing-Ke Shih else 1016e3ec7017SPing-Ke Shih request_deep_mode = false; 1017e3ec7017SPing-Ke Shih 1018e3ec7017SPing-Ke Shih if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1019e3ec7017SPing-Ke Shih in_deep_mode = true; 1020e3ec7017SPing-Ke Shih else 1021e3ec7017SPing-Ke Shih in_deep_mode = false; 1022e3ec7017SPing-Ke Shih 1023e3ec7017SPing-Ke Shih if (request_deep_mode != in_deep_mode) 1024e3ec7017SPing-Ke Shih return -EPERM; 1025e3ec7017SPing-Ke Shih 1026e3ec7017SPing-Ke Shih if (request_deep_mode) 1027e3ec7017SPing-Ke Shih return 0; 1028e3ec7017SPing-Ke Shih 1029e3ec7017SPing-Ke Shih rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1030e1757e80SPing-Ke Shih cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1031e3ec7017SPing-Ke Shih PS_CPWM_RSP_SEQ_NUM); 1032e3ec7017SPing-Ke Shih 1033e3ec7017SPing-Ke Shih if (rpwm_req_num != cpwm_rsp_seq) 1034e3ec7017SPing-Ke Shih return -EPERM; 1035e3ec7017SPing-Ke Shih 1036e3ec7017SPing-Ke Shih rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1037e3ec7017SPing-Ke Shih CPWM_SEQ_NUM_MAX; 1038e3ec7017SPing-Ke Shih 1039e1757e80SPing-Ke Shih cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1040e3ec7017SPing-Ke Shih if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1041e3ec7017SPing-Ke Shih return -EPERM; 1042e3ec7017SPing-Ke Shih 1043e1757e80SPing-Ke Shih cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1044e3ec7017SPing-Ke Shih if (cpwm_status != req_pwr_state) 1045e3ec7017SPing-Ke Shih return -EPERM; 1046e3ec7017SPing-Ke Shih 1047e3ec7017SPing-Ke Shih return 0; 1048e3ec7017SPing-Ke Shih } 1049e3ec7017SPing-Ke Shih 1050e3ec7017SPing-Ke Shih void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1051e3ec7017SPing-Ke Shih { 1052e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 105339a76521SPing-Ke Shih unsigned long delay = enter ? 10 : 150; 1054e3ec7017SPing-Ke Shih int ret; 1055e3ec7017SPing-Ke Shih 1056e3ec7017SPing-Ke Shih if (enter) 1057e3ec7017SPing-Ke Shih state = rtw89_mac_get_req_pwr_state(rtwdev); 1058e3ec7017SPing-Ke Shih else 1059e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1060e3ec7017SPing-Ke Shih 10617bfd05ffSChin-Yen Lee rtw89_mac_send_rpwm(rtwdev, state, false); 1062e3ec7017SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, !ret, 106339a76521SPing-Ke Shih delay, 15000, false, rtwdev, state); 1064e3ec7017SPing-Ke Shih if (ret) 1065e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1066e3ec7017SPing-Ke Shih enter ? "entering" : "leaving"); 1067e3ec7017SPing-Ke Shih } 1068e3ec7017SPing-Ke Shih 10697bfd05ffSChin-Yen Lee void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 10707bfd05ffSChin-Yen Lee { 10717bfd05ffSChin-Yen Lee enum rtw89_rpwm_req_pwr_state state; 10727bfd05ffSChin-Yen Lee 10737bfd05ffSChin-Yen Lee state = rtw89_mac_get_req_pwr_state(rtwdev); 10747bfd05ffSChin-Yen Lee rtw89_mac_send_rpwm(rtwdev, state, true); 10757bfd05ffSChin-Yen Lee } 10767bfd05ffSChin-Yen Lee 1077e3ec7017SPing-Ke Shih static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1078e3ec7017SPing-Ke Shih { 1079e3ec7017SPing-Ke Shih #define PWR_ACT 1 1080e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1081e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq; 10822a7e54dbSPing-Ke Shih int (*cfg_func)(struct rtw89_dev *rtwdev); 1083e3ec7017SPing-Ke Shih struct rtw89_hal *hal = &rtwdev->hal; 1084e3ec7017SPing-Ke Shih int ret; 1085e3ec7017SPing-Ke Shih u8 val; 1086e3ec7017SPing-Ke Shih 10872a7e54dbSPing-Ke Shih if (on) { 1088e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_on_seq; 10892a7e54dbSPing-Ke Shih cfg_func = chip->ops->pwr_on_func; 10902a7e54dbSPing-Ke Shih } else { 1091e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_off_seq; 10922a7e54dbSPing-Ke Shih cfg_func = chip->ops->pwr_off_func; 10932a7e54dbSPing-Ke Shih } 1094e3ec7017SPing-Ke Shih 1095e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1096e3ec7017SPing-Ke Shih __rtw89_leave_ps_mode(rtwdev); 1097e3ec7017SPing-Ke Shih 1098e3ec7017SPing-Ke Shih val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1099e3ec7017SPing-Ke Shih if (on && val == PWR_ACT) { 1100e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC has already powered on\n"); 1101e3ec7017SPing-Ke Shih return -EBUSY; 1102e3ec7017SPing-Ke Shih } 1103e3ec7017SPing-Ke Shih 11042a7e54dbSPing-Ke Shih ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1105e3ec7017SPing-Ke Shih if (ret) 1106e3ec7017SPing-Ke Shih return ret; 1107e3ec7017SPing-Ke Shih 1108e3ec7017SPing-Ke Shih if (on) { 1109e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1110e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1111e3ec7017SPing-Ke Shih } else { 1112e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1113e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1114e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1115e3ec7017SPing-Ke Shih hal->current_channel = 0; 1116e3ec7017SPing-Ke Shih } 1117e3ec7017SPing-Ke Shih 1118e3ec7017SPing-Ke Shih return 0; 1119e3ec7017SPing-Ke Shih #undef PWR_ACT 1120e3ec7017SPing-Ke Shih } 1121e3ec7017SPing-Ke Shih 1122e3ec7017SPing-Ke Shih void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1123e3ec7017SPing-Ke Shih { 1124e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 1125e3ec7017SPing-Ke Shih } 1126e3ec7017SPing-Ke Shih 1127e3ec7017SPing-Ke Shih static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1128e3ec7017SPing-Ke Shih { 1129e3ec7017SPing-Ke Shih u32 func_en = 0; 1130e3ec7017SPing-Ke Shih u32 ck_en = 0; 1131e3ec7017SPing-Ke Shih u32 c1pc_en = 0; 1132e3ec7017SPing-Ke Shih u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1133e3ec7017SPing-Ke Shih u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1134e3ec7017SPing-Ke Shih 1135e3ec7017SPing-Ke Shih func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1136e3ec7017SPing-Ke Shih B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 11375cb5562dSPing-Ke Shih B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 11385cb5562dSPing-Ke Shih B_AX_CMAC_CRPRT; 1139e3ec7017SPing-Ke Shih ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1140e3ec7017SPing-Ke Shih B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1141e3ec7017SPing-Ke Shih B_AX_RMAC_CKEN; 1142e3ec7017SPing-Ke Shih c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1143e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1144e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1145e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1146e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1147e3ec7017SPing-Ke Shih 1148e3ec7017SPing-Ke Shih if (en) { 1149e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1150e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1151e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1152e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1153e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1154e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1155e3ec7017SPing-Ke Shih } 1156e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1157e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1158e3ec7017SPing-Ke Shih } else { 1159e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1160e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1161e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1162e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1163e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1164e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1165e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1166e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1167e3ec7017SPing-Ke Shih } 1168e3ec7017SPing-Ke Shih } 1169e3ec7017SPing-Ke Shih 1170e3ec7017SPing-Ke Shih return 0; 1171e3ec7017SPing-Ke Shih } 1172e3ec7017SPing-Ke Shih 1173e3ec7017SPing-Ke Shih static int dmac_func_en(struct rtw89_dev *rtwdev) 1174e3ec7017SPing-Ke Shih { 1175828a4396SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1176e3ec7017SPing-Ke Shih u32 val32; 1177e3ec7017SPing-Ke Shih 1178828a4396SChia-Yuan Li if (chip_id == RTL8852C) 1179828a4396SChia-Yuan Li val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1180828a4396SChia-Yuan Li B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1181828a4396SChia-Yuan Li B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1182828a4396SChia-Yuan Li B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1183828a4396SChia-Yuan Li B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1184828a4396SChia-Yuan Li B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1185828a4396SChia-Yuan Li B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1186828a4396SChia-Yuan Li else 1187828a4396SChia-Yuan Li val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1188828a4396SChia-Yuan Li B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1189828a4396SChia-Yuan Li B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1190828a4396SChia-Yuan Li B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1191828a4396SChia-Yuan Li B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1192828a4396SChia-Yuan Li B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1193828a4396SChia-Yuan Li B_AX_DMAC_CRPRT); 1194e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1195e3ec7017SPing-Ke Shih 1196e3ec7017SPing-Ke Shih val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1197e3ec7017SPing-Ke Shih B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1198e3ec7017SPing-Ke Shih B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1199828a4396SChia-Yuan Li B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1200e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1201e3ec7017SPing-Ke Shih 120243863efeSChangcheng Deng return 0; 1203e3ec7017SPing-Ke Shih } 1204e3ec7017SPing-Ke Shih 1205e3ec7017SPing-Ke Shih static int chip_func_en(struct rtw89_dev *rtwdev) 1206e3ec7017SPing-Ke Shih { 1207828a4396SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1208828a4396SChia-Yuan Li 1209828a4396SChia-Yuan Li if (chip_id == RTL8852A) 1210828a4396SChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL0, 1211828a4396SChia-Yuan Li B_AX_OCP_L1_MASK); 1212e3ec7017SPing-Ke Shih 1213e3ec7017SPing-Ke Shih return 0; 1214e3ec7017SPing-Ke Shih } 1215e3ec7017SPing-Ke Shih 1216e3ec7017SPing-Ke Shih static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1217e3ec7017SPing-Ke Shih { 1218e3ec7017SPing-Ke Shih int ret; 1219e3ec7017SPing-Ke Shih 1220e3ec7017SPing-Ke Shih ret = dmac_func_en(rtwdev); 1221e3ec7017SPing-Ke Shih if (ret) 1222e3ec7017SPing-Ke Shih return ret; 1223e3ec7017SPing-Ke Shih 1224e3ec7017SPing-Ke Shih ret = cmac_func_en(rtwdev, 0, true); 1225e3ec7017SPing-Ke Shih if (ret) 1226e3ec7017SPing-Ke Shih return ret; 1227e3ec7017SPing-Ke Shih 1228e3ec7017SPing-Ke Shih ret = chip_func_en(rtwdev); 1229e3ec7017SPing-Ke Shih if (ret) 1230e3ec7017SPing-Ke Shih return ret; 1231e3ec7017SPing-Ke Shih 1232e3ec7017SPing-Ke Shih return ret; 1233e3ec7017SPing-Ke Shih } 1234e3ec7017SPing-Ke Shih 123530645118SPing-Ke Shih const struct rtw89_mac_size_set rtw89_mac_size = { 123630645118SPing-Ke Shih .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1237e3ec7017SPing-Ke Shih /* PCIE 64 */ 123830645118SPing-Ke Shih .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1239e3ec7017SPing-Ke Shih /* DLFW */ 124030645118SPing-Ke Shih .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 124179d099e0SPing-Ke Shih /* 8852C DLFW */ 124230645118SPing-Ke Shih .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 124379d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 124430645118SPing-Ke Shih .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1245e3ec7017SPing-Ke Shih /* PCIE */ 124630645118SPing-Ke Shih .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1247e3ec7017SPing-Ke Shih /* DLFW */ 124830645118SPing-Ke Shih .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 124979d099e0SPing-Ke Shih /* 8852C DLFW */ 125030645118SPing-Ke Shih .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 125179d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 125230645118SPing-Ke Shih .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1253e3ec7017SPing-Ke Shih /* PCIE 64 */ 125430645118SPing-Ke Shih .wde_qt0 = {3792, 196, 0, 107,}, 1255e3ec7017SPing-Ke Shih /* DLFW */ 125630645118SPing-Ke Shih .wde_qt4 = {0, 0, 0, 0,}, 125779d099e0SPing-Ke Shih /* 8852C DLFW */ 125830645118SPing-Ke Shih .wde_qt17 = {0, 0, 0, 0,}, 125979d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 126030645118SPing-Ke Shih .wde_qt18 = {3228, 60, 0, 40,}, 1261e3ec7017SPing-Ke Shih /* PCIE SCC */ 126230645118SPing-Ke Shih .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1263e3ec7017SPing-Ke Shih /* PCIE SCC */ 126430645118SPing-Ke Shih .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1265e3ec7017SPing-Ke Shih /* DLFW */ 126630645118SPing-Ke Shih .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 126779d099e0SPing-Ke Shih /* DLFW 52C */ 126830645118SPing-Ke Shih .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 126979d099e0SPing-Ke Shih /* DLFW 52C */ 127030645118SPing-Ke Shih .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 127179d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 127230645118SPing-Ke Shih .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 127379d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 127430645118SPing-Ke Shih .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 127579d099e0SPing-Ke Shih }; 127630645118SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_size); 127779d099e0SPing-Ke Shih 1278e3ec7017SPing-Ke Shih static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1279e3ec7017SPing-Ke Shih enum rtw89_qta_mode mode) 1280e3ec7017SPing-Ke Shih { 1281e3ec7017SPing-Ke Shih struct rtw89_mac_info *mac = &rtwdev->mac; 1282e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 1283e3ec7017SPing-Ke Shih 1284e3ec7017SPing-Ke Shih cfg = &rtwdev->chip->dle_mem[mode]; 1285e3ec7017SPing-Ke Shih if (!cfg) 1286e3ec7017SPing-Ke Shih return NULL; 1287e3ec7017SPing-Ke Shih 1288e3ec7017SPing-Ke Shih if (cfg->mode != mode) { 1289e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1290e3ec7017SPing-Ke Shih return NULL; 1291e3ec7017SPing-Ke Shih } 1292e3ec7017SPing-Ke Shih 1293e3ec7017SPing-Ke Shih mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; 1294e3ec7017SPing-Ke Shih mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1295e3ec7017SPing-Ke Shih mac->dle_info.qta_mode = mode; 1296e3ec7017SPing-Ke Shih mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1297e3ec7017SPing-Ke Shih mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1298e3ec7017SPing-Ke Shih 1299e3ec7017SPing-Ke Shih return cfg; 1300e3ec7017SPing-Ke Shih } 1301e3ec7017SPing-Ke Shih 1302e3ec7017SPing-Ke Shih static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1303e3ec7017SPing-Ke Shih const struct rtw89_dle_size *ple) 1304e3ec7017SPing-Ke Shih { 1305e3ec7017SPing-Ke Shih return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1306e3ec7017SPing-Ke Shih ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1307e3ec7017SPing-Ke Shih } 1308e3ec7017SPing-Ke Shih 1309e3ec7017SPing-Ke Shih static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1310e3ec7017SPing-Ke Shih { 1311e3ec7017SPing-Ke Shih if (enable) 1312e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1313e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1314e3ec7017SPing-Ke Shih else 1315e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1316e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1317e3ec7017SPing-Ke Shih } 1318e3ec7017SPing-Ke Shih 1319e3ec7017SPing-Ke Shih static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1320e3ec7017SPing-Ke Shih { 1321e3ec7017SPing-Ke Shih if (enable) 1322e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, 1323e3ec7017SPing-Ke Shih B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1324e3ec7017SPing-Ke Shih else 1325e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, 1326e3ec7017SPing-Ke Shih B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1327e3ec7017SPing-Ke Shih } 1328e3ec7017SPing-Ke Shih 1329e3ec7017SPing-Ke Shih static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1330e3ec7017SPing-Ke Shih { 1331e3ec7017SPing-Ke Shih const struct rtw89_dle_size *size_cfg; 1332e3ec7017SPing-Ke Shih u32 val; 1333e3ec7017SPing-Ke Shih u8 bound = 0; 1334e3ec7017SPing-Ke Shih 1335e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1336e3ec7017SPing-Ke Shih size_cfg = cfg->wde_size; 1337e3ec7017SPing-Ke Shih 1338e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1339e3ec7017SPing-Ke Shih default: 1340e3ec7017SPing-Ke Shih case RTW89_WDE_PG_64: 1341e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1342e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1343e3ec7017SPing-Ke Shih break; 1344e3ec7017SPing-Ke Shih case RTW89_WDE_PG_128: 1345e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1346e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1347e3ec7017SPing-Ke Shih break; 1348e3ec7017SPing-Ke Shih case RTW89_WDE_PG_256: 1349e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1350e3ec7017SPing-Ke Shih return -EINVAL; 1351e3ec7017SPing-Ke Shih } 1352e3ec7017SPing-Ke Shih 1353e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1354e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1355e3ec7017SPing-Ke Shih B_AX_WDE_FREE_PAGE_NUM_MASK); 1356e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1357e3ec7017SPing-Ke Shih 1358e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1359e3ec7017SPing-Ke Shih bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1360e3ec7017SPing-Ke Shih * size_cfg->pge_size / DLE_BOUND_UNIT; 1361e3ec7017SPing-Ke Shih size_cfg = cfg->ple_size; 1362e3ec7017SPing-Ke Shih 1363e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1364e3ec7017SPing-Ke Shih default: 1365e3ec7017SPing-Ke Shih case RTW89_PLE_PG_64: 1366e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1367e3ec7017SPing-Ke Shih return -EINVAL; 1368e3ec7017SPing-Ke Shih case RTW89_PLE_PG_128: 1369e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1370e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1371e3ec7017SPing-Ke Shih break; 1372e3ec7017SPing-Ke Shih case RTW89_PLE_PG_256: 1373e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1374e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1375e3ec7017SPing-Ke Shih break; 1376e3ec7017SPing-Ke Shih } 1377e3ec7017SPing-Ke Shih 1378e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1379e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1380e3ec7017SPing-Ke Shih B_AX_PLE_FREE_PAGE_NUM_MASK); 1381e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1382e3ec7017SPing-Ke Shih 1383e3ec7017SPing-Ke Shih return 0; 1384e3ec7017SPing-Ke Shih } 1385e3ec7017SPing-Ke Shih 1386e3ec7017SPing-Ke Shih #define INVALID_QT_WCPU U16_MAX 1387e3ec7017SPing-Ke Shih #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1388e3ec7017SPing-Ke Shih do { \ 1389e3ec7017SPing-Ke Shih val = ((_min_x) & \ 1390e3ec7017SPing-Ke Shih B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1391e3ec7017SPing-Ke Shih (((_max_x) << 16) & \ 1392e3ec7017SPing-Ke Shih B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1393e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, \ 1394e3ec7017SPing-Ke Shih R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1395e3ec7017SPing-Ke Shih val); \ 1396e3ec7017SPing-Ke Shih } while (0) 1397e3ec7017SPing-Ke Shih #define SET_QUOTA(_x, _module, _idx) \ 1398e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1399e3ec7017SPing-Ke Shih 1400e3ec7017SPing-Ke Shih static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1401e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *min_cfg, 1402e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *max_cfg, 1403e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 1404e3ec7017SPing-Ke Shih { 1405e3ec7017SPing-Ke Shih u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1406e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu : min_cfg->wcpu; 1407e3ec7017SPing-Ke Shih u32 val; 1408e3ec7017SPing-Ke Shih 1409e3ec7017SPing-Ke Shih SET_QUOTA(hif, WDE, 0); 1410e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1411e3ec7017SPing-Ke Shih SET_QUOTA(pkt_in, WDE, 3); 1412e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, WDE, 4); 1413e3ec7017SPing-Ke Shih } 1414e3ec7017SPing-Ke Shih 1415e3ec7017SPing-Ke Shih static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1416e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *min_cfg, 1417e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *max_cfg) 1418e3ec7017SPing-Ke Shih { 1419e3ec7017SPing-Ke Shih u32 val; 1420e3ec7017SPing-Ke Shih 1421e3ec7017SPing-Ke Shih SET_QUOTA(cma0_tx, PLE, 0); 1422e3ec7017SPing-Ke Shih SET_QUOTA(cma1_tx, PLE, 1); 1423e3ec7017SPing-Ke Shih SET_QUOTA(c2h, PLE, 2); 1424e3ec7017SPing-Ke Shih SET_QUOTA(h2c, PLE, 3); 1425e3ec7017SPing-Ke Shih SET_QUOTA(wcpu, PLE, 4); 1426e3ec7017SPing-Ke Shih SET_QUOTA(mpdu_proc, PLE, 5); 1427e3ec7017SPing-Ke Shih SET_QUOTA(cma0_dma, PLE, 6); 1428e3ec7017SPing-Ke Shih SET_QUOTA(cma1_dma, PLE, 7); 1429e3ec7017SPing-Ke Shih SET_QUOTA(bb_rpt, PLE, 8); 1430e3ec7017SPing-Ke Shih SET_QUOTA(wd_rel, PLE, 9); 1431e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, PLE, 10); 143279d099e0SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852C) 143379d099e0SPing-Ke Shih SET_QUOTA(tx_rpt, PLE, 11); 1434e3ec7017SPing-Ke Shih } 1435e3ec7017SPing-Ke Shih 1436e3ec7017SPing-Ke Shih #undef SET_QUOTA 1437e3ec7017SPing-Ke Shih 1438e3ec7017SPing-Ke Shih static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1439e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, 1440e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 1441e3ec7017SPing-Ke Shih { 1442e3ec7017SPing-Ke Shih wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1443e3ec7017SPing-Ke Shih ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1444e3ec7017SPing-Ke Shih } 1445e3ec7017SPing-Ke Shih 1446e3ec7017SPing-Ke Shih static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1447e3ec7017SPing-Ke Shih enum rtw89_qta_mode ext_mode) 1448e3ec7017SPing-Ke Shih { 1449e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, *ext_cfg; 1450e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1451e3ec7017SPing-Ke Shih int ret = 0; 1452e3ec7017SPing-Ke Shih u32 ini; 1453e3ec7017SPing-Ke Shih 1454e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1455e3ec7017SPing-Ke Shih if (ret) 1456e3ec7017SPing-Ke Shih return ret; 1457e3ec7017SPing-Ke Shih 1458e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 1459e3ec7017SPing-Ke Shih if (!cfg) { 1460e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1461e3ec7017SPing-Ke Shih ret = -EINVAL; 1462e3ec7017SPing-Ke Shih goto error; 1463e3ec7017SPing-Ke Shih } 1464e3ec7017SPing-Ke Shih 1465e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_DLFW) { 1466e3ec7017SPing-Ke Shih ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1467e3ec7017SPing-Ke Shih if (!ext_cfg) { 1468e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1469e3ec7017SPing-Ke Shih ext_mode); 1470e3ec7017SPing-Ke Shih ret = -EINVAL; 1471e3ec7017SPing-Ke Shih goto error; 1472e3ec7017SPing-Ke Shih } 1473e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1474e3ec7017SPing-Ke Shih } 1475e3ec7017SPing-Ke Shih 1476e3ec7017SPing-Ke Shih if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { 1477e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1478e3ec7017SPing-Ke Shih ret = -EINVAL; 1479e3ec7017SPing-Ke Shih goto error; 1480e3ec7017SPing-Ke Shih } 1481e3ec7017SPing-Ke Shih 1482e3ec7017SPing-Ke Shih dle_func_en(rtwdev, false); 1483e3ec7017SPing-Ke Shih dle_clk_en(rtwdev, true); 1484e3ec7017SPing-Ke Shih 1485e3ec7017SPing-Ke Shih ret = dle_mix_cfg(rtwdev, cfg); 1486e3ec7017SPing-Ke Shih if (ret) { 1487e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1488e3ec7017SPing-Ke Shih goto error; 1489e3ec7017SPing-Ke Shih } 1490e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1491e3ec7017SPing-Ke Shih 1492e3ec7017SPing-Ke Shih dle_func_en(rtwdev, true); 1493e3ec7017SPing-Ke Shih 1494e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, ini, 1495e3ec7017SPing-Ke Shih (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1496e3ec7017SPing-Ke Shih 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1497e3ec7017SPing-Ke Shih if (ret) { 1498e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1499e3ec7017SPing-Ke Shih return ret; 1500e3ec7017SPing-Ke Shih } 1501e3ec7017SPing-Ke Shih 1502e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, ini, 1503e3ec7017SPing-Ke Shih (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1504e3ec7017SPing-Ke Shih 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1505e3ec7017SPing-Ke Shih if (ret) { 1506e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1507e3ec7017SPing-Ke Shih return ret; 1508e3ec7017SPing-Ke Shih } 1509e3ec7017SPing-Ke Shih 1510e3ec7017SPing-Ke Shih return 0; 1511e3ec7017SPing-Ke Shih error: 1512e3ec7017SPing-Ke Shih dle_func_en(rtwdev, false); 1513e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1514e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1515e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1516e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1517e3ec7017SPing-Ke Shih 1518e3ec7017SPing-Ke Shih return ret; 1519e3ec7017SPing-Ke Shih } 1520e3ec7017SPing-Ke Shih 1521e07a9968SPing-Ke Shih static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1522e07a9968SPing-Ke Shih enum rtw89_qta_mode mode) 1523e07a9968SPing-Ke Shih { 1524e07a9968SPing-Ke Shih u32 reg, max_preld_size, min_rsvd_size; 1525e07a9968SPing-Ke Shih 1526e07a9968SPing-Ke Shih max_preld_size = (mac_idx == RTW89_MAC_0 ? 1527e07a9968SPing-Ke Shih PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1528e07a9968SPing-Ke Shih reg = mac_idx == RTW89_MAC_0 ? 1529e07a9968SPing-Ke Shih R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1530e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1531e07a9968SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1532e07a9968SPing-Ke Shih 1533e07a9968SPing-Ke Shih min_rsvd_size = PRELD_AMSDU_SIZE; 1534e07a9968SPing-Ke Shih reg = mac_idx == RTW89_MAC_0 ? 1535e07a9968SPing-Ke Shih R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1536e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1537e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1538e07a9968SPing-Ke Shih 1539e07a9968SPing-Ke Shih return 0; 1540e07a9968SPing-Ke Shih } 1541e07a9968SPing-Ke Shih 1542e07a9968SPing-Ke Shih static bool is_qta_poh(struct rtw89_dev *rtwdev) 1543e07a9968SPing-Ke Shih { 1544e07a9968SPing-Ke Shih return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1545e07a9968SPing-Ke Shih } 1546e07a9968SPing-Ke Shih 1547e07a9968SPing-Ke Shih static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1548e07a9968SPing-Ke Shih enum rtw89_qta_mode mode) 1549e07a9968SPing-Ke Shih { 1550e07a9968SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1551e07a9968SPing-Ke Shih 1552e07a9968SPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || !is_qta_poh(rtwdev)) 1553e07a9968SPing-Ke Shih return 0; 1554e07a9968SPing-Ke Shih 1555e07a9968SPing-Ke Shih return preload_init_set(rtwdev, mac_idx, mode); 1556e07a9968SPing-Ke Shih } 1557e07a9968SPing-Ke Shih 1558e3ec7017SPing-Ke Shih static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1559e3ec7017SPing-Ke Shih { 1560e3ec7017SPing-Ke Shih u32 msk32; 1561e3ec7017SPing-Ke Shih u32 val32; 1562e3ec7017SPing-Ke Shih 1563e3ec7017SPing-Ke Shih msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1564e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1565e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1566e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1567e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1568e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1569e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1570e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1571e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1572e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1573e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1574e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1575e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1576e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1577e3ec7017SPing-Ke Shih 1578e3ec7017SPing-Ke Shih if ((val32 & msk32) == msk32) 1579e3ec7017SPing-Ke Shih return true; 1580e3ec7017SPing-Ke Shih 1581e3ec7017SPing-Ke Shih return false; 1582e3ec7017SPing-Ke Shih } 1583e3ec7017SPing-Ke Shih 1584cf7b8b80SPing-Ke Shih static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 1585cf7b8b80SPing-Ke Shih { 1586cf7b8b80SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1587cf7b8b80SPing-Ke Shih 1588cf7b8b80SPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 1589cf7b8b80SPing-Ke Shih return; 1590cf7b8b80SPing-Ke Shih 1591cf7b8b80SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 1592cf7b8b80SPing-Ke Shih SS2F_PATH_WLCPU); 1593cf7b8b80SPing-Ke Shih } 1594cf7b8b80SPing-Ke Shih 1595e3ec7017SPing-Ke Shih static int sta_sch_init(struct rtw89_dev *rtwdev) 1596e3ec7017SPing-Ke Shih { 1597e3ec7017SPing-Ke Shih u32 p_val; 1598e3ec7017SPing-Ke Shih u8 val; 1599e3ec7017SPing-Ke Shih int ret; 1600e3ec7017SPing-Ke Shih 1601e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1602e3ec7017SPing-Ke Shih if (ret) 1603e3ec7017SPing-Ke Shih return ret; 1604e3ec7017SPing-Ke Shih 1605e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1606e3ec7017SPing-Ke Shih val |= B_AX_SS_EN; 1607e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1608e3ec7017SPing-Ke Shih 1609e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1610e3ec7017SPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1611e3ec7017SPing-Ke Shih if (ret) { 1612e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1613e3ec7017SPing-Ke Shih return ret; 1614e3ec7017SPing-Ke Shih } 1615e3ec7017SPing-Ke Shih 16169a1ab283SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 16179a1ab283SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 1618cf7b8b80SPing-Ke Shih 1619cf7b8b80SPing-Ke Shih _patch_ss2f_path(rtwdev); 1620e3ec7017SPing-Ke Shih 1621e3ec7017SPing-Ke Shih return 0; 1622e3ec7017SPing-Ke Shih } 1623e3ec7017SPing-Ke Shih 1624e3ec7017SPing-Ke Shih static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1625e3ec7017SPing-Ke Shih { 1626e3ec7017SPing-Ke Shih int ret; 1627e3ec7017SPing-Ke Shih 1628e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1629e3ec7017SPing-Ke Shih if (ret) 1630e3ec7017SPing-Ke Shih return ret; 1631e3ec7017SPing-Ke Shih 1632e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1633e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1634e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1635e3ec7017SPing-Ke Shih B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1636e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1637e3ec7017SPing-Ke Shih 1638e3ec7017SPing-Ke Shih return 0; 1639e3ec7017SPing-Ke Shih } 1640e3ec7017SPing-Ke Shih 1641e3ec7017SPing-Ke Shih static int sec_eng_init(struct rtw89_dev *rtwdev) 1642e3ec7017SPing-Ke Shih { 1643b61adeedSPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1644e3ec7017SPing-Ke Shih u32 val = 0; 1645e3ec7017SPing-Ke Shih int ret; 1646e3ec7017SPing-Ke Shih 1647e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1648e3ec7017SPing-Ke Shih if (ret) 1649e3ec7017SPing-Ke Shih return ret; 1650e3ec7017SPing-Ke Shih 1651e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 1652e3ec7017SPing-Ke Shih /* init clock */ 1653e3ec7017SPing-Ke Shih val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 1654e3ec7017SPing-Ke Shih /* init TX encryption */ 1655e3ec7017SPing-Ke Shih val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 1656e3ec7017SPing-Ke Shih val |= (B_AX_MC_DEC | B_AX_BC_DEC); 1657b61adeedSPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 1658e3ec7017SPing-Ke Shih val &= ~B_AX_TX_PARTIAL_MODE; 1659e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 1660e3ec7017SPing-Ke Shih 1661e3ec7017SPing-Ke Shih /* init MIC ICV append */ 1662e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 1663e3ec7017SPing-Ke Shih val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 1664e3ec7017SPing-Ke Shih 1665e3ec7017SPing-Ke Shih /* option init */ 1666e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 1667e3ec7017SPing-Ke Shih 1668b61adeedSPing-Ke Shih if (chip->chip_id == RTL8852C) 1669b61adeedSPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 1670b61adeedSPing-Ke Shih B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 1671b61adeedSPing-Ke Shih 1672e3ec7017SPing-Ke Shih return 0; 1673e3ec7017SPing-Ke Shih } 1674e3ec7017SPing-Ke Shih 1675e3ec7017SPing-Ke Shih static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1676e3ec7017SPing-Ke Shih { 1677e3ec7017SPing-Ke Shih int ret; 1678e3ec7017SPing-Ke Shih 1679e3ec7017SPing-Ke Shih ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 1680e3ec7017SPing-Ke Shih if (ret) { 1681e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 1682e3ec7017SPing-Ke Shih return ret; 1683e3ec7017SPing-Ke Shih } 1684e3ec7017SPing-Ke Shih 1685e07a9968SPing-Ke Shih ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 1686e07a9968SPing-Ke Shih if (ret) { 1687e07a9968SPing-Ke Shih rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 1688e07a9968SPing-Ke Shih return ret; 1689e07a9968SPing-Ke Shih } 1690e07a9968SPing-Ke Shih 1691e3ec7017SPing-Ke Shih ret = hfc_init(rtwdev, true, true, true); 1692e3ec7017SPing-Ke Shih if (ret) { 1693e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 1694e3ec7017SPing-Ke Shih return ret; 1695e3ec7017SPing-Ke Shih } 1696e3ec7017SPing-Ke Shih 1697e3ec7017SPing-Ke Shih ret = sta_sch_init(rtwdev); 1698e3ec7017SPing-Ke Shih if (ret) { 1699e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 1700e3ec7017SPing-Ke Shih return ret; 1701e3ec7017SPing-Ke Shih } 1702e3ec7017SPing-Ke Shih 1703e3ec7017SPing-Ke Shih ret = mpdu_proc_init(rtwdev); 1704e3ec7017SPing-Ke Shih if (ret) { 1705e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 1706e3ec7017SPing-Ke Shih return ret; 1707e3ec7017SPing-Ke Shih } 1708e3ec7017SPing-Ke Shih 1709e3ec7017SPing-Ke Shih ret = sec_eng_init(rtwdev); 1710e3ec7017SPing-Ke Shih if (ret) { 1711e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 1712e3ec7017SPing-Ke Shih return ret; 1713e3ec7017SPing-Ke Shih } 1714e3ec7017SPing-Ke Shih 1715e3ec7017SPing-Ke Shih return ret; 1716e3ec7017SPing-Ke Shih } 1717e3ec7017SPing-Ke Shih 1718e3ec7017SPing-Ke Shih static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1719e3ec7017SPing-Ke Shih { 1720e3ec7017SPing-Ke Shih u32 val, reg; 1721e3ec7017SPing-Ke Shih u16 p_val; 1722e3ec7017SPing-Ke Shih int ret; 1723e3ec7017SPing-Ke Shih 1724e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1725e3ec7017SPing-Ke Shih if (ret) 1726e3ec7017SPing-Ke Shih return ret; 1727e3ec7017SPing-Ke Shih 1728e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); 1729e3ec7017SPing-Ke Shih 1730e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1731e3ec7017SPing-Ke Shih val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 1732e3ec7017SPing-Ke Shih B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 1733e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1734e3ec7017SPing-Ke Shih 1735e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 1736e3ec7017SPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, B_AX_ADDR_CAM_CLR); 1737e3ec7017SPing-Ke Shih if (ret) { 1738e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 1739e3ec7017SPing-Ke Shih return ret; 1740e3ec7017SPing-Ke Shih } 1741e3ec7017SPing-Ke Shih 1742e3ec7017SPing-Ke Shih return 0; 1743e3ec7017SPing-Ke Shih } 1744e3ec7017SPing-Ke Shih 1745e3ec7017SPing-Ke Shih static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1746e3ec7017SPing-Ke Shih { 1747e3ec7017SPing-Ke Shih u32 ret; 1748e3ec7017SPing-Ke Shih u32 reg; 1749e3ec7017SPing-Ke Shih 1750e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1751e3ec7017SPing-Ke Shih if (ret) 1752e3ec7017SPing-Ke Shih return ret; 1753e3ec7017SPing-Ke Shih 1754c49154ffSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx); 1755c49154ffSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, SIFS_MACTXEN_T1); 1756c49154ffSPing-Ke Shih 1757c49154ffSPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852B) { 1758c49154ffSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx); 1759c49154ffSPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 1760c49154ffSPing-Ke Shih } 1761c49154ffSPing-Ke Shih 1762c49154ffSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx); 1763c49154ffSPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 1764c49154ffSPing-Ke Shih 1765e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); 1766e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, SCH_PREBKF_24US); 1767e3ec7017SPing-Ke Shih 1768e3ec7017SPing-Ke Shih return 0; 1769e3ec7017SPing-Ke Shih } 1770e3ec7017SPing-Ke Shih 1771e3ec7017SPing-Ke Shih static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 1772e3ec7017SPing-Ke Shih enum rtw89_machdr_frame_type type, 1773e3ec7017SPing-Ke Shih enum rtw89_mac_fwd_target fwd_target, 1774e3ec7017SPing-Ke Shih u8 mac_idx) 1775e3ec7017SPing-Ke Shih { 1776e3ec7017SPing-Ke Shih u32 reg; 1777e3ec7017SPing-Ke Shih u32 val; 1778e3ec7017SPing-Ke Shih 1779e3ec7017SPing-Ke Shih switch (fwd_target) { 1780e3ec7017SPing-Ke Shih case RTW89_FWD_DONT_CARE: 1781e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_DROP; 1782e3ec7017SPing-Ke Shih break; 1783e3ec7017SPing-Ke Shih case RTW89_FWD_TO_HOST: 1784e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_HOST; 1785e3ec7017SPing-Ke Shih break; 1786e3ec7017SPing-Ke Shih case RTW89_FWD_TO_WLAN_CPU: 1787e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_WLCPU; 1788e3ec7017SPing-Ke Shih break; 1789e3ec7017SPing-Ke Shih default: 1790e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 1791e3ec7017SPing-Ke Shih return -EINVAL; 1792e3ec7017SPing-Ke Shih } 1793e3ec7017SPing-Ke Shih 1794e3ec7017SPing-Ke Shih switch (type) { 1795e3ec7017SPing-Ke Shih case RTW89_MGNT: 1796e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); 1797e3ec7017SPing-Ke Shih break; 1798e3ec7017SPing-Ke Shih case RTW89_CTRL: 1799e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); 1800e3ec7017SPing-Ke Shih break; 1801e3ec7017SPing-Ke Shih case RTW89_DATA: 1802e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); 1803e3ec7017SPing-Ke Shih break; 1804e3ec7017SPing-Ke Shih default: 1805e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 1806e3ec7017SPing-Ke Shih return -EINVAL; 1807e3ec7017SPing-Ke Shih } 1808e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1809e3ec7017SPing-Ke Shih 1810e3ec7017SPing-Ke Shih return 0; 1811e3ec7017SPing-Ke Shih } 1812e3ec7017SPing-Ke Shih 1813e3ec7017SPing-Ke Shih static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1814e3ec7017SPing-Ke Shih { 1815e3ec7017SPing-Ke Shih int ret, i; 1816e3ec7017SPing-Ke Shih u32 mac_ftlr, plcp_ftlr; 1817e3ec7017SPing-Ke Shih 1818e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1819e3ec7017SPing-Ke Shih if (ret) 1820e3ec7017SPing-Ke Shih return ret; 1821e3ec7017SPing-Ke Shih 1822e3ec7017SPing-Ke Shih for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 1823e3ec7017SPing-Ke Shih ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 1824e3ec7017SPing-Ke Shih mac_idx); 1825e3ec7017SPing-Ke Shih if (ret) 1826e3ec7017SPing-Ke Shih return ret; 1827e3ec7017SPing-Ke Shih } 1828e3ec7017SPing-Ke Shih mac_ftlr = rtwdev->hal.rx_fltr; 1829e3ec7017SPing-Ke Shih plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 1830e3ec7017SPing-Ke Shih B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 1831e3ec7017SPing-Ke Shih B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 1832e3ec7017SPing-Ke Shih B_AX_HE_SIGB_CRC_CHK; 1833e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), 1834e3ec7017SPing-Ke Shih mac_ftlr); 1835e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), 1836e3ec7017SPing-Ke Shih plcp_ftlr); 1837e3ec7017SPing-Ke Shih 1838e3ec7017SPing-Ke Shih return 0; 1839e3ec7017SPing-Ke Shih } 1840e3ec7017SPing-Ke Shih 1841e3ec7017SPing-Ke Shih static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 1842e3ec7017SPing-Ke Shih { 1843e3ec7017SPing-Ke Shih u32 reg, val32; 1844e3ec7017SPing-Ke Shih u32 b_rsp_chk_nav, b_rsp_chk_cca; 1845e3ec7017SPing-Ke Shih 1846e3ec7017SPing-Ke Shih b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 1847e3ec7017SPing-Ke Shih B_AX_RSP_CHK_BASIC_NAV; 1848e3ec7017SPing-Ke Shih b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 1849e3ec7017SPing-Ke Shih B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 1850e3ec7017SPing-Ke Shih B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 1851e3ec7017SPing-Ke Shih 1852e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 1853e3ec7017SPing-Ke Shih case RTL8852A: 1854e3ec7017SPing-Ke Shih case RTL8852B: 1855e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 1856e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 1857e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 1858e3ec7017SPing-Ke Shih 1859e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1860e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 1861e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 1862e3ec7017SPing-Ke Shih break; 1863e3ec7017SPing-Ke Shih default: 1864e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 1865e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 1866e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 1867e3ec7017SPing-Ke Shih 1868e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1869e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 1870e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 1871e3ec7017SPing-Ke Shih break; 1872e3ec7017SPing-Ke Shih } 1873e3ec7017SPing-Ke Shih } 1874e3ec7017SPing-Ke Shih 1875e3ec7017SPing-Ke Shih static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1876e3ec7017SPing-Ke Shih { 1877e3ec7017SPing-Ke Shih u32 val, reg; 1878e3ec7017SPing-Ke Shih int ret; 1879e3ec7017SPing-Ke Shih 1880e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1881e3ec7017SPing-Ke Shih if (ret) 1882e3ec7017SPing-Ke Shih return ret; 1883e3ec7017SPing-Ke Shih 1884e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); 1885e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1886e3ec7017SPing-Ke Shih val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 1887e3ec7017SPing-Ke Shih B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 1888e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 1889e3ec7017SPing-Ke Shih B_AX_CTN_CHK_INTRA_NAV | 1890e3ec7017SPing-Ke Shih B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 1891e3ec7017SPing-Ke Shih B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 1892e3ec7017SPing-Ke Shih B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 1893e3ec7017SPing-Ke Shih B_AX_CTN_CHK_CCA_P20 | B_AX_SIFS_CHK_EDCCA); 1894e3ec7017SPing-Ke Shih val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 1895e3ec7017SPing-Ke Shih B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 1896e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 1897e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV); 1898e3ec7017SPing-Ke Shih 1899e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1900e3ec7017SPing-Ke Shih 1901e3ec7017SPing-Ke Shih _patch_dis_resp_chk(rtwdev, mac_idx); 1902e3ec7017SPing-Ke Shih 1903e3ec7017SPing-Ke Shih return 0; 1904e3ec7017SPing-Ke Shih } 1905e3ec7017SPing-Ke Shih 190619cb9427SPing-Ke Shih static int nav_ctrl_init(struct rtw89_dev *rtwdev) 190719cb9427SPing-Ke Shih { 190819cb9427SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 190919cb9427SPing-Ke Shih B_AX_WMAC_TF_UP_NAV_EN | 191019cb9427SPing-Ke Shih B_AX_WMAC_NAV_UPPER_EN); 191119cb9427SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_12MS); 191219cb9427SPing-Ke Shih 191319cb9427SPing-Ke Shih return 0; 191419cb9427SPing-Ke Shih } 191519cb9427SPing-Ke Shih 1916e3ec7017SPing-Ke Shih static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1917e3ec7017SPing-Ke Shih { 1918e3ec7017SPing-Ke Shih u32 reg; 1919e3ec7017SPing-Ke Shih int ret; 1920e3ec7017SPing-Ke Shih 1921e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1922e3ec7017SPing-Ke Shih if (ret) 1923e3ec7017SPing-Ke Shih return ret; 1924e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); 1925e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 1926e3ec7017SPing-Ke Shih 1927e3ec7017SPing-Ke Shih return 0; 1928e3ec7017SPing-Ke Shih } 1929e3ec7017SPing-Ke Shih 1930e3ec7017SPing-Ke Shih static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1931e3ec7017SPing-Ke Shih { 1932e3ec7017SPing-Ke Shih u32 reg; 1933e3ec7017SPing-Ke Shih int ret; 1934e3ec7017SPing-Ke Shih 1935e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1936e3ec7017SPing-Ke Shih if (ret) 1937e3ec7017SPing-Ke Shih return ret; 1938e3ec7017SPing-Ke Shih 1939e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); 1940e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 1941e3ec7017SPing-Ke Shih 194275fd91aaSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx); 194375fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 194475fd91aaSPing-Ke Shih 194575fd91aaSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx); 194675fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 194775fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 194875fd91aaSPing-Ke Shih 1949e3ec7017SPing-Ke Shih return 0; 1950e3ec7017SPing-Ke Shih } 1951e3ec7017SPing-Ke Shih 1952e3ec7017SPing-Ke Shih static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1953e3ec7017SPing-Ke Shih { 1954e3ec7017SPing-Ke Shih u32 reg, val, sifs; 1955e3ec7017SPing-Ke Shih int ret; 1956e3ec7017SPing-Ke Shih 1957e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1958e3ec7017SPing-Ke Shih if (ret) 1959e3ec7017SPing-Ke Shih return ret; 1960e3ec7017SPing-Ke Shih 1961e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1962e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1963e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 1964e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 1965e3ec7017SPing-Ke Shih 1966e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 1967e3ec7017SPing-Ke Shih case RTL8852A: 1968e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52A; 1969e3ec7017SPing-Ke Shih break; 1970e3ec7017SPing-Ke Shih case RTL8852B: 1971e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52B; 1972e3ec7017SPing-Ke Shih break; 1973e3ec7017SPing-Ke Shih default: 1974e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52C; 1975e3ec7017SPing-Ke Shih break; 1976e3ec7017SPing-Ke Shih } 1977e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 1978e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 1979e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1980e3ec7017SPing-Ke Shih 1981e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); 1982e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 1983e3ec7017SPing-Ke Shih 1984e3ec7017SPing-Ke Shih return 0; 1985e3ec7017SPing-Ke Shih } 1986e3ec7017SPing-Ke Shih 198718175197SPing-Ke Shih static void rst_bacam(struct rtw89_dev *rtwdev) 198818175197SPing-Ke Shih { 198918175197SPing-Ke Shih u32 val32; 199018175197SPing-Ke Shih int ret; 199118175197SPing-Ke Shih 199218175197SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 199318175197SPing-Ke Shih S_AX_BACAM_RST_ALL); 199418175197SPing-Ke Shih 199518175197SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 199618175197SPing-Ke Shih 1, 1000, false, 199718175197SPing-Ke Shih rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 199818175197SPing-Ke Shih if (ret) 199918175197SPing-Ke Shih rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 200018175197SPing-Ke Shih } 200118175197SPing-Ke Shih 2002e3ec7017SPing-Ke Shih static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2003e3ec7017SPing-Ke Shih { 2004e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_CCA_TO 32 2005e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_DATA_TO 15 2006e3ec7017SPing-Ke Shih #define RX_MAX_LEN_UNIT 512 2007e3ec7017SPing-Ke Shih #define PLD_RLS_MAX_PG 127 2008e3ec7017SPing-Ke Shih int ret; 2009e3ec7017SPing-Ke Shih u32 reg, rx_max_len, rx_qta; 2010e3ec7017SPing-Ke Shih u16 val; 2011e3ec7017SPing-Ke Shih 2012e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2013e3ec7017SPing-Ke Shih if (ret) 2014e3ec7017SPing-Ke Shih return ret; 2015e3ec7017SPing-Ke Shih 201618175197SPing-Ke Shih if (mac_idx == RTW89_MAC_0) 201718175197SPing-Ke Shih rst_bacam(rtwdev); 201818175197SPing-Ke Shih 2019e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); 2020e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2021e3ec7017SPing-Ke Shih 2022e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); 2023e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 2024e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2025e3ec7017SPing-Ke Shih B_AX_RX_DLK_DATA_TIME_MASK); 2026e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2027e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK); 2028e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 2029e3ec7017SPing-Ke Shih 2030e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); 2031e3ec7017SPing-Ke Shih rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2032e3ec7017SPing-Ke Shih 2033e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); 2034e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_0) 2035e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2036e3ec7017SPing-Ke Shih else 2037e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2038e3ec7017SPing-Ke Shih rx_qta = rx_qta > PLD_RLS_MAX_PG ? PLD_RLS_MAX_PG : rx_qta; 2039e3ec7017SPing-Ke Shih rx_max_len = (rx_qta - 1) * rtwdev->mac.dle_info.ple_pg_size / 2040e3ec7017SPing-Ke Shih RX_MAX_LEN_UNIT; 2041e3ec7017SPing-Ke Shih rx_max_len = rx_max_len > B_AX_RX_MPDU_MAX_LEN_SIZE ? 2042e3ec7017SPing-Ke Shih B_AX_RX_MPDU_MAX_LEN_SIZE : rx_max_len; 2043e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2044e3ec7017SPing-Ke Shih 2045e3ec7017SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852A && 2046e3ec7017SPing-Ke Shih rtwdev->hal.cv == CHIP_CBV) { 2047e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, 2048e3ec7017SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), 2049e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK, 0); 2050e3ec7017SPing-Ke Shih rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), 2051e3ec7017SPing-Ke Shih BIT(12)); 2052e3ec7017SPing-Ke Shih } 2053e3ec7017SPing-Ke Shih 2054e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); 2055e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2056e3ec7017SPing-Ke Shih 2057e3ec7017SPing-Ke Shih return ret; 2058e3ec7017SPing-Ke Shih } 2059e3ec7017SPing-Ke Shih 2060e3ec7017SPing-Ke Shih static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2061e3ec7017SPing-Ke Shih { 2062e3ec7017SPing-Ke Shih u32 val, reg; 2063e3ec7017SPing-Ke Shih int ret; 2064e3ec7017SPing-Ke Shih 2065e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2066e3ec7017SPing-Ke Shih if (ret) 2067e3ec7017SPing-Ke Shih return ret; 2068e3ec7017SPing-Ke Shih 2069e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2070e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2071e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2072e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2073e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2074e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2075e3ec7017SPing-Ke Shih 2076e3ec7017SPing-Ke Shih return 0; 2077e3ec7017SPing-Ke Shih } 2078e3ec7017SPing-Ke Shih 2079e3ec7017SPing-Ke Shih static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2080e3ec7017SPing-Ke Shih { 2081e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 2082e3ec7017SPing-Ke Shih 2083e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 2084e3ec7017SPing-Ke Shih if (!cfg) { 2085e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2086e3ec7017SPing-Ke Shih return false; 2087e3ec7017SPing-Ke Shih } 2088e3ec7017SPing-Ke Shih 2089e3ec7017SPing-Ke Shih return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2090e3ec7017SPing-Ke Shih } 2091e3ec7017SPing-Ke Shih 2092e3ec7017SPing-Ke Shih static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2093e3ec7017SPing-Ke Shih { 2094e3ec7017SPing-Ke Shih u32 val, reg; 2095e3ec7017SPing-Ke Shih int ret; 2096e3ec7017SPing-Ke Shih 2097e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2098e3ec7017SPing-Ke Shih if (ret) 2099e3ec7017SPing-Ke Shih return ret; 2100e3ec7017SPing-Ke Shih 2101e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2102e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2103e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2104e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2105e3ec7017SPing-Ke Shih B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 21069fb4862eSPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 21079fb4862eSPing-Ke Shih B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2108e3ec7017SPing-Ke Shih val |= B_AX_HW_CTS2SELF_EN; 2109e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2110e3ec7017SPing-Ke Shih 2111e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); 2112e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2113e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2114e3ec7017SPing-Ke Shih val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2115e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2116e3ec7017SPing-Ke Shih } 2117e3ec7017SPing-Ke Shih 21189fb4862eSPing-Ke Shih if (mac_idx == RTW89_MAC_0) { 21199fb4862eSPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 21209fb4862eSPing-Ke Shih B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 21219fb4862eSPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 21229fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_0 | 21239fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_1 | 21249fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_UL); 21259fb4862eSPing-Ke Shih rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 21269fb4862eSPing-Ke Shih B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 21279fb4862eSPing-Ke Shih } else if (mac_idx == RTW89_MAC_1) { 21289fb4862eSPing-Ke Shih rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 21299fb4862eSPing-Ke Shih B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 21309fb4862eSPing-Ke Shih } 2131e3ec7017SPing-Ke Shih 2132e3ec7017SPing-Ke Shih return 0; 2133e3ec7017SPing-Ke Shih } 2134e3ec7017SPing-Ke Shih 2135e3ec7017SPing-Ke Shih static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2136e3ec7017SPing-Ke Shih { 2137e3ec7017SPing-Ke Shih int ret; 2138e3ec7017SPing-Ke Shih 2139e3ec7017SPing-Ke Shih ret = scheduler_init(rtwdev, mac_idx); 2140e3ec7017SPing-Ke Shih if (ret) { 2141e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2142e3ec7017SPing-Ke Shih return ret; 2143e3ec7017SPing-Ke Shih } 2144e3ec7017SPing-Ke Shih 2145e3ec7017SPing-Ke Shih ret = addr_cam_init(rtwdev, mac_idx); 2146e3ec7017SPing-Ke Shih if (ret) { 2147e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2148e3ec7017SPing-Ke Shih ret); 2149e3ec7017SPing-Ke Shih return ret; 2150e3ec7017SPing-Ke Shih } 2151e3ec7017SPing-Ke Shih 2152e3ec7017SPing-Ke Shih ret = rx_fltr_init(rtwdev, mac_idx); 2153e3ec7017SPing-Ke Shih if (ret) { 2154e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2155e3ec7017SPing-Ke Shih ret); 2156e3ec7017SPing-Ke Shih return ret; 2157e3ec7017SPing-Ke Shih } 2158e3ec7017SPing-Ke Shih 2159e3ec7017SPing-Ke Shih ret = cca_ctrl_init(rtwdev, mac_idx); 2160e3ec7017SPing-Ke Shih if (ret) { 2161e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2162e3ec7017SPing-Ke Shih ret); 2163e3ec7017SPing-Ke Shih return ret; 2164e3ec7017SPing-Ke Shih } 2165e3ec7017SPing-Ke Shih 216619cb9427SPing-Ke Shih ret = nav_ctrl_init(rtwdev); 216719cb9427SPing-Ke Shih if (ret) { 216819cb9427SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 216919cb9427SPing-Ke Shih ret); 217019cb9427SPing-Ke Shih return ret; 217119cb9427SPing-Ke Shih } 217219cb9427SPing-Ke Shih 2173e3ec7017SPing-Ke Shih ret = spatial_reuse_init(rtwdev, mac_idx); 2174e3ec7017SPing-Ke Shih if (ret) { 2175e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2176e3ec7017SPing-Ke Shih mac_idx, ret); 2177e3ec7017SPing-Ke Shih return ret; 2178e3ec7017SPing-Ke Shih } 2179e3ec7017SPing-Ke Shih 2180e3ec7017SPing-Ke Shih ret = tmac_init(rtwdev, mac_idx); 2181e3ec7017SPing-Ke Shih if (ret) { 2182e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2183e3ec7017SPing-Ke Shih return ret; 2184e3ec7017SPing-Ke Shih } 2185e3ec7017SPing-Ke Shih 2186e3ec7017SPing-Ke Shih ret = trxptcl_init(rtwdev, mac_idx); 2187e3ec7017SPing-Ke Shih if (ret) { 2188e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2189e3ec7017SPing-Ke Shih return ret; 2190e3ec7017SPing-Ke Shih } 2191e3ec7017SPing-Ke Shih 2192e3ec7017SPing-Ke Shih ret = rmac_init(rtwdev, mac_idx); 2193e3ec7017SPing-Ke Shih if (ret) { 2194e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2195e3ec7017SPing-Ke Shih return ret; 2196e3ec7017SPing-Ke Shih } 2197e3ec7017SPing-Ke Shih 2198e3ec7017SPing-Ke Shih ret = cmac_com_init(rtwdev, mac_idx); 2199e3ec7017SPing-Ke Shih if (ret) { 2200e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2201e3ec7017SPing-Ke Shih return ret; 2202e3ec7017SPing-Ke Shih } 2203e3ec7017SPing-Ke Shih 2204e3ec7017SPing-Ke Shih ret = ptcl_init(rtwdev, mac_idx); 2205e3ec7017SPing-Ke Shih if (ret) { 2206e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2207e3ec7017SPing-Ke Shih return ret; 2208e3ec7017SPing-Ke Shih } 2209e3ec7017SPing-Ke Shih 2210e3ec7017SPing-Ke Shih return ret; 2211e3ec7017SPing-Ke Shih } 2212e3ec7017SPing-Ke Shih 2213e3ec7017SPing-Ke Shih static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2214e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info *c2h_info) 2215e3ec7017SPing-Ke Shih { 2216e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 2217e3ec7017SPing-Ke Shih u32 ret; 2218e3ec7017SPing-Ke Shih 2219e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2220e3ec7017SPing-Ke Shih h2c_info.content_len = 0; 2221e3ec7017SPing-Ke Shih 2222e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2223e3ec7017SPing-Ke Shih if (ret) 2224e3ec7017SPing-Ke Shih return ret; 2225e3ec7017SPing-Ke Shih 2226e3ec7017SPing-Ke Shih if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2227e3ec7017SPing-Ke Shih return -EINVAL; 2228e3ec7017SPing-Ke Shih 2229e3ec7017SPing-Ke Shih return 0; 2230e3ec7017SPing-Ke Shih } 2231e3ec7017SPing-Ke Shih 2232e3ec7017SPing-Ke Shih int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2233e3ec7017SPing-Ke Shih { 2234e3ec7017SPing-Ke Shih struct rtw89_hal *hal = &rtwdev->hal; 2235e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2236e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 2237e3ec7017SPing-Ke Shih struct rtw89_c2h_phy_cap *cap = 2238e3ec7017SPing-Ke Shih (struct rtw89_c2h_phy_cap *)&c2h_info.c2hreg[0]; 2239e3ec7017SPing-Ke Shih u32 ret; 2240e3ec7017SPing-Ke Shih 2241e3ec7017SPing-Ke Shih ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2242e3ec7017SPing-Ke Shih if (ret) 2243e3ec7017SPing-Ke Shih return ret; 2244e3ec7017SPing-Ke Shih 2245e3ec7017SPing-Ke Shih hal->tx_nss = cap->tx_nss ? 2246e3ec7017SPing-Ke Shih min_t(u8, cap->tx_nss, chip->tx_nss) : chip->tx_nss; 2247e3ec7017SPing-Ke Shih hal->rx_nss = cap->rx_nss ? 2248e3ec7017SPing-Ke Shih min_t(u8, cap->rx_nss, chip->rx_nss) : chip->rx_nss; 2249e3ec7017SPing-Ke Shih 2250e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 2251e3ec7017SPing-Ke Shih "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2252e3ec7017SPing-Ke Shih hal->tx_nss, cap->tx_nss, chip->tx_nss, 2253e3ec7017SPing-Ke Shih hal->rx_nss, cap->rx_nss, chip->rx_nss); 2254e3ec7017SPing-Ke Shih 2255e3ec7017SPing-Ke Shih return 0; 2256e3ec7017SPing-Ke Shih } 2257e3ec7017SPing-Ke Shih 2258e3ec7017SPing-Ke Shih static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2259e3ec7017SPing-Ke Shih u16 tx_en_u16, u16 mask_u16) 2260e3ec7017SPing-Ke Shih { 2261e3ec7017SPing-Ke Shih u32 ret; 2262e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 2263e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 2264e3ec7017SPing-Ke Shih struct rtw89_h2creg_sch_tx_en *h2creg = 2265e3ec7017SPing-Ke Shih (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; 2266e3ec7017SPing-Ke Shih 2267e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2268e3ec7017SPing-Ke Shih h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; 2269e3ec7017SPing-Ke Shih h2creg->tx_en = tx_en_u16; 2270e3ec7017SPing-Ke Shih h2creg->mask = mask_u16; 2271e3ec7017SPing-Ke Shih h2creg->band = band; 2272e3ec7017SPing-Ke Shih 2273e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2274e3ec7017SPing-Ke Shih if (ret) 2275e3ec7017SPing-Ke Shih return ret; 2276e3ec7017SPing-Ke Shih 2277e3ec7017SPing-Ke Shih if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2278e3ec7017SPing-Ke Shih return -EINVAL; 2279e3ec7017SPing-Ke Shih 2280e3ec7017SPing-Ke Shih return 0; 2281e3ec7017SPing-Ke Shih } 2282e3ec7017SPing-Ke Shih 2283e3ec7017SPing-Ke Shih static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2284e3ec7017SPing-Ke Shih u16 tx_en, u16 tx_en_mask) 2285e3ec7017SPing-Ke Shih { 2286e3ec7017SPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); 2287e3ec7017SPing-Ke Shih u16 val; 2288e3ec7017SPing-Ke Shih int ret; 2289e3ec7017SPing-Ke Shih 2290e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2291e3ec7017SPing-Ke Shih if (ret) 2292e3ec7017SPing-Ke Shih return ret; 2293e3ec7017SPing-Ke Shih 2294e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2295e3ec7017SPing-Ke Shih return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2296e3ec7017SPing-Ke Shih tx_en, tx_en_mask); 2297e3ec7017SPing-Ke Shih 2298e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 2299e3ec7017SPing-Ke Shih val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2300e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 2301e3ec7017SPing-Ke Shih 2302e3ec7017SPing-Ke Shih return 0; 2303e3ec7017SPing-Ke Shih } 2304e3ec7017SPing-Ke Shih 2305de7ba639SPing-Ke Shih static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2306de7ba639SPing-Ke Shih u32 tx_en, u32 tx_en_mask) 2307de7ba639SPing-Ke Shih { 2308de7ba639SPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx); 2309de7ba639SPing-Ke Shih u32 val; 2310de7ba639SPing-Ke Shih int ret; 2311de7ba639SPing-Ke Shih 2312de7ba639SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2313de7ba639SPing-Ke Shih if (ret) 2314de7ba639SPing-Ke Shih return ret; 2315de7ba639SPing-Ke Shih 2316de7ba639SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2317de7ba639SPing-Ke Shih val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2318de7ba639SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2319de7ba639SPing-Ke Shih 2320de7ba639SPing-Ke Shih return 0; 2321de7ba639SPing-Ke Shih } 2322de7ba639SPing-Ke Shih 2323e3ec7017SPing-Ke Shih int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2324d780f926SPing-Ke Shih u32 *tx_en, enum rtw89_sch_tx_sel sel) 2325e3ec7017SPing-Ke Shih { 2326e3ec7017SPing-Ke Shih int ret; 2327e3ec7017SPing-Ke Shih 2328e3ec7017SPing-Ke Shih *tx_en = rtw89_read16(rtwdev, 2329e3ec7017SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); 2330e3ec7017SPing-Ke Shih 2331e3ec7017SPing-Ke Shih switch (sel) { 2332e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_ALL: 2333de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2334de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK); 2335e3ec7017SPing-Ke Shih if (ret) 2336e3ec7017SPing-Ke Shih return ret; 2337e3ec7017SPing-Ke Shih break; 2338e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_HIQ: 2339e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2340e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_HGQ); 2341e3ec7017SPing-Ke Shih if (ret) 2342e3ec7017SPing-Ke Shih return ret; 2343e3ec7017SPing-Ke Shih break; 2344e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MG0: 2345e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2346e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_MGQ); 2347e3ec7017SPing-Ke Shih if (ret) 2348e3ec7017SPing-Ke Shih return ret; 2349e3ec7017SPing-Ke Shih break; 2350e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MACID: 2351de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2352de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK); 2353e3ec7017SPing-Ke Shih if (ret) 2354e3ec7017SPing-Ke Shih return ret; 2355e3ec7017SPing-Ke Shih break; 2356e3ec7017SPing-Ke Shih default: 2357e3ec7017SPing-Ke Shih return 0; 2358e3ec7017SPing-Ke Shih } 2359e3ec7017SPing-Ke Shih 2360e3ec7017SPing-Ke Shih return 0; 2361e3ec7017SPing-Ke Shih } 2362861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2363e3ec7017SPing-Ke Shih 2364de7ba639SPing-Ke Shih int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2365de7ba639SPing-Ke Shih u32 *tx_en, enum rtw89_sch_tx_sel sel) 2366de7ba639SPing-Ke Shih { 2367de7ba639SPing-Ke Shih int ret; 2368de7ba639SPing-Ke Shih 2369de7ba639SPing-Ke Shih *tx_en = rtw89_read32(rtwdev, 2370de7ba639SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx)); 2371de7ba639SPing-Ke Shih 2372de7ba639SPing-Ke Shih switch (sel) { 2373de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_ALL: 2374de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2375de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 2376de7ba639SPing-Ke Shih if (ret) 2377de7ba639SPing-Ke Shih return ret; 2378de7ba639SPing-Ke Shih break; 2379de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_HIQ: 2380de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2381de7ba639SPing-Ke Shih 0, B_AX_CTN_TXEN_HGQ); 2382de7ba639SPing-Ke Shih if (ret) 2383de7ba639SPing-Ke Shih return ret; 2384de7ba639SPing-Ke Shih break; 2385de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_MG0: 2386de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2387de7ba639SPing-Ke Shih 0, B_AX_CTN_TXEN_MGQ); 2388de7ba639SPing-Ke Shih if (ret) 2389de7ba639SPing-Ke Shih return ret; 2390de7ba639SPing-Ke Shih break; 2391de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_MACID: 2392de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2393de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 2394de7ba639SPing-Ke Shih if (ret) 2395de7ba639SPing-Ke Shih return ret; 2396de7ba639SPing-Ke Shih break; 2397de7ba639SPing-Ke Shih default: 2398de7ba639SPing-Ke Shih return 0; 2399de7ba639SPing-Ke Shih } 2400de7ba639SPing-Ke Shih 2401de7ba639SPing-Ke Shih return 0; 2402de7ba639SPing-Ke Shih } 2403de7ba639SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2404de7ba639SPing-Ke Shih 2405d780f926SPing-Ke Shih int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2406e3ec7017SPing-Ke Shih { 2407e3ec7017SPing-Ke Shih int ret; 2408e3ec7017SPing-Ke Shih 2409de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2410e3ec7017SPing-Ke Shih if (ret) 2411e3ec7017SPing-Ke Shih return ret; 2412e3ec7017SPing-Ke Shih 2413e3ec7017SPing-Ke Shih return 0; 2414e3ec7017SPing-Ke Shih } 2415861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2416e3ec7017SPing-Ke Shih 2417de7ba639SPing-Ke Shih int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2418de7ba639SPing-Ke Shih { 2419de7ba639SPing-Ke Shih int ret; 2420de7ba639SPing-Ke Shih 2421de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2422de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 2423de7ba639SPing-Ke Shih if (ret) 2424de7ba639SPing-Ke Shih return ret; 2425de7ba639SPing-Ke Shih 2426de7ba639SPing-Ke Shih return 0; 2427de7ba639SPing-Ke Shih } 2428de7ba639SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2429de7ba639SPing-Ke Shih 2430e3ec7017SPing-Ke Shih static u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, 2431e3ec7017SPing-Ke Shih bool wd) 2432e3ec7017SPing-Ke Shih { 2433e3ec7017SPing-Ke Shih u32 val, reg; 2434e3ec7017SPing-Ke Shih int ret; 2435e3ec7017SPing-Ke Shih 2436e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2437e3ec7017SPing-Ke Shih val = buf_len; 2438e3ec7017SPing-Ke Shih val |= B_AX_WD_BUF_REQ_EXEC; 2439e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2440e3ec7017SPing-Ke Shih 2441e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2442e3ec7017SPing-Ke Shih 2443e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2444e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 2445e3ec7017SPing-Ke Shih if (ret) 2446e3ec7017SPing-Ke Shih return 0xffff; 2447e3ec7017SPing-Ke Shih 2448e3ec7017SPing-Ke Shih return FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2449e3ec7017SPing-Ke Shih } 2450e3ec7017SPing-Ke Shih 2451e3ec7017SPing-Ke Shih static int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2452e3ec7017SPing-Ke Shih struct rtw89_cpuio_ctrl *ctrl_para, 2453e3ec7017SPing-Ke Shih bool wd) 2454e3ec7017SPing-Ke Shih { 2455e3ec7017SPing-Ke Shih u32 val, cmd_type, reg; 2456e3ec7017SPing-Ke Shih int ret; 2457e3ec7017SPing-Ke Shih 2458e3ec7017SPing-Ke Shih cmd_type = ctrl_para->cmd_type; 2459e3ec7017SPing-Ke Shih 2460e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2461e3ec7017SPing-Ke Shih val = 0; 2462e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->start_pktid, 2463e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2464e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->end_pktid, 2465e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2466e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2467e3ec7017SPing-Ke Shih 2468e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2469e3ec7017SPing-Ke Shih val = 0; 2470e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_pid, 2471e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_PID_MASK); 2472e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_qid, 2473e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_QID_MASK); 2474e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_pid, 2475e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_PID_MASK); 2476e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_qid, 2477e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_QID_MASK); 2478e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2479e3ec7017SPing-Ke Shih 2480e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2481e3ec7017SPing-Ke Shih val = 0; 2482e3ec7017SPing-Ke Shih val = u32_replace_bits(val, cmd_type, 2483e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_CMD_TYPE_MASK); 2484e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->macid, 2485e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_MACID_MASK); 2486e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->pkt_num, 2487e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_PKTNUM_MASK); 2488e3ec7017SPing-Ke Shih val |= B_AX_WD_CPUQ_OP_EXEC; 2489e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2490e3ec7017SPing-Ke Shih 2491e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2492e3ec7017SPing-Ke Shih 2493e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2494e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 2495e3ec7017SPing-Ke Shih if (ret) 2496e3ec7017SPing-Ke Shih return ret; 2497e3ec7017SPing-Ke Shih 2498e3ec7017SPing-Ke Shih if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2499e3ec7017SPing-Ke Shih cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2500e3ec7017SPing-Ke Shih ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2501e3ec7017SPing-Ke Shih 2502e3ec7017SPing-Ke Shih return 0; 2503e3ec7017SPing-Ke Shih } 2504e3ec7017SPing-Ke Shih 2505e3ec7017SPing-Ke Shih static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2506e3ec7017SPing-Ke Shih { 2507e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 2508e3ec7017SPing-Ke Shih struct rtw89_cpuio_ctrl ctrl_para = {0}; 2509e3ec7017SPing-Ke Shih u16 pkt_id; 2510e3ec7017SPing-Ke Shih int ret; 2511e3ec7017SPing-Ke Shih 2512e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 2513e3ec7017SPing-Ke Shih if (!cfg) { 2514e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2515e3ec7017SPing-Ke Shih return -EINVAL; 2516e3ec7017SPing-Ke Shih } 2517e3ec7017SPing-Ke Shih 2518e3ec7017SPing-Ke Shih if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { 2519e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2520e3ec7017SPing-Ke Shih return -EINVAL; 2521e3ec7017SPing-Ke Shih } 2522e3ec7017SPing-Ke Shih 2523e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2524e3ec7017SPing-Ke Shih 2525e3ec7017SPing-Ke Shih pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true); 2526e3ec7017SPing-Ke Shih if (pkt_id == 0xffff) { 2527e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2528e3ec7017SPing-Ke Shih return -ENOMEM; 2529e3ec7017SPing-Ke Shih } 2530e3ec7017SPing-Ke Shih 2531e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2532e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 2533e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 2534e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 2535e3ec7017SPing-Ke Shih ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2536e3ec7017SPing-Ke Shih ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2537e3ec7017SPing-Ke Shih ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2538e3ec7017SPing-Ke Shih if (ret) { 2539e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2540e3ec7017SPing-Ke Shih return -EFAULT; 2541e3ec7017SPing-Ke Shih } 2542e3ec7017SPing-Ke Shih 2543e3ec7017SPing-Ke Shih pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, false); 2544e3ec7017SPing-Ke Shih if (pkt_id == 0xffff) { 2545e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2546e3ec7017SPing-Ke Shih return -ENOMEM; 2547e3ec7017SPing-Ke Shih } 2548e3ec7017SPing-Ke Shih 2549e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2550e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 2551e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 2552e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 2553e3ec7017SPing-Ke Shih ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 2554e3ec7017SPing-Ke Shih ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 2555e3ec7017SPing-Ke Shih ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 2556e3ec7017SPing-Ke Shih if (ret) { 2557e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 2558e3ec7017SPing-Ke Shih return -EFAULT; 2559e3ec7017SPing-Ke Shih } 2560e3ec7017SPing-Ke Shih 2561e3ec7017SPing-Ke Shih return 0; 2562e3ec7017SPing-Ke Shih } 2563e3ec7017SPing-Ke Shih 2564e3ec7017SPing-Ke Shih static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 2565e3ec7017SPing-Ke Shih { 2566e3ec7017SPing-Ke Shih int ret; 2567e3ec7017SPing-Ke Shih u32 reg; 2568e3ec7017SPing-Ke Shih u8 val; 2569e3ec7017SPing-Ke Shih 2570e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2571e3ec7017SPing-Ke Shih if (ret) 2572e3ec7017SPing-Ke Shih return ret; 2573e3ec7017SPing-Ke Shih 2574e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); 2575e3ec7017SPing-Ke Shih 2576e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, 2577e3ec7017SPing-Ke Shih (val & B_AX_PTCL_TX_ON_STAT) == 0, 2578e3ec7017SPing-Ke Shih SW_CVR_DUR_US, 2579e3ec7017SPing-Ke Shih SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 2580e3ec7017SPing-Ke Shih false, rtwdev, reg); 2581e3ec7017SPing-Ke Shih if (ret) 2582e3ec7017SPing-Ke Shih return ret; 2583e3ec7017SPing-Ke Shih 2584e3ec7017SPing-Ke Shih return 0; 2585e3ec7017SPing-Ke Shih } 2586e3ec7017SPing-Ke Shih 2587e3ec7017SPing-Ke Shih static int band1_enable(struct rtw89_dev *rtwdev) 2588e3ec7017SPing-Ke Shih { 2589e3ec7017SPing-Ke Shih int ret, i; 2590e3ec7017SPing-Ke Shih u32 sleep_bak[4] = {0}; 2591e3ec7017SPing-Ke Shih u32 pause_bak[4] = {0}; 2592d780f926SPing-Ke Shih u32 tx_en; 2593e3ec7017SPing-Ke Shih 2594de7ba639SPing-Ke Shih ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 2595e3ec7017SPing-Ke Shih if (ret) { 2596e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 2597e3ec7017SPing-Ke Shih return ret; 2598e3ec7017SPing-Ke Shih } 2599e3ec7017SPing-Ke Shih 2600e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 2601e3ec7017SPing-Ke Shih sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 2602e3ec7017SPing-Ke Shih pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 2603e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 2604e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 2605e3ec7017SPing-Ke Shih } 2606e3ec7017SPing-Ke Shih 2607e3ec7017SPing-Ke Shih ret = band_idle_ck_b(rtwdev, 0); 2608e3ec7017SPing-Ke Shih if (ret) { 2609e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 2610e3ec7017SPing-Ke Shih return ret; 2611e3ec7017SPing-Ke Shih } 2612e3ec7017SPing-Ke Shih 2613e3ec7017SPing-Ke Shih ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 2614e3ec7017SPing-Ke Shih if (ret) { 2615e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 2616e3ec7017SPing-Ke Shih return ret; 2617e3ec7017SPing-Ke Shih } 2618e3ec7017SPing-Ke Shih 2619e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 2620e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 2621e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 2622e3ec7017SPing-Ke Shih } 2623e3ec7017SPing-Ke Shih 2624de7ba639SPing-Ke Shih ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 2625e3ec7017SPing-Ke Shih if (ret) { 2626e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 2627e3ec7017SPing-Ke Shih return ret; 2628e3ec7017SPing-Ke Shih } 2629e3ec7017SPing-Ke Shih 2630e3ec7017SPing-Ke Shih ret = cmac_func_en(rtwdev, 1, true); 2631e3ec7017SPing-Ke Shih if (ret) { 2632e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 2633e3ec7017SPing-Ke Shih return ret; 2634e3ec7017SPing-Ke Shih } 2635e3ec7017SPing-Ke Shih 2636e3ec7017SPing-Ke Shih ret = cmac_init(rtwdev, 1); 2637e3ec7017SPing-Ke Shih if (ret) { 2638e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 2639e3ec7017SPing-Ke Shih return ret; 2640e3ec7017SPing-Ke Shih } 2641e3ec7017SPing-Ke Shih 2642e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 2643e3ec7017SPing-Ke Shih B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 2644e3ec7017SPing-Ke Shih 2645e3ec7017SPing-Ke Shih return 0; 2646e3ec7017SPing-Ke Shih } 2647e3ec7017SPing-Ke Shih 2648eeadcd2aSChia-Yuan Li static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 2649eeadcd2aSChia-Yuan Li { 2650eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2651eeadcd2aSChia-Yuan Li 2652eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 2653eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 2654eeadcd2aSChia-Yuan Li } 2655eeadcd2aSChia-Yuan Li 2656eeadcd2aSChia-Yuan Li static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 2657eeadcd2aSChia-Yuan Li { 2658eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2659eeadcd2aSChia-Yuan Li 2660eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 2661eeadcd2aSChia-Yuan Li } 2662eeadcd2aSChia-Yuan Li 2663eeadcd2aSChia-Yuan Li static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 2664eeadcd2aSChia-Yuan Li { 2665eeadcd2aSChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2666eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2667eeadcd2aSChia-Yuan Li 2668eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 2669eeadcd2aSChia-Yuan Li B_AX_TX_GET_ERRPKTID_INT_EN | 2670eeadcd2aSChia-Yuan Li B_AX_TX_NXT_ERRPKTID_INT_EN | 2671eeadcd2aSChia-Yuan Li B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 2672eeadcd2aSChia-Yuan Li B_AX_TX_OFFSET_ERR_INT_EN | 2673eeadcd2aSChia-Yuan Li B_AX_TX_HDR3_SIZE_ERR_INT_EN); 2674eeadcd2aSChia-Yuan Li if (chip_id == RTL8852C) 2675eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 2676eeadcd2aSChia-Yuan Li B_AX_TX_ETH_TYPE_ERR_EN | 2677eeadcd2aSChia-Yuan Li B_AX_TX_LLC_PRE_ERR_EN | 2678eeadcd2aSChia-Yuan Li B_AX_TX_NW_TYPE_ERR_EN | 2679eeadcd2aSChia-Yuan Li B_AX_TX_KSRCH_ERR_EN); 2680eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 2681eeadcd2aSChia-Yuan Li imr->mpdu_tx_imr_set); 2682eeadcd2aSChia-Yuan Li 2683eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 2684eeadcd2aSChia-Yuan Li B_AX_GETPKTID_ERR_INT_EN | 2685eeadcd2aSChia-Yuan Li B_AX_MHDRLEN_ERR_INT_EN | 2686eeadcd2aSChia-Yuan Li B_AX_RPT_ERR_INT_EN); 2687eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 2688eeadcd2aSChia-Yuan Li imr->mpdu_rx_imr_set); 2689eeadcd2aSChia-Yuan Li } 2690eeadcd2aSChia-Yuan Li 2691eeadcd2aSChia-Yuan Li static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 2692eeadcd2aSChia-Yuan Li { 2693eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2694eeadcd2aSChia-Yuan Li 2695eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 2696eeadcd2aSChia-Yuan Li B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 2697eeadcd2aSChia-Yuan Li B_AX_RPT_HANG_TIMEOUT_INT_EN | 2698eeadcd2aSChia-Yuan Li B_AX_PLE_B_PKTID_ERR_INT_EN); 2699eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 2700eeadcd2aSChia-Yuan Li imr->sta_sch_imr_set); 2701eeadcd2aSChia-Yuan Li } 2702eeadcd2aSChia-Yuan Li 2703eeadcd2aSChia-Yuan Li static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 2704eeadcd2aSChia-Yuan Li { 2705eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2706eeadcd2aSChia-Yuan Li 2707eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 2708eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b0_clr); 2709eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 2710eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b0_set); 2711eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 2712eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b1_clr); 2713eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 2714eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b1_set); 2715eeadcd2aSChia-Yuan Li } 2716eeadcd2aSChia-Yuan Li 2717eeadcd2aSChia-Yuan Li static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 2718eeadcd2aSChia-Yuan Li { 2719eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2720eeadcd2aSChia-Yuan Li 2721eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 2722eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 2723eeadcd2aSChia-Yuan Li } 2724eeadcd2aSChia-Yuan Li 2725eeadcd2aSChia-Yuan Li static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 2726eeadcd2aSChia-Yuan Li { 2727eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2728eeadcd2aSChia-Yuan Li 2729eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 2730eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 2731eeadcd2aSChia-Yuan Li } 2732eeadcd2aSChia-Yuan Li 2733eeadcd2aSChia-Yuan Li static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 2734eeadcd2aSChia-Yuan Li { 2735eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 2736eeadcd2aSChia-Yuan Li B_AX_PKTIN_GETPKTID_ERR_INT_EN); 2737eeadcd2aSChia-Yuan Li } 2738eeadcd2aSChia-Yuan Li 2739eeadcd2aSChia-Yuan Li static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 2740eeadcd2aSChia-Yuan Li { 2741eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2742eeadcd2aSChia-Yuan Li 2743eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 2744eeadcd2aSChia-Yuan Li imr->host_disp_imr_clr); 2745eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 2746eeadcd2aSChia-Yuan Li imr->host_disp_imr_set); 2747eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 2748eeadcd2aSChia-Yuan Li imr->cpu_disp_imr_clr); 2749eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 2750eeadcd2aSChia-Yuan Li imr->cpu_disp_imr_set); 2751eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 2752eeadcd2aSChia-Yuan Li imr->other_disp_imr_clr); 2753eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 2754eeadcd2aSChia-Yuan Li imr->other_disp_imr_set); 2755eeadcd2aSChia-Yuan Li } 2756eeadcd2aSChia-Yuan Li 2757eeadcd2aSChia-Yuan Li static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 2758eeadcd2aSChia-Yuan Li { 2759eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 2760eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 2761eeadcd2aSChia-Yuan Li } 2762eeadcd2aSChia-Yuan Li 2763eeadcd2aSChia-Yuan Li static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 2764eeadcd2aSChia-Yuan Li { 2765eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2766eeadcd2aSChia-Yuan Li 2767eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_BBRPT_COM_ERR_IMR, 2768eeadcd2aSChia-Yuan Li B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 2769eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 2770eeadcd2aSChia-Yuan Li B_AX_BBRPT_CHINFO_IMR_CLR); 2771eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 2772eeadcd2aSChia-Yuan Li imr->bbrpt_err_imr_set); 2773eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 2774eeadcd2aSChia-Yuan Li B_AX_BBRPT_DFS_TO_ERR_INT_EN); 2775eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 2776eeadcd2aSChia-Yuan Li } 2777eeadcd2aSChia-Yuan Li 2778d86369e9SChia-Yuan Li static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2779d86369e9SChia-Yuan Li { 2780d86369e9SChia-Yuan Li u32 reg; 2781d86369e9SChia-Yuan Li 2782d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); 2783d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 2784d86369e9SChia-Yuan Li B_AX_FSM_TIMEOUT_ERR_INT_EN); 2785d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 2786d86369e9SChia-Yuan Li } 2787d86369e9SChia-Yuan Li 2788d86369e9SChia-Yuan Li static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2789d86369e9SChia-Yuan Li { 2790d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2791d86369e9SChia-Yuan Li u32 reg; 2792d86369e9SChia-Yuan Li 2793d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); 2794d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 2795d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 2796d86369e9SChia-Yuan Li } 2797d86369e9SChia-Yuan Li 2798d86369e9SChia-Yuan Li static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2799d86369e9SChia-Yuan Li { 2800d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2801d86369e9SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2802d86369e9SChia-Yuan Li u32 reg; 2803d86369e9SChia-Yuan Li 2804d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx); 2805d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 2806d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 2807d86369e9SChia-Yuan Li 2808d86369e9SChia-Yuan Li if (chip_id == RTL8852C) { 2809d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx); 2810d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 2811d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 2812d86369e9SChia-Yuan Li } 2813d86369e9SChia-Yuan Li } 2814d86369e9SChia-Yuan Li 2815d86369e9SChia-Yuan Li static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2816d86369e9SChia-Yuan Li { 2817d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2818d86369e9SChia-Yuan Li u32 reg; 2819d86369e9SChia-Yuan Li 2820d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx); 2821d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 2822d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 2823d86369e9SChia-Yuan Li } 2824d86369e9SChia-Yuan Li 2825d86369e9SChia-Yuan Li static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2826d86369e9SChia-Yuan Li { 2827d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2828d86369e9SChia-Yuan Li u32 reg; 2829d86369e9SChia-Yuan Li 2830d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx); 2831d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 2832d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 2833d86369e9SChia-Yuan Li } 2834d86369e9SChia-Yuan Li 2835d86369e9SChia-Yuan Li static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2836d86369e9SChia-Yuan Li { 2837d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2838d86369e9SChia-Yuan Li u32 reg; 2839d86369e9SChia-Yuan Li 2840d86369e9SChia-Yuan Li reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx); 2841d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 2842d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 2843d86369e9SChia-Yuan Li } 2844d86369e9SChia-Yuan Li 2845e3ec7017SPing-Ke Shih static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 2846e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 2847e3ec7017SPing-Ke Shih { 2848e3ec7017SPing-Ke Shih int ret; 2849e3ec7017SPing-Ke Shih 2850e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 2851e3ec7017SPing-Ke Shih if (ret) { 2852e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 2853e3ec7017SPing-Ke Shih sel, mac_idx); 2854e3ec7017SPing-Ke Shih return ret; 2855e3ec7017SPing-Ke Shih } 2856e3ec7017SPing-Ke Shih 2857e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 2858eeadcd2aSChia-Yuan Li rtw89_wdrls_imr_enable(rtwdev); 2859eeadcd2aSChia-Yuan Li rtw89_wsec_imr_enable(rtwdev); 2860eeadcd2aSChia-Yuan Li rtw89_mpdu_trx_imr_enable(rtwdev); 2861eeadcd2aSChia-Yuan Li rtw89_sta_sch_imr_enable(rtwdev); 2862eeadcd2aSChia-Yuan Li rtw89_txpktctl_imr_enable(rtwdev); 2863eeadcd2aSChia-Yuan Li rtw89_wde_imr_enable(rtwdev); 2864eeadcd2aSChia-Yuan Li rtw89_ple_imr_enable(rtwdev); 2865eeadcd2aSChia-Yuan Li rtw89_pktin_imr_enable(rtwdev); 2866eeadcd2aSChia-Yuan Li rtw89_dispatcher_imr_enable(rtwdev); 2867eeadcd2aSChia-Yuan Li rtw89_cpuio_imr_enable(rtwdev); 2868eeadcd2aSChia-Yuan Li rtw89_bbrpt_imr_enable(rtwdev); 2869e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL) { 2870d86369e9SChia-Yuan Li rtw89_scheduler_imr_enable(rtwdev, mac_idx); 2871d86369e9SChia-Yuan Li rtw89_ptcl_imr_enable(rtwdev, mac_idx); 2872d86369e9SChia-Yuan Li rtw89_cdma_imr_enable(rtwdev, mac_idx); 2873d86369e9SChia-Yuan Li rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 2874d86369e9SChia-Yuan Li rtw89_rmac_imr_enable(rtwdev, mac_idx); 2875d86369e9SChia-Yuan Li rtw89_tmac_imr_enable(rtwdev, mac_idx); 2876e3ec7017SPing-Ke Shih } else { 2877e3ec7017SPing-Ke Shih return -EINVAL; 2878e3ec7017SPing-Ke Shih } 2879e3ec7017SPing-Ke Shih 2880e3ec7017SPing-Ke Shih return 0; 2881e3ec7017SPing-Ke Shih } 2882e3ec7017SPing-Ke Shih 28839f405b01SPing-Ke Shih static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) 28849f405b01SPing-Ke Shih { 28859f405b01SPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 28869f405b01SPing-Ke Shih 28879f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 28889f405b01SPing-Ke Shih en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 28899f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 28909f405b01SPing-Ke Shih en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 28919f405b01SPing-Ke Shih if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 28929f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 28939f405b01SPing-Ke Shih en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 28949f405b01SPing-Ke Shih } 28959f405b01SPing-Ke Shih 2896e3ec7017SPing-Ke Shih static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 2897e3ec7017SPing-Ke Shih { 2898e3ec7017SPing-Ke Shih int ret = 0; 2899e3ec7017SPing-Ke Shih 2900e3ec7017SPing-Ke Shih if (enable) { 2901e3ec7017SPing-Ke Shih ret = band1_enable(rtwdev); 2902e3ec7017SPing-Ke Shih if (ret) { 2903e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 2904e3ec7017SPing-Ke Shih return ret; 2905e3ec7017SPing-Ke Shih } 2906e3ec7017SPing-Ke Shih 2907e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 2908e3ec7017SPing-Ke Shih if (ret) { 2909e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 2910e3ec7017SPing-Ke Shih return ret; 2911e3ec7017SPing-Ke Shih } 2912e3ec7017SPing-Ke Shih } else { 2913e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 2914e3ec7017SPing-Ke Shih return -EINVAL; 2915e3ec7017SPing-Ke Shih } 2916e3ec7017SPing-Ke Shih 2917e3ec7017SPing-Ke Shih return 0; 2918e3ec7017SPing-Ke Shih } 2919e3ec7017SPing-Ke Shih 2920e3ec7017SPing-Ke Shih static int set_host_rpr(struct rtw89_dev *rtwdev) 2921e3ec7017SPing-Ke Shih { 2922e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2923e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 2924e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 2925e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 2926e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 2927e3ec7017SPing-Ke Shih } else { 2928e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 2929e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 2930e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 2931e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 2932e3ec7017SPing-Ke Shih } 2933e3ec7017SPing-Ke Shih 2934e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 2935e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 2936e3ec7017SPing-Ke Shih 2937e3ec7017SPing-Ke Shih return 0; 2938e3ec7017SPing-Ke Shih } 2939e3ec7017SPing-Ke Shih 2940e3ec7017SPing-Ke Shih static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 2941e3ec7017SPing-Ke Shih { 2942e3ec7017SPing-Ke Shih enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 2943e3ec7017SPing-Ke Shih int ret; 2944e3ec7017SPing-Ke Shih 2945e3ec7017SPing-Ke Shih ret = dmac_init(rtwdev, 0); 2946e3ec7017SPing-Ke Shih if (ret) { 2947e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 2948e3ec7017SPing-Ke Shih return ret; 2949e3ec7017SPing-Ke Shih } 2950e3ec7017SPing-Ke Shih 2951e3ec7017SPing-Ke Shih ret = cmac_init(rtwdev, 0); 2952e3ec7017SPing-Ke Shih if (ret) { 2953e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 2954e3ec7017SPing-Ke Shih return ret; 2955e3ec7017SPing-Ke Shih } 2956e3ec7017SPing-Ke Shih 2957e3ec7017SPing-Ke Shih if (is_qta_dbcc(rtwdev, qta_mode)) { 2958e3ec7017SPing-Ke Shih ret = rtw89_mac_dbcc_enable(rtwdev, true); 2959e3ec7017SPing-Ke Shih if (ret) { 2960e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 2961e3ec7017SPing-Ke Shih return ret; 2962e3ec7017SPing-Ke Shih } 2963e3ec7017SPing-Ke Shih } 2964e3ec7017SPing-Ke Shih 2965e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2966e3ec7017SPing-Ke Shih if (ret) { 2967e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 2968e3ec7017SPing-Ke Shih return ret; 2969e3ec7017SPing-Ke Shih } 2970e3ec7017SPing-Ke Shih 2971e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 2972e3ec7017SPing-Ke Shih if (ret) { 2973e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 2974e3ec7017SPing-Ke Shih return ret; 2975e3ec7017SPing-Ke Shih } 2976e3ec7017SPing-Ke Shih 29779f405b01SPing-Ke Shih rtw89_mac_err_imr_ctrl(rtwdev, true); 29789f405b01SPing-Ke Shih 2979e3ec7017SPing-Ke Shih ret = set_host_rpr(rtwdev); 2980e3ec7017SPing-Ke Shih if (ret) { 2981e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 2982e3ec7017SPing-Ke Shih return ret; 2983e3ec7017SPing-Ke Shih } 2984e3ec7017SPing-Ke Shih 2985e3ec7017SPing-Ke Shih return 0; 2986e3ec7017SPing-Ke Shih } 2987e3ec7017SPing-Ke Shih 2988ec356ffbSChia-Yuan Li static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 2989ec356ffbSChia-Yuan Li { 2990ec356ffbSChia-Yuan Li u32 val32; 2991ec356ffbSChia-Yuan Li 2992ec356ffbSChia-Yuan Li rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 2993ec356ffbSChia-Yuan Li WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 2994ec356ffbSChia-Yuan Li 2995ec356ffbSChia-Yuan Li val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 2996ec356ffbSChia-Yuan Li val32 |= B_AX_FS_WDT_INT; 2997ec356ffbSChia-Yuan Li val32 &= ~B_AX_FS_WDT_INT_MSK; 2998ec356ffbSChia-Yuan Li rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 2999ec356ffbSChia-Yuan Li } 3000ec356ffbSChia-Yuan Li 3001e3ec7017SPing-Ke Shih static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) 3002e3ec7017SPing-Ke Shih { 3003e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3004e3ec7017SPing-Ke Shih 3005e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3006de78869dSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3007de78869dSChia-Yuan Li B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3008e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3009ec356ffbSChia-Yuan Li 3010ec356ffbSChia-Yuan Li rtw89_disable_fw_watchdog(rtwdev); 3011ec356ffbSChia-Yuan Li 3012de78869dSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3013de78869dSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3014e3ec7017SPing-Ke Shih } 3015e3ec7017SPing-Ke Shih 3016e3ec7017SPing-Ke Shih static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, 3017e3ec7017SPing-Ke Shih bool dlfw) 3018e3ec7017SPing-Ke Shih { 3019e3ec7017SPing-Ke Shih u32 val; 3020e3ec7017SPing-Ke Shih int ret; 3021e3ec7017SPing-Ke Shih 3022e3ec7017SPing-Ke Shih if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3023e3ec7017SPing-Ke Shih return -EFAULT; 3024e3ec7017SPing-Ke Shih 3025e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3026e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3027e3ec7017SPing-Ke Shih 3028e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3029e3ec7017SPing-Ke Shih 3030e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3031e3ec7017SPing-Ke Shih val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3032e3ec7017SPing-Ke Shih val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3033e3ec7017SPing-Ke Shih B_AX_WCPU_FWDL_STS_MASK); 3034e3ec7017SPing-Ke Shih 3035e3ec7017SPing-Ke Shih if (dlfw) 3036e3ec7017SPing-Ke Shih val |= B_AX_WCPU_FWDL_EN; 3037e3ec7017SPing-Ke Shih 3038e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3039e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3040e3ec7017SPing-Ke Shih boot_reason); 3041e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3042e3ec7017SPing-Ke Shih 3043e3ec7017SPing-Ke Shih if (!dlfw) { 3044e3ec7017SPing-Ke Shih mdelay(5); 3045e3ec7017SPing-Ke Shih 3046e3ec7017SPing-Ke Shih ret = rtw89_fw_check_rdy(rtwdev); 3047e3ec7017SPing-Ke Shih if (ret) 3048e3ec7017SPing-Ke Shih return ret; 3049e3ec7017SPing-Ke Shih } 3050e3ec7017SPing-Ke Shih 3051e3ec7017SPing-Ke Shih return 0; 3052e3ec7017SPing-Ke Shih } 3053e3ec7017SPing-Ke Shih 3054a7d82a7aSPing-Ke Shih static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3055e3ec7017SPing-Ke Shih { 3056a7d82a7aSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3057e3ec7017SPing-Ke Shih u32 val; 3058e3ec7017SPing-Ke Shih int ret; 3059e3ec7017SPing-Ke Shih 3060a7d82a7aSPing-Ke Shih if (chip_id == RTL8852C) 3061a7d82a7aSPing-Ke Shih val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3062a7d82a7aSPing-Ke Shih B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3063a7d82a7aSPing-Ke Shih else 3064e3ec7017SPing-Ke Shih val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3065e3ec7017SPing-Ke Shih B_AX_PKT_BUF_EN; 3066e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3067e3ec7017SPing-Ke Shih 3068e3ec7017SPing-Ke Shih val = B_AX_DISPATCHER_CLK_EN; 3069e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3070e3ec7017SPing-Ke Shih 3071a7d82a7aSPing-Ke Shih if (chip_id != RTL8852C) 3072a7d82a7aSPing-Ke Shih goto dle; 3073a7d82a7aSPing-Ke Shih 3074a7d82a7aSPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3075a7d82a7aSPing-Ke Shih val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3076a7d82a7aSPing-Ke Shih val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3077a7d82a7aSPing-Ke Shih B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3078a7d82a7aSPing-Ke Shih rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3079a7d82a7aSPing-Ke Shih 3080a7d82a7aSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3081a7d82a7aSPing-Ke Shih B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3082a7d82a7aSPing-Ke Shih B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3083a7d82a7aSPing-Ke Shih B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3084a7d82a7aSPing-Ke Shih B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3085a7d82a7aSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3086a7d82a7aSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3087a7d82a7aSPing-Ke Shih 3088a7d82a7aSPing-Ke Shih dle: 3089e3ec7017SPing-Ke Shih ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3090e3ec7017SPing-Ke Shih if (ret) { 3091e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3092e3ec7017SPing-Ke Shih return ret; 3093e3ec7017SPing-Ke Shih } 3094e3ec7017SPing-Ke Shih 3095e3ec7017SPing-Ke Shih ret = hfc_init(rtwdev, true, false, true); 3096e3ec7017SPing-Ke Shih if (ret) { 3097e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3098e3ec7017SPing-Ke Shih return ret; 3099e3ec7017SPing-Ke Shih } 3100e3ec7017SPing-Ke Shih 3101e3ec7017SPing-Ke Shih return ret; 3102e3ec7017SPing-Ke Shih } 3103e3ec7017SPing-Ke Shih 3104e3ec7017SPing-Ke Shih static void rtw89_mac_hci_func_en(struct rtw89_dev *rtwdev) 3105e3ec7017SPing-Ke Shih { 31062af64b4aSPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 31072af64b4aSPing-Ke Shih 31082af64b4aSPing-Ke Shih rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 3109e3ec7017SPing-Ke Shih B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 3110e3ec7017SPing-Ke Shih } 3111e3ec7017SPing-Ke Shih 311261ebeecbSPing-Ke Shih int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3113e3ec7017SPing-Ke Shih { 3114e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3115e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3116e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3117e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3118e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3119e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 312061ebeecbSPing-Ke Shih 312161ebeecbSPing-Ke Shih return 0; 3122e3ec7017SPing-Ke Shih } 312361ebeecbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3124e3ec7017SPing-Ke Shih 3125e3ec7017SPing-Ke Shih void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3126e3ec7017SPing-Ke Shih { 3127e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3128e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3129e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3130e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3131e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3132e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3133e3ec7017SPing-Ke Shih } 313461ebeecbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3135e3ec7017SPing-Ke Shih 3136e3ec7017SPing-Ke Shih int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) 3137e3ec7017SPing-Ke Shih { 3138e3ec7017SPing-Ke Shih int ret; 3139e3ec7017SPing-Ke Shih 3140e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 3141e3ec7017SPing-Ke Shih if (ret) { 3142e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 3143e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 3144e3ec7017SPing-Ke Shih if (ret) 3145e3ec7017SPing-Ke Shih return ret; 3146e3ec7017SPing-Ke Shih } 3147e3ec7017SPing-Ke Shih 3148e3ec7017SPing-Ke Shih rtw89_mac_hci_func_en(rtwdev); 3149e3ec7017SPing-Ke Shih 3150a7d82a7aSPing-Ke Shih ret = rtw89_mac_dmac_pre_init(rtwdev); 3151a7d82a7aSPing-Ke Shih if (ret) 3152a7d82a7aSPing-Ke Shih return ret; 3153a7d82a7aSPing-Ke Shih 3154e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_pre_init) { 3155e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3156e3ec7017SPing-Ke Shih if (ret) 3157e3ec7017SPing-Ke Shih return ret; 3158e3ec7017SPing-Ke Shih } 3159e3ec7017SPing-Ke Shih 3160e3ec7017SPing-Ke Shih rtw89_mac_disable_cpu(rtwdev); 3161e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_cpu(rtwdev, 0, true); 3162e3ec7017SPing-Ke Shih if (ret) 3163e3ec7017SPing-Ke Shih return ret; 3164e3ec7017SPing-Ke Shih 3165e3ec7017SPing-Ke Shih ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); 3166e3ec7017SPing-Ke Shih if (ret) 3167e3ec7017SPing-Ke Shih return ret; 3168e3ec7017SPing-Ke Shih 3169e3ec7017SPing-Ke Shih return 0; 3170e3ec7017SPing-Ke Shih } 3171e3ec7017SPing-Ke Shih 3172e3ec7017SPing-Ke Shih int rtw89_mac_init(struct rtw89_dev *rtwdev) 3173e3ec7017SPing-Ke Shih { 3174e3ec7017SPing-Ke Shih int ret; 3175e3ec7017SPing-Ke Shih 3176e3ec7017SPing-Ke Shih ret = rtw89_mac_partial_init(rtwdev); 3177e3ec7017SPing-Ke Shih if (ret) 3178e3ec7017SPing-Ke Shih goto fail; 3179e3ec7017SPing-Ke Shih 318061ebeecbSPing-Ke Shih ret = rtw89_chip_enable_bb_rf(rtwdev); 318161ebeecbSPing-Ke Shih if (ret) 318261ebeecbSPing-Ke Shih goto fail; 3183e3ec7017SPing-Ke Shih 3184e3ec7017SPing-Ke Shih ret = rtw89_mac_sys_init(rtwdev); 3185e3ec7017SPing-Ke Shih if (ret) 3186e3ec7017SPing-Ke Shih goto fail; 3187e3ec7017SPing-Ke Shih 3188e3ec7017SPing-Ke Shih ret = rtw89_mac_trx_init(rtwdev); 3189e3ec7017SPing-Ke Shih if (ret) 3190e3ec7017SPing-Ke Shih goto fail; 3191e3ec7017SPing-Ke Shih 3192e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_post_init) { 3193e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3194e3ec7017SPing-Ke Shih if (ret) 3195e3ec7017SPing-Ke Shih goto fail; 3196e3ec7017SPing-Ke Shih } 3197e3ec7017SPing-Ke Shih 3198e3ec7017SPing-Ke Shih rtw89_fw_send_all_early_h2c(rtwdev); 3199e3ec7017SPing-Ke Shih rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3200e3ec7017SPing-Ke Shih 3201e3ec7017SPing-Ke Shih return ret; 3202e3ec7017SPing-Ke Shih fail: 3203e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 3204e3ec7017SPing-Ke Shih 3205e3ec7017SPing-Ke Shih return ret; 3206e3ec7017SPing-Ke Shih } 3207e3ec7017SPing-Ke Shih 3208e3ec7017SPing-Ke Shih static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3209e3ec7017SPing-Ke Shih { 3210e3ec7017SPing-Ke Shih u8 i; 3211e3ec7017SPing-Ke Shih 3212e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 3213e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3214e3ec7017SPing-Ke Shih DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3215e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3216e3ec7017SPing-Ke Shih } 3217e3ec7017SPing-Ke Shih } 3218e3ec7017SPing-Ke Shih 3219e3ec7017SPing-Ke Shih static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3220e3ec7017SPing-Ke Shih { 3221e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3222e3ec7017SPing-Ke Shih CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3223e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3224e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3225e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3226e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3227e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3228e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3229e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3230e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3231e3ec7017SPing-Ke Shih } 3232e3ec7017SPing-Ke Shih 32331b73e77dSPing-Ke Shih int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3234e3ec7017SPing-Ke Shih { 3235e3ec7017SPing-Ke Shih u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3236e3ec7017SPing-Ke Shih u8 grp = macid >> 5; 3237e3ec7017SPing-Ke Shih int ret; 3238e3ec7017SPing-Ke Shih 3239e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3240e3ec7017SPing-Ke Shih if (ret) 3241e3ec7017SPing-Ke Shih return ret; 3242e3ec7017SPing-Ke Shih 3243e3ec7017SPing-Ke Shih rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3244e3ec7017SPing-Ke Shih 3245e3ec7017SPing-Ke Shih return 0; 3246e3ec7017SPing-Ke Shih } 3247e3ec7017SPing-Ke Shih 3248e3ec7017SPing-Ke Shih static const struct rtw89_port_reg rtw_port_base = { 3249e3ec7017SPing-Ke Shih .port_cfg = R_AX_PORT_CFG_P0, 3250e3ec7017SPing-Ke Shih .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3251e3ec7017SPing-Ke Shih .bcn_area = R_AX_BCN_AREA_P0, 3252e3ec7017SPing-Ke Shih .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3253e3ec7017SPing-Ke Shih .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3254e3ec7017SPing-Ke Shih .tbtt_agg = R_AX_TBTT_AGG_P0, 3255e3ec7017SPing-Ke Shih .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3256e3ec7017SPing-Ke Shih .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3257e3ec7017SPing-Ke Shih .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3258e3ec7017SPing-Ke Shih .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3259e3ec7017SPing-Ke Shih .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3260e3ec7017SPing-Ke Shih .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3261e3ec7017SPing-Ke Shih .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3262e3ec7017SPing-Ke Shih .tsftr_l = R_AX_TSFTR_LOW_P0, 3263e3ec7017SPing-Ke Shih .tsftr_h = R_AX_TSFTR_HIGH_P0 3264e3ec7017SPing-Ke Shih }; 3265e3ec7017SPing-Ke Shih 3266e3ec7017SPing-Ke Shih #define BCN_INTERVAL 100 3267e3ec7017SPing-Ke Shih #define BCN_ERLY_DEF 160 3268e3ec7017SPing-Ke Shih #define BCN_SETUP_DEF 2 3269e3ec7017SPing-Ke Shih #define BCN_HOLD_DEF 200 3270e3ec7017SPing-Ke Shih #define BCN_MASK_DEF 0 3271e3ec7017SPing-Ke Shih #define TBTT_ERLY_DEF 5 3272e3ec7017SPing-Ke Shih #define BCN_SET_UNIT 32 3273e3ec7017SPing-Ke Shih #define BCN_ERLY_SET_DLY (10 * 2) 3274e3ec7017SPing-Ke Shih 3275e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3276e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3277e3ec7017SPing-Ke Shih { 3278e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3279e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3280e3ec7017SPing-Ke Shih 3281e3ec7017SPing-Ke Shih if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3282e3ec7017SPing-Ke Shih return; 3283e3ec7017SPing-Ke Shih 3284e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3285e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3286e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3287e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3288e3ec7017SPing-Ke Shih 3289e3ec7017SPing-Ke Shih msleep(vif->bss_conf.beacon_int + 1); 3290e3ec7017SPing-Ke Shih 3291e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3292e3ec7017SPing-Ke Shih B_AX_BRK_SETUP); 3293e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3294e3ec7017SPing-Ke Shih rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3295e3ec7017SPing-Ke Shih } 3296e3ec7017SPing-Ke Shih 3297e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3298e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 3299e3ec7017SPing-Ke Shih { 3300e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3301e3ec7017SPing-Ke Shih 3302e3ec7017SPing-Ke Shih if (en) 3303e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3304e3ec7017SPing-Ke Shih else 3305e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3306e3ec7017SPing-Ke Shih } 3307e3ec7017SPing-Ke Shih 3308e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3309e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 3310e3ec7017SPing-Ke Shih { 3311e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3312e3ec7017SPing-Ke Shih 3313e3ec7017SPing-Ke Shih if (en) 3314e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3315e3ec7017SPing-Ke Shih else 3316e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3317e3ec7017SPing-Ke Shih } 3318e3ec7017SPing-Ke Shih 3319e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3320e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3321e3ec7017SPing-Ke Shih { 3322e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3323e3ec7017SPing-Ke Shih 3324e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3325e3ec7017SPing-Ke Shih rtwvif->net_type); 3326e3ec7017SPing-Ke Shih } 3327e3ec7017SPing-Ke Shih 3328e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3329e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3330e3ec7017SPing-Ke Shih { 3331e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3332e3ec7017SPing-Ke Shih bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3333e3ec7017SPing-Ke Shih u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3334e3ec7017SPing-Ke Shih 3335e3ec7017SPing-Ke Shih if (en) 3336e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3337e3ec7017SPing-Ke Shih else 3338e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3339e3ec7017SPing-Ke Shih } 3340e3ec7017SPing-Ke Shih 3341e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3342e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3343e3ec7017SPing-Ke Shih { 3344e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3345e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3346e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3347e3ec7017SPing-Ke Shih u32 bit = B_AX_RX_BSSID_FIT_EN; 3348e3ec7017SPing-Ke Shih 3349e3ec7017SPing-Ke Shih if (en) 3350e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3351e3ec7017SPing-Ke Shih else 3352e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3353e3ec7017SPing-Ke Shih } 3354e3ec7017SPing-Ke Shih 3355e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3356e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3357e3ec7017SPing-Ke Shih { 3358e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3359e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3360e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3361e3ec7017SPing-Ke Shih 3362e3ec7017SPing-Ke Shih if (en) 3363e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3364e3ec7017SPing-Ke Shih else 3365e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3366e3ec7017SPing-Ke Shih } 3367e3ec7017SPing-Ke Shih 3368e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3369e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3370e3ec7017SPing-Ke Shih { 3371e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3372e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3373e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3374e3ec7017SPing-Ke Shih 3375e3ec7017SPing-Ke Shih if (en) 3376e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3377e3ec7017SPing-Ke Shih else 3378e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3379e3ec7017SPing-Ke Shih } 3380e3ec7017SPing-Ke Shih 3381e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3382e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3383e3ec7017SPing-Ke Shih { 3384e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3385e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3386e3ec7017SPing-Ke Shih u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3387e3ec7017SPing-Ke Shih 3388e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3389e3ec7017SPing-Ke Shih bcn_int); 3390e3ec7017SPing-Ke Shih } 3391e3ec7017SPing-Ke Shih 3392283c3d88SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3393283c3d88SPing-Ke Shih struct rtw89_vif *rtwvif) 3394283c3d88SPing-Ke Shih { 3395283c3d88SPing-Ke Shih static const u32 hiq_win_addr[RTW89_PORT_NUM] = { 3396283c3d88SPing-Ke Shih R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3397283c3d88SPing-Ke Shih R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3398283c3d88SPing-Ke Shih R_AX_PORT_HGQ_WINDOW_CFG + 3, 3399283c3d88SPing-Ke Shih }; 3400283c3d88SPing-Ke Shih u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3401283c3d88SPing-Ke Shih u8 port = rtwvif->port; 3402283c3d88SPing-Ke Shih u32 reg; 3403283c3d88SPing-Ke Shih 3404283c3d88SPing-Ke Shih reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx); 3405283c3d88SPing-Ke Shih rtw89_write8(rtwdev, reg, win); 3406283c3d88SPing-Ke Shih } 3407283c3d88SPing-Ke Shih 3408283c3d88SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3409283c3d88SPing-Ke Shih struct rtw89_vif *rtwvif) 3410283c3d88SPing-Ke Shih { 3411283c3d88SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3412283c3d88SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3413283c3d88SPing-Ke Shih u32 addr; 3414283c3d88SPing-Ke Shih 3415283c3d88SPing-Ke Shih addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); 3416283c3d88SPing-Ke Shih rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3417283c3d88SPing-Ke Shih 3418283c3d88SPing-Ke Shih rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3419283c3d88SPing-Ke Shih vif->bss_conf.dtim_period); 3420283c3d88SPing-Ke Shih } 3421283c3d88SPing-Ke Shih 3422e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3423e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3424e3ec7017SPing-Ke Shih { 3425e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3426e3ec7017SPing-Ke Shih 3427e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3428e3ec7017SPing-Ke Shih B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3429e3ec7017SPing-Ke Shih } 3430e3ec7017SPing-Ke Shih 3431e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3432e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3433e3ec7017SPing-Ke Shih { 3434e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3435e3ec7017SPing-Ke Shih 3436e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3437e3ec7017SPing-Ke Shih B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3438e3ec7017SPing-Ke Shih } 3439e3ec7017SPing-Ke Shih 3440e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3441e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3442e3ec7017SPing-Ke Shih { 3443e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3444e3ec7017SPing-Ke Shih 3445e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3446e3ec7017SPing-Ke Shih B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3447e3ec7017SPing-Ke Shih } 3448e3ec7017SPing-Ke Shih 3449e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3450e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3451e3ec7017SPing-Ke Shih { 3452e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3453e3ec7017SPing-Ke Shih 3454e3ec7017SPing-Ke Shih rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3455e3ec7017SPing-Ke Shih B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3456e3ec7017SPing-Ke Shih } 3457e3ec7017SPing-Ke Shih 3458e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3459e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3460e3ec7017SPing-Ke Shih { 3461e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3462e3ec7017SPing-Ke Shih static const u32 masks[RTW89_PORT_NUM] = { 3463e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3464e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3465e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_4_MASK, 3466e3ec7017SPing-Ke Shih }; 3467e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3468e3ec7017SPing-Ke Shih u32 reg_base; 3469e3ec7017SPing-Ke Shih u32 reg; 3470e3ec7017SPing-Ke Shih u8 bss_color; 3471e3ec7017SPing-Ke Shih 3472e3ec7017SPing-Ke Shih bss_color = vif->bss_conf.he_bss_color.color; 3473e3ec7017SPing-Ke Shih reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; 3474e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); 3475e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3476e3ec7017SPing-Ke Shih } 3477e3ec7017SPing-Ke Shih 3478e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3479e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3480e3ec7017SPing-Ke Shih { 3481e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3482e3ec7017SPing-Ke Shih u32 reg; 3483e3ec7017SPing-Ke Shih 3484e3ec7017SPing-Ke Shih if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3485e3ec7017SPing-Ke Shih return; 3486e3ec7017SPing-Ke Shih 3487e3ec7017SPing-Ke Shih if (port == 0) { 3488e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); 3489e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3490e3ec7017SPing-Ke Shih } 3491e3ec7017SPing-Ke Shih } 3492e3ec7017SPing-Ke Shih 3493e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3494e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3495e3ec7017SPing-Ke Shih { 3496e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3497e3ec7017SPing-Ke Shih u32 reg; 3498e3ec7017SPing-Ke Shih u32 val; 3499e3ec7017SPing-Ke Shih 3500e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); 3501e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 3502e3ec7017SPing-Ke Shih val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 3503e3ec7017SPing-Ke Shih if (port == 0) 3504e3ec7017SPing-Ke Shih val &= ~BIT(0); 3505e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 3506e3ec7017SPing-Ke Shih } 3507e3ec7017SPing-Ke Shih 3508e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 3509e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3510e3ec7017SPing-Ke Shih { 3511e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3512e3ec7017SPing-Ke Shih 3513e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN); 3514e3ec7017SPing-Ke Shih } 3515e3ec7017SPing-Ke Shih 3516e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 3517e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3518e3ec7017SPing-Ke Shih { 3519e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 3520e3ec7017SPing-Ke Shih 3521e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 3522e3ec7017SPing-Ke Shih BCN_ERLY_DEF); 3523e3ec7017SPing-Ke Shih } 3524e3ec7017SPing-Ke Shih 3525e3ec7017SPing-Ke Shih int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3526e3ec7017SPing-Ke Shih { 3527e3ec7017SPing-Ke Shih int ret; 3528e3ec7017SPing-Ke Shih 3529e3ec7017SPing-Ke Shih ret = rtw89_mac_port_update(rtwdev, rtwvif); 3530e3ec7017SPing-Ke Shih if (ret) 3531e3ec7017SPing-Ke Shih return ret; 3532e3ec7017SPing-Ke Shih 3533e3ec7017SPing-Ke Shih rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 3534e3ec7017SPing-Ke Shih rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 3535e3ec7017SPing-Ke Shih 35361b73e77dSPing-Ke Shih ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 3537e3ec7017SPing-Ke Shih if (ret) 3538e3ec7017SPing-Ke Shih return ret; 3539e3ec7017SPing-Ke Shih 3540ff66964aSPing-Ke Shih ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 3541e3ec7017SPing-Ke Shih if (ret) 3542e3ec7017SPing-Ke Shih return ret; 3543e3ec7017SPing-Ke Shih 3544e3ec7017SPing-Ke Shih ret = rtw89_cam_init(rtwdev, rtwvif); 3545e3ec7017SPing-Ke Shih if (ret) 3546e3ec7017SPing-Ke Shih return ret; 3547e3ec7017SPing-Ke Shih 354840822e07SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3549e3ec7017SPing-Ke Shih if (ret) 3550e3ec7017SPing-Ke Shih return ret; 3551e3ec7017SPing-Ke Shih 3552742c470bSPing-Ke Shih ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 3553e3ec7017SPing-Ke Shih if (ret) 3554e3ec7017SPing-Ke Shih return ret; 3555e3ec7017SPing-Ke Shih 3556e3ec7017SPing-Ke Shih return 0; 3557e3ec7017SPing-Ke Shih } 3558e3ec7017SPing-Ke Shih 3559e3ec7017SPing-Ke Shih int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3560e3ec7017SPing-Ke Shih { 3561e3ec7017SPing-Ke Shih int ret; 3562e3ec7017SPing-Ke Shih 3563ff66964aSPing-Ke Shih ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 3564e3ec7017SPing-Ke Shih if (ret) 3565e3ec7017SPing-Ke Shih return ret; 3566e3ec7017SPing-Ke Shih 3567e3ec7017SPing-Ke Shih rtw89_cam_deinit(rtwdev, rtwvif); 3568e3ec7017SPing-Ke Shih 356940822e07SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3570e3ec7017SPing-Ke Shih if (ret) 3571e3ec7017SPing-Ke Shih return ret; 3572e3ec7017SPing-Ke Shih 3573e3ec7017SPing-Ke Shih return 0; 3574e3ec7017SPing-Ke Shih } 3575e3ec7017SPing-Ke Shih 3576e3ec7017SPing-Ke Shih int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3577e3ec7017SPing-Ke Shih { 3578e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3579e3ec7017SPing-Ke Shih 3580e3ec7017SPing-Ke Shih if (port >= RTW89_PORT_NUM) 3581e3ec7017SPing-Ke Shih return -EINVAL; 3582e3ec7017SPing-Ke Shih 3583e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 3584e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 3585e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 3586e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 3587e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 3588e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 3589e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 3590e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 3591e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 3592283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 3593283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 3594283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 3595e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 3596e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 3597e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 3598e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 3599e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 3600e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 3601e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_func_en(rtwdev, rtwvif); 3602e3ec7017SPing-Ke Shih fsleep(BCN_ERLY_SET_DLY); 3603e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 3604e3ec7017SPing-Ke Shih 3605e3ec7017SPing-Ke Shih return 0; 3606e3ec7017SPing-Ke Shih } 3607e3ec7017SPing-Ke Shih 3608e3ec7017SPing-Ke Shih int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3609e3ec7017SPing-Ke Shih { 3610e3ec7017SPing-Ke Shih int ret; 3611e3ec7017SPing-Ke Shih 3612e3ec7017SPing-Ke Shih rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 3613e3ec7017SPing-Ke Shih RTW89_MAX_MAC_ID_NUM); 3614e3ec7017SPing-Ke Shih if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 3615e3ec7017SPing-Ke Shih return -ENOSPC; 3616e3ec7017SPing-Ke Shih 3617e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_init(rtwdev, rtwvif); 3618e3ec7017SPing-Ke Shih if (ret) 3619e3ec7017SPing-Ke Shih goto release_mac_id; 3620e3ec7017SPing-Ke Shih 3621e3ec7017SPing-Ke Shih return 0; 3622e3ec7017SPing-Ke Shih 3623e3ec7017SPing-Ke Shih release_mac_id: 3624e3ec7017SPing-Ke Shih rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 3625e3ec7017SPing-Ke Shih 3626e3ec7017SPing-Ke Shih return ret; 3627e3ec7017SPing-Ke Shih } 3628e3ec7017SPing-Ke Shih 3629e3ec7017SPing-Ke Shih int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3630e3ec7017SPing-Ke Shih { 3631e3ec7017SPing-Ke Shih int ret; 3632e3ec7017SPing-Ke Shih 3633e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 3634e3ec7017SPing-Ke Shih rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 3635e3ec7017SPing-Ke Shih 3636e3ec7017SPing-Ke Shih return ret; 3637e3ec7017SPing-Ke Shih } 3638e3ec7017SPing-Ke Shih 3639e3ec7017SPing-Ke Shih static void 3640e3ec7017SPing-Ke Shih rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3641e3ec7017SPing-Ke Shih { 3642e3ec7017SPing-Ke Shih } 3643e3ec7017SPing-Ke Shih 364489590777SPo Hao Huang static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 364589590777SPo Hao Huang { 364689590777SPo Hao Huang struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 364789590777SPo Hao Huang 364889590777SPo Hao Huang return band == scan_info->op_band && channel == scan_info->op_pri_ch; 364989590777SPo Hao Huang } 365089590777SPo Hao Huang 365189590777SPo Hao Huang static void 365289590777SPo Hao Huang rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 365389590777SPo Hao Huang u32 len) 365489590777SPo Hao Huang { 365589590777SPo Hao Huang struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 365689590777SPo Hao Huang struct rtw89_hal *hal = &rtwdev->hal; 365789590777SPo Hao Huang u8 reason, status, tx_fail, band; 365889590777SPo Hao Huang u16 chan; 365989590777SPo Hao Huang 366089590777SPo Hao Huang tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 366189590777SPo Hao Huang status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 366289590777SPo Hao Huang chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 366389590777SPo Hao Huang reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 366489590777SPo Hao Huang band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 366589590777SPo Hao Huang 366689590777SPo Hao Huang if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 366789590777SPo Hao Huang band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 366889590777SPo Hao Huang 366989590777SPo Hao Huang rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 367089590777SPo Hao Huang "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d\n", 367189590777SPo Hao Huang band, chan, reason, status, tx_fail); 367289590777SPo Hao Huang 367389590777SPo Hao Huang switch (reason) { 367489590777SPo Hao Huang case RTW89_SCAN_LEAVE_CH_NOTIFY: 367589590777SPo Hao Huang if (rtw89_is_op_chan(rtwdev, band, chan)) 367689590777SPo Hao Huang ieee80211_stop_queues(rtwdev->hw); 367789590777SPo Hao Huang return; 367889590777SPo Hao Huang case RTW89_SCAN_END_SCAN_NOTIFY: 367989590777SPo Hao Huang rtw89_hw_scan_complete(rtwdev, vif, false); 368089590777SPo Hao Huang break; 368189590777SPo Hao Huang case RTW89_SCAN_ENTER_CH_NOTIFY: 368289590777SPo Hao Huang if (rtw89_is_op_chan(rtwdev, band, chan)) 368389590777SPo Hao Huang ieee80211_wake_queues(rtwdev->hw); 368489590777SPo Hao Huang break; 368589590777SPo Hao Huang default: 368689590777SPo Hao Huang return; 368789590777SPo Hao Huang } 368889590777SPo Hao Huang 368989590777SPo Hao Huang hal->prev_band_type = hal->current_band_type; 369089590777SPo Hao Huang hal->prev_primary_channel = hal->current_channel; 369189590777SPo Hao Huang hal->current_channel = chan; 369289590777SPo Hao Huang hal->current_band_type = band; 369389590777SPo Hao Huang } 369489590777SPo Hao Huang 3695e3ec7017SPing-Ke Shih static void 3696e3ec7017SPing-Ke Shih rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3697e3ec7017SPing-Ke Shih { 3698e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 3699e3ec7017SPing-Ke Shih "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 3700e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 3701e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 3702e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 3703e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 3704e3ec7017SPing-Ke Shih } 3705e3ec7017SPing-Ke Shih 3706e3ec7017SPing-Ke Shih static void 3707e3ec7017SPing-Ke Shih rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3708e3ec7017SPing-Ke Shih { 3709e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 3710e3ec7017SPing-Ke Shih "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 3711e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data), 3712e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data), 3713e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data), 3714e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data), 3715e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data)); 3716e3ec7017SPing-Ke Shih } 3717e3ec7017SPing-Ke Shih 3718e3ec7017SPing-Ke Shih static void 3719e3ec7017SPing-Ke Shih rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3720e3ec7017SPing-Ke Shih { 3721e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), 3722e3ec7017SPing-Ke Shih RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); 3723e3ec7017SPing-Ke Shih } 3724e3ec7017SPing-Ke Shih 3725fccca934SPing-Ke Shih static void 3726fccca934SPing-Ke Shih rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3727fccca934SPing-Ke Shih { 3728fccca934SPing-Ke Shih } 3729fccca934SPing-Ke Shih 37302b8219e9SPo Hao Huang static void 37312b8219e9SPo Hao Huang rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 37322b8219e9SPo Hao Huang u32 len) 37332b8219e9SPo Hao Huang { 37342b8219e9SPo Hao Huang } 37352b8219e9SPo Hao Huang 3736e3ec7017SPing-Ke Shih static 3737e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 3738e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 3739e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 3740e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 37412b8219e9SPo Hao Huang [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 3742e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 3743e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 374489590777SPo Hao Huang [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 3745e3ec7017SPing-Ke Shih }; 3746e3ec7017SPing-Ke Shih 3747e3ec7017SPing-Ke Shih static 3748e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 3749e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 3750e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 3751e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 3752e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 3753fccca934SPing-Ke Shih [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 3754e3ec7017SPing-Ke Shih }; 3755e3ec7017SPing-Ke Shih 3756e3ec7017SPing-Ke Shih void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3757e3ec7017SPing-Ke Shih u32 len, u8 class, u8 func) 3758e3ec7017SPing-Ke Shih { 3759e3ec7017SPing-Ke Shih void (*handler)(struct rtw89_dev *rtwdev, 3760e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = NULL; 3761e3ec7017SPing-Ke Shih 3762e3ec7017SPing-Ke Shih switch (class) { 3763e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_INFO: 3764e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 3765e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_info_handler[func]; 3766e3ec7017SPing-Ke Shih break; 3767e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_OFLD: 3768e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 3769e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_ofld_handler[func]; 3770e3ec7017SPing-Ke Shih break; 3771e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_FWDBG: 3772e3ec7017SPing-Ke Shih return; 3773e3ec7017SPing-Ke Shih default: 3774e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d not support\n", class); 3775e3ec7017SPing-Ke Shih return; 3776e3ec7017SPing-Ke Shih } 3777e3ec7017SPing-Ke Shih if (!handler) { 3778e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 3779e3ec7017SPing-Ke Shih func); 3780e3ec7017SPing-Ke Shih return; 3781e3ec7017SPing-Ke Shih } 3782e3ec7017SPing-Ke Shih handler(rtwdev, skb, len); 3783e3ec7017SPing-Ke Shih } 3784e3ec7017SPing-Ke Shih 3785e3ec7017SPing-Ke Shih bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 3786e3ec7017SPing-Ke Shih enum rtw89_phy_idx phy_idx, 3787e3ec7017SPing-Ke Shih u32 reg_base, u32 *cr) 3788e3ec7017SPing-Ke Shih { 3789e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 3790e3ec7017SPing-Ke Shih enum rtw89_qta_mode mode = dle_mem->mode; 3791e3ec7017SPing-Ke Shih u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); 3792e3ec7017SPing-Ke Shih 3793e3ec7017SPing-Ke Shih if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { 3794e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 3795e3ec7017SPing-Ke Shih addr); 3796e3ec7017SPing-Ke Shih goto error; 3797e3ec7017SPing-Ke Shih } 3798e3ec7017SPing-Ke Shih 3799e3ec7017SPing-Ke Shih if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) 3800e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_SCC) { 3801e3ec7017SPing-Ke Shih rtw89_err(rtwdev, 3802e3ec7017SPing-Ke Shih "[TXPWR] addr=0x%x but hw not enable\n", 3803e3ec7017SPing-Ke Shih addr); 3804e3ec7017SPing-Ke Shih goto error; 3805e3ec7017SPing-Ke Shih } 3806e3ec7017SPing-Ke Shih 3807e3ec7017SPing-Ke Shih *cr = addr; 3808e3ec7017SPing-Ke Shih return true; 3809e3ec7017SPing-Ke Shih 3810e3ec7017SPing-Ke Shih error: 3811e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 3812e3ec7017SPing-Ke Shih addr, phy_idx); 3813e3ec7017SPing-Ke Shih 3814e3ec7017SPing-Ke Shih return false; 3815e3ec7017SPing-Ke Shih } 3816861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); 3817e3ec7017SPing-Ke Shih 3818e3ec7017SPing-Ke Shih int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 3819e3ec7017SPing-Ke Shih { 3820e3ec7017SPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); 3821e3ec7017SPing-Ke Shih int ret = 0; 3822e3ec7017SPing-Ke Shih 3823e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3824e3ec7017SPing-Ke Shih if (ret) 3825e3ec7017SPing-Ke Shih return ret; 3826e3ec7017SPing-Ke Shih 3827e3ec7017SPing-Ke Shih if (!enable) { 3828e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 3829e3ec7017SPing-Ke Shih return ret; 3830e3ec7017SPing-Ke Shih } 3831e3ec7017SPing-Ke Shih 3832e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 3833e3ec7017SPing-Ke Shih B_AX_APP_MAC_INFO_RPT | 3834e3ec7017SPing-Ke Shih B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 3835e3ec7017SPing-Ke Shih B_AX_PPDU_STAT_RPT_CRC32); 3836e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 3837e3ec7017SPing-Ke Shih RTW89_PRPT_DEST_HOST); 3838e3ec7017SPing-Ke Shih 3839e3ec7017SPing-Ke Shih return ret; 3840e3ec7017SPing-Ke Shih } 3841861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 3842e3ec7017SPing-Ke Shih 3843e3ec7017SPing-Ke Shih void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 3844e3ec7017SPing-Ke Shih { 3845e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_SH 5 3846e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_SH 4 3847e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_MAX 255 3848e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_MAX 255 3849e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_DEF 88 3850e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_DEF 4080 3851e3ec7017SPing-Ke Shih struct ieee80211_hw *hw = rtwdev->hw; 3852e3ec7017SPing-Ke Shih u32 rts_threshold = hw->wiphy->rts_threshold; 3853e3ec7017SPing-Ke Shih u32 time_th, len_th; 3854e3ec7017SPing-Ke Shih u32 reg; 3855e3ec7017SPing-Ke Shih 3856e3ec7017SPing-Ke Shih if (rts_threshold == (u32)-1) { 3857e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_DEF; 3858e3ec7017SPing-Ke Shih len_th = MAC_AX_LEN_TH_DEF; 3859e3ec7017SPing-Ke Shih } else { 3860e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 3861e3ec7017SPing-Ke Shih len_th = rts_threshold; 3862e3ec7017SPing-Ke Shih } 3863e3ec7017SPing-Ke Shih 3864e3ec7017SPing-Ke Shih time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 3865e3ec7017SPing-Ke Shih len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 3866e3ec7017SPing-Ke Shih 3867e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); 3868e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 3869e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 3870e3ec7017SPing-Ke Shih } 3871e3ec7017SPing-Ke Shih 3872e3ec7017SPing-Ke Shih void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 3873e3ec7017SPing-Ke Shih { 3874e3ec7017SPing-Ke Shih bool empty; 3875e3ec7017SPing-Ke Shih int ret; 3876e3ec7017SPing-Ke Shih 3877e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3878e3ec7017SPing-Ke Shih return; 3879e3ec7017SPing-Ke Shih 3880e3ec7017SPing-Ke Shih ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 3881e3ec7017SPing-Ke Shih 10000, 200000, false, rtwdev); 3882e3ec7017SPing-Ke Shih if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 3883e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "timed out to flush queues\n"); 3884e3ec7017SPing-Ke Shih } 3885e3ec7017SPing-Ke Shih 3886e3ec7017SPing-Ke Shih int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 3887e3ec7017SPing-Ke Shih { 3888e3ec7017SPing-Ke Shih u8 val; 3889e3ec7017SPing-Ke Shih u16 val16; 3890e3ec7017SPing-Ke Shih u32 val32; 3891e3ec7017SPing-Ke Shih int ret; 3892e3ec7017SPing-Ke Shih 3893e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 3894e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 3895e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 3896e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 3897e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 3898e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 3899e3ec7017SPing-Ke Shih 3900e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 3901e3ec7017SPing-Ke Shih val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 3902e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 3903e3ec7017SPing-Ke Shih 3904e3ec7017SPing-Ke Shih ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 3905e3ec7017SPing-Ke Shih if (ret) { 3906e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 3907e3ec7017SPing-Ke Shih return ret; 3908e3ec7017SPing-Ke Shih } 3909e3ec7017SPing-Ke Shih val32 = val32 & B_AX_WL_RX_CTRL; 3910e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 3911e3ec7017SPing-Ke Shih if (ret) { 3912e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 3913e3ec7017SPing-Ke Shih return ret; 3914e3ec7017SPing-Ke Shih } 3915e3ec7017SPing-Ke Shih 3916e3ec7017SPing-Ke Shih switch (coex->pta_mode) { 3917e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_RTK_MODE: 3918e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 3919e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 3920e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 3921e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 3922e3ec7017SPing-Ke Shih 3923e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 3924e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 3925e3ec7017SPing-Ke Shih 3926e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 3927e3ec7017SPing-Ke Shih val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 3928e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 3929e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 3930e3ec7017SPing-Ke Shih break; 3931e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_CSR_MODE: 3932e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 3933e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 3934e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 3935e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 3936e3ec7017SPing-Ke Shih 3937e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 3938e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 3939e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 3940e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 3941e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 3942e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_STAT_DELAY_MASK; 3943e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 3944e3ec7017SPing-Ke Shih val16 |= B_AX_ENHANCED_BT; 3945e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 3946e3ec7017SPing-Ke Shih 3947e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 3948e3ec7017SPing-Ke Shih break; 3949e3ec7017SPing-Ke Shih default: 3950e3ec7017SPing-Ke Shih return -EINVAL; 3951e3ec7017SPing-Ke Shih } 3952e3ec7017SPing-Ke Shih 3953e3ec7017SPing-Ke Shih switch (coex->direction) { 3954e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INNER: 3955e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3956e3ec7017SPing-Ke Shih val = (val & ~BIT(2)) | BIT(1); 3957e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3958e3ec7017SPing-Ke Shih break; 3959e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_OUTPUT: 3960e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3961e3ec7017SPing-Ke Shih val = val | BIT(1) | BIT(0); 3962e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3963e3ec7017SPing-Ke Shih break; 3964e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INPUT: 3965e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3966e3ec7017SPing-Ke Shih val = val & ~(BIT(2) | BIT(1)); 3967e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3968e3ec7017SPing-Ke Shih break; 3969e3ec7017SPing-Ke Shih default: 3970e3ec7017SPing-Ke Shih return -EINVAL; 3971e3ec7017SPing-Ke Shih } 3972e3ec7017SPing-Ke Shih 3973e3ec7017SPing-Ke Shih return 0; 3974e3ec7017SPing-Ke Shih } 3975861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_coex_init); 3976e3ec7017SPing-Ke Shih 3977065cf8f9SChia-Yuan Li int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 3978065cf8f9SChia-Yuan Li const struct rtw89_mac_ax_coex *coex) 3979065cf8f9SChia-Yuan Li { 3980065cf8f9SChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 3981065cf8f9SChia-Yuan Li B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 3982065cf8f9SChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 3983065cf8f9SChia-Yuan Li rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 3984065cf8f9SChia-Yuan Li rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 3985065cf8f9SChia-Yuan Li 3986065cf8f9SChia-Yuan Li switch (coex->pta_mode) { 3987065cf8f9SChia-Yuan Li case RTW89_MAC_AX_COEX_RTK_MODE: 3988065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 3989065cf8f9SChia-Yuan Li MAC_AX_RTK_MODE); 3990065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 3991065cf8f9SChia-Yuan Li B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 3992065cf8f9SChia-Yuan Li break; 3993065cf8f9SChia-Yuan Li case RTW89_MAC_AX_COEX_CSR_MODE: 3994065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 3995065cf8f9SChia-Yuan Li MAC_AX_CSR_MODE); 3996065cf8f9SChia-Yuan Li break; 3997065cf8f9SChia-Yuan Li default: 3998065cf8f9SChia-Yuan Li return -EINVAL; 3999065cf8f9SChia-Yuan Li } 4000065cf8f9SChia-Yuan Li 4001065cf8f9SChia-Yuan Li return 0; 4002065cf8f9SChia-Yuan Li } 4003065cf8f9SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 4004065cf8f9SChia-Yuan Li 4005e3ec7017SPing-Ke Shih int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4006e3ec7017SPing-Ke Shih const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4007e3ec7017SPing-Ke Shih { 40088001c741SPing-Ke Shih u32 val = 0, ret; 4009e3ec7017SPing-Ke Shih 40108001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_bt) 40118001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 40128001c741SPing-Ke Shih 40138001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_bt_sw_en) 40148001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 40158001c741SPing-Ke Shih 40168001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_wl) 40178001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 40188001c741SPing-Ke Shih 40198001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_wl_sw_en) 40208001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 40218001c741SPing-Ke Shih 40228001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_bt) 40238001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 40248001c741SPing-Ke Shih 40258001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_bt_sw_en) 40268001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 40278001c741SPing-Ke Shih 40288001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_wl) 40298001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 40308001c741SPing-Ke Shih 40318001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_wl_sw_en) 40328001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 40338001c741SPing-Ke Shih 4034e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 4035e3ec7017SPing-Ke Shih if (ret) { 4036e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write LTE fail!\n"); 4037e3ec7017SPing-Ke Shih return ret; 4038e3ec7017SPing-Ke Shih } 4039e3ec7017SPing-Ke Shih 4040e3ec7017SPing-Ke Shih return 0; 4041e3ec7017SPing-Ke Shih } 4042feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 4043feed6541SChia-Yuan Li 4044feed6541SChia-Yuan Li int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 4045feed6541SChia-Yuan Li const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4046feed6541SChia-Yuan Li { 4047feed6541SChia-Yuan Li u32 val = 0; 4048feed6541SChia-Yuan Li 4049feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_bt) 4050feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 4051feed6541SChia-Yuan Li B_AX_GNT_BT_TX_VAL; 4052feed6541SChia-Yuan Li else 4053feed6541SChia-Yuan Li val |= B_AX_WL_ACT_VAL; 4054feed6541SChia-Yuan Li 4055feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_bt_sw_en) 4056feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4057feed6541SChia-Yuan Li B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4058feed6541SChia-Yuan Li 4059feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_wl) 4060feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 4061feed6541SChia-Yuan Li B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4062feed6541SChia-Yuan Li 4063feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_wl_sw_en) 4064feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4065feed6541SChia-Yuan Li B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4066feed6541SChia-Yuan Li 4067feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_bt) 4068feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 4069feed6541SChia-Yuan Li B_AX_GNT_BT_TX_VAL; 4070feed6541SChia-Yuan Li else 4071feed6541SChia-Yuan Li val |= B_AX_WL_ACT_VAL; 4072feed6541SChia-Yuan Li 4073feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_bt_sw_en) 4074feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4075feed6541SChia-Yuan Li B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4076feed6541SChia-Yuan Li 4077feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_wl) 4078feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 4079feed6541SChia-Yuan Li B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4080feed6541SChia-Yuan Li 4081feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_wl_sw_en) 4082feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4083feed6541SChia-Yuan Li B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4084feed6541SChia-Yuan Li 4085feed6541SChia-Yuan Li rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 4086feed6541SChia-Yuan Li 4087feed6541SChia-Yuan Li return 0; 4088feed6541SChia-Yuan Li } 4089feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 4090e3ec7017SPing-Ke Shih 4091e3ec7017SPing-Ke Shih int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 4092e3ec7017SPing-Ke Shih { 4093e3ec7017SPing-Ke Shih u32 reg; 409428e7ea8aSPing-Ke Shih u16 val; 4095e3ec7017SPing-Ke Shih int ret; 4096e3ec7017SPing-Ke Shih 4097e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 4098e3ec7017SPing-Ke Shih if (ret) 4099e3ec7017SPing-Ke Shih return ret; 4100e3ec7017SPing-Ke Shih 4101e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); 4102e3ec7017SPing-Ke Shih val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 4103e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 4104e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 4105e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 4106e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 4107e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 4108e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 410928e7ea8aSPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 411028e7ea8aSPing-Ke Shih B_AX_PLT_EN; 411128e7ea8aSPing-Ke Shih rtw89_write16(rtwdev, reg, val); 4112e3ec7017SPing-Ke Shih 4113e3ec7017SPing-Ke Shih return 0; 4114e3ec7017SPing-Ke Shih } 4115e3ec7017SPing-Ke Shih 4116e3ec7017SPing-Ke Shih void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 4117e3ec7017SPing-Ke Shih { 4118e3ec7017SPing-Ke Shih u32 fw_sb; 4119e3ec7017SPing-Ke Shih 4120e3ec7017SPing-Ke Shih fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4121e3ec7017SPing-Ke Shih fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 4122e3ec7017SPing-Ke Shih fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 4123e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4124e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 4125e3ec7017SPing-Ke Shih else 4126e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 4127e3ec7017SPing-Ke Shih val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 4128e3ec7017SPing-Ke Shih val = B_AX_TOGGLE | 4129e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 4130e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 4131e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 4132e3ec7017SPing-Ke Shih fsleep(1000); /* avoid BT FW loss information */ 4133e3ec7017SPing-Ke Shih } 4134e3ec7017SPing-Ke Shih 4135e3ec7017SPing-Ke Shih u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 4136e3ec7017SPing-Ke Shih { 4137e3ec7017SPing-Ke Shih return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4138e3ec7017SPing-Ke Shih } 4139e3ec7017SPing-Ke Shih 4140e3ec7017SPing-Ke Shih int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4141e3ec7017SPing-Ke Shih { 4142e3ec7017SPing-Ke Shih u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 4143e3ec7017SPing-Ke Shih 4144e3ec7017SPing-Ke Shih val = wl ? val | BIT(2) : val & ~BIT(2); 4145e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 4146e3ec7017SPing-Ke Shih 4147e3ec7017SPing-Ke Shih return 0; 4148e3ec7017SPing-Ke Shih } 4149feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 4150feed6541SChia-Yuan Li 4151feed6541SChia-Yuan Li int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 4152feed6541SChia-Yuan Li { 4153feed6541SChia-Yuan Li struct rtw89_btc *btc = &rtwdev->btc; 4154feed6541SChia-Yuan Li struct rtw89_btc_dm *dm = &btc->dm; 4155feed6541SChia-Yuan Li struct rtw89_mac_ax_gnt *g = dm->gnt.band; 4156feed6541SChia-Yuan Li int i; 4157feed6541SChia-Yuan Li 4158feed6541SChia-Yuan Li if (wl) 4159feed6541SChia-Yuan Li return 0; 4160feed6541SChia-Yuan Li 4161feed6541SChia-Yuan Li for (i = 0; i < RTW89_PHY_MAX; i++) { 4162feed6541SChia-Yuan Li g[i].gnt_bt_sw_en = 1; 4163feed6541SChia-Yuan Li g[i].gnt_bt = 1; 4164feed6541SChia-Yuan Li g[i].gnt_wl_sw_en = 1; 4165feed6541SChia-Yuan Li g[i].gnt_wl = 0; 4166feed6541SChia-Yuan Li } 4167feed6541SChia-Yuan Li 4168feed6541SChia-Yuan Li return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 4169feed6541SChia-Yuan Li } 4170feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 4171e3ec7017SPing-Ke Shih 4172e3ec7017SPing-Ke Shih bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 4173e3ec7017SPing-Ke Shih { 4174e3ec7017SPing-Ke Shih u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 4175e3ec7017SPing-Ke Shih 4176e3ec7017SPing-Ke Shih return FIELD_GET(B_AX_LTE_MUX_CTRL_PATH >> 24, val); 4177e3ec7017SPing-Ke Shih } 4178e3ec7017SPing-Ke Shih 41798c7e9cebSChing-Te Ku u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 41808c7e9cebSChing-Te Ku { 41818c7e9cebSChing-Te Ku u32 reg; 41828c7e9cebSChing-Te Ku u16 cnt; 41838c7e9cebSChing-Te Ku 41848c7e9cebSChing-Te Ku reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); 41858c7e9cebSChing-Te Ku cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 41868c7e9cebSChing-Te Ku rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 41878c7e9cebSChing-Te Ku 41888c7e9cebSChing-Te Ku return cnt; 41898c7e9cebSChing-Te Ku } 41908c7e9cebSChing-Te Ku 4191e3ec7017SPing-Ke Shih static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 4192e3ec7017SPing-Ke Shih { 4193e3ec7017SPing-Ke Shih u32 reg; 4194e3ec7017SPing-Ke Shih u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 4195e3ec7017SPing-Ke Shih B_AX_BFMEE_HE_NDPA_EN; 4196e3ec7017SPing-Ke Shih 4197e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 4198e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 4199e3ec7017SPing-Ke Shih if (en) { 4200e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4201e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, mask); 4202e3ec7017SPing-Ke Shih } else { 4203e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4204e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, mask); 4205e3ec7017SPing-Ke Shih } 4206e3ec7017SPing-Ke Shih } 4207e3ec7017SPing-Ke Shih 4208e3ec7017SPing-Ke Shih static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 4209e3ec7017SPing-Ke Shih { 4210e3ec7017SPing-Ke Shih u32 reg; 4211e3ec7017SPing-Ke Shih u32 val32; 4212e3ec7017SPing-Ke Shih int ret; 4213e3ec7017SPing-Ke Shih 4214e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4215e3ec7017SPing-Ke Shih if (ret) 4216e3ec7017SPing-Ke Shih return ret; 4217e3ec7017SPing-Ke Shih 4218e3ec7017SPing-Ke Shih /* AP mode set tx gid to 63 */ 4219e3ec7017SPing-Ke Shih /* STA mode set tx gid to 0(default) */ 4220e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); 4221e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 4222e3ec7017SPing-Ke Shih 4223e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 4224e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 4225e3ec7017SPing-Ke Shih 4226e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 4227e3ec7017SPing-Ke Shih val32 = FIELD_PREP(B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, BFRP_RX_STANDBY_TIMER); 4228e3ec7017SPing-Ke Shih val32 |= FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 4229e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 4230e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 4231e3ec7017SPing-Ke Shih 4232e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4233e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 4234e3ec7017SPing-Ke Shih B_AX_BFMEE_USE_NSTS | 4235e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_GID_SEL | 4236e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_FORCE_RETE_EN); 4237e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 4238e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, 4239e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 4240e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 4241e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 4242e3ec7017SPing-Ke Shih 4243*62440fbeSPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_CSIRPT_OPTION, mac_idx); 4244*62440fbeSPing-Ke Shih rtw89_write32_set(rtwdev, reg, 4245*62440fbeSPing-Ke Shih B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 4246*62440fbeSPing-Ke Shih 4247e3ec7017SPing-Ke Shih return 0; 4248e3ec7017SPing-Ke Shih } 4249e3ec7017SPing-Ke Shih 4250e3ec7017SPing-Ke Shih static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 4251e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 4252e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 4253e3ec7017SPing-Ke Shih { 4254e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4255e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 4256e3ec7017SPing-Ke Shih u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 4257e3ec7017SPing-Ke Shih u8 port_sel = rtwvif->port; 4258e3ec7017SPing-Ke Shih u8 sound_dim = 3, t; 4259046d2e7cSSriram R u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 4260e3ec7017SPing-Ke Shih u32 reg; 4261e3ec7017SPing-Ke Shih u16 val; 4262e3ec7017SPing-Ke Shih int ret; 4263e3ec7017SPing-Ke Shih 4264e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4265e3ec7017SPing-Ke Shih if (ret) 4266e3ec7017SPing-Ke Shih return ret; 4267e3ec7017SPing-Ke Shih 4268e3ec7017SPing-Ke Shih if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4269e3ec7017SPing-Ke Shih (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 4270e3ec7017SPing-Ke Shih ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 4271e3ec7017SPing-Ke Shih stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 4272e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 4273e3ec7017SPing-Ke Shih phy_cap[5]); 4274e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 4275e3ec7017SPing-Ke Shih } 4276046d2e7cSSriram R if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4277046d2e7cSSriram R (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 4278046d2e7cSSriram R ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 4279046d2e7cSSriram R stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 4280e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 4281046d2e7cSSriram R sta->deflink.vht_cap.cap); 4282e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 4283e3ec7017SPing-Ke Shih } 4284e3ec7017SPing-Ke Shih nc = min(nc, sound_dim); 4285e3ec7017SPing-Ke Shih nr = min(nr, sound_dim); 4286e3ec7017SPing-Ke Shih 4287e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4288e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 4289e3ec7017SPing-Ke Shih 4290e3ec7017SPing-Ke Shih val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 4291e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 4292e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 4293e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 4294e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 4295e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 4296e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 4297e3ec7017SPing-Ke Shih 4298e3ec7017SPing-Ke Shih if (port_sel == 0) 4299e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4300e3ec7017SPing-Ke Shih else 4301e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 4302e3ec7017SPing-Ke Shih 4303e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 4304e3ec7017SPing-Ke Shih 4305e3ec7017SPing-Ke Shih return 0; 4306e3ec7017SPing-Ke Shih } 4307e3ec7017SPing-Ke Shih 4308e3ec7017SPing-Ke Shih static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 4309e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 4310e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 4311e3ec7017SPing-Ke Shih { 4312e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4313e3ec7017SPing-Ke Shih u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 4314e3ec7017SPing-Ke Shih u32 reg; 4315e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 4316e3ec7017SPing-Ke Shih int ret; 4317e3ec7017SPing-Ke Shih 4318e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4319e3ec7017SPing-Ke Shih if (ret) 4320e3ec7017SPing-Ke Shih return ret; 4321e3ec7017SPing-Ke Shih 4322046d2e7cSSriram R if (sta->deflink.he_cap.has_he) { 4323e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 4324e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 4325e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 4326e3ec7017SPing-Ke Shih } 4327046d2e7cSSriram R if (sta->deflink.vht_cap.vht_supported) { 4328e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 4329e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 4330e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 4331e3ec7017SPing-Ke Shih } 4332046d2e7cSSriram R if (sta->deflink.ht_cap.ht_supported) { 4333e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 4334e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 4335e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 4336e3ec7017SPing-Ke Shih } 4337e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4338e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 4339e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 4340e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, 4341e3ec7017SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 4342e3ec7017SPing-Ke Shih rrsc); 4343e3ec7017SPing-Ke Shih 4344e3ec7017SPing-Ke Shih return 0; 4345e3ec7017SPing-Ke Shih } 4346e3ec7017SPing-Ke Shih 4347e3ec7017SPing-Ke Shih void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4348e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 4349e3ec7017SPing-Ke Shih { 4350e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4351e3ec7017SPing-Ke Shih 4352e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) { 4353e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, 4354e3ec7017SPing-Ke Shih "initialize bfee for new association\n"); 4355e3ec7017SPing-Ke Shih rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 4356e3ec7017SPing-Ke Shih rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 4357e3ec7017SPing-Ke Shih rtw89_mac_csi_rrsc(rtwdev, vif, sta); 4358e3ec7017SPing-Ke Shih } 4359e3ec7017SPing-Ke Shih } 4360e3ec7017SPing-Ke Shih 4361e3ec7017SPing-Ke Shih void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4362e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 4363e3ec7017SPing-Ke Shih { 4364e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4365e3ec7017SPing-Ke Shih 4366e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 4367e3ec7017SPing-Ke Shih } 4368e3ec7017SPing-Ke Shih 4369e3ec7017SPing-Ke Shih void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4370e3ec7017SPing-Ke Shih struct ieee80211_bss_conf *conf) 4371e3ec7017SPing-Ke Shih { 4372e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4373e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 4374e3ec7017SPing-Ke Shih __le32 *p; 4375e3ec7017SPing-Ke Shih 4376e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 4377e3ec7017SPing-Ke Shih 4378e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.membership; 4379e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), 4380e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 4381e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), 4382e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 4383e3ec7017SPing-Ke Shih 4384e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.position; 4385e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), 4386e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 4387e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), 4388e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 4389e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), 4390e3ec7017SPing-Ke Shih le32_to_cpu(p[2])); 4391e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), 4392e3ec7017SPing-Ke Shih le32_to_cpu(p[3])); 4393e3ec7017SPing-Ke Shih } 4394e3ec7017SPing-Ke Shih 4395e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data { 4396e3ec7017SPing-Ke Shih struct rtw89_dev *rtwdev; 4397e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta; 4398e3ec7017SPing-Ke Shih int count; 4399e3ec7017SPing-Ke Shih }; 4400e3ec7017SPing-Ke Shih 4401e3ec7017SPing-Ke Shih static 4402e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 4403e3ec7017SPing-Ke Shih { 4404e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data *iter_data = 4405e3ec7017SPing-Ke Shih (struct rtw89_mac_bf_monitor_iter_data *)data; 4406e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta = iter_data->down_sta; 4407e3ec7017SPing-Ke Shih int *count = &iter_data->count; 4408e3ec7017SPing-Ke Shih 4409e3ec7017SPing-Ke Shih if (down_sta == sta) 4410e3ec7017SPing-Ke Shih return; 4411e3ec7017SPing-Ke Shih 4412e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) 4413e3ec7017SPing-Ke Shih (*count)++; 4414e3ec7017SPing-Ke Shih } 4415e3ec7017SPing-Ke Shih 4416e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 4417e3ec7017SPing-Ke Shih struct ieee80211_sta *sta, bool disconnect) 4418e3ec7017SPing-Ke Shih { 4419e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data data; 4420e3ec7017SPing-Ke Shih 4421e3ec7017SPing-Ke Shih data.rtwdev = rtwdev; 4422e3ec7017SPing-Ke Shih data.down_sta = disconnect ? sta : NULL; 4423e3ec7017SPing-Ke Shih data.count = 0; 4424e3ec7017SPing-Ke Shih ieee80211_iterate_stations_atomic(rtwdev->hw, 4425e3ec7017SPing-Ke Shih rtw89_mac_bf_monitor_calc_iter, 4426e3ec7017SPing-Ke Shih &data); 4427e3ec7017SPing-Ke Shih 4428e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 4429e3ec7017SPing-Ke Shih if (data.count) 4430e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 4431e3ec7017SPing-Ke Shih else 4432e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 4433e3ec7017SPing-Ke Shih } 4434e3ec7017SPing-Ke Shih 4435e3ec7017SPing-Ke Shih void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 4436e3ec7017SPing-Ke Shih { 4437e3ec7017SPing-Ke Shih struct rtw89_traffic_stats *stats = &rtwdev->stats; 4438e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif; 44391646ce8fSYe Guojin bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 4440e3ec7017SPing-Ke Shih bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4441e3ec7017SPing-Ke Shih 4442e3ec7017SPing-Ke Shih if (en == old) 4443e3ec7017SPing-Ke Shih return; 4444e3ec7017SPing-Ke Shih 4445e3ec7017SPing-Ke Shih rtw89_for_each_rtwvif(rtwdev, rtwvif) 4446e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 4447e3ec7017SPing-Ke Shih } 4448e3ec7017SPing-Ke Shih 4449e3ec7017SPing-Ke Shih static int 4450e3ec7017SPing-Ke Shih __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4451e3ec7017SPing-Ke Shih u32 tx_time) 4452e3ec7017SPing-Ke Shih { 4453e3ec7017SPing-Ke Shih #define MAC_AX_DFLT_TX_TIME 5280 4454e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 4455e3ec7017SPing-Ke Shih u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 4456e3ec7017SPing-Ke Shih u32 reg; 4457e3ec7017SPing-Ke Shih int ret = 0; 4458e3ec7017SPing-Ke Shih 4459e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 4460e3ec7017SPing-Ke Shih rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 4461e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4462e3ec7017SPing-Ke Shih } else { 4463e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4464e3ec7017SPing-Ke Shih if (ret) { 4465e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 4466e3ec7017SPing-Ke Shih return ret; 4467e3ec7017SPing-Ke Shih } 4468e3ec7017SPing-Ke Shih 4469e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 4470e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 4471e3ec7017SPing-Ke Shih max_tx_time >> 5); 4472e3ec7017SPing-Ke Shih } 4473e3ec7017SPing-Ke Shih 4474e3ec7017SPing-Ke Shih return ret; 4475e3ec7017SPing-Ke Shih } 4476e3ec7017SPing-Ke Shih 4477e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4478e3ec7017SPing-Ke Shih bool resume, u32 tx_time) 4479e3ec7017SPing-Ke Shih { 4480e3ec7017SPing-Ke Shih int ret = 0; 4481e3ec7017SPing-Ke Shih 4482e3ec7017SPing-Ke Shih if (!resume) { 4483e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = true; 4484e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 4485e3ec7017SPing-Ke Shih } else { 4486e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 4487e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = false; 4488e3ec7017SPing-Ke Shih } 4489e3ec7017SPing-Ke Shih 4490e3ec7017SPing-Ke Shih return ret; 4491e3ec7017SPing-Ke Shih } 4492e3ec7017SPing-Ke Shih 4493e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4494e3ec7017SPing-Ke Shih u32 *tx_time) 4495e3ec7017SPing-Ke Shih { 4496e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 4497e3ec7017SPing-Ke Shih u32 reg; 4498e3ec7017SPing-Ke Shih int ret = 0; 4499e3ec7017SPing-Ke Shih 4500e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 4501e3ec7017SPing-Ke Shih *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 4502e3ec7017SPing-Ke Shih } else { 4503e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4504e3ec7017SPing-Ke Shih if (ret) { 4505e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 4506e3ec7017SPing-Ke Shih return ret; 4507e3ec7017SPing-Ke Shih } 4508e3ec7017SPing-Ke Shih 4509e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 4510e3ec7017SPing-Ke Shih *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 4511e3ec7017SPing-Ke Shih } 4512e3ec7017SPing-Ke Shih 4513e3ec7017SPing-Ke Shih return ret; 4514e3ec7017SPing-Ke Shih } 4515e3ec7017SPing-Ke Shih 4516e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 4517e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, 4518e3ec7017SPing-Ke Shih bool resume, u8 tx_retry) 4519e3ec7017SPing-Ke Shih { 4520e3ec7017SPing-Ke Shih int ret = 0; 4521e3ec7017SPing-Ke Shih 4522e3ec7017SPing-Ke Shih rtwsta->data_tx_cnt_lmt = tx_retry; 4523e3ec7017SPing-Ke Shih 4524e3ec7017SPing-Ke Shih if (!resume) { 4525e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = true; 4526e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4527e3ec7017SPing-Ke Shih } else { 4528e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4529e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = false; 4530e3ec7017SPing-Ke Shih } 4531e3ec7017SPing-Ke Shih 4532e3ec7017SPing-Ke Shih return ret; 4533e3ec7017SPing-Ke Shih } 4534e3ec7017SPing-Ke Shih 4535e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 4536e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, u8 *tx_retry) 4537e3ec7017SPing-Ke Shih { 4538e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 4539e3ec7017SPing-Ke Shih u32 reg; 4540e3ec7017SPing-Ke Shih int ret = 0; 4541e3ec7017SPing-Ke Shih 4542e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_retry_limit) { 4543e3ec7017SPing-Ke Shih *tx_retry = rtwsta->data_tx_cnt_lmt; 4544e3ec7017SPing-Ke Shih } else { 4545e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4546e3ec7017SPing-Ke Shih if (ret) { 4547e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 4548e3ec7017SPing-Ke Shih return ret; 4549e3ec7017SPing-Ke Shih } 4550e3ec7017SPing-Ke Shih 4551e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); 4552e3ec7017SPing-Ke Shih *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 4553e3ec7017SPing-Ke Shih } 4554e3ec7017SPing-Ke Shih 4555e3ec7017SPing-Ke Shih return ret; 4556e3ec7017SPing-Ke Shih } 4557e3ec7017SPing-Ke Shih 4558e3ec7017SPing-Ke Shih int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 4559e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 4560e3ec7017SPing-Ke Shih { 4561e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 4562e3ec7017SPing-Ke Shih u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; 4563e3ec7017SPing-Ke Shih u32 reg; 4564e3ec7017SPing-Ke Shih u32 ret; 4565e3ec7017SPing-Ke Shih 4566e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4567e3ec7017SPing-Ke Shih if (ret) 4568e3ec7017SPing-Ke Shih return ret; 4569e3ec7017SPing-Ke Shih 4570e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); 4571e3ec7017SPing-Ke Shih if (en) 4572e3ec7017SPing-Ke Shih rtw89_write16_set(rtwdev, reg, set); 4573e3ec7017SPing-Ke Shih else 4574e3ec7017SPing-Ke Shih rtw89_write16_clr(rtwdev, reg, set); 4575e3ec7017SPing-Ke Shih 4576e3ec7017SPing-Ke Shih return 0; 4577e3ec7017SPing-Ke Shih } 45782a7e54dbSPing-Ke Shih 45792a7e54dbSPing-Ke Shih int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 45802a7e54dbSPing-Ke Shih { 45812a7e54dbSPing-Ke Shih u32 val32; 45822a7e54dbSPing-Ke Shih int ret; 45832a7e54dbSPing-Ke Shih 45842a7e54dbSPing-Ke Shih val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 45852a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 45862a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 45872a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 45882a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 45892a7e54dbSPing-Ke Shih rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 45902a7e54dbSPing-Ke Shih 45912a7e54dbSPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 45922a7e54dbSPing-Ke Shih 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 45932a7e54dbSPing-Ke Shih if (ret) { 45942a7e54dbSPing-Ke Shih rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 45952a7e54dbSPing-Ke Shih offset, val, mask); 45962a7e54dbSPing-Ke Shih return ret; 45972a7e54dbSPing-Ke Shih } 45982a7e54dbSPing-Ke Shih 45992a7e54dbSPing-Ke Shih return 0; 46002a7e54dbSPing-Ke Shih } 46012a7e54dbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 4602bdfbf06cSPing-Ke Shih 4603bdfbf06cSPing-Ke Shih int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 4604bdfbf06cSPing-Ke Shih { 4605bdfbf06cSPing-Ke Shih u32 val32; 4606bdfbf06cSPing-Ke Shih int ret; 4607bdfbf06cSPing-Ke Shih 4608bdfbf06cSPing-Ke Shih val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 4609bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 4610bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 4611bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 4612bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 4613bdfbf06cSPing-Ke Shih rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 4614bdfbf06cSPing-Ke Shih 4615bdfbf06cSPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 4616bdfbf06cSPing-Ke Shih 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 4617bdfbf06cSPing-Ke Shih if (ret) { 4618bdfbf06cSPing-Ke Shih rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 4619bdfbf06cSPing-Ke Shih return ret; 4620bdfbf06cSPing-Ke Shih } 4621bdfbf06cSPing-Ke Shih 4622bdfbf06cSPing-Ke Shih *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 4623bdfbf06cSPing-Ke Shih 4624bdfbf06cSPing-Ke Shih return 0; 4625bdfbf06cSPing-Ke Shih } 4626