1e3ec7017SPing-Ke Shih // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2e3ec7017SPing-Ke Shih /* Copyright(c) 2019-2020 Realtek Corporation 3e3ec7017SPing-Ke Shih */ 4e3ec7017SPing-Ke Shih 5e3ec7017SPing-Ke Shih #include "cam.h" 6967439c7SZong-Zhe Yang #include "chan.h" 7e3ec7017SPing-Ke Shih #include "debug.h" 8e3ec7017SPing-Ke Shih #include "fw.h" 9e3ec7017SPing-Ke Shih #include "mac.h" 10f7333fc2SChia-Yuan Li #include "pci.h" 11e3ec7017SPing-Ke Shih #include "ps.h" 12e3ec7017SPing-Ke Shih #include "reg.h" 13e3ec7017SPing-Ke Shih #include "util.h" 14e3ec7017SPing-Ke Shih 1560168f6cSPing-Ke Shih static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 16e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 17e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 18e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 19e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 20e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 21e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 22e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 23e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 24e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 25e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 26e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 27e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 28e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 29e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 30e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 31e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 32e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 33ec356ffbSChia-Yuan Li [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 34dadb2086SPing-Ke Shih [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 35732dd91dSPing-Ke Shih [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 36732dd91dSPing-Ke Shih [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 37e1400b11SZong-Zhe Yang }; 38e1400b11SZong-Zhe Yang 39ec356ffbSChia-Yuan Li static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 40ec356ffbSChia-Yuan Li u32 val, enum rtw89_mac_mem_sel sel) 41ec356ffbSChia-Yuan Li { 4260168f6cSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4360168f6cSPing-Ke Shih u32 addr = mac->mem_base_addrs[sel] + offset; 44ec356ffbSChia-Yuan Li 4560168f6cSPing-Ke Shih rtw89_write32(rtwdev, mac->filter_model_addr, addr); 4660168f6cSPing-Ke Shih rtw89_write32(rtwdev, mac->indir_access_addr, val); 47ec356ffbSChia-Yuan Li } 48ec356ffbSChia-Yuan Li 49ec356ffbSChia-Yuan Li static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 50ec356ffbSChia-Yuan Li enum rtw89_mac_mem_sel sel) 51ec356ffbSChia-Yuan Li { 5260168f6cSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5360168f6cSPing-Ke Shih u32 addr = mac->mem_base_addrs[sel] + offset; 54ec356ffbSChia-Yuan Li 5560168f6cSPing-Ke Shih rtw89_write32(rtwdev, mac->filter_model_addr, addr); 5660168f6cSPing-Ke Shih return rtw89_read32(rtwdev, mac->indir_access_addr); 57ec356ffbSChia-Yuan Li } 58ec356ffbSChia-Yuan Li 59e3ec7017SPing-Ke Shih int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 60e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 61e3ec7017SPing-Ke Shih { 62e3ec7017SPing-Ke Shih u32 val, r_val; 63e3ec7017SPing-Ke Shih 64e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 65e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 66e3ec7017SPing-Ke Shih val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 67e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 68e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 69e3ec7017SPing-Ke Shih val = B_AX_CMAC_EN; 70e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 71e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 72e3ec7017SPing-Ke Shih val = B_AX_CMAC1_FEN; 73e3ec7017SPing-Ke Shih } else { 74e3ec7017SPing-Ke Shih return -EINVAL; 75e3ec7017SPing-Ke Shih } 76e3ec7017SPing-Ke Shih if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 77e3ec7017SPing-Ke Shih (val & r_val) != val) 78e3ec7017SPing-Ke Shih return -EFAULT; 79e3ec7017SPing-Ke Shih 80e3ec7017SPing-Ke Shih return 0; 81e3ec7017SPing-Ke Shih } 82e3ec7017SPing-Ke Shih 83e3ec7017SPing-Ke Shih int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 84e3ec7017SPing-Ke Shih { 85e3ec7017SPing-Ke Shih u8 lte_ctrl; 86e3ec7017SPing-Ke Shih int ret; 87e3ec7017SPing-Ke Shih 88e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 89e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 90e3ec7017SPing-Ke Shih if (ret) 91e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 92e3ec7017SPing-Ke Shih 93e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 94e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 95e3ec7017SPing-Ke Shih 96e3ec7017SPing-Ke Shih return ret; 97e3ec7017SPing-Ke Shih } 98e3ec7017SPing-Ke Shih 99e3ec7017SPing-Ke Shih int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 100e3ec7017SPing-Ke Shih { 101e3ec7017SPing-Ke Shih u8 lte_ctrl; 102e3ec7017SPing-Ke Shih int ret; 103e3ec7017SPing-Ke Shih 104e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 105e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 106e3ec7017SPing-Ke Shih if (ret) 107e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 108e3ec7017SPing-Ke Shih 109e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 110e3ec7017SPing-Ke Shih *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 111e3ec7017SPing-Ke Shih 112e3ec7017SPing-Ke Shih return ret; 113e3ec7017SPing-Ke Shih } 114e3ec7017SPing-Ke Shih 115e3ec7017SPing-Ke Shih static 116e3ec7017SPing-Ke Shih int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 117e3ec7017SPing-Ke Shih { 118e3ec7017SPing-Ke Shih u32 ctrl_reg, data_reg, ctrl_data; 119e3ec7017SPing-Ke Shih u32 val; 120e3ec7017SPing-Ke Shih int ret; 121e3ec7017SPing-Ke Shih 122e3ec7017SPing-Ke Shih switch (ctrl->type) { 123e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_WDE: 124e3ec7017SPing-Ke Shih ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 125e3ec7017SPing-Ke Shih data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 126e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 127e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 128e3ec7017SPing-Ke Shih B_AX_WDE_DFI_ACTIVE; 129e3ec7017SPing-Ke Shih break; 130e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_PLE: 131e3ec7017SPing-Ke Shih ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 132e3ec7017SPing-Ke Shih data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 133e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 134e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 135e3ec7017SPing-Ke Shih B_AX_PLE_DFI_ACTIVE; 136e3ec7017SPing-Ke Shih break; 137e3ec7017SPing-Ke Shih default: 138e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 139e3ec7017SPing-Ke Shih return -EINVAL; 140e3ec7017SPing-Ke Shih } 141e3ec7017SPing-Ke Shih 142e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 143e3ec7017SPing-Ke Shih 144e3ec7017SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 145e3ec7017SPing-Ke Shih 1, 1000, false, rtwdev, ctrl_reg); 146e3ec7017SPing-Ke Shih if (ret) { 147e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 148e3ec7017SPing-Ke Shih ctrl_reg, ctrl_data); 149e3ec7017SPing-Ke Shih return ret; 150e3ec7017SPing-Ke Shih } 151e3ec7017SPing-Ke Shih 152e3ec7017SPing-Ke Shih ctrl->out_data = rtw89_read32(rtwdev, data_reg); 153e3ec7017SPing-Ke Shih return 0; 154e3ec7017SPing-Ke Shih } 155e3ec7017SPing-Ke Shih 156e3ec7017SPing-Ke Shih static int dle_dfi_quota(struct rtw89_dev *rtwdev, 157e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota *quota) 158e3ec7017SPing-Ke Shih { 159e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 160e3ec7017SPing-Ke Shih int ret; 161e3ec7017SPing-Ke Shih 162e3ec7017SPing-Ke Shih ctrl.type = quota->dle_type; 163e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QUOTA; 164e3ec7017SPing-Ke Shih ctrl.addr = quota->qtaid; 165e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 166e3ec7017SPing-Ke Shih if (ret) { 167e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 168e3ec7017SPing-Ke Shih return ret; 169e3ec7017SPing-Ke Shih } 170e3ec7017SPing-Ke Shih 171e3ec7017SPing-Ke Shih quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 172e3ec7017SPing-Ke Shih quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 173e3ec7017SPing-Ke Shih return 0; 174e3ec7017SPing-Ke Shih } 175e3ec7017SPing-Ke Shih 176e3ec7017SPing-Ke Shih static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 177e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty *qempty) 178e3ec7017SPing-Ke Shih { 179e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 180e3ec7017SPing-Ke Shih u32 ret; 181e3ec7017SPing-Ke Shih 182e3ec7017SPing-Ke Shih ctrl.type = qempty->dle_type; 183e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QEMPTY; 184e3ec7017SPing-Ke Shih ctrl.addr = qempty->grpsel; 185e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 186e3ec7017SPing-Ke Shih if (ret) { 187e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 188e3ec7017SPing-Ke Shih return ret; 189e3ec7017SPing-Ke Shih } 190e3ec7017SPing-Ke Shih 191e3ec7017SPing-Ke Shih qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 192e3ec7017SPing-Ke Shih return 0; 193e3ec7017SPing-Ke Shih } 194e3ec7017SPing-Ke Shih 195e3ec7017SPing-Ke Shih static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 196e3ec7017SPing-Ke Shih { 197e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 198e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 199e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 200e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 201e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 202e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 203e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 204e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 205e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 206e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 207e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 208e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 209e3ec7017SPing-Ke Shih } 210e3ec7017SPing-Ke Shih 211e3ec7017SPing-Ke Shih static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 212e3ec7017SPing-Ke Shih { 213e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty qempty; 214e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota quota; 215e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 216e3ec7017SPing-Ke Shih u32 val, not_empty, i; 217e3ec7017SPing-Ke Shih int ret; 218e3ec7017SPing-Ke Shih 219e3ec7017SPing-Ke Shih qempty.dle_type = DLE_CTRL_TYPE_PLE; 220e3ec7017SPing-Ke Shih qempty.grpsel = 0; 22189e4a00fSÍñigo Huguet qempty.qempty = ~(u32)0; 222e3ec7017SPing-Ke Shih ret = dle_dfi_qempty(rtwdev, &qempty); 223e3ec7017SPing-Ke Shih if (ret) 224e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 225e3ec7017SPing-Ke Shih else 226e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 227e3ec7017SPing-Ke Shih 228e3ec7017SPing-Ke Shih for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 229e3ec7017SPing-Ke Shih if (!(not_empty & BIT(0))) 230e3ec7017SPing-Ke Shih continue; 231e3ec7017SPing-Ke Shih ctrl.type = DLE_CTRL_TYPE_PLE; 232e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QLNKTBL; 233e3ec7017SPing-Ke Shih ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 234e3ec7017SPing-Ke Shih FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 235e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 236e3ec7017SPing-Ke Shih if (ret) 237e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 238e3ec7017SPing-Ke Shih else 239e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 240e3ec7017SPing-Ke Shih FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 241e3ec7017SPing-Ke Shih ctrl.out_data)); 242e3ec7017SPing-Ke Shih } 243e3ec7017SPing-Ke Shih 244e3ec7017SPing-Ke Shih quota.dle_type = DLE_CTRL_TYPE_PLE; 245e3ec7017SPing-Ke Shih quota.qtaid = 6; 246e3ec7017SPing-Ke Shih ret = dle_dfi_quota(rtwdev, "a); 247e3ec7017SPing-Ke Shih if (ret) 248e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 249e3ec7017SPing-Ke Shih else 250e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 251e3ec7017SPing-Ke Shih quota.rsv_pgnum, quota.use_pgnum); 252e3ec7017SPing-Ke Shih 253e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 254e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 255e3ec7017SPing-Ke Shih FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 256e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 257e3ec7017SPing-Ke Shih FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 258e3ec7017SPing-Ke Shih 259e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 260e3ec7017SPing-Ke Shih } 261e3ec7017SPing-Ke Shih 262e3ec7017SPing-Ke Shih static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 263e3ec7017SPing-Ke Shih enum mac_ax_err_info err) 264e3ec7017SPing-Ke Shih { 265e3ec7017SPing-Ke Shih u32 dbg, event; 266e3ec7017SPing-Ke Shih 267e3ec7017SPing-Ke Shih dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 268e3ec7017SPing-Ke Shih event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 269e3ec7017SPing-Ke Shih 270e3ec7017SPing-Ke Shih switch (event) { 271e3ec7017SPing-Ke Shih case MAC_AX_L0_TO_L1_RX_QTA_LOST: 272e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota lost!\n"); 273e3ec7017SPing-Ke Shih rtw89_mac_dump_qta_lost(rtwdev); 274e3ec7017SPing-Ke Shih break; 275e3ec7017SPing-Ke Shih default: 276e3ec7017SPing-Ke Shih break; 277e3ec7017SPing-Ke Shih } 278e3ec7017SPing-Ke Shih } 279e3ec7017SPing-Ke Shih 280f7333fc2SChia-Yuan Li static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 281e3ec7017SPing-Ke Shih { 282f7333fc2SChia-Yuan Li const struct rtw89_chip_info *chip = rtwdev->chip; 283f7333fc2SChia-Yuan Li u32 dmac_err; 284f7333fc2SChia-Yuan Li int i, ret; 285e3ec7017SPing-Ke Shih 286f7333fc2SChia-Yuan Li ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 287f7333fc2SChia-Yuan Li if (ret) { 288f7333fc2SChia-Yuan Li rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 289e3ec7017SPing-Ke Shih return; 290f7333fc2SChia-Yuan Li } 291e3ec7017SPing-Ke Shih 292e3ec7017SPing-Ke Shih dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 293e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 294f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 295f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 296e3ec7017SPing-Ke Shih 297e3ec7017SPing-Ke Shih if (dmac_err) { 298f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 299f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 300e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 301f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 302f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 303f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 304f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 305f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 306f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 307f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 308f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 309f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 310f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 311f7333fc2SChia-Yuan Li } 312e3ec7017SPing-Ke Shih } 313e3ec7017SPing-Ke Shih 314e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 315f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 316e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 317e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 318e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 319f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) 320f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 321f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 322f7333fc2SChia-Yuan Li else 323f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 324f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 325e3ec7017SPing-Ke Shih } 326e3ec7017SPing-Ke Shih 327e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WSEC_ERR_FLAG) { 328f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 329f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 330f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 331f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 332f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 333f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 334f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 335f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 336f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 337f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 338f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 339f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 340f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 341f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 342f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 343f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 344f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 345f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 346f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 347f7333fc2SChia-Yuan Li 348f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 349f7333fc2SChia-Yuan Li B_AX_DBG_SEL0, 0x8B); 350f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 351f7333fc2SChia-Yuan Li B_AX_DBG_SEL1, 0x8B); 352f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 353f7333fc2SChia-Yuan Li B_AX_SEL_0XC0_MASK, 1); 354f7333fc2SChia-Yuan Li for (i = 0; i < 0x10; i++) { 355f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 356f7333fc2SChia-Yuan Li B_AX_SEC_DBG_PORT_FIELD_MASK, i); 357f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 358f7333fc2SChia-Yuan Li i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 359f7333fc2SChia-Yuan Li } 360f7333fc2SChia-Yuan Li } else { 361e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 362e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 363f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 364e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 365f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 366e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 367f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 368e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 369f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 370e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 371f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 372e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 373f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 374e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 375f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 376e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 377f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 378e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 379f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 380e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 381e3ec7017SPing-Ke Shih } 382f7333fc2SChia-Yuan Li } 383e3ec7017SPing-Ke Shih 384e3ec7017SPing-Ke Shih if (dmac_err & B_AX_MPDU_ERR_FLAG) { 385f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 386e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 387e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 388e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 389f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 390e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 391e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 392e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 393e3ec7017SPing-Ke Shih } 394e3ec7017SPing-Ke Shih 395e3ec7017SPing-Ke Shih if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 396f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 397e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 398e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 399e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 400e3ec7017SPing-Ke Shih } 401e3ec7017SPing-Ke Shih 402e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 403f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 404e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 405e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 406e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 407f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 408e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 409e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 410e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 411e3ec7017SPing-Ke Shih } 412e3ec7017SPing-Ke Shih 413e3ec7017SPing-Ke Shih if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 414f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 415f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 416f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 417f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 418f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 419f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 420f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 421f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 422f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 423f7333fc2SChia-Yuan Li } else { 424e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 425e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 426e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 427e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 428e3ec7017SPing-Ke Shih } 429f7333fc2SChia-Yuan Li } 430e3ec7017SPing-Ke Shih 431e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 432f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 433e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 434e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 435e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 436f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 437e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 438e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 439e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 440e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 441e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 442e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 443e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 444e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 445e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 446e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 447e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 448e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 449e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 450e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 451e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 452e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 453e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 454e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 455e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 456f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 457f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 458f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 459f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 460f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 461f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 462f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 463f7333fc2SChia-Yuan Li } else { 464e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 465e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 466e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 467e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 468e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 469e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 470f7333fc2SChia-Yuan Li } 471e3ec7017SPing-Ke Shih } 472e3ec7017SPing-Ke Shih 473e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 474f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 475e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 476e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 477e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 478e3ec7017SPing-Ke Shih } 479e3ec7017SPing-Ke Shih 480f7333fc2SChia-Yuan Li if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 481f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 482f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 483f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 484f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 485f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 486f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 487f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 488f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 489f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 490f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 491f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 492f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 493e3ec7017SPing-Ke Shih } 494e3ec7017SPing-Ke Shih 495f7333fc2SChia-Yuan Li if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 496f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 497f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 498f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 499f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 500f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 501f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 502f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 503f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 504f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 505f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 506f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 507f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 508f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 509f7333fc2SChia-Yuan Li } else { 510e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 511e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 512f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 513f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 514f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 515f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 516f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 517f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 518f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 519f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 520f7333fc2SChia-Yuan Li } 521e3ec7017SPing-Ke Shih } 522e3ec7017SPing-Ke Shih 523f7333fc2SChia-Yuan Li if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 524f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 525f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 526f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 527f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 528f7333fc2SChia-Yuan Li } 529f7333fc2SChia-Yuan Li } 530f7333fc2SChia-Yuan Li 531f7333fc2SChia-Yuan Li static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev, 532f7333fc2SChia-Yuan Li u8 band) 533f7333fc2SChia-Yuan Li { 534f7333fc2SChia-Yuan Li const struct rtw89_chip_info *chip = rtwdev->chip; 535f7333fc2SChia-Yuan Li u32 offset = 0; 536f7333fc2SChia-Yuan Li u32 cmac_err; 537f7333fc2SChia-Yuan Li int ret; 538f7333fc2SChia-Yuan Li 539f7333fc2SChia-Yuan Li ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 540f7333fc2SChia-Yuan Li if (ret) { 541f7333fc2SChia-Yuan Li if (band) 542f7333fc2SChia-Yuan Li rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 543f7333fc2SChia-Yuan Li else 544f7333fc2SChia-Yuan Li rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 545f7333fc2SChia-Yuan Li return; 546f7333fc2SChia-Yuan Li } 547f7333fc2SChia-Yuan Li 548f7333fc2SChia-Yuan Li if (band) 549f7333fc2SChia-Yuan Li offset = RTW89_MAC_AX_BAND_REG_OFFSET; 550f7333fc2SChia-Yuan Li 551f7333fc2SChia-Yuan Li cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 552f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 553f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 554f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 555f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 556f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 557f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 558f7333fc2SChia-Yuan Li 559e3ec7017SPing-Ke Shih if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 560f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 561f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 562f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 563f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 564e3ec7017SPing-Ke Shih } 565e3ec7017SPing-Ke Shih 566e3ec7017SPing-Ke Shih if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 567f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 568f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 569f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 570f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 571e3ec7017SPing-Ke Shih } 572e3ec7017SPing-Ke Shih 573e3ec7017SPing-Ke Shih if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 574f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 575f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 576f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 577f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 578f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 579f7333fc2SChia-Yuan Li } else { 580f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 581f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 582f7333fc2SChia-Yuan Li } 583e3ec7017SPing-Ke Shih } 584e3ec7017SPing-Ke Shih 585f7333fc2SChia-Yuan Li if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 586f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 587f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 588f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 589f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 590f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 591f7333fc2SChia-Yuan Li } else { 592f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 593f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 594f7333fc2SChia-Yuan Li } 595e3ec7017SPing-Ke Shih } 596e3ec7017SPing-Ke Shih 597e3ec7017SPing-Ke Shih if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 598f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 599f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 600f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 601f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 602e3ec7017SPing-Ke Shih } 603e3ec7017SPing-Ke Shih 604e3ec7017SPing-Ke Shih if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 605f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 606f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 607f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 608f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 609f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 610f7333fc2SChia-Yuan Li } else { 611f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 612f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 613e3ec7017SPing-Ke Shih } 614f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 615f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 616f7333fc2SChia-Yuan Li } 617f7333fc2SChia-Yuan Li 618f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 619f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 620f7333fc2SChia-Yuan Li } 621f7333fc2SChia-Yuan Li 622f7333fc2SChia-Yuan Li static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 623f7333fc2SChia-Yuan Li enum mac_ax_err_info err) 624f7333fc2SChia-Yuan Li { 625f7333fc2SChia-Yuan Li if (err != MAC_AX_ERR_L1_ERR_DMAC && 626f7333fc2SChia-Yuan Li err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 627f7333fc2SChia-Yuan Li err != MAC_AX_ERR_L0_ERR_CMAC0 && 628f5d98831SZong-Zhe Yang err != MAC_AX_ERR_L0_ERR_CMAC1 && 629f5d98831SZong-Zhe Yang err != MAC_AX_ERR_RXI300) 630f7333fc2SChia-Yuan Li return; 631f7333fc2SChia-Yuan Li 632f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 633f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 634f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 635f7333fc2SChia-Yuan Li 636f7333fc2SChia-Yuan Li rtw89_mac_dump_dmac_err_status(rtwdev); 637f7333fc2SChia-Yuan Li rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0); 638f7333fc2SChia-Yuan Li if (rtwdev->dbcc_en) 639f7333fc2SChia-Yuan Li rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1); 640e3ec7017SPing-Ke Shih 641e3ec7017SPing-Ke Shih rtwdev->hci.ops->dump_err_status(rtwdev); 642e3ec7017SPing-Ke Shih 643e3ec7017SPing-Ke Shih if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 644e3ec7017SPing-Ke Shih rtw89_mac_dump_l0_to_l1(rtwdev, err); 645e3ec7017SPing-Ke Shih 646e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "<---\n"); 647e3ec7017SPing-Ke Shih } 648e3ec7017SPing-Ke Shih 6498130e94eSChin-Yen Lee static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 6508130e94eSChin-Yen Lee { 6518130e94eSChin-Yen Lee struct rtw89_ser *ser = &rtwdev->ser; 6528130e94eSChin-Yen Lee u32 dmac_err, imr, isr; 6538130e94eSChin-Yen Lee int ret; 6548130e94eSChin-Yen Lee 6558130e94eSChin-Yen Lee if (rtwdev->chip->chip_id == RTL8852C) { 6568130e94eSChin-Yen Lee ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 6578130e94eSChin-Yen Lee if (ret) 6588130e94eSChin-Yen Lee return true; 6598130e94eSChin-Yen Lee 6608130e94eSChin-Yen Lee if (err == MAC_AX_ERR_L1_ERR_DMAC) { 6618130e94eSChin-Yen Lee dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 6628130e94eSChin-Yen Lee imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 6638130e94eSChin-Yen Lee isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 6648130e94eSChin-Yen Lee 6658130e94eSChin-Yen Lee if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 6668130e94eSChin-Yen Lee ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 6678130e94eSChin-Yen Lee set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 6688130e94eSChin-Yen Lee return true; 6698130e94eSChin-Yen Lee } 6708130e94eSChin-Yen Lee } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 6718130e94eSChin-Yen Lee if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 6728130e94eSChin-Yen Lee return true; 6738130e94eSChin-Yen Lee } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 6748130e94eSChin-Yen Lee if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 6758130e94eSChin-Yen Lee return true; 6768130e94eSChin-Yen Lee } 6778130e94eSChin-Yen Lee } 6788130e94eSChin-Yen Lee 6798130e94eSChin-Yen Lee return false; 6808130e94eSChin-Yen Lee } 6818130e94eSChin-Yen Lee 682e3ec7017SPing-Ke Shih u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 683e3ec7017SPing-Ke Shih { 684198b6cf7SZong-Zhe Yang u32 err, err_scnr; 685e3ec7017SPing-Ke Shih int ret; 686e3ec7017SPing-Ke Shih 687e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 688e3ec7017SPing-Ke Shih false, rtwdev, R_AX_HALT_C2H_CTRL); 689e3ec7017SPing-Ke Shih if (ret) { 690e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "Polling FW err status fail\n"); 691e3ec7017SPing-Ke Shih return ret; 692e3ec7017SPing-Ke Shih } 693e3ec7017SPing-Ke Shih 694e3ec7017SPing-Ke Shih err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 695e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 696e3ec7017SPing-Ke Shih 697198b6cf7SZong-Zhe Yang err_scnr = RTW89_ERROR_SCENARIO(err); 698198b6cf7SZong-Zhe Yang if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 699198b6cf7SZong-Zhe Yang err = MAC_AX_ERR_CPU_EXCEPTION; 700198b6cf7SZong-Zhe Yang else if (err_scnr == RTW89_WCPU_ASSERTION) 701198b6cf7SZong-Zhe Yang err = MAC_AX_ERR_ASSERTION; 702f5d98831SZong-Zhe Yang else if (err_scnr == RTW89_RXI300_ERROR) 703f5d98831SZong-Zhe Yang err = MAC_AX_ERR_RXI300; 704198b6cf7SZong-Zhe Yang 7058130e94eSChin-Yen Lee if (rtw89_mac_suppress_log(rtwdev, err)) 7068130e94eSChin-Yen Lee return err; 7078130e94eSChin-Yen Lee 708e3ec7017SPing-Ke Shih rtw89_fw_st_dbg_dump(rtwdev); 709e3ec7017SPing-Ke Shih rtw89_mac_dump_err_status(rtwdev, err); 710e3ec7017SPing-Ke Shih 711e3ec7017SPing-Ke Shih return err; 712e3ec7017SPing-Ke Shih } 713e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_get_err_status); 714e3ec7017SPing-Ke Shih 715e3ec7017SPing-Ke Shih int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 716e3ec7017SPing-Ke Shih { 71756617fd0SZong-Zhe Yang struct rtw89_ser *ser = &rtwdev->ser; 718e3ec7017SPing-Ke Shih u32 halt; 719e3ec7017SPing-Ke Shih int ret = 0; 720e3ec7017SPing-Ke Shih 721e3ec7017SPing-Ke Shih if (err > MAC_AX_SET_ERR_MAX) { 722e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 723e3ec7017SPing-Ke Shih return -EINVAL; 724e3ec7017SPing-Ke Shih } 725e3ec7017SPing-Ke Shih 726e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 727e3ec7017SPing-Ke Shih 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 728e3ec7017SPing-Ke Shih if (ret) { 729e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 730e3ec7017SPing-Ke Shih return -EFAULT; 731e3ec7017SPing-Ke Shih } 732e3ec7017SPing-Ke Shih 733e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 73456617fd0SZong-Zhe Yang 73556617fd0SZong-Zhe Yang if (ser->prehandle_l1 && 73656617fd0SZong-Zhe Yang (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 73756617fd0SZong-Zhe Yang return 0; 73856617fd0SZong-Zhe Yang 739e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 740e3ec7017SPing-Ke Shih 741e3ec7017SPing-Ke Shih return 0; 742e3ec7017SPing-Ke Shih } 743e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_set_err_status); 744e3ec7017SPing-Ke Shih 745e3ec7017SPing-Ke Shih static int hfc_reset_param(struct rtw89_dev *rtwdev) 746e3ec7017SPing-Ke Shih { 747e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 748e3ec7017SPing-Ke Shih struct rtw89_hfc_param_ini param_ini = {NULL}; 749e3ec7017SPing-Ke Shih u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 750e3ec7017SPing-Ke Shih 751e3ec7017SPing-Ke Shih switch (rtwdev->hci.type) { 752e3ec7017SPing-Ke Shih case RTW89_HCI_TYPE_PCIE: 753e3ec7017SPing-Ke Shih param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 754e3ec7017SPing-Ke Shih param->en = 0; 755e3ec7017SPing-Ke Shih break; 756e3ec7017SPing-Ke Shih default: 757e3ec7017SPing-Ke Shih return -EINVAL; 758e3ec7017SPing-Ke Shih } 759e3ec7017SPing-Ke Shih 760e3ec7017SPing-Ke Shih if (param_ini.pub_cfg) 761e3ec7017SPing-Ke Shih param->pub_cfg = *param_ini.pub_cfg; 762e3ec7017SPing-Ke Shih 76365a9140eSDmitry Antipov if (param_ini.prec_cfg) 764e3ec7017SPing-Ke Shih param->prec_cfg = *param_ini.prec_cfg; 765e3ec7017SPing-Ke Shih 766e3ec7017SPing-Ke Shih if (param_ini.ch_cfg) 767e3ec7017SPing-Ke Shih param->ch_cfg = param_ini.ch_cfg; 768e3ec7017SPing-Ke Shih 769e3ec7017SPing-Ke Shih memset(¶m->ch_info, 0, sizeof(param->ch_info)); 770e3ec7017SPing-Ke Shih memset(¶m->pub_info, 0, sizeof(param->pub_info)); 771e3ec7017SPing-Ke Shih param->mode = param_ini.mode; 772e3ec7017SPing-Ke Shih 773e3ec7017SPing-Ke Shih return 0; 774e3ec7017SPing-Ke Shih } 775e3ec7017SPing-Ke Shih 776e3ec7017SPing-Ke Shih static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 777e3ec7017SPing-Ke Shih { 778e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 779e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 780e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 781e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 782e3ec7017SPing-Ke Shih 783e3ec7017SPing-Ke Shih if (ch >= RTW89_DMA_CH_NUM) 784e3ec7017SPing-Ke Shih return -EINVAL; 785e3ec7017SPing-Ke Shih 786e3ec7017SPing-Ke Shih if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 787e3ec7017SPing-Ke Shih ch_cfg[ch].max > pub_cfg->pub_max) 788e3ec7017SPing-Ke Shih return -EINVAL; 789e3ec7017SPing-Ke Shih if (ch_cfg[ch].grp >= grp_num) 790e3ec7017SPing-Ke Shih return -EINVAL; 791e3ec7017SPing-Ke Shih 792e3ec7017SPing-Ke Shih return 0; 793e3ec7017SPing-Ke Shih } 794e3ec7017SPing-Ke Shih 795e3ec7017SPing-Ke Shih static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 796e3ec7017SPing-Ke Shih { 797e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 798e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 799e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 800e3ec7017SPing-Ke Shih 801e3ec7017SPing-Ke Shih if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 802e3ec7017SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852A) 803e3ec7017SPing-Ke Shih return 0; 804e3ec7017SPing-Ke Shih else 805e3ec7017SPing-Ke Shih return -EFAULT; 806e3ec7017SPing-Ke Shih } 807e3ec7017SPing-Ke Shih 808e3ec7017SPing-Ke Shih return 0; 809e3ec7017SPing-Ke Shih } 810e3ec7017SPing-Ke Shih 811e3ec7017SPing-Ke Shih static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 812e3ec7017SPing-Ke Shih { 813e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 814e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 815e3ec7017SPing-Ke Shih 816e3ec7017SPing-Ke Shih if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 817c6477cb2SKevin Lo return -EFAULT; 818e3ec7017SPing-Ke Shih 819e3ec7017SPing-Ke Shih return 0; 820e3ec7017SPing-Ke Shih } 821e3ec7017SPing-Ke Shih 822e3ec7017SPing-Ke Shih static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 823e3ec7017SPing-Ke Shih { 824ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 825ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 826e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 827e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 828e3ec7017SPing-Ke Shih int ret = 0; 829e3ec7017SPing-Ke Shih u32 val = 0; 830e3ec7017SPing-Ke Shih 831e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 832e3ec7017SPing-Ke Shih if (ret) 833e3ec7017SPing-Ke Shih return ret; 834e3ec7017SPing-Ke Shih 835e3ec7017SPing-Ke Shih ret = hfc_ch_cfg_chk(rtwdev, ch); 836e3ec7017SPing-Ke Shih if (ret) 837e3ec7017SPing-Ke Shih return ret; 838e3ec7017SPing-Ke Shih 839e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_B1HI) 840e3ec7017SPing-Ke Shih return -EINVAL; 841e3ec7017SPing-Ke Shih 842e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 843e3ec7017SPing-Ke Shih u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 844e3ec7017SPing-Ke Shih (cfg[ch].grp ? B_AX_GRP : 0); 845ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 846e3ec7017SPing-Ke Shih 847e3ec7017SPing-Ke Shih return 0; 848e3ec7017SPing-Ke Shih } 849e3ec7017SPing-Ke Shih 850e3ec7017SPing-Ke Shih static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 851e3ec7017SPing-Ke Shih { 852ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 853ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 854e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 855e3ec7017SPing-Ke Shih struct rtw89_hfc_ch_info *info = param->ch_info; 856e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 857e3ec7017SPing-Ke Shih u32 val; 858e3ec7017SPing-Ke Shih u32 ret; 859e3ec7017SPing-Ke Shih 860e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 861e3ec7017SPing-Ke Shih if (ret) 862e3ec7017SPing-Ke Shih return ret; 863e3ec7017SPing-Ke Shih 864e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_H2C) 865e3ec7017SPing-Ke Shih return -EINVAL; 866e3ec7017SPing-Ke Shih 867ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 868e3ec7017SPing-Ke Shih info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 869e3ec7017SPing-Ke Shih if (ch < RTW89_DMA_H2C) 870e3ec7017SPing-Ke Shih info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 871e3ec7017SPing-Ke Shih else 872e3ec7017SPing-Ke Shih info[ch].used = cfg[ch].min - info[ch].aval; 873e3ec7017SPing-Ke Shih 874e3ec7017SPing-Ke Shih return 0; 875e3ec7017SPing-Ke Shih } 876e3ec7017SPing-Ke Shih 877e3ec7017SPing-Ke Shih static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 878e3ec7017SPing-Ke Shih { 879ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 880ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 881e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 882e3ec7017SPing-Ke Shih u32 val; 883e3ec7017SPing-Ke Shih int ret; 884e3ec7017SPing-Ke Shih 885e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 886e3ec7017SPing-Ke Shih if (ret) 887e3ec7017SPing-Ke Shih return ret; 888e3ec7017SPing-Ke Shih 889e3ec7017SPing-Ke Shih ret = hfc_pub_cfg_chk(rtwdev); 890e3ec7017SPing-Ke Shih if (ret) 891e3ec7017SPing-Ke Shih return ret; 892e3ec7017SPing-Ke Shih 893e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 894e3ec7017SPing-Ke Shih u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 895ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 896e3ec7017SPing-Ke Shih 897e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 898ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 899e3ec7017SPing-Ke Shih 900e3ec7017SPing-Ke Shih return 0; 901e3ec7017SPing-Ke Shih } 902e3ec7017SPing-Ke Shih 903e3ec7017SPing-Ke Shih static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 904e3ec7017SPing-Ke Shih { 905ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 906ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 907e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 908e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 909e3ec7017SPing-Ke Shih struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 910e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 911e3ec7017SPing-Ke Shih u32 val; 912e3ec7017SPing-Ke Shih int ret; 913e3ec7017SPing-Ke Shih 914e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 915e3ec7017SPing-Ke Shih if (ret) 916e3ec7017SPing-Ke Shih return ret; 917e3ec7017SPing-Ke Shih 918ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_info1); 919e3ec7017SPing-Ke Shih info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 920e3ec7017SPing-Ke Shih info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 921ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_info3); 922e3ec7017SPing-Ke Shih info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 923e3ec7017SPing-Ke Shih info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 924e3ec7017SPing-Ke Shih info->pub_aval = 925ab8a5671SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 926e3ec7017SPing-Ke Shih B_AX_PUB_AVAL_PG_MASK); 927e3ec7017SPing-Ke Shih info->wp_aval = 928ab8a5671SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 929e3ec7017SPing-Ke Shih B_AX_WP_AVAL_PG_MASK); 930e3ec7017SPing-Ke Shih 931ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 932e3ec7017SPing-Ke Shih param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 933e3ec7017SPing-Ke Shih param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 934e3ec7017SPing-Ke Shih param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 935e3ec7017SPing-Ke Shih prec_cfg->ch011_full_cond = 936e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 937e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond = 938e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 939e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_full_cond = 940e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 941e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_full_cond = 942e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 943e3ec7017SPing-Ke Shih 944ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 945e3ec7017SPing-Ke Shih prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 946e3ec7017SPing-Ke Shih prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 947e3ec7017SPing-Ke Shih 948ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 949e3ec7017SPing-Ke Shih pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 950e3ec7017SPing-Ke Shih 951ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 952e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 953e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 954e3ec7017SPing-Ke Shih 955ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 956e3ec7017SPing-Ke Shih pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 957e3ec7017SPing-Ke Shih 958ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 959e3ec7017SPing-Ke Shih pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 960e3ec7017SPing-Ke Shih pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 961e3ec7017SPing-Ke Shih 962e3ec7017SPing-Ke Shih ret = hfc_pub_info_chk(rtwdev); 963e3ec7017SPing-Ke Shih if (param->en && ret) 964e3ec7017SPing-Ke Shih return ret; 965e3ec7017SPing-Ke Shih 966e3ec7017SPing-Ke Shih return 0; 967e3ec7017SPing-Ke Shih } 968e3ec7017SPing-Ke Shih 969e3ec7017SPing-Ke Shih static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 970e3ec7017SPing-Ke Shih { 971ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 972ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 973e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 974e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 975e3ec7017SPing-Ke Shih u32 val; 976e3ec7017SPing-Ke Shih 977e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 978ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 979e3ec7017SPing-Ke Shih 980ab8a5671SPing-Ke Shih rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 981e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK, 982e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond); 983e3ec7017SPing-Ke Shih } 984e3ec7017SPing-Ke Shih 985e3ec7017SPing-Ke Shih static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 986e3ec7017SPing-Ke Shih { 987ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 988ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 989e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 990e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 991e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 992e3ec7017SPing-Ke Shih u32 val; 993e3ec7017SPing-Ke Shih 994e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 995e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 996ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 997e3ec7017SPing-Ke Shih 998e3ec7017SPing-Ke Shih val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 999ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1000e3ec7017SPing-Ke Shih 1001e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1002e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH07_MASK) | 1003e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->wp_ch811_prec, 1004e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH811_MASK); 1005ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1006e3ec7017SPing-Ke Shih 1007ab8a5671SPing-Ke Shih val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1008e3ec7017SPing-Ke Shih param->mode, B_AX_HCI_FC_MODE_MASK); 1009e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1010e3ec7017SPing-Ke Shih B_AX_HCI_FC_WD_FULL_COND_MASK); 1011e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1012e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK); 1013e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1014e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1015e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1016e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1017ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1018e3ec7017SPing-Ke Shih } 1019e3ec7017SPing-Ke Shih 1020e3ec7017SPing-Ke Shih static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1021e3ec7017SPing-Ke Shih { 1022ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1023ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 1024e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1025e3ec7017SPing-Ke Shih u32 val; 1026e3ec7017SPing-Ke Shih 1027ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1028e3ec7017SPing-Ke Shih param->en = en; 1029e3ec7017SPing-Ke Shih param->h2c_en = h2c_en; 1030e3ec7017SPing-Ke Shih val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1031e3ec7017SPing-Ke Shih val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1032e3ec7017SPing-Ke Shih (val & ~B_AX_HCI_FC_CH12_EN); 1033ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1034e3ec7017SPing-Ke Shih } 1035e3ec7017SPing-Ke Shih 1036e3ec7017SPing-Ke Shih static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1037e3ec7017SPing-Ke Shih { 1038a1b7163aSPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1039a1b7163aSPing-Ke Shih u32 dma_ch_mask = chip->dma_ch_mask; 1040e3ec7017SPing-Ke Shih u8 ch; 1041e3ec7017SPing-Ke Shih u32 ret = 0; 1042e3ec7017SPing-Ke Shih 1043e3ec7017SPing-Ke Shih if (reset) 1044e3ec7017SPing-Ke Shih ret = hfc_reset_param(rtwdev); 1045e3ec7017SPing-Ke Shih if (ret) 1046e3ec7017SPing-Ke Shih return ret; 1047e3ec7017SPing-Ke Shih 1048e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1049e3ec7017SPing-Ke Shih if (ret) 1050e3ec7017SPing-Ke Shih return ret; 1051e3ec7017SPing-Ke Shih 1052e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, false, false); 1053e3ec7017SPing-Ke Shih 1054e3ec7017SPing-Ke Shih if (!en && h2c_en) { 1055e3ec7017SPing-Ke Shih hfc_h2c_cfg(rtwdev); 1056e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, en, h2c_en); 1057e3ec7017SPing-Ke Shih return ret; 1058e3ec7017SPing-Ke Shih } 1059e3ec7017SPing-Ke Shih 1060e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1061a1b7163aSPing-Ke Shih if (dma_ch_mask & BIT(ch)) 1062a1b7163aSPing-Ke Shih continue; 1063e3ec7017SPing-Ke Shih ret = hfc_ch_ctrl(rtwdev, ch); 1064e3ec7017SPing-Ke Shih if (ret) 1065e3ec7017SPing-Ke Shih return ret; 1066e3ec7017SPing-Ke Shih } 1067e3ec7017SPing-Ke Shih 1068e3ec7017SPing-Ke Shih ret = hfc_pub_ctrl(rtwdev); 1069e3ec7017SPing-Ke Shih if (ret) 1070e3ec7017SPing-Ke Shih return ret; 1071e3ec7017SPing-Ke Shih 1072e3ec7017SPing-Ke Shih hfc_mix_cfg(rtwdev); 1073e3ec7017SPing-Ke Shih if (en || h2c_en) { 1074e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, en, h2c_en); 1075e3ec7017SPing-Ke Shih udelay(10); 1076e3ec7017SPing-Ke Shih } 1077e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1078a1b7163aSPing-Ke Shih if (dma_ch_mask & BIT(ch)) 1079a1b7163aSPing-Ke Shih continue; 1080e3ec7017SPing-Ke Shih ret = hfc_upd_ch_info(rtwdev, ch); 1081e3ec7017SPing-Ke Shih if (ret) 1082e3ec7017SPing-Ke Shih return ret; 1083e3ec7017SPing-Ke Shih } 1084e3ec7017SPing-Ke Shih ret = hfc_upd_mix_info(rtwdev); 1085e3ec7017SPing-Ke Shih 1086e3ec7017SPing-Ke Shih return ret; 1087e3ec7017SPing-Ke Shih } 1088e3ec7017SPing-Ke Shih 1089e3ec7017SPing-Ke Shih #define PWR_POLL_CNT 2000 1090e3ec7017SPing-Ke Shih static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1091e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cfg) 1092e3ec7017SPing-Ke Shih { 1093e3ec7017SPing-Ke Shih u8 val = 0; 1094e3ec7017SPing-Ke Shih int ret; 1095e3ec7017SPing-Ke Shih u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1096e3ec7017SPing-Ke Shih cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1097e3ec7017SPing-Ke Shih 1098e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1099e3ec7017SPing-Ke Shih 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1100e3ec7017SPing-Ke Shih 1101e3ec7017SPing-Ke Shih if (!ret) 1102e3ec7017SPing-Ke Shih return 0; 1103e3ec7017SPing-Ke Shih 1104e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1105e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1106e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1107e3ec7017SPing-Ke Shih 1108e3ec7017SPing-Ke Shih return -EBUSY; 1109e3ec7017SPing-Ke Shih } 1110e3ec7017SPing-Ke Shih 1111e3ec7017SPing-Ke Shih static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1112e3ec7017SPing-Ke Shih u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1113e3ec7017SPing-Ke Shih { 1114e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cur_cfg; 1115e3ec7017SPing-Ke Shih u32 addr; 1116e3ec7017SPing-Ke Shih u8 val; 1117e3ec7017SPing-Ke Shih 1118e3ec7017SPing-Ke Shih for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1119e3ec7017SPing-Ke Shih if (!(cur_cfg->intf_msk & intf_msk) || 1120e3ec7017SPing-Ke Shih !(cur_cfg->cv_msk & cv_msk)) 1121e3ec7017SPing-Ke Shih continue; 1122e3ec7017SPing-Ke Shih 1123e3ec7017SPing-Ke Shih switch (cur_cfg->cmd) { 1124e3ec7017SPing-Ke Shih case PWR_CMD_WRITE: 1125e3ec7017SPing-Ke Shih addr = cur_cfg->addr; 1126e3ec7017SPing-Ke Shih 1127e3ec7017SPing-Ke Shih if (cur_cfg->base == PWR_BASE_SDIO) 1128e3ec7017SPing-Ke Shih addr |= SDIO_LOCAL_BASE_ADDR; 1129e3ec7017SPing-Ke Shih 1130e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, addr); 1131e3ec7017SPing-Ke Shih val &= ~(cur_cfg->msk); 1132e3ec7017SPing-Ke Shih val |= (cur_cfg->val & cur_cfg->msk); 1133e3ec7017SPing-Ke Shih 1134e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, addr, val); 1135e3ec7017SPing-Ke Shih break; 1136e3ec7017SPing-Ke Shih case PWR_CMD_POLL: 1137e3ec7017SPing-Ke Shih if (pwr_cmd_poll(rtwdev, cur_cfg)) 1138e3ec7017SPing-Ke Shih return -EBUSY; 1139e3ec7017SPing-Ke Shih break; 1140e3ec7017SPing-Ke Shih case PWR_CMD_DELAY: 1141e3ec7017SPing-Ke Shih if (cur_cfg->val == PWR_DELAY_US) 1142e3ec7017SPing-Ke Shih udelay(cur_cfg->addr); 1143e3ec7017SPing-Ke Shih else 1144e3ec7017SPing-Ke Shih fsleep(cur_cfg->addr * 1000); 1145e3ec7017SPing-Ke Shih break; 1146e3ec7017SPing-Ke Shih default: 1147e3ec7017SPing-Ke Shih return -EINVAL; 1148e3ec7017SPing-Ke Shih } 1149e3ec7017SPing-Ke Shih } 1150e3ec7017SPing-Ke Shih 1151e3ec7017SPing-Ke Shih return 0; 1152e3ec7017SPing-Ke Shih } 1153e3ec7017SPing-Ke Shih 1154e3ec7017SPing-Ke Shih static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1155e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq) 1156e3ec7017SPing-Ke Shih { 1157e3ec7017SPing-Ke Shih int ret; 1158e3ec7017SPing-Ke Shih 1159e3ec7017SPing-Ke Shih for (; *cfg_seq; cfg_seq++) { 1160e3ec7017SPing-Ke Shih ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1161e3ec7017SPing-Ke Shih PWR_INTF_MSK_PCIE, *cfg_seq); 1162e3ec7017SPing-Ke Shih if (ret) 1163e3ec7017SPing-Ke Shih return -EBUSY; 1164e3ec7017SPing-Ke Shih } 1165e3ec7017SPing-Ke Shih 1166e3ec7017SPing-Ke Shih return 0; 1167e3ec7017SPing-Ke Shih } 1168e3ec7017SPing-Ke Shih 1169e3ec7017SPing-Ke Shih static enum rtw89_rpwm_req_pwr_state 1170e3ec7017SPing-Ke Shih rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1171e3ec7017SPing-Ke Shih { 1172e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 1173e3ec7017SPing-Ke Shih 1174e3ec7017SPing-Ke Shih switch (rtwdev->ps_mode) { 1175e3ec7017SPing-Ke Shih case RTW89_PS_MODE_RFOFF: 1176e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1177e3ec7017SPing-Ke Shih break; 1178e3ec7017SPing-Ke Shih case RTW89_PS_MODE_CLK_GATED: 1179e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1180e3ec7017SPing-Ke Shih break; 1181e3ec7017SPing-Ke Shih case RTW89_PS_MODE_PWR_GATED: 1182e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1183e3ec7017SPing-Ke Shih break; 1184e3ec7017SPing-Ke Shih default: 1185e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1186e3ec7017SPing-Ke Shih break; 1187e3ec7017SPing-Ke Shih } 1188e3ec7017SPing-Ke Shih return state; 1189e3ec7017SPing-Ke Shih } 1190e3ec7017SPing-Ke Shih 1191e3ec7017SPing-Ke Shih static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 11927bfd05ffSChin-Yen Lee enum rtw89_rpwm_req_pwr_state req_pwr_state, 11937bfd05ffSChin-Yen Lee bool notify_wake) 1194e3ec7017SPing-Ke Shih { 1195e3ec7017SPing-Ke Shih u16 request; 1196e3ec7017SPing-Ke Shih 11977bfd05ffSChin-Yen Lee spin_lock_bh(&rtwdev->rpwm_lock); 11987bfd05ffSChin-Yen Lee 1199e3ec7017SPing-Ke Shih request = rtw89_read16(rtwdev, R_AX_RPWM); 1200e3ec7017SPing-Ke Shih request ^= request | PS_RPWM_TOGGLE; 12017bfd05ffSChin-Yen Lee request |= req_pwr_state; 1202e3ec7017SPing-Ke Shih 12037bfd05ffSChin-Yen Lee if (notify_wake) { 12047bfd05ffSChin-Yen Lee request |= PS_RPWM_NOTIFY_WAKE; 12057bfd05ffSChin-Yen Lee } else { 1206e3ec7017SPing-Ke Shih rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1207e3ec7017SPing-Ke Shih RPWM_SEQ_NUM_MAX; 12087bfd05ffSChin-Yen Lee request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 12097bfd05ffSChin-Yen Lee rtwdev->mac.rpwm_seq_num); 1210e3ec7017SPing-Ke Shih 1211e3ec7017SPing-Ke Shih if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1212e3ec7017SPing-Ke Shih request |= PS_RPWM_ACK; 12137bfd05ffSChin-Yen Lee } 1214e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 12157bfd05ffSChin-Yen Lee 12167bfd05ffSChin-Yen Lee spin_unlock_bh(&rtwdev->rpwm_lock); 1217e3ec7017SPing-Ke Shih } 1218e3ec7017SPing-Ke Shih 1219e3ec7017SPing-Ke Shih static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1220e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state req_pwr_state) 1221e3ec7017SPing-Ke Shih { 1222e3ec7017SPing-Ke Shih bool request_deep_mode; 1223e3ec7017SPing-Ke Shih bool in_deep_mode; 1224e3ec7017SPing-Ke Shih u8 rpwm_req_num; 1225e3ec7017SPing-Ke Shih u8 cpwm_rsp_seq; 1226e3ec7017SPing-Ke Shih u8 cpwm_seq; 1227e3ec7017SPing-Ke Shih u8 cpwm_status; 1228e3ec7017SPing-Ke Shih 1229e3ec7017SPing-Ke Shih if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1230e3ec7017SPing-Ke Shih request_deep_mode = true; 1231e3ec7017SPing-Ke Shih else 1232e3ec7017SPing-Ke Shih request_deep_mode = false; 1233e3ec7017SPing-Ke Shih 1234e3ec7017SPing-Ke Shih if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1235e3ec7017SPing-Ke Shih in_deep_mode = true; 1236e3ec7017SPing-Ke Shih else 1237e3ec7017SPing-Ke Shih in_deep_mode = false; 1238e3ec7017SPing-Ke Shih 1239e3ec7017SPing-Ke Shih if (request_deep_mode != in_deep_mode) 1240e3ec7017SPing-Ke Shih return -EPERM; 1241e3ec7017SPing-Ke Shih 1242e3ec7017SPing-Ke Shih if (request_deep_mode) 1243e3ec7017SPing-Ke Shih return 0; 1244e3ec7017SPing-Ke Shih 1245e3ec7017SPing-Ke Shih rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1246e1757e80SPing-Ke Shih cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1247e3ec7017SPing-Ke Shih PS_CPWM_RSP_SEQ_NUM); 1248e3ec7017SPing-Ke Shih 1249e3ec7017SPing-Ke Shih if (rpwm_req_num != cpwm_rsp_seq) 1250e3ec7017SPing-Ke Shih return -EPERM; 1251e3ec7017SPing-Ke Shih 1252e3ec7017SPing-Ke Shih rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1253e3ec7017SPing-Ke Shih CPWM_SEQ_NUM_MAX; 1254e3ec7017SPing-Ke Shih 1255e1757e80SPing-Ke Shih cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1256e3ec7017SPing-Ke Shih if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1257e3ec7017SPing-Ke Shih return -EPERM; 1258e3ec7017SPing-Ke Shih 1259e1757e80SPing-Ke Shih cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1260e3ec7017SPing-Ke Shih if (cpwm_status != req_pwr_state) 1261e3ec7017SPing-Ke Shih return -EPERM; 1262e3ec7017SPing-Ke Shih 1263e3ec7017SPing-Ke Shih return 0; 1264e3ec7017SPing-Ke Shih } 1265e3ec7017SPing-Ke Shih 1266e3ec7017SPing-Ke Shih void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1267e3ec7017SPing-Ke Shih { 1268e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 126939a76521SPing-Ke Shih unsigned long delay = enter ? 10 : 150; 1270e3ec7017SPing-Ke Shih int ret; 127148c0e347SChin-Yen Lee int i; 1272e3ec7017SPing-Ke Shih 1273e3ec7017SPing-Ke Shih if (enter) 1274e3ec7017SPing-Ke Shih state = rtw89_mac_get_req_pwr_state(rtwdev); 1275e3ec7017SPing-Ke Shih else 1276e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1277e3ec7017SPing-Ke Shih 127848c0e347SChin-Yen Lee for (i = 0; i < RPWM_TRY_CNT; i++) { 12797bfd05ffSChin-Yen Lee rtw89_mac_send_rpwm(rtwdev, state, false); 128048c0e347SChin-Yen Lee ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 128148c0e347SChin-Yen Lee !ret, delay, 15000, false, 128248c0e347SChin-Yen Lee rtwdev, state); 128348c0e347SChin-Yen Lee if (!ret) 128448c0e347SChin-Yen Lee break; 128548c0e347SChin-Yen Lee 128648c0e347SChin-Yen Lee if (i == RPWM_TRY_CNT - 1) 1287e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1288e3ec7017SPing-Ke Shih enter ? "entering" : "leaving"); 128948c0e347SChin-Yen Lee else 129048c0e347SChin-Yen Lee rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 129148c0e347SChin-Yen Lee "%d time firmware failed to ack for %s ps mode\n", 129248c0e347SChin-Yen Lee i + 1, enter ? "entering" : "leaving"); 129348c0e347SChin-Yen Lee } 1294e3ec7017SPing-Ke Shih } 1295e3ec7017SPing-Ke Shih 12967bfd05ffSChin-Yen Lee void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 12977bfd05ffSChin-Yen Lee { 12987bfd05ffSChin-Yen Lee enum rtw89_rpwm_req_pwr_state state; 12997bfd05ffSChin-Yen Lee 13007bfd05ffSChin-Yen Lee state = rtw89_mac_get_req_pwr_state(rtwdev); 13017bfd05ffSChin-Yen Lee rtw89_mac_send_rpwm(rtwdev, state, true); 13027bfd05ffSChin-Yen Lee } 13037bfd05ffSChin-Yen Lee 1304e3ec7017SPing-Ke Shih static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1305e3ec7017SPing-Ke Shih { 1306e3ec7017SPing-Ke Shih #define PWR_ACT 1 1307e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1308e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq; 13092a7e54dbSPing-Ke Shih int (*cfg_func)(struct rtw89_dev *rtwdev); 1310e3ec7017SPing-Ke Shih int ret; 1311e3ec7017SPing-Ke Shih u8 val; 1312e3ec7017SPing-Ke Shih 13132a7e54dbSPing-Ke Shih if (on) { 1314e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_on_seq; 13152a7e54dbSPing-Ke Shih cfg_func = chip->ops->pwr_on_func; 13162a7e54dbSPing-Ke Shih } else { 1317e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_off_seq; 13182a7e54dbSPing-Ke Shih cfg_func = chip->ops->pwr_off_func; 13192a7e54dbSPing-Ke Shih } 1320e3ec7017SPing-Ke Shih 1321e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1322e3ec7017SPing-Ke Shih __rtw89_leave_ps_mode(rtwdev); 1323e3ec7017SPing-Ke Shih 1324e3ec7017SPing-Ke Shih val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1325e3ec7017SPing-Ke Shih if (on && val == PWR_ACT) { 1326e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC has already powered on\n"); 1327e3ec7017SPing-Ke Shih return -EBUSY; 1328e3ec7017SPing-Ke Shih } 1329e3ec7017SPing-Ke Shih 13302a7e54dbSPing-Ke Shih ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1331e3ec7017SPing-Ke Shih if (ret) 1332e3ec7017SPing-Ke Shih return ret; 1333e3ec7017SPing-Ke Shih 1334e3ec7017SPing-Ke Shih if (on) { 1335e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1336e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1337e3ec7017SPing-Ke Shih } else { 1338e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1339e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1340e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1341967439c7SZong-Zhe Yang rtw89_set_entity_state(rtwdev, false); 1342e3ec7017SPing-Ke Shih } 1343e3ec7017SPing-Ke Shih 1344e3ec7017SPing-Ke Shih return 0; 1345e3ec7017SPing-Ke Shih #undef PWR_ACT 1346e3ec7017SPing-Ke Shih } 1347e3ec7017SPing-Ke Shih 1348e3ec7017SPing-Ke Shih void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1349e3ec7017SPing-Ke Shih { 1350e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 1351e3ec7017SPing-Ke Shih } 1352e3ec7017SPing-Ke Shih 1353e3ec7017SPing-Ke Shih static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1354e3ec7017SPing-Ke Shih { 1355e3ec7017SPing-Ke Shih u32 func_en = 0; 1356e3ec7017SPing-Ke Shih u32 ck_en = 0; 1357e3ec7017SPing-Ke Shih u32 c1pc_en = 0; 1358e3ec7017SPing-Ke Shih u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1359e3ec7017SPing-Ke Shih u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1360e3ec7017SPing-Ke Shih 1361e3ec7017SPing-Ke Shih func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1362e3ec7017SPing-Ke Shih B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 13635cb5562dSPing-Ke Shih B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 13645cb5562dSPing-Ke Shih B_AX_CMAC_CRPRT; 1365e3ec7017SPing-Ke Shih ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1366e3ec7017SPing-Ke Shih B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1367e3ec7017SPing-Ke Shih B_AX_RMAC_CKEN; 1368e3ec7017SPing-Ke Shih c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1369e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1370e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1371e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1372e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1373e3ec7017SPing-Ke Shih 1374e3ec7017SPing-Ke Shih if (en) { 1375e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1376e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1377e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1378e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1379e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1380e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1381e3ec7017SPing-Ke Shih } 1382e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1383e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1384e3ec7017SPing-Ke Shih } else { 1385e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1386e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1387e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1388e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1389e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1390e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1391e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1392e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1393e3ec7017SPing-Ke Shih } 1394e3ec7017SPing-Ke Shih } 1395e3ec7017SPing-Ke Shih 1396e3ec7017SPing-Ke Shih return 0; 1397e3ec7017SPing-Ke Shih } 1398e3ec7017SPing-Ke Shih 1399e3ec7017SPing-Ke Shih static int dmac_func_en(struct rtw89_dev *rtwdev) 1400e3ec7017SPing-Ke Shih { 1401828a4396SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1402e3ec7017SPing-Ke Shih u32 val32; 1403e3ec7017SPing-Ke Shih 1404828a4396SChia-Yuan Li if (chip_id == RTL8852C) 1405828a4396SChia-Yuan Li val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1406828a4396SChia-Yuan Li B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1407828a4396SChia-Yuan Li B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1408828a4396SChia-Yuan Li B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1409828a4396SChia-Yuan Li B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1410828a4396SChia-Yuan Li B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1411828a4396SChia-Yuan Li B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1412828a4396SChia-Yuan Li else 1413828a4396SChia-Yuan Li val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1414828a4396SChia-Yuan Li B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1415828a4396SChia-Yuan Li B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1416828a4396SChia-Yuan Li B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1417828a4396SChia-Yuan Li B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1418828a4396SChia-Yuan Li B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1419828a4396SChia-Yuan Li B_AX_DMAC_CRPRT); 1420e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1421e3ec7017SPing-Ke Shih 1422e3ec7017SPing-Ke Shih val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1423e3ec7017SPing-Ke Shih B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1424e3ec7017SPing-Ke Shih B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1425828a4396SChia-Yuan Li B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1426e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1427e3ec7017SPing-Ke Shih 142843863efeSChangcheng Deng return 0; 1429e3ec7017SPing-Ke Shih } 1430e3ec7017SPing-Ke Shih 1431e3ec7017SPing-Ke Shih static int chip_func_en(struct rtw89_dev *rtwdev) 1432e3ec7017SPing-Ke Shih { 1433828a4396SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1434828a4396SChia-Yuan Li 143514b6e9f4SPing-Ke Shih if (chip_id == RTL8852A || chip_id == RTL8852B) 143614b6e9f4SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1437828a4396SChia-Yuan Li B_AX_OCP_L1_MASK); 1438e3ec7017SPing-Ke Shih 1439e3ec7017SPing-Ke Shih return 0; 1440e3ec7017SPing-Ke Shih } 1441e3ec7017SPing-Ke Shih 1442e3ec7017SPing-Ke Shih static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1443e3ec7017SPing-Ke Shih { 1444e3ec7017SPing-Ke Shih int ret; 1445e3ec7017SPing-Ke Shih 1446e3ec7017SPing-Ke Shih ret = dmac_func_en(rtwdev); 1447e3ec7017SPing-Ke Shih if (ret) 1448e3ec7017SPing-Ke Shih return ret; 1449e3ec7017SPing-Ke Shih 1450e3ec7017SPing-Ke Shih ret = cmac_func_en(rtwdev, 0, true); 1451e3ec7017SPing-Ke Shih if (ret) 1452e3ec7017SPing-Ke Shih return ret; 1453e3ec7017SPing-Ke Shih 1454e3ec7017SPing-Ke Shih ret = chip_func_en(rtwdev); 1455e3ec7017SPing-Ke Shih if (ret) 1456e3ec7017SPing-Ke Shih return ret; 1457e3ec7017SPing-Ke Shih 1458e3ec7017SPing-Ke Shih return ret; 1459e3ec7017SPing-Ke Shih } 1460e3ec7017SPing-Ke Shih 146130645118SPing-Ke Shih const struct rtw89_mac_size_set rtw89_mac_size = { 146230645118SPing-Ke Shih .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1463e3ec7017SPing-Ke Shih /* PCIE 64 */ 146430645118SPing-Ke Shih .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1465e3ec7017SPing-Ke Shih /* DLFW */ 146630645118SPing-Ke Shih .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1467a1cb0971SPing-Ke Shih /* PCIE 64 */ 1468a1cb0971SPing-Ke Shih .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1469c0426c44SPing-Ke Shih /* 8852B PCIE SCC */ 1470c0426c44SPing-Ke Shih .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1471a1cb0971SPing-Ke Shih /* DLFW */ 1472a1cb0971SPing-Ke Shih .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 147379d099e0SPing-Ke Shih /* 8852C DLFW */ 147430645118SPing-Ke Shih .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 147579d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 147630645118SPing-Ke Shih .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1477e3ec7017SPing-Ke Shih /* PCIE */ 147830645118SPing-Ke Shih .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1479e3ec7017SPing-Ke Shih /* DLFW */ 148030645118SPing-Ke Shih .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1481a1cb0971SPing-Ke Shih /* PCIE 64 */ 1482a1cb0971SPing-Ke Shih .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1483a1cb0971SPing-Ke Shih /* DLFW */ 1484a1cb0971SPing-Ke Shih .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 148579d099e0SPing-Ke Shih /* 8852C DLFW */ 148630645118SPing-Ke Shih .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 148779d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 148830645118SPing-Ke Shih .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1489e3ec7017SPing-Ke Shih /* PCIE 64 */ 149030645118SPing-Ke Shih .wde_qt0 = {3792, 196, 0, 107,}, 1491e3ec7017SPing-Ke Shih /* DLFW */ 149230645118SPing-Ke Shih .wde_qt4 = {0, 0, 0, 0,}, 1493a1cb0971SPing-Ke Shih /* PCIE 64 */ 1494a1cb0971SPing-Ke Shih .wde_qt6 = {448, 48, 0, 16,}, 1495c0426c44SPing-Ke Shih /* 8852B PCIE SCC */ 1496c0426c44SPing-Ke Shih .wde_qt7 = {446, 48, 0, 16,}, 149779d099e0SPing-Ke Shih /* 8852C DLFW */ 149830645118SPing-Ke Shih .wde_qt17 = {0, 0, 0, 0,}, 149979d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 150030645118SPing-Ke Shih .wde_qt18 = {3228, 60, 0, 40,}, 1501e3ec7017SPing-Ke Shih /* PCIE SCC */ 150230645118SPing-Ke Shih .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1503e3ec7017SPing-Ke Shih /* PCIE SCC */ 150430645118SPing-Ke Shih .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1505e3ec7017SPing-Ke Shih /* DLFW */ 150630645118SPing-Ke Shih .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1507a1cb0971SPing-Ke Shih /* PCIE 64 */ 1508a1cb0971SPing-Ke Shih .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 150979d099e0SPing-Ke Shih /* DLFW 52C */ 151030645118SPing-Ke Shih .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 151179d099e0SPing-Ke Shih /* DLFW 52C */ 151230645118SPing-Ke Shih .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 151379d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 151430645118SPing-Ke Shih .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 151579d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 151630645118SPing-Ke Shih .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1517a1cb0971SPing-Ke Shih /* PCIE 64 */ 1518a1cb0971SPing-Ke Shih .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 15197a68ec3dSChih-Kang Chang /* 8852A PCIE WOW */ 15207a68ec3dSChih-Kang Chang .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 15216863ad91SChin-Yen Lee /* 8852B PCIE WOW */ 15226863ad91SChin-Yen Lee .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 152385d1539cSPing-Ke Shih /* 8851B PCIE WOW */ 152485d1539cSPing-Ke Shih .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 152579d099e0SPing-Ke Shih }; 152630645118SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_size); 152779d099e0SPing-Ke Shih 1528e3ec7017SPing-Ke Shih static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1529e3ec7017SPing-Ke Shih enum rtw89_qta_mode mode) 1530e3ec7017SPing-Ke Shih { 1531e3ec7017SPing-Ke Shih struct rtw89_mac_info *mac = &rtwdev->mac; 1532e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 1533e3ec7017SPing-Ke Shih 1534e3ec7017SPing-Ke Shih cfg = &rtwdev->chip->dle_mem[mode]; 1535e3ec7017SPing-Ke Shih if (!cfg) 1536e3ec7017SPing-Ke Shih return NULL; 1537e3ec7017SPing-Ke Shih 1538e3ec7017SPing-Ke Shih if (cfg->mode != mode) { 1539e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1540e3ec7017SPing-Ke Shih return NULL; 1541e3ec7017SPing-Ke Shih } 1542e3ec7017SPing-Ke Shih 1543e3ec7017SPing-Ke Shih mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1544e3ec7017SPing-Ke Shih mac->dle_info.qta_mode = mode; 1545e3ec7017SPing-Ke Shih mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1546e3ec7017SPing-Ke Shih mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1547e3ec7017SPing-Ke Shih 1548e3ec7017SPing-Ke Shih return cfg; 1549e3ec7017SPing-Ke Shih } 1550e3ec7017SPing-Ke Shih 155141d56769SChih-Kang Chang static bool mac_is_txq_empty(struct rtw89_dev *rtwdev) 155241d56769SChih-Kang Chang { 155341d56769SChih-Kang Chang struct rtw89_mac_dle_dfi_qempty qempty; 155441d56769SChih-Kang Chang u32 qnum, qtmp, val32, msk32; 155541d56769SChih-Kang Chang int i, j, ret; 155641d56769SChih-Kang Chang 155741d56769SChih-Kang Chang qnum = rtwdev->chip->wde_qempty_acq_num; 155841d56769SChih-Kang Chang qempty.dle_type = DLE_CTRL_TYPE_WDE; 155941d56769SChih-Kang Chang 156041d56769SChih-Kang Chang for (i = 0; i < qnum; i++) { 156141d56769SChih-Kang Chang qempty.grpsel = i; 156241d56769SChih-Kang Chang ret = dle_dfi_qempty(rtwdev, &qempty); 156341d56769SChih-Kang Chang if (ret) { 156441d56769SChih-Kang Chang rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 156541d56769SChih-Kang Chang return false; 156641d56769SChih-Kang Chang } 156741d56769SChih-Kang Chang qtmp = qempty.qempty; 156841d56769SChih-Kang Chang for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 156941d56769SChih-Kang Chang val32 = FIELD_GET(QEMP_ACQ_GRP_QSEL_MASK, qtmp); 157041d56769SChih-Kang Chang if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 157141d56769SChih-Kang Chang return false; 157241d56769SChih-Kang Chang qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 157341d56769SChih-Kang Chang } 157441d56769SChih-Kang Chang } 157541d56769SChih-Kang Chang 157641d56769SChih-Kang Chang qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel; 157741d56769SChih-Kang Chang ret = dle_dfi_qempty(rtwdev, &qempty); 157841d56769SChih-Kang Chang if (ret) { 157941d56769SChih-Kang Chang rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 158041d56769SChih-Kang Chang return false; 158141d56769SChih-Kang Chang } 158241d56769SChih-Kang Chang msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 158341d56769SChih-Kang Chang if ((qempty.qempty & msk32) != msk32) 158441d56769SChih-Kang Chang return false; 158541d56769SChih-Kang Chang 158641d56769SChih-Kang Chang if (rtwdev->dbcc_en) { 158741d56769SChih-Kang Chang msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 158841d56769SChih-Kang Chang if ((qempty.qempty & msk32) != msk32) 158941d56769SChih-Kang Chang return false; 159041d56769SChih-Kang Chang } 159141d56769SChih-Kang Chang 159241d56769SChih-Kang Chang msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 159341d56769SChih-Kang Chang B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 159441d56769SChih-Kang Chang B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 159541d56769SChih-Kang Chang B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 159641d56769SChih-Kang Chang B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 159741d56769SChih-Kang Chang B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 159841d56769SChih-Kang Chang B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 159941d56769SChih-Kang Chang B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 160041d56769SChih-Kang Chang val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 160141d56769SChih-Kang Chang 160241d56769SChih-Kang Chang return (val32 & msk32) == msk32; 160341d56769SChih-Kang Chang } 160441d56769SChih-Kang Chang 1605e3ec7017SPing-Ke Shih static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1606e3ec7017SPing-Ke Shih const struct rtw89_dle_size *ple) 1607e3ec7017SPing-Ke Shih { 1608e3ec7017SPing-Ke Shih return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1609e3ec7017SPing-Ke Shih ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1610e3ec7017SPing-Ke Shih } 1611e3ec7017SPing-Ke Shih 16125f8c35b9SPing-Ke Shih static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 16135f8c35b9SPing-Ke Shih enum rtw89_qta_mode mode) 16145f8c35b9SPing-Ke Shih { 16155f8c35b9SPing-Ke Shih u32 size = rtwdev->chip->fifo_size; 16165f8c35b9SPing-Ke Shih 16175f8c35b9SPing-Ke Shih if (mode == RTW89_QTA_SCC) 16185f8c35b9SPing-Ke Shih size -= rtwdev->chip->dle_scc_rsvd_size; 16195f8c35b9SPing-Ke Shih 16205f8c35b9SPing-Ke Shih return size; 16215f8c35b9SPing-Ke Shih } 16225f8c35b9SPing-Ke Shih 1623e3ec7017SPing-Ke Shih static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1624e3ec7017SPing-Ke Shih { 1625e3ec7017SPing-Ke Shih if (enable) 1626e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1627e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1628e3ec7017SPing-Ke Shih else 1629e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1630e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1631e3ec7017SPing-Ke Shih } 1632e3ec7017SPing-Ke Shih 1633e3ec7017SPing-Ke Shih static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1634e3ec7017SPing-Ke Shih { 16355c3afcbaSPing-Ke Shih u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 16365c3afcbaSPing-Ke Shih 16375c3afcbaSPing-Ke Shih if (enable) { 16385c3afcbaSPing-Ke Shih if (rtwdev->chip->chip_id == RTL8851B) 16395c3afcbaSPing-Ke Shih val |= B_AX_AXIDMA_CLK_EN; 16405c3afcbaSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 16415c3afcbaSPing-Ke Shih } else { 16425c3afcbaSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 16435c3afcbaSPing-Ke Shih } 1644e3ec7017SPing-Ke Shih } 1645e3ec7017SPing-Ke Shih 1646e3ec7017SPing-Ke Shih static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1647e3ec7017SPing-Ke Shih { 1648e3ec7017SPing-Ke Shih const struct rtw89_dle_size *size_cfg; 1649e3ec7017SPing-Ke Shih u32 val; 1650e3ec7017SPing-Ke Shih u8 bound = 0; 1651e3ec7017SPing-Ke Shih 1652e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1653e3ec7017SPing-Ke Shih size_cfg = cfg->wde_size; 1654e3ec7017SPing-Ke Shih 1655e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1656e3ec7017SPing-Ke Shih default: 1657e3ec7017SPing-Ke Shih case RTW89_WDE_PG_64: 1658e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1659e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1660e3ec7017SPing-Ke Shih break; 1661e3ec7017SPing-Ke Shih case RTW89_WDE_PG_128: 1662e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1663e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1664e3ec7017SPing-Ke Shih break; 1665e3ec7017SPing-Ke Shih case RTW89_WDE_PG_256: 1666e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1667e3ec7017SPing-Ke Shih return -EINVAL; 1668e3ec7017SPing-Ke Shih } 1669e3ec7017SPing-Ke Shih 1670e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1671e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1672e3ec7017SPing-Ke Shih B_AX_WDE_FREE_PAGE_NUM_MASK); 1673e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1674e3ec7017SPing-Ke Shih 1675e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1676e3ec7017SPing-Ke Shih bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1677e3ec7017SPing-Ke Shih * size_cfg->pge_size / DLE_BOUND_UNIT; 1678e3ec7017SPing-Ke Shih size_cfg = cfg->ple_size; 1679e3ec7017SPing-Ke Shih 1680e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1681e3ec7017SPing-Ke Shih default: 1682e3ec7017SPing-Ke Shih case RTW89_PLE_PG_64: 1683e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1684e3ec7017SPing-Ke Shih return -EINVAL; 1685e3ec7017SPing-Ke Shih case RTW89_PLE_PG_128: 1686e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1687e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1688e3ec7017SPing-Ke Shih break; 1689e3ec7017SPing-Ke Shih case RTW89_PLE_PG_256: 1690e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1691e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1692e3ec7017SPing-Ke Shih break; 1693e3ec7017SPing-Ke Shih } 1694e3ec7017SPing-Ke Shih 1695e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1696e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1697e3ec7017SPing-Ke Shih B_AX_PLE_FREE_PAGE_NUM_MASK); 1698e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1699e3ec7017SPing-Ke Shih 1700e3ec7017SPing-Ke Shih return 0; 1701e3ec7017SPing-Ke Shih } 1702e3ec7017SPing-Ke Shih 1703e3ec7017SPing-Ke Shih #define INVALID_QT_WCPU U16_MAX 1704e3ec7017SPing-Ke Shih #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1705e3ec7017SPing-Ke Shih do { \ 1706525c06c8SPing-Ke Shih val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1707525c06c8SPing-Ke Shih u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1708e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, \ 1709e3ec7017SPing-Ke Shih R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1710e3ec7017SPing-Ke Shih val); \ 1711e3ec7017SPing-Ke Shih } while (0) 1712e3ec7017SPing-Ke Shih #define SET_QUOTA(_x, _module, _idx) \ 1713e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1714e3ec7017SPing-Ke Shih 1715e3ec7017SPing-Ke Shih static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1716e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *min_cfg, 1717e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *max_cfg, 1718e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 1719e3ec7017SPing-Ke Shih { 1720e3ec7017SPing-Ke Shih u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1721e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu : min_cfg->wcpu; 1722e3ec7017SPing-Ke Shih u32 val; 1723e3ec7017SPing-Ke Shih 1724e3ec7017SPing-Ke Shih SET_QUOTA(hif, WDE, 0); 1725e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1726e3ec7017SPing-Ke Shih SET_QUOTA(pkt_in, WDE, 3); 1727e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, WDE, 4); 1728e3ec7017SPing-Ke Shih } 1729e3ec7017SPing-Ke Shih 1730e3ec7017SPing-Ke Shih static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1731e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *min_cfg, 1732e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *max_cfg) 1733e3ec7017SPing-Ke Shih { 1734e3ec7017SPing-Ke Shih u32 val; 1735e3ec7017SPing-Ke Shih 1736e3ec7017SPing-Ke Shih SET_QUOTA(cma0_tx, PLE, 0); 1737e3ec7017SPing-Ke Shih SET_QUOTA(cma1_tx, PLE, 1); 1738e3ec7017SPing-Ke Shih SET_QUOTA(c2h, PLE, 2); 1739e3ec7017SPing-Ke Shih SET_QUOTA(h2c, PLE, 3); 1740e3ec7017SPing-Ke Shih SET_QUOTA(wcpu, PLE, 4); 1741e3ec7017SPing-Ke Shih SET_QUOTA(mpdu_proc, PLE, 5); 1742e3ec7017SPing-Ke Shih SET_QUOTA(cma0_dma, PLE, 6); 1743e3ec7017SPing-Ke Shih SET_QUOTA(cma1_dma, PLE, 7); 1744e3ec7017SPing-Ke Shih SET_QUOTA(bb_rpt, PLE, 8); 1745e3ec7017SPing-Ke Shih SET_QUOTA(wd_rel, PLE, 9); 1746e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, PLE, 10); 174779d099e0SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852C) 174879d099e0SPing-Ke Shih SET_QUOTA(tx_rpt, PLE, 11); 1749e3ec7017SPing-Ke Shih } 1750e3ec7017SPing-Ke Shih 17517a68ec3dSChih-Kang Chang int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 17527a68ec3dSChih-Kang Chang { 17537a68ec3dSChih-Kang Chang const struct rtw89_ple_quota *min_cfg, *max_cfg; 17547a68ec3dSChih-Kang Chang const struct rtw89_dle_mem *cfg; 17557a68ec3dSChih-Kang Chang u32 val; 17567a68ec3dSChih-Kang Chang 17577a68ec3dSChih-Kang Chang if (rtwdev->chip->chip_id == RTL8852C) 17587a68ec3dSChih-Kang Chang return 0; 17597a68ec3dSChih-Kang Chang 17607a68ec3dSChih-Kang Chang if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 17617a68ec3dSChih-Kang Chang rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 17627a68ec3dSChih-Kang Chang return -EINVAL; 17637a68ec3dSChih-Kang Chang } 17647a68ec3dSChih-Kang Chang 17657a68ec3dSChih-Kang Chang if (wow) 17667a68ec3dSChih-Kang Chang cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 17677a68ec3dSChih-Kang Chang else 17687a68ec3dSChih-Kang Chang cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 17697a68ec3dSChih-Kang Chang if (!cfg) { 17707a68ec3dSChih-Kang Chang rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 17717a68ec3dSChih-Kang Chang return -EINVAL; 17727a68ec3dSChih-Kang Chang } 17737a68ec3dSChih-Kang Chang 17747a68ec3dSChih-Kang Chang min_cfg = cfg->ple_min_qt; 17757a68ec3dSChih-Kang Chang max_cfg = cfg->ple_max_qt; 17767a68ec3dSChih-Kang Chang SET_QUOTA(cma0_dma, PLE, 6); 17777a68ec3dSChih-Kang Chang SET_QUOTA(cma1_dma, PLE, 7); 17787a68ec3dSChih-Kang Chang 17797a68ec3dSChih-Kang Chang return 0; 17807a68ec3dSChih-Kang Chang } 1781e3ec7017SPing-Ke Shih #undef SET_QUOTA 1782e3ec7017SPing-Ke Shih 178319e28c7fSChin-Yen Lee void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 178419e28c7fSChin-Yen Lee { 178519e28c7fSChin-Yen Lee u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 178619e28c7fSChin-Yen Lee 178719e28c7fSChin-Yen Lee if (enable) 178819e28c7fSChin-Yen Lee rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 178919e28c7fSChin-Yen Lee else 179019e28c7fSChin-Yen Lee rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 179119e28c7fSChin-Yen Lee } 179219e28c7fSChin-Yen Lee 1793e3ec7017SPing-Ke Shih static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1794e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, 1795e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 1796e3ec7017SPing-Ke Shih { 1797e3ec7017SPing-Ke Shih wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1798e3ec7017SPing-Ke Shih ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1799e3ec7017SPing-Ke Shih } 1800e3ec7017SPing-Ke Shih 1801e3ec7017SPing-Ke Shih static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1802e3ec7017SPing-Ke Shih enum rtw89_qta_mode ext_mode) 1803e3ec7017SPing-Ke Shih { 1804e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, *ext_cfg; 1805e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1806e3ec7017SPing-Ke Shih int ret = 0; 1807e3ec7017SPing-Ke Shih u32 ini; 1808e3ec7017SPing-Ke Shih 1809e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1810e3ec7017SPing-Ke Shih if (ret) 1811e3ec7017SPing-Ke Shih return ret; 1812e3ec7017SPing-Ke Shih 1813e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 1814e3ec7017SPing-Ke Shih if (!cfg) { 1815e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1816e3ec7017SPing-Ke Shih ret = -EINVAL; 1817e3ec7017SPing-Ke Shih goto error; 1818e3ec7017SPing-Ke Shih } 1819e3ec7017SPing-Ke Shih 1820e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_DLFW) { 1821e3ec7017SPing-Ke Shih ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1822e3ec7017SPing-Ke Shih if (!ext_cfg) { 1823e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1824e3ec7017SPing-Ke Shih ext_mode); 1825e3ec7017SPing-Ke Shih ret = -EINVAL; 1826e3ec7017SPing-Ke Shih goto error; 1827e3ec7017SPing-Ke Shih } 1828e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1829e3ec7017SPing-Ke Shih } 1830e3ec7017SPing-Ke Shih 18315f8c35b9SPing-Ke Shih if (dle_used_size(cfg->wde_size, cfg->ple_size) != 18325f8c35b9SPing-Ke Shih dle_expected_used_size(rtwdev, mode)) { 1833e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1834e3ec7017SPing-Ke Shih ret = -EINVAL; 1835e3ec7017SPing-Ke Shih goto error; 1836e3ec7017SPing-Ke Shih } 1837e3ec7017SPing-Ke Shih 1838e3ec7017SPing-Ke Shih dle_func_en(rtwdev, false); 1839e3ec7017SPing-Ke Shih dle_clk_en(rtwdev, true); 1840e3ec7017SPing-Ke Shih 1841e3ec7017SPing-Ke Shih ret = dle_mix_cfg(rtwdev, cfg); 1842e3ec7017SPing-Ke Shih if (ret) { 1843e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1844e3ec7017SPing-Ke Shih goto error; 1845e3ec7017SPing-Ke Shih } 1846e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1847e3ec7017SPing-Ke Shih 1848e3ec7017SPing-Ke Shih dle_func_en(rtwdev, true); 1849e3ec7017SPing-Ke Shih 1850e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, ini, 1851e3ec7017SPing-Ke Shih (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1852e3ec7017SPing-Ke Shih 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1853e3ec7017SPing-Ke Shih if (ret) { 1854e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1855e3ec7017SPing-Ke Shih return ret; 1856e3ec7017SPing-Ke Shih } 1857e3ec7017SPing-Ke Shih 1858e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, ini, 1859e3ec7017SPing-Ke Shih (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1860e3ec7017SPing-Ke Shih 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1861e3ec7017SPing-Ke Shih if (ret) { 1862e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1863e3ec7017SPing-Ke Shih return ret; 1864e3ec7017SPing-Ke Shih } 1865e3ec7017SPing-Ke Shih 1866e3ec7017SPing-Ke Shih return 0; 1867e3ec7017SPing-Ke Shih error: 1868e3ec7017SPing-Ke Shih dle_func_en(rtwdev, false); 1869e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1870e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1871e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1872e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1873e3ec7017SPing-Ke Shih 1874e3ec7017SPing-Ke Shih return ret; 1875e3ec7017SPing-Ke Shih } 1876e3ec7017SPing-Ke Shih 1877e07a9968SPing-Ke Shih static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1878e07a9968SPing-Ke Shih enum rtw89_qta_mode mode) 1879e07a9968SPing-Ke Shih { 1880e07a9968SPing-Ke Shih u32 reg, max_preld_size, min_rsvd_size; 1881e07a9968SPing-Ke Shih 1882e07a9968SPing-Ke Shih max_preld_size = (mac_idx == RTW89_MAC_0 ? 1883e07a9968SPing-Ke Shih PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1884e07a9968SPing-Ke Shih reg = mac_idx == RTW89_MAC_0 ? 1885e07a9968SPing-Ke Shih R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1886e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1887e07a9968SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1888e07a9968SPing-Ke Shih 1889e07a9968SPing-Ke Shih min_rsvd_size = PRELD_AMSDU_SIZE; 1890e07a9968SPing-Ke Shih reg = mac_idx == RTW89_MAC_0 ? 1891e07a9968SPing-Ke Shih R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1892e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1893e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1894e07a9968SPing-Ke Shih 1895e07a9968SPing-Ke Shih return 0; 1896e07a9968SPing-Ke Shih } 1897e07a9968SPing-Ke Shih 1898e07a9968SPing-Ke Shih static bool is_qta_poh(struct rtw89_dev *rtwdev) 1899e07a9968SPing-Ke Shih { 1900e07a9968SPing-Ke Shih return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1901e07a9968SPing-Ke Shih } 1902e07a9968SPing-Ke Shih 1903e07a9968SPing-Ke Shih static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1904e07a9968SPing-Ke Shih enum rtw89_qta_mode mode) 1905e07a9968SPing-Ke Shih { 1906e07a9968SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1907e07a9968SPing-Ke Shih 19085c3afcbaSPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 19095c3afcbaSPing-Ke Shih chip->chip_id == RTL8851B || !is_qta_poh(rtwdev)) 1910e07a9968SPing-Ke Shih return 0; 1911e07a9968SPing-Ke Shih 1912e07a9968SPing-Ke Shih return preload_init_set(rtwdev, mac_idx, mode); 1913e07a9968SPing-Ke Shih } 1914e07a9968SPing-Ke Shih 1915e3ec7017SPing-Ke Shih static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1916e3ec7017SPing-Ke Shih { 1917e3ec7017SPing-Ke Shih u32 msk32; 1918e3ec7017SPing-Ke Shih u32 val32; 1919e3ec7017SPing-Ke Shih 1920e3ec7017SPing-Ke Shih msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1921e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1922e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1923e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1924e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1925e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1926e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1927e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1928e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1929e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1930e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1931e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1932e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1933e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1934e3ec7017SPing-Ke Shih 1935e3ec7017SPing-Ke Shih if ((val32 & msk32) == msk32) 1936e3ec7017SPing-Ke Shih return true; 1937e3ec7017SPing-Ke Shih 1938e3ec7017SPing-Ke Shih return false; 1939e3ec7017SPing-Ke Shih } 1940e3ec7017SPing-Ke Shih 1941cf7b8b80SPing-Ke Shih static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 1942cf7b8b80SPing-Ke Shih { 1943cf7b8b80SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1944cf7b8b80SPing-Ke Shih 19455c3afcbaSPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 19465c3afcbaSPing-Ke Shih chip->chip_id == RTL8851B) 1947cf7b8b80SPing-Ke Shih return; 1948cf7b8b80SPing-Ke Shih 1949cf7b8b80SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 1950cf7b8b80SPing-Ke Shih SS2F_PATH_WLCPU); 1951cf7b8b80SPing-Ke Shih } 1952cf7b8b80SPing-Ke Shih 1953e3ec7017SPing-Ke Shih static int sta_sch_init(struct rtw89_dev *rtwdev) 1954e3ec7017SPing-Ke Shih { 1955e3ec7017SPing-Ke Shih u32 p_val; 1956e3ec7017SPing-Ke Shih u8 val; 1957e3ec7017SPing-Ke Shih int ret; 1958e3ec7017SPing-Ke Shih 1959e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1960e3ec7017SPing-Ke Shih if (ret) 1961e3ec7017SPing-Ke Shih return ret; 1962e3ec7017SPing-Ke Shih 1963e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1964e3ec7017SPing-Ke Shih val |= B_AX_SS_EN; 1965e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1966e3ec7017SPing-Ke Shih 1967e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1968e3ec7017SPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1969e3ec7017SPing-Ke Shih if (ret) { 1970e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1971e3ec7017SPing-Ke Shih return ret; 1972e3ec7017SPing-Ke Shih } 1973e3ec7017SPing-Ke Shih 19749a1ab283SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 19759a1ab283SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 1976cf7b8b80SPing-Ke Shih 1977cf7b8b80SPing-Ke Shih _patch_ss2f_path(rtwdev); 1978e3ec7017SPing-Ke Shih 1979e3ec7017SPing-Ke Shih return 0; 1980e3ec7017SPing-Ke Shih } 1981e3ec7017SPing-Ke Shih 1982e3ec7017SPing-Ke Shih static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1983e3ec7017SPing-Ke Shih { 1984e3ec7017SPing-Ke Shih int ret; 1985e3ec7017SPing-Ke Shih 1986e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1987e3ec7017SPing-Ke Shih if (ret) 1988e3ec7017SPing-Ke Shih return ret; 1989e3ec7017SPing-Ke Shih 1990e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1991e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1992e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1993e3ec7017SPing-Ke Shih B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1994e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1995e3ec7017SPing-Ke Shih 1996e3ec7017SPing-Ke Shih return 0; 1997e3ec7017SPing-Ke Shih } 1998e3ec7017SPing-Ke Shih 1999e3ec7017SPing-Ke Shih static int sec_eng_init(struct rtw89_dev *rtwdev) 2000e3ec7017SPing-Ke Shih { 2001b61adeedSPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2002e3ec7017SPing-Ke Shih u32 val = 0; 2003e3ec7017SPing-Ke Shih int ret; 2004e3ec7017SPing-Ke Shih 2005e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2006e3ec7017SPing-Ke Shih if (ret) 2007e3ec7017SPing-Ke Shih return ret; 2008e3ec7017SPing-Ke Shih 2009e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2010e3ec7017SPing-Ke Shih /* init clock */ 2011e3ec7017SPing-Ke Shih val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2012e3ec7017SPing-Ke Shih /* init TX encryption */ 2013e3ec7017SPing-Ke Shih val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2014e3ec7017SPing-Ke Shih val |= (B_AX_MC_DEC | B_AX_BC_DEC); 20155c3afcbaSPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 20165c3afcbaSPing-Ke Shih chip->chip_id == RTL8851B) 2017e3ec7017SPing-Ke Shih val &= ~B_AX_TX_PARTIAL_MODE; 2018e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2019e3ec7017SPing-Ke Shih 2020e3ec7017SPing-Ke Shih /* init MIC ICV append */ 2021e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2022e3ec7017SPing-Ke Shih val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2023e3ec7017SPing-Ke Shih 2024e3ec7017SPing-Ke Shih /* option init */ 2025e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2026e3ec7017SPing-Ke Shih 2027b61adeedSPing-Ke Shih if (chip->chip_id == RTL8852C) 2028b61adeedSPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2029b61adeedSPing-Ke Shih B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2030b61adeedSPing-Ke Shih 2031e3ec7017SPing-Ke Shih return 0; 2032e3ec7017SPing-Ke Shih } 2033e3ec7017SPing-Ke Shih 2034e3ec7017SPing-Ke Shih static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2035e3ec7017SPing-Ke Shih { 2036e3ec7017SPing-Ke Shih int ret; 2037e3ec7017SPing-Ke Shih 2038e3ec7017SPing-Ke Shih ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2039e3ec7017SPing-Ke Shih if (ret) { 2040e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2041e3ec7017SPing-Ke Shih return ret; 2042e3ec7017SPing-Ke Shih } 2043e3ec7017SPing-Ke Shih 2044e07a9968SPing-Ke Shih ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2045e07a9968SPing-Ke Shih if (ret) { 2046e07a9968SPing-Ke Shih rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2047e07a9968SPing-Ke Shih return ret; 2048e07a9968SPing-Ke Shih } 2049e07a9968SPing-Ke Shih 2050e3ec7017SPing-Ke Shih ret = hfc_init(rtwdev, true, true, true); 2051e3ec7017SPing-Ke Shih if (ret) { 2052e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2053e3ec7017SPing-Ke Shih return ret; 2054e3ec7017SPing-Ke Shih } 2055e3ec7017SPing-Ke Shih 2056e3ec7017SPing-Ke Shih ret = sta_sch_init(rtwdev); 2057e3ec7017SPing-Ke Shih if (ret) { 2058e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2059e3ec7017SPing-Ke Shih return ret; 2060e3ec7017SPing-Ke Shih } 2061e3ec7017SPing-Ke Shih 2062e3ec7017SPing-Ke Shih ret = mpdu_proc_init(rtwdev); 2063e3ec7017SPing-Ke Shih if (ret) { 2064e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2065e3ec7017SPing-Ke Shih return ret; 2066e3ec7017SPing-Ke Shih } 2067e3ec7017SPing-Ke Shih 2068e3ec7017SPing-Ke Shih ret = sec_eng_init(rtwdev); 2069e3ec7017SPing-Ke Shih if (ret) { 2070e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2071e3ec7017SPing-Ke Shih return ret; 2072e3ec7017SPing-Ke Shih } 2073e3ec7017SPing-Ke Shih 2074e3ec7017SPing-Ke Shih return ret; 2075e3ec7017SPing-Ke Shih } 2076e3ec7017SPing-Ke Shih 2077e3ec7017SPing-Ke Shih static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2078e3ec7017SPing-Ke Shih { 2079e3ec7017SPing-Ke Shih u32 val, reg; 2080e3ec7017SPing-Ke Shih u16 p_val; 2081e3ec7017SPing-Ke Shih int ret; 2082e3ec7017SPing-Ke Shih 2083e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2084e3ec7017SPing-Ke Shih if (ret) 2085e3ec7017SPing-Ke Shih return ret; 2086e3ec7017SPing-Ke Shih 2087c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2088e3ec7017SPing-Ke Shih 2089e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2090e3ec7017SPing-Ke Shih val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2091e3ec7017SPing-Ke Shih B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2092e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2093e3ec7017SPing-Ke Shih 2094e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2095ad275d0aSPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2096e3ec7017SPing-Ke Shih if (ret) { 2097e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2098e3ec7017SPing-Ke Shih return ret; 2099e3ec7017SPing-Ke Shih } 2100e3ec7017SPing-Ke Shih 2101e3ec7017SPing-Ke Shih return 0; 2102e3ec7017SPing-Ke Shih } 2103e3ec7017SPing-Ke Shih 2104e3ec7017SPing-Ke Shih static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2105e3ec7017SPing-Ke Shih { 2106e3ec7017SPing-Ke Shih u32 ret; 2107e3ec7017SPing-Ke Shih u32 reg; 210860b2ede9SChia-Yuan Li u32 val; 2109e3ec7017SPing-Ke Shih 2110e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2111e3ec7017SPing-Ke Shih if (ret) 2112e3ec7017SPing-Ke Shih return ret; 2113e3ec7017SPing-Ke Shih 2114c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2115ee546904SChia-Yuan Li if (rtwdev->chip->chip_id == RTL8852C) 2116ee546904SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2117ee546904SChia-Yuan Li SIFS_MACTXEN_T1_V1); 2118ee546904SChia-Yuan Li else 2119ee546904SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2120ee546904SChia-Yuan Li SIFS_MACTXEN_T1); 2121c49154ffSPing-Ke Shih 21225c3afcbaSPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) { 2123c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2124c49154ffSPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2125c49154ffSPing-Ke Shih } 2126c49154ffSPing-Ke Shih 2127c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2128c49154ffSPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2129c49154ffSPing-Ke Shih 2130c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 213160b2ede9SChia-Yuan Li if (rtwdev->chip->chip_id == RTL8852C) { 213260b2ede9SChia-Yuan Li val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 213360b2ede9SChia-Yuan Li B_AX_TX_PARTIAL_MODE); 213460b2ede9SChia-Yuan Li if (!val) 213560b2ede9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 213660b2ede9SChia-Yuan Li SCH_PREBKF_24US); 213760b2ede9SChia-Yuan Li } else { 213860b2ede9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 213960b2ede9SChia-Yuan Li SCH_PREBKF_24US); 214060b2ede9SChia-Yuan Li } 2141e3ec7017SPing-Ke Shih 2142e3ec7017SPing-Ke Shih return 0; 2143e3ec7017SPing-Ke Shih } 2144e3ec7017SPing-Ke Shih 214519e28c7fSChin-Yen Lee int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 2146e3ec7017SPing-Ke Shih enum rtw89_machdr_frame_type type, 2147e3ec7017SPing-Ke Shih enum rtw89_mac_fwd_target fwd_target, 2148e3ec7017SPing-Ke Shih u8 mac_idx) 2149e3ec7017SPing-Ke Shih { 2150e3ec7017SPing-Ke Shih u32 reg; 2151e3ec7017SPing-Ke Shih u32 val; 2152e3ec7017SPing-Ke Shih 2153e3ec7017SPing-Ke Shih switch (fwd_target) { 2154e3ec7017SPing-Ke Shih case RTW89_FWD_DONT_CARE: 2155e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_DROP; 2156e3ec7017SPing-Ke Shih break; 2157e3ec7017SPing-Ke Shih case RTW89_FWD_TO_HOST: 2158e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_HOST; 2159e3ec7017SPing-Ke Shih break; 2160e3ec7017SPing-Ke Shih case RTW89_FWD_TO_WLAN_CPU: 2161e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_WLCPU; 2162e3ec7017SPing-Ke Shih break; 2163e3ec7017SPing-Ke Shih default: 2164e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2165e3ec7017SPing-Ke Shih return -EINVAL; 2166e3ec7017SPing-Ke Shih } 2167e3ec7017SPing-Ke Shih 2168e3ec7017SPing-Ke Shih switch (type) { 2169e3ec7017SPing-Ke Shih case RTW89_MGNT: 2170c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2171e3ec7017SPing-Ke Shih break; 2172e3ec7017SPing-Ke Shih case RTW89_CTRL: 2173c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2174e3ec7017SPing-Ke Shih break; 2175e3ec7017SPing-Ke Shih case RTW89_DATA: 2176c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2177e3ec7017SPing-Ke Shih break; 2178e3ec7017SPing-Ke Shih default: 2179e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2180e3ec7017SPing-Ke Shih return -EINVAL; 2181e3ec7017SPing-Ke Shih } 2182e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2183e3ec7017SPing-Ke Shih 2184e3ec7017SPing-Ke Shih return 0; 2185e3ec7017SPing-Ke Shih } 2186e3ec7017SPing-Ke Shih 2187e3ec7017SPing-Ke Shih static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2188e3ec7017SPing-Ke Shih { 2189e3ec7017SPing-Ke Shih int ret, i; 2190e3ec7017SPing-Ke Shih u32 mac_ftlr, plcp_ftlr; 2191e3ec7017SPing-Ke Shih 2192e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2193e3ec7017SPing-Ke Shih if (ret) 2194e3ec7017SPing-Ke Shih return ret; 2195e3ec7017SPing-Ke Shih 2196e3ec7017SPing-Ke Shih for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2197e3ec7017SPing-Ke Shih ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 2198e3ec7017SPing-Ke Shih mac_idx); 2199e3ec7017SPing-Ke Shih if (ret) 2200e3ec7017SPing-Ke Shih return ret; 2201e3ec7017SPing-Ke Shih } 2202e3ec7017SPing-Ke Shih mac_ftlr = rtwdev->hal.rx_fltr; 2203e3ec7017SPing-Ke Shih plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2204e3ec7017SPing-Ke Shih B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2205e3ec7017SPing-Ke Shih B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2206e3ec7017SPing-Ke Shih B_AX_HE_SIGB_CRC_CHK; 2207c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2208e3ec7017SPing-Ke Shih mac_ftlr); 2209c220d08eSPing-Ke Shih rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2210e3ec7017SPing-Ke Shih plcp_ftlr); 2211e3ec7017SPing-Ke Shih 2212e3ec7017SPing-Ke Shih return 0; 2213e3ec7017SPing-Ke Shih } 2214e3ec7017SPing-Ke Shih 2215e3ec7017SPing-Ke Shih static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2216e3ec7017SPing-Ke Shih { 2217e3ec7017SPing-Ke Shih u32 reg, val32; 2218e3ec7017SPing-Ke Shih u32 b_rsp_chk_nav, b_rsp_chk_cca; 2219e3ec7017SPing-Ke Shih 2220e3ec7017SPing-Ke Shih b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2221e3ec7017SPing-Ke Shih B_AX_RSP_CHK_BASIC_NAV; 2222e3ec7017SPing-Ke Shih b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2223e3ec7017SPing-Ke Shih B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2224e3ec7017SPing-Ke Shih B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2225e3ec7017SPing-Ke Shih 2226e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 2227e3ec7017SPing-Ke Shih case RTL8852A: 2228e3ec7017SPing-Ke Shih case RTL8852B: 2229c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2230e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2231e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2232e3ec7017SPing-Ke Shih 2233c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2234e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2235e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2236e3ec7017SPing-Ke Shih break; 2237e3ec7017SPing-Ke Shih default: 2238c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2239e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2240e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2241e3ec7017SPing-Ke Shih 2242c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2243e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2244e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2245e3ec7017SPing-Ke Shih break; 2246e3ec7017SPing-Ke Shih } 2247e3ec7017SPing-Ke Shih } 2248e3ec7017SPing-Ke Shih 2249e3ec7017SPing-Ke Shih static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2250e3ec7017SPing-Ke Shih { 2251e3ec7017SPing-Ke Shih u32 val, reg; 2252e3ec7017SPing-Ke Shih int ret; 2253e3ec7017SPing-Ke Shih 2254e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2255e3ec7017SPing-Ke Shih if (ret) 2256e3ec7017SPing-Ke Shih return ret; 2257e3ec7017SPing-Ke Shih 2258c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2259e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2260e3ec7017SPing-Ke Shih val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2261e3ec7017SPing-Ke Shih B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2262e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2263e3ec7017SPing-Ke Shih B_AX_CTN_CHK_INTRA_NAV | 2264e3ec7017SPing-Ke Shih B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2265e3ec7017SPing-Ke Shih B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2266e3ec7017SPing-Ke Shih B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 226798ed6159SPing-Ke Shih B_AX_CTN_CHK_CCA_P20); 2268e3ec7017SPing-Ke Shih val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2269e3ec7017SPing-Ke Shih B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2270e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 227198ed6159SPing-Ke Shih B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 227298ed6159SPing-Ke Shih B_AX_SIFS_CHK_EDCCA); 2273e3ec7017SPing-Ke Shih 2274e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2275e3ec7017SPing-Ke Shih 2276e3ec7017SPing-Ke Shih _patch_dis_resp_chk(rtwdev, mac_idx); 2277e3ec7017SPing-Ke Shih 2278e3ec7017SPing-Ke Shih return 0; 2279e3ec7017SPing-Ke Shih } 2280e3ec7017SPing-Ke Shih 228119cb9427SPing-Ke Shih static int nav_ctrl_init(struct rtw89_dev *rtwdev) 228219cb9427SPing-Ke Shih { 228319cb9427SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 228419cb9427SPing-Ke Shih B_AX_WMAC_TF_UP_NAV_EN | 228519cb9427SPing-Ke Shih B_AX_WMAC_NAV_UPPER_EN); 2286c060dc51SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 228719cb9427SPing-Ke Shih 228819cb9427SPing-Ke Shih return 0; 228919cb9427SPing-Ke Shih } 229019cb9427SPing-Ke Shih 2291e3ec7017SPing-Ke Shih static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2292e3ec7017SPing-Ke Shih { 2293e3ec7017SPing-Ke Shih u32 reg; 2294e3ec7017SPing-Ke Shih int ret; 2295e3ec7017SPing-Ke Shih 2296e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2297e3ec7017SPing-Ke Shih if (ret) 2298e3ec7017SPing-Ke Shih return ret; 2299c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2300e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2301e3ec7017SPing-Ke Shih 2302e3ec7017SPing-Ke Shih return 0; 2303e3ec7017SPing-Ke Shih } 2304e3ec7017SPing-Ke Shih 2305e3ec7017SPing-Ke Shih static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2306e3ec7017SPing-Ke Shih { 2307e3ec7017SPing-Ke Shih u32 reg; 2308e3ec7017SPing-Ke Shih int ret; 2309e3ec7017SPing-Ke Shih 2310e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2311e3ec7017SPing-Ke Shih if (ret) 2312e3ec7017SPing-Ke Shih return ret; 2313e3ec7017SPing-Ke Shih 2314c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2315e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2316e3ec7017SPing-Ke Shih 2317c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 231875fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 231975fd91aaSPing-Ke Shih 2320c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 232175fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 232275fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 232375fd91aaSPing-Ke Shih 2324e3ec7017SPing-Ke Shih return 0; 2325e3ec7017SPing-Ke Shih } 2326e3ec7017SPing-Ke Shih 2327e3ec7017SPing-Ke Shih static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2328e3ec7017SPing-Ke Shih { 23299ef9edb9SChia-Yuan Li const struct rtw89_chip_info *chip = rtwdev->chip; 23309ef9edb9SChia-Yuan Li const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2331e3ec7017SPing-Ke Shih u32 reg, val, sifs; 2332e3ec7017SPing-Ke Shih int ret; 2333e3ec7017SPing-Ke Shih 2334e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2335e3ec7017SPing-Ke Shih if (ret) 2336e3ec7017SPing-Ke Shih return ret; 2337e3ec7017SPing-Ke Shih 2338c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2339e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2340e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2341e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2342e3ec7017SPing-Ke Shih 2343e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 2344e3ec7017SPing-Ke Shih case RTL8852A: 2345e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52A; 2346e3ec7017SPing-Ke Shih break; 2347e3ec7017SPing-Ke Shih case RTL8852B: 2348e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52B; 2349e3ec7017SPing-Ke Shih break; 2350e3ec7017SPing-Ke Shih default: 2351e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52C; 2352e3ec7017SPing-Ke Shih break; 2353e3ec7017SPing-Ke Shih } 2354e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2355e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2356e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2357e3ec7017SPing-Ke Shih 2358c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2359e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2360e3ec7017SPing-Ke Shih 2361c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 23629ef9edb9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2363c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 23649ef9edb9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 23659ef9edb9SChia-Yuan Li 2366e3ec7017SPing-Ke Shih return 0; 2367e3ec7017SPing-Ke Shih } 2368e3ec7017SPing-Ke Shih 236918175197SPing-Ke Shih static void rst_bacam(struct rtw89_dev *rtwdev) 237018175197SPing-Ke Shih { 237118175197SPing-Ke Shih u32 val32; 237218175197SPing-Ke Shih int ret; 237318175197SPing-Ke Shih 237418175197SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 237518175197SPing-Ke Shih S_AX_BACAM_RST_ALL); 237618175197SPing-Ke Shih 237718175197SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 237818175197SPing-Ke Shih 1, 1000, false, 237918175197SPing-Ke Shih rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 238018175197SPing-Ke Shih if (ret) 238118175197SPing-Ke Shih rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 238218175197SPing-Ke Shih } 238318175197SPing-Ke Shih 2384e3ec7017SPing-Ke Shih static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2385e3ec7017SPing-Ke Shih { 2386e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_CCA_TO 32 2387e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_DATA_TO 15 2388e3ec7017SPing-Ke Shih #define RX_MAX_LEN_UNIT 512 2389e3ec7017SPing-Ke Shih #define PLD_RLS_MAX_PG 127 23904b0d341bSPing-Ke Shih #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2391e3ec7017SPing-Ke Shih int ret; 2392e3ec7017SPing-Ke Shih u32 reg, rx_max_len, rx_qta; 2393e3ec7017SPing-Ke Shih u16 val; 2394e3ec7017SPing-Ke Shih 2395e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2396e3ec7017SPing-Ke Shih if (ret) 2397e3ec7017SPing-Ke Shih return ret; 2398e3ec7017SPing-Ke Shih 239918175197SPing-Ke Shih if (mac_idx == RTW89_MAC_0) 240018175197SPing-Ke Shih rst_bacam(rtwdev); 240118175197SPing-Ke Shih 2402c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2403e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2404e3ec7017SPing-Ke Shih 2405c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2406e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 2407e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2408e3ec7017SPing-Ke Shih B_AX_RX_DLK_DATA_TIME_MASK); 2409e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2410e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK); 2411e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 2412e3ec7017SPing-Ke Shih 2413c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2414e3ec7017SPing-Ke Shih rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2415e3ec7017SPing-Ke Shih 2416c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2417e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_0) 2418e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2419e3ec7017SPing-Ke Shih else 2420e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 24214b0d341bSPing-Ke Shih rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 24224b0d341bSPing-Ke Shih rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 24234b0d341bSPing-Ke Shih rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 24244b0d341bSPing-Ke Shih rx_max_len /= RX_MAX_LEN_UNIT; 2425e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2426e3ec7017SPing-Ke Shih 2427e3ec7017SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852A && 2428e3ec7017SPing-Ke Shih rtwdev->hal.cv == CHIP_CBV) { 2429e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, 2430c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2431e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK, 0); 2432c220d08eSPing-Ke Shih rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2433e3ec7017SPing-Ke Shih BIT(12)); 2434e3ec7017SPing-Ke Shih } 2435e3ec7017SPing-Ke Shih 2436c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2437e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2438e3ec7017SPing-Ke Shih 2439e3ec7017SPing-Ke Shih return ret; 2440e3ec7017SPing-Ke Shih } 2441e3ec7017SPing-Ke Shih 2442e3ec7017SPing-Ke Shih static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2443e3ec7017SPing-Ke Shih { 24449ef9edb9SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2445e3ec7017SPing-Ke Shih u32 val, reg; 2446e3ec7017SPing-Ke Shih int ret; 2447e3ec7017SPing-Ke Shih 2448e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2449e3ec7017SPing-Ke Shih if (ret) 2450e3ec7017SPing-Ke Shih return ret; 2451e3ec7017SPing-Ke Shih 2452c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2453e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2454e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2455e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2456e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2457e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2458e3ec7017SPing-Ke Shih 24599ef9edb9SChia-Yuan Li if (chip_id == RTL8852A || chip_id == RTL8852B) { 2460c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 24619ef9edb9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 24629ef9edb9SChia-Yuan Li } 24639ef9edb9SChia-Yuan Li 2464e3ec7017SPing-Ke Shih return 0; 2465e3ec7017SPing-Ke Shih } 2466e3ec7017SPing-Ke Shih 2467e3ec7017SPing-Ke Shih static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2468e3ec7017SPing-Ke Shih { 2469e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 2470e3ec7017SPing-Ke Shih 2471e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 2472e3ec7017SPing-Ke Shih if (!cfg) { 2473e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2474e3ec7017SPing-Ke Shih return false; 2475e3ec7017SPing-Ke Shih } 2476e3ec7017SPing-Ke Shih 2477e3ec7017SPing-Ke Shih return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2478e3ec7017SPing-Ke Shih } 2479e3ec7017SPing-Ke Shih 2480e3ec7017SPing-Ke Shih static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2481e3ec7017SPing-Ke Shih { 2482e3ec7017SPing-Ke Shih u32 val, reg; 2483e3ec7017SPing-Ke Shih int ret; 2484e3ec7017SPing-Ke Shih 2485e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2486e3ec7017SPing-Ke Shih if (ret) 2487e3ec7017SPing-Ke Shih return ret; 2488e3ec7017SPing-Ke Shih 2489e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2490c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2491e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2492e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2493e3ec7017SPing-Ke Shih B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 24949fb4862eSPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 24959fb4862eSPing-Ke Shih B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2496e3ec7017SPing-Ke Shih val |= B_AX_HW_CTS2SELF_EN; 2497e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2498e3ec7017SPing-Ke Shih 2499c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2500e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2501e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2502e3ec7017SPing-Ke Shih val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2503e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2504e3ec7017SPing-Ke Shih } 2505e3ec7017SPing-Ke Shih 25069fb4862eSPing-Ke Shih if (mac_idx == RTW89_MAC_0) { 25079fb4862eSPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 25089fb4862eSPing-Ke Shih B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 25099fb4862eSPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 25109fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_0 | 25119fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_1 | 25129fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_UL); 25139fb4862eSPing-Ke Shih rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 25149fb4862eSPing-Ke Shih B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 25159fb4862eSPing-Ke Shih } else if (mac_idx == RTW89_MAC_1) { 25169fb4862eSPing-Ke Shih rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 25179fb4862eSPing-Ke Shih B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 25189fb4862eSPing-Ke Shih } 2519e3ec7017SPing-Ke Shih 2520e3ec7017SPing-Ke Shih return 0; 2521e3ec7017SPing-Ke Shih } 2522e3ec7017SPing-Ke Shih 2523a0d99ebbSPing-Ke Shih static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2524a0d99ebbSPing-Ke Shih { 2525a0d99ebbSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2526a0d99ebbSPing-Ke Shih u32 reg; 2527a0d99ebbSPing-Ke Shih int ret; 2528a0d99ebbSPing-Ke Shih 2529b74bb07cSPing-Ke Shih if (chip_id != RTL8852B) 2530a0d99ebbSPing-Ke Shih return 0; 2531a0d99ebbSPing-Ke Shih 2532a0d99ebbSPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2533a0d99ebbSPing-Ke Shih if (ret) 2534a0d99ebbSPing-Ke Shih return ret; 2535a0d99ebbSPing-Ke Shih 2536c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2537a0d99ebbSPing-Ke Shih rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2538a0d99ebbSPing-Ke Shih 2539a0d99ebbSPing-Ke Shih return 0; 2540a0d99ebbSPing-Ke Shih } 2541a0d99ebbSPing-Ke Shih 2542e3ec7017SPing-Ke Shih static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2543e3ec7017SPing-Ke Shih { 2544e3ec7017SPing-Ke Shih int ret; 2545e3ec7017SPing-Ke Shih 2546e3ec7017SPing-Ke Shih ret = scheduler_init(rtwdev, mac_idx); 2547e3ec7017SPing-Ke Shih if (ret) { 2548e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2549e3ec7017SPing-Ke Shih return ret; 2550e3ec7017SPing-Ke Shih } 2551e3ec7017SPing-Ke Shih 2552e3ec7017SPing-Ke Shih ret = addr_cam_init(rtwdev, mac_idx); 2553e3ec7017SPing-Ke Shih if (ret) { 2554e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2555e3ec7017SPing-Ke Shih ret); 2556e3ec7017SPing-Ke Shih return ret; 2557e3ec7017SPing-Ke Shih } 2558e3ec7017SPing-Ke Shih 2559e3ec7017SPing-Ke Shih ret = rx_fltr_init(rtwdev, mac_idx); 2560e3ec7017SPing-Ke Shih if (ret) { 2561e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2562e3ec7017SPing-Ke Shih ret); 2563e3ec7017SPing-Ke Shih return ret; 2564e3ec7017SPing-Ke Shih } 2565e3ec7017SPing-Ke Shih 2566e3ec7017SPing-Ke Shih ret = cca_ctrl_init(rtwdev, mac_idx); 2567e3ec7017SPing-Ke Shih if (ret) { 2568e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2569e3ec7017SPing-Ke Shih ret); 2570e3ec7017SPing-Ke Shih return ret; 2571e3ec7017SPing-Ke Shih } 2572e3ec7017SPing-Ke Shih 257319cb9427SPing-Ke Shih ret = nav_ctrl_init(rtwdev); 257419cb9427SPing-Ke Shih if (ret) { 257519cb9427SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 257619cb9427SPing-Ke Shih ret); 257719cb9427SPing-Ke Shih return ret; 257819cb9427SPing-Ke Shih } 257919cb9427SPing-Ke Shih 2580e3ec7017SPing-Ke Shih ret = spatial_reuse_init(rtwdev, mac_idx); 2581e3ec7017SPing-Ke Shih if (ret) { 2582e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2583e3ec7017SPing-Ke Shih mac_idx, ret); 2584e3ec7017SPing-Ke Shih return ret; 2585e3ec7017SPing-Ke Shih } 2586e3ec7017SPing-Ke Shih 2587e3ec7017SPing-Ke Shih ret = tmac_init(rtwdev, mac_idx); 2588e3ec7017SPing-Ke Shih if (ret) { 2589e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2590e3ec7017SPing-Ke Shih return ret; 2591e3ec7017SPing-Ke Shih } 2592e3ec7017SPing-Ke Shih 2593e3ec7017SPing-Ke Shih ret = trxptcl_init(rtwdev, mac_idx); 2594e3ec7017SPing-Ke Shih if (ret) { 2595e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2596e3ec7017SPing-Ke Shih return ret; 2597e3ec7017SPing-Ke Shih } 2598e3ec7017SPing-Ke Shih 2599e3ec7017SPing-Ke Shih ret = rmac_init(rtwdev, mac_idx); 2600e3ec7017SPing-Ke Shih if (ret) { 2601e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2602e3ec7017SPing-Ke Shih return ret; 2603e3ec7017SPing-Ke Shih } 2604e3ec7017SPing-Ke Shih 2605e3ec7017SPing-Ke Shih ret = cmac_com_init(rtwdev, mac_idx); 2606e3ec7017SPing-Ke Shih if (ret) { 2607e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2608e3ec7017SPing-Ke Shih return ret; 2609e3ec7017SPing-Ke Shih } 2610e3ec7017SPing-Ke Shih 2611e3ec7017SPing-Ke Shih ret = ptcl_init(rtwdev, mac_idx); 2612e3ec7017SPing-Ke Shih if (ret) { 2613e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2614e3ec7017SPing-Ke Shih return ret; 2615e3ec7017SPing-Ke Shih } 2616e3ec7017SPing-Ke Shih 2617a0d99ebbSPing-Ke Shih ret = cmac_dma_init(rtwdev, mac_idx); 2618a0d99ebbSPing-Ke Shih if (ret) { 2619a0d99ebbSPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2620a0d99ebbSPing-Ke Shih return ret; 2621a0d99ebbSPing-Ke Shih } 2622a0d99ebbSPing-Ke Shih 2623e3ec7017SPing-Ke Shih return ret; 2624e3ec7017SPing-Ke Shih } 2625e3ec7017SPing-Ke Shih 2626e3ec7017SPing-Ke Shih static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2627e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info *c2h_info) 2628e3ec7017SPing-Ke Shih { 2629e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 2630e3ec7017SPing-Ke Shih u32 ret; 2631e3ec7017SPing-Ke Shih 2632e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2633e3ec7017SPing-Ke Shih h2c_info.content_len = 0; 2634e3ec7017SPing-Ke Shih 2635e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2636e3ec7017SPing-Ke Shih if (ret) 2637e3ec7017SPing-Ke Shih return ret; 2638e3ec7017SPing-Ke Shih 2639e3ec7017SPing-Ke Shih if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2640e3ec7017SPing-Ke Shih return -EINVAL; 2641e3ec7017SPing-Ke Shih 2642e3ec7017SPing-Ke Shih return 0; 2643e3ec7017SPing-Ke Shih } 2644e3ec7017SPing-Ke Shih 2645e3ec7017SPing-Ke Shih int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2646e3ec7017SPing-Ke Shih { 2647f48453e0SPing-Ke Shih struct rtw89_efuse *efuse = &rtwdev->efuse; 2648e3ec7017SPing-Ke Shih struct rtw89_hal *hal = &rtwdev->hal; 2649e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2650e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 265168012b44SPing-Ke Shih const struct rtw89_c2hreg_phycap *phycap; 2652c7ad08c6SPing-Ke Shih u8 tx_nss; 2653c7ad08c6SPing-Ke Shih u8 rx_nss; 2654dc229d94SPing-Ke Shih u8 tx_ant; 2655dc229d94SPing-Ke Shih u8 rx_ant; 2656e3ec7017SPing-Ke Shih u32 ret; 2657e3ec7017SPing-Ke Shih 2658e3ec7017SPing-Ke Shih ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2659e3ec7017SPing-Ke Shih if (ret) 2660e3ec7017SPing-Ke Shih return ret; 2661e3ec7017SPing-Ke Shih 266268012b44SPing-Ke Shih phycap = &c2h_info.u.phycap; 266368012b44SPing-Ke Shih 266468012b44SPing-Ke Shih tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 266568012b44SPing-Ke Shih rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 266668012b44SPing-Ke Shih tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 266768012b44SPing-Ke Shih rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2668c7ad08c6SPing-Ke Shih 2669c7ad08c6SPing-Ke Shih hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2670c7ad08c6SPing-Ke Shih hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2671e3ec7017SPing-Ke Shih 2672dc229d94SPing-Ke Shih if (tx_ant == 1) 2673dc229d94SPing-Ke Shih hal->antenna_tx = RF_B; 2674dc229d94SPing-Ke Shih if (rx_ant == 1) 2675dc229d94SPing-Ke Shih hal->antenna_rx = RF_B; 2676dc229d94SPing-Ke Shih 2677dc229d94SPing-Ke Shih if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2678dc229d94SPing-Ke Shih hal->antenna_tx = RF_B; 2679dc229d94SPing-Ke Shih hal->tx_path_diversity = true; 2680dc229d94SPing-Ke Shih } 2681dc229d94SPing-Ke Shih 2682f48453e0SPing-Ke Shih if (chip->rf_path_num == 1) { 2683f48453e0SPing-Ke Shih hal->antenna_tx = RF_A; 2684f48453e0SPing-Ke Shih hal->antenna_rx = RF_A; 2685f48453e0SPing-Ke Shih if ((efuse->rfe_type % 3) == 2) 2686f48453e0SPing-Ke Shih hal->ant_diversity = true; 2687f48453e0SPing-Ke Shih } 2688f48453e0SPing-Ke Shih 2689e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 2690e3ec7017SPing-Ke Shih "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2691c7ad08c6SPing-Ke Shih hal->tx_nss, tx_nss, chip->tx_nss, 2692c7ad08c6SPing-Ke Shih hal->rx_nss, rx_nss, chip->rx_nss); 2693dc229d94SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 2694dc229d94SPing-Ke Shih "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2695dc229d94SPing-Ke Shih tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2696dc229d94SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2697f48453e0SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2698e3ec7017SPing-Ke Shih 2699e3ec7017SPing-Ke Shih return 0; 2700e3ec7017SPing-Ke Shih } 2701e3ec7017SPing-Ke Shih 2702e3ec7017SPing-Ke Shih static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2703e3ec7017SPing-Ke Shih u16 tx_en_u16, u16 mask_u16) 2704e3ec7017SPing-Ke Shih { 2705e3ec7017SPing-Ke Shih u32 ret; 2706e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 2707e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 270868012b44SPing-Ke Shih struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 2709e3ec7017SPing-Ke Shih 2710e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 271168012b44SPing-Ke Shih h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 271268012b44SPing-Ke Shih 271368012b44SPing-Ke Shih u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 271468012b44SPing-Ke Shih u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 271568012b44SPing-Ke Shih u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 2716e3ec7017SPing-Ke Shih 2717e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2718e3ec7017SPing-Ke Shih if (ret) 2719e3ec7017SPing-Ke Shih return ret; 2720e3ec7017SPing-Ke Shih 2721e3ec7017SPing-Ke Shih if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2722e3ec7017SPing-Ke Shih return -EINVAL; 2723e3ec7017SPing-Ke Shih 2724e3ec7017SPing-Ke Shih return 0; 2725e3ec7017SPing-Ke Shih } 2726e3ec7017SPing-Ke Shih 2727e3ec7017SPing-Ke Shih static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2728e3ec7017SPing-Ke Shih u16 tx_en, u16 tx_en_mask) 2729e3ec7017SPing-Ke Shih { 2730c220d08eSPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 2731e3ec7017SPing-Ke Shih u16 val; 2732e3ec7017SPing-Ke Shih int ret; 2733e3ec7017SPing-Ke Shih 2734e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2735e3ec7017SPing-Ke Shih if (ret) 2736e3ec7017SPing-Ke Shih return ret; 2737e3ec7017SPing-Ke Shih 2738e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2739e3ec7017SPing-Ke Shih return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2740e3ec7017SPing-Ke Shih tx_en, tx_en_mask); 2741e3ec7017SPing-Ke Shih 2742e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 2743e3ec7017SPing-Ke Shih val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2744e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 2745e3ec7017SPing-Ke Shih 2746e3ec7017SPing-Ke Shih return 0; 2747e3ec7017SPing-Ke Shih } 2748e3ec7017SPing-Ke Shih 2749de7ba639SPing-Ke Shih static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2750de7ba639SPing-Ke Shih u32 tx_en, u32 tx_en_mask) 2751de7ba639SPing-Ke Shih { 2752c220d08eSPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 2753de7ba639SPing-Ke Shih u32 val; 2754de7ba639SPing-Ke Shih int ret; 2755de7ba639SPing-Ke Shih 2756de7ba639SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2757de7ba639SPing-Ke Shih if (ret) 2758de7ba639SPing-Ke Shih return ret; 2759de7ba639SPing-Ke Shih 2760de7ba639SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2761de7ba639SPing-Ke Shih val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2762de7ba639SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2763de7ba639SPing-Ke Shih 2764de7ba639SPing-Ke Shih return 0; 2765de7ba639SPing-Ke Shih } 2766de7ba639SPing-Ke Shih 2767e3ec7017SPing-Ke Shih int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2768d780f926SPing-Ke Shih u32 *tx_en, enum rtw89_sch_tx_sel sel) 2769e3ec7017SPing-Ke Shih { 2770e3ec7017SPing-Ke Shih int ret; 2771e3ec7017SPing-Ke Shih 2772e3ec7017SPing-Ke Shih *tx_en = rtw89_read16(rtwdev, 2773c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 2774e3ec7017SPing-Ke Shih 2775e3ec7017SPing-Ke Shih switch (sel) { 2776e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_ALL: 2777de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2778de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK); 2779e3ec7017SPing-Ke Shih if (ret) 2780e3ec7017SPing-Ke Shih return ret; 2781e3ec7017SPing-Ke Shih break; 2782e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_HIQ: 2783e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2784e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_HGQ); 2785e3ec7017SPing-Ke Shih if (ret) 2786e3ec7017SPing-Ke Shih return ret; 2787e3ec7017SPing-Ke Shih break; 2788e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MG0: 2789e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2790e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_MGQ); 2791e3ec7017SPing-Ke Shih if (ret) 2792e3ec7017SPing-Ke Shih return ret; 2793e3ec7017SPing-Ke Shih break; 2794e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MACID: 2795de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2796de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK); 2797e3ec7017SPing-Ke Shih if (ret) 2798e3ec7017SPing-Ke Shih return ret; 2799e3ec7017SPing-Ke Shih break; 2800e3ec7017SPing-Ke Shih default: 2801e3ec7017SPing-Ke Shih return 0; 2802e3ec7017SPing-Ke Shih } 2803e3ec7017SPing-Ke Shih 2804e3ec7017SPing-Ke Shih return 0; 2805e3ec7017SPing-Ke Shih } 2806861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2807e3ec7017SPing-Ke Shih 2808de7ba639SPing-Ke Shih int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2809de7ba639SPing-Ke Shih u32 *tx_en, enum rtw89_sch_tx_sel sel) 2810de7ba639SPing-Ke Shih { 2811de7ba639SPing-Ke Shih int ret; 2812de7ba639SPing-Ke Shih 2813de7ba639SPing-Ke Shih *tx_en = rtw89_read32(rtwdev, 2814c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 2815de7ba639SPing-Ke Shih 2816de7ba639SPing-Ke Shih switch (sel) { 2817de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_ALL: 2818de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2819de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 2820de7ba639SPing-Ke Shih if (ret) 2821de7ba639SPing-Ke Shih return ret; 2822de7ba639SPing-Ke Shih break; 2823de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_HIQ: 2824de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2825de7ba639SPing-Ke Shih 0, B_AX_CTN_TXEN_HGQ); 2826de7ba639SPing-Ke Shih if (ret) 2827de7ba639SPing-Ke Shih return ret; 2828de7ba639SPing-Ke Shih break; 2829de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_MG0: 2830de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2831de7ba639SPing-Ke Shih 0, B_AX_CTN_TXEN_MGQ); 2832de7ba639SPing-Ke Shih if (ret) 2833de7ba639SPing-Ke Shih return ret; 2834de7ba639SPing-Ke Shih break; 2835de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_MACID: 2836de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2837de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 2838de7ba639SPing-Ke Shih if (ret) 2839de7ba639SPing-Ke Shih return ret; 2840de7ba639SPing-Ke Shih break; 2841de7ba639SPing-Ke Shih default: 2842de7ba639SPing-Ke Shih return 0; 2843de7ba639SPing-Ke Shih } 2844de7ba639SPing-Ke Shih 2845de7ba639SPing-Ke Shih return 0; 2846de7ba639SPing-Ke Shih } 2847de7ba639SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2848de7ba639SPing-Ke Shih 2849d780f926SPing-Ke Shih int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2850e3ec7017SPing-Ke Shih { 2851e3ec7017SPing-Ke Shih int ret; 2852e3ec7017SPing-Ke Shih 2853de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2854e3ec7017SPing-Ke Shih if (ret) 2855e3ec7017SPing-Ke Shih return ret; 2856e3ec7017SPing-Ke Shih 2857e3ec7017SPing-Ke Shih return 0; 2858e3ec7017SPing-Ke Shih } 2859861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2860e3ec7017SPing-Ke Shih 2861de7ba639SPing-Ke Shih int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2862de7ba639SPing-Ke Shih { 2863de7ba639SPing-Ke Shih int ret; 2864de7ba639SPing-Ke Shih 2865de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2866de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 2867de7ba639SPing-Ke Shih if (ret) 2868de7ba639SPing-Ke Shih return ret; 2869de7ba639SPing-Ke Shih 2870de7ba639SPing-Ke Shih return 0; 2871de7ba639SPing-Ke Shih } 2872de7ba639SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2873de7ba639SPing-Ke Shih 2874eaddda24SPing-Ke Shih int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 2875e3ec7017SPing-Ke Shih { 2876e3ec7017SPing-Ke Shih u32 val, reg; 2877e3ec7017SPing-Ke Shih int ret; 2878e3ec7017SPing-Ke Shih 2879e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2880e3ec7017SPing-Ke Shih val = buf_len; 2881e3ec7017SPing-Ke Shih val |= B_AX_WD_BUF_REQ_EXEC; 2882e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2883e3ec7017SPing-Ke Shih 2884e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2885e3ec7017SPing-Ke Shih 2886e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2887e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 2888e3ec7017SPing-Ke Shih if (ret) 2889eaddda24SPing-Ke Shih return ret; 2890e3ec7017SPing-Ke Shih 2891eaddda24SPing-Ke Shih *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2892eaddda24SPing-Ke Shih if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 2893eaddda24SPing-Ke Shih return -ENOENT; 2894eaddda24SPing-Ke Shih 2895eaddda24SPing-Ke Shih return 0; 2896e3ec7017SPing-Ke Shih } 2897e3ec7017SPing-Ke Shih 28988a1f6c88SZong-Zhe Yang int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 28998a1f6c88SZong-Zhe Yang struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 2900e3ec7017SPing-Ke Shih { 2901e3ec7017SPing-Ke Shih u32 val, cmd_type, reg; 2902e3ec7017SPing-Ke Shih int ret; 2903e3ec7017SPing-Ke Shih 2904e3ec7017SPing-Ke Shih cmd_type = ctrl_para->cmd_type; 2905e3ec7017SPing-Ke Shih 2906e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2907e3ec7017SPing-Ke Shih val = 0; 2908e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->start_pktid, 2909e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2910e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->end_pktid, 2911e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2912e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2913e3ec7017SPing-Ke Shih 2914e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2915e3ec7017SPing-Ke Shih val = 0; 2916e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_pid, 2917e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_PID_MASK); 2918e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_qid, 2919e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_QID_MASK); 2920e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_pid, 2921e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_PID_MASK); 2922e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_qid, 2923e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_QID_MASK); 2924e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2925e3ec7017SPing-Ke Shih 2926e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2927e3ec7017SPing-Ke Shih val = 0; 2928e3ec7017SPing-Ke Shih val = u32_replace_bits(val, cmd_type, 2929e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_CMD_TYPE_MASK); 2930e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->macid, 2931e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_MACID_MASK); 2932e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->pkt_num, 2933e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_PKTNUM_MASK); 2934e3ec7017SPing-Ke Shih val |= B_AX_WD_CPUQ_OP_EXEC; 2935e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2936e3ec7017SPing-Ke Shih 2937e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2938e3ec7017SPing-Ke Shih 2939e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2940e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 2941e3ec7017SPing-Ke Shih if (ret) 2942e3ec7017SPing-Ke Shih return ret; 2943e3ec7017SPing-Ke Shih 2944e3ec7017SPing-Ke Shih if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2945e3ec7017SPing-Ke Shih cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2946e3ec7017SPing-Ke Shih ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2947e3ec7017SPing-Ke Shih 2948e3ec7017SPing-Ke Shih return 0; 2949e3ec7017SPing-Ke Shih } 2950e3ec7017SPing-Ke Shih 2951e3ec7017SPing-Ke Shih static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2952e3ec7017SPing-Ke Shih { 2953e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 2954e3ec7017SPing-Ke Shih struct rtw89_cpuio_ctrl ctrl_para = {0}; 2955e3ec7017SPing-Ke Shih u16 pkt_id; 2956e3ec7017SPing-Ke Shih int ret; 2957e3ec7017SPing-Ke Shih 2958e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 2959e3ec7017SPing-Ke Shih if (!cfg) { 2960e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2961e3ec7017SPing-Ke Shih return -EINVAL; 2962e3ec7017SPing-Ke Shih } 2963e3ec7017SPing-Ke Shih 29645f8c35b9SPing-Ke Shih if (dle_used_size(cfg->wde_size, cfg->ple_size) != 29655f8c35b9SPing-Ke Shih dle_expected_used_size(rtwdev, mode)) { 2966e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2967e3ec7017SPing-Ke Shih return -EINVAL; 2968e3ec7017SPing-Ke Shih } 2969e3ec7017SPing-Ke Shih 2970e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2971e3ec7017SPing-Ke Shih 2972eaddda24SPing-Ke Shih ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id); 2973eaddda24SPing-Ke Shih if (ret) { 2974e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2975eaddda24SPing-Ke Shih return ret; 2976e3ec7017SPing-Ke Shih } 2977e3ec7017SPing-Ke Shih 2978e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2979e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 2980e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 2981e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 2982e3ec7017SPing-Ke Shih ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2983e3ec7017SPing-Ke Shih ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2984e3ec7017SPing-Ke Shih ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2985e3ec7017SPing-Ke Shih if (ret) { 2986e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2987e3ec7017SPing-Ke Shih return -EFAULT; 2988e3ec7017SPing-Ke Shih } 2989e3ec7017SPing-Ke Shih 2990eaddda24SPing-Ke Shih ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, false, &pkt_id); 2991eaddda24SPing-Ke Shih if (ret) { 2992e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2993eaddda24SPing-Ke Shih return ret; 2994e3ec7017SPing-Ke Shih } 2995e3ec7017SPing-Ke Shih 2996e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2997e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 2998e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 2999e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 3000e3ec7017SPing-Ke Shih ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3001e3ec7017SPing-Ke Shih ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3002e3ec7017SPing-Ke Shih ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 3003e3ec7017SPing-Ke Shih if (ret) { 3004e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3005e3ec7017SPing-Ke Shih return -EFAULT; 3006e3ec7017SPing-Ke Shih } 3007e3ec7017SPing-Ke Shih 3008e3ec7017SPing-Ke Shih return 0; 3009e3ec7017SPing-Ke Shih } 3010e3ec7017SPing-Ke Shih 3011e3ec7017SPing-Ke Shih static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3012e3ec7017SPing-Ke Shih { 3013e3ec7017SPing-Ke Shih int ret; 3014e3ec7017SPing-Ke Shih u32 reg; 3015e3ec7017SPing-Ke Shih u8 val; 3016e3ec7017SPing-Ke Shih 3017e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3018e3ec7017SPing-Ke Shih if (ret) 3019e3ec7017SPing-Ke Shih return ret; 3020e3ec7017SPing-Ke Shih 3021c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3022e3ec7017SPing-Ke Shih 3023e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, 3024e3ec7017SPing-Ke Shih (val & B_AX_PTCL_TX_ON_STAT) == 0, 3025e3ec7017SPing-Ke Shih SW_CVR_DUR_US, 3026e3ec7017SPing-Ke Shih SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3027e3ec7017SPing-Ke Shih false, rtwdev, reg); 3028e3ec7017SPing-Ke Shih if (ret) 3029e3ec7017SPing-Ke Shih return ret; 3030e3ec7017SPing-Ke Shih 3031e3ec7017SPing-Ke Shih return 0; 3032e3ec7017SPing-Ke Shih } 3033e3ec7017SPing-Ke Shih 3034e3ec7017SPing-Ke Shih static int band1_enable(struct rtw89_dev *rtwdev) 3035e3ec7017SPing-Ke Shih { 3036e3ec7017SPing-Ke Shih int ret, i; 3037e3ec7017SPing-Ke Shih u32 sleep_bak[4] = {0}; 3038e3ec7017SPing-Ke Shih u32 pause_bak[4] = {0}; 3039d780f926SPing-Ke Shih u32 tx_en; 3040e3ec7017SPing-Ke Shih 3041de7ba639SPing-Ke Shih ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3042e3ec7017SPing-Ke Shih if (ret) { 3043e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3044e3ec7017SPing-Ke Shih return ret; 3045e3ec7017SPing-Ke Shih } 3046e3ec7017SPing-Ke Shih 3047e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 3048e3ec7017SPing-Ke Shih sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3049e3ec7017SPing-Ke Shih pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3050e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3051e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3052e3ec7017SPing-Ke Shih } 3053e3ec7017SPing-Ke Shih 3054e3ec7017SPing-Ke Shih ret = band_idle_ck_b(rtwdev, 0); 3055e3ec7017SPing-Ke Shih if (ret) { 3056e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3057e3ec7017SPing-Ke Shih return ret; 3058e3ec7017SPing-Ke Shih } 3059e3ec7017SPing-Ke Shih 3060e3ec7017SPing-Ke Shih ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 3061e3ec7017SPing-Ke Shih if (ret) { 3062e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3063e3ec7017SPing-Ke Shih return ret; 3064e3ec7017SPing-Ke Shih } 3065e3ec7017SPing-Ke Shih 3066e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 3067e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3068e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3069e3ec7017SPing-Ke Shih } 3070e3ec7017SPing-Ke Shih 3071de7ba639SPing-Ke Shih ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3072e3ec7017SPing-Ke Shih if (ret) { 3073e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3074e3ec7017SPing-Ke Shih return ret; 3075e3ec7017SPing-Ke Shih } 3076e3ec7017SPing-Ke Shih 3077e3ec7017SPing-Ke Shih ret = cmac_func_en(rtwdev, 1, true); 3078e3ec7017SPing-Ke Shih if (ret) { 3079e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3080e3ec7017SPing-Ke Shih return ret; 3081e3ec7017SPing-Ke Shih } 3082e3ec7017SPing-Ke Shih 3083e3ec7017SPing-Ke Shih ret = cmac_init(rtwdev, 1); 3084e3ec7017SPing-Ke Shih if (ret) { 3085e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3086e3ec7017SPing-Ke Shih return ret; 3087e3ec7017SPing-Ke Shih } 3088e3ec7017SPing-Ke Shih 3089e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3090e3ec7017SPing-Ke Shih B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3091e3ec7017SPing-Ke Shih 3092e3ec7017SPing-Ke Shih return 0; 3093e3ec7017SPing-Ke Shih } 3094e3ec7017SPing-Ke Shih 3095eeadcd2aSChia-Yuan Li static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3096eeadcd2aSChia-Yuan Li { 3097eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3098eeadcd2aSChia-Yuan Li 3099eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3100eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3101eeadcd2aSChia-Yuan Li } 3102eeadcd2aSChia-Yuan Li 3103eeadcd2aSChia-Yuan Li static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3104eeadcd2aSChia-Yuan Li { 3105eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3106eeadcd2aSChia-Yuan Li 3107eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3108eeadcd2aSChia-Yuan Li } 3109eeadcd2aSChia-Yuan Li 3110eeadcd2aSChia-Yuan Li static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3111eeadcd2aSChia-Yuan Li { 3112eeadcd2aSChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3113eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3114eeadcd2aSChia-Yuan Li 3115eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3116eeadcd2aSChia-Yuan Li B_AX_TX_GET_ERRPKTID_INT_EN | 3117eeadcd2aSChia-Yuan Li B_AX_TX_NXT_ERRPKTID_INT_EN | 3118eeadcd2aSChia-Yuan Li B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3119eeadcd2aSChia-Yuan Li B_AX_TX_OFFSET_ERR_INT_EN | 3120eeadcd2aSChia-Yuan Li B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3121eeadcd2aSChia-Yuan Li if (chip_id == RTL8852C) 3122eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3123eeadcd2aSChia-Yuan Li B_AX_TX_ETH_TYPE_ERR_EN | 3124eeadcd2aSChia-Yuan Li B_AX_TX_LLC_PRE_ERR_EN | 3125eeadcd2aSChia-Yuan Li B_AX_TX_NW_TYPE_ERR_EN | 3126eeadcd2aSChia-Yuan Li B_AX_TX_KSRCH_ERR_EN); 3127eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3128eeadcd2aSChia-Yuan Li imr->mpdu_tx_imr_set); 3129eeadcd2aSChia-Yuan Li 3130eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3131eeadcd2aSChia-Yuan Li B_AX_GETPKTID_ERR_INT_EN | 3132eeadcd2aSChia-Yuan Li B_AX_MHDRLEN_ERR_INT_EN | 3133eeadcd2aSChia-Yuan Li B_AX_RPT_ERR_INT_EN); 3134eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3135eeadcd2aSChia-Yuan Li imr->mpdu_rx_imr_set); 3136eeadcd2aSChia-Yuan Li } 3137eeadcd2aSChia-Yuan Li 3138eeadcd2aSChia-Yuan Li static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3139eeadcd2aSChia-Yuan Li { 3140eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3141eeadcd2aSChia-Yuan Li 3142eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3143eeadcd2aSChia-Yuan Li B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3144eeadcd2aSChia-Yuan Li B_AX_RPT_HANG_TIMEOUT_INT_EN | 3145eeadcd2aSChia-Yuan Li B_AX_PLE_B_PKTID_ERR_INT_EN); 3146eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3147eeadcd2aSChia-Yuan Li imr->sta_sch_imr_set); 3148eeadcd2aSChia-Yuan Li } 3149eeadcd2aSChia-Yuan Li 3150eeadcd2aSChia-Yuan Li static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3151eeadcd2aSChia-Yuan Li { 3152eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3153eeadcd2aSChia-Yuan Li 3154eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3155eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b0_clr); 3156eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3157eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b0_set); 3158eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3159eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b1_clr); 3160eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3161eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b1_set); 3162eeadcd2aSChia-Yuan Li } 3163eeadcd2aSChia-Yuan Li 3164eeadcd2aSChia-Yuan Li static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3165eeadcd2aSChia-Yuan Li { 3166eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3167eeadcd2aSChia-Yuan Li 3168eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3169eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3170eeadcd2aSChia-Yuan Li } 3171eeadcd2aSChia-Yuan Li 3172eeadcd2aSChia-Yuan Li static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3173eeadcd2aSChia-Yuan Li { 3174eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3175eeadcd2aSChia-Yuan Li 3176eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3177eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3178eeadcd2aSChia-Yuan Li } 3179eeadcd2aSChia-Yuan Li 3180eeadcd2aSChia-Yuan Li static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3181eeadcd2aSChia-Yuan Li { 3182eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3183eeadcd2aSChia-Yuan Li B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3184eeadcd2aSChia-Yuan Li } 3185eeadcd2aSChia-Yuan Li 3186eeadcd2aSChia-Yuan Li static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3187eeadcd2aSChia-Yuan Li { 3188eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3189eeadcd2aSChia-Yuan Li 3190eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3191eeadcd2aSChia-Yuan Li imr->host_disp_imr_clr); 3192eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3193eeadcd2aSChia-Yuan Li imr->host_disp_imr_set); 3194eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3195eeadcd2aSChia-Yuan Li imr->cpu_disp_imr_clr); 3196eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3197eeadcd2aSChia-Yuan Li imr->cpu_disp_imr_set); 3198eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3199eeadcd2aSChia-Yuan Li imr->other_disp_imr_clr); 3200eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3201eeadcd2aSChia-Yuan Li imr->other_disp_imr_set); 3202eeadcd2aSChia-Yuan Li } 3203eeadcd2aSChia-Yuan Li 3204eeadcd2aSChia-Yuan Li static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3205eeadcd2aSChia-Yuan Li { 3206eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3207eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3208eeadcd2aSChia-Yuan Li } 3209eeadcd2aSChia-Yuan Li 3210eeadcd2aSChia-Yuan Li static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3211eeadcd2aSChia-Yuan Li { 3212eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3213eeadcd2aSChia-Yuan Li 321475f1ed29SPing-Ke Shih rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3215eeadcd2aSChia-Yuan Li B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3216eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3217eeadcd2aSChia-Yuan Li B_AX_BBRPT_CHINFO_IMR_CLR); 3218eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3219eeadcd2aSChia-Yuan Li imr->bbrpt_err_imr_set); 3220eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3221eeadcd2aSChia-Yuan Li B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3222eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3223eeadcd2aSChia-Yuan Li } 3224eeadcd2aSChia-Yuan Li 3225d86369e9SChia-Yuan Li static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3226d86369e9SChia-Yuan Li { 3227d86369e9SChia-Yuan Li u32 reg; 3228d86369e9SChia-Yuan Li 3229c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3230d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3231d86369e9SChia-Yuan Li B_AX_FSM_TIMEOUT_ERR_INT_EN); 3232d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3233d86369e9SChia-Yuan Li } 3234d86369e9SChia-Yuan Li 3235d86369e9SChia-Yuan Li static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3236d86369e9SChia-Yuan Li { 3237d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3238d86369e9SChia-Yuan Li u32 reg; 3239d86369e9SChia-Yuan Li 3240c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3241d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3242d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3243d86369e9SChia-Yuan Li } 3244d86369e9SChia-Yuan Li 3245d86369e9SChia-Yuan Li static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3246d86369e9SChia-Yuan Li { 3247d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3248d86369e9SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3249d86369e9SChia-Yuan Li u32 reg; 3250d86369e9SChia-Yuan Li 3251c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3252d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3253d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3254d86369e9SChia-Yuan Li 3255d86369e9SChia-Yuan Li if (chip_id == RTL8852C) { 3256c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3257d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3258d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3259d86369e9SChia-Yuan Li } 3260d86369e9SChia-Yuan Li } 3261d86369e9SChia-Yuan Li 3262d86369e9SChia-Yuan Li static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3263d86369e9SChia-Yuan Li { 3264d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3265d86369e9SChia-Yuan Li u32 reg; 3266d86369e9SChia-Yuan Li 3267c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3268d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3269d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3270d86369e9SChia-Yuan Li } 3271d86369e9SChia-Yuan Li 3272d86369e9SChia-Yuan Li static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3273d86369e9SChia-Yuan Li { 3274d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3275d86369e9SChia-Yuan Li u32 reg; 3276d86369e9SChia-Yuan Li 3277c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3278d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3279d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3280d86369e9SChia-Yuan Li } 3281d86369e9SChia-Yuan Li 3282d86369e9SChia-Yuan Li static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3283d86369e9SChia-Yuan Li { 3284d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3285d86369e9SChia-Yuan Li u32 reg; 3286d86369e9SChia-Yuan Li 3287c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3288d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3289d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3290d86369e9SChia-Yuan Li } 3291d86369e9SChia-Yuan Li 3292e3ec7017SPing-Ke Shih static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 3293e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 3294e3ec7017SPing-Ke Shih { 3295e3ec7017SPing-Ke Shih int ret; 3296e3ec7017SPing-Ke Shih 3297e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3298e3ec7017SPing-Ke Shih if (ret) { 3299e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3300e3ec7017SPing-Ke Shih sel, mac_idx); 3301e3ec7017SPing-Ke Shih return ret; 3302e3ec7017SPing-Ke Shih } 3303e3ec7017SPing-Ke Shih 3304e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 3305eeadcd2aSChia-Yuan Li rtw89_wdrls_imr_enable(rtwdev); 3306eeadcd2aSChia-Yuan Li rtw89_wsec_imr_enable(rtwdev); 3307eeadcd2aSChia-Yuan Li rtw89_mpdu_trx_imr_enable(rtwdev); 3308eeadcd2aSChia-Yuan Li rtw89_sta_sch_imr_enable(rtwdev); 3309eeadcd2aSChia-Yuan Li rtw89_txpktctl_imr_enable(rtwdev); 3310eeadcd2aSChia-Yuan Li rtw89_wde_imr_enable(rtwdev); 3311eeadcd2aSChia-Yuan Li rtw89_ple_imr_enable(rtwdev); 3312eeadcd2aSChia-Yuan Li rtw89_pktin_imr_enable(rtwdev); 3313eeadcd2aSChia-Yuan Li rtw89_dispatcher_imr_enable(rtwdev); 3314eeadcd2aSChia-Yuan Li rtw89_cpuio_imr_enable(rtwdev); 3315eeadcd2aSChia-Yuan Li rtw89_bbrpt_imr_enable(rtwdev); 3316e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL) { 3317d86369e9SChia-Yuan Li rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3318d86369e9SChia-Yuan Li rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3319d86369e9SChia-Yuan Li rtw89_cdma_imr_enable(rtwdev, mac_idx); 3320d86369e9SChia-Yuan Li rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3321d86369e9SChia-Yuan Li rtw89_rmac_imr_enable(rtwdev, mac_idx); 3322d86369e9SChia-Yuan Li rtw89_tmac_imr_enable(rtwdev, mac_idx); 3323e3ec7017SPing-Ke Shih } else { 3324e3ec7017SPing-Ke Shih return -EINVAL; 3325e3ec7017SPing-Ke Shih } 3326e3ec7017SPing-Ke Shih 3327e3ec7017SPing-Ke Shih return 0; 3328e3ec7017SPing-Ke Shih } 3329e3ec7017SPing-Ke Shih 33309f405b01SPing-Ke Shih static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) 33319f405b01SPing-Ke Shih { 33329f405b01SPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 33339f405b01SPing-Ke Shih 33349f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 33359f405b01SPing-Ke Shih en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 33369f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 33379f405b01SPing-Ke Shih en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 33389f405b01SPing-Ke Shih if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 33399f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 33409f405b01SPing-Ke Shih en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 33419f405b01SPing-Ke Shih } 33429f405b01SPing-Ke Shih 3343e3ec7017SPing-Ke Shih static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 3344e3ec7017SPing-Ke Shih { 3345e3ec7017SPing-Ke Shih int ret = 0; 3346e3ec7017SPing-Ke Shih 3347e3ec7017SPing-Ke Shih if (enable) { 3348e3ec7017SPing-Ke Shih ret = band1_enable(rtwdev); 3349e3ec7017SPing-Ke Shih if (ret) { 3350e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3351e3ec7017SPing-Ke Shih return ret; 3352e3ec7017SPing-Ke Shih } 3353e3ec7017SPing-Ke Shih 3354e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3355e3ec7017SPing-Ke Shih if (ret) { 3356e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3357e3ec7017SPing-Ke Shih return ret; 3358e3ec7017SPing-Ke Shih } 3359e3ec7017SPing-Ke Shih } else { 3360e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3361e3ec7017SPing-Ke Shih return -EINVAL; 3362e3ec7017SPing-Ke Shih } 3363e3ec7017SPing-Ke Shih 3364e3ec7017SPing-Ke Shih return 0; 3365e3ec7017SPing-Ke Shih } 3366e3ec7017SPing-Ke Shih 3367e3ec7017SPing-Ke Shih static int set_host_rpr(struct rtw89_dev *rtwdev) 3368e3ec7017SPing-Ke Shih { 3369e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3370e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3371e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3372e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3373e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 3374e3ec7017SPing-Ke Shih } else { 3375e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3376e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3377e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3378e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 3379e3ec7017SPing-Ke Shih } 3380e3ec7017SPing-Ke Shih 3381e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3382e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3383e3ec7017SPing-Ke Shih 3384e3ec7017SPing-Ke Shih return 0; 3385e3ec7017SPing-Ke Shih } 3386e3ec7017SPing-Ke Shih 3387e3ec7017SPing-Ke Shih static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 3388e3ec7017SPing-Ke Shih { 3389e3ec7017SPing-Ke Shih enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3390e3ec7017SPing-Ke Shih int ret; 3391e3ec7017SPing-Ke Shih 3392e3ec7017SPing-Ke Shih ret = dmac_init(rtwdev, 0); 3393e3ec7017SPing-Ke Shih if (ret) { 3394e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3395e3ec7017SPing-Ke Shih return ret; 3396e3ec7017SPing-Ke Shih } 3397e3ec7017SPing-Ke Shih 3398e3ec7017SPing-Ke Shih ret = cmac_init(rtwdev, 0); 3399e3ec7017SPing-Ke Shih if (ret) { 3400e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3401e3ec7017SPing-Ke Shih return ret; 3402e3ec7017SPing-Ke Shih } 3403e3ec7017SPing-Ke Shih 3404e3ec7017SPing-Ke Shih if (is_qta_dbcc(rtwdev, qta_mode)) { 3405e3ec7017SPing-Ke Shih ret = rtw89_mac_dbcc_enable(rtwdev, true); 3406e3ec7017SPing-Ke Shih if (ret) { 3407e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3408e3ec7017SPing-Ke Shih return ret; 3409e3ec7017SPing-Ke Shih } 3410e3ec7017SPing-Ke Shih } 3411e3ec7017SPing-Ke Shih 3412e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3413e3ec7017SPing-Ke Shih if (ret) { 3414e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3415e3ec7017SPing-Ke Shih return ret; 3416e3ec7017SPing-Ke Shih } 3417e3ec7017SPing-Ke Shih 3418e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3419e3ec7017SPing-Ke Shih if (ret) { 3420e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3421e3ec7017SPing-Ke Shih return ret; 3422e3ec7017SPing-Ke Shih } 3423e3ec7017SPing-Ke Shih 34249f405b01SPing-Ke Shih rtw89_mac_err_imr_ctrl(rtwdev, true); 34259f405b01SPing-Ke Shih 3426e3ec7017SPing-Ke Shih ret = set_host_rpr(rtwdev); 3427e3ec7017SPing-Ke Shih if (ret) { 3428e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3429e3ec7017SPing-Ke Shih return ret; 3430e3ec7017SPing-Ke Shih } 3431e3ec7017SPing-Ke Shih 3432e3ec7017SPing-Ke Shih return 0; 3433e3ec7017SPing-Ke Shih } 3434e3ec7017SPing-Ke Shih 3435ec356ffbSChia-Yuan Li static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3436ec356ffbSChia-Yuan Li { 34375c3afcbaSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3438ec356ffbSChia-Yuan Li u32 val32; 3439ec356ffbSChia-Yuan Li 34405c3afcbaSPing-Ke Shih if (chip_id == RTL8852B || chip_id == RTL8851B) { 34415c3afcbaSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 34425c3afcbaSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 34435c3afcbaSPing-Ke Shih return; 34445c3afcbaSPing-Ke Shih } 34455c3afcbaSPing-Ke Shih 3446ec356ffbSChia-Yuan Li rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3447ec356ffbSChia-Yuan Li WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3448ec356ffbSChia-Yuan Li 3449ec356ffbSChia-Yuan Li val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3450ec356ffbSChia-Yuan Li val32 |= B_AX_FS_WDT_INT; 3451ec356ffbSChia-Yuan Li val32 &= ~B_AX_FS_WDT_INT_MSK; 3452ec356ffbSChia-Yuan Li rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3453ec356ffbSChia-Yuan Li } 3454ec356ffbSChia-Yuan Li 3455ae4dc23dSPing-Ke Shih static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3456e3ec7017SPing-Ke Shih { 3457e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3458e3ec7017SPing-Ke Shih 3459e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3460de78869dSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3461de78869dSChia-Yuan Li B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3462e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3463ec356ffbSChia-Yuan Li 3464ec356ffbSChia-Yuan Li rtw89_disable_fw_watchdog(rtwdev); 3465ec356ffbSChia-Yuan Li 3466de78869dSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3467de78869dSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3468e3ec7017SPing-Ke Shih } 3469e3ec7017SPing-Ke Shih 3470a712eef6SPing-Ke Shih static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3471a712eef6SPing-Ke Shih bool dlfw, bool include_bb) 3472e3ec7017SPing-Ke Shih { 3473e3ec7017SPing-Ke Shih u32 val; 3474e3ec7017SPing-Ke Shih int ret; 3475e3ec7017SPing-Ke Shih 3476e3ec7017SPing-Ke Shih if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3477e3ec7017SPing-Ke Shih return -EFAULT; 3478e3ec7017SPing-Ke Shih 3479e749ef96SPing-Ke Shih rtw89_write32(rtwdev, R_AX_UDM1, 0); 3480e749ef96SPing-Ke Shih rtw89_write32(rtwdev, R_AX_UDM2, 0); 3481e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3482e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3483a63ae673SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3484a63ae673SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3485e3ec7017SPing-Ke Shih 3486e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3487e3ec7017SPing-Ke Shih 3488e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3489e3ec7017SPing-Ke Shih val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3490e3ec7017SPing-Ke Shih val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3491e3ec7017SPing-Ke Shih B_AX_WCPU_FWDL_STS_MASK); 3492e3ec7017SPing-Ke Shih 3493e3ec7017SPing-Ke Shih if (dlfw) 3494e3ec7017SPing-Ke Shih val |= B_AX_WCPU_FWDL_EN; 3495e3ec7017SPing-Ke Shih 3496e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 34972e5a65f5SPing-Ke Shih 34982e5a65f5SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852B) 34992e5a65f5SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 35002e5a65f5SPing-Ke Shih B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 35012e5a65f5SPing-Ke Shih 3502e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3503e3ec7017SPing-Ke Shih boot_reason); 3504e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3505e3ec7017SPing-Ke Shih 3506e3ec7017SPing-Ke Shih if (!dlfw) { 3507e3ec7017SPing-Ke Shih mdelay(5); 3508e3ec7017SPing-Ke Shih 3509fa31a8c5SPing-Ke Shih ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3510e3ec7017SPing-Ke Shih if (ret) 3511e3ec7017SPing-Ke Shih return ret; 3512e3ec7017SPing-Ke Shih } 3513e3ec7017SPing-Ke Shih 3514e3ec7017SPing-Ke Shih return 0; 3515e3ec7017SPing-Ke Shih } 3516e3ec7017SPing-Ke Shih 3517a7d82a7aSPing-Ke Shih static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3518e3ec7017SPing-Ke Shih { 3519a7d82a7aSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3520e3ec7017SPing-Ke Shih u32 val; 3521e3ec7017SPing-Ke Shih int ret; 3522e3ec7017SPing-Ke Shih 3523a7d82a7aSPing-Ke Shih if (chip_id == RTL8852C) 3524a7d82a7aSPing-Ke Shih val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3525a7d82a7aSPing-Ke Shih B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3526a7d82a7aSPing-Ke Shih else 3527e3ec7017SPing-Ke Shih val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3528e3ec7017SPing-Ke Shih B_AX_PKT_BUF_EN; 3529e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3530e3ec7017SPing-Ke Shih 35315c3afcbaSPing-Ke Shih if (chip_id == RTL8851B) 35325c3afcbaSPing-Ke Shih val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 35335c3afcbaSPing-Ke Shih else 3534e3ec7017SPing-Ke Shih val = B_AX_DISPATCHER_CLK_EN; 3535e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3536e3ec7017SPing-Ke Shih 3537a7d82a7aSPing-Ke Shih if (chip_id != RTL8852C) 3538a7d82a7aSPing-Ke Shih goto dle; 3539a7d82a7aSPing-Ke Shih 3540a7d82a7aSPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3541a7d82a7aSPing-Ke Shih val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3542a7d82a7aSPing-Ke Shih val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3543a7d82a7aSPing-Ke Shih B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3544a7d82a7aSPing-Ke Shih rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3545a7d82a7aSPing-Ke Shih 3546a7d82a7aSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3547a7d82a7aSPing-Ke Shih B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3548a7d82a7aSPing-Ke Shih B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3549a7d82a7aSPing-Ke Shih B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3550a7d82a7aSPing-Ke Shih B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3551a7d82a7aSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3552a7d82a7aSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3553a7d82a7aSPing-Ke Shih 3554a7d82a7aSPing-Ke Shih dle: 3555e3ec7017SPing-Ke Shih ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3556e3ec7017SPing-Ke Shih if (ret) { 3557e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3558e3ec7017SPing-Ke Shih return ret; 3559e3ec7017SPing-Ke Shih } 3560e3ec7017SPing-Ke Shih 3561e3ec7017SPing-Ke Shih ret = hfc_init(rtwdev, true, false, true); 3562e3ec7017SPing-Ke Shih if (ret) { 3563e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3564e3ec7017SPing-Ke Shih return ret; 3565e3ec7017SPing-Ke Shih } 3566e3ec7017SPing-Ke Shih 3567e3ec7017SPing-Ke Shih return ret; 3568e3ec7017SPing-Ke Shih } 3569e3ec7017SPing-Ke Shih 357061ebeecbSPing-Ke Shih int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3571e3ec7017SPing-Ke Shih { 3572e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3573e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3574e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3575e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3576e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3577e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 357861ebeecbSPing-Ke Shih 357961ebeecbSPing-Ke Shih return 0; 3580e3ec7017SPing-Ke Shih } 358161ebeecbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3582e3ec7017SPing-Ke Shih 358314b6e9f4SPing-Ke Shih int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3584e3ec7017SPing-Ke Shih { 3585e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3586e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3587e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3588e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3589e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3590e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 359114b6e9f4SPing-Ke Shih 359214b6e9f4SPing-Ke Shih return 0; 3593e3ec7017SPing-Ke Shih } 359461ebeecbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3595e3ec7017SPing-Ke Shih 3596a712eef6SPing-Ke Shih int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 3597e3ec7017SPing-Ke Shih { 3598e3ec7017SPing-Ke Shih int ret; 3599e3ec7017SPing-Ke Shih 3600e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 3601e3ec7017SPing-Ke Shih if (ret) { 3602e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 3603e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 3604e3ec7017SPing-Ke Shih if (ret) 3605e3ec7017SPing-Ke Shih return ret; 3606e3ec7017SPing-Ke Shih } 3607e3ec7017SPing-Ke Shih 360852f12705SChin-Yen Lee rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3609e3ec7017SPing-Ke Shih 3610c6ea2a83SPing-Ke Shih if (include_bb) { 3611c6ea2a83SPing-Ke Shih rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 3612c6ea2a83SPing-Ke Shih if (rtwdev->dbcc_en) 3613c6ea2a83SPing-Ke Shih rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 3614c6ea2a83SPing-Ke Shih } 3615c6ea2a83SPing-Ke Shih 3616a7d82a7aSPing-Ke Shih ret = rtw89_mac_dmac_pre_init(rtwdev); 3617a7d82a7aSPing-Ke Shih if (ret) 3618a7d82a7aSPing-Ke Shih return ret; 3619a7d82a7aSPing-Ke Shih 3620e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_pre_init) { 3621e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3622e3ec7017SPing-Ke Shih if (ret) 3623e3ec7017SPing-Ke Shih return ret; 3624e3ec7017SPing-Ke Shih } 3625e3ec7017SPing-Ke Shih 3626a712eef6SPing-Ke Shih ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 3627e3ec7017SPing-Ke Shih if (ret) 3628e3ec7017SPing-Ke Shih return ret; 3629e3ec7017SPing-Ke Shih 3630e3ec7017SPing-Ke Shih return 0; 3631e3ec7017SPing-Ke Shih } 3632e3ec7017SPing-Ke Shih 3633e3ec7017SPing-Ke Shih int rtw89_mac_init(struct rtw89_dev *rtwdev) 3634e3ec7017SPing-Ke Shih { 3635a712eef6SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 3636a712eef6SPing-Ke Shih bool include_bb = !!chip->bbmcu_nr; 3637e3ec7017SPing-Ke Shih int ret; 3638e3ec7017SPing-Ke Shih 3639a712eef6SPing-Ke Shih ret = rtw89_mac_partial_init(rtwdev, include_bb); 3640e3ec7017SPing-Ke Shih if (ret) 3641e3ec7017SPing-Ke Shih goto fail; 3642e3ec7017SPing-Ke Shih 364361ebeecbSPing-Ke Shih ret = rtw89_chip_enable_bb_rf(rtwdev); 364461ebeecbSPing-Ke Shih if (ret) 364561ebeecbSPing-Ke Shih goto fail; 3646e3ec7017SPing-Ke Shih 3647e3ec7017SPing-Ke Shih ret = rtw89_mac_sys_init(rtwdev); 3648e3ec7017SPing-Ke Shih if (ret) 3649e3ec7017SPing-Ke Shih goto fail; 3650e3ec7017SPing-Ke Shih 3651e3ec7017SPing-Ke Shih ret = rtw89_mac_trx_init(rtwdev); 3652e3ec7017SPing-Ke Shih if (ret) 3653e3ec7017SPing-Ke Shih goto fail; 3654e3ec7017SPing-Ke Shih 3655e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_post_init) { 3656e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3657e3ec7017SPing-Ke Shih if (ret) 3658e3ec7017SPing-Ke Shih goto fail; 3659e3ec7017SPing-Ke Shih } 3660e3ec7017SPing-Ke Shih 3661e3ec7017SPing-Ke Shih rtw89_fw_send_all_early_h2c(rtwdev); 3662e3ec7017SPing-Ke Shih rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3663e3ec7017SPing-Ke Shih 3664e3ec7017SPing-Ke Shih return ret; 3665e3ec7017SPing-Ke Shih fail: 3666e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 3667e3ec7017SPing-Ke Shih 3668e3ec7017SPing-Ke Shih return ret; 3669e3ec7017SPing-Ke Shih } 3670e3ec7017SPing-Ke Shih 3671e3ec7017SPing-Ke Shih static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3672e3ec7017SPing-Ke Shih { 3673e3ec7017SPing-Ke Shih u8 i; 3674e3ec7017SPing-Ke Shih 367560168f6cSPing-Ke Shih if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 367660168f6cSPing-Ke Shih return; 367760168f6cSPing-Ke Shih 3678e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 3679e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3680e3ec7017SPing-Ke Shih DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3681e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3682e3ec7017SPing-Ke Shih } 3683e3ec7017SPing-Ke Shih } 3684e3ec7017SPing-Ke Shih 3685e3ec7017SPing-Ke Shih static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3686e3ec7017SPing-Ke Shih { 368760168f6cSPing-Ke Shih if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 368860168f6cSPing-Ke Shih return; 368960168f6cSPing-Ke Shih 3690e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3691e3ec7017SPing-Ke Shih CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3692e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3693e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3694e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3695e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3696e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3697e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3698e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3699e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3700e3ec7017SPing-Ke Shih } 3701e3ec7017SPing-Ke Shih 37021b73e77dSPing-Ke Shih int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3703e3ec7017SPing-Ke Shih { 3704e3ec7017SPing-Ke Shih u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3705e3ec7017SPing-Ke Shih u8 grp = macid >> 5; 3706e3ec7017SPing-Ke Shih int ret; 3707e3ec7017SPing-Ke Shih 3708ac3a9f18SPing-Ke Shih /* If this is called by change_interface() in the case of P2P, it could 3709ac3a9f18SPing-Ke Shih * be power-off, so ignore this operation. 3710ac3a9f18SPing-Ke Shih */ 3711ac3a9f18SPing-Ke Shih if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 3712ac3a9f18SPing-Ke Shih !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3713ac3a9f18SPing-Ke Shih return 0; 3714ac3a9f18SPing-Ke Shih 3715e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3716e3ec7017SPing-Ke Shih if (ret) 3717e3ec7017SPing-Ke Shih return ret; 3718e3ec7017SPing-Ke Shih 3719e3ec7017SPing-Ke Shih rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3720e3ec7017SPing-Ke Shih 3721e3ec7017SPing-Ke Shih return 0; 3722e3ec7017SPing-Ke Shih } 3723e3ec7017SPing-Ke Shih 37247c8a55ddSPing-Ke Shih static const struct rtw89_port_reg rtw89_port_base_ax = { 3725e3ec7017SPing-Ke Shih .port_cfg = R_AX_PORT_CFG_P0, 3726e3ec7017SPing-Ke Shih .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3727e3ec7017SPing-Ke Shih .bcn_area = R_AX_BCN_AREA_P0, 3728e3ec7017SPing-Ke Shih .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3729e3ec7017SPing-Ke Shih .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3730e3ec7017SPing-Ke Shih .tbtt_agg = R_AX_TBTT_AGG_P0, 3731e3ec7017SPing-Ke Shih .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3732e3ec7017SPing-Ke Shih .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3733e3ec7017SPing-Ke Shih .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3734e3ec7017SPing-Ke Shih .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3735e3ec7017SPing-Ke Shih .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3736e3ec7017SPing-Ke Shih .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3737e3ec7017SPing-Ke Shih .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3738e3ec7017SPing-Ke Shih .tsftr_l = R_AX_TSFTR_LOW_P0, 373965129813SPing-Ke Shih .tsftr_h = R_AX_TSFTR_HIGH_P0, 374065129813SPing-Ke Shih .md_tsft = R_AX_MD_TSFT_STMP_CTL, 374165129813SPing-Ke Shih .bss_color = R_AX_PTCL_BSS_COLOR_0, 374265129813SPing-Ke Shih .mbssid = R_AX_MBSSID_CTRL, 374365129813SPing-Ke Shih .mbssid_drop = R_AX_MBSSID_DROP_0, 374465129813SPing-Ke Shih .tsf_sync = R_AX_PORT0_TSF_SYNC, 374565129813SPing-Ke Shih .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 374665129813SPing-Ke Shih R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 374765129813SPing-Ke Shih R_AX_PORT_HGQ_WINDOW_CFG + 3}, 3748e3ec7017SPing-Ke Shih }; 3749e3ec7017SPing-Ke Shih 3750e3ec7017SPing-Ke Shih #define BCN_INTERVAL 100 3751e3ec7017SPing-Ke Shih #define BCN_ERLY_DEF 160 3752e3ec7017SPing-Ke Shih #define BCN_SETUP_DEF 2 3753e3ec7017SPing-Ke Shih #define BCN_HOLD_DEF 200 3754e3ec7017SPing-Ke Shih #define BCN_MASK_DEF 0 3755e3ec7017SPing-Ke Shih #define TBTT_ERLY_DEF 5 3756e3ec7017SPing-Ke Shih #define BCN_SET_UNIT 32 3757e3ec7017SPing-Ke Shih #define BCN_ERLY_SET_DLY (10 * 2) 3758e3ec7017SPing-Ke Shih 3759e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3760e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3761e3ec7017SPing-Ke Shih { 37627c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 37637c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3764e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3765e3ec7017SPing-Ke Shih 3766e3ec7017SPing-Ke Shih if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3767e3ec7017SPing-Ke Shih return; 3768e3ec7017SPing-Ke Shih 3769e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3770e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3771e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3772e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3773e3ec7017SPing-Ke Shih 3774e3ec7017SPing-Ke Shih msleep(vif->bss_conf.beacon_int + 1); 3775e3ec7017SPing-Ke Shih 3776e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3777e3ec7017SPing-Ke Shih B_AX_BRK_SETUP); 3778e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3779e3ec7017SPing-Ke Shih rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3780e3ec7017SPing-Ke Shih } 3781e3ec7017SPing-Ke Shih 3782e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3783e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 3784e3ec7017SPing-Ke Shih { 37857c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 37867c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3787e3ec7017SPing-Ke Shih 3788e3ec7017SPing-Ke Shih if (en) 3789e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3790e3ec7017SPing-Ke Shih else 3791e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3792e3ec7017SPing-Ke Shih } 3793e3ec7017SPing-Ke Shih 3794e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3795e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 3796e3ec7017SPing-Ke Shih { 37977c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 37987c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3799e3ec7017SPing-Ke Shih 3800e3ec7017SPing-Ke Shih if (en) 3801e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3802e3ec7017SPing-Ke Shih else 3803e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3804e3ec7017SPing-Ke Shih } 3805e3ec7017SPing-Ke Shih 3806e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3807e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3808e3ec7017SPing-Ke Shih { 38097c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 38107c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3811e3ec7017SPing-Ke Shih 3812e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3813e3ec7017SPing-Ke Shih rtwvif->net_type); 3814e3ec7017SPing-Ke Shih } 3815e3ec7017SPing-Ke Shih 3816e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3817e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3818e3ec7017SPing-Ke Shih { 38197c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 38207c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3821e3ec7017SPing-Ke Shih bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3822e3ec7017SPing-Ke Shih u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3823e3ec7017SPing-Ke Shih 3824e3ec7017SPing-Ke Shih if (en) 3825e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3826e3ec7017SPing-Ke Shih else 3827e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3828e3ec7017SPing-Ke Shih } 3829e3ec7017SPing-Ke Shih 3830e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3831e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3832e3ec7017SPing-Ke Shih { 38337c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 38347c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3835e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3836e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3837e3ec7017SPing-Ke Shih u32 bit = B_AX_RX_BSSID_FIT_EN; 3838e3ec7017SPing-Ke Shih 3839e3ec7017SPing-Ke Shih if (en) 3840e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3841e3ec7017SPing-Ke Shih else 3842e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3843e3ec7017SPing-Ke Shih } 3844e3ec7017SPing-Ke Shih 3845e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3846e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3847e3ec7017SPing-Ke Shih { 38487c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 38497c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3850e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3851e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3852e3ec7017SPing-Ke Shih 3853e3ec7017SPing-Ke Shih if (en) 3854e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3855e3ec7017SPing-Ke Shih else 3856e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3857e3ec7017SPing-Ke Shih } 3858e3ec7017SPing-Ke Shih 3859e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3860e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3861e3ec7017SPing-Ke Shih { 38627c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 38637c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3864e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3865e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3866e3ec7017SPing-Ke Shih 3867e3ec7017SPing-Ke Shih if (en) 3868e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3869e3ec7017SPing-Ke Shih else 3870e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3871e3ec7017SPing-Ke Shih } 3872e3ec7017SPing-Ke Shih 3873e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3874e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3875e3ec7017SPing-Ke Shih { 38767c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 38777c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3878e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3879e3ec7017SPing-Ke Shih u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3880e3ec7017SPing-Ke Shih 3881e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3882e3ec7017SPing-Ke Shih bcn_int); 3883e3ec7017SPing-Ke Shih } 3884e3ec7017SPing-Ke Shih 3885283c3d88SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3886283c3d88SPing-Ke Shih struct rtw89_vif *rtwvif) 3887283c3d88SPing-Ke Shih { 3888283c3d88SPing-Ke Shih u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 38897c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 38907c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3891283c3d88SPing-Ke Shih u8 port = rtwvif->port; 3892283c3d88SPing-Ke Shih u32 reg; 3893283c3d88SPing-Ke Shih 389465129813SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif->mac_idx); 3895283c3d88SPing-Ke Shih rtw89_write8(rtwdev, reg, win); 3896283c3d88SPing-Ke Shih } 3897283c3d88SPing-Ke Shih 3898283c3d88SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3899283c3d88SPing-Ke Shih struct rtw89_vif *rtwvif) 3900283c3d88SPing-Ke Shih { 39017c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 39027c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3903283c3d88SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3904283c3d88SPing-Ke Shih u32 addr; 3905283c3d88SPing-Ke Shih 390665129813SPing-Ke Shih addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif->mac_idx); 3907283c3d88SPing-Ke Shih rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3908283c3d88SPing-Ke Shih 3909283c3d88SPing-Ke Shih rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3910283c3d88SPing-Ke Shih vif->bss_conf.dtim_period); 3911283c3d88SPing-Ke Shih } 3912283c3d88SPing-Ke Shih 3913e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3914e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3915e3ec7017SPing-Ke Shih { 39167c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 39177c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3918e3ec7017SPing-Ke Shih 3919e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3920e3ec7017SPing-Ke Shih B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3921e3ec7017SPing-Ke Shih } 3922e3ec7017SPing-Ke Shih 3923e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3924e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3925e3ec7017SPing-Ke Shih { 39267c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 39277c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3928e3ec7017SPing-Ke Shih 3929e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3930e3ec7017SPing-Ke Shih B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3931e3ec7017SPing-Ke Shih } 3932e3ec7017SPing-Ke Shih 3933e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3934e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3935e3ec7017SPing-Ke Shih { 39367c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 39377c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3938e3ec7017SPing-Ke Shih 3939e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3940e3ec7017SPing-Ke Shih B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3941e3ec7017SPing-Ke Shih } 3942e3ec7017SPing-Ke Shih 3943e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3944e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3945e3ec7017SPing-Ke Shih { 39467c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 39477c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3948e3ec7017SPing-Ke Shih 3949e3ec7017SPing-Ke Shih rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3950e3ec7017SPing-Ke Shih B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3951e3ec7017SPing-Ke Shih } 3952e3ec7017SPing-Ke Shih 3953e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3954e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3955e3ec7017SPing-Ke Shih { 39567c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 39577c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3958e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3959e3ec7017SPing-Ke Shih static const u32 masks[RTW89_PORT_NUM] = { 3960e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3961e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3962e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_4_MASK, 3963e3ec7017SPing-Ke Shih }; 3964e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3965e3ec7017SPing-Ke Shih u32 reg_base; 3966e3ec7017SPing-Ke Shih u32 reg; 3967e3ec7017SPing-Ke Shih u8 bss_color; 3968e3ec7017SPing-Ke Shih 3969e3ec7017SPing-Ke Shih bss_color = vif->bss_conf.he_bss_color.color; 397065129813SPing-Ke Shih reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 3971c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx); 3972e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3973e3ec7017SPing-Ke Shih } 3974e3ec7017SPing-Ke Shih 3975e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3976e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3977e3ec7017SPing-Ke Shih { 39787c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 39797c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3980e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3981e3ec7017SPing-Ke Shih u32 reg; 3982e3ec7017SPing-Ke Shih 3983e3ec7017SPing-Ke Shih if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3984e3ec7017SPing-Ke Shih return; 3985e3ec7017SPing-Ke Shih 3986e3ec7017SPing-Ke Shih if (port == 0) { 398765129813SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif->mac_idx); 3988e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3989e3ec7017SPing-Ke Shih } 3990e3ec7017SPing-Ke Shih } 3991e3ec7017SPing-Ke Shih 3992e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3993e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 3994e3ec7017SPing-Ke Shih { 39957c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 39967c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 3997e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3998e3ec7017SPing-Ke Shih u32 reg; 3999e3ec7017SPing-Ke Shih u32 val; 4000e3ec7017SPing-Ke Shih 400165129813SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif->mac_idx); 4002e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 4003e3ec7017SPing-Ke Shih val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4004e3ec7017SPing-Ke Shih if (port == 0) 4005e3ec7017SPing-Ke Shih val &= ~BIT(0); 4006e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 4007e3ec7017SPing-Ke Shih } 4008e3ec7017SPing-Ke Shih 4009e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4010d592b9f7SPo-Hao Huang struct rtw89_vif *rtwvif, bool enable) 4011e3ec7017SPing-Ke Shih { 40127c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 40137c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4014e3ec7017SPing-Ke Shih 4015d592b9f7SPo-Hao Huang if (enable) 4016d592b9f7SPo-Hao Huang rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 4017d592b9f7SPo-Hao Huang B_AX_PORT_FUNC_EN); 4018d592b9f7SPo-Hao Huang else 4019d592b9f7SPo-Hao Huang rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 4020d592b9f7SPo-Hao Huang B_AX_PORT_FUNC_EN); 4021e3ec7017SPing-Ke Shih } 4022e3ec7017SPing-Ke Shih 4023e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4024e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4025e3ec7017SPing-Ke Shih { 40267c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 40277c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4028e3ec7017SPing-Ke Shih 4029e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 4030e3ec7017SPing-Ke Shih BCN_ERLY_DEF); 4031e3ec7017SPing-Ke Shih } 4032e3ec7017SPing-Ke Shih 4033704052f5SChia-Yuan Li static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4034704052f5SChia-Yuan Li struct rtw89_vif *rtwvif) 4035704052f5SChia-Yuan Li { 40367c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 40377c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4038704052f5SChia-Yuan Li u16 val; 4039704052f5SChia-Yuan Li 4040704052f5SChia-Yuan Li if (rtwdev->chip->chip_id != RTL8852C) 4041704052f5SChia-Yuan Li return; 4042704052f5SChia-Yuan Li 4043704052f5SChia-Yuan Li if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4044704052f5SChia-Yuan Li rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4045704052f5SChia-Yuan Li return; 4046704052f5SChia-Yuan Li 4047704052f5SChia-Yuan Li val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4048704052f5SChia-Yuan Li B_AX_TBTT_SHIFT_OFST_SIGN; 4049704052f5SChia-Yuan Li 4050704052f5SChia-Yuan Li rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 4051704052f5SChia-Yuan Li B_AX_TBTT_SHIFT_OFST_MASK, val); 4052704052f5SChia-Yuan Li } 4053704052f5SChia-Yuan Li 405442db7eddSZong-Zhe Yang void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4055fb2b8cecSPo-Hao Huang struct rtw89_vif *rtwvif, 405642db7eddSZong-Zhe Yang struct rtw89_vif *rtwvif_src, 405742db7eddSZong-Zhe Yang u16 offset_tu) 4058fb2b8cecSPo-Hao Huang { 40597c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 40607c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4061fb2b8cecSPo-Hao Huang u32 val, reg; 4062fb2b8cecSPo-Hao Huang 406342db7eddSZong-Zhe Yang val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 406465129813SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif->port * 4, 406542db7eddSZong-Zhe Yang rtwvif->mac_idx); 406642db7eddSZong-Zhe Yang 406742db7eddSZong-Zhe Yang rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 406842db7eddSZong-Zhe Yang rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 406942db7eddSZong-Zhe Yang rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 407042db7eddSZong-Zhe Yang } 407142db7eddSZong-Zhe Yang 407242db7eddSZong-Zhe Yang static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 407342db7eddSZong-Zhe Yang struct rtw89_vif *rtwvif, 407442db7eddSZong-Zhe Yang struct rtw89_vif *rtwvif_src, 407542db7eddSZong-Zhe Yang u8 offset, int *n_offset) 407642db7eddSZong-Zhe Yang { 4077fb2b8cecSPo-Hao Huang if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 4078fb2b8cecSPo-Hao Huang return; 4079fb2b8cecSPo-Hao Huang 4080fb2b8cecSPo-Hao Huang /* adjust offset randomly to avoid beacon conflict */ 4081fb2b8cecSPo-Hao Huang offset = offset - offset / 4 + get_random_u32() % (offset / 2); 408242db7eddSZong-Zhe Yang rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 408342db7eddSZong-Zhe Yang (*n_offset) * offset); 4084fb2b8cecSPo-Hao Huang 40851120e6a6SZong-Zhe Yang (*n_offset)++; 4086fb2b8cecSPo-Hao Huang } 4087fb2b8cecSPo-Hao Huang 4088fb2b8cecSPo-Hao Huang static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4089fb2b8cecSPo-Hao Huang { 4090fb2b8cecSPo-Hao Huang struct rtw89_vif *src = NULL, *tmp; 4091fb2b8cecSPo-Hao Huang u8 offset = 100, vif_aps = 0; 4092fb2b8cecSPo-Hao Huang int n_offset = 1; 4093fb2b8cecSPo-Hao Huang 4094fb2b8cecSPo-Hao Huang rtw89_for_each_rtwvif(rtwdev, tmp) { 4095fb2b8cecSPo-Hao Huang if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4096fb2b8cecSPo-Hao Huang src = tmp; 4097fb2b8cecSPo-Hao Huang if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4098fb2b8cecSPo-Hao Huang vif_aps++; 4099fb2b8cecSPo-Hao Huang } 4100fb2b8cecSPo-Hao Huang 4101fb2b8cecSPo-Hao Huang if (vif_aps == 0) 4102fb2b8cecSPo-Hao Huang return; 4103fb2b8cecSPo-Hao Huang 4104fb2b8cecSPo-Hao Huang offset /= (vif_aps + 1); 4105fb2b8cecSPo-Hao Huang 4106fb2b8cecSPo-Hao Huang rtw89_for_each_rtwvif(rtwdev, tmp) 410742db7eddSZong-Zhe Yang rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4108fb2b8cecSPo-Hao Huang } 4109fb2b8cecSPo-Hao Huang 4110e3ec7017SPing-Ke Shih int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4111e3ec7017SPing-Ke Shih { 4112e3ec7017SPing-Ke Shih int ret; 4113e3ec7017SPing-Ke Shih 4114e3ec7017SPing-Ke Shih ret = rtw89_mac_port_update(rtwdev, rtwvif); 4115e3ec7017SPing-Ke Shih if (ret) 4116e3ec7017SPing-Ke Shih return ret; 4117e3ec7017SPing-Ke Shih 4118e3ec7017SPing-Ke Shih rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4119e3ec7017SPing-Ke Shih rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4120e3ec7017SPing-Ke Shih 41211b73e77dSPing-Ke Shih ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4122e3ec7017SPing-Ke Shih if (ret) 4123e3ec7017SPing-Ke Shih return ret; 4124e3ec7017SPing-Ke Shih 4125ff66964aSPing-Ke Shih ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4126e3ec7017SPing-Ke Shih if (ret) 4127e3ec7017SPing-Ke Shih return ret; 4128e3ec7017SPing-Ke Shih 4129a0e78d5cSPo-Hao Huang ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4130a0e78d5cSPo-Hao Huang if (ret) 4131a0e78d5cSPo-Hao Huang return ret; 4132a0e78d5cSPo-Hao Huang 4133e3ec7017SPing-Ke Shih ret = rtw89_cam_init(rtwdev, rtwvif); 4134e3ec7017SPing-Ke Shih if (ret) 4135e3ec7017SPing-Ke Shih return ret; 4136e3ec7017SPing-Ke Shih 413740822e07SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4138e3ec7017SPing-Ke Shih if (ret) 4139e3ec7017SPing-Ke Shih return ret; 4140e3ec7017SPing-Ke Shih 4141742c470bSPing-Ke Shih ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 4142e3ec7017SPing-Ke Shih if (ret) 4143e3ec7017SPing-Ke Shih return ret; 4144e3ec7017SPing-Ke Shih 4145e3ec7017SPing-Ke Shih return 0; 4146e3ec7017SPing-Ke Shih } 4147e3ec7017SPing-Ke Shih 4148e3ec7017SPing-Ke Shih int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4149e3ec7017SPing-Ke Shih { 4150e3ec7017SPing-Ke Shih int ret; 4151e3ec7017SPing-Ke Shih 4152ff66964aSPing-Ke Shih ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4153e3ec7017SPing-Ke Shih if (ret) 4154e3ec7017SPing-Ke Shih return ret; 4155e3ec7017SPing-Ke Shih 4156e3ec7017SPing-Ke Shih rtw89_cam_deinit(rtwdev, rtwvif); 4157e3ec7017SPing-Ke Shih 415840822e07SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4159e3ec7017SPing-Ke Shih if (ret) 4160e3ec7017SPing-Ke Shih return ret; 4161e3ec7017SPing-Ke Shih 4162e3ec7017SPing-Ke Shih return 0; 4163e3ec7017SPing-Ke Shih } 4164e3ec7017SPing-Ke Shih 4165e3ec7017SPing-Ke Shih int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4166e3ec7017SPing-Ke Shih { 4167e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 4168e3ec7017SPing-Ke Shih 4169e3ec7017SPing-Ke Shih if (port >= RTW89_PORT_NUM) 4170e3ec7017SPing-Ke Shih return -EINVAL; 4171e3ec7017SPing-Ke Shih 4172e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4173e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4174e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4175e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4176e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4177e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4178e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 4179e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 4180e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4181283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4182283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4183283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4184e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4185e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4186e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4187e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4188704052f5SChia-Yuan Li rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4189e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4190e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4191d592b9f7SPo-Hao Huang rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4192fb2b8cecSPo-Hao Huang rtw89_mac_port_tsf_resync_all(rtwdev); 4193e3ec7017SPing-Ke Shih fsleep(BCN_ERLY_SET_DLY); 4194e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4195e3ec7017SPing-Ke Shih 4196e3ec7017SPing-Ke Shih return 0; 4197e3ec7017SPing-Ke Shih } 4198e3ec7017SPing-Ke Shih 419976f478a3SZong-Zhe Yang int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 420076f478a3SZong-Zhe Yang u64 *tsf) 420176f478a3SZong-Zhe Yang { 42027c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 42037c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 420476f478a3SZong-Zhe Yang u32 tsf_low, tsf_high; 420576f478a3SZong-Zhe Yang int ret; 420676f478a3SZong-Zhe Yang 420776f478a3SZong-Zhe Yang ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 420876f478a3SZong-Zhe Yang if (ret) 420976f478a3SZong-Zhe Yang return ret; 421076f478a3SZong-Zhe Yang 421176f478a3SZong-Zhe Yang tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 421276f478a3SZong-Zhe Yang tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 421376f478a3SZong-Zhe Yang *tsf = (u64)tsf_high << 32 | tsf_low; 421476f478a3SZong-Zhe Yang 421576f478a3SZong-Zhe Yang return 0; 421676f478a3SZong-Zhe Yang } 421776f478a3SZong-Zhe Yang 42188d540f9dSKuan-Chung Chen static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 42198d540f9dSKuan-Chung Chen struct cfg80211_bss *bss, 42208d540f9dSKuan-Chung Chen void *data) 42218d540f9dSKuan-Chung Chen { 42228d540f9dSKuan-Chung Chen const struct cfg80211_bss_ies *ies; 42238d540f9dSKuan-Chung Chen const struct element *elem; 42248d540f9dSKuan-Chung Chen bool *tolerated = data; 42258d540f9dSKuan-Chung Chen 42268d540f9dSKuan-Chung Chen rcu_read_lock(); 42278d540f9dSKuan-Chung Chen ies = rcu_dereference(bss->ies); 42288d540f9dSKuan-Chung Chen elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 42298d540f9dSKuan-Chung Chen ies->len); 42308d540f9dSKuan-Chung Chen 42318d540f9dSKuan-Chung Chen if (!elem || elem->datalen < 10 || 42328d540f9dSKuan-Chung Chen !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 42338d540f9dSKuan-Chung Chen *tolerated = false; 42348d540f9dSKuan-Chung Chen rcu_read_unlock(); 42358d540f9dSKuan-Chung Chen } 42368d540f9dSKuan-Chung Chen 42378d540f9dSKuan-Chung Chen void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 42388d540f9dSKuan-Chung Chen struct ieee80211_vif *vif) 42398d540f9dSKuan-Chung Chen { 42408d540f9dSKuan-Chung Chen struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 42418d540f9dSKuan-Chung Chen struct ieee80211_hw *hw = rtwdev->hw; 42428d540f9dSKuan-Chung Chen bool tolerated = true; 42438d540f9dSKuan-Chung Chen u32 reg; 42448d540f9dSKuan-Chung Chen 42458d540f9dSKuan-Chung Chen if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 42468d540f9dSKuan-Chung Chen return; 42478d540f9dSKuan-Chung Chen 42488d540f9dSKuan-Chung Chen if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR)) 42498d540f9dSKuan-Chung Chen return; 42508d540f9dSKuan-Chung Chen 42518d540f9dSKuan-Chung Chen cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef, 42528d540f9dSKuan-Chung Chen rtw89_mac_check_he_obss_narrow_bw_ru_iter, 42538d540f9dSKuan-Chung Chen &tolerated); 42548d540f9dSKuan-Chung Chen 4255c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); 42568d540f9dSKuan-Chung Chen if (tolerated) 42578d540f9dSKuan-Chung Chen rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 42588d540f9dSKuan-Chung Chen else 42598d540f9dSKuan-Chung Chen rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 42608d540f9dSKuan-Chung Chen } 42618d540f9dSKuan-Chung Chen 4262d592b9f7SPo-Hao Huang void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4263d592b9f7SPo-Hao Huang { 4264d592b9f7SPo-Hao Huang rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false); 4265d592b9f7SPo-Hao Huang } 4266d592b9f7SPo-Hao Huang 4267e3ec7017SPing-Ke Shih int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4268e3ec7017SPing-Ke Shih { 4269e3ec7017SPing-Ke Shih int ret; 4270e3ec7017SPing-Ke Shih 4271e3ec7017SPing-Ke Shih rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 4272e3ec7017SPing-Ke Shih RTW89_MAX_MAC_ID_NUM); 4273e3ec7017SPing-Ke Shih if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4274e3ec7017SPing-Ke Shih return -ENOSPC; 4275e3ec7017SPing-Ke Shih 4276e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4277e3ec7017SPing-Ke Shih if (ret) 4278e3ec7017SPing-Ke Shih goto release_mac_id; 4279e3ec7017SPing-Ke Shih 4280e3ec7017SPing-Ke Shih return 0; 4281e3ec7017SPing-Ke Shih 4282e3ec7017SPing-Ke Shih release_mac_id: 4283e3ec7017SPing-Ke Shih rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4284e3ec7017SPing-Ke Shih 4285e3ec7017SPing-Ke Shih return ret; 4286e3ec7017SPing-Ke Shih } 4287e3ec7017SPing-Ke Shih 4288e3ec7017SPing-Ke Shih int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4289e3ec7017SPing-Ke Shih { 4290e3ec7017SPing-Ke Shih int ret; 4291e3ec7017SPing-Ke Shih 4292e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4293e3ec7017SPing-Ke Shih rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4294e3ec7017SPing-Ke Shih 4295e3ec7017SPing-Ke Shih return ret; 4296e3ec7017SPing-Ke Shih } 4297e3ec7017SPing-Ke Shih 4298e3ec7017SPing-Ke Shih static void 4299e3ec7017SPing-Ke Shih rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4300e3ec7017SPing-Ke Shih { 4301e3ec7017SPing-Ke Shih } 4302e3ec7017SPing-Ke Shih 430389590777SPo Hao Huang static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 430489590777SPo Hao Huang { 4305e7399db2SPo-Hao Huang const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 430689590777SPo Hao Huang 4307e7399db2SPo-Hao Huang return band == op->band_type && channel == op->primary_channel; 430889590777SPo Hao Huang } 430989590777SPo Hao Huang 431089590777SPo Hao Huang static void 431189590777SPo Hao Huang rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 431289590777SPo Hao Huang u32 len) 431389590777SPo Hao Huang { 431489590777SPo Hao Huang struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4315bd1056d4SPo-Hao Huang struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4316cbb145b9SZong-Zhe Yang struct rtw89_chan new; 43173a1e7cb1SPo-Hao Huang u8 reason, status, tx_fail, band, actual_period; 4318bd1056d4SPo-Hao Huang u32 last_chan = rtwdev->scan_info.last_chan_idx; 431989590777SPo Hao Huang u16 chan; 4320bd1056d4SPo-Hao Huang int ret; 432189590777SPo Hao Huang 4322a0e97ae3SPo-Hao Huang if (!rtwvif) 4323a0e97ae3SPo-Hao Huang return; 4324a0e97ae3SPo-Hao Huang 432589590777SPo Hao Huang tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 432689590777SPo Hao Huang status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 432789590777SPo Hao Huang chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 432889590777SPo Hao Huang reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 432989590777SPo Hao Huang band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 43303a1e7cb1SPo-Hao Huang actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data); 433189590777SPo Hao Huang 433289590777SPo Hao Huang if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 433389590777SPo Hao Huang band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 433489590777SPo Hao Huang 433589590777SPo Hao Huang rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 43363a1e7cb1SPo-Hao Huang "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 43373a1e7cb1SPo-Hao Huang band, chan, reason, status, tx_fail, actual_period); 433889590777SPo Hao Huang 433989590777SPo Hao Huang switch (reason) { 434089590777SPo Hao Huang case RTW89_SCAN_LEAVE_CH_NOTIFY: 434189590777SPo Hao Huang if (rtw89_is_op_chan(rtwdev, band, chan)) 434289590777SPo Hao Huang ieee80211_stop_queues(rtwdev->hw); 434389590777SPo Hao Huang return; 434489590777SPo Hao Huang case RTW89_SCAN_END_SCAN_NOTIFY: 4345bd1056d4SPo-Hao Huang if (rtwvif && rtwvif->scan_req && 4346bd1056d4SPo-Hao Huang last_chan < rtwvif->scan_req->n_channels) { 4347bd1056d4SPo-Hao Huang ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4348bd1056d4SPo-Hao Huang if (ret) { 4349bd1056d4SPo-Hao Huang rtw89_hw_scan_abort(rtwdev, vif); 4350bd1056d4SPo-Hao Huang rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4351bd1056d4SPo-Hao Huang } 4352bd1056d4SPo-Hao Huang } else { 435389590777SPo Hao Huang rtw89_hw_scan_complete(rtwdev, vif, false); 4354bd1056d4SPo-Hao Huang } 435589590777SPo Hao Huang break; 435689590777SPo Hao Huang case RTW89_SCAN_ENTER_CH_NOTIFY: 435728000f7bSPo Hao Huang if (rtw89_is_op_chan(rtwdev, band, chan)) { 4358e7399db2SPo-Hao Huang rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4359e7399db2SPo-Hao Huang &rtwdev->scan_info.op_chan); 436089590777SPo Hao Huang ieee80211_wake_queues(rtwdev->hw); 4361e7399db2SPo-Hao Huang } else { 4362e7399db2SPo-Hao Huang rtw89_chan_create(&new, chan, chan, band, 4363e7399db2SPo-Hao Huang RTW89_CHANNEL_WIDTH_20); 4364e7399db2SPo-Hao Huang rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4365e7399db2SPo-Hao Huang &new); 436628000f7bSPo Hao Huang } 436789590777SPo Hao Huang break; 436889590777SPo Hao Huang default: 436989590777SPo Hao Huang return; 437089590777SPo Hao Huang } 437189590777SPo Hao Huang } 437289590777SPo Hao Huang 4373e3ec7017SPing-Ke Shih static void 4374d2b6da24SPo-Hao Huang rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4375d2b6da24SPo-Hao Huang struct sk_buff *skb) 4376d2b6da24SPo-Hao Huang { 4377d2b6da24SPo-Hao Huang struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4378d2b6da24SPo-Hao Huang enum nl80211_cqm_rssi_threshold_event nl_event; 4379d2b6da24SPo-Hao Huang const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4380d2b6da24SPo-Hao Huang (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4381d2b6da24SPo-Hao Huang u8 type, event, mac_id; 4382d2b6da24SPo-Hao Huang s8 sig; 4383d2b6da24SPo-Hao Huang 4384d2b6da24SPo-Hao Huang type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4385d2b6da24SPo-Hao Huang sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4386d2b6da24SPo-Hao Huang event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4387d2b6da24SPo-Hao Huang mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4388d2b6da24SPo-Hao Huang 4389d2b6da24SPo-Hao Huang if (mac_id != rtwvif->mac_id) 4390d2b6da24SPo-Hao Huang return; 4391d2b6da24SPo-Hao Huang 4392d2b6da24SPo-Hao Huang rtw89_debug(rtwdev, RTW89_DBG_FW, 4393d2b6da24SPo-Hao Huang "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4394d2b6da24SPo-Hao Huang mac_id, type, sig, event); 4395d2b6da24SPo-Hao Huang 4396d2b6da24SPo-Hao Huang switch (type) { 4397d2b6da24SPo-Hao Huang case RTW89_BCN_FLTR_BEACON_LOSS: 4398a0e97ae3SPo-Hao Huang if (!rtwdev->scanning && !rtwvif->offchan) 4399d2b6da24SPo-Hao Huang ieee80211_connection_loss(vif); 4400d2b6da24SPo-Hao Huang else 4401d2b6da24SPo-Hao Huang rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4402d2b6da24SPo-Hao Huang return; 4403d2b6da24SPo-Hao Huang case RTW89_BCN_FLTR_NOTIFY: 4404d2b6da24SPo-Hao Huang nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4405d2b6da24SPo-Hao Huang break; 4406d2b6da24SPo-Hao Huang case RTW89_BCN_FLTR_RSSI: 4407d2b6da24SPo-Hao Huang if (event == RTW89_BCN_FLTR_RSSI_LOW) 4408d2b6da24SPo-Hao Huang nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4409d2b6da24SPo-Hao Huang else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4410d2b6da24SPo-Hao Huang nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4411d2b6da24SPo-Hao Huang else 4412d2b6da24SPo-Hao Huang return; 4413d2b6da24SPo-Hao Huang break; 4414d2b6da24SPo-Hao Huang default: 4415d2b6da24SPo-Hao Huang return; 4416d2b6da24SPo-Hao Huang } 4417d2b6da24SPo-Hao Huang 4418d2b6da24SPo-Hao Huang ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4419d2b6da24SPo-Hao Huang } 4420d2b6da24SPo-Hao Huang 4421d2b6da24SPo-Hao Huang static void 4422d2b6da24SPo-Hao Huang rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4423d2b6da24SPo-Hao Huang u32 len) 4424d2b6da24SPo-Hao Huang { 4425d2b6da24SPo-Hao Huang struct rtw89_vif *rtwvif; 4426d2b6da24SPo-Hao Huang 4427d2b6da24SPo-Hao Huang rtw89_for_each_rtwvif(rtwdev, rtwvif) 4428d2b6da24SPo-Hao Huang rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4429d2b6da24SPo-Hao Huang } 4430d2b6da24SPo-Hao Huang 4431d2b6da24SPo-Hao Huang static void 4432e3ec7017SPing-Ke Shih rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4433e3ec7017SPing-Ke Shih { 443432bb12ebSZong-Zhe Yang /* N.B. This will run in interrupt context. */ 443532bb12ebSZong-Zhe Yang 4436e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 4437e3ec7017SPing-Ke Shih "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4438e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4439e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4440e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4441e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4442e3ec7017SPing-Ke Shih } 4443e3ec7017SPing-Ke Shih 4444e3ec7017SPing-Ke Shih static void 4445b9b632f4SZong-Zhe Yang rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4446e3ec7017SPing-Ke Shih { 444732bb12ebSZong-Zhe Yang /* N.B. This will run in interrupt context. */ 4448b9b632f4SZong-Zhe Yang struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4449b9b632f4SZong-Zhe Yang const struct rtw89_c2h_done_ack *c2h = 4450b9b632f4SZong-Zhe Yang (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4451b9b632f4SZong-Zhe Yang u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4452b9b632f4SZong-Zhe Yang u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4453b9b632f4SZong-Zhe Yang u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4454b9b632f4SZong-Zhe Yang u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4455b9b632f4SZong-Zhe Yang u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4456b9b632f4SZong-Zhe Yang struct rtw89_completion_data data = {}; 4457b9b632f4SZong-Zhe Yang unsigned int cond; 445832bb12ebSZong-Zhe Yang 4459e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 4460e3ec7017SPing-Ke Shih "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4461b9b632f4SZong-Zhe Yang h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4462b9b632f4SZong-Zhe Yang 4463b9b632f4SZong-Zhe Yang if (h2c_cat != H2C_CAT_MAC) 4464b9b632f4SZong-Zhe Yang return; 4465b9b632f4SZong-Zhe Yang 4466b9b632f4SZong-Zhe Yang switch (h2c_class) { 4467b9b632f4SZong-Zhe Yang default: 4468b9b632f4SZong-Zhe Yang return; 4469b9b632f4SZong-Zhe Yang case H2C_CL_MAC_FW_OFLD: 4470b9b632f4SZong-Zhe Yang switch (h2c_func) { 4471b9b632f4SZong-Zhe Yang default: 4472b9b632f4SZong-Zhe Yang return; 4473b9b632f4SZong-Zhe Yang case H2C_FUNC_ADD_SCANOFLD_CH: 4474b9b632f4SZong-Zhe Yang case H2C_FUNC_SCANOFLD: 4475b9b632f4SZong-Zhe Yang cond = RTW89_FW_OFLD_WAIT_COND(0, h2c_func); 4476b9b632f4SZong-Zhe Yang break; 4477b9b632f4SZong-Zhe Yang } 4478b9b632f4SZong-Zhe Yang 4479b9b632f4SZong-Zhe Yang data.err = !!h2c_return; 4480b9b632f4SZong-Zhe Yang rtw89_complete_cond(fw_ofld_wait, cond, &data); 4481b9b632f4SZong-Zhe Yang return; 4482b9b632f4SZong-Zhe Yang } 4483e3ec7017SPing-Ke Shih } 4484e3ec7017SPing-Ke Shih 4485e3ec7017SPing-Ke Shih static void 4486e3ec7017SPing-Ke Shih rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4487e3ec7017SPing-Ke Shih { 4488cad2bd8aSChin-Yen Lee rtw89_fw_log_dump(rtwdev, c2h->data, len); 4489e3ec7017SPing-Ke Shih } 4490e3ec7017SPing-Ke Shih 4491fccca934SPing-Ke Shih static void 4492fccca934SPing-Ke Shih rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4493fccca934SPing-Ke Shih { 4494fccca934SPing-Ke Shih } 4495fccca934SPing-Ke Shih 44962b8219e9SPo Hao Huang static void 44978febd68bSZong-Zhe Yang rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 44982b8219e9SPo Hao Huang u32 len) 44992b8219e9SPo Hao Huang { 45008febd68bSZong-Zhe Yang struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 45018febd68bSZong-Zhe Yang const struct rtw89_c2h_pkt_ofld_rsp *c2h = 45028febd68bSZong-Zhe Yang (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 45038febd68bSZong-Zhe Yang u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 45048febd68bSZong-Zhe Yang u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 45058febd68bSZong-Zhe Yang u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 45068febd68bSZong-Zhe Yang struct rtw89_completion_data data = {}; 45078febd68bSZong-Zhe Yang unsigned int cond; 45088febd68bSZong-Zhe Yang 45098b21c08eSZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 45108b21c08eSZong-Zhe Yang pkt_id, pkt_op, pkt_len); 45118b21c08eSZong-Zhe Yang 45128febd68bSZong-Zhe Yang data.err = !pkt_len; 45138febd68bSZong-Zhe Yang cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 45148febd68bSZong-Zhe Yang 45158febd68bSZong-Zhe Yang rtw89_complete_cond(wait, cond, &data); 45162b8219e9SPo Hao Huang } 45172b8219e9SPo Hao Huang 4518f4a43c3bSDian-Syuan Yang static void 4519f4a43c3bSDian-Syuan Yang rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4520f4a43c3bSDian-Syuan Yang u32 len) 4521f4a43c3bSDian-Syuan Yang { 452297211e02SZong-Zhe Yang rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 4523f4a43c3bSDian-Syuan Yang } 4524f4a43c3bSDian-Syuan Yang 4525ef9dff4cSZong-Zhe Yang static void 4526ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4527ef9dff4cSZong-Zhe Yang { 4528ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4529ef9dff4cSZong-Zhe Yang u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4530ef9dff4cSZong-Zhe Yang 4531ef9dff4cSZong-Zhe Yang switch (func) { 4532ef9dff4cSZong-Zhe Yang case H2C_FUNC_ADD_MCC: 4533ef9dff4cSZong-Zhe Yang case H2C_FUNC_START_MCC: 4534ef9dff4cSZong-Zhe Yang case H2C_FUNC_STOP_MCC: 4535ef9dff4cSZong-Zhe Yang case H2C_FUNC_DEL_MCC_GROUP: 4536ef9dff4cSZong-Zhe Yang case H2C_FUNC_RESET_MCC_GROUP: 4537ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_REQ_TSF: 4538ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_MACID_BITMAP: 4539ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SYNC: 4540ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SET_DURATION: 4541ef9dff4cSZong-Zhe Yang break; 4542ef9dff4cSZong-Zhe Yang default: 4543214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4544ef9dff4cSZong-Zhe Yang "invalid MCC C2H RCV ACK: func %d\n", func); 4545ef9dff4cSZong-Zhe Yang return; 4546ef9dff4cSZong-Zhe Yang } 4547ef9dff4cSZong-Zhe Yang 4548214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4549ef9dff4cSZong-Zhe Yang "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4550ef9dff4cSZong-Zhe Yang } 4551ef9dff4cSZong-Zhe Yang 4552ef9dff4cSZong-Zhe Yang static void 4553ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4554ef9dff4cSZong-Zhe Yang { 4555ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4556ef9dff4cSZong-Zhe Yang u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4557ef9dff4cSZong-Zhe Yang u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4558ef9dff4cSZong-Zhe Yang struct rtw89_completion_data data = {}; 4559ef9dff4cSZong-Zhe Yang unsigned int cond; 4560ef9dff4cSZong-Zhe Yang bool next = false; 4561ef9dff4cSZong-Zhe Yang 4562ef9dff4cSZong-Zhe Yang switch (func) { 4563ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_REQ_TSF: 4564ef9dff4cSZong-Zhe Yang next = true; 4565ef9dff4cSZong-Zhe Yang break; 4566ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_MACID_BITMAP: 4567ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SYNC: 4568ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SET_DURATION: 4569ef9dff4cSZong-Zhe Yang break; 4570ef9dff4cSZong-Zhe Yang case H2C_FUNC_ADD_MCC: 4571ef9dff4cSZong-Zhe Yang case H2C_FUNC_START_MCC: 4572ef9dff4cSZong-Zhe Yang case H2C_FUNC_STOP_MCC: 4573ef9dff4cSZong-Zhe Yang case H2C_FUNC_DEL_MCC_GROUP: 4574ef9dff4cSZong-Zhe Yang case H2C_FUNC_RESET_MCC_GROUP: 4575ef9dff4cSZong-Zhe Yang default: 4576214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4577ef9dff4cSZong-Zhe Yang "invalid MCC C2H REQ ACK: func %d\n", func); 4578ef9dff4cSZong-Zhe Yang return; 4579ef9dff4cSZong-Zhe Yang } 4580ef9dff4cSZong-Zhe Yang 4581214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4582ef9dff4cSZong-Zhe Yang "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 4583ef9dff4cSZong-Zhe Yang group, func, retcode); 4584ef9dff4cSZong-Zhe Yang 4585ef9dff4cSZong-Zhe Yang if (!retcode && next) 4586ef9dff4cSZong-Zhe Yang return; 4587ef9dff4cSZong-Zhe Yang 4588ef9dff4cSZong-Zhe Yang data.err = !!retcode; 4589ef9dff4cSZong-Zhe Yang cond = RTW89_MCC_WAIT_COND(group, func); 4590ef9dff4cSZong-Zhe Yang rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4591ef9dff4cSZong-Zhe Yang } 4592ef9dff4cSZong-Zhe Yang 4593ef9dff4cSZong-Zhe Yang static void 4594ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4595ef9dff4cSZong-Zhe Yang { 4596ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 4597ef9dff4cSZong-Zhe Yang struct rtw89_completion_data data = {}; 4598ef9dff4cSZong-Zhe Yang struct rtw89_mac_mcc_tsf_rpt *rpt; 4599ef9dff4cSZong-Zhe Yang unsigned int cond; 4600ef9dff4cSZong-Zhe Yang 4601ef9dff4cSZong-Zhe Yang rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 4602ef9dff4cSZong-Zhe Yang rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 4603ef9dff4cSZong-Zhe Yang rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 4604ef9dff4cSZong-Zhe Yang rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 4605ef9dff4cSZong-Zhe Yang rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 4606ef9dff4cSZong-Zhe Yang rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 4607ef9dff4cSZong-Zhe Yang rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 4608ef9dff4cSZong-Zhe Yang 4609214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4610214a98b1SZong-Zhe Yang "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 4611214a98b1SZong-Zhe Yang rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 4612214a98b1SZong-Zhe Yang rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 4613214a98b1SZong-Zhe Yang 4614ef9dff4cSZong-Zhe Yang cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 4615ef9dff4cSZong-Zhe Yang rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4616ef9dff4cSZong-Zhe Yang } 4617ef9dff4cSZong-Zhe Yang 4618ef9dff4cSZong-Zhe Yang static void 4619ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4620ef9dff4cSZong-Zhe Yang { 4621ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 4622ef9dff4cSZong-Zhe Yang u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 4623ef9dff4cSZong-Zhe Yang u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 4624ef9dff4cSZong-Zhe Yang u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 4625ef9dff4cSZong-Zhe Yang u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 4626ef9dff4cSZong-Zhe Yang struct rtw89_completion_data data = {}; 4627ef9dff4cSZong-Zhe Yang unsigned int cond; 4628ef9dff4cSZong-Zhe Yang bool rsp = true; 4629ef9dff4cSZong-Zhe Yang bool err; 4630ef9dff4cSZong-Zhe Yang u8 func; 4631ef9dff4cSZong-Zhe Yang 4632ef9dff4cSZong-Zhe Yang switch (status) { 4633ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_ADD_ROLE_OK: 4634ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_ADD_ROLE_FAIL: 4635ef9dff4cSZong-Zhe Yang func = H2C_FUNC_ADD_MCC; 4636ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 4637ef9dff4cSZong-Zhe Yang break; 4638ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_START_GROUP_OK: 4639ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_START_GROUP_FAIL: 4640ef9dff4cSZong-Zhe Yang func = H2C_FUNC_START_MCC; 4641ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 4642ef9dff4cSZong-Zhe Yang break; 4643ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_STOP_GROUP_OK: 4644ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_STOP_GROUP_FAIL: 4645ef9dff4cSZong-Zhe Yang func = H2C_FUNC_STOP_MCC; 4646ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 4647ef9dff4cSZong-Zhe Yang break; 4648ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DEL_GROUP_OK: 4649ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DEL_GROUP_FAIL: 4650ef9dff4cSZong-Zhe Yang func = H2C_FUNC_DEL_MCC_GROUP; 4651ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 4652ef9dff4cSZong-Zhe Yang break; 4653ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_RESET_GROUP_OK: 4654ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_RESET_GROUP_FAIL: 4655ef9dff4cSZong-Zhe Yang func = H2C_FUNC_RESET_MCC_GROUP; 4656ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 4657ef9dff4cSZong-Zhe Yang break; 4658ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_SWITCH_CH_OK: 4659ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_SWITCH_CH_FAIL: 4660ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL0_OK: 4661ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL0_FAIL: 4662ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL1_OK: 4663ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL1_FAIL: 4664ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_SWITCH_EARLY: 4665ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TBTT: 4666ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DURATION_START: 4667ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DURATION_END: 4668ef9dff4cSZong-Zhe Yang rsp = false; 4669ef9dff4cSZong-Zhe Yang break; 4670ef9dff4cSZong-Zhe Yang default: 4671214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4672ef9dff4cSZong-Zhe Yang "invalid MCC C2H STS RPT: status %d\n", status); 4673ef9dff4cSZong-Zhe Yang return; 4674ef9dff4cSZong-Zhe Yang } 4675ef9dff4cSZong-Zhe Yang 4676214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4677214a98b1SZong-Zhe Yang "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 4678214a98b1SZong-Zhe Yang group, macid, status, (u64)tsf_high << 32 | tsf_low); 4679ef9dff4cSZong-Zhe Yang 4680ef9dff4cSZong-Zhe Yang if (!rsp) 4681ef9dff4cSZong-Zhe Yang return; 4682ef9dff4cSZong-Zhe Yang 4683ef9dff4cSZong-Zhe Yang data.err = err; 4684ef9dff4cSZong-Zhe Yang cond = RTW89_MCC_WAIT_COND(group, func); 4685ef9dff4cSZong-Zhe Yang rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4686ef9dff4cSZong-Zhe Yang } 4687ef9dff4cSZong-Zhe Yang 4688e3ec7017SPing-Ke Shih static 4689e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 4690e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 4691e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 4692e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 46932b8219e9SPo Hao Huang [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 4694e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 4695e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 469689590777SPo Hao Huang [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 4697f4a43c3bSDian-Syuan Yang [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 4698d2b6da24SPo-Hao Huang [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 4699e3ec7017SPing-Ke Shih }; 4700e3ec7017SPing-Ke Shih 4701e3ec7017SPing-Ke Shih static 4702e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 4703e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 4704e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 4705e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 4706e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 4707fccca934SPing-Ke Shih [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 4708e3ec7017SPing-Ke Shih }; 4709e3ec7017SPing-Ke Shih 4710ef9dff4cSZong-Zhe Yang static 4711ef9dff4cSZong-Zhe Yang void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 4712ef9dff4cSZong-Zhe Yang struct sk_buff *c2h, u32 len) = { 4713ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 4714ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 4715ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 4716ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 4717ef9dff4cSZong-Zhe Yang }; 4718ef9dff4cSZong-Zhe Yang 4719860e8263SZong-Zhe Yang bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 4720860e8263SZong-Zhe Yang { 4721860e8263SZong-Zhe Yang switch (class) { 4722860e8263SZong-Zhe Yang default: 4723860e8263SZong-Zhe Yang return false; 472432bb12ebSZong-Zhe Yang case RTW89_MAC_C2H_CLASS_INFO: 472532bb12ebSZong-Zhe Yang switch (func) { 472632bb12ebSZong-Zhe Yang default: 472732bb12ebSZong-Zhe Yang return false; 472832bb12ebSZong-Zhe Yang case RTW89_MAC_C2H_FUNC_REC_ACK: 472932bb12ebSZong-Zhe Yang case RTW89_MAC_C2H_FUNC_DONE_ACK: 473032bb12ebSZong-Zhe Yang return true; 473132bb12ebSZong-Zhe Yang } 47328febd68bSZong-Zhe Yang case RTW89_MAC_C2H_CLASS_OFLD: 47338febd68bSZong-Zhe Yang switch (func) { 47348febd68bSZong-Zhe Yang default: 47358febd68bSZong-Zhe Yang return false; 47368febd68bSZong-Zhe Yang case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 47378febd68bSZong-Zhe Yang return true; 47388febd68bSZong-Zhe Yang } 4739860e8263SZong-Zhe Yang case RTW89_MAC_C2H_CLASS_MCC: 4740860e8263SZong-Zhe Yang return true; 4741860e8263SZong-Zhe Yang } 4742860e8263SZong-Zhe Yang } 4743860e8263SZong-Zhe Yang 4744e3ec7017SPing-Ke Shih void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4745e3ec7017SPing-Ke Shih u32 len, u8 class, u8 func) 4746e3ec7017SPing-Ke Shih { 4747e3ec7017SPing-Ke Shih void (*handler)(struct rtw89_dev *rtwdev, 4748e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = NULL; 4749e3ec7017SPing-Ke Shih 4750e3ec7017SPing-Ke Shih switch (class) { 4751e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_INFO: 4752e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 4753e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_info_handler[func]; 4754e3ec7017SPing-Ke Shih break; 4755e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_OFLD: 4756e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 4757e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_ofld_handler[func]; 4758e3ec7017SPing-Ke Shih break; 4759ef9dff4cSZong-Zhe Yang case RTW89_MAC_C2H_CLASS_MCC: 4760ef9dff4cSZong-Zhe Yang if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 4761ef9dff4cSZong-Zhe Yang handler = rtw89_mac_c2h_mcc_handler[func]; 4762ef9dff4cSZong-Zhe Yang break; 4763e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_FWDBG: 4764e3ec7017SPing-Ke Shih return; 4765e3ec7017SPing-Ke Shih default: 4766e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d not support\n", class); 4767e3ec7017SPing-Ke Shih return; 4768e3ec7017SPing-Ke Shih } 4769e3ec7017SPing-Ke Shih if (!handler) { 4770e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 4771e3ec7017SPing-Ke Shih func); 4772e3ec7017SPing-Ke Shih return; 4773e3ec7017SPing-Ke Shih } 4774e3ec7017SPing-Ke Shih handler(rtwdev, skb, len); 4775e3ec7017SPing-Ke Shih } 4776e3ec7017SPing-Ke Shih 477706b26738SZong-Zhe Yang static 477806b26738SZong-Zhe Yang bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 4779e3ec7017SPing-Ke Shih enum rtw89_phy_idx phy_idx, 4780e3ec7017SPing-Ke Shih u32 reg_base, u32 *cr) 4781e3ec7017SPing-Ke Shih { 4782e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 4783e3ec7017SPing-Ke Shih enum rtw89_qta_mode mode = dle_mem->mode; 4784c220d08eSPing-Ke Shih u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 4785e3ec7017SPing-Ke Shih 478606b26738SZong-Zhe Yang if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 4787e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 4788e3ec7017SPing-Ke Shih addr); 4789e3ec7017SPing-Ke Shih goto error; 4790e3ec7017SPing-Ke Shih } 4791e3ec7017SPing-Ke Shih 479206b26738SZong-Zhe Yang if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 4793e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_SCC) { 4794e3ec7017SPing-Ke Shih rtw89_err(rtwdev, 4795e3ec7017SPing-Ke Shih "[TXPWR] addr=0x%x but hw not enable\n", 4796e3ec7017SPing-Ke Shih addr); 4797e3ec7017SPing-Ke Shih goto error; 4798e3ec7017SPing-Ke Shih } 4799e3ec7017SPing-Ke Shih 4800e3ec7017SPing-Ke Shih *cr = addr; 4801e3ec7017SPing-Ke Shih return true; 4802e3ec7017SPing-Ke Shih 4803e3ec7017SPing-Ke Shih error: 4804e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 4805e3ec7017SPing-Ke Shih addr, phy_idx); 4806e3ec7017SPing-Ke Shih 4807e3ec7017SPing-Ke Shih return false; 4808e3ec7017SPing-Ke Shih } 4809e3ec7017SPing-Ke Shih 4810e3ec7017SPing-Ke Shih int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 4811e3ec7017SPing-Ke Shih { 4812c220d08eSPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 481321087188SPing-Ke Shih int ret; 4814e3ec7017SPing-Ke Shih 4815e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4816e3ec7017SPing-Ke Shih if (ret) 4817e3ec7017SPing-Ke Shih return ret; 4818e3ec7017SPing-Ke Shih 4819e3ec7017SPing-Ke Shih if (!enable) { 4820e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 482121087188SPing-Ke Shih return 0; 4822e3ec7017SPing-Ke Shih } 4823e3ec7017SPing-Ke Shih 4824e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 4825e3ec7017SPing-Ke Shih B_AX_APP_MAC_INFO_RPT | 4826e3ec7017SPing-Ke Shih B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 4827e3ec7017SPing-Ke Shih B_AX_PPDU_STAT_RPT_CRC32); 4828e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 4829e3ec7017SPing-Ke Shih RTW89_PRPT_DEST_HOST); 4830e3ec7017SPing-Ke Shih 483121087188SPing-Ke Shih return 0; 4832e3ec7017SPing-Ke Shih } 4833861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 4834e3ec7017SPing-Ke Shih 4835e3ec7017SPing-Ke Shih void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 4836e3ec7017SPing-Ke Shih { 4837e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_SH 5 4838e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_SH 4 4839e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_MAX 255 4840e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_MAX 255 4841e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_DEF 88 4842e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_DEF 4080 4843fbd1829dSZong-Zhe Yang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4844e3ec7017SPing-Ke Shih struct ieee80211_hw *hw = rtwdev->hw; 4845e3ec7017SPing-Ke Shih u32 rts_threshold = hw->wiphy->rts_threshold; 4846e3ec7017SPing-Ke Shih u32 time_th, len_th; 4847e3ec7017SPing-Ke Shih u32 reg; 4848e3ec7017SPing-Ke Shih 4849e3ec7017SPing-Ke Shih if (rts_threshold == (u32)-1) { 4850e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_DEF; 4851e3ec7017SPing-Ke Shih len_th = MAC_AX_LEN_TH_DEF; 4852e3ec7017SPing-Ke Shih } else { 4853e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 4854e3ec7017SPing-Ke Shih len_th = rts_threshold; 4855e3ec7017SPing-Ke Shih } 4856e3ec7017SPing-Ke Shih 4857e3ec7017SPing-Ke Shih time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 4858e3ec7017SPing-Ke Shih len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 4859e3ec7017SPing-Ke Shih 4860fbd1829dSZong-Zhe Yang reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 4861e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 4862e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 4863e3ec7017SPing-Ke Shih } 4864e3ec7017SPing-Ke Shih 4865e3ec7017SPing-Ke Shih void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 4866e3ec7017SPing-Ke Shih { 4867e3ec7017SPing-Ke Shih bool empty; 4868e3ec7017SPing-Ke Shih int ret; 4869e3ec7017SPing-Ke Shih 4870e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4871e3ec7017SPing-Ke Shih return; 4872e3ec7017SPing-Ke Shih 4873e3ec7017SPing-Ke Shih ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 4874e3ec7017SPing-Ke Shih 10000, 200000, false, rtwdev); 4875e3ec7017SPing-Ke Shih if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 4876e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "timed out to flush queues\n"); 4877e3ec7017SPing-Ke Shih } 4878e3ec7017SPing-Ke Shih 4879e3ec7017SPing-Ke Shih int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 4880e3ec7017SPing-Ke Shih { 4881e3ec7017SPing-Ke Shih u8 val; 4882e3ec7017SPing-Ke Shih u16 val16; 4883e3ec7017SPing-Ke Shih u32 val32; 4884e3ec7017SPing-Ke Shih int ret; 4885e3ec7017SPing-Ke Shih 4886e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 48875c3afcbaSPing-Ke Shih if (rtwdev->chip->chip_id != RTL8851B) 4888e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 4889e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 4890e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 4891e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 48925c3afcbaSPing-Ke Shih if (rtwdev->chip->chip_id != RTL8851B) 4893e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 4894e3ec7017SPing-Ke Shih 4895e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 4896e3ec7017SPing-Ke Shih val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 4897e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 4898e3ec7017SPing-Ke Shih 4899e3ec7017SPing-Ke Shih ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 4900e3ec7017SPing-Ke Shih if (ret) { 4901e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 4902e3ec7017SPing-Ke Shih return ret; 4903e3ec7017SPing-Ke Shih } 4904e3ec7017SPing-Ke Shih val32 = val32 & B_AX_WL_RX_CTRL; 4905e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 4906e3ec7017SPing-Ke Shih if (ret) { 4907e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 4908e3ec7017SPing-Ke Shih return ret; 4909e3ec7017SPing-Ke Shih } 4910e3ec7017SPing-Ke Shih 4911e3ec7017SPing-Ke Shih switch (coex->pta_mode) { 4912e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_RTK_MODE: 4913e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4914e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 4915e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 4916e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4917e3ec7017SPing-Ke Shih 4918e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 4919e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 4920e3ec7017SPing-Ke Shih 4921e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 4922e3ec7017SPing-Ke Shih val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 4923e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 4924e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 4925e3ec7017SPing-Ke Shih break; 4926e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_CSR_MODE: 4927e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4928e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 4929e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 4930e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4931e3ec7017SPing-Ke Shih 4932e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 4933e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 4934e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 4935e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 4936e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 4937e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_STAT_DELAY_MASK; 4938e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 4939e3ec7017SPing-Ke Shih val16 |= B_AX_ENHANCED_BT; 4940e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 4941e3ec7017SPing-Ke Shih 4942e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 4943e3ec7017SPing-Ke Shih break; 4944e3ec7017SPing-Ke Shih default: 4945e3ec7017SPing-Ke Shih return -EINVAL; 4946e3ec7017SPing-Ke Shih } 4947e3ec7017SPing-Ke Shih 4948e3ec7017SPing-Ke Shih switch (coex->direction) { 4949e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INNER: 4950e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4951e3ec7017SPing-Ke Shih val = (val & ~BIT(2)) | BIT(1); 4952e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4953e3ec7017SPing-Ke Shih break; 4954e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_OUTPUT: 4955e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4956e3ec7017SPing-Ke Shih val = val | BIT(1) | BIT(0); 4957e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4958e3ec7017SPing-Ke Shih break; 4959e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INPUT: 4960e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4961e3ec7017SPing-Ke Shih val = val & ~(BIT(2) | BIT(1)); 4962e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4963e3ec7017SPing-Ke Shih break; 4964e3ec7017SPing-Ke Shih default: 4965e3ec7017SPing-Ke Shih return -EINVAL; 4966e3ec7017SPing-Ke Shih } 4967e3ec7017SPing-Ke Shih 4968e3ec7017SPing-Ke Shih return 0; 4969e3ec7017SPing-Ke Shih } 4970861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_coex_init); 4971e3ec7017SPing-Ke Shih 4972065cf8f9SChia-Yuan Li int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 4973065cf8f9SChia-Yuan Li const struct rtw89_mac_ax_coex *coex) 4974065cf8f9SChia-Yuan Li { 4975065cf8f9SChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 4976065cf8f9SChia-Yuan Li B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 4977065cf8f9SChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 4978065cf8f9SChia-Yuan Li rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 4979065cf8f9SChia-Yuan Li rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 4980065cf8f9SChia-Yuan Li 4981065cf8f9SChia-Yuan Li switch (coex->pta_mode) { 4982065cf8f9SChia-Yuan Li case RTW89_MAC_AX_COEX_RTK_MODE: 4983065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4984065cf8f9SChia-Yuan Li MAC_AX_RTK_MODE); 4985065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 4986065cf8f9SChia-Yuan Li B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 4987065cf8f9SChia-Yuan Li break; 4988065cf8f9SChia-Yuan Li case RTW89_MAC_AX_COEX_CSR_MODE: 4989065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4990065cf8f9SChia-Yuan Li MAC_AX_CSR_MODE); 4991065cf8f9SChia-Yuan Li break; 4992065cf8f9SChia-Yuan Li default: 4993065cf8f9SChia-Yuan Li return -EINVAL; 4994065cf8f9SChia-Yuan Li } 4995065cf8f9SChia-Yuan Li 4996065cf8f9SChia-Yuan Li return 0; 4997065cf8f9SChia-Yuan Li } 4998065cf8f9SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 4999065cf8f9SChia-Yuan Li 5000e3ec7017SPing-Ke Shih int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5001e3ec7017SPing-Ke Shih const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5002e3ec7017SPing-Ke Shih { 50038001c741SPing-Ke Shih u32 val = 0, ret; 5004e3ec7017SPing-Ke Shih 50058001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_bt) 50068001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 50078001c741SPing-Ke Shih 50088001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_bt_sw_en) 50098001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 50108001c741SPing-Ke Shih 50118001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_wl) 50128001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 50138001c741SPing-Ke Shih 50148001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_wl_sw_en) 50158001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 50168001c741SPing-Ke Shih 50178001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_bt) 50188001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 50198001c741SPing-Ke Shih 50208001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_bt_sw_en) 50218001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 50228001c741SPing-Ke Shih 50238001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_wl) 50248001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 50258001c741SPing-Ke Shih 50268001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_wl_sw_en) 50278001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 50288001c741SPing-Ke Shih 5029e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 5030e3ec7017SPing-Ke Shih if (ret) { 5031e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write LTE fail!\n"); 5032e3ec7017SPing-Ke Shih return ret; 5033e3ec7017SPing-Ke Shih } 5034e3ec7017SPing-Ke Shih 5035e3ec7017SPing-Ke Shih return 0; 5036e3ec7017SPing-Ke Shih } 5037feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 5038feed6541SChia-Yuan Li 5039feed6541SChia-Yuan Li int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 5040feed6541SChia-Yuan Li const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5041feed6541SChia-Yuan Li { 5042feed6541SChia-Yuan Li u32 val = 0; 5043feed6541SChia-Yuan Li 5044feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_bt) 5045feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5046feed6541SChia-Yuan Li B_AX_GNT_BT_TX_VAL; 5047feed6541SChia-Yuan Li else 5048feed6541SChia-Yuan Li val |= B_AX_WL_ACT_VAL; 5049feed6541SChia-Yuan Li 5050feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_bt_sw_en) 5051feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5052feed6541SChia-Yuan Li B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5053feed6541SChia-Yuan Li 5054feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_wl) 5055feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5056feed6541SChia-Yuan Li B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5057feed6541SChia-Yuan Li 5058feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_wl_sw_en) 5059feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5060feed6541SChia-Yuan Li B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5061feed6541SChia-Yuan Li 5062feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_bt) 5063feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5064feed6541SChia-Yuan Li B_AX_GNT_BT_TX_VAL; 5065feed6541SChia-Yuan Li else 5066feed6541SChia-Yuan Li val |= B_AX_WL_ACT_VAL; 5067feed6541SChia-Yuan Li 5068feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_bt_sw_en) 5069feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5070feed6541SChia-Yuan Li B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5071feed6541SChia-Yuan Li 5072feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_wl) 5073feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5074feed6541SChia-Yuan Li B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5075feed6541SChia-Yuan Li 5076feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_wl_sw_en) 5077feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5078feed6541SChia-Yuan Li B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5079feed6541SChia-Yuan Li 5080feed6541SChia-Yuan Li rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5081feed6541SChia-Yuan Li 5082feed6541SChia-Yuan Li return 0; 5083feed6541SChia-Yuan Li } 5084feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5085e3ec7017SPing-Ke Shih 5086e3ec7017SPing-Ke Shih int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5087e3ec7017SPing-Ke Shih { 5088e3ec7017SPing-Ke Shih u32 reg; 508928e7ea8aSPing-Ke Shih u16 val; 5090e3ec7017SPing-Ke Shih int ret; 5091e3ec7017SPing-Ke Shih 5092e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5093e3ec7017SPing-Ke Shih if (ret) 5094e3ec7017SPing-Ke Shih return ret; 5095e3ec7017SPing-Ke Shih 5096c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 5097e3ec7017SPing-Ke Shih val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5098e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5099e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5100e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5101e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5102e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5103e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 510428e7ea8aSPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 510528e7ea8aSPing-Ke Shih B_AX_PLT_EN; 510628e7ea8aSPing-Ke Shih rtw89_write16(rtwdev, reg, val); 5107e3ec7017SPing-Ke Shih 5108e3ec7017SPing-Ke Shih return 0; 5109e3ec7017SPing-Ke Shih } 5110e3ec7017SPing-Ke Shih 5111e3ec7017SPing-Ke Shih void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5112e3ec7017SPing-Ke Shih { 5113e3ec7017SPing-Ke Shih u32 fw_sb; 5114e3ec7017SPing-Ke Shih 5115e3ec7017SPing-Ke Shih fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5116e3ec7017SPing-Ke Shih fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5117e3ec7017SPing-Ke Shih fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5118e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5119e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5120e3ec7017SPing-Ke Shih else 5121e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5122e3ec7017SPing-Ke Shih val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5123e3ec7017SPing-Ke Shih val = B_AX_TOGGLE | 5124e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5125e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5126e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5127e3ec7017SPing-Ke Shih fsleep(1000); /* avoid BT FW loss information */ 5128e3ec7017SPing-Ke Shih } 5129e3ec7017SPing-Ke Shih 5130e3ec7017SPing-Ke Shih u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5131e3ec7017SPing-Ke Shih { 5132e3ec7017SPing-Ke Shih return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5133e3ec7017SPing-Ke Shih } 5134e3ec7017SPing-Ke Shih 5135e3ec7017SPing-Ke Shih int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5136e3ec7017SPing-Ke Shih { 5137e3ec7017SPing-Ke Shih u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5138e3ec7017SPing-Ke Shih 5139e3ec7017SPing-Ke Shih val = wl ? val | BIT(2) : val & ~BIT(2); 5140e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5141e3ec7017SPing-Ke Shih 5142e3ec7017SPing-Ke Shih return 0; 5143e3ec7017SPing-Ke Shih } 5144feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5145feed6541SChia-Yuan Li 5146feed6541SChia-Yuan Li int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5147feed6541SChia-Yuan Li { 5148feed6541SChia-Yuan Li struct rtw89_btc *btc = &rtwdev->btc; 5149feed6541SChia-Yuan Li struct rtw89_btc_dm *dm = &btc->dm; 5150feed6541SChia-Yuan Li struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5151feed6541SChia-Yuan Li int i; 5152feed6541SChia-Yuan Li 5153feed6541SChia-Yuan Li if (wl) 5154feed6541SChia-Yuan Li return 0; 5155feed6541SChia-Yuan Li 5156feed6541SChia-Yuan Li for (i = 0; i < RTW89_PHY_MAX; i++) { 5157feed6541SChia-Yuan Li g[i].gnt_bt_sw_en = 1; 5158feed6541SChia-Yuan Li g[i].gnt_bt = 1; 5159feed6541SChia-Yuan Li g[i].gnt_wl_sw_en = 1; 5160feed6541SChia-Yuan Li g[i].gnt_wl = 0; 5161feed6541SChia-Yuan Li } 5162feed6541SChia-Yuan Li 5163feed6541SChia-Yuan Li return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5164feed6541SChia-Yuan Li } 5165feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5166e3ec7017SPing-Ke Shih 5167e3ec7017SPing-Ke Shih bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5168e3ec7017SPing-Ke Shih { 5169ae4e1adbSChing-Te Ku const struct rtw89_chip_info *chip = rtwdev->chip; 5170ae4e1adbSChing-Te Ku u8 val = 0; 5171e3ec7017SPing-Ke Shih 5172ae4e1adbSChing-Te Ku if (chip->chip_id == RTL8852C) 5173ae4e1adbSChing-Te Ku return false; 5174ae4e1adbSChing-Te Ku else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 5175ae4e1adbSChing-Te Ku val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5176ae4e1adbSChing-Te Ku B_AX_LTE_MUX_CTRL_PATH >> 24); 5177ae4e1adbSChing-Te Ku 5178ae4e1adbSChing-Te Ku return !!val; 5179e3ec7017SPing-Ke Shih } 5180e3ec7017SPing-Ke Shih 51818c7e9cebSChing-Te Ku u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 51828c7e9cebSChing-Te Ku { 51838c7e9cebSChing-Te Ku u32 reg; 51848c7e9cebSChing-Te Ku u16 cnt; 51858c7e9cebSChing-Te Ku 5186c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 51878c7e9cebSChing-Te Ku cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 51888c7e9cebSChing-Te Ku rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 51898c7e9cebSChing-Te Ku 51908c7e9cebSChing-Te Ku return cnt; 51918c7e9cebSChing-Te Ku } 51928c7e9cebSChing-Te Ku 51938a66293eSPing-Ke Shih static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 51948a66293eSPing-Ke Shih bool keep) 51958a66293eSPing-Ke Shih { 51968a66293eSPing-Ke Shih u32 reg; 51978a66293eSPing-Ke Shih 51988a66293eSPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5199c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 52008a66293eSPing-Ke Shih if (keep) { 52018a66293eSPing-Ke Shih set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 52028a66293eSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 52038a66293eSPing-Ke Shih BFRP_RX_STANDBY_TIMER_KEEP); 52048a66293eSPing-Ke Shih } else { 52058a66293eSPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 52068a66293eSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 52078a66293eSPing-Ke Shih BFRP_RX_STANDBY_TIMER_RELEASE); 52088a66293eSPing-Ke Shih } 52098a66293eSPing-Ke Shih } 52108a66293eSPing-Ke Shih 5211e3ec7017SPing-Ke Shih static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5212e3ec7017SPing-Ke Shih { 5213*5fa1c5d4SZong-Zhe Yang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5214e3ec7017SPing-Ke Shih u32 reg; 5215*5fa1c5d4SZong-Zhe Yang u32 mask = mac->bfee_ctrl.mask; 5216e3ec7017SPing-Ke Shih 5217e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5218*5fa1c5d4SZong-Zhe Yang reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 5219e3ec7017SPing-Ke Shih if (en) { 5220e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5221e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, mask); 5222e3ec7017SPing-Ke Shih } else { 5223e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5224e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, mask); 5225e3ec7017SPing-Ke Shih } 5226e3ec7017SPing-Ke Shih } 5227e3ec7017SPing-Ke Shih 5228e3ec7017SPing-Ke Shih static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 5229e3ec7017SPing-Ke Shih { 5230e3ec7017SPing-Ke Shih u32 reg; 5231e3ec7017SPing-Ke Shih u32 val32; 5232e3ec7017SPing-Ke Shih int ret; 5233e3ec7017SPing-Ke Shih 5234e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5235e3ec7017SPing-Ke Shih if (ret) 5236e3ec7017SPing-Ke Shih return ret; 5237e3ec7017SPing-Ke Shih 5238e3ec7017SPing-Ke Shih /* AP mode set tx gid to 63 */ 5239e3ec7017SPing-Ke Shih /* STA mode set tx gid to 0(default) */ 5240c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 5241e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5242e3ec7017SPing-Ke Shih 5243c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5244e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5245e3ec7017SPing-Ke Shih 5246c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 52478a66293eSPing-Ke Shih val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5248e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 52498a66293eSPing-Ke Shih rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5250e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5251e3ec7017SPing-Ke Shih 5252c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5253e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5254e3ec7017SPing-Ke Shih B_AX_BFMEE_USE_NSTS | 5255e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_GID_SEL | 5256e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_FORCE_RETE_EN); 5257c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5258e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, 5259e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5260e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5261e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5262e3ec7017SPing-Ke Shih 5263c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 526462440fbeSPing-Ke Shih rtw89_write32_set(rtwdev, reg, 526562440fbeSPing-Ke Shih B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 526662440fbeSPing-Ke Shih 5267e3ec7017SPing-Ke Shih return 0; 5268e3ec7017SPing-Ke Shih } 5269e3ec7017SPing-Ke Shih 5270e3ec7017SPing-Ke Shih static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 5271e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 5272e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5273e3ec7017SPing-Ke Shih { 5274e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5275e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 5276e3ec7017SPing-Ke Shih u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5277e3ec7017SPing-Ke Shih u8 port_sel = rtwvif->port; 5278e3ec7017SPing-Ke Shih u8 sound_dim = 3, t; 5279046d2e7cSSriram R u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5280e3ec7017SPing-Ke Shih u32 reg; 5281e3ec7017SPing-Ke Shih u16 val; 5282e3ec7017SPing-Ke Shih int ret; 5283e3ec7017SPing-Ke Shih 5284e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5285e3ec7017SPing-Ke Shih if (ret) 5286e3ec7017SPing-Ke Shih return ret; 5287e3ec7017SPing-Ke Shih 5288e3ec7017SPing-Ke Shih if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5289e3ec7017SPing-Ke Shih (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5290e3ec7017SPing-Ke Shih ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5291e3ec7017SPing-Ke Shih stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5292e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5293e3ec7017SPing-Ke Shih phy_cap[5]); 5294e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 5295e3ec7017SPing-Ke Shih } 5296046d2e7cSSriram R if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5297046d2e7cSSriram R (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5298046d2e7cSSriram R ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5299046d2e7cSSriram R stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5300e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5301046d2e7cSSriram R sta->deflink.vht_cap.cap); 5302e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 5303e3ec7017SPing-Ke Shih } 5304e3ec7017SPing-Ke Shih nc = min(nc, sound_dim); 5305e3ec7017SPing-Ke Shih nr = min(nr, sound_dim); 5306e3ec7017SPing-Ke Shih 5307c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5308e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5309e3ec7017SPing-Ke Shih 5310e3ec7017SPing-Ke Shih val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5311e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5312e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5313e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5314e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5315e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5316e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5317e3ec7017SPing-Ke Shih 5318e3ec7017SPing-Ke Shih if (port_sel == 0) 5319c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5320e3ec7017SPing-Ke Shih else 5321c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5322e3ec7017SPing-Ke Shih 5323e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 5324e3ec7017SPing-Ke Shih 5325e3ec7017SPing-Ke Shih return 0; 5326e3ec7017SPing-Ke Shih } 5327e3ec7017SPing-Ke Shih 5328e3ec7017SPing-Ke Shih static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 5329e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 5330e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5331e3ec7017SPing-Ke Shih { 5332e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5333e3ec7017SPing-Ke Shih u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5334e3ec7017SPing-Ke Shih u32 reg; 5335e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 5336e3ec7017SPing-Ke Shih int ret; 5337e3ec7017SPing-Ke Shih 5338e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5339e3ec7017SPing-Ke Shih if (ret) 5340e3ec7017SPing-Ke Shih return ret; 5341e3ec7017SPing-Ke Shih 5342046d2e7cSSriram R if (sta->deflink.he_cap.has_he) { 5343e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5344e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5345e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5346e3ec7017SPing-Ke Shih } 5347046d2e7cSSriram R if (sta->deflink.vht_cap.vht_supported) { 5348e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5349e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5350e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5351e3ec7017SPing-Ke Shih } 5352046d2e7cSSriram R if (sta->deflink.ht_cap.ht_supported) { 5353e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5354e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5355e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5356e3ec7017SPing-Ke Shih } 5357c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5358e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5359e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5360e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, 5361c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5362e3ec7017SPing-Ke Shih rrsc); 5363e3ec7017SPing-Ke Shih 5364e3ec7017SPing-Ke Shih return 0; 5365e3ec7017SPing-Ke Shih } 5366e3ec7017SPing-Ke Shih 5367e3ec7017SPing-Ke Shih void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5368e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5369e3ec7017SPing-Ke Shih { 5370e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5371e3ec7017SPing-Ke Shih 5372e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) { 5373e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, 5374e3ec7017SPing-Ke Shih "initialize bfee for new association\n"); 5375e3ec7017SPing-Ke Shih rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 5376e3ec7017SPing-Ke Shih rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 5377e3ec7017SPing-Ke Shih rtw89_mac_csi_rrsc(rtwdev, vif, sta); 5378e3ec7017SPing-Ke Shih } 5379e3ec7017SPing-Ke Shih } 5380e3ec7017SPing-Ke Shih 5381e3ec7017SPing-Ke Shih void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5382e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5383e3ec7017SPing-Ke Shih { 5384e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5385e3ec7017SPing-Ke Shih 5386e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 5387e3ec7017SPing-Ke Shih } 5388e3ec7017SPing-Ke Shih 5389e3ec7017SPing-Ke Shih void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5390e3ec7017SPing-Ke Shih struct ieee80211_bss_conf *conf) 5391e3ec7017SPing-Ke Shih { 5392e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5393e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 5394e3ec7017SPing-Ke Shih __le32 *p; 5395e3ec7017SPing-Ke Shih 5396e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 5397e3ec7017SPing-Ke Shih 5398e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.membership; 5399c220d08eSPing-Ke Shih rtw89_write32(rtwdev, 5400c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 5401e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 5402c220d08eSPing-Ke Shih rtw89_write32(rtwdev, 5403c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 5404e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 5405e3ec7017SPing-Ke Shih 5406e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.position; 5407c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 5408e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 5409c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 5410e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 5411c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 5412e3ec7017SPing-Ke Shih le32_to_cpu(p[2])); 5413c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 5414e3ec7017SPing-Ke Shih le32_to_cpu(p[3])); 5415e3ec7017SPing-Ke Shih } 5416e3ec7017SPing-Ke Shih 5417e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data { 5418e3ec7017SPing-Ke Shih struct rtw89_dev *rtwdev; 5419e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta; 5420e3ec7017SPing-Ke Shih int count; 5421e3ec7017SPing-Ke Shih }; 5422e3ec7017SPing-Ke Shih 5423e3ec7017SPing-Ke Shih static 5424e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 5425e3ec7017SPing-Ke Shih { 5426e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data *iter_data = 5427e3ec7017SPing-Ke Shih (struct rtw89_mac_bf_monitor_iter_data *)data; 5428e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta = iter_data->down_sta; 5429e3ec7017SPing-Ke Shih int *count = &iter_data->count; 5430e3ec7017SPing-Ke Shih 5431e3ec7017SPing-Ke Shih if (down_sta == sta) 5432e3ec7017SPing-Ke Shih return; 5433e3ec7017SPing-Ke Shih 5434e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) 5435e3ec7017SPing-Ke Shih (*count)++; 5436e3ec7017SPing-Ke Shih } 5437e3ec7017SPing-Ke Shih 5438e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 5439e3ec7017SPing-Ke Shih struct ieee80211_sta *sta, bool disconnect) 5440e3ec7017SPing-Ke Shih { 5441e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data data; 5442e3ec7017SPing-Ke Shih 5443e3ec7017SPing-Ke Shih data.rtwdev = rtwdev; 5444e3ec7017SPing-Ke Shih data.down_sta = disconnect ? sta : NULL; 5445e3ec7017SPing-Ke Shih data.count = 0; 5446e3ec7017SPing-Ke Shih ieee80211_iterate_stations_atomic(rtwdev->hw, 5447e3ec7017SPing-Ke Shih rtw89_mac_bf_monitor_calc_iter, 5448e3ec7017SPing-Ke Shih &data); 5449e3ec7017SPing-Ke Shih 5450e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 5451e3ec7017SPing-Ke Shih if (data.count) 5452e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5453e3ec7017SPing-Ke Shih else 5454e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5455e3ec7017SPing-Ke Shih } 5456e3ec7017SPing-Ke Shih 5457e3ec7017SPing-Ke Shih void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 5458e3ec7017SPing-Ke Shih { 5459e3ec7017SPing-Ke Shih struct rtw89_traffic_stats *stats = &rtwdev->stats; 5460e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif; 54611646ce8fSYe Guojin bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 5462e3ec7017SPing-Ke Shih bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 54638a66293eSPing-Ke Shih bool keep_timer = true; 54648a66293eSPing-Ke Shih bool old_keep_timer; 54658a66293eSPing-Ke Shih 54668a66293eSPing-Ke Shih old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 54678a66293eSPing-Ke Shih 54688a66293eSPing-Ke Shih if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 54698a66293eSPing-Ke Shih keep_timer = false; 54708a66293eSPing-Ke Shih 54718a66293eSPing-Ke Shih if (keep_timer != old_keep_timer) { 54728a66293eSPing-Ke Shih rtw89_for_each_rtwvif(rtwdev, rtwvif) 54738a66293eSPing-Ke Shih rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 54748a66293eSPing-Ke Shih keep_timer); 54758a66293eSPing-Ke Shih } 5476e3ec7017SPing-Ke Shih 5477e3ec7017SPing-Ke Shih if (en == old) 5478e3ec7017SPing-Ke Shih return; 5479e3ec7017SPing-Ke Shih 5480e3ec7017SPing-Ke Shih rtw89_for_each_rtwvif(rtwdev, rtwvif) 5481e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 5482e3ec7017SPing-Ke Shih } 5483e3ec7017SPing-Ke Shih 5484e3ec7017SPing-Ke Shih static int 5485e3ec7017SPing-Ke Shih __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5486e3ec7017SPing-Ke Shih u32 tx_time) 5487e3ec7017SPing-Ke Shih { 5488e3ec7017SPing-Ke Shih #define MAC_AX_DFLT_TX_TIME 5280 5489e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 5490e3ec7017SPing-Ke Shih u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 5491e3ec7017SPing-Ke Shih u32 reg; 5492e3ec7017SPing-Ke Shih int ret = 0; 5493e3ec7017SPing-Ke Shih 5494e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 5495e3ec7017SPing-Ke Shih rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 5496e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5497e3ec7017SPing-Ke Shih } else { 5498e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5499e3ec7017SPing-Ke Shih if (ret) { 5500e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 5501e3ec7017SPing-Ke Shih return ret; 5502e3ec7017SPing-Ke Shih } 5503e3ec7017SPing-Ke Shih 5504c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 5505e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 5506e3ec7017SPing-Ke Shih max_tx_time >> 5); 5507e3ec7017SPing-Ke Shih } 5508e3ec7017SPing-Ke Shih 5509e3ec7017SPing-Ke Shih return ret; 5510e3ec7017SPing-Ke Shih } 5511e3ec7017SPing-Ke Shih 5512e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5513e3ec7017SPing-Ke Shih bool resume, u32 tx_time) 5514e3ec7017SPing-Ke Shih { 5515e3ec7017SPing-Ke Shih int ret = 0; 5516e3ec7017SPing-Ke Shih 5517e3ec7017SPing-Ke Shih if (!resume) { 5518e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = true; 5519e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5520e3ec7017SPing-Ke Shih } else { 5521e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5522e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = false; 5523e3ec7017SPing-Ke Shih } 5524e3ec7017SPing-Ke Shih 5525e3ec7017SPing-Ke Shih return ret; 5526e3ec7017SPing-Ke Shih } 5527e3ec7017SPing-Ke Shih 5528e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5529e3ec7017SPing-Ke Shih u32 *tx_time) 5530e3ec7017SPing-Ke Shih { 5531e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 5532e3ec7017SPing-Ke Shih u32 reg; 5533e3ec7017SPing-Ke Shih int ret = 0; 5534e3ec7017SPing-Ke Shih 5535e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 5536e3ec7017SPing-Ke Shih *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 5537e3ec7017SPing-Ke Shih } else { 5538e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5539e3ec7017SPing-Ke Shih if (ret) { 5540e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 5541e3ec7017SPing-Ke Shih return ret; 5542e3ec7017SPing-Ke Shih } 5543e3ec7017SPing-Ke Shih 5544c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 5545e3ec7017SPing-Ke Shih *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 5546e3ec7017SPing-Ke Shih } 5547e3ec7017SPing-Ke Shih 5548e3ec7017SPing-Ke Shih return ret; 5549e3ec7017SPing-Ke Shih } 5550e3ec7017SPing-Ke Shih 5551e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 5552e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, 5553e3ec7017SPing-Ke Shih bool resume, u8 tx_retry) 5554e3ec7017SPing-Ke Shih { 5555e3ec7017SPing-Ke Shih int ret = 0; 5556e3ec7017SPing-Ke Shih 5557e3ec7017SPing-Ke Shih rtwsta->data_tx_cnt_lmt = tx_retry; 5558e3ec7017SPing-Ke Shih 5559e3ec7017SPing-Ke Shih if (!resume) { 5560e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = true; 5561e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5562e3ec7017SPing-Ke Shih } else { 5563e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5564e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = false; 5565e3ec7017SPing-Ke Shih } 5566e3ec7017SPing-Ke Shih 5567e3ec7017SPing-Ke Shih return ret; 5568e3ec7017SPing-Ke Shih } 5569e3ec7017SPing-Ke Shih 5570e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 5571e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, u8 *tx_retry) 5572e3ec7017SPing-Ke Shih { 5573e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 5574e3ec7017SPing-Ke Shih u32 reg; 5575e3ec7017SPing-Ke Shih int ret = 0; 5576e3ec7017SPing-Ke Shih 5577e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_retry_limit) { 5578e3ec7017SPing-Ke Shih *tx_retry = rtwsta->data_tx_cnt_lmt; 5579e3ec7017SPing-Ke Shih } else { 5580e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5581e3ec7017SPing-Ke Shih if (ret) { 5582e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 5583e3ec7017SPing-Ke Shih return ret; 5584e3ec7017SPing-Ke Shih } 5585e3ec7017SPing-Ke Shih 5586c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); 5587e3ec7017SPing-Ke Shih *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 5588e3ec7017SPing-Ke Shih } 5589e3ec7017SPing-Ke Shih 5590e3ec7017SPing-Ke Shih return ret; 5591e3ec7017SPing-Ke Shih } 5592e3ec7017SPing-Ke Shih 5593e3ec7017SPing-Ke Shih int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 5594e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 5595e3ec7017SPing-Ke Shih { 55967f69cd42SZong-Zhe Yang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5597e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 55987f69cd42SZong-Zhe Yang u16 set = mac->muedca_ctrl.mask; 5599e3ec7017SPing-Ke Shih u32 reg; 5600e3ec7017SPing-Ke Shih u32 ret; 5601e3ec7017SPing-Ke Shih 5602e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5603e3ec7017SPing-Ke Shih if (ret) 5604e3ec7017SPing-Ke Shih return ret; 5605e3ec7017SPing-Ke Shih 56067f69cd42SZong-Zhe Yang reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 5607e3ec7017SPing-Ke Shih if (en) 5608e3ec7017SPing-Ke Shih rtw89_write16_set(rtwdev, reg, set); 5609e3ec7017SPing-Ke Shih else 5610e3ec7017SPing-Ke Shih rtw89_write16_clr(rtwdev, reg, set); 5611e3ec7017SPing-Ke Shih 5612e3ec7017SPing-Ke Shih return 0; 5613e3ec7017SPing-Ke Shih } 56142a7e54dbSPing-Ke Shih 56152a7e54dbSPing-Ke Shih int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 56162a7e54dbSPing-Ke Shih { 56172a7e54dbSPing-Ke Shih u32 val32; 56182a7e54dbSPing-Ke Shih int ret; 56192a7e54dbSPing-Ke Shih 56202a7e54dbSPing-Ke Shih val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 56212a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 56222a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 56232a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 56242a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 56252a7e54dbSPing-Ke Shih rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 56262a7e54dbSPing-Ke Shih 56272a7e54dbSPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 56282a7e54dbSPing-Ke Shih 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 56292a7e54dbSPing-Ke Shih if (ret) { 56302a7e54dbSPing-Ke Shih rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 56312a7e54dbSPing-Ke Shih offset, val, mask); 56322a7e54dbSPing-Ke Shih return ret; 56332a7e54dbSPing-Ke Shih } 56342a7e54dbSPing-Ke Shih 56352a7e54dbSPing-Ke Shih return 0; 56362a7e54dbSPing-Ke Shih } 56372a7e54dbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 5638bdfbf06cSPing-Ke Shih 5639bdfbf06cSPing-Ke Shih int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 5640bdfbf06cSPing-Ke Shih { 5641bdfbf06cSPing-Ke Shih u32 val32; 5642bdfbf06cSPing-Ke Shih int ret; 5643bdfbf06cSPing-Ke Shih 5644bdfbf06cSPing-Ke Shih val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5645bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 5646bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 5647bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 5648bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5649bdfbf06cSPing-Ke Shih rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5650bdfbf06cSPing-Ke Shih 5651bdfbf06cSPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5652bdfbf06cSPing-Ke Shih 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5653bdfbf06cSPing-Ke Shih if (ret) { 5654bdfbf06cSPing-Ke Shih rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 5655bdfbf06cSPing-Ke Shih return ret; 5656bdfbf06cSPing-Ke Shih } 5657bdfbf06cSPing-Ke Shih 5658bdfbf06cSPing-Ke Shih *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 5659bdfbf06cSPing-Ke Shih 5660bdfbf06cSPing-Ke Shih return 0; 5661bdfbf06cSPing-Ke Shih } 566208484e1fSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_read_xtal_si); 56639a785583SZong-Zhe Yang 56649a785583SZong-Zhe Yang static 56659a785583SZong-Zhe Yang void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 56669a785583SZong-Zhe Yang { 56679a785583SZong-Zhe Yang static const enum rtw89_pkt_drop_sel sels[] = { 56689a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 56699a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 56709a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 56719a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 56729a785583SZong-Zhe Yang }; 56739a785583SZong-Zhe Yang struct rtw89_vif *rtwvif = rtwsta->rtwvif; 56749a785583SZong-Zhe Yang struct rtw89_pkt_drop_params params = {0}; 56759a785583SZong-Zhe Yang int i; 56769a785583SZong-Zhe Yang 56779a785583SZong-Zhe Yang params.mac_band = RTW89_MAC_0; 56789a785583SZong-Zhe Yang params.macid = rtwsta->mac_id; 56799a785583SZong-Zhe Yang params.port = rtwvif->port; 56809a785583SZong-Zhe Yang params.mbssid = 0; 56819a785583SZong-Zhe Yang params.tf_trs = rtwvif->trigger; 56829a785583SZong-Zhe Yang 56839a785583SZong-Zhe Yang for (i = 0; i < ARRAY_SIZE(sels); i++) { 56849a785583SZong-Zhe Yang params.sel = sels[i]; 56859a785583SZong-Zhe Yang rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 56869a785583SZong-Zhe Yang } 56879a785583SZong-Zhe Yang } 56889a785583SZong-Zhe Yang 56899a785583SZong-Zhe Yang static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 56909a785583SZong-Zhe Yang { 56919a785583SZong-Zhe Yang struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 56929a785583SZong-Zhe Yang struct rtw89_vif *rtwvif = rtwsta->rtwvif; 56939a785583SZong-Zhe Yang struct rtw89_dev *rtwdev = rtwvif->rtwdev; 56949a785583SZong-Zhe Yang struct rtw89_vif *target = data; 56959a785583SZong-Zhe Yang 56969a785583SZong-Zhe Yang if (rtwvif != target) 56979a785583SZong-Zhe Yang return; 56989a785583SZong-Zhe Yang 56999a785583SZong-Zhe Yang rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 57009a785583SZong-Zhe Yang } 57019a785583SZong-Zhe Yang 57029a785583SZong-Zhe Yang void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 57039a785583SZong-Zhe Yang { 57049a785583SZong-Zhe Yang ieee80211_iterate_stations_atomic(rtwdev->hw, 57059a785583SZong-Zhe Yang rtw89_mac_pkt_drop_vif_iter, 57069a785583SZong-Zhe Yang rtwvif); 57079a785583SZong-Zhe Yang } 570841d56769SChih-Kang Chang 570941d56769SChih-Kang Chang int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 571041d56769SChih-Kang Chang enum rtw89_mac_idx band) 571141d56769SChih-Kang Chang { 571241d56769SChih-Kang Chang struct rtw89_pkt_drop_params params = {0}; 571341d56769SChih-Kang Chang bool empty; 571441d56769SChih-Kang Chang int i, ret = 0, try_cnt = 3; 571541d56769SChih-Kang Chang 571641d56769SChih-Kang Chang params.mac_band = band; 571741d56769SChih-Kang Chang params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 571841d56769SChih-Kang Chang 571941d56769SChih-Kang Chang for (i = 0; i < try_cnt; i++) { 572041d56769SChih-Kang Chang ret = read_poll_timeout(mac_is_txq_empty, empty, empty, 50, 572141d56769SChih-Kang Chang 50000, false, rtwdev); 57220d1f7ff1SZong-Zhe Yang if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 572341d56769SChih-Kang Chang rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 572441d56769SChih-Kang Chang else 572541d56769SChih-Kang Chang return 0; 572641d56769SChih-Kang Chang } 572741d56769SChih-Kang Chang return ret; 572841d56769SChih-Kang Chang } 5729c220d08eSPing-Ke Shih 5730fa31a8c5SPing-Ke Shih static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 5731ae4dc23dSPing-Ke Shih { 5732ae4dc23dSPing-Ke Shih u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 5733ae4dc23dSPing-Ke Shih 5734ae4dc23dSPing-Ke Shih return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 5735ae4dc23dSPing-Ke Shih } 5736ae4dc23dSPing-Ke Shih 5737ae4dc23dSPing-Ke Shih static 573880e706a8SPing-Ke Shih int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 573980e706a8SPing-Ke Shih bool h2c_or_fwdl) 574080e706a8SPing-Ke Shih { 574180e706a8SPing-Ke Shih u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 574280e706a8SPing-Ke Shih u8 val; 574380e706a8SPing-Ke Shih 574480e706a8SPing-Ke Shih return read_poll_timeout_atomic(rtw89_read8, val, val & check, 574580e706a8SPing-Ke Shih 1, FWDL_WAIT_CNT, false, 574680e706a8SPing-Ke Shih rtwdev, R_AX_WCPU_FW_CTRL); 574780e706a8SPing-Ke Shih } 574880e706a8SPing-Ke Shih 5749c220d08eSPing-Ke Shih const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 5750c220d08eSPing-Ke Shih .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 575160168f6cSPing-Ke Shih .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 575260168f6cSPing-Ke Shih .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 575360168f6cSPing-Ke Shih .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 57549d87e7dcSPing-Ke Shih .rx_fltr = R_AX_RX_FLTR_OPT, 57557c8a55ddSPing-Ke Shih .port_base = &rtw89_port_base_ax, 5756fbd1829dSZong-Zhe Yang .agg_len_ht = R_AX_AGG_LEN_HT_0, 5757ae4dc23dSPing-Ke Shih 57587f69cd42SZong-Zhe Yang .muedca_ctrl = { 57597f69cd42SZong-Zhe Yang .addr = R_AX_MUEDCA_EN, 57607f69cd42SZong-Zhe Yang .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 57617f69cd42SZong-Zhe Yang }, 5762*5fa1c5d4SZong-Zhe Yang .bfee_ctrl = { 5763*5fa1c5d4SZong-Zhe Yang .addr = R_AX_BFMEE_RESP_OPTION, 5764*5fa1c5d4SZong-Zhe Yang .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 5765*5fa1c5d4SZong-Zhe Yang B_AX_BFMEE_HE_NDPA_EN, 5766*5fa1c5d4SZong-Zhe Yang }, 57677f69cd42SZong-Zhe Yang 5768ae4dc23dSPing-Ke Shih .disable_cpu = rtw89_mac_disable_cpu_ax, 5769ae4dc23dSPing-Ke Shih .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 5770ae4dc23dSPing-Ke Shih .fwdl_get_status = rtw89_fw_get_rdy_ax, 5771ae4dc23dSPing-Ke Shih .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 577206b26738SZong-Zhe Yang 577306b26738SZong-Zhe Yang .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 5774c220d08eSPing-Ke Shih }; 5775c220d08eSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_gen_ax); 5776