1e3ec7017SPing-Ke Shih // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2e3ec7017SPing-Ke Shih /* Copyright(c) 2019-2020 Realtek Corporation 3e3ec7017SPing-Ke Shih */ 4e3ec7017SPing-Ke Shih 5e3ec7017SPing-Ke Shih #include "cam.h" 6967439c7SZong-Zhe Yang #include "chan.h" 7e3ec7017SPing-Ke Shih #include "debug.h" 888e6a923SPing-Ke Shih #include "efuse.h" 9e3ec7017SPing-Ke Shih #include "fw.h" 10e3ec7017SPing-Ke Shih #include "mac.h" 11f7333fc2SChia-Yuan Li #include "pci.h" 12e3ec7017SPing-Ke Shih #include "ps.h" 13e3ec7017SPing-Ke Shih #include "reg.h" 14e3ec7017SPing-Ke Shih #include "util.h" 15e3ec7017SPing-Ke Shih 1660168f6cSPing-Ke Shih static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 17e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 18e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 19e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 20e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 21e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 22e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 23e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 24e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 25e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 26e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 27e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 28e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 29e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 30e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 31e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 32e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 33e1400b11SZong-Zhe Yang [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 34ec356ffbSChia-Yuan Li [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 35dadb2086SPing-Ke Shih [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 36732dd91dSPing-Ke Shih [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 37732dd91dSPing-Ke Shih [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 38e1400b11SZong-Zhe Yang }; 39e1400b11SZong-Zhe Yang 40ec356ffbSChia-Yuan Li static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 41ec356ffbSChia-Yuan Li u32 val, enum rtw89_mac_mem_sel sel) 42ec356ffbSChia-Yuan Li { 4360168f6cSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4460168f6cSPing-Ke Shih u32 addr = mac->mem_base_addrs[sel] + offset; 45ec356ffbSChia-Yuan Li 4660168f6cSPing-Ke Shih rtw89_write32(rtwdev, mac->filter_model_addr, addr); 4760168f6cSPing-Ke Shih rtw89_write32(rtwdev, mac->indir_access_addr, val); 48ec356ffbSChia-Yuan Li } 49ec356ffbSChia-Yuan Li 50ec356ffbSChia-Yuan Li static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 51ec356ffbSChia-Yuan Li enum rtw89_mac_mem_sel sel) 52ec356ffbSChia-Yuan Li { 5360168f6cSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5460168f6cSPing-Ke Shih u32 addr = mac->mem_base_addrs[sel] + offset; 55ec356ffbSChia-Yuan Li 5660168f6cSPing-Ke Shih rtw89_write32(rtwdev, mac->filter_model_addr, addr); 5760168f6cSPing-Ke Shih return rtw89_read32(rtwdev, mac->indir_access_addr); 58ec356ffbSChia-Yuan Li } 59ec356ffbSChia-Yuan Li 60cfb99433SPing-Ke Shih static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 61e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 62e3ec7017SPing-Ke Shih { 63e3ec7017SPing-Ke Shih u32 val, r_val; 64e3ec7017SPing-Ke Shih 65e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 66e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 67e3ec7017SPing-Ke Shih val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 68e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 69e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 70e3ec7017SPing-Ke Shih val = B_AX_CMAC_EN; 71e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 72e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 73e3ec7017SPing-Ke Shih val = B_AX_CMAC1_FEN; 74e3ec7017SPing-Ke Shih } else { 75e3ec7017SPing-Ke Shih return -EINVAL; 76e3ec7017SPing-Ke Shih } 77e3ec7017SPing-Ke Shih if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 78e3ec7017SPing-Ke Shih (val & r_val) != val) 79e3ec7017SPing-Ke Shih return -EFAULT; 80e3ec7017SPing-Ke Shih 81e3ec7017SPing-Ke Shih return 0; 82e3ec7017SPing-Ke Shih } 83e3ec7017SPing-Ke Shih 84e3ec7017SPing-Ke Shih int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 85e3ec7017SPing-Ke Shih { 86e3ec7017SPing-Ke Shih u8 lte_ctrl; 87e3ec7017SPing-Ke Shih int ret; 88e3ec7017SPing-Ke Shih 89e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 90e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 91e3ec7017SPing-Ke Shih if (ret) 92e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 93e3ec7017SPing-Ke Shih 94e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 95e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 96e3ec7017SPing-Ke Shih 97e3ec7017SPing-Ke Shih return ret; 98e3ec7017SPing-Ke Shih } 99e3ec7017SPing-Ke Shih 100e3ec7017SPing-Ke Shih int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 101e3ec7017SPing-Ke Shih { 102e3ec7017SPing-Ke Shih u8 lte_ctrl; 103e3ec7017SPing-Ke Shih int ret; 104e3ec7017SPing-Ke Shih 105e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 106e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 107e3ec7017SPing-Ke Shih if (ret) 108e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 109e3ec7017SPing-Ke Shih 110e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 111e3ec7017SPing-Ke Shih *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 112e3ec7017SPing-Ke Shih 113e3ec7017SPing-Ke Shih return ret; 114e3ec7017SPing-Ke Shih } 115e3ec7017SPing-Ke Shih 1166f8d3655SChia-Yuan Li int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 117e3ec7017SPing-Ke Shih { 118e3ec7017SPing-Ke Shih u32 ctrl_reg, data_reg, ctrl_data; 119e3ec7017SPing-Ke Shih u32 val; 120e3ec7017SPing-Ke Shih int ret; 121e3ec7017SPing-Ke Shih 122e3ec7017SPing-Ke Shih switch (ctrl->type) { 123e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_WDE: 124e3ec7017SPing-Ke Shih ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 125e3ec7017SPing-Ke Shih data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 126e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 127e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 128e3ec7017SPing-Ke Shih B_AX_WDE_DFI_ACTIVE; 129e3ec7017SPing-Ke Shih break; 130e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_PLE: 131e3ec7017SPing-Ke Shih ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 132e3ec7017SPing-Ke Shih data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 133e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 134e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 135e3ec7017SPing-Ke Shih B_AX_PLE_DFI_ACTIVE; 136e3ec7017SPing-Ke Shih break; 137e3ec7017SPing-Ke Shih default: 138e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 139e3ec7017SPing-Ke Shih return -EINVAL; 140e3ec7017SPing-Ke Shih } 141e3ec7017SPing-Ke Shih 142e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 143e3ec7017SPing-Ke Shih 144e3ec7017SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 145e3ec7017SPing-Ke Shih 1, 1000, false, rtwdev, ctrl_reg); 146e3ec7017SPing-Ke Shih if (ret) { 147e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 148e3ec7017SPing-Ke Shih ctrl_reg, ctrl_data); 149e3ec7017SPing-Ke Shih return ret; 150e3ec7017SPing-Ke Shih } 151e3ec7017SPing-Ke Shih 152e3ec7017SPing-Ke Shih ctrl->out_data = rtw89_read32(rtwdev, data_reg); 153e3ec7017SPing-Ke Shih return 0; 154e3ec7017SPing-Ke Shih } 155e3ec7017SPing-Ke Shih 1566f8d3655SChia-Yuan Li int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 157e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota *quota) 158e3ec7017SPing-Ke Shih { 159e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 160e3ec7017SPing-Ke Shih int ret; 161e3ec7017SPing-Ke Shih 162e3ec7017SPing-Ke Shih ctrl.type = quota->dle_type; 163e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QUOTA; 164e3ec7017SPing-Ke Shih ctrl.addr = quota->qtaid; 1656f8d3655SChia-Yuan Li ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 166e3ec7017SPing-Ke Shih if (ret) { 1676f8d3655SChia-Yuan Li rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 168e3ec7017SPing-Ke Shih return ret; 169e3ec7017SPing-Ke Shih } 170e3ec7017SPing-Ke Shih 171e3ec7017SPing-Ke Shih quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 172e3ec7017SPing-Ke Shih quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 173e3ec7017SPing-Ke Shih return 0; 174e3ec7017SPing-Ke Shih } 175e3ec7017SPing-Ke Shih 17627ea6be9SZong-Zhe Yang int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 177e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty *qempty) 178e3ec7017SPing-Ke Shih { 179e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 180e3ec7017SPing-Ke Shih u32 ret; 181e3ec7017SPing-Ke Shih 182e3ec7017SPing-Ke Shih ctrl.type = qempty->dle_type; 183e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QEMPTY; 184e3ec7017SPing-Ke Shih ctrl.addr = qempty->grpsel; 1856f8d3655SChia-Yuan Li ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 186e3ec7017SPing-Ke Shih if (ret) { 1876f8d3655SChia-Yuan Li rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 188e3ec7017SPing-Ke Shih return ret; 189e3ec7017SPing-Ke Shih } 190e3ec7017SPing-Ke Shih 191e3ec7017SPing-Ke Shih qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 192e3ec7017SPing-Ke Shih return 0; 193e3ec7017SPing-Ke Shih } 194e3ec7017SPing-Ke Shih 1956f8d3655SChia-Yuan Li static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 196e3ec7017SPing-Ke Shih { 197e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 198e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 199e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 200e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 201e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 202e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 203e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 204e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 205e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 206e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 207e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 208e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 209e3ec7017SPing-Ke Shih } 210e3ec7017SPing-Ke Shih 2116f8d3655SChia-Yuan Li static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 212e3ec7017SPing-Ke Shih { 213e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty qempty; 214e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota quota; 215e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 216e3ec7017SPing-Ke Shih u32 val, not_empty, i; 217e3ec7017SPing-Ke Shih int ret; 218e3ec7017SPing-Ke Shih 219e3ec7017SPing-Ke Shih qempty.dle_type = DLE_CTRL_TYPE_PLE; 220e3ec7017SPing-Ke Shih qempty.grpsel = 0; 22189e4a00fSÍñigo Huguet qempty.qempty = ~(u32)0; 22227ea6be9SZong-Zhe Yang ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 223e3ec7017SPing-Ke Shih if (ret) 224e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 225e3ec7017SPing-Ke Shih else 226e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 227e3ec7017SPing-Ke Shih 228e3ec7017SPing-Ke Shih for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 229e3ec7017SPing-Ke Shih if (!(not_empty & BIT(0))) 230e3ec7017SPing-Ke Shih continue; 231e3ec7017SPing-Ke Shih ctrl.type = DLE_CTRL_TYPE_PLE; 232e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QLNKTBL; 233e3ec7017SPing-Ke Shih ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 2346f8d3655SChia-Yuan Li u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 2356f8d3655SChia-Yuan Li ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 236e3ec7017SPing-Ke Shih if (ret) 237e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 238e3ec7017SPing-Ke Shih else 2396f8d3655SChia-Yuan Li rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 2406f8d3655SChia-Yuan Li u32_get_bits(ctrl.out_data, 2416f8d3655SChia-Yuan Li QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 242e3ec7017SPing-Ke Shih } 243e3ec7017SPing-Ke Shih 244e3ec7017SPing-Ke Shih quota.dle_type = DLE_CTRL_TYPE_PLE; 245e3ec7017SPing-Ke Shih quota.qtaid = 6; 2466f8d3655SChia-Yuan Li ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 247e3ec7017SPing-Ke Shih if (ret) 248e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 249e3ec7017SPing-Ke Shih else 250e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 251e3ec7017SPing-Ke Shih quota.rsv_pgnum, quota.use_pgnum); 252e3ec7017SPing-Ke Shih 253e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 2546f8d3655SChia-Yuan Li rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 2556f8d3655SChia-Yuan Li u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 2566f8d3655SChia-Yuan Li rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 2576f8d3655SChia-Yuan Li u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 2586f8d3655SChia-Yuan Li val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 2596f8d3655SChia-Yuan Li rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 2606f8d3655SChia-Yuan Li u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 2616f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 2626f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 2636f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 2646f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 2656f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 2666f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 267e3ec7017SPing-Ke Shih 2686f8d3655SChia-Yuan Li if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 2696f8d3655SChia-Yuan Li quota.dle_type = DLE_CTRL_TYPE_PLE; 2706f8d3655SChia-Yuan Li quota.qtaid = 7; 2716f8d3655SChia-Yuan Li ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 2726f8d3655SChia-Yuan Li if (ret) 2736f8d3655SChia-Yuan Li rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 2746f8d3655SChia-Yuan Li else 2756f8d3655SChia-Yuan Li rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 2766f8d3655SChia-Yuan Li quota.rsv_pgnum, quota.use_pgnum); 2776f8d3655SChia-Yuan Li 2786f8d3655SChia-Yuan Li val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 2796f8d3655SChia-Yuan Li rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 2806f8d3655SChia-Yuan Li u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 2816f8d3655SChia-Yuan Li rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 2826f8d3655SChia-Yuan Li u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 2836f8d3655SChia-Yuan Li val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 2846f8d3655SChia-Yuan Li rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 2856f8d3655SChia-Yuan Li u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 2866f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 2876f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 2886f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 2896f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 2906f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 2916f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 292e3ec7017SPing-Ke Shih } 293e3ec7017SPing-Ke Shih 2946f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 2956f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 2966f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 2976f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 2986f8d3655SChia-Yuan Li 2996f8d3655SChia-Yuan Li dump_err_status_dispatcher_ax(rtwdev); 3006f8d3655SChia-Yuan Li } 3016f8d3655SChia-Yuan Li 3026f8d3655SChia-Yuan Li void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 303e3ec7017SPing-Ke Shih enum mac_ax_err_info err) 304e3ec7017SPing-Ke Shih { 3056f8d3655SChia-Yuan Li const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 306e3ec7017SPing-Ke Shih u32 dbg, event; 307e3ec7017SPing-Ke Shih 308e3ec7017SPing-Ke Shih dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 3096f8d3655SChia-Yuan Li event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 310e3ec7017SPing-Ke Shih 311e3ec7017SPing-Ke Shih switch (event) { 312e3ec7017SPing-Ke Shih case MAC_AX_L0_TO_L1_RX_QTA_LOST: 313e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota lost!\n"); 3146f8d3655SChia-Yuan Li mac->dump_qta_lost(rtwdev); 315e3ec7017SPing-Ke Shih break; 316e3ec7017SPing-Ke Shih default: 317e3ec7017SPing-Ke Shih break; 318e3ec7017SPing-Ke Shih } 319e3ec7017SPing-Ke Shih } 320e3ec7017SPing-Ke Shih 3216f8d3655SChia-Yuan Li void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 322e3ec7017SPing-Ke Shih { 323f7333fc2SChia-Yuan Li const struct rtw89_chip_info *chip = rtwdev->chip; 324f7333fc2SChia-Yuan Li u32 dmac_err; 325f7333fc2SChia-Yuan Li int i, ret; 326e3ec7017SPing-Ke Shih 327f7333fc2SChia-Yuan Li ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 328f7333fc2SChia-Yuan Li if (ret) { 329f7333fc2SChia-Yuan Li rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 330e3ec7017SPing-Ke Shih return; 331f7333fc2SChia-Yuan Li } 332e3ec7017SPing-Ke Shih 333e3ec7017SPing-Ke Shih dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 334e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 335f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 336f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 337e3ec7017SPing-Ke Shih 338e3ec7017SPing-Ke Shih if (dmac_err) { 339f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 340f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 341e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 342f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 343f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 344f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 345f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 346f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 347f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 348f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 349f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 350f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 351f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 352f7333fc2SChia-Yuan Li } 353e3ec7017SPing-Ke Shih } 354e3ec7017SPing-Ke Shih 355e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 356f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 357e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 358e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 359e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 360f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) 361f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 362f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 363f7333fc2SChia-Yuan Li else 364f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 365f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 366e3ec7017SPing-Ke Shih } 367e3ec7017SPing-Ke Shih 368e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WSEC_ERR_FLAG) { 369f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 370f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 371f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 372f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 373f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 374f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 375f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 376f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 377f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 378f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 379f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 380f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 381f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 382f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 383f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 384f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 385f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 386f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 387f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 388f7333fc2SChia-Yuan Li 389f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 390f7333fc2SChia-Yuan Li B_AX_DBG_SEL0, 0x8B); 391f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392f7333fc2SChia-Yuan Li B_AX_DBG_SEL1, 0x8B); 393f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 394f7333fc2SChia-Yuan Li B_AX_SEL_0XC0_MASK, 1); 395f7333fc2SChia-Yuan Li for (i = 0; i < 0x10; i++) { 396f7333fc2SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 397f7333fc2SChia-Yuan Li B_AX_SEC_DBG_PORT_FIELD_MASK, i); 398f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 399f7333fc2SChia-Yuan Li i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 400f7333fc2SChia-Yuan Li } 4016f8d3655SChia-Yuan Li } else if (chip->chip_id == RTL8922A) { 4026f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 4036f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 4046f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 4056f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 4066f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 4076f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 4086f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 4096f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 4106f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 4116f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 4126f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 4136f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 4146f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 4156f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 416f7333fc2SChia-Yuan Li } else { 417e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 418e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 419f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 420e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 421f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 422e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 423f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 424e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 425f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 426e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 427f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 428e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 429f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 430e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 431f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 432e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 433f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 434e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 435f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 436e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 437e3ec7017SPing-Ke Shih } 438f7333fc2SChia-Yuan Li } 439e3ec7017SPing-Ke Shih 440e3ec7017SPing-Ke Shih if (dmac_err & B_AX_MPDU_ERR_FLAG) { 441f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 442e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 443e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 444e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 445f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 446e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 447e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 448e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 449e3ec7017SPing-Ke Shih } 450e3ec7017SPing-Ke Shih 451e3ec7017SPing-Ke Shih if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 4526f8d3655SChia-Yuan Li if (chip->chip_id == RTL8922A) { 4536f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 4546f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 4556f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 4566f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 4576f8d3655SChia-Yuan Li } else { 458f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 459e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 460e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 461e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 462e3ec7017SPing-Ke Shih } 4636f8d3655SChia-Yuan Li } 464e3ec7017SPing-Ke Shih 465e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 466f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 467e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 468e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 469e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 470f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 471e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 472e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 473e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 474e3ec7017SPing-Ke Shih } 475e3ec7017SPing-Ke Shih 476e3ec7017SPing-Ke Shih if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 4776f8d3655SChia-Yuan Li if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 478f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 479f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 480f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 481f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 482f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 483f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 484f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 485f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 486f7333fc2SChia-Yuan Li } else { 487e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 488e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 489e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 490e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 491e3ec7017SPing-Ke Shih } 492f7333fc2SChia-Yuan Li } 493e3ec7017SPing-Ke Shih 494e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 495f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 496e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 497e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 498e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 499f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 500e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 501e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 502e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 503e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 504e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 505e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 506e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 507e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 508e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 509e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 510e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 511e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 512e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 513e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 514e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 5156f8d3655SChia-Yuan Li if (chip->chip_id == RTL8922A) { 5166f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 5176f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 5186f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 5196f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 5206f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 5216f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 5226f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 5236f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 5246f8d3655SChia-Yuan Li } else { 5256f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 5266f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 527e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 528e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 529f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 530f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 531f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 532f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 533f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 534f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 535f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 536f7333fc2SChia-Yuan Li } else { 537e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 538e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 539e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 540e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 541e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 542e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 543f7333fc2SChia-Yuan Li } 544e3ec7017SPing-Ke Shih } 5456f8d3655SChia-Yuan Li } 546e3ec7017SPing-Ke Shih 547e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 548f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 549e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 550e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 551e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 552e3ec7017SPing-Ke Shih } 553e3ec7017SPing-Ke Shih 554f7333fc2SChia-Yuan Li if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 5556f8d3655SChia-Yuan Li if (chip->chip_id == RTL8922A) { 5566f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 5576f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 5586f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 5596f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 5606f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 5616f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 5626f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 5636f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 5646f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 5656f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 5666f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 5676f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 5686f8d3655SChia-Yuan Li } else { 569f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 570f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 571f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 572f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 573f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 574f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 575f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 576f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 577f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 578f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 579f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 580f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 581e3ec7017SPing-Ke Shih } 5826f8d3655SChia-Yuan Li } 583e3ec7017SPing-Ke Shih 584f7333fc2SChia-Yuan Li if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 5856f8d3655SChia-Yuan Li if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 586f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 587f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 588f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 589f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 590f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 591f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 592f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 593f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 594f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 595f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 596f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 597f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 598f7333fc2SChia-Yuan Li } else { 599e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 600e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 601f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 602f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 603f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 604f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 605f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 606f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 607f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 608f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 609f7333fc2SChia-Yuan Li } 6106f8d3655SChia-Yuan Li if (chip->chip_id == RTL8922A) { 6116f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 6126f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 6136f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 6146f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 6156f8d3655SChia-Yuan Li } 616e3ec7017SPing-Ke Shih } 617e3ec7017SPing-Ke Shih 6186f8d3655SChia-Yuan Li if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 6196f8d3655SChia-Yuan Li if (chip->chip_id == RTL8922A) { 6206f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 6216f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 6226f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 6236f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 6246f8d3655SChia-Yuan Li } else if (chip->chip_id == RTL8852C) { 625f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 626f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 627f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 628f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 629f7333fc2SChia-Yuan Li } 630f7333fc2SChia-Yuan Li } 631f7333fc2SChia-Yuan Li 6326f8d3655SChia-Yuan Li if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 6336f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 6346f8d3655SChia-Yuan Li rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 6356f8d3655SChia-Yuan Li RTW89_MAC_MEM_AXIDMA)); 6366f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 6376f8d3655SChia-Yuan Li rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 6386f8d3655SChia-Yuan Li RTW89_MAC_MEM_AXIDMA)); 6396f8d3655SChia-Yuan Li } 6406f8d3655SChia-Yuan Li 6416f8d3655SChia-Yuan Li if (dmac_err & B_BE_MLO_ERR_INT) { 6426f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 6436f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 6446f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 6456f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 6466f8d3655SChia-Yuan Li } 6476f8d3655SChia-Yuan Li 6486f8d3655SChia-Yuan Li if (dmac_err & B_BE_PLRLS_ERR_INT) { 6496f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 6506f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 6516f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 6526f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 6536f8d3655SChia-Yuan Li } 6546f8d3655SChia-Yuan Li } 6556f8d3655SChia-Yuan Li 6566f8d3655SChia-Yuan Li static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 657f7333fc2SChia-Yuan Li u8 band) 658f7333fc2SChia-Yuan Li { 659f7333fc2SChia-Yuan Li const struct rtw89_chip_info *chip = rtwdev->chip; 660f7333fc2SChia-Yuan Li u32 offset = 0; 661f7333fc2SChia-Yuan Li u32 cmac_err; 662f7333fc2SChia-Yuan Li int ret; 663f7333fc2SChia-Yuan Li 664f7333fc2SChia-Yuan Li ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 665f7333fc2SChia-Yuan Li if (ret) { 666f7333fc2SChia-Yuan Li if (band) 667f7333fc2SChia-Yuan Li rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 668f7333fc2SChia-Yuan Li else 669f7333fc2SChia-Yuan Li rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 670f7333fc2SChia-Yuan Li return; 671f7333fc2SChia-Yuan Li } 672f7333fc2SChia-Yuan Li 673f7333fc2SChia-Yuan Li if (band) 674f7333fc2SChia-Yuan Li offset = RTW89_MAC_AX_BAND_REG_OFFSET; 675f7333fc2SChia-Yuan Li 676f7333fc2SChia-Yuan Li cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 677f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 678f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 679f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 680f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 681f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 682f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 683f7333fc2SChia-Yuan Li 684e3ec7017SPing-Ke Shih if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 685f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 686f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 687f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 688f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 689e3ec7017SPing-Ke Shih } 690e3ec7017SPing-Ke Shih 691e3ec7017SPing-Ke Shih if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 692f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 693f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 694f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 695f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 696e3ec7017SPing-Ke Shih } 697e3ec7017SPing-Ke Shih 698e3ec7017SPing-Ke Shih if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 699f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 700f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 701f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 702f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 703f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 704f7333fc2SChia-Yuan Li } else { 705f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 706f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 707f7333fc2SChia-Yuan Li } 708e3ec7017SPing-Ke Shih } 709e3ec7017SPing-Ke Shih 710f7333fc2SChia-Yuan Li if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 711f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 712f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 713f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 714f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 715f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 716f7333fc2SChia-Yuan Li } else { 717f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 718f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 719f7333fc2SChia-Yuan Li } 720e3ec7017SPing-Ke Shih } 721e3ec7017SPing-Ke Shih 722e3ec7017SPing-Ke Shih if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 723f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 724f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 725f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 726f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 727e3ec7017SPing-Ke Shih } 728e3ec7017SPing-Ke Shih 729e3ec7017SPing-Ke Shih if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 730f7333fc2SChia-Yuan Li if (chip->chip_id == RTL8852C) { 731f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 732f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 733f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 734f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 735f7333fc2SChia-Yuan Li } else { 736f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 737f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 738e3ec7017SPing-Ke Shih } 739f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 740f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 741f7333fc2SChia-Yuan Li } 742f7333fc2SChia-Yuan Li 743f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 744f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 745f7333fc2SChia-Yuan Li } 746f7333fc2SChia-Yuan Li 7476f8d3655SChia-Yuan Li static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 748f7333fc2SChia-Yuan Li enum mac_ax_err_info err) 749f7333fc2SChia-Yuan Li { 750f7333fc2SChia-Yuan Li if (err != MAC_AX_ERR_L1_ERR_DMAC && 751f7333fc2SChia-Yuan Li err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 752f7333fc2SChia-Yuan Li err != MAC_AX_ERR_L0_ERR_CMAC0 && 753f5d98831SZong-Zhe Yang err != MAC_AX_ERR_L0_ERR_CMAC1 && 754f5d98831SZong-Zhe Yang err != MAC_AX_ERR_RXI300) 755f7333fc2SChia-Yuan Li return; 756f7333fc2SChia-Yuan Li 757f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 758f7333fc2SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 759f7333fc2SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 7606f8d3655SChia-Yuan Li rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 7616f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 7626f8d3655SChia-Yuan Li rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 7636f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 7646f8d3655SChia-Yuan Li rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 7656f8d3655SChia-Yuan Li rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 766f7333fc2SChia-Yuan Li 767f7333fc2SChia-Yuan Li rtw89_mac_dump_dmac_err_status(rtwdev); 7686f8d3655SChia-Yuan Li rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 7696f8d3655SChia-Yuan Li rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 770e3ec7017SPing-Ke Shih 771e3ec7017SPing-Ke Shih rtwdev->hci.ops->dump_err_status(rtwdev); 772e3ec7017SPing-Ke Shih 773e3ec7017SPing-Ke Shih if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 774e3ec7017SPing-Ke Shih rtw89_mac_dump_l0_to_l1(rtwdev, err); 775e3ec7017SPing-Ke Shih 776e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "<---\n"); 777e3ec7017SPing-Ke Shih } 778e3ec7017SPing-Ke Shih 7798130e94eSChin-Yen Lee static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 7808130e94eSChin-Yen Lee { 7818130e94eSChin-Yen Lee struct rtw89_ser *ser = &rtwdev->ser; 7828130e94eSChin-Yen Lee u32 dmac_err, imr, isr; 7838130e94eSChin-Yen Lee int ret; 7848130e94eSChin-Yen Lee 7858130e94eSChin-Yen Lee if (rtwdev->chip->chip_id == RTL8852C) { 7868130e94eSChin-Yen Lee ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 7878130e94eSChin-Yen Lee if (ret) 7888130e94eSChin-Yen Lee return true; 7898130e94eSChin-Yen Lee 7908130e94eSChin-Yen Lee if (err == MAC_AX_ERR_L1_ERR_DMAC) { 7918130e94eSChin-Yen Lee dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 7928130e94eSChin-Yen Lee imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 7938130e94eSChin-Yen Lee isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 7948130e94eSChin-Yen Lee 7958130e94eSChin-Yen Lee if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 7968130e94eSChin-Yen Lee ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 7978130e94eSChin-Yen Lee set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 7988130e94eSChin-Yen Lee return true; 7998130e94eSChin-Yen Lee } 8008130e94eSChin-Yen Lee } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 8018130e94eSChin-Yen Lee if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 8028130e94eSChin-Yen Lee return true; 8038130e94eSChin-Yen Lee } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 8048130e94eSChin-Yen Lee if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 8058130e94eSChin-Yen Lee return true; 8068130e94eSChin-Yen Lee } 8078130e94eSChin-Yen Lee } 8088130e94eSChin-Yen Lee 8098130e94eSChin-Yen Lee return false; 8108130e94eSChin-Yen Lee } 8118130e94eSChin-Yen Lee 812e3ec7017SPing-Ke Shih u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 813e3ec7017SPing-Ke Shih { 8146f8d3655SChia-Yuan Li const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 815198b6cf7SZong-Zhe Yang u32 err, err_scnr; 816e3ec7017SPing-Ke Shih int ret; 817e3ec7017SPing-Ke Shih 818e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 819e3ec7017SPing-Ke Shih false, rtwdev, R_AX_HALT_C2H_CTRL); 820e3ec7017SPing-Ke Shih if (ret) { 821e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "Polling FW err status fail\n"); 822e3ec7017SPing-Ke Shih return ret; 823e3ec7017SPing-Ke Shih } 824e3ec7017SPing-Ke Shih 825e3ec7017SPing-Ke Shih err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 826e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 827e3ec7017SPing-Ke Shih 828198b6cf7SZong-Zhe Yang err_scnr = RTW89_ERROR_SCENARIO(err); 829198b6cf7SZong-Zhe Yang if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 830198b6cf7SZong-Zhe Yang err = MAC_AX_ERR_CPU_EXCEPTION; 831198b6cf7SZong-Zhe Yang else if (err_scnr == RTW89_WCPU_ASSERTION) 832198b6cf7SZong-Zhe Yang err = MAC_AX_ERR_ASSERTION; 833f5d98831SZong-Zhe Yang else if (err_scnr == RTW89_RXI300_ERROR) 834f5d98831SZong-Zhe Yang err = MAC_AX_ERR_RXI300; 835198b6cf7SZong-Zhe Yang 8368130e94eSChin-Yen Lee if (rtw89_mac_suppress_log(rtwdev, err)) 8378130e94eSChin-Yen Lee return err; 8388130e94eSChin-Yen Lee 839e3ec7017SPing-Ke Shih rtw89_fw_st_dbg_dump(rtwdev); 8406f8d3655SChia-Yuan Li mac->dump_err_status(rtwdev, err); 841e3ec7017SPing-Ke Shih 842e3ec7017SPing-Ke Shih return err; 843e3ec7017SPing-Ke Shih } 844e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_get_err_status); 845e3ec7017SPing-Ke Shih 846e3ec7017SPing-Ke Shih int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 847e3ec7017SPing-Ke Shih { 84856617fd0SZong-Zhe Yang struct rtw89_ser *ser = &rtwdev->ser; 849e3ec7017SPing-Ke Shih u32 halt; 850e3ec7017SPing-Ke Shih int ret = 0; 851e3ec7017SPing-Ke Shih 852e3ec7017SPing-Ke Shih if (err > MAC_AX_SET_ERR_MAX) { 853e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 854e3ec7017SPing-Ke Shih return -EINVAL; 855e3ec7017SPing-Ke Shih } 856e3ec7017SPing-Ke Shih 857e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 858e3ec7017SPing-Ke Shih 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 859e3ec7017SPing-Ke Shih if (ret) { 860e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 861e3ec7017SPing-Ke Shih return -EFAULT; 862e3ec7017SPing-Ke Shih } 863e3ec7017SPing-Ke Shih 864e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 86556617fd0SZong-Zhe Yang 86656617fd0SZong-Zhe Yang if (ser->prehandle_l1 && 86756617fd0SZong-Zhe Yang (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 86856617fd0SZong-Zhe Yang return 0; 86956617fd0SZong-Zhe Yang 870e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 871e3ec7017SPing-Ke Shih 872e3ec7017SPing-Ke Shih return 0; 873e3ec7017SPing-Ke Shih } 874e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_set_err_status); 875e3ec7017SPing-Ke Shih 876e3ec7017SPing-Ke Shih static int hfc_reset_param(struct rtw89_dev *rtwdev) 877e3ec7017SPing-Ke Shih { 878e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 879e3ec7017SPing-Ke Shih struct rtw89_hfc_param_ini param_ini = {NULL}; 880e3ec7017SPing-Ke Shih u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 881e3ec7017SPing-Ke Shih 882e3ec7017SPing-Ke Shih switch (rtwdev->hci.type) { 883e3ec7017SPing-Ke Shih case RTW89_HCI_TYPE_PCIE: 884e3ec7017SPing-Ke Shih param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 885e3ec7017SPing-Ke Shih param->en = 0; 886e3ec7017SPing-Ke Shih break; 887e3ec7017SPing-Ke Shih default: 888e3ec7017SPing-Ke Shih return -EINVAL; 889e3ec7017SPing-Ke Shih } 890e3ec7017SPing-Ke Shih 891e3ec7017SPing-Ke Shih if (param_ini.pub_cfg) 892e3ec7017SPing-Ke Shih param->pub_cfg = *param_ini.pub_cfg; 893e3ec7017SPing-Ke Shih 89465a9140eSDmitry Antipov if (param_ini.prec_cfg) 895e3ec7017SPing-Ke Shih param->prec_cfg = *param_ini.prec_cfg; 896e3ec7017SPing-Ke Shih 897e3ec7017SPing-Ke Shih if (param_ini.ch_cfg) 898e3ec7017SPing-Ke Shih param->ch_cfg = param_ini.ch_cfg; 899e3ec7017SPing-Ke Shih 900e3ec7017SPing-Ke Shih memset(¶m->ch_info, 0, sizeof(param->ch_info)); 901e3ec7017SPing-Ke Shih memset(¶m->pub_info, 0, sizeof(param->pub_info)); 902e3ec7017SPing-Ke Shih param->mode = param_ini.mode; 903e3ec7017SPing-Ke Shih 904e3ec7017SPing-Ke Shih return 0; 905e3ec7017SPing-Ke Shih } 906e3ec7017SPing-Ke Shih 907e3ec7017SPing-Ke Shih static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 908e3ec7017SPing-Ke Shih { 909e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 910e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 911e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 912e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 913e3ec7017SPing-Ke Shih 914e3ec7017SPing-Ke Shih if (ch >= RTW89_DMA_CH_NUM) 915e3ec7017SPing-Ke Shih return -EINVAL; 916e3ec7017SPing-Ke Shih 917e3ec7017SPing-Ke Shih if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 918e3ec7017SPing-Ke Shih ch_cfg[ch].max > pub_cfg->pub_max) 919e3ec7017SPing-Ke Shih return -EINVAL; 920e3ec7017SPing-Ke Shih if (ch_cfg[ch].grp >= grp_num) 921e3ec7017SPing-Ke Shih return -EINVAL; 922e3ec7017SPing-Ke Shih 923e3ec7017SPing-Ke Shih return 0; 924e3ec7017SPing-Ke Shih } 925e3ec7017SPing-Ke Shih 926e3ec7017SPing-Ke Shih static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 927e3ec7017SPing-Ke Shih { 928e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 929e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 930e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 931e3ec7017SPing-Ke Shih 932e3ec7017SPing-Ke Shih if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 933e3ec7017SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852A) 934e3ec7017SPing-Ke Shih return 0; 935e3ec7017SPing-Ke Shih else 936e3ec7017SPing-Ke Shih return -EFAULT; 937e3ec7017SPing-Ke Shih } 938e3ec7017SPing-Ke Shih 939e3ec7017SPing-Ke Shih return 0; 940e3ec7017SPing-Ke Shih } 941e3ec7017SPing-Ke Shih 942e3ec7017SPing-Ke Shih static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 943e3ec7017SPing-Ke Shih { 944e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 945e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 946e3ec7017SPing-Ke Shih 947e3ec7017SPing-Ke Shih if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 948c6477cb2SKevin Lo return -EFAULT; 949e3ec7017SPing-Ke Shih 950e3ec7017SPing-Ke Shih return 0; 951e3ec7017SPing-Ke Shih } 952e3ec7017SPing-Ke Shih 953e3ec7017SPing-Ke Shih static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 954e3ec7017SPing-Ke Shih { 955ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 956ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 957e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 958e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 959e3ec7017SPing-Ke Shih int ret = 0; 960e3ec7017SPing-Ke Shih u32 val = 0; 961e3ec7017SPing-Ke Shih 962e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 963e3ec7017SPing-Ke Shih if (ret) 964e3ec7017SPing-Ke Shih return ret; 965e3ec7017SPing-Ke Shih 966e3ec7017SPing-Ke Shih ret = hfc_ch_cfg_chk(rtwdev, ch); 967e3ec7017SPing-Ke Shih if (ret) 968e3ec7017SPing-Ke Shih return ret; 969e3ec7017SPing-Ke Shih 970e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_B1HI) 971e3ec7017SPing-Ke Shih return -EINVAL; 972e3ec7017SPing-Ke Shih 973e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 974e3ec7017SPing-Ke Shih u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 975e3ec7017SPing-Ke Shih (cfg[ch].grp ? B_AX_GRP : 0); 976ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 977e3ec7017SPing-Ke Shih 978e3ec7017SPing-Ke Shih return 0; 979e3ec7017SPing-Ke Shih } 980e3ec7017SPing-Ke Shih 981e3ec7017SPing-Ke Shih static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 982e3ec7017SPing-Ke Shih { 983ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 984ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 985e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 986e3ec7017SPing-Ke Shih struct rtw89_hfc_ch_info *info = param->ch_info; 987e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 988e3ec7017SPing-Ke Shih u32 val; 989e3ec7017SPing-Ke Shih u32 ret; 990e3ec7017SPing-Ke Shih 991e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 992e3ec7017SPing-Ke Shih if (ret) 993e3ec7017SPing-Ke Shih return ret; 994e3ec7017SPing-Ke Shih 995e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_H2C) 996e3ec7017SPing-Ke Shih return -EINVAL; 997e3ec7017SPing-Ke Shih 998ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 999e3ec7017SPing-Ke Shih info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1000e3ec7017SPing-Ke Shih if (ch < RTW89_DMA_H2C) 1001e3ec7017SPing-Ke Shih info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1002e3ec7017SPing-Ke Shih else 1003e3ec7017SPing-Ke Shih info[ch].used = cfg[ch].min - info[ch].aval; 1004e3ec7017SPing-Ke Shih 1005e3ec7017SPing-Ke Shih return 0; 1006e3ec7017SPing-Ke Shih } 1007e3ec7017SPing-Ke Shih 1008e3ec7017SPing-Ke Shih static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1009e3ec7017SPing-Ke Shih { 1010ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1011ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 1012e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1013e3ec7017SPing-Ke Shih u32 val; 1014e3ec7017SPing-Ke Shih int ret; 1015e3ec7017SPing-Ke Shih 1016e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1017e3ec7017SPing-Ke Shih if (ret) 1018e3ec7017SPing-Ke Shih return ret; 1019e3ec7017SPing-Ke Shih 1020e3ec7017SPing-Ke Shih ret = hfc_pub_cfg_chk(rtwdev); 1021e3ec7017SPing-Ke Shih if (ret) 1022e3ec7017SPing-Ke Shih return ret; 1023e3ec7017SPing-Ke Shih 1024e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1025e3ec7017SPing-Ke Shih u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1026ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1027e3ec7017SPing-Ke Shih 1028e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1029ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1030e3ec7017SPing-Ke Shih 1031e3ec7017SPing-Ke Shih return 0; 1032e3ec7017SPing-Ke Shih } 1033e3ec7017SPing-Ke Shih 103439e9b569SPing-Ke Shih static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1035e3ec7017SPing-Ke Shih { 1036ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1037ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 1038e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1039e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1040e3ec7017SPing-Ke Shih struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1041e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1042e3ec7017SPing-Ke Shih u32 val; 1043e3ec7017SPing-Ke Shih 1044ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_info1); 1045e3ec7017SPing-Ke Shih info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1046e3ec7017SPing-Ke Shih info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1047ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_info3); 1048e3ec7017SPing-Ke Shih info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1049e3ec7017SPing-Ke Shih info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1050e3ec7017SPing-Ke Shih info->pub_aval = 1051ab8a5671SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1052e3ec7017SPing-Ke Shih B_AX_PUB_AVAL_PG_MASK); 1053e3ec7017SPing-Ke Shih info->wp_aval = 1054ab8a5671SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1055e3ec7017SPing-Ke Shih B_AX_WP_AVAL_PG_MASK); 1056e3ec7017SPing-Ke Shih 1057ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1058e3ec7017SPing-Ke Shih param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1059e3ec7017SPing-Ke Shih param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1060e3ec7017SPing-Ke Shih param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1061e3ec7017SPing-Ke Shih prec_cfg->ch011_full_cond = 1062e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1063e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond = 1064e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1065e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_full_cond = 1066e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1067e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_full_cond = 1068e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1069e3ec7017SPing-Ke Shih 1070ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1071e3ec7017SPing-Ke Shih prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1072e3ec7017SPing-Ke Shih prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1073e3ec7017SPing-Ke Shih 1074ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1075e3ec7017SPing-Ke Shih pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1076e3ec7017SPing-Ke Shih 1077ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1078e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1079e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1080e3ec7017SPing-Ke Shih 1081ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1082e3ec7017SPing-Ke Shih pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1083e3ec7017SPing-Ke Shih 1084ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1085e3ec7017SPing-Ke Shih pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1086e3ec7017SPing-Ke Shih pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 10870d16d8fbSPing-Ke Shih } 10880d16d8fbSPing-Ke Shih 10890d16d8fbSPing-Ke Shih static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 10900d16d8fbSPing-Ke Shih { 109139e9b569SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 10920d16d8fbSPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 10930d16d8fbSPing-Ke Shih int ret; 10940d16d8fbSPing-Ke Shih 10950d16d8fbSPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 10960d16d8fbSPing-Ke Shih if (ret) 10970d16d8fbSPing-Ke Shih return ret; 10980d16d8fbSPing-Ke Shih 109939e9b569SPing-Ke Shih mac->hfc_get_mix_info(rtwdev); 1100e3ec7017SPing-Ke Shih 1101e3ec7017SPing-Ke Shih ret = hfc_pub_info_chk(rtwdev); 1102e3ec7017SPing-Ke Shih if (param->en && ret) 1103e3ec7017SPing-Ke Shih return ret; 1104e3ec7017SPing-Ke Shih 1105e3ec7017SPing-Ke Shih return 0; 1106e3ec7017SPing-Ke Shih } 1107e3ec7017SPing-Ke Shih 110839e9b569SPing-Ke Shih static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1109e3ec7017SPing-Ke Shih { 1110ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1111ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 1112e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1113e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1114e3ec7017SPing-Ke Shih u32 val; 1115e3ec7017SPing-Ke Shih 1116e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1117ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1118e3ec7017SPing-Ke Shih 1119ab8a5671SPing-Ke Shih rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1120e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK, 1121e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond); 1122e3ec7017SPing-Ke Shih } 1123e3ec7017SPing-Ke Shih 112439e9b569SPing-Ke Shih static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1125e3ec7017SPing-Ke Shih { 1126ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1127ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 1128e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1129e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1130e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1131e3ec7017SPing-Ke Shih u32 val; 1132e3ec7017SPing-Ke Shih 1133e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1134e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1135ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1136e3ec7017SPing-Ke Shih 1137e3ec7017SPing-Ke Shih val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1138ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1139e3ec7017SPing-Ke Shih 1140e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1141e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH07_MASK) | 1142e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->wp_ch811_prec, 1143e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH811_MASK); 1144ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1145e3ec7017SPing-Ke Shih 1146ab8a5671SPing-Ke Shih val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1147e3ec7017SPing-Ke Shih param->mode, B_AX_HCI_FC_MODE_MASK); 1148e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1149e3ec7017SPing-Ke Shih B_AX_HCI_FC_WD_FULL_COND_MASK); 1150e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1151e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK); 1152e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1153e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1154e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1155e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1156ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1157e3ec7017SPing-Ke Shih } 1158e3ec7017SPing-Ke Shih 115939e9b569SPing-Ke Shih static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1160e3ec7017SPing-Ke Shih { 1161ab8a5671SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1162ab8a5671SPing-Ke Shih const struct rtw89_page_regs *regs = chip->page_regs; 1163e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1164e3ec7017SPing-Ke Shih u32 val; 1165e3ec7017SPing-Ke Shih 1166ab8a5671SPing-Ke Shih val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1167e3ec7017SPing-Ke Shih param->en = en; 1168e3ec7017SPing-Ke Shih param->h2c_en = h2c_en; 1169e3ec7017SPing-Ke Shih val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1170e3ec7017SPing-Ke Shih val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1171e3ec7017SPing-Ke Shih (val & ~B_AX_HCI_FC_CH12_EN); 1172ab8a5671SPing-Ke Shih rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1173e3ec7017SPing-Ke Shih } 1174e3ec7017SPing-Ke Shih 1175fc663fa0SPing-Ke Shih int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1176e3ec7017SPing-Ke Shih { 117739e9b569SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1178a1b7163aSPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1179a1b7163aSPing-Ke Shih u32 dma_ch_mask = chip->dma_ch_mask; 1180e3ec7017SPing-Ke Shih u8 ch; 1181e3ec7017SPing-Ke Shih u32 ret = 0; 1182e3ec7017SPing-Ke Shih 1183e3ec7017SPing-Ke Shih if (reset) 1184e3ec7017SPing-Ke Shih ret = hfc_reset_param(rtwdev); 1185e3ec7017SPing-Ke Shih if (ret) 1186e3ec7017SPing-Ke Shih return ret; 1187e3ec7017SPing-Ke Shih 1188e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1189e3ec7017SPing-Ke Shih if (ret) 1190e3ec7017SPing-Ke Shih return ret; 1191e3ec7017SPing-Ke Shih 119239e9b569SPing-Ke Shih mac->hfc_func_en(rtwdev, false, false); 1193e3ec7017SPing-Ke Shih 1194e3ec7017SPing-Ke Shih if (!en && h2c_en) { 119539e9b569SPing-Ke Shih mac->hfc_h2c_cfg(rtwdev); 119639e9b569SPing-Ke Shih mac->hfc_func_en(rtwdev, en, h2c_en); 1197e3ec7017SPing-Ke Shih return ret; 1198e3ec7017SPing-Ke Shih } 1199e3ec7017SPing-Ke Shih 1200e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1201a1b7163aSPing-Ke Shih if (dma_ch_mask & BIT(ch)) 1202a1b7163aSPing-Ke Shih continue; 1203e3ec7017SPing-Ke Shih ret = hfc_ch_ctrl(rtwdev, ch); 1204e3ec7017SPing-Ke Shih if (ret) 1205e3ec7017SPing-Ke Shih return ret; 1206e3ec7017SPing-Ke Shih } 1207e3ec7017SPing-Ke Shih 1208e3ec7017SPing-Ke Shih ret = hfc_pub_ctrl(rtwdev); 1209e3ec7017SPing-Ke Shih if (ret) 1210e3ec7017SPing-Ke Shih return ret; 1211e3ec7017SPing-Ke Shih 121239e9b569SPing-Ke Shih mac->hfc_mix_cfg(rtwdev); 1213e3ec7017SPing-Ke Shih if (en || h2c_en) { 121439e9b569SPing-Ke Shih mac->hfc_func_en(rtwdev, en, h2c_en); 1215e3ec7017SPing-Ke Shih udelay(10); 1216e3ec7017SPing-Ke Shih } 1217e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1218a1b7163aSPing-Ke Shih if (dma_ch_mask & BIT(ch)) 1219a1b7163aSPing-Ke Shih continue; 1220e3ec7017SPing-Ke Shih ret = hfc_upd_ch_info(rtwdev, ch); 1221e3ec7017SPing-Ke Shih if (ret) 1222e3ec7017SPing-Ke Shih return ret; 1223e3ec7017SPing-Ke Shih } 1224e3ec7017SPing-Ke Shih ret = hfc_upd_mix_info(rtwdev); 1225e3ec7017SPing-Ke Shih 1226e3ec7017SPing-Ke Shih return ret; 1227e3ec7017SPing-Ke Shih } 1228e3ec7017SPing-Ke Shih 1229e3ec7017SPing-Ke Shih #define PWR_POLL_CNT 2000 1230e3ec7017SPing-Ke Shih static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1231e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cfg) 1232e3ec7017SPing-Ke Shih { 1233e3ec7017SPing-Ke Shih u8 val = 0; 1234e3ec7017SPing-Ke Shih int ret; 1235e3ec7017SPing-Ke Shih u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1236e3ec7017SPing-Ke Shih cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1237e3ec7017SPing-Ke Shih 1238e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1239e3ec7017SPing-Ke Shih 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1240e3ec7017SPing-Ke Shih 1241e3ec7017SPing-Ke Shih if (!ret) 1242e3ec7017SPing-Ke Shih return 0; 1243e3ec7017SPing-Ke Shih 1244e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1245e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1246e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1247e3ec7017SPing-Ke Shih 1248e3ec7017SPing-Ke Shih return -EBUSY; 1249e3ec7017SPing-Ke Shih } 1250e3ec7017SPing-Ke Shih 1251e3ec7017SPing-Ke Shih static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1252e3ec7017SPing-Ke Shih u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1253e3ec7017SPing-Ke Shih { 1254e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cur_cfg; 1255e3ec7017SPing-Ke Shih u32 addr; 1256e3ec7017SPing-Ke Shih u8 val; 1257e3ec7017SPing-Ke Shih 1258e3ec7017SPing-Ke Shih for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1259e3ec7017SPing-Ke Shih if (!(cur_cfg->intf_msk & intf_msk) || 1260e3ec7017SPing-Ke Shih !(cur_cfg->cv_msk & cv_msk)) 1261e3ec7017SPing-Ke Shih continue; 1262e3ec7017SPing-Ke Shih 1263e3ec7017SPing-Ke Shih switch (cur_cfg->cmd) { 1264e3ec7017SPing-Ke Shih case PWR_CMD_WRITE: 1265e3ec7017SPing-Ke Shih addr = cur_cfg->addr; 1266e3ec7017SPing-Ke Shih 1267e3ec7017SPing-Ke Shih if (cur_cfg->base == PWR_BASE_SDIO) 1268e3ec7017SPing-Ke Shih addr |= SDIO_LOCAL_BASE_ADDR; 1269e3ec7017SPing-Ke Shih 1270e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, addr); 1271e3ec7017SPing-Ke Shih val &= ~(cur_cfg->msk); 1272e3ec7017SPing-Ke Shih val |= (cur_cfg->val & cur_cfg->msk); 1273e3ec7017SPing-Ke Shih 1274e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, addr, val); 1275e3ec7017SPing-Ke Shih break; 1276e3ec7017SPing-Ke Shih case PWR_CMD_POLL: 1277e3ec7017SPing-Ke Shih if (pwr_cmd_poll(rtwdev, cur_cfg)) 1278e3ec7017SPing-Ke Shih return -EBUSY; 1279e3ec7017SPing-Ke Shih break; 1280e3ec7017SPing-Ke Shih case PWR_CMD_DELAY: 1281e3ec7017SPing-Ke Shih if (cur_cfg->val == PWR_DELAY_US) 1282e3ec7017SPing-Ke Shih udelay(cur_cfg->addr); 1283e3ec7017SPing-Ke Shih else 1284e3ec7017SPing-Ke Shih fsleep(cur_cfg->addr * 1000); 1285e3ec7017SPing-Ke Shih break; 1286e3ec7017SPing-Ke Shih default: 1287e3ec7017SPing-Ke Shih return -EINVAL; 1288e3ec7017SPing-Ke Shih } 1289e3ec7017SPing-Ke Shih } 1290e3ec7017SPing-Ke Shih 1291e3ec7017SPing-Ke Shih return 0; 1292e3ec7017SPing-Ke Shih } 1293e3ec7017SPing-Ke Shih 1294e3ec7017SPing-Ke Shih static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1295e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq) 1296e3ec7017SPing-Ke Shih { 1297e3ec7017SPing-Ke Shih int ret; 1298e3ec7017SPing-Ke Shih 1299e3ec7017SPing-Ke Shih for (; *cfg_seq; cfg_seq++) { 1300e3ec7017SPing-Ke Shih ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1301e3ec7017SPing-Ke Shih PWR_INTF_MSK_PCIE, *cfg_seq); 1302e3ec7017SPing-Ke Shih if (ret) 1303e3ec7017SPing-Ke Shih return -EBUSY; 1304e3ec7017SPing-Ke Shih } 1305e3ec7017SPing-Ke Shih 1306e3ec7017SPing-Ke Shih return 0; 1307e3ec7017SPing-Ke Shih } 1308e3ec7017SPing-Ke Shih 1309e3ec7017SPing-Ke Shih static enum rtw89_rpwm_req_pwr_state 1310e3ec7017SPing-Ke Shih rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1311e3ec7017SPing-Ke Shih { 1312e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 1313e3ec7017SPing-Ke Shih 1314e3ec7017SPing-Ke Shih switch (rtwdev->ps_mode) { 1315e3ec7017SPing-Ke Shih case RTW89_PS_MODE_RFOFF: 1316e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1317e3ec7017SPing-Ke Shih break; 1318e3ec7017SPing-Ke Shih case RTW89_PS_MODE_CLK_GATED: 1319e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1320e3ec7017SPing-Ke Shih break; 1321e3ec7017SPing-Ke Shih case RTW89_PS_MODE_PWR_GATED: 1322e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1323e3ec7017SPing-Ke Shih break; 1324e3ec7017SPing-Ke Shih default: 1325e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1326e3ec7017SPing-Ke Shih break; 1327e3ec7017SPing-Ke Shih } 1328e3ec7017SPing-Ke Shih return state; 1329e3ec7017SPing-Ke Shih } 1330e3ec7017SPing-Ke Shih 1331e3ec7017SPing-Ke Shih static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 13327bfd05ffSChin-Yen Lee enum rtw89_rpwm_req_pwr_state req_pwr_state, 13337bfd05ffSChin-Yen Lee bool notify_wake) 1334e3ec7017SPing-Ke Shih { 1335e3ec7017SPing-Ke Shih u16 request; 1336e3ec7017SPing-Ke Shih 13377bfd05ffSChin-Yen Lee spin_lock_bh(&rtwdev->rpwm_lock); 13387bfd05ffSChin-Yen Lee 1339e3ec7017SPing-Ke Shih request = rtw89_read16(rtwdev, R_AX_RPWM); 1340e3ec7017SPing-Ke Shih request ^= request | PS_RPWM_TOGGLE; 13417bfd05ffSChin-Yen Lee request |= req_pwr_state; 1342e3ec7017SPing-Ke Shih 13437bfd05ffSChin-Yen Lee if (notify_wake) { 13447bfd05ffSChin-Yen Lee request |= PS_RPWM_NOTIFY_WAKE; 13457bfd05ffSChin-Yen Lee } else { 1346e3ec7017SPing-Ke Shih rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1347e3ec7017SPing-Ke Shih RPWM_SEQ_NUM_MAX; 13487bfd05ffSChin-Yen Lee request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 13497bfd05ffSChin-Yen Lee rtwdev->mac.rpwm_seq_num); 1350e3ec7017SPing-Ke Shih 1351e3ec7017SPing-Ke Shih if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1352e3ec7017SPing-Ke Shih request |= PS_RPWM_ACK; 13537bfd05ffSChin-Yen Lee } 1354e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 13557bfd05ffSChin-Yen Lee 13567bfd05ffSChin-Yen Lee spin_unlock_bh(&rtwdev->rpwm_lock); 1357e3ec7017SPing-Ke Shih } 1358e3ec7017SPing-Ke Shih 1359e3ec7017SPing-Ke Shih static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1360e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state req_pwr_state) 1361e3ec7017SPing-Ke Shih { 1362e3ec7017SPing-Ke Shih bool request_deep_mode; 1363e3ec7017SPing-Ke Shih bool in_deep_mode; 1364e3ec7017SPing-Ke Shih u8 rpwm_req_num; 1365e3ec7017SPing-Ke Shih u8 cpwm_rsp_seq; 1366e3ec7017SPing-Ke Shih u8 cpwm_seq; 1367e3ec7017SPing-Ke Shih u8 cpwm_status; 1368e3ec7017SPing-Ke Shih 1369e3ec7017SPing-Ke Shih if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1370e3ec7017SPing-Ke Shih request_deep_mode = true; 1371e3ec7017SPing-Ke Shih else 1372e3ec7017SPing-Ke Shih request_deep_mode = false; 1373e3ec7017SPing-Ke Shih 1374e3ec7017SPing-Ke Shih if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1375e3ec7017SPing-Ke Shih in_deep_mode = true; 1376e3ec7017SPing-Ke Shih else 1377e3ec7017SPing-Ke Shih in_deep_mode = false; 1378e3ec7017SPing-Ke Shih 1379e3ec7017SPing-Ke Shih if (request_deep_mode != in_deep_mode) 1380e3ec7017SPing-Ke Shih return -EPERM; 1381e3ec7017SPing-Ke Shih 1382e3ec7017SPing-Ke Shih if (request_deep_mode) 1383e3ec7017SPing-Ke Shih return 0; 1384e3ec7017SPing-Ke Shih 1385e3ec7017SPing-Ke Shih rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1386e1757e80SPing-Ke Shih cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1387e3ec7017SPing-Ke Shih PS_CPWM_RSP_SEQ_NUM); 1388e3ec7017SPing-Ke Shih 1389e3ec7017SPing-Ke Shih if (rpwm_req_num != cpwm_rsp_seq) 1390e3ec7017SPing-Ke Shih return -EPERM; 1391e3ec7017SPing-Ke Shih 1392e3ec7017SPing-Ke Shih rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1393e3ec7017SPing-Ke Shih CPWM_SEQ_NUM_MAX; 1394e3ec7017SPing-Ke Shih 1395e1757e80SPing-Ke Shih cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1396e3ec7017SPing-Ke Shih if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1397e3ec7017SPing-Ke Shih return -EPERM; 1398e3ec7017SPing-Ke Shih 1399e1757e80SPing-Ke Shih cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1400e3ec7017SPing-Ke Shih if (cpwm_status != req_pwr_state) 1401e3ec7017SPing-Ke Shih return -EPERM; 1402e3ec7017SPing-Ke Shih 1403e3ec7017SPing-Ke Shih return 0; 1404e3ec7017SPing-Ke Shih } 1405e3ec7017SPing-Ke Shih 1406e3ec7017SPing-Ke Shih void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1407e3ec7017SPing-Ke Shih { 1408e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 140939a76521SPing-Ke Shih unsigned long delay = enter ? 10 : 150; 1410e3ec7017SPing-Ke Shih int ret; 141148c0e347SChin-Yen Lee int i; 1412e3ec7017SPing-Ke Shih 1413e3ec7017SPing-Ke Shih if (enter) 1414e3ec7017SPing-Ke Shih state = rtw89_mac_get_req_pwr_state(rtwdev); 1415e3ec7017SPing-Ke Shih else 1416e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1417e3ec7017SPing-Ke Shih 141848c0e347SChin-Yen Lee for (i = 0; i < RPWM_TRY_CNT; i++) { 14197bfd05ffSChin-Yen Lee rtw89_mac_send_rpwm(rtwdev, state, false); 142048c0e347SChin-Yen Lee ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 142148c0e347SChin-Yen Lee !ret, delay, 15000, false, 142248c0e347SChin-Yen Lee rtwdev, state); 142348c0e347SChin-Yen Lee if (!ret) 142448c0e347SChin-Yen Lee break; 142548c0e347SChin-Yen Lee 142648c0e347SChin-Yen Lee if (i == RPWM_TRY_CNT - 1) 1427e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1428e3ec7017SPing-Ke Shih enter ? "entering" : "leaving"); 142948c0e347SChin-Yen Lee else 143048c0e347SChin-Yen Lee rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 143148c0e347SChin-Yen Lee "%d time firmware failed to ack for %s ps mode\n", 143248c0e347SChin-Yen Lee i + 1, enter ? "entering" : "leaving"); 143348c0e347SChin-Yen Lee } 1434e3ec7017SPing-Ke Shih } 1435e3ec7017SPing-Ke Shih 14367bfd05ffSChin-Yen Lee void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 14377bfd05ffSChin-Yen Lee { 14387bfd05ffSChin-Yen Lee enum rtw89_rpwm_req_pwr_state state; 14397bfd05ffSChin-Yen Lee 14407bfd05ffSChin-Yen Lee state = rtw89_mac_get_req_pwr_state(rtwdev); 14417bfd05ffSChin-Yen Lee rtw89_mac_send_rpwm(rtwdev, state, true); 14427bfd05ffSChin-Yen Lee } 14437bfd05ffSChin-Yen Lee 1444e3ec7017SPing-Ke Shih static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1445e3ec7017SPing-Ke Shih { 1446e3ec7017SPing-Ke Shih #define PWR_ACT 1 1447e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1448e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq; 14492a7e54dbSPing-Ke Shih int (*cfg_func)(struct rtw89_dev *rtwdev); 1450e3ec7017SPing-Ke Shih int ret; 1451e3ec7017SPing-Ke Shih u8 val; 1452e3ec7017SPing-Ke Shih 14532a7e54dbSPing-Ke Shih if (on) { 1454e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_on_seq; 14552a7e54dbSPing-Ke Shih cfg_func = chip->ops->pwr_on_func; 14562a7e54dbSPing-Ke Shih } else { 1457e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_off_seq; 14582a7e54dbSPing-Ke Shih cfg_func = chip->ops->pwr_off_func; 14592a7e54dbSPing-Ke Shih } 1460e3ec7017SPing-Ke Shih 1461e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1462e3ec7017SPing-Ke Shih __rtw89_leave_ps_mode(rtwdev); 1463e3ec7017SPing-Ke Shih 1464e3ec7017SPing-Ke Shih val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1465e3ec7017SPing-Ke Shih if (on && val == PWR_ACT) { 1466e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC has already powered on\n"); 1467e3ec7017SPing-Ke Shih return -EBUSY; 1468e3ec7017SPing-Ke Shih } 1469e3ec7017SPing-Ke Shih 14702a7e54dbSPing-Ke Shih ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1471e3ec7017SPing-Ke Shih if (ret) 1472e3ec7017SPing-Ke Shih return ret; 1473e3ec7017SPing-Ke Shih 1474e3ec7017SPing-Ke Shih if (on) { 1475e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1476cfb99433SPing-Ke Shih set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1477cfb99433SPing-Ke Shih set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1478e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1479e3ec7017SPing-Ke Shih } else { 1480e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1481cfb99433SPing-Ke Shih clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1482cfb99433SPing-Ke Shih clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1483cfb99433SPing-Ke Shih clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1484e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1485e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1486967439c7SZong-Zhe Yang rtw89_set_entity_state(rtwdev, false); 1487e3ec7017SPing-Ke Shih } 1488e3ec7017SPing-Ke Shih 1489e3ec7017SPing-Ke Shih return 0; 1490e3ec7017SPing-Ke Shih #undef PWR_ACT 1491e3ec7017SPing-Ke Shih } 1492e3ec7017SPing-Ke Shih 1493e3ec7017SPing-Ke Shih void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1494e3ec7017SPing-Ke Shih { 1495e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 1496e3ec7017SPing-Ke Shih } 1497e3ec7017SPing-Ke Shih 1498fc663fa0SPing-Ke Shih static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1499e3ec7017SPing-Ke Shih { 1500e3ec7017SPing-Ke Shih u32 func_en = 0; 1501e3ec7017SPing-Ke Shih u32 ck_en = 0; 1502e3ec7017SPing-Ke Shih u32 c1pc_en = 0; 1503e3ec7017SPing-Ke Shih u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1504e3ec7017SPing-Ke Shih u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1505e3ec7017SPing-Ke Shih 1506e3ec7017SPing-Ke Shih func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1507e3ec7017SPing-Ke Shih B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 15085cb5562dSPing-Ke Shih B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 15095cb5562dSPing-Ke Shih B_AX_CMAC_CRPRT; 1510e3ec7017SPing-Ke Shih ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1511e3ec7017SPing-Ke Shih B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1512e3ec7017SPing-Ke Shih B_AX_RMAC_CKEN; 1513e3ec7017SPing-Ke Shih c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1514e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1515e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1516e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1517e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1518e3ec7017SPing-Ke Shih 1519e3ec7017SPing-Ke Shih if (en) { 1520e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1521e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1522e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1523e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1524e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1525e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1526e3ec7017SPing-Ke Shih } 1527e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1528e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1529e3ec7017SPing-Ke Shih } else { 1530e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1531e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1532e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1533e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1534e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1535e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1536e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1537e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1538e3ec7017SPing-Ke Shih } 1539e3ec7017SPing-Ke Shih } 1540e3ec7017SPing-Ke Shih 1541e3ec7017SPing-Ke Shih return 0; 1542e3ec7017SPing-Ke Shih } 1543e3ec7017SPing-Ke Shih 1544fc663fa0SPing-Ke Shih static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1545e3ec7017SPing-Ke Shih { 1546828a4396SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1547e3ec7017SPing-Ke Shih u32 val32; 1548e3ec7017SPing-Ke Shih 1549828a4396SChia-Yuan Li if (chip_id == RTL8852C) 1550828a4396SChia-Yuan Li val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1551828a4396SChia-Yuan Li B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1552828a4396SChia-Yuan Li B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1553828a4396SChia-Yuan Li B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1554828a4396SChia-Yuan Li B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1555828a4396SChia-Yuan Li B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1556828a4396SChia-Yuan Li B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1557828a4396SChia-Yuan Li else 1558828a4396SChia-Yuan Li val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1559828a4396SChia-Yuan Li B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1560828a4396SChia-Yuan Li B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1561828a4396SChia-Yuan Li B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1562828a4396SChia-Yuan Li B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1563828a4396SChia-Yuan Li B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1564828a4396SChia-Yuan Li B_AX_DMAC_CRPRT); 1565e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1566e3ec7017SPing-Ke Shih 1567e3ec7017SPing-Ke Shih val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1568e3ec7017SPing-Ke Shih B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1569e3ec7017SPing-Ke Shih B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1570828a4396SChia-Yuan Li B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1571e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1572e3ec7017SPing-Ke Shih 157343863efeSChangcheng Deng return 0; 1574e3ec7017SPing-Ke Shih } 1575e3ec7017SPing-Ke Shih 1576fc663fa0SPing-Ke Shih static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1577e3ec7017SPing-Ke Shih { 1578828a4396SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1579828a4396SChia-Yuan Li 158014b6e9f4SPing-Ke Shih if (chip_id == RTL8852A || chip_id == RTL8852B) 158114b6e9f4SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1582828a4396SChia-Yuan Li B_AX_OCP_L1_MASK); 1583e3ec7017SPing-Ke Shih 1584e3ec7017SPing-Ke Shih return 0; 1585e3ec7017SPing-Ke Shih } 1586e3ec7017SPing-Ke Shih 1587fc663fa0SPing-Ke Shih static int sys_init_ax(struct rtw89_dev *rtwdev) 1588e3ec7017SPing-Ke Shih { 1589e3ec7017SPing-Ke Shih int ret; 1590e3ec7017SPing-Ke Shih 1591fc663fa0SPing-Ke Shih ret = dmac_func_en_ax(rtwdev); 1592e3ec7017SPing-Ke Shih if (ret) 1593e3ec7017SPing-Ke Shih return ret; 1594e3ec7017SPing-Ke Shih 1595fc663fa0SPing-Ke Shih ret = cmac_func_en_ax(rtwdev, 0, true); 1596e3ec7017SPing-Ke Shih if (ret) 1597e3ec7017SPing-Ke Shih return ret; 1598e3ec7017SPing-Ke Shih 1599fc663fa0SPing-Ke Shih ret = chip_func_en_ax(rtwdev); 1600e3ec7017SPing-Ke Shih if (ret) 1601e3ec7017SPing-Ke Shih return ret; 1602e3ec7017SPing-Ke Shih 1603e3ec7017SPing-Ke Shih return ret; 1604e3ec7017SPing-Ke Shih } 1605e3ec7017SPing-Ke Shih 160630645118SPing-Ke Shih const struct rtw89_mac_size_set rtw89_mac_size = { 160730645118SPing-Ke Shih .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1608fdb3bb0aSPing-Ke Shih .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0}, 1609fdb3bb0aSPing-Ke Shih .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0}, 1610e3ec7017SPing-Ke Shih /* PCIE 64 */ 161130645118SPing-Ke Shih .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1612fdb3bb0aSPing-Ke Shih .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1613e3ec7017SPing-Ke Shih /* DLFW */ 161430645118SPing-Ke Shih .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1615fdb3bb0aSPing-Ke Shih .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1616a1cb0971SPing-Ke Shih /* PCIE 64 */ 1617a1cb0971SPing-Ke Shih .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1618c0426c44SPing-Ke Shih /* 8852B PCIE SCC */ 1619c0426c44SPing-Ke Shih .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1620a1cb0971SPing-Ke Shih /* DLFW */ 1621a1cb0971SPing-Ke Shih .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 162279d099e0SPing-Ke Shih /* 8852C DLFW */ 162330645118SPing-Ke Shih .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 162479d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 162530645118SPing-Ke Shih .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1626e3ec7017SPing-Ke Shih /* PCIE */ 162730645118SPing-Ke Shih .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1628fdb3bb0aSPing-Ke Shih .ple_size0_v1 = {RTW89_PLE_PG_128, 2672, 256, 212992,}, 1629fdb3bb0aSPing-Ke Shih .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1630e3ec7017SPing-Ke Shih /* DLFW */ 163130645118SPing-Ke Shih .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1632a1cb0971SPing-Ke Shih /* PCIE 64 */ 1633a1cb0971SPing-Ke Shih .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1634a1cb0971SPing-Ke Shih /* DLFW */ 1635a1cb0971SPing-Ke Shih .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 163679d099e0SPing-Ke Shih /* 8852C DLFW */ 163730645118SPing-Ke Shih .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 163879d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 163930645118SPing-Ke Shih .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1640e3ec7017SPing-Ke Shih /* PCIE 64 */ 164130645118SPing-Ke Shih .wde_qt0 = {3792, 196, 0, 107,}, 1642fdb3bb0aSPing-Ke Shih .wde_qt0_v1 = {3302, 6, 0, 20,}, 1643e3ec7017SPing-Ke Shih /* DLFW */ 164430645118SPing-Ke Shih .wde_qt4 = {0, 0, 0, 0,}, 1645a1cb0971SPing-Ke Shih /* PCIE 64 */ 1646a1cb0971SPing-Ke Shih .wde_qt6 = {448, 48, 0, 16,}, 1647c0426c44SPing-Ke Shih /* 8852B PCIE SCC */ 1648c0426c44SPing-Ke Shih .wde_qt7 = {446, 48, 0, 16,}, 164979d099e0SPing-Ke Shih /* 8852C DLFW */ 165030645118SPing-Ke Shih .wde_qt17 = {0, 0, 0, 0,}, 165179d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 165230645118SPing-Ke Shih .wde_qt18 = {3228, 60, 0, 40,}, 1653fdb3bb0aSPing-Ke Shih .ple_qt0 = {320, 0, 32, 16, 13, 13, 292, 0, 32, 18, 1, 4, 0,}, 1654fdb3bb0aSPing-Ke Shih .ple_qt1 = {320, 0, 32, 16, 1944, 1944, 2223, 0, 1963, 1949, 1, 1935, 0,}, 1655e3ec7017SPing-Ke Shih /* PCIE SCC */ 165630645118SPing-Ke Shih .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1657e3ec7017SPing-Ke Shih /* PCIE SCC */ 165830645118SPing-Ke Shih .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1659fdb3bb0aSPing-Ke Shih .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1660e3ec7017SPing-Ke Shih /* DLFW */ 166130645118SPing-Ke Shih .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1662a1cb0971SPing-Ke Shih /* PCIE 64 */ 1663a1cb0971SPing-Ke Shih .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 166479d099e0SPing-Ke Shih /* DLFW 52C */ 166530645118SPing-Ke Shih .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 166679d099e0SPing-Ke Shih /* DLFW 52C */ 166730645118SPing-Ke Shih .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 166879d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 166930645118SPing-Ke Shih .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 167079d099e0SPing-Ke Shih /* 8852C PCIE SCC */ 167130645118SPing-Ke Shih .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1672a1cb0971SPing-Ke Shih /* PCIE 64 */ 1673a1cb0971SPing-Ke Shih .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 16747a68ec3dSChih-Kang Chang /* 8852A PCIE WOW */ 16757a68ec3dSChih-Kang Chang .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 16766863ad91SChin-Yen Lee /* 8852B PCIE WOW */ 16776863ad91SChin-Yen Lee .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 167885d1539cSPing-Ke Shih /* 8851B PCIE WOW */ 167985d1539cSPing-Ke Shih .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1680fdb3bb0aSPing-Ke Shih .ple_rsvd_qt0 = {2, 112, 56, 6, 6, 6, 6, 0, 0, 62,}, 1681fdb3bb0aSPing-Ke Shih .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1682fdb3bb0aSPing-Ke Shih .rsvd0_size0 = {212992, 0,}, 1683fdb3bb0aSPing-Ke Shih .rsvd1_size0 = {587776, 2048,}, 168479d099e0SPing-Ke Shih }; 168530645118SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_size); 168679d099e0SPing-Ke Shih 1687e3ec7017SPing-Ke Shih static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1688e3ec7017SPing-Ke Shih enum rtw89_qta_mode mode) 1689e3ec7017SPing-Ke Shih { 1690e3ec7017SPing-Ke Shih struct rtw89_mac_info *mac = &rtwdev->mac; 1691e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 1692e3ec7017SPing-Ke Shih 1693e3ec7017SPing-Ke Shih cfg = &rtwdev->chip->dle_mem[mode]; 1694e3ec7017SPing-Ke Shih if (!cfg) 1695e3ec7017SPing-Ke Shih return NULL; 1696e3ec7017SPing-Ke Shih 1697e3ec7017SPing-Ke Shih if (cfg->mode != mode) { 1698e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1699e3ec7017SPing-Ke Shih return NULL; 1700e3ec7017SPing-Ke Shih } 1701e3ec7017SPing-Ke Shih 1702cecf1643SPing-Ke Shih mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1703e3ec7017SPing-Ke Shih mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1704cecf1643SPing-Ke Shih mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1705e3ec7017SPing-Ke Shih mac->dle_info.qta_mode = mode; 1706e3ec7017SPing-Ke Shih mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1707e3ec7017SPing-Ke Shih mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1708e3ec7017SPing-Ke Shih 1709e3ec7017SPing-Ke Shih return cfg; 1710e3ec7017SPing-Ke Shih } 1711e3ec7017SPing-Ke Shih 1712cecf1643SPing-Ke Shih int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1713cecf1643SPing-Ke Shih enum rtw89_mac_dle_rsvd_qt_type type, 1714cecf1643SPing-Ke Shih struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1715cecf1643SPing-Ke Shih { 1716cecf1643SPing-Ke Shih struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1717cecf1643SPing-Ke Shih const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1718cecf1643SPing-Ke Shih 1719cecf1643SPing-Ke Shih switch (type) { 1720cecf1643SPing-Ke Shih case DLE_RSVD_QT_MPDU_INFO: 1721cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg; 1722cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1723cecf1643SPing-Ke Shih break; 1724cecf1643SPing-Ke Shih case DLE_RSVD_QT_B0_CSI: 1725cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1726cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->b0_csi; 1727cecf1643SPing-Ke Shih break; 1728cecf1643SPing-Ke Shih case DLE_RSVD_QT_B1_CSI: 1729cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg + 1730cecf1643SPing-Ke Shih rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1731cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->b1_csi; 1732cecf1643SPing-Ke Shih break; 1733cecf1643SPing-Ke Shih case DLE_RSVD_QT_B0_LMR: 1734cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg + 1735cecf1643SPing-Ke Shih rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1736cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->b0_lmr; 1737cecf1643SPing-Ke Shih break; 1738cecf1643SPing-Ke Shih case DLE_RSVD_QT_B1_LMR: 1739cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg + 1740cecf1643SPing-Ke Shih rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1741cecf1643SPing-Ke Shih rsvd_qt->b0_lmr; 1742cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->b1_lmr; 1743cecf1643SPing-Ke Shih break; 1744cecf1643SPing-Ke Shih case DLE_RSVD_QT_B0_FTM: 1745cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg + 1746cecf1643SPing-Ke Shih rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1747cecf1643SPing-Ke Shih rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1748cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->b0_ftm; 1749cecf1643SPing-Ke Shih break; 1750cecf1643SPing-Ke Shih case DLE_RSVD_QT_B1_FTM: 1751cecf1643SPing-Ke Shih cfg->pktid = dle_info->ple_free_pg + 1752cecf1643SPing-Ke Shih rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1753cecf1643SPing-Ke Shih rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1754cecf1643SPing-Ke Shih cfg->pg_num = rsvd_qt->b1_ftm; 1755cecf1643SPing-Ke Shih break; 1756cecf1643SPing-Ke Shih default: 1757cecf1643SPing-Ke Shih return -EINVAL; 1758cecf1643SPing-Ke Shih } 1759cecf1643SPing-Ke Shih 1760cecf1643SPing-Ke Shih cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1761cecf1643SPing-Ke Shih 1762cecf1643SPing-Ke Shih return 0; 1763cecf1643SPing-Ke Shih } 1764cecf1643SPing-Ke Shih 176527ea6be9SZong-Zhe Yang static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 176641d56769SChih-Kang Chang { 176741d56769SChih-Kang Chang struct rtw89_mac_dle_dfi_qempty qempty; 17682706cb25SZong-Zhe Yang u32 grpnum, qtmp, val32, msk32; 176941d56769SChih-Kang Chang int i, j, ret; 177041d56769SChih-Kang Chang 17712706cb25SZong-Zhe Yang grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 177241d56769SChih-Kang Chang qempty.dle_type = DLE_CTRL_TYPE_WDE; 177341d56769SChih-Kang Chang 17742706cb25SZong-Zhe Yang for (i = 0; i < grpnum; i++) { 177541d56769SChih-Kang Chang qempty.grpsel = i; 177627ea6be9SZong-Zhe Yang ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 177741d56769SChih-Kang Chang if (ret) { 177841d56769SChih-Kang Chang rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 177941d56769SChih-Kang Chang return false; 178041d56769SChih-Kang Chang } 178141d56769SChih-Kang Chang qtmp = qempty.qempty; 178241d56769SChih-Kang Chang for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 17836f8d3655SChia-Yuan Li val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 178441d56769SChih-Kang Chang if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 178541d56769SChih-Kang Chang return false; 178641d56769SChih-Kang Chang qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 178741d56769SChih-Kang Chang } 178841d56769SChih-Kang Chang } 178941d56769SChih-Kang Chang 17902706cb25SZong-Zhe Yang qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 179127ea6be9SZong-Zhe Yang ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 179241d56769SChih-Kang Chang if (ret) { 179341d56769SChih-Kang Chang rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 179441d56769SChih-Kang Chang return false; 179541d56769SChih-Kang Chang } 179641d56769SChih-Kang Chang msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 179741d56769SChih-Kang Chang if ((qempty.qempty & msk32) != msk32) 179841d56769SChih-Kang Chang return false; 179941d56769SChih-Kang Chang 180041d56769SChih-Kang Chang if (rtwdev->dbcc_en) { 180141d56769SChih-Kang Chang msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 180241d56769SChih-Kang Chang if ((qempty.qempty & msk32) != msk32) 180341d56769SChih-Kang Chang return false; 180441d56769SChih-Kang Chang } 180541d56769SChih-Kang Chang 180641d56769SChih-Kang Chang msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 180741d56769SChih-Kang Chang B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 180841d56769SChih-Kang Chang B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 180941d56769SChih-Kang Chang B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 181041d56769SChih-Kang Chang B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 181141d56769SChih-Kang Chang B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 181241d56769SChih-Kang Chang B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 181341d56769SChih-Kang Chang B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 181441d56769SChih-Kang Chang val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 181541d56769SChih-Kang Chang 181641d56769SChih-Kang Chang return (val32 & msk32) == msk32; 181741d56769SChih-Kang Chang } 181841d56769SChih-Kang Chang 1819aabe741eSPing-Ke Shih static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1820e3ec7017SPing-Ke Shih { 1821aabe741eSPing-Ke Shih const struct rtw89_dle_size *wde = cfg->wde_size; 1822aabe741eSPing-Ke Shih const struct rtw89_dle_size *ple = cfg->ple_size; 1823aabe741eSPing-Ke Shih u32 used; 1824aabe741eSPing-Ke Shih 1825aabe741eSPing-Ke Shih used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1826e3ec7017SPing-Ke Shih ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1827aabe741eSPing-Ke Shih 1828aabe741eSPing-Ke Shih if (cfg->rsvd0_size && cfg->rsvd1_size) { 1829aabe741eSPing-Ke Shih used += cfg->rsvd0_size->size; 1830aabe741eSPing-Ke Shih used += cfg->rsvd1_size->size; 1831aabe741eSPing-Ke Shih } 1832aabe741eSPing-Ke Shih 1833aabe741eSPing-Ke Shih return used; 1834e3ec7017SPing-Ke Shih } 1835e3ec7017SPing-Ke Shih 18365f8c35b9SPing-Ke Shih static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 18375f8c35b9SPing-Ke Shih enum rtw89_qta_mode mode) 18385f8c35b9SPing-Ke Shih { 18395f8c35b9SPing-Ke Shih u32 size = rtwdev->chip->fifo_size; 18405f8c35b9SPing-Ke Shih 18415f8c35b9SPing-Ke Shih if (mode == RTW89_QTA_SCC) 18425f8c35b9SPing-Ke Shih size -= rtwdev->chip->dle_scc_rsvd_size; 18435f8c35b9SPing-Ke Shih 18445f8c35b9SPing-Ke Shih return size; 18455f8c35b9SPing-Ke Shih } 18465f8c35b9SPing-Ke Shih 184739e9b569SPing-Ke Shih static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 1848e3ec7017SPing-Ke Shih { 1849e3ec7017SPing-Ke Shih if (enable) 1850e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1851e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1852e3ec7017SPing-Ke Shih else 1853e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1854e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1855e3ec7017SPing-Ke Shih } 1856e3ec7017SPing-Ke Shih 185739e9b569SPing-Ke Shih static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 1858e3ec7017SPing-Ke Shih { 18595c3afcbaSPing-Ke Shih u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 18605c3afcbaSPing-Ke Shih 18615c3afcbaSPing-Ke Shih if (enable) { 18625c3afcbaSPing-Ke Shih if (rtwdev->chip->chip_id == RTL8851B) 18635c3afcbaSPing-Ke Shih val |= B_AX_AXIDMA_CLK_EN; 18645c3afcbaSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 18655c3afcbaSPing-Ke Shih } else { 18665c3afcbaSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 18675c3afcbaSPing-Ke Shih } 1868e3ec7017SPing-Ke Shih } 1869e3ec7017SPing-Ke Shih 187039e9b569SPing-Ke Shih static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1871e3ec7017SPing-Ke Shih { 1872e3ec7017SPing-Ke Shih const struct rtw89_dle_size *size_cfg; 1873e3ec7017SPing-Ke Shih u32 val; 1874e3ec7017SPing-Ke Shih u8 bound = 0; 1875e3ec7017SPing-Ke Shih 1876e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1877e3ec7017SPing-Ke Shih size_cfg = cfg->wde_size; 1878e3ec7017SPing-Ke Shih 1879e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1880e3ec7017SPing-Ke Shih default: 1881e3ec7017SPing-Ke Shih case RTW89_WDE_PG_64: 1882e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1883e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1884e3ec7017SPing-Ke Shih break; 1885e3ec7017SPing-Ke Shih case RTW89_WDE_PG_128: 1886e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1887e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1888e3ec7017SPing-Ke Shih break; 1889e3ec7017SPing-Ke Shih case RTW89_WDE_PG_256: 1890e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1891e3ec7017SPing-Ke Shih return -EINVAL; 1892e3ec7017SPing-Ke Shih } 1893e3ec7017SPing-Ke Shih 1894e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1895e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1896e3ec7017SPing-Ke Shih B_AX_WDE_FREE_PAGE_NUM_MASK); 1897e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1898e3ec7017SPing-Ke Shih 1899e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1900e3ec7017SPing-Ke Shih bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1901e3ec7017SPing-Ke Shih * size_cfg->pge_size / DLE_BOUND_UNIT; 1902e3ec7017SPing-Ke Shih size_cfg = cfg->ple_size; 1903e3ec7017SPing-Ke Shih 1904e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1905e3ec7017SPing-Ke Shih default: 1906e3ec7017SPing-Ke Shih case RTW89_PLE_PG_64: 1907e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1908e3ec7017SPing-Ke Shih return -EINVAL; 1909e3ec7017SPing-Ke Shih case RTW89_PLE_PG_128: 1910e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1911e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1912e3ec7017SPing-Ke Shih break; 1913e3ec7017SPing-Ke Shih case RTW89_PLE_PG_256: 1914e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1915e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1916e3ec7017SPing-Ke Shih break; 1917e3ec7017SPing-Ke Shih } 1918e3ec7017SPing-Ke Shih 1919e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1920e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1921e3ec7017SPing-Ke Shih B_AX_PLE_FREE_PAGE_NUM_MASK); 1922e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1923e3ec7017SPing-Ke Shih 1924e3ec7017SPing-Ke Shih return 0; 1925e3ec7017SPing-Ke Shih } 1926e3ec7017SPing-Ke Shih 192739e9b569SPing-Ke Shih static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 19280d16d8fbSPing-Ke Shih { 19290d16d8fbSPing-Ke Shih u32 reg, mask; 19300d16d8fbSPing-Ke Shih u32 ini; 19310d16d8fbSPing-Ke Shih 19320d16d8fbSPing-Ke Shih if (wde_or_ple) { 19330d16d8fbSPing-Ke Shih reg = R_AX_WDE_INI_STATUS; 19340d16d8fbSPing-Ke Shih mask = WDE_MGN_INI_RDY; 19350d16d8fbSPing-Ke Shih } else { 19360d16d8fbSPing-Ke Shih reg = R_AX_PLE_INI_STATUS; 19370d16d8fbSPing-Ke Shih mask = PLE_MGN_INI_RDY; 19380d16d8fbSPing-Ke Shih } 19390d16d8fbSPing-Ke Shih 19400d16d8fbSPing-Ke Shih return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 19410d16d8fbSPing-Ke Shih 2000, false, rtwdev, reg); 19420d16d8fbSPing-Ke Shih } 19430d16d8fbSPing-Ke Shih 1944e3ec7017SPing-Ke Shih #define INVALID_QT_WCPU U16_MAX 1945e3ec7017SPing-Ke Shih #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1946e3ec7017SPing-Ke Shih do { \ 1947525c06c8SPing-Ke Shih val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1948525c06c8SPing-Ke Shih u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1949e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, \ 1950e3ec7017SPing-Ke Shih R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1951e3ec7017SPing-Ke Shih val); \ 1952e3ec7017SPing-Ke Shih } while (0) 1953e3ec7017SPing-Ke Shih #define SET_QUOTA(_x, _module, _idx) \ 1954e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1955e3ec7017SPing-Ke Shih 195639e9b569SPing-Ke Shih static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 1957e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *min_cfg, 1958e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *max_cfg, 1959e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 1960e3ec7017SPing-Ke Shih { 1961e3ec7017SPing-Ke Shih u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1962e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu : min_cfg->wcpu; 1963e3ec7017SPing-Ke Shih u32 val; 1964e3ec7017SPing-Ke Shih 1965e3ec7017SPing-Ke Shih SET_QUOTA(hif, WDE, 0); 1966e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1967e3ec7017SPing-Ke Shih SET_QUOTA(pkt_in, WDE, 3); 1968e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, WDE, 4); 1969e3ec7017SPing-Ke Shih } 1970e3ec7017SPing-Ke Shih 197139e9b569SPing-Ke Shih static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 1972e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *min_cfg, 1973e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *max_cfg) 1974e3ec7017SPing-Ke Shih { 1975e3ec7017SPing-Ke Shih u32 val; 1976e3ec7017SPing-Ke Shih 1977e3ec7017SPing-Ke Shih SET_QUOTA(cma0_tx, PLE, 0); 1978e3ec7017SPing-Ke Shih SET_QUOTA(cma1_tx, PLE, 1); 1979e3ec7017SPing-Ke Shih SET_QUOTA(c2h, PLE, 2); 1980e3ec7017SPing-Ke Shih SET_QUOTA(h2c, PLE, 3); 1981e3ec7017SPing-Ke Shih SET_QUOTA(wcpu, PLE, 4); 1982e3ec7017SPing-Ke Shih SET_QUOTA(mpdu_proc, PLE, 5); 1983e3ec7017SPing-Ke Shih SET_QUOTA(cma0_dma, PLE, 6); 1984e3ec7017SPing-Ke Shih SET_QUOTA(cma1_dma, PLE, 7); 1985e3ec7017SPing-Ke Shih SET_QUOTA(bb_rpt, PLE, 8); 1986e3ec7017SPing-Ke Shih SET_QUOTA(wd_rel, PLE, 9); 1987e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, PLE, 10); 198879d099e0SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852C) 198979d099e0SPing-Ke Shih SET_QUOTA(tx_rpt, PLE, 11); 1990e3ec7017SPing-Ke Shih } 1991e3ec7017SPing-Ke Shih 19927a68ec3dSChih-Kang Chang int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 19937a68ec3dSChih-Kang Chang { 19947a68ec3dSChih-Kang Chang const struct rtw89_ple_quota *min_cfg, *max_cfg; 19957a68ec3dSChih-Kang Chang const struct rtw89_dle_mem *cfg; 19967a68ec3dSChih-Kang Chang u32 val; 19977a68ec3dSChih-Kang Chang 19987a68ec3dSChih-Kang Chang if (rtwdev->chip->chip_id == RTL8852C) 19997a68ec3dSChih-Kang Chang return 0; 20007a68ec3dSChih-Kang Chang 20017a68ec3dSChih-Kang Chang if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 20027a68ec3dSChih-Kang Chang rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 20037a68ec3dSChih-Kang Chang return -EINVAL; 20047a68ec3dSChih-Kang Chang } 20057a68ec3dSChih-Kang Chang 20067a68ec3dSChih-Kang Chang if (wow) 20077a68ec3dSChih-Kang Chang cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 20087a68ec3dSChih-Kang Chang else 20097a68ec3dSChih-Kang Chang cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 20107a68ec3dSChih-Kang Chang if (!cfg) { 20117a68ec3dSChih-Kang Chang rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 20127a68ec3dSChih-Kang Chang return -EINVAL; 20137a68ec3dSChih-Kang Chang } 20147a68ec3dSChih-Kang Chang 20157a68ec3dSChih-Kang Chang min_cfg = cfg->ple_min_qt; 20167a68ec3dSChih-Kang Chang max_cfg = cfg->ple_max_qt; 20177a68ec3dSChih-Kang Chang SET_QUOTA(cma0_dma, PLE, 6); 20187a68ec3dSChih-Kang Chang SET_QUOTA(cma1_dma, PLE, 7); 20197a68ec3dSChih-Kang Chang 20207a68ec3dSChih-Kang Chang return 0; 20217a68ec3dSChih-Kang Chang } 2022e3ec7017SPing-Ke Shih #undef SET_QUOTA 2023e3ec7017SPing-Ke Shih 202419e28c7fSChin-Yen Lee void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 202519e28c7fSChin-Yen Lee { 202619e28c7fSChin-Yen Lee u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 202719e28c7fSChin-Yen Lee 202819e28c7fSChin-Yen Lee if (enable) 202919e28c7fSChin-Yen Lee rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 203019e28c7fSChin-Yen Lee else 203119e28c7fSChin-Yen Lee rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 203219e28c7fSChin-Yen Lee } 203319e28c7fSChin-Yen Lee 2034e3ec7017SPing-Ke Shih static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2035e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, 2036e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 2037e3ec7017SPing-Ke Shih { 203839e9b569SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 203939e9b569SPing-Ke Shih 204039e9b569SPing-Ke Shih mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 204139e9b569SPing-Ke Shih mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2042e3ec7017SPing-Ke Shih } 2043e3ec7017SPing-Ke Shih 2044fc663fa0SPing-Ke Shih int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2045e3ec7017SPing-Ke Shih enum rtw89_qta_mode ext_mode) 2046e3ec7017SPing-Ke Shih { 204739e9b569SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2048e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, *ext_cfg; 2049e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 205039e9b569SPing-Ke Shih int ret; 2051e3ec7017SPing-Ke Shih 2052e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2053e3ec7017SPing-Ke Shih if (ret) 2054e3ec7017SPing-Ke Shih return ret; 2055e3ec7017SPing-Ke Shih 2056e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 2057e3ec7017SPing-Ke Shih if (!cfg) { 2058e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2059e3ec7017SPing-Ke Shih ret = -EINVAL; 2060e3ec7017SPing-Ke Shih goto error; 2061e3ec7017SPing-Ke Shih } 2062e3ec7017SPing-Ke Shih 2063e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_DLFW) { 2064e3ec7017SPing-Ke Shih ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2065e3ec7017SPing-Ke Shih if (!ext_cfg) { 2066e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2067e3ec7017SPing-Ke Shih ext_mode); 2068e3ec7017SPing-Ke Shih ret = -EINVAL; 2069e3ec7017SPing-Ke Shih goto error; 2070e3ec7017SPing-Ke Shih } 2071e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2072e3ec7017SPing-Ke Shih } 2073e3ec7017SPing-Ke Shih 2074aabe741eSPing-Ke Shih if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2075e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2076e3ec7017SPing-Ke Shih ret = -EINVAL; 2077e3ec7017SPing-Ke Shih goto error; 2078e3ec7017SPing-Ke Shih } 2079e3ec7017SPing-Ke Shih 208039e9b569SPing-Ke Shih mac->dle_func_en(rtwdev, false); 208139e9b569SPing-Ke Shih mac->dle_clk_en(rtwdev, true); 2082e3ec7017SPing-Ke Shih 208339e9b569SPing-Ke Shih ret = mac->dle_mix_cfg(rtwdev, cfg); 2084e3ec7017SPing-Ke Shih if (ret) { 2085e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2086e3ec7017SPing-Ke Shih goto error; 2087e3ec7017SPing-Ke Shih } 2088e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2089e3ec7017SPing-Ke Shih 209039e9b569SPing-Ke Shih mac->dle_func_en(rtwdev, true); 2091e3ec7017SPing-Ke Shih 209239e9b569SPing-Ke Shih ret = mac->chk_dle_rdy(rtwdev, true); 2093e3ec7017SPing-Ke Shih if (ret) { 2094e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2095e3ec7017SPing-Ke Shih return ret; 2096e3ec7017SPing-Ke Shih } 2097e3ec7017SPing-Ke Shih 209839e9b569SPing-Ke Shih ret = mac->chk_dle_rdy(rtwdev, false); 2099e3ec7017SPing-Ke Shih if (ret) { 2100e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2101e3ec7017SPing-Ke Shih return ret; 2102e3ec7017SPing-Ke Shih } 2103e3ec7017SPing-Ke Shih 2104e3ec7017SPing-Ke Shih return 0; 2105e3ec7017SPing-Ke Shih error: 210639e9b569SPing-Ke Shih mac->dle_func_en(rtwdev, false); 2107e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2108e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2109e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2110e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2111e3ec7017SPing-Ke Shih 2112e3ec7017SPing-Ke Shih return ret; 2113e3ec7017SPing-Ke Shih } 2114e3ec7017SPing-Ke Shih 2115e07a9968SPing-Ke Shih static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2116e07a9968SPing-Ke Shih enum rtw89_qta_mode mode) 2117e07a9968SPing-Ke Shih { 2118e07a9968SPing-Ke Shih u32 reg, max_preld_size, min_rsvd_size; 2119e07a9968SPing-Ke Shih 2120e07a9968SPing-Ke Shih max_preld_size = (mac_idx == RTW89_MAC_0 ? 2121e07a9968SPing-Ke Shih PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2122e07a9968SPing-Ke Shih reg = mac_idx == RTW89_MAC_0 ? 2123e07a9968SPing-Ke Shih R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2124e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2125e07a9968SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2126e07a9968SPing-Ke Shih 2127e07a9968SPing-Ke Shih min_rsvd_size = PRELD_AMSDU_SIZE; 2128e07a9968SPing-Ke Shih reg = mac_idx == RTW89_MAC_0 ? 2129e07a9968SPing-Ke Shih R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2130e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2131e07a9968SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2132e07a9968SPing-Ke Shih 2133e07a9968SPing-Ke Shih return 0; 2134e07a9968SPing-Ke Shih } 2135e07a9968SPing-Ke Shih 2136e07a9968SPing-Ke Shih static bool is_qta_poh(struct rtw89_dev *rtwdev) 2137e07a9968SPing-Ke Shih { 2138e07a9968SPing-Ke Shih return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2139e07a9968SPing-Ke Shih } 2140e07a9968SPing-Ke Shih 2141fc663fa0SPing-Ke Shih int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2142e07a9968SPing-Ke Shih enum rtw89_qta_mode mode) 2143e07a9968SPing-Ke Shih { 2144e07a9968SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2145e07a9968SPing-Ke Shih 21465c3afcbaSPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 21475c3afcbaSPing-Ke Shih chip->chip_id == RTL8851B || !is_qta_poh(rtwdev)) 2148e07a9968SPing-Ke Shih return 0; 2149e07a9968SPing-Ke Shih 2150e07a9968SPing-Ke Shih return preload_init_set(rtwdev, mac_idx, mode); 2151e07a9968SPing-Ke Shih } 2152e07a9968SPing-Ke Shih 2153e3ec7017SPing-Ke Shih static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2154e3ec7017SPing-Ke Shih { 2155e3ec7017SPing-Ke Shih u32 msk32; 2156e3ec7017SPing-Ke Shih u32 val32; 2157e3ec7017SPing-Ke Shih 2158e3ec7017SPing-Ke Shih msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2159e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2160e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2161e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2162e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2163e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2164e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2165e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2166e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2167e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2168e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2169e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2170e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2171e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2172e3ec7017SPing-Ke Shih 2173e3ec7017SPing-Ke Shih if ((val32 & msk32) == msk32) 2174e3ec7017SPing-Ke Shih return true; 2175e3ec7017SPing-Ke Shih 2176e3ec7017SPing-Ke Shih return false; 2177e3ec7017SPing-Ke Shih } 2178e3ec7017SPing-Ke Shih 2179cf7b8b80SPing-Ke Shih static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2180cf7b8b80SPing-Ke Shih { 2181cf7b8b80SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2182cf7b8b80SPing-Ke Shih 21835c3afcbaSPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 21845c3afcbaSPing-Ke Shih chip->chip_id == RTL8851B) 2185cf7b8b80SPing-Ke Shih return; 2186cf7b8b80SPing-Ke Shih 2187cf7b8b80SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2188cf7b8b80SPing-Ke Shih SS2F_PATH_WLCPU); 2189cf7b8b80SPing-Ke Shih } 2190cf7b8b80SPing-Ke Shih 2191fc663fa0SPing-Ke Shih static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2192e3ec7017SPing-Ke Shih { 2193e3ec7017SPing-Ke Shih u32 p_val; 2194e3ec7017SPing-Ke Shih u8 val; 2195e3ec7017SPing-Ke Shih int ret; 2196e3ec7017SPing-Ke Shih 2197e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2198e3ec7017SPing-Ke Shih if (ret) 2199e3ec7017SPing-Ke Shih return ret; 2200e3ec7017SPing-Ke Shih 2201e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2202e3ec7017SPing-Ke Shih val |= B_AX_SS_EN; 2203e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2204e3ec7017SPing-Ke Shih 2205e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2206e3ec7017SPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2207e3ec7017SPing-Ke Shih if (ret) { 2208e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2209e3ec7017SPing-Ke Shih return ret; 2210e3ec7017SPing-Ke Shih } 2211e3ec7017SPing-Ke Shih 22129a1ab283SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 22139a1ab283SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2214cf7b8b80SPing-Ke Shih 2215cf7b8b80SPing-Ke Shih _patch_ss2f_path(rtwdev); 2216e3ec7017SPing-Ke Shih 2217e3ec7017SPing-Ke Shih return 0; 2218e3ec7017SPing-Ke Shih } 2219e3ec7017SPing-Ke Shih 2220fc663fa0SPing-Ke Shih static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2221e3ec7017SPing-Ke Shih { 2222e3ec7017SPing-Ke Shih int ret; 2223e3ec7017SPing-Ke Shih 2224e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2225e3ec7017SPing-Ke Shih if (ret) 2226e3ec7017SPing-Ke Shih return ret; 2227e3ec7017SPing-Ke Shih 2228e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2229e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2230e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2231e3ec7017SPing-Ke Shih B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2232e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2233e3ec7017SPing-Ke Shih 2234e3ec7017SPing-Ke Shih return 0; 2235e3ec7017SPing-Ke Shih } 2236e3ec7017SPing-Ke Shih 2237fc663fa0SPing-Ke Shih static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2238e3ec7017SPing-Ke Shih { 2239b61adeedSPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2240e3ec7017SPing-Ke Shih u32 val = 0; 2241e3ec7017SPing-Ke Shih int ret; 2242e3ec7017SPing-Ke Shih 2243e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2244e3ec7017SPing-Ke Shih if (ret) 2245e3ec7017SPing-Ke Shih return ret; 2246e3ec7017SPing-Ke Shih 2247e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2248e3ec7017SPing-Ke Shih /* init clock */ 2249e3ec7017SPing-Ke Shih val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2250e3ec7017SPing-Ke Shih /* init TX encryption */ 2251e3ec7017SPing-Ke Shih val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2252e3ec7017SPing-Ke Shih val |= (B_AX_MC_DEC | B_AX_BC_DEC); 22535c3afcbaSPing-Ke Shih if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 22545c3afcbaSPing-Ke Shih chip->chip_id == RTL8851B) 2255e3ec7017SPing-Ke Shih val &= ~B_AX_TX_PARTIAL_MODE; 2256e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2257e3ec7017SPing-Ke Shih 2258e3ec7017SPing-Ke Shih /* init MIC ICV append */ 2259e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2260e3ec7017SPing-Ke Shih val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2261e3ec7017SPing-Ke Shih 2262e3ec7017SPing-Ke Shih /* option init */ 2263e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2264e3ec7017SPing-Ke Shih 2265b61adeedSPing-Ke Shih if (chip->chip_id == RTL8852C) 2266b61adeedSPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2267b61adeedSPing-Ke Shih B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2268b61adeedSPing-Ke Shih 2269e3ec7017SPing-Ke Shih return 0; 2270e3ec7017SPing-Ke Shih } 2271e3ec7017SPing-Ke Shih 2272fc663fa0SPing-Ke Shih static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2273e3ec7017SPing-Ke Shih { 2274e3ec7017SPing-Ke Shih int ret; 2275e3ec7017SPing-Ke Shih 2276fc663fa0SPing-Ke Shih ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2277e3ec7017SPing-Ke Shih if (ret) { 2278e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2279e3ec7017SPing-Ke Shih return ret; 2280e3ec7017SPing-Ke Shih } 2281e3ec7017SPing-Ke Shih 2282fc663fa0SPing-Ke Shih ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2283e07a9968SPing-Ke Shih if (ret) { 2284e07a9968SPing-Ke Shih rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2285e07a9968SPing-Ke Shih return ret; 2286e07a9968SPing-Ke Shih } 2287e07a9968SPing-Ke Shih 2288fc663fa0SPing-Ke Shih ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2289e3ec7017SPing-Ke Shih if (ret) { 2290e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2291e3ec7017SPing-Ke Shih return ret; 2292e3ec7017SPing-Ke Shih } 2293e3ec7017SPing-Ke Shih 2294fc663fa0SPing-Ke Shih ret = sta_sch_init_ax(rtwdev); 2295e3ec7017SPing-Ke Shih if (ret) { 2296e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2297e3ec7017SPing-Ke Shih return ret; 2298e3ec7017SPing-Ke Shih } 2299e3ec7017SPing-Ke Shih 2300fc663fa0SPing-Ke Shih ret = mpdu_proc_init_ax(rtwdev); 2301e3ec7017SPing-Ke Shih if (ret) { 2302e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2303e3ec7017SPing-Ke Shih return ret; 2304e3ec7017SPing-Ke Shih } 2305e3ec7017SPing-Ke Shih 2306fc663fa0SPing-Ke Shih ret = sec_eng_init_ax(rtwdev); 2307e3ec7017SPing-Ke Shih if (ret) { 2308e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2309e3ec7017SPing-Ke Shih return ret; 2310e3ec7017SPing-Ke Shih } 2311e3ec7017SPing-Ke Shih 2312e3ec7017SPing-Ke Shih return ret; 2313e3ec7017SPing-Ke Shih } 2314e3ec7017SPing-Ke Shih 2315fc663fa0SPing-Ke Shih static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2316e3ec7017SPing-Ke Shih { 2317e3ec7017SPing-Ke Shih u32 val, reg; 2318e3ec7017SPing-Ke Shih u16 p_val; 2319e3ec7017SPing-Ke Shih int ret; 2320e3ec7017SPing-Ke Shih 2321e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2322e3ec7017SPing-Ke Shih if (ret) 2323e3ec7017SPing-Ke Shih return ret; 2324e3ec7017SPing-Ke Shih 2325c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2326e3ec7017SPing-Ke Shih 2327e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2328e3ec7017SPing-Ke Shih val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2329e3ec7017SPing-Ke Shih B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2330e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2331e3ec7017SPing-Ke Shih 2332e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2333ad275d0aSPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2334e3ec7017SPing-Ke Shih if (ret) { 2335e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2336e3ec7017SPing-Ke Shih return ret; 2337e3ec7017SPing-Ke Shih } 2338e3ec7017SPing-Ke Shih 2339e3ec7017SPing-Ke Shih return 0; 2340e3ec7017SPing-Ke Shih } 2341e3ec7017SPing-Ke Shih 2342fc663fa0SPing-Ke Shih static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2343e3ec7017SPing-Ke Shih { 2344e3ec7017SPing-Ke Shih u32 ret; 2345e3ec7017SPing-Ke Shih u32 reg; 234660b2ede9SChia-Yuan Li u32 val; 2347e3ec7017SPing-Ke Shih 2348e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2349e3ec7017SPing-Ke Shih if (ret) 2350e3ec7017SPing-Ke Shih return ret; 2351e3ec7017SPing-Ke Shih 2352c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2353ee546904SChia-Yuan Li if (rtwdev->chip->chip_id == RTL8852C) 2354ee546904SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2355ee546904SChia-Yuan Li SIFS_MACTXEN_T1_V1); 2356ee546904SChia-Yuan Li else 2357ee546904SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2358ee546904SChia-Yuan Li SIFS_MACTXEN_T1); 2359c49154ffSPing-Ke Shih 23605c3afcbaSPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) { 2361c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2362c49154ffSPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2363c49154ffSPing-Ke Shih } 2364c49154ffSPing-Ke Shih 2365c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2366c49154ffSPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2367c49154ffSPing-Ke Shih 2368c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 236960b2ede9SChia-Yuan Li if (rtwdev->chip->chip_id == RTL8852C) { 237060b2ede9SChia-Yuan Li val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 237160b2ede9SChia-Yuan Li B_AX_TX_PARTIAL_MODE); 237260b2ede9SChia-Yuan Li if (!val) 237360b2ede9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 237460b2ede9SChia-Yuan Li SCH_PREBKF_24US); 237560b2ede9SChia-Yuan Li } else { 237660b2ede9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 237760b2ede9SChia-Yuan Li SCH_PREBKF_24US); 237860b2ede9SChia-Yuan Li } 2379e3ec7017SPing-Ke Shih 2380e3ec7017SPing-Ke Shih return 0; 2381e3ec7017SPing-Ke Shih } 2382e3ec7017SPing-Ke Shih 2383fc663fa0SPing-Ke Shih static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2384e3ec7017SPing-Ke Shih enum rtw89_machdr_frame_type type, 2385e3ec7017SPing-Ke Shih enum rtw89_mac_fwd_target fwd_target, 2386e3ec7017SPing-Ke Shih u8 mac_idx) 2387e3ec7017SPing-Ke Shih { 2388e3ec7017SPing-Ke Shih u32 reg; 2389e3ec7017SPing-Ke Shih u32 val; 2390e3ec7017SPing-Ke Shih 2391e3ec7017SPing-Ke Shih switch (fwd_target) { 2392e3ec7017SPing-Ke Shih case RTW89_FWD_DONT_CARE: 2393e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_DROP; 2394e3ec7017SPing-Ke Shih break; 2395e3ec7017SPing-Ke Shih case RTW89_FWD_TO_HOST: 2396e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_HOST; 2397e3ec7017SPing-Ke Shih break; 2398e3ec7017SPing-Ke Shih case RTW89_FWD_TO_WLAN_CPU: 2399e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_WLCPU; 2400e3ec7017SPing-Ke Shih break; 2401e3ec7017SPing-Ke Shih default: 2402e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2403e3ec7017SPing-Ke Shih return -EINVAL; 2404e3ec7017SPing-Ke Shih } 2405e3ec7017SPing-Ke Shih 2406e3ec7017SPing-Ke Shih switch (type) { 2407e3ec7017SPing-Ke Shih case RTW89_MGNT: 2408c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2409e3ec7017SPing-Ke Shih break; 2410e3ec7017SPing-Ke Shih case RTW89_CTRL: 2411c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2412e3ec7017SPing-Ke Shih break; 2413e3ec7017SPing-Ke Shih case RTW89_DATA: 2414c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2415e3ec7017SPing-Ke Shih break; 2416e3ec7017SPing-Ke Shih default: 2417e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2418e3ec7017SPing-Ke Shih return -EINVAL; 2419e3ec7017SPing-Ke Shih } 2420e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2421e3ec7017SPing-Ke Shih 2422e3ec7017SPing-Ke Shih return 0; 2423e3ec7017SPing-Ke Shih } 2424e3ec7017SPing-Ke Shih 2425fc663fa0SPing-Ke Shih static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2426e3ec7017SPing-Ke Shih { 2427e3ec7017SPing-Ke Shih int ret, i; 2428e3ec7017SPing-Ke Shih u32 mac_ftlr, plcp_ftlr; 2429e3ec7017SPing-Ke Shih 2430e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2431e3ec7017SPing-Ke Shih if (ret) 2432e3ec7017SPing-Ke Shih return ret; 2433e3ec7017SPing-Ke Shih 2434e3ec7017SPing-Ke Shih for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2435fc663fa0SPing-Ke Shih ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2436e3ec7017SPing-Ke Shih mac_idx); 2437e3ec7017SPing-Ke Shih if (ret) 2438e3ec7017SPing-Ke Shih return ret; 2439e3ec7017SPing-Ke Shih } 2440e3ec7017SPing-Ke Shih mac_ftlr = rtwdev->hal.rx_fltr; 2441e3ec7017SPing-Ke Shih plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2442e3ec7017SPing-Ke Shih B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2443e3ec7017SPing-Ke Shih B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2444e3ec7017SPing-Ke Shih B_AX_HE_SIGB_CRC_CHK; 2445c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2446e3ec7017SPing-Ke Shih mac_ftlr); 2447c220d08eSPing-Ke Shih rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2448e3ec7017SPing-Ke Shih plcp_ftlr); 2449e3ec7017SPing-Ke Shih 2450e3ec7017SPing-Ke Shih return 0; 2451e3ec7017SPing-Ke Shih } 2452e3ec7017SPing-Ke Shih 2453e3ec7017SPing-Ke Shih static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2454e3ec7017SPing-Ke Shih { 2455e3ec7017SPing-Ke Shih u32 reg, val32; 2456e3ec7017SPing-Ke Shih u32 b_rsp_chk_nav, b_rsp_chk_cca; 2457e3ec7017SPing-Ke Shih 2458e3ec7017SPing-Ke Shih b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2459e3ec7017SPing-Ke Shih B_AX_RSP_CHK_BASIC_NAV; 2460e3ec7017SPing-Ke Shih b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2461e3ec7017SPing-Ke Shih B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2462e3ec7017SPing-Ke Shih B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2463e3ec7017SPing-Ke Shih 2464e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 2465e3ec7017SPing-Ke Shih case RTL8852A: 2466e3ec7017SPing-Ke Shih case RTL8852B: 2467c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2468e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2469e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2470e3ec7017SPing-Ke Shih 2471c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2472e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2473e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2474e3ec7017SPing-Ke Shih break; 2475e3ec7017SPing-Ke Shih default: 2476c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2477e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2478e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2479e3ec7017SPing-Ke Shih 2480c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2481e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2482e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 2483e3ec7017SPing-Ke Shih break; 2484e3ec7017SPing-Ke Shih } 2485e3ec7017SPing-Ke Shih } 2486e3ec7017SPing-Ke Shih 2487fc663fa0SPing-Ke Shih static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2488e3ec7017SPing-Ke Shih { 2489e3ec7017SPing-Ke Shih u32 val, reg; 2490e3ec7017SPing-Ke Shih int ret; 2491e3ec7017SPing-Ke Shih 2492e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2493e3ec7017SPing-Ke Shih if (ret) 2494e3ec7017SPing-Ke Shih return ret; 2495e3ec7017SPing-Ke Shih 2496c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2497e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2498e3ec7017SPing-Ke Shih val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2499e3ec7017SPing-Ke Shih B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2500e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2501e3ec7017SPing-Ke Shih B_AX_CTN_CHK_INTRA_NAV | 2502e3ec7017SPing-Ke Shih B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2503e3ec7017SPing-Ke Shih B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2504e3ec7017SPing-Ke Shih B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 250598ed6159SPing-Ke Shih B_AX_CTN_CHK_CCA_P20); 2506e3ec7017SPing-Ke Shih val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2507e3ec7017SPing-Ke Shih B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2508e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 250998ed6159SPing-Ke Shih B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 251098ed6159SPing-Ke Shih B_AX_SIFS_CHK_EDCCA); 2511e3ec7017SPing-Ke Shih 2512e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2513e3ec7017SPing-Ke Shih 2514e3ec7017SPing-Ke Shih _patch_dis_resp_chk(rtwdev, mac_idx); 2515e3ec7017SPing-Ke Shih 2516e3ec7017SPing-Ke Shih return 0; 2517e3ec7017SPing-Ke Shih } 2518e3ec7017SPing-Ke Shih 2519fc663fa0SPing-Ke Shih static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 252019cb9427SPing-Ke Shih { 252119cb9427SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 252219cb9427SPing-Ke Shih B_AX_WMAC_TF_UP_NAV_EN | 252319cb9427SPing-Ke Shih B_AX_WMAC_NAV_UPPER_EN); 2524c060dc51SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 252519cb9427SPing-Ke Shih 252619cb9427SPing-Ke Shih return 0; 252719cb9427SPing-Ke Shih } 252819cb9427SPing-Ke Shih 2529fc663fa0SPing-Ke Shih static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2530e3ec7017SPing-Ke Shih { 2531e3ec7017SPing-Ke Shih u32 reg; 2532e3ec7017SPing-Ke Shih int ret; 2533e3ec7017SPing-Ke Shih 2534e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2535e3ec7017SPing-Ke Shih if (ret) 2536e3ec7017SPing-Ke Shih return ret; 2537c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2538e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2539e3ec7017SPing-Ke Shih 2540505b57d0SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2541505b57d0SPing-Ke Shih rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2542505b57d0SPing-Ke Shih 2543e3ec7017SPing-Ke Shih return 0; 2544e3ec7017SPing-Ke Shih } 2545e3ec7017SPing-Ke Shih 2546fc663fa0SPing-Ke Shih static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2547e3ec7017SPing-Ke Shih { 2548e3ec7017SPing-Ke Shih u32 reg; 2549e3ec7017SPing-Ke Shih int ret; 2550e3ec7017SPing-Ke Shih 2551e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2552e3ec7017SPing-Ke Shih if (ret) 2553e3ec7017SPing-Ke Shih return ret; 2554e3ec7017SPing-Ke Shih 2555c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2556e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2557e3ec7017SPing-Ke Shih 2558c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 255975fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 256075fd91aaSPing-Ke Shih 2561c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 256275fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 256375fd91aaSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 256475fd91aaSPing-Ke Shih 2565e3ec7017SPing-Ke Shih return 0; 2566e3ec7017SPing-Ke Shih } 2567e3ec7017SPing-Ke Shih 2568fc663fa0SPing-Ke Shih static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2569e3ec7017SPing-Ke Shih { 25709ef9edb9SChia-Yuan Li const struct rtw89_chip_info *chip = rtwdev->chip; 25719ef9edb9SChia-Yuan Li const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2572e3ec7017SPing-Ke Shih u32 reg, val, sifs; 2573e3ec7017SPing-Ke Shih int ret; 2574e3ec7017SPing-Ke Shih 2575e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2576e3ec7017SPing-Ke Shih if (ret) 2577e3ec7017SPing-Ke Shih return ret; 2578e3ec7017SPing-Ke Shih 2579c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2580e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2581e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2582e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2583e3ec7017SPing-Ke Shih 2584e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 2585e3ec7017SPing-Ke Shih case RTL8852A: 2586e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52A; 2587e3ec7017SPing-Ke Shih break; 2588e3ec7017SPing-Ke Shih case RTL8852B: 2589e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52B; 2590e3ec7017SPing-Ke Shih break; 2591e3ec7017SPing-Ke Shih default: 2592e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52C; 2593e3ec7017SPing-Ke Shih break; 2594e3ec7017SPing-Ke Shih } 2595e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2596e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2597e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2598e3ec7017SPing-Ke Shih 2599c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2600e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2601e3ec7017SPing-Ke Shih 2602c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 26039ef9edb9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2604c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 26059ef9edb9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 26069ef9edb9SChia-Yuan Li 2607e3ec7017SPing-Ke Shih return 0; 2608e3ec7017SPing-Ke Shih } 2609e3ec7017SPing-Ke Shih 261018175197SPing-Ke Shih static void rst_bacam(struct rtw89_dev *rtwdev) 261118175197SPing-Ke Shih { 261218175197SPing-Ke Shih u32 val32; 261318175197SPing-Ke Shih int ret; 261418175197SPing-Ke Shih 261518175197SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 261618175197SPing-Ke Shih S_AX_BACAM_RST_ALL); 261718175197SPing-Ke Shih 261818175197SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 261918175197SPing-Ke Shih 1, 1000, false, 262018175197SPing-Ke Shih rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 262118175197SPing-Ke Shih if (ret) 262218175197SPing-Ke Shih rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 262318175197SPing-Ke Shih } 262418175197SPing-Ke Shih 2625fc663fa0SPing-Ke Shih static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2626e3ec7017SPing-Ke Shih { 2627e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_CCA_TO 32 2628e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_DATA_TO 15 2629e3ec7017SPing-Ke Shih #define RX_MAX_LEN_UNIT 512 2630e3ec7017SPing-Ke Shih #define PLD_RLS_MAX_PG 127 26314b0d341bSPing-Ke Shih #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2632e3ec7017SPing-Ke Shih int ret; 2633e3ec7017SPing-Ke Shih u32 reg, rx_max_len, rx_qta; 2634e3ec7017SPing-Ke Shih u16 val; 2635e3ec7017SPing-Ke Shih 2636e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2637e3ec7017SPing-Ke Shih if (ret) 2638e3ec7017SPing-Ke Shih return ret; 2639e3ec7017SPing-Ke Shih 264018175197SPing-Ke Shih if (mac_idx == RTW89_MAC_0) 264118175197SPing-Ke Shih rst_bacam(rtwdev); 264218175197SPing-Ke Shih 2643c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2644e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2645e3ec7017SPing-Ke Shih 2646c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2647e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 2648e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2649e3ec7017SPing-Ke Shih B_AX_RX_DLK_DATA_TIME_MASK); 2650e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2651e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK); 2652e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 2653e3ec7017SPing-Ke Shih 2654c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2655e3ec7017SPing-Ke Shih rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2656e3ec7017SPing-Ke Shih 2657c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2658e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_0) 2659e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2660e3ec7017SPing-Ke Shih else 2661e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 26624b0d341bSPing-Ke Shih rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 26634b0d341bSPing-Ke Shih rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 26644b0d341bSPing-Ke Shih rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 26654b0d341bSPing-Ke Shih rx_max_len /= RX_MAX_LEN_UNIT; 2666e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2667e3ec7017SPing-Ke Shih 2668e3ec7017SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852A && 2669e3ec7017SPing-Ke Shih rtwdev->hal.cv == CHIP_CBV) { 2670e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, 2671c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2672e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK, 0); 2673c220d08eSPing-Ke Shih rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2674e3ec7017SPing-Ke Shih BIT(12)); 2675e3ec7017SPing-Ke Shih } 2676e3ec7017SPing-Ke Shih 2677c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2678e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2679e3ec7017SPing-Ke Shih 2680e3ec7017SPing-Ke Shih return ret; 2681e3ec7017SPing-Ke Shih } 2682e3ec7017SPing-Ke Shih 2683fc663fa0SPing-Ke Shih static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2684e3ec7017SPing-Ke Shih { 26859ef9edb9SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2686e3ec7017SPing-Ke Shih u32 val, reg; 2687e3ec7017SPing-Ke Shih int ret; 2688e3ec7017SPing-Ke Shih 2689e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2690e3ec7017SPing-Ke Shih if (ret) 2691e3ec7017SPing-Ke Shih return ret; 2692e3ec7017SPing-Ke Shih 2693c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2694e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2695e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2696e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2697e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2698e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2699e3ec7017SPing-Ke Shih 27009ef9edb9SChia-Yuan Li if (chip_id == RTL8852A || chip_id == RTL8852B) { 2701c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 27029ef9edb9SChia-Yuan Li rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 27039ef9edb9SChia-Yuan Li } 27049ef9edb9SChia-Yuan Li 2705e3ec7017SPing-Ke Shih return 0; 2706e3ec7017SPing-Ke Shih } 2707e3ec7017SPing-Ke Shih 2708fc663fa0SPing-Ke Shih bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2709e3ec7017SPing-Ke Shih { 2710e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 2711e3ec7017SPing-Ke Shih 2712e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 2713e3ec7017SPing-Ke Shih if (!cfg) { 2714e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2715e3ec7017SPing-Ke Shih return false; 2716e3ec7017SPing-Ke Shih } 2717e3ec7017SPing-Ke Shih 2718e3ec7017SPing-Ke Shih return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2719e3ec7017SPing-Ke Shih } 2720e3ec7017SPing-Ke Shih 2721fc663fa0SPing-Ke Shih static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2722e3ec7017SPing-Ke Shih { 2723e3ec7017SPing-Ke Shih u32 val, reg; 2724e3ec7017SPing-Ke Shih int ret; 2725e3ec7017SPing-Ke Shih 2726e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2727e3ec7017SPing-Ke Shih if (ret) 2728e3ec7017SPing-Ke Shih return ret; 2729e3ec7017SPing-Ke Shih 2730e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2731c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2732e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2733e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2734e3ec7017SPing-Ke Shih B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 27359fb4862eSPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 27369fb4862eSPing-Ke Shih B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2737e3ec7017SPing-Ke Shih val |= B_AX_HW_CTS2SELF_EN; 2738e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2739e3ec7017SPing-Ke Shih 2740c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2741e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2742e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2743e3ec7017SPing-Ke Shih val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2744e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2745e3ec7017SPing-Ke Shih } 2746e3ec7017SPing-Ke Shih 27479fb4862eSPing-Ke Shih if (mac_idx == RTW89_MAC_0) { 27489fb4862eSPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 27499fb4862eSPing-Ke Shih B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 27509fb4862eSPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 27519fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_0 | 27529fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_1 | 27539fb4862eSPing-Ke Shih B_AX_PTCL_TRIGGER_SS_EN_UL); 27549fb4862eSPing-Ke Shih rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 27559fb4862eSPing-Ke Shih B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 27569fb4862eSPing-Ke Shih } else if (mac_idx == RTW89_MAC_1) { 27579fb4862eSPing-Ke Shih rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 27589fb4862eSPing-Ke Shih B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 27599fb4862eSPing-Ke Shih } 2760e3ec7017SPing-Ke Shih 2761e3ec7017SPing-Ke Shih return 0; 2762e3ec7017SPing-Ke Shih } 2763e3ec7017SPing-Ke Shih 2764fc663fa0SPing-Ke Shih static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2765a0d99ebbSPing-Ke Shih { 2766a0d99ebbSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2767a0d99ebbSPing-Ke Shih u32 reg; 2768a0d99ebbSPing-Ke Shih int ret; 2769a0d99ebbSPing-Ke Shih 2770b74bb07cSPing-Ke Shih if (chip_id != RTL8852B) 2771a0d99ebbSPing-Ke Shih return 0; 2772a0d99ebbSPing-Ke Shih 2773a0d99ebbSPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2774a0d99ebbSPing-Ke Shih if (ret) 2775a0d99ebbSPing-Ke Shih return ret; 2776a0d99ebbSPing-Ke Shih 2777c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2778a0d99ebbSPing-Ke Shih rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2779a0d99ebbSPing-Ke Shih 2780a0d99ebbSPing-Ke Shih return 0; 2781a0d99ebbSPing-Ke Shih } 2782a0d99ebbSPing-Ke Shih 2783fc663fa0SPing-Ke Shih static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2784e3ec7017SPing-Ke Shih { 2785e3ec7017SPing-Ke Shih int ret; 2786e3ec7017SPing-Ke Shih 2787fc663fa0SPing-Ke Shih ret = scheduler_init_ax(rtwdev, mac_idx); 2788e3ec7017SPing-Ke Shih if (ret) { 2789e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2790e3ec7017SPing-Ke Shih return ret; 2791e3ec7017SPing-Ke Shih } 2792e3ec7017SPing-Ke Shih 2793fc663fa0SPing-Ke Shih ret = addr_cam_init_ax(rtwdev, mac_idx); 2794e3ec7017SPing-Ke Shih if (ret) { 2795e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2796e3ec7017SPing-Ke Shih ret); 2797e3ec7017SPing-Ke Shih return ret; 2798e3ec7017SPing-Ke Shih } 2799e3ec7017SPing-Ke Shih 2800fc663fa0SPing-Ke Shih ret = rx_fltr_init_ax(rtwdev, mac_idx); 2801e3ec7017SPing-Ke Shih if (ret) { 2802e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2803e3ec7017SPing-Ke Shih ret); 2804e3ec7017SPing-Ke Shih return ret; 2805e3ec7017SPing-Ke Shih } 2806e3ec7017SPing-Ke Shih 2807fc663fa0SPing-Ke Shih ret = cca_ctrl_init_ax(rtwdev, mac_idx); 2808e3ec7017SPing-Ke Shih if (ret) { 2809e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2810e3ec7017SPing-Ke Shih ret); 2811e3ec7017SPing-Ke Shih return ret; 2812e3ec7017SPing-Ke Shih } 2813e3ec7017SPing-Ke Shih 2814fc663fa0SPing-Ke Shih ret = nav_ctrl_init_ax(rtwdev); 281519cb9427SPing-Ke Shih if (ret) { 281619cb9427SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 281719cb9427SPing-Ke Shih ret); 281819cb9427SPing-Ke Shih return ret; 281919cb9427SPing-Ke Shih } 282019cb9427SPing-Ke Shih 2821fc663fa0SPing-Ke Shih ret = spatial_reuse_init_ax(rtwdev, mac_idx); 2822e3ec7017SPing-Ke Shih if (ret) { 2823e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2824e3ec7017SPing-Ke Shih mac_idx, ret); 2825e3ec7017SPing-Ke Shih return ret; 2826e3ec7017SPing-Ke Shih } 2827e3ec7017SPing-Ke Shih 2828fc663fa0SPing-Ke Shih ret = tmac_init_ax(rtwdev, mac_idx); 2829e3ec7017SPing-Ke Shih if (ret) { 2830e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2831e3ec7017SPing-Ke Shih return ret; 2832e3ec7017SPing-Ke Shih } 2833e3ec7017SPing-Ke Shih 2834fc663fa0SPing-Ke Shih ret = trxptcl_init_ax(rtwdev, mac_idx); 2835e3ec7017SPing-Ke Shih if (ret) { 2836e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2837e3ec7017SPing-Ke Shih return ret; 2838e3ec7017SPing-Ke Shih } 2839e3ec7017SPing-Ke Shih 2840fc663fa0SPing-Ke Shih ret = rmac_init_ax(rtwdev, mac_idx); 2841e3ec7017SPing-Ke Shih if (ret) { 2842e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2843e3ec7017SPing-Ke Shih return ret; 2844e3ec7017SPing-Ke Shih } 2845e3ec7017SPing-Ke Shih 2846fc663fa0SPing-Ke Shih ret = cmac_com_init_ax(rtwdev, mac_idx); 2847e3ec7017SPing-Ke Shih if (ret) { 2848e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2849e3ec7017SPing-Ke Shih return ret; 2850e3ec7017SPing-Ke Shih } 2851e3ec7017SPing-Ke Shih 2852fc663fa0SPing-Ke Shih ret = ptcl_init_ax(rtwdev, mac_idx); 2853e3ec7017SPing-Ke Shih if (ret) { 2854e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2855e3ec7017SPing-Ke Shih return ret; 2856e3ec7017SPing-Ke Shih } 2857e3ec7017SPing-Ke Shih 2858fc663fa0SPing-Ke Shih ret = cmac_dma_init_ax(rtwdev, mac_idx); 2859a0d99ebbSPing-Ke Shih if (ret) { 2860a0d99ebbSPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2861a0d99ebbSPing-Ke Shih return ret; 2862a0d99ebbSPing-Ke Shih } 2863a0d99ebbSPing-Ke Shih 2864e3ec7017SPing-Ke Shih return ret; 2865e3ec7017SPing-Ke Shih } 2866e3ec7017SPing-Ke Shih 2867e3ec7017SPing-Ke Shih static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2868e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info *c2h_info) 2869e3ec7017SPing-Ke Shih { 287088e6a923SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2871e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 2872e3ec7017SPing-Ke Shih u32 ret; 2873e3ec7017SPing-Ke Shih 287488e6a923SPing-Ke Shih mac->cnv_efuse_state(rtwdev, false); 287588e6a923SPing-Ke Shih 2876e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2877e3ec7017SPing-Ke Shih h2c_info.content_len = 0; 2878e3ec7017SPing-Ke Shih 2879e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2880e3ec7017SPing-Ke Shih if (ret) 288188e6a923SPing-Ke Shih goto out; 2882e3ec7017SPing-Ke Shih 2883e3ec7017SPing-Ke Shih if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 288488e6a923SPing-Ke Shih ret = -EINVAL; 2885e3ec7017SPing-Ke Shih 288688e6a923SPing-Ke Shih out: 288788e6a923SPing-Ke Shih mac->cnv_efuse_state(rtwdev, true); 288888e6a923SPing-Ke Shih 288988e6a923SPing-Ke Shih return ret; 2890e3ec7017SPing-Ke Shih } 2891e3ec7017SPing-Ke Shih 2892e3ec7017SPing-Ke Shih int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2893e3ec7017SPing-Ke Shih { 2894f48453e0SPing-Ke Shih struct rtw89_efuse *efuse = &rtwdev->efuse; 2895e3ec7017SPing-Ke Shih struct rtw89_hal *hal = &rtwdev->hal; 2896e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2897e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 289868012b44SPing-Ke Shih const struct rtw89_c2hreg_phycap *phycap; 2899c7ad08c6SPing-Ke Shih u8 tx_nss; 2900c7ad08c6SPing-Ke Shih u8 rx_nss; 2901dc229d94SPing-Ke Shih u8 tx_ant; 2902dc229d94SPing-Ke Shih u8 rx_ant; 2903e3ec7017SPing-Ke Shih u32 ret; 2904e3ec7017SPing-Ke Shih 2905e3ec7017SPing-Ke Shih ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2906e3ec7017SPing-Ke Shih if (ret) 2907e3ec7017SPing-Ke Shih return ret; 2908e3ec7017SPing-Ke Shih 290968012b44SPing-Ke Shih phycap = &c2h_info.u.phycap; 291068012b44SPing-Ke Shih 291168012b44SPing-Ke Shih tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 291268012b44SPing-Ke Shih rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 291368012b44SPing-Ke Shih tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 291468012b44SPing-Ke Shih rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2915c7ad08c6SPing-Ke Shih 2916c7ad08c6SPing-Ke Shih hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2917c7ad08c6SPing-Ke Shih hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2918e3ec7017SPing-Ke Shih 2919dc229d94SPing-Ke Shih if (tx_ant == 1) 2920dc229d94SPing-Ke Shih hal->antenna_tx = RF_B; 2921dc229d94SPing-Ke Shih if (rx_ant == 1) 2922dc229d94SPing-Ke Shih hal->antenna_rx = RF_B; 2923dc229d94SPing-Ke Shih 2924dc229d94SPing-Ke Shih if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2925dc229d94SPing-Ke Shih hal->antenna_tx = RF_B; 2926dc229d94SPing-Ke Shih hal->tx_path_diversity = true; 2927dc229d94SPing-Ke Shih } 2928dc229d94SPing-Ke Shih 2929f48453e0SPing-Ke Shih if (chip->rf_path_num == 1) { 2930f48453e0SPing-Ke Shih hal->antenna_tx = RF_A; 2931f48453e0SPing-Ke Shih hal->antenna_rx = RF_A; 2932f48453e0SPing-Ke Shih if ((efuse->rfe_type % 3) == 2) 2933f48453e0SPing-Ke Shih hal->ant_diversity = true; 2934f48453e0SPing-Ke Shih } 2935f48453e0SPing-Ke Shih 2936e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 2937e3ec7017SPing-Ke Shih "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2938c7ad08c6SPing-Ke Shih hal->tx_nss, tx_nss, chip->tx_nss, 2939c7ad08c6SPing-Ke Shih hal->rx_nss, rx_nss, chip->rx_nss); 2940dc229d94SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 2941dc229d94SPing-Ke Shih "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2942dc229d94SPing-Ke Shih tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2943dc229d94SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2944f48453e0SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2945e3ec7017SPing-Ke Shih 2946e3ec7017SPing-Ke Shih return 0; 2947e3ec7017SPing-Ke Shih } 2948e3ec7017SPing-Ke Shih 2949e3ec7017SPing-Ke Shih static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2950e3ec7017SPing-Ke Shih u16 tx_en_u16, u16 mask_u16) 2951e3ec7017SPing-Ke Shih { 2952e3ec7017SPing-Ke Shih u32 ret; 2953e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 2954e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 295568012b44SPing-Ke Shih struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 2956e3ec7017SPing-Ke Shih 2957e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 295868012b44SPing-Ke Shih h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 295968012b44SPing-Ke Shih 296068012b44SPing-Ke Shih u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 296168012b44SPing-Ke Shih u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 296268012b44SPing-Ke Shih u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 2963e3ec7017SPing-Ke Shih 2964e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2965e3ec7017SPing-Ke Shih if (ret) 2966e3ec7017SPing-Ke Shih return ret; 2967e3ec7017SPing-Ke Shih 2968e3ec7017SPing-Ke Shih if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2969e3ec7017SPing-Ke Shih return -EINVAL; 2970e3ec7017SPing-Ke Shih 2971e3ec7017SPing-Ke Shih return 0; 2972e3ec7017SPing-Ke Shih } 2973e3ec7017SPing-Ke Shih 2974e3ec7017SPing-Ke Shih static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2975e3ec7017SPing-Ke Shih u16 tx_en, u16 tx_en_mask) 2976e3ec7017SPing-Ke Shih { 2977c220d08eSPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 2978e3ec7017SPing-Ke Shih u16 val; 2979e3ec7017SPing-Ke Shih int ret; 2980e3ec7017SPing-Ke Shih 2981e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2982e3ec7017SPing-Ke Shih if (ret) 2983e3ec7017SPing-Ke Shih return ret; 2984e3ec7017SPing-Ke Shih 2985e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2986e3ec7017SPing-Ke Shih return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2987e3ec7017SPing-Ke Shih tx_en, tx_en_mask); 2988e3ec7017SPing-Ke Shih 2989e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 2990e3ec7017SPing-Ke Shih val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2991e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 2992e3ec7017SPing-Ke Shih 2993e3ec7017SPing-Ke Shih return 0; 2994e3ec7017SPing-Ke Shih } 2995e3ec7017SPing-Ke Shih 2996de7ba639SPing-Ke Shih static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2997de7ba639SPing-Ke Shih u32 tx_en, u32 tx_en_mask) 2998de7ba639SPing-Ke Shih { 2999c220d08eSPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3000de7ba639SPing-Ke Shih u32 val; 3001de7ba639SPing-Ke Shih int ret; 3002de7ba639SPing-Ke Shih 3003de7ba639SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3004de7ba639SPing-Ke Shih if (ret) 3005de7ba639SPing-Ke Shih return ret; 3006de7ba639SPing-Ke Shih 3007de7ba639SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 3008de7ba639SPing-Ke Shih val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3009de7ba639SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 3010de7ba639SPing-Ke Shih 3011de7ba639SPing-Ke Shih return 0; 3012de7ba639SPing-Ke Shih } 3013de7ba639SPing-Ke Shih 3014e3ec7017SPing-Ke Shih int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3015d780f926SPing-Ke Shih u32 *tx_en, enum rtw89_sch_tx_sel sel) 3016e3ec7017SPing-Ke Shih { 3017e3ec7017SPing-Ke Shih int ret; 3018e3ec7017SPing-Ke Shih 3019e3ec7017SPing-Ke Shih *tx_en = rtw89_read16(rtwdev, 3020c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3021e3ec7017SPing-Ke Shih 3022e3ec7017SPing-Ke Shih switch (sel) { 3023e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_ALL: 3024de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3025de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK); 3026e3ec7017SPing-Ke Shih if (ret) 3027e3ec7017SPing-Ke Shih return ret; 3028e3ec7017SPing-Ke Shih break; 3029e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_HIQ: 3030e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3031e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_HGQ); 3032e3ec7017SPing-Ke Shih if (ret) 3033e3ec7017SPing-Ke Shih return ret; 3034e3ec7017SPing-Ke Shih break; 3035e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MG0: 3036e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3037e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_MGQ); 3038e3ec7017SPing-Ke Shih if (ret) 3039e3ec7017SPing-Ke Shih return ret; 3040e3ec7017SPing-Ke Shih break; 3041e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MACID: 3042de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3043de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK); 3044e3ec7017SPing-Ke Shih if (ret) 3045e3ec7017SPing-Ke Shih return ret; 3046e3ec7017SPing-Ke Shih break; 3047e3ec7017SPing-Ke Shih default: 3048e3ec7017SPing-Ke Shih return 0; 3049e3ec7017SPing-Ke Shih } 3050e3ec7017SPing-Ke Shih 3051e3ec7017SPing-Ke Shih return 0; 3052e3ec7017SPing-Ke Shih } 3053861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3054e3ec7017SPing-Ke Shih 3055de7ba639SPing-Ke Shih int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3056de7ba639SPing-Ke Shih u32 *tx_en, enum rtw89_sch_tx_sel sel) 3057de7ba639SPing-Ke Shih { 3058de7ba639SPing-Ke Shih int ret; 3059de7ba639SPing-Ke Shih 3060de7ba639SPing-Ke Shih *tx_en = rtw89_read32(rtwdev, 3061c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3062de7ba639SPing-Ke Shih 3063de7ba639SPing-Ke Shih switch (sel) { 3064de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_ALL: 3065de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3066de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 3067de7ba639SPing-Ke Shih if (ret) 3068de7ba639SPing-Ke Shih return ret; 3069de7ba639SPing-Ke Shih break; 3070de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_HIQ: 3071de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3072de7ba639SPing-Ke Shih 0, B_AX_CTN_TXEN_HGQ); 3073de7ba639SPing-Ke Shih if (ret) 3074de7ba639SPing-Ke Shih return ret; 3075de7ba639SPing-Ke Shih break; 3076de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_MG0: 3077de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3078de7ba639SPing-Ke Shih 0, B_AX_CTN_TXEN_MGQ); 3079de7ba639SPing-Ke Shih if (ret) 3080de7ba639SPing-Ke Shih return ret; 3081de7ba639SPing-Ke Shih break; 3082de7ba639SPing-Ke Shih case RTW89_SCH_TX_SEL_MACID: 3083de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3084de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 3085de7ba639SPing-Ke Shih if (ret) 3086de7ba639SPing-Ke Shih return ret; 3087de7ba639SPing-Ke Shih break; 3088de7ba639SPing-Ke Shih default: 3089de7ba639SPing-Ke Shih return 0; 3090de7ba639SPing-Ke Shih } 3091de7ba639SPing-Ke Shih 3092de7ba639SPing-Ke Shih return 0; 3093de7ba639SPing-Ke Shih } 3094de7ba639SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3095de7ba639SPing-Ke Shih 3096d780f926SPing-Ke Shih int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3097e3ec7017SPing-Ke Shih { 3098e3ec7017SPing-Ke Shih int ret; 3099e3ec7017SPing-Ke Shih 3100de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3101e3ec7017SPing-Ke Shih if (ret) 3102e3ec7017SPing-Ke Shih return ret; 3103e3ec7017SPing-Ke Shih 3104e3ec7017SPing-Ke Shih return 0; 3105e3ec7017SPing-Ke Shih } 3106861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3107e3ec7017SPing-Ke Shih 3108de7ba639SPing-Ke Shih int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3109de7ba639SPing-Ke Shih { 3110de7ba639SPing-Ke Shih int ret; 3111de7ba639SPing-Ke Shih 3112de7ba639SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3113de7ba639SPing-Ke Shih B_AX_CTN_TXEN_ALL_MASK_V1); 3114de7ba639SPing-Ke Shih if (ret) 3115de7ba639SPing-Ke Shih return ret; 3116de7ba639SPing-Ke Shih 3117de7ba639SPing-Ke Shih return 0; 3118de7ba639SPing-Ke Shih } 3119de7ba639SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3120de7ba639SPing-Ke Shih 312139e9b569SPing-Ke Shih static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3122e3ec7017SPing-Ke Shih { 3123e3ec7017SPing-Ke Shih u32 val, reg; 3124e3ec7017SPing-Ke Shih int ret; 3125e3ec7017SPing-Ke Shih 3126e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3127e3ec7017SPing-Ke Shih val = buf_len; 3128e3ec7017SPing-Ke Shih val |= B_AX_WD_BUF_REQ_EXEC; 3129e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 3130e3ec7017SPing-Ke Shih 3131e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3132e3ec7017SPing-Ke Shih 3133e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3134e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 3135e3ec7017SPing-Ke Shih if (ret) 3136eaddda24SPing-Ke Shih return ret; 3137e3ec7017SPing-Ke Shih 3138eaddda24SPing-Ke Shih *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3139eaddda24SPing-Ke Shih if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3140eaddda24SPing-Ke Shih return -ENOENT; 3141eaddda24SPing-Ke Shih 3142eaddda24SPing-Ke Shih return 0; 3143e3ec7017SPing-Ke Shih } 3144e3ec7017SPing-Ke Shih 314539e9b569SPing-Ke Shih static int set_cpuio_ax(struct rtw89_dev *rtwdev, 31468a1f6c88SZong-Zhe Yang struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3147e3ec7017SPing-Ke Shih { 3148e3ec7017SPing-Ke Shih u32 val, cmd_type, reg; 3149e3ec7017SPing-Ke Shih int ret; 3150e3ec7017SPing-Ke Shih 3151e3ec7017SPing-Ke Shih cmd_type = ctrl_para->cmd_type; 3152e3ec7017SPing-Ke Shih 3153e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3154e3ec7017SPing-Ke Shih val = 0; 3155e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->start_pktid, 3156e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3157e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->end_pktid, 3158e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3159e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 3160e3ec7017SPing-Ke Shih 3161e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3162e3ec7017SPing-Ke Shih val = 0; 3163e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_pid, 3164e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_PID_MASK); 3165e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_qid, 3166e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_QID_MASK); 3167e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_pid, 3168e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_PID_MASK); 3169e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_qid, 3170e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_QID_MASK); 3171e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 3172e3ec7017SPing-Ke Shih 3173e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3174e3ec7017SPing-Ke Shih val = 0; 3175e3ec7017SPing-Ke Shih val = u32_replace_bits(val, cmd_type, 3176e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_CMD_TYPE_MASK); 3177e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->macid, 3178e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_MACID_MASK); 3179e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->pkt_num, 3180e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_PKTNUM_MASK); 3181e3ec7017SPing-Ke Shih val |= B_AX_WD_CPUQ_OP_EXEC; 3182e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 3183e3ec7017SPing-Ke Shih 3184e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3185e3ec7017SPing-Ke Shih 3186e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3187e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 3188e3ec7017SPing-Ke Shih if (ret) 3189e3ec7017SPing-Ke Shih return ret; 3190e3ec7017SPing-Ke Shih 3191e3ec7017SPing-Ke Shih if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3192e3ec7017SPing-Ke Shih cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3193e3ec7017SPing-Ke Shih ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3194e3ec7017SPing-Ke Shih 3195e3ec7017SPing-Ke Shih return 0; 3196e3ec7017SPing-Ke Shih } 3197e3ec7017SPing-Ke Shih 3198b6e65d18SPing-Ke Shih int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3199b6e65d18SPing-Ke Shih bool band1_en) 3200e3ec7017SPing-Ke Shih { 320139e9b569SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3202e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 3203e3ec7017SPing-Ke Shih 3204e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 3205e3ec7017SPing-Ke Shih if (!cfg) { 3206e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3207e3ec7017SPing-Ke Shih return -EINVAL; 3208e3ec7017SPing-Ke Shih } 3209e3ec7017SPing-Ke Shih 3210aabe741eSPing-Ke Shih if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3211e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3212e3ec7017SPing-Ke Shih return -EINVAL; 3213e3ec7017SPing-Ke Shih } 3214e3ec7017SPing-Ke Shih 3215e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3216e3ec7017SPing-Ke Shih 3217b6e65d18SPing-Ke Shih return mac->dle_quota_change(rtwdev, band1_en); 3218b6e65d18SPing-Ke Shih } 3219b6e65d18SPing-Ke Shih 3220b6e65d18SPing-Ke Shih static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3221b6e65d18SPing-Ke Shih { 3222b6e65d18SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3223b6e65d18SPing-Ke Shih struct rtw89_cpuio_ctrl ctrl_para = {0}; 3224b6e65d18SPing-Ke Shih u16 pkt_id; 3225b6e65d18SPing-Ke Shih int ret; 3226b6e65d18SPing-Ke Shih 322739e9b569SPing-Ke Shih ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3228eaddda24SPing-Ke Shih if (ret) { 3229e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3230eaddda24SPing-Ke Shih return ret; 3231e3ec7017SPing-Ke Shih } 3232e3ec7017SPing-Ke Shih 3233e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3234e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 3235e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 3236e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 3237e3ec7017SPing-Ke Shih ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3238e3ec7017SPing-Ke Shih ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 323939e9b569SPing-Ke Shih ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3240e3ec7017SPing-Ke Shih if (ret) { 3241e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3242e3ec7017SPing-Ke Shih return -EFAULT; 3243e3ec7017SPing-Ke Shih } 3244e3ec7017SPing-Ke Shih 324539e9b569SPing-Ke Shih ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3246eaddda24SPing-Ke Shih if (ret) { 3247e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3248eaddda24SPing-Ke Shih return ret; 3249e3ec7017SPing-Ke Shih } 3250e3ec7017SPing-Ke Shih 3251e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3252e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 3253e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 3254e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 3255e3ec7017SPing-Ke Shih ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3256e3ec7017SPing-Ke Shih ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 325739e9b569SPing-Ke Shih ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3258e3ec7017SPing-Ke Shih if (ret) { 3259e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3260e3ec7017SPing-Ke Shih return -EFAULT; 3261e3ec7017SPing-Ke Shih } 3262e3ec7017SPing-Ke Shih 3263e3ec7017SPing-Ke Shih return 0; 3264e3ec7017SPing-Ke Shih } 3265e3ec7017SPing-Ke Shih 3266e3ec7017SPing-Ke Shih static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3267e3ec7017SPing-Ke Shih { 3268e3ec7017SPing-Ke Shih int ret; 3269e3ec7017SPing-Ke Shih u32 reg; 3270e3ec7017SPing-Ke Shih u8 val; 3271e3ec7017SPing-Ke Shih 3272e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3273e3ec7017SPing-Ke Shih if (ret) 3274e3ec7017SPing-Ke Shih return ret; 3275e3ec7017SPing-Ke Shih 3276c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3277e3ec7017SPing-Ke Shih 3278e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, 3279e3ec7017SPing-Ke Shih (val & B_AX_PTCL_TX_ON_STAT) == 0, 3280e3ec7017SPing-Ke Shih SW_CVR_DUR_US, 3281e3ec7017SPing-Ke Shih SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3282e3ec7017SPing-Ke Shih false, rtwdev, reg); 3283e3ec7017SPing-Ke Shih if (ret) 3284e3ec7017SPing-Ke Shih return ret; 3285e3ec7017SPing-Ke Shih 3286e3ec7017SPing-Ke Shih return 0; 3287e3ec7017SPing-Ke Shih } 3288e3ec7017SPing-Ke Shih 3289fc663fa0SPing-Ke Shih static int band1_enable_ax(struct rtw89_dev *rtwdev) 3290e3ec7017SPing-Ke Shih { 3291e3ec7017SPing-Ke Shih int ret, i; 3292e3ec7017SPing-Ke Shih u32 sleep_bak[4] = {0}; 3293e3ec7017SPing-Ke Shih u32 pause_bak[4] = {0}; 3294d780f926SPing-Ke Shih u32 tx_en; 3295e3ec7017SPing-Ke Shih 3296de7ba639SPing-Ke Shih ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3297e3ec7017SPing-Ke Shih if (ret) { 3298e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3299e3ec7017SPing-Ke Shih return ret; 3300e3ec7017SPing-Ke Shih } 3301e3ec7017SPing-Ke Shih 3302e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 3303e3ec7017SPing-Ke Shih sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3304e3ec7017SPing-Ke Shih pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3305e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3306e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3307e3ec7017SPing-Ke Shih } 3308e3ec7017SPing-Ke Shih 3309e3ec7017SPing-Ke Shih ret = band_idle_ck_b(rtwdev, 0); 3310e3ec7017SPing-Ke Shih if (ret) { 3311e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3312e3ec7017SPing-Ke Shih return ret; 3313e3ec7017SPing-Ke Shih } 3314e3ec7017SPing-Ke Shih 3315b6e65d18SPing-Ke Shih ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3316e3ec7017SPing-Ke Shih if (ret) { 3317e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3318e3ec7017SPing-Ke Shih return ret; 3319e3ec7017SPing-Ke Shih } 3320e3ec7017SPing-Ke Shih 3321e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 3322e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3323e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3324e3ec7017SPing-Ke Shih } 3325e3ec7017SPing-Ke Shih 3326de7ba639SPing-Ke Shih ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3327e3ec7017SPing-Ke Shih if (ret) { 3328e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3329e3ec7017SPing-Ke Shih return ret; 3330e3ec7017SPing-Ke Shih } 3331e3ec7017SPing-Ke Shih 3332fc663fa0SPing-Ke Shih ret = cmac_func_en_ax(rtwdev, 1, true); 3333e3ec7017SPing-Ke Shih if (ret) { 3334e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3335e3ec7017SPing-Ke Shih return ret; 3336e3ec7017SPing-Ke Shih } 3337e3ec7017SPing-Ke Shih 3338fc663fa0SPing-Ke Shih ret = cmac_init_ax(rtwdev, 1); 3339e3ec7017SPing-Ke Shih if (ret) { 3340e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3341e3ec7017SPing-Ke Shih return ret; 3342e3ec7017SPing-Ke Shih } 3343e3ec7017SPing-Ke Shih 3344e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3345e3ec7017SPing-Ke Shih B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3346e3ec7017SPing-Ke Shih 3347e3ec7017SPing-Ke Shih return 0; 3348e3ec7017SPing-Ke Shih } 3349e3ec7017SPing-Ke Shih 3350eeadcd2aSChia-Yuan Li static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3351eeadcd2aSChia-Yuan Li { 3352eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3353eeadcd2aSChia-Yuan Li 3354eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3355eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3356eeadcd2aSChia-Yuan Li } 3357eeadcd2aSChia-Yuan Li 3358eeadcd2aSChia-Yuan Li static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3359eeadcd2aSChia-Yuan Li { 3360eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3361eeadcd2aSChia-Yuan Li 3362eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3363eeadcd2aSChia-Yuan Li } 3364eeadcd2aSChia-Yuan Li 3365eeadcd2aSChia-Yuan Li static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3366eeadcd2aSChia-Yuan Li { 3367eeadcd2aSChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3368eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3369eeadcd2aSChia-Yuan Li 3370eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3371eeadcd2aSChia-Yuan Li B_AX_TX_GET_ERRPKTID_INT_EN | 3372eeadcd2aSChia-Yuan Li B_AX_TX_NXT_ERRPKTID_INT_EN | 3373eeadcd2aSChia-Yuan Li B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3374eeadcd2aSChia-Yuan Li B_AX_TX_OFFSET_ERR_INT_EN | 3375eeadcd2aSChia-Yuan Li B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3376eeadcd2aSChia-Yuan Li if (chip_id == RTL8852C) 3377eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3378eeadcd2aSChia-Yuan Li B_AX_TX_ETH_TYPE_ERR_EN | 3379eeadcd2aSChia-Yuan Li B_AX_TX_LLC_PRE_ERR_EN | 3380eeadcd2aSChia-Yuan Li B_AX_TX_NW_TYPE_ERR_EN | 3381eeadcd2aSChia-Yuan Li B_AX_TX_KSRCH_ERR_EN); 3382eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3383eeadcd2aSChia-Yuan Li imr->mpdu_tx_imr_set); 3384eeadcd2aSChia-Yuan Li 3385eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3386eeadcd2aSChia-Yuan Li B_AX_GETPKTID_ERR_INT_EN | 3387eeadcd2aSChia-Yuan Li B_AX_MHDRLEN_ERR_INT_EN | 3388eeadcd2aSChia-Yuan Li B_AX_RPT_ERR_INT_EN); 3389eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3390eeadcd2aSChia-Yuan Li imr->mpdu_rx_imr_set); 3391eeadcd2aSChia-Yuan Li } 3392eeadcd2aSChia-Yuan Li 3393eeadcd2aSChia-Yuan Li static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3394eeadcd2aSChia-Yuan Li { 3395eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3396eeadcd2aSChia-Yuan Li 3397eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3398eeadcd2aSChia-Yuan Li B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3399eeadcd2aSChia-Yuan Li B_AX_RPT_HANG_TIMEOUT_INT_EN | 3400eeadcd2aSChia-Yuan Li B_AX_PLE_B_PKTID_ERR_INT_EN); 3401eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3402eeadcd2aSChia-Yuan Li imr->sta_sch_imr_set); 3403eeadcd2aSChia-Yuan Li } 3404eeadcd2aSChia-Yuan Li 3405eeadcd2aSChia-Yuan Li static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3406eeadcd2aSChia-Yuan Li { 3407eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3408eeadcd2aSChia-Yuan Li 3409eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3410eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b0_clr); 3411eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3412eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b0_set); 3413eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3414eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b1_clr); 3415eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3416eeadcd2aSChia-Yuan Li imr->txpktctl_imr_b1_set); 3417eeadcd2aSChia-Yuan Li } 3418eeadcd2aSChia-Yuan Li 3419eeadcd2aSChia-Yuan Li static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3420eeadcd2aSChia-Yuan Li { 3421eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3422eeadcd2aSChia-Yuan Li 3423eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3424eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3425eeadcd2aSChia-Yuan Li } 3426eeadcd2aSChia-Yuan Li 3427eeadcd2aSChia-Yuan Li static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3428eeadcd2aSChia-Yuan Li { 3429eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3430eeadcd2aSChia-Yuan Li 3431eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3432eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3433eeadcd2aSChia-Yuan Li } 3434eeadcd2aSChia-Yuan Li 3435eeadcd2aSChia-Yuan Li static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3436eeadcd2aSChia-Yuan Li { 3437eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3438eeadcd2aSChia-Yuan Li B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3439eeadcd2aSChia-Yuan Li } 3440eeadcd2aSChia-Yuan Li 3441eeadcd2aSChia-Yuan Li static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3442eeadcd2aSChia-Yuan Li { 3443eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3444eeadcd2aSChia-Yuan Li 3445eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3446eeadcd2aSChia-Yuan Li imr->host_disp_imr_clr); 3447eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3448eeadcd2aSChia-Yuan Li imr->host_disp_imr_set); 3449eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3450eeadcd2aSChia-Yuan Li imr->cpu_disp_imr_clr); 3451eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3452eeadcd2aSChia-Yuan Li imr->cpu_disp_imr_set); 3453eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3454eeadcd2aSChia-Yuan Li imr->other_disp_imr_clr); 3455eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3456eeadcd2aSChia-Yuan Li imr->other_disp_imr_set); 3457eeadcd2aSChia-Yuan Li } 3458eeadcd2aSChia-Yuan Li 3459eeadcd2aSChia-Yuan Li static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3460eeadcd2aSChia-Yuan Li { 3461eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3462eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3463eeadcd2aSChia-Yuan Li } 3464eeadcd2aSChia-Yuan Li 3465eeadcd2aSChia-Yuan Li static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3466eeadcd2aSChia-Yuan Li { 3467eeadcd2aSChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3468eeadcd2aSChia-Yuan Li 346975f1ed29SPing-Ke Shih rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3470eeadcd2aSChia-Yuan Li B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3471eeadcd2aSChia-Yuan Li rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3472eeadcd2aSChia-Yuan Li B_AX_BBRPT_CHINFO_IMR_CLR); 3473eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3474eeadcd2aSChia-Yuan Li imr->bbrpt_err_imr_set); 3475eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3476eeadcd2aSChia-Yuan Li B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3477eeadcd2aSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3478eeadcd2aSChia-Yuan Li } 3479eeadcd2aSChia-Yuan Li 3480d86369e9SChia-Yuan Li static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3481d86369e9SChia-Yuan Li { 3482d86369e9SChia-Yuan Li u32 reg; 3483d86369e9SChia-Yuan Li 3484c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3485d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3486d86369e9SChia-Yuan Li B_AX_FSM_TIMEOUT_ERR_INT_EN); 3487d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3488d86369e9SChia-Yuan Li } 3489d86369e9SChia-Yuan Li 3490d86369e9SChia-Yuan Li static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3491d86369e9SChia-Yuan Li { 3492d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3493d86369e9SChia-Yuan Li u32 reg; 3494d86369e9SChia-Yuan Li 3495c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3496d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3497d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3498d86369e9SChia-Yuan Li } 3499d86369e9SChia-Yuan Li 3500d86369e9SChia-Yuan Li static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3501d86369e9SChia-Yuan Li { 3502d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3503d86369e9SChia-Yuan Li enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3504d86369e9SChia-Yuan Li u32 reg; 3505d86369e9SChia-Yuan Li 3506c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3507d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3508d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3509d86369e9SChia-Yuan Li 3510d86369e9SChia-Yuan Li if (chip_id == RTL8852C) { 3511c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3512d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3513d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3514d86369e9SChia-Yuan Li } 3515d86369e9SChia-Yuan Li } 3516d86369e9SChia-Yuan Li 3517d86369e9SChia-Yuan Li static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3518d86369e9SChia-Yuan Li { 3519d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3520d86369e9SChia-Yuan Li u32 reg; 3521d86369e9SChia-Yuan Li 3522c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3523d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3524d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3525d86369e9SChia-Yuan Li } 3526d86369e9SChia-Yuan Li 3527d86369e9SChia-Yuan Li static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3528d86369e9SChia-Yuan Li { 3529d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3530d86369e9SChia-Yuan Li u32 reg; 3531d86369e9SChia-Yuan Li 3532c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3533d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3534d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3535d86369e9SChia-Yuan Li } 3536d86369e9SChia-Yuan Li 3537d86369e9SChia-Yuan Li static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3538d86369e9SChia-Yuan Li { 3539d86369e9SChia-Yuan Li const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3540d86369e9SChia-Yuan Li u32 reg; 3541d86369e9SChia-Yuan Li 3542c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3543d86369e9SChia-Yuan Li rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3544d86369e9SChia-Yuan Li rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3545d86369e9SChia-Yuan Li } 3546d86369e9SChia-Yuan Li 3547fc663fa0SPing-Ke Shih static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3548e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 3549e3ec7017SPing-Ke Shih { 3550e3ec7017SPing-Ke Shih int ret; 3551e3ec7017SPing-Ke Shih 3552e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3553e3ec7017SPing-Ke Shih if (ret) { 3554e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3555e3ec7017SPing-Ke Shih sel, mac_idx); 3556e3ec7017SPing-Ke Shih return ret; 3557e3ec7017SPing-Ke Shih } 3558e3ec7017SPing-Ke Shih 3559e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 3560eeadcd2aSChia-Yuan Li rtw89_wdrls_imr_enable(rtwdev); 3561eeadcd2aSChia-Yuan Li rtw89_wsec_imr_enable(rtwdev); 3562eeadcd2aSChia-Yuan Li rtw89_mpdu_trx_imr_enable(rtwdev); 3563eeadcd2aSChia-Yuan Li rtw89_sta_sch_imr_enable(rtwdev); 3564eeadcd2aSChia-Yuan Li rtw89_txpktctl_imr_enable(rtwdev); 3565eeadcd2aSChia-Yuan Li rtw89_wde_imr_enable(rtwdev); 3566eeadcd2aSChia-Yuan Li rtw89_ple_imr_enable(rtwdev); 3567eeadcd2aSChia-Yuan Li rtw89_pktin_imr_enable(rtwdev); 3568eeadcd2aSChia-Yuan Li rtw89_dispatcher_imr_enable(rtwdev); 3569eeadcd2aSChia-Yuan Li rtw89_cpuio_imr_enable(rtwdev); 3570eeadcd2aSChia-Yuan Li rtw89_bbrpt_imr_enable(rtwdev); 3571e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL) { 3572d86369e9SChia-Yuan Li rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3573d86369e9SChia-Yuan Li rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3574d86369e9SChia-Yuan Li rtw89_cdma_imr_enable(rtwdev, mac_idx); 3575d86369e9SChia-Yuan Li rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3576d86369e9SChia-Yuan Li rtw89_rmac_imr_enable(rtwdev, mac_idx); 3577d86369e9SChia-Yuan Li rtw89_tmac_imr_enable(rtwdev, mac_idx); 3578e3ec7017SPing-Ke Shih } else { 3579e3ec7017SPing-Ke Shih return -EINVAL; 3580e3ec7017SPing-Ke Shih } 3581e3ec7017SPing-Ke Shih 3582e3ec7017SPing-Ke Shih return 0; 3583e3ec7017SPing-Ke Shih } 3584e3ec7017SPing-Ke Shih 3585fc663fa0SPing-Ke Shih static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 35869f405b01SPing-Ke Shih { 35879f405b01SPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 35889f405b01SPing-Ke Shih 35899f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 35909f405b01SPing-Ke Shih en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 35919f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 35929f405b01SPing-Ke Shih en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 35939f405b01SPing-Ke Shih if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 35949f405b01SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 35959f405b01SPing-Ke Shih en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 35969f405b01SPing-Ke Shih } 35979f405b01SPing-Ke Shih 3598fc663fa0SPing-Ke Shih static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3599e3ec7017SPing-Ke Shih { 3600e3ec7017SPing-Ke Shih int ret = 0; 3601e3ec7017SPing-Ke Shih 3602e3ec7017SPing-Ke Shih if (enable) { 3603fc663fa0SPing-Ke Shih ret = band1_enable_ax(rtwdev); 3604e3ec7017SPing-Ke Shih if (ret) { 3605e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3606e3ec7017SPing-Ke Shih return ret; 3607e3ec7017SPing-Ke Shih } 3608e3ec7017SPing-Ke Shih 3609fc663fa0SPing-Ke Shih ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3610e3ec7017SPing-Ke Shih if (ret) { 3611e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3612e3ec7017SPing-Ke Shih return ret; 3613e3ec7017SPing-Ke Shih } 3614e3ec7017SPing-Ke Shih } else { 3615e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3616e3ec7017SPing-Ke Shih return -EINVAL; 3617e3ec7017SPing-Ke Shih } 3618e3ec7017SPing-Ke Shih 3619e3ec7017SPing-Ke Shih return 0; 3620e3ec7017SPing-Ke Shih } 3621e3ec7017SPing-Ke Shih 3622fc663fa0SPing-Ke Shih static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3623e3ec7017SPing-Ke Shih { 3624e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3625e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3626e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3627e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3628e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 3629e3ec7017SPing-Ke Shih } else { 3630e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3631e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3632e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3633e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 3634e3ec7017SPing-Ke Shih } 3635e3ec7017SPing-Ke Shih 3636e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3637e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3638e3ec7017SPing-Ke Shih 3639e3ec7017SPing-Ke Shih return 0; 3640e3ec7017SPing-Ke Shih } 3641e3ec7017SPing-Ke Shih 3642fc663fa0SPing-Ke Shih static int trx_init_ax(struct rtw89_dev *rtwdev) 3643e3ec7017SPing-Ke Shih { 3644e3ec7017SPing-Ke Shih enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3645e3ec7017SPing-Ke Shih int ret; 3646e3ec7017SPing-Ke Shih 3647fc663fa0SPing-Ke Shih ret = dmac_init_ax(rtwdev, 0); 3648e3ec7017SPing-Ke Shih if (ret) { 3649e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3650e3ec7017SPing-Ke Shih return ret; 3651e3ec7017SPing-Ke Shih } 3652e3ec7017SPing-Ke Shih 3653fc663fa0SPing-Ke Shih ret = cmac_init_ax(rtwdev, 0); 3654e3ec7017SPing-Ke Shih if (ret) { 3655e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3656e3ec7017SPing-Ke Shih return ret; 3657e3ec7017SPing-Ke Shih } 3658e3ec7017SPing-Ke Shih 3659fc663fa0SPing-Ke Shih if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3660fc663fa0SPing-Ke Shih ret = dbcc_enable_ax(rtwdev, true); 3661e3ec7017SPing-Ke Shih if (ret) { 3662e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3663e3ec7017SPing-Ke Shih return ret; 3664e3ec7017SPing-Ke Shih } 3665e3ec7017SPing-Ke Shih } 3666e3ec7017SPing-Ke Shih 3667fc663fa0SPing-Ke Shih ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3668e3ec7017SPing-Ke Shih if (ret) { 3669e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3670e3ec7017SPing-Ke Shih return ret; 3671e3ec7017SPing-Ke Shih } 3672e3ec7017SPing-Ke Shih 3673fc663fa0SPing-Ke Shih ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3674e3ec7017SPing-Ke Shih if (ret) { 3675e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3676e3ec7017SPing-Ke Shih return ret; 3677e3ec7017SPing-Ke Shih } 3678e3ec7017SPing-Ke Shih 3679fc663fa0SPing-Ke Shih err_imr_ctrl_ax(rtwdev, true); 36809f405b01SPing-Ke Shih 3681fc663fa0SPing-Ke Shih ret = set_host_rpr_ax(rtwdev); 3682e3ec7017SPing-Ke Shih if (ret) { 3683e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3684e3ec7017SPing-Ke Shih return ret; 3685e3ec7017SPing-Ke Shih } 3686e3ec7017SPing-Ke Shih 3687e3ec7017SPing-Ke Shih return 0; 3688e3ec7017SPing-Ke Shih } 3689e3ec7017SPing-Ke Shih 36903b96833aSPing-Ke Shih static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 36913b96833aSPing-Ke Shih { 36923b96833aSPing-Ke Shih #define BACAM_1024BMP_OCC_ENTRY 4 36933b96833aSPing-Ke Shih #define BACAM_MAX_RU_SUPPORT_B0_STA 1 36943b96833aSPing-Ke Shih #define BACAM_MAX_RU_SUPPORT_B1_STA 1 36953b96833aSPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 36963b96833aSPing-Ke Shih u8 users, offset; 36973b96833aSPing-Ke Shih 36983b96833aSPing-Ke Shih if (chip->bacam_ver != RTW89_BACAM_V1) 36993b96833aSPing-Ke Shih return 0; 37003b96833aSPing-Ke Shih 37013b96833aSPing-Ke Shih offset = 0; 37023b96833aSPing-Ke Shih users = BACAM_MAX_RU_SUPPORT_B0_STA; 37033b96833aSPing-Ke Shih rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 37043b96833aSPing-Ke Shih 37053b96833aSPing-Ke Shih offset += users * BACAM_1024BMP_OCC_ENTRY; 37063b96833aSPing-Ke Shih users = BACAM_MAX_RU_SUPPORT_B1_STA; 37073b96833aSPing-Ke Shih rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 37083b96833aSPing-Ke Shih 37093b96833aSPing-Ke Shih return 0; 37103b96833aSPing-Ke Shih } 37113b96833aSPing-Ke Shih 3712ec356ffbSChia-Yuan Li static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3713ec356ffbSChia-Yuan Li { 37145c3afcbaSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3715ec356ffbSChia-Yuan Li u32 val32; 3716ec356ffbSChia-Yuan Li 37175c3afcbaSPing-Ke Shih if (chip_id == RTL8852B || chip_id == RTL8851B) { 37185c3afcbaSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 37195c3afcbaSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 37205c3afcbaSPing-Ke Shih return; 37215c3afcbaSPing-Ke Shih } 37225c3afcbaSPing-Ke Shih 3723ec356ffbSChia-Yuan Li rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3724ec356ffbSChia-Yuan Li WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3725ec356ffbSChia-Yuan Li 3726ec356ffbSChia-Yuan Li val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3727ec356ffbSChia-Yuan Li val32 |= B_AX_FS_WDT_INT; 3728ec356ffbSChia-Yuan Li val32 &= ~B_AX_FS_WDT_INT_MSK; 3729ec356ffbSChia-Yuan Li rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3730ec356ffbSChia-Yuan Li } 3731ec356ffbSChia-Yuan Li 3732ae4dc23dSPing-Ke Shih static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3733e3ec7017SPing-Ke Shih { 3734e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3735e3ec7017SPing-Ke Shih 3736e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3737de78869dSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3738de78869dSChia-Yuan Li B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3739e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3740ec356ffbSChia-Yuan Li 3741ec356ffbSChia-Yuan Li rtw89_disable_fw_watchdog(rtwdev); 3742ec356ffbSChia-Yuan Li 3743de78869dSChia-Yuan Li rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3744de78869dSChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3745e3ec7017SPing-Ke Shih } 3746e3ec7017SPing-Ke Shih 3747a712eef6SPing-Ke Shih static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3748a712eef6SPing-Ke Shih bool dlfw, bool include_bb) 3749e3ec7017SPing-Ke Shih { 3750e3ec7017SPing-Ke Shih u32 val; 3751e3ec7017SPing-Ke Shih int ret; 3752e3ec7017SPing-Ke Shih 3753e3ec7017SPing-Ke Shih if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3754e3ec7017SPing-Ke Shih return -EFAULT; 3755e3ec7017SPing-Ke Shih 3756e749ef96SPing-Ke Shih rtw89_write32(rtwdev, R_AX_UDM1, 0); 3757e749ef96SPing-Ke Shih rtw89_write32(rtwdev, R_AX_UDM2, 0); 3758e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3759e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3760a63ae673SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3761a63ae673SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3762e3ec7017SPing-Ke Shih 3763e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3764e3ec7017SPing-Ke Shih 3765e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3766e3ec7017SPing-Ke Shih val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3767e3ec7017SPing-Ke Shih val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3768e3ec7017SPing-Ke Shih B_AX_WCPU_FWDL_STS_MASK); 3769e3ec7017SPing-Ke Shih 3770e3ec7017SPing-Ke Shih if (dlfw) 3771e3ec7017SPing-Ke Shih val |= B_AX_WCPU_FWDL_EN; 3772e3ec7017SPing-Ke Shih 3773e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 37742e5a65f5SPing-Ke Shih 37752e5a65f5SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852B) 37762e5a65f5SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 37772e5a65f5SPing-Ke Shih B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 37782e5a65f5SPing-Ke Shih 3779e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3780e3ec7017SPing-Ke Shih boot_reason); 3781e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3782e3ec7017SPing-Ke Shih 3783e3ec7017SPing-Ke Shih if (!dlfw) { 3784e3ec7017SPing-Ke Shih mdelay(5); 3785e3ec7017SPing-Ke Shih 3786fa31a8c5SPing-Ke Shih ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3787e3ec7017SPing-Ke Shih if (ret) 3788e3ec7017SPing-Ke Shih return ret; 3789e3ec7017SPing-Ke Shih } 3790e3ec7017SPing-Ke Shih 3791e3ec7017SPing-Ke Shih return 0; 3792e3ec7017SPing-Ke Shih } 3793e3ec7017SPing-Ke Shih 379439e9b569SPing-Ke Shih static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 3795e3ec7017SPing-Ke Shih { 3796a7d82a7aSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3797e3ec7017SPing-Ke Shih u32 val; 3798e3ec7017SPing-Ke Shih 3799a7d82a7aSPing-Ke Shih if (chip_id == RTL8852C) 3800a7d82a7aSPing-Ke Shih val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3801a7d82a7aSPing-Ke Shih B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3802a7d82a7aSPing-Ke Shih else 3803e3ec7017SPing-Ke Shih val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3804e3ec7017SPing-Ke Shih B_AX_PKT_BUF_EN; 3805e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 38060d16d8fbSPing-Ke Shih } 38070d16d8fbSPing-Ke Shih 380839e9b569SPing-Ke Shih static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 38090d16d8fbSPing-Ke Shih { 38100d16d8fbSPing-Ke Shih enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 38110d16d8fbSPing-Ke Shih u32 val; 3812e3ec7017SPing-Ke Shih 38135c3afcbaSPing-Ke Shih if (chip_id == RTL8851B) 38145c3afcbaSPing-Ke Shih val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 38155c3afcbaSPing-Ke Shih else 3816e3ec7017SPing-Ke Shih val = B_AX_DISPATCHER_CLK_EN; 3817e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3818e3ec7017SPing-Ke Shih 3819a7d82a7aSPing-Ke Shih if (chip_id != RTL8852C) 38200d16d8fbSPing-Ke Shih return; 3821a7d82a7aSPing-Ke Shih 3822a7d82a7aSPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3823a7d82a7aSPing-Ke Shih val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3824a7d82a7aSPing-Ke Shih val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3825a7d82a7aSPing-Ke Shih B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3826a7d82a7aSPing-Ke Shih rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3827a7d82a7aSPing-Ke Shih 3828a7d82a7aSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3829a7d82a7aSPing-Ke Shih B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3830a7d82a7aSPing-Ke Shih B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3831a7d82a7aSPing-Ke Shih B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3832a7d82a7aSPing-Ke Shih B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3833a7d82a7aSPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3834a7d82a7aSPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 38350d16d8fbSPing-Ke Shih } 3836a7d82a7aSPing-Ke Shih 38370d16d8fbSPing-Ke Shih static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 38380d16d8fbSPing-Ke Shih { 383939e9b569SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 38400d16d8fbSPing-Ke Shih int ret; 38410d16d8fbSPing-Ke Shih 384239e9b569SPing-Ke Shih mac->hci_func_en(rtwdev); 384339e9b569SPing-Ke Shih mac->dmac_func_pre_en(rtwdev); 38440d16d8fbSPing-Ke Shih 3845fc663fa0SPing-Ke Shih ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3846e3ec7017SPing-Ke Shih if (ret) { 3847e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3848e3ec7017SPing-Ke Shih return ret; 3849e3ec7017SPing-Ke Shih } 3850e3ec7017SPing-Ke Shih 3851fc663fa0SPing-Ke Shih ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 3852e3ec7017SPing-Ke Shih if (ret) { 3853e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3854e3ec7017SPing-Ke Shih return ret; 3855e3ec7017SPing-Ke Shih } 3856e3ec7017SPing-Ke Shih 3857e3ec7017SPing-Ke Shih return ret; 3858e3ec7017SPing-Ke Shih } 3859e3ec7017SPing-Ke Shih 386061ebeecbSPing-Ke Shih int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3861e3ec7017SPing-Ke Shih { 3862e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3863e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3864e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3865e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3866e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3867e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 386861ebeecbSPing-Ke Shih 386961ebeecbSPing-Ke Shih return 0; 3870e3ec7017SPing-Ke Shih } 387161ebeecbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3872e3ec7017SPing-Ke Shih 387314b6e9f4SPing-Ke Shih int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3874e3ec7017SPing-Ke Shih { 3875e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3876e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3877e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3878e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3879e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3880e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 388114b6e9f4SPing-Ke Shih 388214b6e9f4SPing-Ke Shih return 0; 3883e3ec7017SPing-Ke Shih } 388461ebeecbSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3885e3ec7017SPing-Ke Shih 3886a712eef6SPing-Ke Shih int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 3887e3ec7017SPing-Ke Shih { 3888e3ec7017SPing-Ke Shih int ret; 3889e3ec7017SPing-Ke Shih 3890e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 3891e3ec7017SPing-Ke Shih if (ret) { 3892e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 3893e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 3894e3ec7017SPing-Ke Shih if (ret) 3895e3ec7017SPing-Ke Shih return ret; 3896e3ec7017SPing-Ke Shih } 3897e3ec7017SPing-Ke Shih 389852f12705SChin-Yen Lee rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3899e3ec7017SPing-Ke Shih 3900c6ea2a83SPing-Ke Shih if (include_bb) { 3901c6ea2a83SPing-Ke Shih rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 3902c6ea2a83SPing-Ke Shih if (rtwdev->dbcc_en) 3903c6ea2a83SPing-Ke Shih rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 3904c6ea2a83SPing-Ke Shih } 3905c6ea2a83SPing-Ke Shih 3906a7d82a7aSPing-Ke Shih ret = rtw89_mac_dmac_pre_init(rtwdev); 3907a7d82a7aSPing-Ke Shih if (ret) 3908a7d82a7aSPing-Ke Shih return ret; 3909a7d82a7aSPing-Ke Shih 3910e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_pre_init) { 3911e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3912e3ec7017SPing-Ke Shih if (ret) 3913e3ec7017SPing-Ke Shih return ret; 3914e3ec7017SPing-Ke Shih } 3915e3ec7017SPing-Ke Shih 3916a712eef6SPing-Ke Shih ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 3917e3ec7017SPing-Ke Shih if (ret) 3918e3ec7017SPing-Ke Shih return ret; 3919e3ec7017SPing-Ke Shih 3920e3ec7017SPing-Ke Shih return 0; 3921e3ec7017SPing-Ke Shih } 3922e3ec7017SPing-Ke Shih 3923e3ec7017SPing-Ke Shih int rtw89_mac_init(struct rtw89_dev *rtwdev) 3924e3ec7017SPing-Ke Shih { 3925fc663fa0SPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3926a712eef6SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 3927a712eef6SPing-Ke Shih bool include_bb = !!chip->bbmcu_nr; 3928e3ec7017SPing-Ke Shih int ret; 3929e3ec7017SPing-Ke Shih 3930a712eef6SPing-Ke Shih ret = rtw89_mac_partial_init(rtwdev, include_bb); 3931e3ec7017SPing-Ke Shih if (ret) 3932e3ec7017SPing-Ke Shih goto fail; 3933e3ec7017SPing-Ke Shih 393461ebeecbSPing-Ke Shih ret = rtw89_chip_enable_bb_rf(rtwdev); 393561ebeecbSPing-Ke Shih if (ret) 393661ebeecbSPing-Ke Shih goto fail; 3937e3ec7017SPing-Ke Shih 3938fc663fa0SPing-Ke Shih ret = mac->sys_init(rtwdev); 3939e3ec7017SPing-Ke Shih if (ret) 3940e3ec7017SPing-Ke Shih goto fail; 3941e3ec7017SPing-Ke Shih 3942fc663fa0SPing-Ke Shih ret = mac->trx_init(rtwdev); 3943e3ec7017SPing-Ke Shih if (ret) 3944e3ec7017SPing-Ke Shih goto fail; 3945e3ec7017SPing-Ke Shih 39463b96833aSPing-Ke Shih ret = rtw89_mac_feat_init(rtwdev); 39473b96833aSPing-Ke Shih if (ret) 39483b96833aSPing-Ke Shih goto fail; 39493b96833aSPing-Ke Shih 3950e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_post_init) { 3951e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3952e3ec7017SPing-Ke Shih if (ret) 3953e3ec7017SPing-Ke Shih goto fail; 3954e3ec7017SPing-Ke Shih } 3955e3ec7017SPing-Ke Shih 3956e3ec7017SPing-Ke Shih rtw89_fw_send_all_early_h2c(rtwdev); 3957e3ec7017SPing-Ke Shih rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3958e3ec7017SPing-Ke Shih 3959e3ec7017SPing-Ke Shih return ret; 3960e3ec7017SPing-Ke Shih fail: 3961e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 3962e3ec7017SPing-Ke Shih 3963e3ec7017SPing-Ke Shih return ret; 3964e3ec7017SPing-Ke Shih } 3965e3ec7017SPing-Ke Shih 3966e3ec7017SPing-Ke Shih static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3967e3ec7017SPing-Ke Shih { 3968e3ec7017SPing-Ke Shih u8 i; 3969e3ec7017SPing-Ke Shih 397060168f6cSPing-Ke Shih if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 397160168f6cSPing-Ke Shih return; 397260168f6cSPing-Ke Shih 3973e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 3974e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3975e3ec7017SPing-Ke Shih DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3976e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3977e3ec7017SPing-Ke Shih } 3978e3ec7017SPing-Ke Shih } 3979e3ec7017SPing-Ke Shih 3980e3ec7017SPing-Ke Shih static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3981e3ec7017SPing-Ke Shih { 398260168f6cSPing-Ke Shih if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 398360168f6cSPing-Ke Shih return; 398460168f6cSPing-Ke Shih 3985e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3986e3ec7017SPing-Ke Shih CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3987e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3988e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3989e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3990e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3991e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3992e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3993e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3994e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3995e3ec7017SPing-Ke Shih } 3996e3ec7017SPing-Ke Shih 39971b73e77dSPing-Ke Shih int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3998e3ec7017SPing-Ke Shih { 3999e3ec7017SPing-Ke Shih u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4000e3ec7017SPing-Ke Shih u8 grp = macid >> 5; 4001e3ec7017SPing-Ke Shih int ret; 4002e3ec7017SPing-Ke Shih 4003ac3a9f18SPing-Ke Shih /* If this is called by change_interface() in the case of P2P, it could 4004ac3a9f18SPing-Ke Shih * be power-off, so ignore this operation. 4005ac3a9f18SPing-Ke Shih */ 4006ac3a9f18SPing-Ke Shih if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4007ac3a9f18SPing-Ke Shih !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4008ac3a9f18SPing-Ke Shih return 0; 4009ac3a9f18SPing-Ke Shih 4010e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4011e3ec7017SPing-Ke Shih if (ret) 4012e3ec7017SPing-Ke Shih return ret; 4013e3ec7017SPing-Ke Shih 4014e3ec7017SPing-Ke Shih rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4015e3ec7017SPing-Ke Shih 4016e3ec7017SPing-Ke Shih return 0; 4017e3ec7017SPing-Ke Shih } 4018e3ec7017SPing-Ke Shih 40197c8a55ddSPing-Ke Shih static const struct rtw89_port_reg rtw89_port_base_ax = { 4020e3ec7017SPing-Ke Shih .port_cfg = R_AX_PORT_CFG_P0, 4021e3ec7017SPing-Ke Shih .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4022e3ec7017SPing-Ke Shih .bcn_area = R_AX_BCN_AREA_P0, 4023e3ec7017SPing-Ke Shih .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4024e3ec7017SPing-Ke Shih .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4025e3ec7017SPing-Ke Shih .tbtt_agg = R_AX_TBTT_AGG_P0, 4026e3ec7017SPing-Ke Shih .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4027e3ec7017SPing-Ke Shih .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4028e3ec7017SPing-Ke Shih .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4029e3ec7017SPing-Ke Shih .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4030e3ec7017SPing-Ke Shih .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4031e3ec7017SPing-Ke Shih .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4032e3ec7017SPing-Ke Shih .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4033e3ec7017SPing-Ke Shih .tsftr_l = R_AX_TSFTR_LOW_P0, 403465129813SPing-Ke Shih .tsftr_h = R_AX_TSFTR_HIGH_P0, 403565129813SPing-Ke Shih .md_tsft = R_AX_MD_TSFT_STMP_CTL, 403665129813SPing-Ke Shih .bss_color = R_AX_PTCL_BSS_COLOR_0, 403765129813SPing-Ke Shih .mbssid = R_AX_MBSSID_CTRL, 403865129813SPing-Ke Shih .mbssid_drop = R_AX_MBSSID_DROP_0, 403965129813SPing-Ke Shih .tsf_sync = R_AX_PORT0_TSF_SYNC, 4040*598481c6SChih-Kang Chang .ptcl_dbg = R_AX_PTCL_DBG, 4041*598481c6SChih-Kang Chang .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4042*598481c6SChih-Kang Chang .bcn_drop_all = R_AX_BCN_DROP_ALL0, 404365129813SPing-Ke Shih .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 404465129813SPing-Ke Shih R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 404565129813SPing-Ke Shih R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4046e3ec7017SPing-Ke Shih }; 4047e3ec7017SPing-Ke Shih 40480052b3c4SPo-Hao Huang static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 40490052b3c4SPo-Hao Huang struct rtw89_vif *rtwvif, u8 type) 40500052b3c4SPo-Hao Huang { 4051*598481c6SChih-Kang Chang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4052*598481c6SChih-Kang Chang const struct rtw89_port_reg *p = mac->port_base; 40530052b3c4SPo-Hao Huang u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif->port); 40540052b3c4SPo-Hao Huang u32 reg_info, reg_ctrl; 40550052b3c4SPo-Hao Huang u32 val; 40560052b3c4SPo-Hao Huang int ret; 40570052b3c4SPo-Hao Huang 4058*598481c6SChih-Kang Chang reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif->mac_idx); 4059*598481c6SChih-Kang Chang reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif->mac_idx); 40600052b3c4SPo-Hao Huang 40610052b3c4SPo-Hao Huang rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 40620052b3c4SPo-Hao Huang rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 40630052b3c4SPo-Hao Huang fsleep(100); 40640052b3c4SPo-Hao Huang 40650052b3c4SPo-Hao Huang ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 40660052b3c4SPo-Hao Huang true, rtwdev, reg_info, mask); 40670052b3c4SPo-Hao Huang if (ret) 40680052b3c4SPo-Hao Huang rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 40690052b3c4SPo-Hao Huang } 40700052b3c4SPo-Hao Huang 40710052b3c4SPo-Hao Huang static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 40720052b3c4SPo-Hao Huang { 40730052b3c4SPo-Hao Huang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 40740052b3c4SPo-Hao Huang const struct rtw89_port_reg *p = mac->port_base; 40750052b3c4SPo-Hao Huang 4076*598481c6SChih-Kang Chang rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif->port)); 40770052b3c4SPo-Hao Huang rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 1); 40780052b3c4SPo-Hao Huang rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 0); 40790052b3c4SPo-Hao Huang rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 0); 40800052b3c4SPo-Hao Huang rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 2); 40810052b3c4SPo-Hao Huang rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK, 1); 40820052b3c4SPo-Hao Huang rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 1); 40830052b3c4SPo-Hao Huang rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 40840052b3c4SPo-Hao Huang 40850052b3c4SPo-Hao Huang rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM0); 40860052b3c4SPo-Hao Huang if (rtwvif->port == RTW89_PORT_0) 40870052b3c4SPo-Hao Huang rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM1); 40880052b3c4SPo-Hao Huang 4089*598481c6SChih-Kang Chang rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif->port)); 40900052b3c4SPo-Hao Huang rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TBTT_PROHIB_EN); 40915ba45ba7SChih-Kang Chang fsleep(2000); 40920052b3c4SPo-Hao Huang } 40930052b3c4SPo-Hao Huang 4094e3ec7017SPing-Ke Shih #define BCN_INTERVAL 100 4095e3ec7017SPing-Ke Shih #define BCN_ERLY_DEF 160 4096e3ec7017SPing-Ke Shih #define BCN_SETUP_DEF 2 4097e3ec7017SPing-Ke Shih #define BCN_HOLD_DEF 200 4098e3ec7017SPing-Ke Shih #define BCN_MASK_DEF 0 4099e3ec7017SPing-Ke Shih #define TBTT_ERLY_DEF 5 4100e3ec7017SPing-Ke Shih #define BCN_SET_UNIT 32 4101e3ec7017SPing-Ke Shih #define BCN_ERLY_SET_DLY (10 * 2) 4102e3ec7017SPing-Ke Shih 4103e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4104e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4105e3ec7017SPing-Ke Shih { 41067c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 41077c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4108e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 41090052b3c4SPo-Hao Huang const struct rtw89_chip_info *chip = rtwdev->chip; 41100052b3c4SPo-Hao Huang bool need_backup = false; 41110052b3c4SPo-Hao Huang u32 backup_val; 4112e3ec7017SPing-Ke Shih 4113e3ec7017SPing-Ke Shih if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 4114e3ec7017SPing-Ke Shih return; 4115e3ec7017SPing-Ke Shih 41160052b3c4SPo-Hao Huang if (chip->chip_id == RTL8852A && rtwvif->port != RTW89_PORT_0) { 41170052b3c4SPo-Hao Huang need_backup = true; 41180052b3c4SPo-Hao Huang backup_val = rtw89_read32_port(rtwdev, rtwvif, p->tbtt_prohib); 41190052b3c4SPo-Hao Huang } 41200052b3c4SPo-Hao Huang 41210052b3c4SPo-Hao Huang if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 41220052b3c4SPo-Hao Huang rtw89_mac_bcn_drop(rtwdev, rtwvif); 41230052b3c4SPo-Hao Huang 41240052b3c4SPo-Hao Huang if (chip->chip_id == RTL8852A) { 4125e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 4126e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 4127e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 4128e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 41290052b3c4SPo-Hao Huang } 4130e3ec7017SPing-Ke Shih 4131e3ec7017SPing-Ke Shih msleep(vif->bss_conf.beacon_int + 1); 4132e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 4133e3ec7017SPing-Ke Shih B_AX_BRK_SETUP); 4134e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 4135e3ec7017SPing-Ke Shih rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 41360052b3c4SPo-Hao Huang 41370052b3c4SPo-Hao Huang if (need_backup) 41380052b3c4SPo-Hao Huang rtw89_write32_port(rtwdev, rtwvif, p->tbtt_prohib, backup_val); 4139e3ec7017SPing-Ke Shih } 4140e3ec7017SPing-Ke Shih 4141e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4142e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 4143e3ec7017SPing-Ke Shih { 41447c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 41457c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4146e3ec7017SPing-Ke Shih 4147e3ec7017SPing-Ke Shih if (en) 4148e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4149e3ec7017SPing-Ke Shih else 4150e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4151e3ec7017SPing-Ke Shih } 4152e3ec7017SPing-Ke Shih 4153e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4154e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 4155e3ec7017SPing-Ke Shih { 41567c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 41577c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4158e3ec7017SPing-Ke Shih 4159e3ec7017SPing-Ke Shih if (en) 4160e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4161e3ec7017SPing-Ke Shih else 4162e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4163e3ec7017SPing-Ke Shih } 4164e3ec7017SPing-Ke Shih 4165e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4166e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4167e3ec7017SPing-Ke Shih { 41687c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 41697c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4170e3ec7017SPing-Ke Shih 4171e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 4172e3ec7017SPing-Ke Shih rtwvif->net_type); 4173e3ec7017SPing-Ke Shih } 4174e3ec7017SPing-Ke Shih 4175e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4176e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4177e3ec7017SPing-Ke Shih { 41787c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 41797c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4180e3ec7017SPing-Ke Shih bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 4181e3ec7017SPing-Ke Shih u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4182e3ec7017SPing-Ke Shih 4183e3ec7017SPing-Ke Shih if (en) 4184e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 4185e3ec7017SPing-Ke Shih else 4186e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 4187e3ec7017SPing-Ke Shih } 4188e3ec7017SPing-Ke Shih 4189e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4190e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4191e3ec7017SPing-Ke Shih { 41927c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 41937c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4194e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4195e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4196e3ec7017SPing-Ke Shih u32 bit = B_AX_RX_BSSID_FIT_EN; 4197e3ec7017SPing-Ke Shih 4198e3ec7017SPing-Ke Shih if (en) 4199e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 4200e3ec7017SPing-Ke Shih else 4201e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 4202e3ec7017SPing-Ke Shih } 4203e3ec7017SPing-Ke Shih 4204f59a98c8SChih-Kang Chang void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4205f59a98c8SChih-Kang Chang struct rtw89_vif *rtwvif, bool en) 4206e3ec7017SPing-Ke Shih { 42077c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 42087c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4209e3ec7017SPing-Ke Shih 4210e3ec7017SPing-Ke Shih if (en) 4211e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4212e3ec7017SPing-Ke Shih else 4213e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4214e3ec7017SPing-Ke Shih } 4215e3ec7017SPing-Ke Shih 4216f59a98c8SChih-Kang Chang static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4217f59a98c8SChih-Kang Chang struct rtw89_vif *rtwvif) 4218f59a98c8SChih-Kang Chang { 4219f59a98c8SChih-Kang Chang bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4220f59a98c8SChih-Kang Chang rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4221f59a98c8SChih-Kang Chang 4222f59a98c8SChih-Kang Chang rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif, en); 4223f59a98c8SChih-Kang Chang } 4224f59a98c8SChih-Kang Chang 4225e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4226756b3120SChih-Kang Chang struct rtw89_vif *rtwvif, bool en) 4227e3ec7017SPing-Ke Shih { 42287c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 42297c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4230e3ec7017SPing-Ke Shih 4231e3ec7017SPing-Ke Shih if (en) 4232e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4233e3ec7017SPing-Ke Shih else 4234e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4235e3ec7017SPing-Ke Shih } 4236e3ec7017SPing-Ke Shih 4237756b3120SChih-Kang Chang static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4238756b3120SChih-Kang Chang struct rtw89_vif *rtwvif) 4239756b3120SChih-Kang Chang { 4240756b3120SChih-Kang Chang bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 4241756b3120SChih-Kang Chang rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4242756b3120SChih-Kang Chang 4243756b3120SChih-Kang Chang rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4244756b3120SChih-Kang Chang } 4245756b3120SChih-Kang Chang 4246756b3120SChih-Kang Chang void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4247756b3120SChih-Kang Chang { 4248756b3120SChih-Kang Chang struct rtw89_vif *rtwvif; 4249756b3120SChih-Kang Chang 4250756b3120SChih-Kang Chang rtw89_for_each_rtwvif(rtwdev, rtwvif) 4251756b3120SChih-Kang Chang if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4252756b3120SChih-Kang Chang rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4253756b3120SChih-Kang Chang } 4254756b3120SChih-Kang Chang 4255e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4256e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4257e3ec7017SPing-Ke Shih { 42587c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 42597c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4260e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4261e3ec7017SPing-Ke Shih u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 4262e3ec7017SPing-Ke Shih 4263e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 4264e3ec7017SPing-Ke Shih bcn_int); 4265e3ec7017SPing-Ke Shih } 4266e3ec7017SPing-Ke Shih 4267283c3d88SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4268283c3d88SPing-Ke Shih struct rtw89_vif *rtwvif) 4269283c3d88SPing-Ke Shih { 4270283c3d88SPing-Ke Shih u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 42717c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 42727c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4273283c3d88SPing-Ke Shih u8 port = rtwvif->port; 4274283c3d88SPing-Ke Shih u32 reg; 4275283c3d88SPing-Ke Shih 427665129813SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif->mac_idx); 4277283c3d88SPing-Ke Shih rtw89_write8(rtwdev, reg, win); 4278283c3d88SPing-Ke Shih } 4279283c3d88SPing-Ke Shih 4280283c3d88SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4281283c3d88SPing-Ke Shih struct rtw89_vif *rtwvif) 4282283c3d88SPing-Ke Shih { 42837c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 42847c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4285283c3d88SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4286283c3d88SPing-Ke Shih u32 addr; 4287283c3d88SPing-Ke Shih 428865129813SPing-Ke Shih addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif->mac_idx); 4289283c3d88SPing-Ke Shih rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4290283c3d88SPing-Ke Shih 4291283c3d88SPing-Ke Shih rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4292283c3d88SPing-Ke Shih vif->bss_conf.dtim_period); 4293283c3d88SPing-Ke Shih } 4294283c3d88SPing-Ke Shih 4295e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4296e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4297e3ec7017SPing-Ke Shih { 42987c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 42997c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4300e3ec7017SPing-Ke Shih 4301e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4302e3ec7017SPing-Ke Shih B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4303e3ec7017SPing-Ke Shih } 4304e3ec7017SPing-Ke Shih 4305e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4306e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4307e3ec7017SPing-Ke Shih { 43087c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43097c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4310e3ec7017SPing-Ke Shih 4311e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4312e3ec7017SPing-Ke Shih B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4313e3ec7017SPing-Ke Shih } 4314e3ec7017SPing-Ke Shih 4315e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4316e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4317e3ec7017SPing-Ke Shih { 43187c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43197c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4320e3ec7017SPing-Ke Shih 4321e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 4322e3ec7017SPing-Ke Shih B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4323e3ec7017SPing-Ke Shih } 4324e3ec7017SPing-Ke Shih 4325e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4326e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4327e3ec7017SPing-Ke Shih { 43287c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43297c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4330e3ec7017SPing-Ke Shih 4331e3ec7017SPing-Ke Shih rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 4332e3ec7017SPing-Ke Shih B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4333e3ec7017SPing-Ke Shih } 4334e3ec7017SPing-Ke Shih 4335e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4336e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4337e3ec7017SPing-Ke Shih { 43387c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43397c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4340e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4341e3ec7017SPing-Ke Shih static const u32 masks[RTW89_PORT_NUM] = { 4342e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4343e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4344e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_4_MASK, 4345e3ec7017SPing-Ke Shih }; 4346e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 4347e3ec7017SPing-Ke Shih u32 reg_base; 4348e3ec7017SPing-Ke Shih u32 reg; 4349e3ec7017SPing-Ke Shih u8 bss_color; 4350e3ec7017SPing-Ke Shih 4351e3ec7017SPing-Ke Shih bss_color = vif->bss_conf.he_bss_color.color; 435265129813SPing-Ke Shih reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4353c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx); 4354e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4355e3ec7017SPing-Ke Shih } 4356e3ec7017SPing-Ke Shih 4357e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4358e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4359e3ec7017SPing-Ke Shih { 43607c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43617c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4362e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 4363e3ec7017SPing-Ke Shih u32 reg; 4364e3ec7017SPing-Ke Shih 4365e3ec7017SPing-Ke Shih if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4366e3ec7017SPing-Ke Shih return; 4367e3ec7017SPing-Ke Shih 4368e3ec7017SPing-Ke Shih if (port == 0) { 436965129813SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif->mac_idx); 4370e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4371e3ec7017SPing-Ke Shih } 4372e3ec7017SPing-Ke Shih } 4373e3ec7017SPing-Ke Shih 4374e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4375e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4376e3ec7017SPing-Ke Shih { 43777c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43787c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4379e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 4380e3ec7017SPing-Ke Shih u32 reg; 4381e3ec7017SPing-Ke Shih u32 val; 4382e3ec7017SPing-Ke Shih 438365129813SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif->mac_idx); 4384e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 4385e3ec7017SPing-Ke Shih val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4386e3ec7017SPing-Ke Shih if (port == 0) 4387e3ec7017SPing-Ke Shih val &= ~BIT(0); 4388e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 4389e3ec7017SPing-Ke Shih } 4390e3ec7017SPing-Ke Shih 4391e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4392d592b9f7SPo-Hao Huang struct rtw89_vif *rtwvif, bool enable) 4393e3ec7017SPing-Ke Shih { 43947c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 43957c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4396e3ec7017SPing-Ke Shih 4397d592b9f7SPo-Hao Huang if (enable) 4398d592b9f7SPo-Hao Huang rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 4399d592b9f7SPo-Hao Huang B_AX_PORT_FUNC_EN); 4400d592b9f7SPo-Hao Huang else 4401d592b9f7SPo-Hao Huang rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 4402d592b9f7SPo-Hao Huang B_AX_PORT_FUNC_EN); 4403e3ec7017SPing-Ke Shih } 4404e3ec7017SPing-Ke Shih 4405e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4406e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 4407e3ec7017SPing-Ke Shih { 44087c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44097c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4410e3ec7017SPing-Ke Shih 4411e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 4412e3ec7017SPing-Ke Shih BCN_ERLY_DEF); 4413e3ec7017SPing-Ke Shih } 4414e3ec7017SPing-Ke Shih 4415704052f5SChia-Yuan Li static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4416704052f5SChia-Yuan Li struct rtw89_vif *rtwvif) 4417704052f5SChia-Yuan Li { 44187c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44197c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4420704052f5SChia-Yuan Li u16 val; 4421704052f5SChia-Yuan Li 4422704052f5SChia-Yuan Li if (rtwdev->chip->chip_id != RTL8852C) 4423704052f5SChia-Yuan Li return; 4424704052f5SChia-Yuan Li 4425704052f5SChia-Yuan Li if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4426704052f5SChia-Yuan Li rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4427704052f5SChia-Yuan Li return; 4428704052f5SChia-Yuan Li 4429704052f5SChia-Yuan Li val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4430704052f5SChia-Yuan Li B_AX_TBTT_SHIFT_OFST_SIGN; 4431704052f5SChia-Yuan Li 4432704052f5SChia-Yuan Li rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 4433704052f5SChia-Yuan Li B_AX_TBTT_SHIFT_OFST_MASK, val); 4434704052f5SChia-Yuan Li } 4435704052f5SChia-Yuan Li 443642db7eddSZong-Zhe Yang void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4437fb2b8cecSPo-Hao Huang struct rtw89_vif *rtwvif, 443842db7eddSZong-Zhe Yang struct rtw89_vif *rtwvif_src, 443942db7eddSZong-Zhe Yang u16 offset_tu) 4440fb2b8cecSPo-Hao Huang { 44417c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44427c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 4443fb2b8cecSPo-Hao Huang u32 val, reg; 4444fb2b8cecSPo-Hao Huang 444542db7eddSZong-Zhe Yang val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 444665129813SPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif->port * 4, 444742db7eddSZong-Zhe Yang rtwvif->mac_idx); 444842db7eddSZong-Zhe Yang 444942db7eddSZong-Zhe Yang rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 445042db7eddSZong-Zhe Yang rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 445142db7eddSZong-Zhe Yang rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 445242db7eddSZong-Zhe Yang } 445342db7eddSZong-Zhe Yang 445442db7eddSZong-Zhe Yang static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 445542db7eddSZong-Zhe Yang struct rtw89_vif *rtwvif, 445642db7eddSZong-Zhe Yang struct rtw89_vif *rtwvif_src, 445742db7eddSZong-Zhe Yang u8 offset, int *n_offset) 445842db7eddSZong-Zhe Yang { 4459fb2b8cecSPo-Hao Huang if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 4460fb2b8cecSPo-Hao Huang return; 4461fb2b8cecSPo-Hao Huang 4462fb2b8cecSPo-Hao Huang /* adjust offset randomly to avoid beacon conflict */ 4463fb2b8cecSPo-Hao Huang offset = offset - offset / 4 + get_random_u32() % (offset / 2); 446442db7eddSZong-Zhe Yang rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 446542db7eddSZong-Zhe Yang (*n_offset) * offset); 4466fb2b8cecSPo-Hao Huang 44671120e6a6SZong-Zhe Yang (*n_offset)++; 4468fb2b8cecSPo-Hao Huang } 4469fb2b8cecSPo-Hao Huang 4470fb2b8cecSPo-Hao Huang static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4471fb2b8cecSPo-Hao Huang { 4472fb2b8cecSPo-Hao Huang struct rtw89_vif *src = NULL, *tmp; 4473fb2b8cecSPo-Hao Huang u8 offset = 100, vif_aps = 0; 4474fb2b8cecSPo-Hao Huang int n_offset = 1; 4475fb2b8cecSPo-Hao Huang 4476fb2b8cecSPo-Hao Huang rtw89_for_each_rtwvif(rtwdev, tmp) { 4477fb2b8cecSPo-Hao Huang if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4478fb2b8cecSPo-Hao Huang src = tmp; 4479fb2b8cecSPo-Hao Huang if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4480fb2b8cecSPo-Hao Huang vif_aps++; 4481fb2b8cecSPo-Hao Huang } 4482fb2b8cecSPo-Hao Huang 4483fb2b8cecSPo-Hao Huang if (vif_aps == 0) 4484fb2b8cecSPo-Hao Huang return; 4485fb2b8cecSPo-Hao Huang 4486fb2b8cecSPo-Hao Huang offset /= (vif_aps + 1); 4487fb2b8cecSPo-Hao Huang 4488fb2b8cecSPo-Hao Huang rtw89_for_each_rtwvif(rtwdev, tmp) 448942db7eddSZong-Zhe Yang rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4490fb2b8cecSPo-Hao Huang } 4491fb2b8cecSPo-Hao Huang 4492e3ec7017SPing-Ke Shih int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4493e3ec7017SPing-Ke Shih { 4494e3ec7017SPing-Ke Shih int ret; 4495e3ec7017SPing-Ke Shih 4496e3ec7017SPing-Ke Shih ret = rtw89_mac_port_update(rtwdev, rtwvif); 4497e3ec7017SPing-Ke Shih if (ret) 4498e3ec7017SPing-Ke Shih return ret; 4499e3ec7017SPing-Ke Shih 4500e3ec7017SPing-Ke Shih rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4501e3ec7017SPing-Ke Shih rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4502e3ec7017SPing-Ke Shih 45031b73e77dSPing-Ke Shih ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4504e3ec7017SPing-Ke Shih if (ret) 4505e3ec7017SPing-Ke Shih return ret; 4506e3ec7017SPing-Ke Shih 4507ff66964aSPing-Ke Shih ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4508e3ec7017SPing-Ke Shih if (ret) 4509e3ec7017SPing-Ke Shih return ret; 4510e3ec7017SPing-Ke Shih 4511a0e78d5cSPo-Hao Huang ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4512a0e78d5cSPo-Hao Huang if (ret) 4513a0e78d5cSPo-Hao Huang return ret; 4514a0e78d5cSPo-Hao Huang 4515e3ec7017SPing-Ke Shih ret = rtw89_cam_init(rtwdev, rtwvif); 4516e3ec7017SPing-Ke Shih if (ret) 4517e3ec7017SPing-Ke Shih return ret; 4518e3ec7017SPing-Ke Shih 451940822e07SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4520e3ec7017SPing-Ke Shih if (ret) 4521e3ec7017SPing-Ke Shih return ret; 4522e3ec7017SPing-Ke Shih 45233d49ed07SPing-Ke Shih ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, NULL); 4524e3ec7017SPing-Ke Shih if (ret) 4525e3ec7017SPing-Ke Shih return ret; 4526e3ec7017SPing-Ke Shih 4527011e2768SPing-Ke Shih ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, NULL); 4528011e2768SPing-Ke Shih if (ret) 4529011e2768SPing-Ke Shih return ret; 4530011e2768SPing-Ke Shih 4531e3ec7017SPing-Ke Shih return 0; 4532e3ec7017SPing-Ke Shih } 4533e3ec7017SPing-Ke Shih 4534e3ec7017SPing-Ke Shih int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4535e3ec7017SPing-Ke Shih { 4536e3ec7017SPing-Ke Shih int ret; 4537e3ec7017SPing-Ke Shih 4538ff66964aSPing-Ke Shih ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4539e3ec7017SPing-Ke Shih if (ret) 4540e3ec7017SPing-Ke Shih return ret; 4541e3ec7017SPing-Ke Shih 4542e3ec7017SPing-Ke Shih rtw89_cam_deinit(rtwdev, rtwvif); 4543e3ec7017SPing-Ke Shih 454440822e07SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4545e3ec7017SPing-Ke Shih if (ret) 4546e3ec7017SPing-Ke Shih return ret; 4547e3ec7017SPing-Ke Shih 4548e3ec7017SPing-Ke Shih return 0; 4549e3ec7017SPing-Ke Shih } 4550e3ec7017SPing-Ke Shih 4551e3ec7017SPing-Ke Shih int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4552e3ec7017SPing-Ke Shih { 4553e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 4554e3ec7017SPing-Ke Shih 4555e3ec7017SPing-Ke Shih if (port >= RTW89_PORT_NUM) 4556e3ec7017SPing-Ke Shih return -EINVAL; 4557e3ec7017SPing-Ke Shih 4558e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4559e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4560e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4561e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4562e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4563e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4564f59a98c8SChih-Kang Chang rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif); 4565756b3120SChih-Kang Chang rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif); 4566e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4567283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4568283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4569283c3d88SPing-Ke Shih rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4570e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4571e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4572e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4573e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4574704052f5SChia-Yuan Li rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4575e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4576e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4577d592b9f7SPo-Hao Huang rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4578fb2b8cecSPo-Hao Huang rtw89_mac_port_tsf_resync_all(rtwdev); 4579e3ec7017SPing-Ke Shih fsleep(BCN_ERLY_SET_DLY); 4580e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4581e3ec7017SPing-Ke Shih 4582e3ec7017SPing-Ke Shih return 0; 4583e3ec7017SPing-Ke Shih } 4584e3ec7017SPing-Ke Shih 458576f478a3SZong-Zhe Yang int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 458676f478a3SZong-Zhe Yang u64 *tsf) 458776f478a3SZong-Zhe Yang { 45887c8a55ddSPing-Ke Shih const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 45897c8a55ddSPing-Ke Shih const struct rtw89_port_reg *p = mac->port_base; 459076f478a3SZong-Zhe Yang u32 tsf_low, tsf_high; 459176f478a3SZong-Zhe Yang int ret; 459276f478a3SZong-Zhe Yang 459376f478a3SZong-Zhe Yang ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 459476f478a3SZong-Zhe Yang if (ret) 459576f478a3SZong-Zhe Yang return ret; 459676f478a3SZong-Zhe Yang 459776f478a3SZong-Zhe Yang tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 459876f478a3SZong-Zhe Yang tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 459976f478a3SZong-Zhe Yang *tsf = (u64)tsf_high << 32 | tsf_low; 460076f478a3SZong-Zhe Yang 460176f478a3SZong-Zhe Yang return 0; 460276f478a3SZong-Zhe Yang } 460376f478a3SZong-Zhe Yang 46048d540f9dSKuan-Chung Chen static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 46058d540f9dSKuan-Chung Chen struct cfg80211_bss *bss, 46068d540f9dSKuan-Chung Chen void *data) 46078d540f9dSKuan-Chung Chen { 46088d540f9dSKuan-Chung Chen const struct cfg80211_bss_ies *ies; 46098d540f9dSKuan-Chung Chen const struct element *elem; 46108d540f9dSKuan-Chung Chen bool *tolerated = data; 46118d540f9dSKuan-Chung Chen 46128d540f9dSKuan-Chung Chen rcu_read_lock(); 46138d540f9dSKuan-Chung Chen ies = rcu_dereference(bss->ies); 46148d540f9dSKuan-Chung Chen elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 46158d540f9dSKuan-Chung Chen ies->len); 46168d540f9dSKuan-Chung Chen 46178d540f9dSKuan-Chung Chen if (!elem || elem->datalen < 10 || 46188d540f9dSKuan-Chung Chen !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 46198d540f9dSKuan-Chung Chen *tolerated = false; 46208d540f9dSKuan-Chung Chen rcu_read_unlock(); 46218d540f9dSKuan-Chung Chen } 46228d540f9dSKuan-Chung Chen 46238d540f9dSKuan-Chung Chen void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 46248d540f9dSKuan-Chung Chen struct ieee80211_vif *vif) 46258d540f9dSKuan-Chung Chen { 46268d540f9dSKuan-Chung Chen struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 462749ea9823SZong-Zhe Yang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 46288d540f9dSKuan-Chung Chen struct ieee80211_hw *hw = rtwdev->hw; 46298d540f9dSKuan-Chung Chen bool tolerated = true; 46308d540f9dSKuan-Chung Chen u32 reg; 46318d540f9dSKuan-Chung Chen 46328d540f9dSKuan-Chung Chen if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 46338d540f9dSKuan-Chung Chen return; 46348d540f9dSKuan-Chung Chen 46356092077aSJohannes Berg if (!(vif->bss_conf.chanreq.oper.chan->flags & IEEE80211_CHAN_RADAR)) 46368d540f9dSKuan-Chung Chen return; 46378d540f9dSKuan-Chung Chen 46386092077aSJohannes Berg cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chanreq.oper, 46398d540f9dSKuan-Chung Chen rtw89_mac_check_he_obss_narrow_bw_ru_iter, 46408d540f9dSKuan-Chung Chen &tolerated); 46418d540f9dSKuan-Chung Chen 464249ea9823SZong-Zhe Yang reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 464349ea9823SZong-Zhe Yang rtwvif->mac_idx); 46448d540f9dSKuan-Chung Chen if (tolerated) 464549ea9823SZong-Zhe Yang rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 46468d540f9dSKuan-Chung Chen else 464749ea9823SZong-Zhe Yang rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 46488d540f9dSKuan-Chung Chen } 46498d540f9dSKuan-Chung Chen 4650d592b9f7SPo-Hao Huang void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4651d592b9f7SPo-Hao Huang { 46520052b3c4SPo-Hao Huang rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4653d592b9f7SPo-Hao Huang } 4654d592b9f7SPo-Hao Huang 4655e3ec7017SPing-Ke Shih int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4656e3ec7017SPing-Ke Shih { 4657e3ec7017SPing-Ke Shih int ret; 4658e3ec7017SPing-Ke Shih 4659e3ec7017SPing-Ke Shih rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 4660e3ec7017SPing-Ke Shih RTW89_MAX_MAC_ID_NUM); 4661e3ec7017SPing-Ke Shih if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4662e3ec7017SPing-Ke Shih return -ENOSPC; 4663e3ec7017SPing-Ke Shih 4664e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4665e3ec7017SPing-Ke Shih if (ret) 4666e3ec7017SPing-Ke Shih goto release_mac_id; 4667e3ec7017SPing-Ke Shih 4668e3ec7017SPing-Ke Shih return 0; 4669e3ec7017SPing-Ke Shih 4670e3ec7017SPing-Ke Shih release_mac_id: 4671e3ec7017SPing-Ke Shih rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4672e3ec7017SPing-Ke Shih 4673e3ec7017SPing-Ke Shih return ret; 4674e3ec7017SPing-Ke Shih } 4675e3ec7017SPing-Ke Shih 4676e3ec7017SPing-Ke Shih int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4677e3ec7017SPing-Ke Shih { 4678e3ec7017SPing-Ke Shih int ret; 4679e3ec7017SPing-Ke Shih 4680e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4681e3ec7017SPing-Ke Shih rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4682e3ec7017SPing-Ke Shih 4683e3ec7017SPing-Ke Shih return ret; 4684e3ec7017SPing-Ke Shih } 4685e3ec7017SPing-Ke Shih 4686e3ec7017SPing-Ke Shih static void 4687e3ec7017SPing-Ke Shih rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4688e3ec7017SPing-Ke Shih { 4689e3ec7017SPing-Ke Shih } 4690e3ec7017SPing-Ke Shih 469189590777SPo Hao Huang static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 469289590777SPo Hao Huang { 4693e7399db2SPo-Hao Huang const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 469489590777SPo Hao Huang 4695e7399db2SPo-Hao Huang return band == op->band_type && channel == op->primary_channel; 469689590777SPo Hao Huang } 469789590777SPo Hao Huang 469889590777SPo Hao Huang static void 4699b9979843SPo-Hao Huang rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 470089590777SPo Hao Huang u32 len) 470189590777SPo Hao Huang { 4702b9979843SPo-Hao Huang const struct rtw89_c2h_scanofld *c2h = 4703b9979843SPo-Hao Huang (const struct rtw89_c2h_scanofld *)skb->data; 470489590777SPo Hao Huang struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4705bd1056d4SPo-Hao Huang struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4706cbb145b9SZong-Zhe Yang struct rtw89_chan new; 4707b5d70201SPo-Hao Huang u8 reason, status, tx_fail, band, actual_period, expect_period; 4708b5d70201SPo-Hao Huang u32 last_chan = rtwdev->scan_info.last_chan_idx, report_tsf; 4709b5d70201SPo-Hao Huang u8 mac_idx, sw_def, fw_def; 471089590777SPo Hao Huang u16 chan; 4711bd1056d4SPo-Hao Huang int ret; 471289590777SPo Hao Huang 4713a0e97ae3SPo-Hao Huang if (!rtwvif) 4714a0e97ae3SPo-Hao Huang return; 4715a0e97ae3SPo-Hao Huang 4716b9979843SPo-Hao Huang tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 4717b9979843SPo-Hao Huang status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 4718b9979843SPo-Hao Huang chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 4719b9979843SPo-Hao Huang reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 4720b9979843SPo-Hao Huang band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 4721b9979843SPo-Hao Huang actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 4722b5d70201SPo-Hao Huang mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 4723b5d70201SPo-Hao Huang 472489590777SPo Hao Huang 472589590777SPo Hao Huang if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 472689590777SPo Hao Huang band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 472789590777SPo Hao Huang 472889590777SPo Hao Huang rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4729b5d70201SPo-Hao Huang "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4730b5d70201SPo-Hao Huang mac_idx, band, chan, reason, status, tx_fail, actual_period); 4731b5d70201SPo-Hao Huang 4732b5d70201SPo-Hao Huang if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4733b5d70201SPo-Hao Huang sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 4734b5d70201SPo-Hao Huang expect_period = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 4735b5d70201SPo-Hao Huang fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 4736b5d70201SPo-Hao Huang report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 4737b5d70201SPo-Hao Huang 4738b5d70201SPo-Hao Huang rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4739b5d70201SPo-Hao Huang "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 4740b5d70201SPo-Hao Huang sw_def, fw_def, report_tsf, expect_period); 4741b5d70201SPo-Hao Huang } 474289590777SPo Hao Huang 474389590777SPo Hao Huang switch (reason) { 4744b5d70201SPo-Hao Huang case RTW89_SCAN_LEAVE_OP_NOTIFY: 474589590777SPo Hao Huang case RTW89_SCAN_LEAVE_CH_NOTIFY: 4746756b3120SChih-Kang Chang if (rtw89_is_op_chan(rtwdev, band, chan)) { 4747756b3120SChih-Kang Chang rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, false); 474889590777SPo Hao Huang ieee80211_stop_queues(rtwdev->hw); 4749756b3120SChih-Kang Chang } 475089590777SPo Hao Huang return; 475189590777SPo Hao Huang case RTW89_SCAN_END_SCAN_NOTIFY: 4752bd1056d4SPo-Hao Huang if (rtwvif && rtwvif->scan_req && 4753bd1056d4SPo-Hao Huang last_chan < rtwvif->scan_req->n_channels) { 4754bd1056d4SPo-Hao Huang ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4755bd1056d4SPo-Hao Huang if (ret) { 4756bd1056d4SPo-Hao Huang rtw89_hw_scan_abort(rtwdev, vif); 4757bd1056d4SPo-Hao Huang rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4758bd1056d4SPo-Hao Huang } 4759bd1056d4SPo-Hao Huang } else { 4760bcbefbd0SPo-Hao Huang rtw89_hw_scan_complete(rtwdev, vif, rtwdev->scan_info.abort); 4761bd1056d4SPo-Hao Huang } 476289590777SPo Hao Huang break; 4763b5d70201SPo-Hao Huang case RTW89_SCAN_ENTER_OP_NOTIFY: 476489590777SPo Hao Huang case RTW89_SCAN_ENTER_CH_NOTIFY: 476528000f7bSPo Hao Huang if (rtw89_is_op_chan(rtwdev, band, chan)) { 4766e7399db2SPo-Hao Huang rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4767e7399db2SPo-Hao Huang &rtwdev->scan_info.op_chan); 4768756b3120SChih-Kang Chang rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, true); 476989590777SPo Hao Huang ieee80211_wake_queues(rtwdev->hw); 4770e7399db2SPo-Hao Huang } else { 4771e7399db2SPo-Hao Huang rtw89_chan_create(&new, chan, chan, band, 4772e7399db2SPo-Hao Huang RTW89_CHANNEL_WIDTH_20); 4773e7399db2SPo-Hao Huang rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4774e7399db2SPo-Hao Huang &new); 477528000f7bSPo Hao Huang } 477689590777SPo Hao Huang break; 477789590777SPo Hao Huang default: 477889590777SPo Hao Huang return; 477989590777SPo Hao Huang } 478089590777SPo Hao Huang } 478189590777SPo Hao Huang 4782e3ec7017SPing-Ke Shih static void 4783d2b6da24SPo-Hao Huang rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4784d2b6da24SPo-Hao Huang struct sk_buff *skb) 4785d2b6da24SPo-Hao Huang { 4786d2b6da24SPo-Hao Huang struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4787d2b6da24SPo-Hao Huang enum nl80211_cqm_rssi_threshold_event nl_event; 4788d2b6da24SPo-Hao Huang const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4789d2b6da24SPo-Hao Huang (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4790d2b6da24SPo-Hao Huang u8 type, event, mac_id; 4791d2b6da24SPo-Hao Huang s8 sig; 4792d2b6da24SPo-Hao Huang 4793d2b6da24SPo-Hao Huang type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4794d2b6da24SPo-Hao Huang sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4795d2b6da24SPo-Hao Huang event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4796d2b6da24SPo-Hao Huang mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4797d2b6da24SPo-Hao Huang 4798d2b6da24SPo-Hao Huang if (mac_id != rtwvif->mac_id) 4799d2b6da24SPo-Hao Huang return; 4800d2b6da24SPo-Hao Huang 4801d2b6da24SPo-Hao Huang rtw89_debug(rtwdev, RTW89_DBG_FW, 4802d2b6da24SPo-Hao Huang "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4803d2b6da24SPo-Hao Huang mac_id, type, sig, event); 4804d2b6da24SPo-Hao Huang 4805d2b6da24SPo-Hao Huang switch (type) { 4806d2b6da24SPo-Hao Huang case RTW89_BCN_FLTR_BEACON_LOSS: 4807a0e97ae3SPo-Hao Huang if (!rtwdev->scanning && !rtwvif->offchan) 4808d2b6da24SPo-Hao Huang ieee80211_connection_loss(vif); 4809d2b6da24SPo-Hao Huang else 4810d2b6da24SPo-Hao Huang rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4811d2b6da24SPo-Hao Huang return; 4812d2b6da24SPo-Hao Huang case RTW89_BCN_FLTR_NOTIFY: 4813d2b6da24SPo-Hao Huang nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4814d2b6da24SPo-Hao Huang break; 4815d2b6da24SPo-Hao Huang case RTW89_BCN_FLTR_RSSI: 4816d2b6da24SPo-Hao Huang if (event == RTW89_BCN_FLTR_RSSI_LOW) 4817d2b6da24SPo-Hao Huang nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4818d2b6da24SPo-Hao Huang else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4819d2b6da24SPo-Hao Huang nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4820d2b6da24SPo-Hao Huang else 4821d2b6da24SPo-Hao Huang return; 4822d2b6da24SPo-Hao Huang break; 4823d2b6da24SPo-Hao Huang default: 4824d2b6da24SPo-Hao Huang return; 4825d2b6da24SPo-Hao Huang } 4826d2b6da24SPo-Hao Huang 4827d2b6da24SPo-Hao Huang ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4828d2b6da24SPo-Hao Huang } 4829d2b6da24SPo-Hao Huang 4830d2b6da24SPo-Hao Huang static void 4831d2b6da24SPo-Hao Huang rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4832d2b6da24SPo-Hao Huang u32 len) 4833d2b6da24SPo-Hao Huang { 4834d2b6da24SPo-Hao Huang struct rtw89_vif *rtwvif; 4835d2b6da24SPo-Hao Huang 4836d2b6da24SPo-Hao Huang rtw89_for_each_rtwvif(rtwdev, rtwvif) 4837d2b6da24SPo-Hao Huang rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4838d2b6da24SPo-Hao Huang } 4839d2b6da24SPo-Hao Huang 4840d2b6da24SPo-Hao Huang static void 4841e3ec7017SPing-Ke Shih rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4842e3ec7017SPing-Ke Shih { 484332bb12ebSZong-Zhe Yang /* N.B. This will run in interrupt context. */ 484432bb12ebSZong-Zhe Yang 4845e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 4846e3ec7017SPing-Ke Shih "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4847e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4848e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4849e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4850e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4851e3ec7017SPing-Ke Shih } 4852e3ec7017SPing-Ke Shih 4853e3ec7017SPing-Ke Shih static void 4854b9b632f4SZong-Zhe Yang rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4855e3ec7017SPing-Ke Shih { 485632bb12ebSZong-Zhe Yang /* N.B. This will run in interrupt context. */ 4857b9b632f4SZong-Zhe Yang struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4858b9b632f4SZong-Zhe Yang const struct rtw89_c2h_done_ack *c2h = 4859b9b632f4SZong-Zhe Yang (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4860b9b632f4SZong-Zhe Yang u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4861b9b632f4SZong-Zhe Yang u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4862b9b632f4SZong-Zhe Yang u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4863b9b632f4SZong-Zhe Yang u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4864b9b632f4SZong-Zhe Yang u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4865b9b632f4SZong-Zhe Yang struct rtw89_completion_data data = {}; 4866b9b632f4SZong-Zhe Yang unsigned int cond; 486732bb12ebSZong-Zhe Yang 4868e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 4869e3ec7017SPing-Ke Shih "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4870b9b632f4SZong-Zhe Yang h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4871b9b632f4SZong-Zhe Yang 4872b9b632f4SZong-Zhe Yang if (h2c_cat != H2C_CAT_MAC) 4873b9b632f4SZong-Zhe Yang return; 4874b9b632f4SZong-Zhe Yang 4875b9b632f4SZong-Zhe Yang switch (h2c_class) { 4876b9b632f4SZong-Zhe Yang default: 4877b9b632f4SZong-Zhe Yang return; 4878b9b632f4SZong-Zhe Yang case H2C_CL_MAC_FW_OFLD: 4879b9b632f4SZong-Zhe Yang switch (h2c_func) { 4880b9b632f4SZong-Zhe Yang default: 4881b9b632f4SZong-Zhe Yang return; 4882b9b632f4SZong-Zhe Yang case H2C_FUNC_ADD_SCANOFLD_CH: 4883bcbefbd0SPo-Hao Huang cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 4884bcbefbd0SPo-Hao Huang break; 4885b9b632f4SZong-Zhe Yang case H2C_FUNC_SCANOFLD: 4886bcbefbd0SPo-Hao Huang cond = RTW89_SCANOFLD_WAIT_COND_START; 4887b9b632f4SZong-Zhe Yang break; 48884ba24331SPo-Hao Huang case H2C_FUNC_SCANOFLD_BE: 48894ba24331SPo-Hao Huang cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 48904ba24331SPo-Hao Huang break; 4891b9b632f4SZong-Zhe Yang } 4892b9b632f4SZong-Zhe Yang 4893b9b632f4SZong-Zhe Yang data.err = !!h2c_return; 4894b9b632f4SZong-Zhe Yang rtw89_complete_cond(fw_ofld_wait, cond, &data); 4895b9b632f4SZong-Zhe Yang return; 4896b9b632f4SZong-Zhe Yang } 4897e3ec7017SPing-Ke Shih } 4898e3ec7017SPing-Ke Shih 4899e3ec7017SPing-Ke Shih static void 4900e3ec7017SPing-Ke Shih rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4901e3ec7017SPing-Ke Shih { 4902cad2bd8aSChin-Yen Lee rtw89_fw_log_dump(rtwdev, c2h->data, len); 4903e3ec7017SPing-Ke Shih } 4904e3ec7017SPing-Ke Shih 4905fccca934SPing-Ke Shih static void 4906fccca934SPing-Ke Shih rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4907fccca934SPing-Ke Shih { 4908fccca934SPing-Ke Shih } 4909fccca934SPing-Ke Shih 49102b8219e9SPo Hao Huang static void 49118febd68bSZong-Zhe Yang rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 49122b8219e9SPo Hao Huang u32 len) 49132b8219e9SPo Hao Huang { 49148febd68bSZong-Zhe Yang struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 49158febd68bSZong-Zhe Yang const struct rtw89_c2h_pkt_ofld_rsp *c2h = 49168febd68bSZong-Zhe Yang (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 49178febd68bSZong-Zhe Yang u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 49188febd68bSZong-Zhe Yang u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 49198febd68bSZong-Zhe Yang u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 49208febd68bSZong-Zhe Yang struct rtw89_completion_data data = {}; 49218febd68bSZong-Zhe Yang unsigned int cond; 49228febd68bSZong-Zhe Yang 49238b21c08eSZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 49248b21c08eSZong-Zhe Yang pkt_id, pkt_op, pkt_len); 49258b21c08eSZong-Zhe Yang 49268febd68bSZong-Zhe Yang data.err = !pkt_len; 49278febd68bSZong-Zhe Yang cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 49288febd68bSZong-Zhe Yang 49298febd68bSZong-Zhe Yang rtw89_complete_cond(wait, cond, &data); 49302b8219e9SPo Hao Huang } 49312b8219e9SPo Hao Huang 4932f4a43c3bSDian-Syuan Yang static void 4933f4a43c3bSDian-Syuan Yang rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4934f4a43c3bSDian-Syuan Yang u32 len) 4935f4a43c3bSDian-Syuan Yang { 493697211e02SZong-Zhe Yang rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 4937f4a43c3bSDian-Syuan Yang } 4938f4a43c3bSDian-Syuan Yang 4939ef9dff4cSZong-Zhe Yang static void 4940ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4941ef9dff4cSZong-Zhe Yang { 4942ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4943ef9dff4cSZong-Zhe Yang u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4944ef9dff4cSZong-Zhe Yang 4945ef9dff4cSZong-Zhe Yang switch (func) { 4946ef9dff4cSZong-Zhe Yang case H2C_FUNC_ADD_MCC: 4947ef9dff4cSZong-Zhe Yang case H2C_FUNC_START_MCC: 4948ef9dff4cSZong-Zhe Yang case H2C_FUNC_STOP_MCC: 4949ef9dff4cSZong-Zhe Yang case H2C_FUNC_DEL_MCC_GROUP: 4950ef9dff4cSZong-Zhe Yang case H2C_FUNC_RESET_MCC_GROUP: 4951ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_REQ_TSF: 4952ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_MACID_BITMAP: 4953ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SYNC: 4954ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SET_DURATION: 4955ef9dff4cSZong-Zhe Yang break; 4956ef9dff4cSZong-Zhe Yang default: 4957214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4958ef9dff4cSZong-Zhe Yang "invalid MCC C2H RCV ACK: func %d\n", func); 4959ef9dff4cSZong-Zhe Yang return; 4960ef9dff4cSZong-Zhe Yang } 4961ef9dff4cSZong-Zhe Yang 4962214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4963ef9dff4cSZong-Zhe Yang "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4964ef9dff4cSZong-Zhe Yang } 4965ef9dff4cSZong-Zhe Yang 4966ef9dff4cSZong-Zhe Yang static void 4967ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4968ef9dff4cSZong-Zhe Yang { 4969ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4970ef9dff4cSZong-Zhe Yang u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4971ef9dff4cSZong-Zhe Yang u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4972ef9dff4cSZong-Zhe Yang struct rtw89_completion_data data = {}; 4973ef9dff4cSZong-Zhe Yang unsigned int cond; 4974ef9dff4cSZong-Zhe Yang bool next = false; 4975ef9dff4cSZong-Zhe Yang 4976ef9dff4cSZong-Zhe Yang switch (func) { 4977ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_REQ_TSF: 4978ef9dff4cSZong-Zhe Yang next = true; 4979ef9dff4cSZong-Zhe Yang break; 4980ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_MACID_BITMAP: 4981ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SYNC: 4982ef9dff4cSZong-Zhe Yang case H2C_FUNC_MCC_SET_DURATION: 4983ef9dff4cSZong-Zhe Yang break; 4984ef9dff4cSZong-Zhe Yang case H2C_FUNC_ADD_MCC: 4985ef9dff4cSZong-Zhe Yang case H2C_FUNC_START_MCC: 4986ef9dff4cSZong-Zhe Yang case H2C_FUNC_STOP_MCC: 4987ef9dff4cSZong-Zhe Yang case H2C_FUNC_DEL_MCC_GROUP: 4988ef9dff4cSZong-Zhe Yang case H2C_FUNC_RESET_MCC_GROUP: 4989ef9dff4cSZong-Zhe Yang default: 4990214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4991ef9dff4cSZong-Zhe Yang "invalid MCC C2H REQ ACK: func %d\n", func); 4992ef9dff4cSZong-Zhe Yang return; 4993ef9dff4cSZong-Zhe Yang } 4994ef9dff4cSZong-Zhe Yang 4995214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4996ef9dff4cSZong-Zhe Yang "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 4997ef9dff4cSZong-Zhe Yang group, func, retcode); 4998ef9dff4cSZong-Zhe Yang 4999ef9dff4cSZong-Zhe Yang if (!retcode && next) 5000ef9dff4cSZong-Zhe Yang return; 5001ef9dff4cSZong-Zhe Yang 5002ef9dff4cSZong-Zhe Yang data.err = !!retcode; 5003ef9dff4cSZong-Zhe Yang cond = RTW89_MCC_WAIT_COND(group, func); 5004ef9dff4cSZong-Zhe Yang rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5005ef9dff4cSZong-Zhe Yang } 5006ef9dff4cSZong-Zhe Yang 5007ef9dff4cSZong-Zhe Yang static void 5008ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5009ef9dff4cSZong-Zhe Yang { 5010ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5011ef9dff4cSZong-Zhe Yang struct rtw89_completion_data data = {}; 5012ef9dff4cSZong-Zhe Yang struct rtw89_mac_mcc_tsf_rpt *rpt; 5013ef9dff4cSZong-Zhe Yang unsigned int cond; 5014ef9dff4cSZong-Zhe Yang 5015ef9dff4cSZong-Zhe Yang rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5016ef9dff4cSZong-Zhe Yang rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5017ef9dff4cSZong-Zhe Yang rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5018ef9dff4cSZong-Zhe Yang rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5019ef9dff4cSZong-Zhe Yang rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5020ef9dff4cSZong-Zhe Yang rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5021ef9dff4cSZong-Zhe Yang rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5022ef9dff4cSZong-Zhe Yang 5023214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5024214a98b1SZong-Zhe Yang "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5025214a98b1SZong-Zhe Yang rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5026214a98b1SZong-Zhe Yang rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5027214a98b1SZong-Zhe Yang 5028ef9dff4cSZong-Zhe Yang cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5029ef9dff4cSZong-Zhe Yang rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5030ef9dff4cSZong-Zhe Yang } 5031ef9dff4cSZong-Zhe Yang 5032ef9dff4cSZong-Zhe Yang static void 5033ef9dff4cSZong-Zhe Yang rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5034ef9dff4cSZong-Zhe Yang { 5035ef9dff4cSZong-Zhe Yang u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5036ef9dff4cSZong-Zhe Yang u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5037ef9dff4cSZong-Zhe Yang u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5038ef9dff4cSZong-Zhe Yang u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5039ef9dff4cSZong-Zhe Yang u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5040ef9dff4cSZong-Zhe Yang struct rtw89_completion_data data = {}; 5041ef9dff4cSZong-Zhe Yang unsigned int cond; 5042ef9dff4cSZong-Zhe Yang bool rsp = true; 5043ef9dff4cSZong-Zhe Yang bool err; 5044ef9dff4cSZong-Zhe Yang u8 func; 5045ef9dff4cSZong-Zhe Yang 5046ef9dff4cSZong-Zhe Yang switch (status) { 5047ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_ADD_ROLE_OK: 5048ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5049ef9dff4cSZong-Zhe Yang func = H2C_FUNC_ADD_MCC; 5050ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5051ef9dff4cSZong-Zhe Yang break; 5052ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_START_GROUP_OK: 5053ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_START_GROUP_FAIL: 5054ef9dff4cSZong-Zhe Yang func = H2C_FUNC_START_MCC; 5055ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5056ef9dff4cSZong-Zhe Yang break; 5057ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_STOP_GROUP_OK: 5058ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5059ef9dff4cSZong-Zhe Yang func = H2C_FUNC_STOP_MCC; 5060ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5061ef9dff4cSZong-Zhe Yang break; 5062ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DEL_GROUP_OK: 5063ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5064ef9dff4cSZong-Zhe Yang func = H2C_FUNC_DEL_MCC_GROUP; 5065ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5066ef9dff4cSZong-Zhe Yang break; 5067ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_RESET_GROUP_OK: 5068ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5069ef9dff4cSZong-Zhe Yang func = H2C_FUNC_RESET_MCC_GROUP; 5070ef9dff4cSZong-Zhe Yang err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5071ef9dff4cSZong-Zhe Yang break; 5072ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_SWITCH_CH_OK: 5073ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5074ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL0_OK: 5075ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL0_FAIL: 5076ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL1_OK: 5077ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TXNULL1_FAIL: 5078ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_SWITCH_EARLY: 5079ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_TBTT: 5080ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DURATION_START: 5081ef9dff4cSZong-Zhe Yang case RTW89_MAC_MCC_DURATION_END: 5082ef9dff4cSZong-Zhe Yang rsp = false; 5083ef9dff4cSZong-Zhe Yang break; 5084ef9dff4cSZong-Zhe Yang default: 5085214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5086ef9dff4cSZong-Zhe Yang "invalid MCC C2H STS RPT: status %d\n", status); 5087ef9dff4cSZong-Zhe Yang return; 5088ef9dff4cSZong-Zhe Yang } 5089ef9dff4cSZong-Zhe Yang 5090214a98b1SZong-Zhe Yang rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5091214a98b1SZong-Zhe Yang "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5092214a98b1SZong-Zhe Yang group, macid, status, (u64)tsf_high << 32 | tsf_low); 5093ef9dff4cSZong-Zhe Yang 5094ef9dff4cSZong-Zhe Yang if (!rsp) 5095ef9dff4cSZong-Zhe Yang return; 5096ef9dff4cSZong-Zhe Yang 5097ef9dff4cSZong-Zhe Yang data.err = err; 5098ef9dff4cSZong-Zhe Yang cond = RTW89_MCC_WAIT_COND(group, func); 5099ef9dff4cSZong-Zhe Yang rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5100ef9dff4cSZong-Zhe Yang } 5101ef9dff4cSZong-Zhe Yang 5102e3ec7017SPing-Ke Shih static 5103e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5104e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 5105e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5106e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 51072b8219e9SPo Hao Huang [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5108e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 5109e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 511089590777SPo Hao Huang [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5111f4a43c3bSDian-Syuan Yang [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5112d2b6da24SPo-Hao Huang [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5113e3ec7017SPing-Ke Shih }; 5114e3ec7017SPing-Ke Shih 5115e3ec7017SPing-Ke Shih static 5116e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5117e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 5118e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5119e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5120e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5121fccca934SPing-Ke Shih [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5122e3ec7017SPing-Ke Shih }; 5123e3ec7017SPing-Ke Shih 5124ef9dff4cSZong-Zhe Yang static 5125ef9dff4cSZong-Zhe Yang void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5126ef9dff4cSZong-Zhe Yang struct sk_buff *c2h, u32 len) = { 5127ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5128ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5129ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5130ef9dff4cSZong-Zhe Yang [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5131ef9dff4cSZong-Zhe Yang }; 5132ef9dff4cSZong-Zhe Yang 5133bcbefbd0SPo-Hao Huang static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 5134bcbefbd0SPo-Hao Huang struct sk_buff *skb) 5135bcbefbd0SPo-Hao Huang { 5136bcbefbd0SPo-Hao Huang const struct rtw89_c2h_scanofld *c2h = 5137bcbefbd0SPo-Hao Huang (const struct rtw89_c2h_scanofld *)skb->data; 5138bcbefbd0SPo-Hao Huang struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5139bcbefbd0SPo-Hao Huang struct rtw89_completion_data data = {}; 51404ba24331SPo-Hao Huang unsigned int cond; 5141bcbefbd0SPo-Hao Huang u8 status, reason; 5142bcbefbd0SPo-Hao Huang 5143bcbefbd0SPo-Hao Huang status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5144bcbefbd0SPo-Hao Huang reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5145bcbefbd0SPo-Hao Huang data.err = status != RTW89_SCAN_STATUS_SUCCESS; 5146bcbefbd0SPo-Hao Huang 51474ba24331SPo-Hao Huang if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 51484ba24331SPo-Hao Huang if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 51494ba24331SPo-Hao Huang cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 51504ba24331SPo-Hao Huang else 51514ba24331SPo-Hao Huang cond = RTW89_SCANOFLD_WAIT_COND_STOP; 51524ba24331SPo-Hao Huang 51534ba24331SPo-Hao Huang rtw89_complete_cond(fw_ofld_wait, cond, &data); 51544ba24331SPo-Hao Huang } 5155bcbefbd0SPo-Hao Huang } 5156bcbefbd0SPo-Hao Huang 5157bcbefbd0SPo-Hao Huang bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5158bcbefbd0SPo-Hao Huang u8 class, u8 func) 5159860e8263SZong-Zhe Yang { 5160860e8263SZong-Zhe Yang switch (class) { 5161860e8263SZong-Zhe Yang default: 5162860e8263SZong-Zhe Yang return false; 516332bb12ebSZong-Zhe Yang case RTW89_MAC_C2H_CLASS_INFO: 516432bb12ebSZong-Zhe Yang switch (func) { 516532bb12ebSZong-Zhe Yang default: 516632bb12ebSZong-Zhe Yang return false; 516732bb12ebSZong-Zhe Yang case RTW89_MAC_C2H_FUNC_REC_ACK: 516832bb12ebSZong-Zhe Yang case RTW89_MAC_C2H_FUNC_DONE_ACK: 516932bb12ebSZong-Zhe Yang return true; 517032bb12ebSZong-Zhe Yang } 51718febd68bSZong-Zhe Yang case RTW89_MAC_C2H_CLASS_OFLD: 51728febd68bSZong-Zhe Yang switch (func) { 51738febd68bSZong-Zhe Yang default: 51748febd68bSZong-Zhe Yang return false; 5175bcbefbd0SPo-Hao Huang case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 5176bcbefbd0SPo-Hao Huang rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 5177bcbefbd0SPo-Hao Huang return false; 51788febd68bSZong-Zhe Yang case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 51798febd68bSZong-Zhe Yang return true; 51808febd68bSZong-Zhe Yang } 5181860e8263SZong-Zhe Yang case RTW89_MAC_C2H_CLASS_MCC: 5182860e8263SZong-Zhe Yang return true; 5183860e8263SZong-Zhe Yang } 5184860e8263SZong-Zhe Yang } 5185860e8263SZong-Zhe Yang 5186e3ec7017SPing-Ke Shih void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5187e3ec7017SPing-Ke Shih u32 len, u8 class, u8 func) 5188e3ec7017SPing-Ke Shih { 5189e3ec7017SPing-Ke Shih void (*handler)(struct rtw89_dev *rtwdev, 5190e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = NULL; 5191e3ec7017SPing-Ke Shih 5192e3ec7017SPing-Ke Shih switch (class) { 5193e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_INFO: 5194e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 5195e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_info_handler[func]; 5196e3ec7017SPing-Ke Shih break; 5197e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_OFLD: 5198e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 5199e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_ofld_handler[func]; 5200e3ec7017SPing-Ke Shih break; 5201ef9dff4cSZong-Zhe Yang case RTW89_MAC_C2H_CLASS_MCC: 5202ef9dff4cSZong-Zhe Yang if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 5203ef9dff4cSZong-Zhe Yang handler = rtw89_mac_c2h_mcc_handler[func]; 5204ef9dff4cSZong-Zhe Yang break; 5205e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_FWDBG: 5206e3ec7017SPing-Ke Shih return; 5207e3ec7017SPing-Ke Shih default: 5208e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d not support\n", class); 5209e3ec7017SPing-Ke Shih return; 5210e3ec7017SPing-Ke Shih } 5211e3ec7017SPing-Ke Shih if (!handler) { 5212e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 5213e3ec7017SPing-Ke Shih func); 5214e3ec7017SPing-Ke Shih return; 5215e3ec7017SPing-Ke Shih } 5216e3ec7017SPing-Ke Shih handler(rtwdev, skb, len); 5217e3ec7017SPing-Ke Shih } 5218e3ec7017SPing-Ke Shih 521906b26738SZong-Zhe Yang static 522006b26738SZong-Zhe Yang bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 5221e3ec7017SPing-Ke Shih enum rtw89_phy_idx phy_idx, 5222e3ec7017SPing-Ke Shih u32 reg_base, u32 *cr) 5223e3ec7017SPing-Ke Shih { 5224e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 5225e3ec7017SPing-Ke Shih enum rtw89_qta_mode mode = dle_mem->mode; 5226c220d08eSPing-Ke Shih u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 5227e3ec7017SPing-Ke Shih 522806b26738SZong-Zhe Yang if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 5229e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 5230e3ec7017SPing-Ke Shih addr); 5231e3ec7017SPing-Ke Shih goto error; 5232e3ec7017SPing-Ke Shih } 5233e3ec7017SPing-Ke Shih 523406b26738SZong-Zhe Yang if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 5235e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_SCC) { 5236e3ec7017SPing-Ke Shih rtw89_err(rtwdev, 5237e3ec7017SPing-Ke Shih "[TXPWR] addr=0x%x but hw not enable\n", 5238e3ec7017SPing-Ke Shih addr); 5239e3ec7017SPing-Ke Shih goto error; 5240e3ec7017SPing-Ke Shih } 5241e3ec7017SPing-Ke Shih 5242e3ec7017SPing-Ke Shih *cr = addr; 5243e3ec7017SPing-Ke Shih return true; 5244e3ec7017SPing-Ke Shih 5245e3ec7017SPing-Ke Shih error: 5246e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 5247e3ec7017SPing-Ke Shih addr, phy_idx); 5248e3ec7017SPing-Ke Shih 5249e3ec7017SPing-Ke Shih return false; 5250e3ec7017SPing-Ke Shih } 5251e3ec7017SPing-Ke Shih 5252b16daa62SPing-Ke Shih static 5253b16daa62SPing-Ke Shih int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 5254e3ec7017SPing-Ke Shih { 5255c220d08eSPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 525621087188SPing-Ke Shih int ret; 5257e3ec7017SPing-Ke Shih 5258e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5259e3ec7017SPing-Ke Shih if (ret) 5260e3ec7017SPing-Ke Shih return ret; 5261e3ec7017SPing-Ke Shih 5262e3ec7017SPing-Ke Shih if (!enable) { 5263e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 526421087188SPing-Ke Shih return 0; 5265e3ec7017SPing-Ke Shih } 5266e3ec7017SPing-Ke Shih 5267e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 5268e3ec7017SPing-Ke Shih B_AX_APP_MAC_INFO_RPT | 5269e3ec7017SPing-Ke Shih B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 5270e3ec7017SPing-Ke Shih B_AX_PPDU_STAT_RPT_CRC32); 5271e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 5272e3ec7017SPing-Ke Shih RTW89_PRPT_DEST_HOST); 5273e3ec7017SPing-Ke Shih 527421087188SPing-Ke Shih return 0; 5275e3ec7017SPing-Ke Shih } 5276e3ec7017SPing-Ke Shih 5277e3ec7017SPing-Ke Shih void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 5278e3ec7017SPing-Ke Shih { 5279e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_SH 5 5280e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_SH 4 5281e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_MAX 255 5282e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_MAX 255 5283e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_DEF 88 5284e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_DEF 4080 5285fbd1829dSZong-Zhe Yang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5286e3ec7017SPing-Ke Shih struct ieee80211_hw *hw = rtwdev->hw; 5287e3ec7017SPing-Ke Shih u32 rts_threshold = hw->wiphy->rts_threshold; 5288e3ec7017SPing-Ke Shih u32 time_th, len_th; 5289e3ec7017SPing-Ke Shih u32 reg; 5290e3ec7017SPing-Ke Shih 5291e3ec7017SPing-Ke Shih if (rts_threshold == (u32)-1) { 5292e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_DEF; 5293e3ec7017SPing-Ke Shih len_th = MAC_AX_LEN_TH_DEF; 5294e3ec7017SPing-Ke Shih } else { 5295e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 5296e3ec7017SPing-Ke Shih len_th = rts_threshold; 5297e3ec7017SPing-Ke Shih } 5298e3ec7017SPing-Ke Shih 5299e3ec7017SPing-Ke Shih time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 5300e3ec7017SPing-Ke Shih len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 5301e3ec7017SPing-Ke Shih 5302fbd1829dSZong-Zhe Yang reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 5303e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 5304e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 5305e3ec7017SPing-Ke Shih } 5306e3ec7017SPing-Ke Shih 5307e3ec7017SPing-Ke Shih void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 5308e3ec7017SPing-Ke Shih { 5309e3ec7017SPing-Ke Shih bool empty; 5310e3ec7017SPing-Ke Shih int ret; 5311e3ec7017SPing-Ke Shih 5312e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5313e3ec7017SPing-Ke Shih return; 5314e3ec7017SPing-Ke Shih 5315e3ec7017SPing-Ke Shih ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 5316e3ec7017SPing-Ke Shih 10000, 200000, false, rtwdev); 5317e3ec7017SPing-Ke Shih if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 5318e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "timed out to flush queues\n"); 5319e3ec7017SPing-Ke Shih } 5320e3ec7017SPing-Ke Shih 5321e3ec7017SPing-Ke Shih int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 5322e3ec7017SPing-Ke Shih { 5323e3ec7017SPing-Ke Shih u8 val; 5324e3ec7017SPing-Ke Shih u16 val16; 5325e3ec7017SPing-Ke Shih u32 val32; 5326e3ec7017SPing-Ke Shih int ret; 5327e3ec7017SPing-Ke Shih 5328e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 53295c3afcbaSPing-Ke Shih if (rtwdev->chip->chip_id != RTL8851B) 5330e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 5331e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 5332e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 5333e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 53345c3afcbaSPing-Ke Shih if (rtwdev->chip->chip_id != RTL8851B) 5335e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 5336e3ec7017SPing-Ke Shih 5337e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 5338e3ec7017SPing-Ke Shih val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 5339e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 5340e3ec7017SPing-Ke Shih 5341e3ec7017SPing-Ke Shih ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 5342e3ec7017SPing-Ke Shih if (ret) { 5343e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 5344e3ec7017SPing-Ke Shih return ret; 5345e3ec7017SPing-Ke Shih } 5346e3ec7017SPing-Ke Shih val32 = val32 & B_AX_WL_RX_CTRL; 5347e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 5348e3ec7017SPing-Ke Shih if (ret) { 5349e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 5350e3ec7017SPing-Ke Shih return ret; 5351e3ec7017SPing-Ke Shih } 5352e3ec7017SPing-Ke Shih 5353e3ec7017SPing-Ke Shih switch (coex->pta_mode) { 5354e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_RTK_MODE: 5355e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5356e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 5357e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 5358e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5359e3ec7017SPing-Ke Shih 5360e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 5361e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 5362e3ec7017SPing-Ke Shih 5363e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 5364e3ec7017SPing-Ke Shih val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 5365e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 5366e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 5367e3ec7017SPing-Ke Shih break; 5368e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_CSR_MODE: 5369e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5370e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 5371e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 5372e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5373e3ec7017SPing-Ke Shih 5374e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 5375e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 5376e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 5377e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 5378e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 5379e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_STAT_DELAY_MASK; 5380e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 5381e3ec7017SPing-Ke Shih val16 |= B_AX_ENHANCED_BT; 5382e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 5383e3ec7017SPing-Ke Shih 5384e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 5385e3ec7017SPing-Ke Shih break; 5386e3ec7017SPing-Ke Shih default: 5387e3ec7017SPing-Ke Shih return -EINVAL; 5388e3ec7017SPing-Ke Shih } 5389e3ec7017SPing-Ke Shih 5390e3ec7017SPing-Ke Shih switch (coex->direction) { 5391e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INNER: 5392e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5393e3ec7017SPing-Ke Shih val = (val & ~BIT(2)) | BIT(1); 5394e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5395e3ec7017SPing-Ke Shih break; 5396e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_OUTPUT: 5397e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5398e3ec7017SPing-Ke Shih val = val | BIT(1) | BIT(0); 5399e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5400e3ec7017SPing-Ke Shih break; 5401e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INPUT: 5402e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5403e3ec7017SPing-Ke Shih val = val & ~(BIT(2) | BIT(1)); 5404e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5405e3ec7017SPing-Ke Shih break; 5406e3ec7017SPing-Ke Shih default: 5407e3ec7017SPing-Ke Shih return -EINVAL; 5408e3ec7017SPing-Ke Shih } 5409e3ec7017SPing-Ke Shih 5410e3ec7017SPing-Ke Shih return 0; 5411e3ec7017SPing-Ke Shih } 5412861e58c8SZong-Zhe Yang EXPORT_SYMBOL(rtw89_mac_coex_init); 5413e3ec7017SPing-Ke Shih 5414065cf8f9SChia-Yuan Li int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 5415065cf8f9SChia-Yuan Li const struct rtw89_mac_ax_coex *coex) 5416065cf8f9SChia-Yuan Li { 5417065cf8f9SChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 5418065cf8f9SChia-Yuan Li B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 5419065cf8f9SChia-Yuan Li rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 5420065cf8f9SChia-Yuan Li rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 5421065cf8f9SChia-Yuan Li rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 5422065cf8f9SChia-Yuan Li 5423065cf8f9SChia-Yuan Li switch (coex->pta_mode) { 5424065cf8f9SChia-Yuan Li case RTW89_MAC_AX_COEX_RTK_MODE: 5425065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5426065cf8f9SChia-Yuan Li MAC_AX_RTK_MODE); 5427065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 5428065cf8f9SChia-Yuan Li B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 5429065cf8f9SChia-Yuan Li break; 5430065cf8f9SChia-Yuan Li case RTW89_MAC_AX_COEX_CSR_MODE: 5431065cf8f9SChia-Yuan Li rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5432065cf8f9SChia-Yuan Li MAC_AX_CSR_MODE); 5433065cf8f9SChia-Yuan Li break; 5434065cf8f9SChia-Yuan Li default: 5435065cf8f9SChia-Yuan Li return -EINVAL; 5436065cf8f9SChia-Yuan Li } 5437065cf8f9SChia-Yuan Li 5438065cf8f9SChia-Yuan Li return 0; 5439065cf8f9SChia-Yuan Li } 5440065cf8f9SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 5441065cf8f9SChia-Yuan Li 5442e3ec7017SPing-Ke Shih int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5443e3ec7017SPing-Ke Shih const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5444e3ec7017SPing-Ke Shih { 54458001c741SPing-Ke Shih u32 val = 0, ret; 5446e3ec7017SPing-Ke Shih 54478001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_bt) 54488001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 54498001c741SPing-Ke Shih 54508001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_bt_sw_en) 54518001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 54528001c741SPing-Ke Shih 54538001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_wl) 54548001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 54558001c741SPing-Ke Shih 54568001c741SPing-Ke Shih if (gnt_cfg->band[0].gnt_wl_sw_en) 54578001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 54588001c741SPing-Ke Shih 54598001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_bt) 54608001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 54618001c741SPing-Ke Shih 54628001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_bt_sw_en) 54638001c741SPing-Ke Shih val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 54648001c741SPing-Ke Shih 54658001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_wl) 54668001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 54678001c741SPing-Ke Shih 54688001c741SPing-Ke Shih if (gnt_cfg->band[1].gnt_wl_sw_en) 54698001c741SPing-Ke Shih val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 54708001c741SPing-Ke Shih 5471e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 5472e3ec7017SPing-Ke Shih if (ret) { 5473e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write LTE fail!\n"); 5474e3ec7017SPing-Ke Shih return ret; 5475e3ec7017SPing-Ke Shih } 5476e3ec7017SPing-Ke Shih 5477e3ec7017SPing-Ke Shih return 0; 5478e3ec7017SPing-Ke Shih } 5479feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 5480feed6541SChia-Yuan Li 5481feed6541SChia-Yuan Li int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 5482feed6541SChia-Yuan Li const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5483feed6541SChia-Yuan Li { 5484feed6541SChia-Yuan Li u32 val = 0; 5485feed6541SChia-Yuan Li 5486feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_bt) 5487feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5488feed6541SChia-Yuan Li B_AX_GNT_BT_TX_VAL; 5489feed6541SChia-Yuan Li else 5490feed6541SChia-Yuan Li val |= B_AX_WL_ACT_VAL; 5491feed6541SChia-Yuan Li 5492feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_bt_sw_en) 5493feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5494feed6541SChia-Yuan Li B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5495feed6541SChia-Yuan Li 5496feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_wl) 5497feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5498feed6541SChia-Yuan Li B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5499feed6541SChia-Yuan Li 5500feed6541SChia-Yuan Li if (gnt_cfg->band[0].gnt_wl_sw_en) 5501feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5502feed6541SChia-Yuan Li B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5503feed6541SChia-Yuan Li 5504feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_bt) 5505feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5506feed6541SChia-Yuan Li B_AX_GNT_BT_TX_VAL; 5507feed6541SChia-Yuan Li else 5508feed6541SChia-Yuan Li val |= B_AX_WL_ACT_VAL; 5509feed6541SChia-Yuan Li 5510feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_bt_sw_en) 5511feed6541SChia-Yuan Li val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5512feed6541SChia-Yuan Li B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5513feed6541SChia-Yuan Li 5514feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_wl) 5515feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5516feed6541SChia-Yuan Li B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5517feed6541SChia-Yuan Li 5518feed6541SChia-Yuan Li if (gnt_cfg->band[1].gnt_wl_sw_en) 5519feed6541SChia-Yuan Li val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5520feed6541SChia-Yuan Li B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5521feed6541SChia-Yuan Li 5522feed6541SChia-Yuan Li rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5523feed6541SChia-Yuan Li 5524feed6541SChia-Yuan Li return 0; 5525feed6541SChia-Yuan Li } 5526feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5527e3ec7017SPing-Ke Shih 5528e3ec7017SPing-Ke Shih int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5529e3ec7017SPing-Ke Shih { 5530e3ec7017SPing-Ke Shih u32 reg; 553128e7ea8aSPing-Ke Shih u16 val; 5532e3ec7017SPing-Ke Shih int ret; 5533e3ec7017SPing-Ke Shih 5534e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5535e3ec7017SPing-Ke Shih if (ret) 5536e3ec7017SPing-Ke Shih return ret; 5537e3ec7017SPing-Ke Shih 5538c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 5539e3ec7017SPing-Ke Shih val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5540e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5541e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5542e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5543e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5544e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5545e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 554628e7ea8aSPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 554728e7ea8aSPing-Ke Shih B_AX_PLT_EN; 554828e7ea8aSPing-Ke Shih rtw89_write16(rtwdev, reg, val); 5549e3ec7017SPing-Ke Shih 5550e3ec7017SPing-Ke Shih return 0; 5551e3ec7017SPing-Ke Shih } 5552e3ec7017SPing-Ke Shih 5553e3ec7017SPing-Ke Shih void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5554e3ec7017SPing-Ke Shih { 5555e3ec7017SPing-Ke Shih u32 fw_sb; 5556e3ec7017SPing-Ke Shih 5557e3ec7017SPing-Ke Shih fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5558e3ec7017SPing-Ke Shih fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5559e3ec7017SPing-Ke Shih fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5560e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5561e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5562e3ec7017SPing-Ke Shih else 5563e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5564e3ec7017SPing-Ke Shih val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5565e3ec7017SPing-Ke Shih val = B_AX_TOGGLE | 5566e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5567e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5568e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5569e3ec7017SPing-Ke Shih fsleep(1000); /* avoid BT FW loss information */ 5570e3ec7017SPing-Ke Shih } 5571e3ec7017SPing-Ke Shih 5572e3ec7017SPing-Ke Shih u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5573e3ec7017SPing-Ke Shih { 5574e3ec7017SPing-Ke Shih return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5575e3ec7017SPing-Ke Shih } 5576e3ec7017SPing-Ke Shih 5577e3ec7017SPing-Ke Shih int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5578e3ec7017SPing-Ke Shih { 5579e3ec7017SPing-Ke Shih u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5580e3ec7017SPing-Ke Shih 5581e3ec7017SPing-Ke Shih val = wl ? val | BIT(2) : val & ~BIT(2); 5582e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5583e3ec7017SPing-Ke Shih 5584e3ec7017SPing-Ke Shih return 0; 5585e3ec7017SPing-Ke Shih } 5586feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5587feed6541SChia-Yuan Li 5588feed6541SChia-Yuan Li int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5589feed6541SChia-Yuan Li { 5590feed6541SChia-Yuan Li struct rtw89_btc *btc = &rtwdev->btc; 5591feed6541SChia-Yuan Li struct rtw89_btc_dm *dm = &btc->dm; 5592feed6541SChia-Yuan Li struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5593feed6541SChia-Yuan Li int i; 5594feed6541SChia-Yuan Li 5595feed6541SChia-Yuan Li if (wl) 5596feed6541SChia-Yuan Li return 0; 5597feed6541SChia-Yuan Li 5598feed6541SChia-Yuan Li for (i = 0; i < RTW89_PHY_MAX; i++) { 5599feed6541SChia-Yuan Li g[i].gnt_bt_sw_en = 1; 5600feed6541SChia-Yuan Li g[i].gnt_bt = 1; 5601feed6541SChia-Yuan Li g[i].gnt_wl_sw_en = 1; 5602feed6541SChia-Yuan Li g[i].gnt_wl = 0; 5603feed6541SChia-Yuan Li } 5604feed6541SChia-Yuan Li 5605feed6541SChia-Yuan Li return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5606feed6541SChia-Yuan Li } 5607feed6541SChia-Yuan Li EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5608e3ec7017SPing-Ke Shih 5609e3ec7017SPing-Ke Shih bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5610e3ec7017SPing-Ke Shih { 5611ae4e1adbSChing-Te Ku const struct rtw89_chip_info *chip = rtwdev->chip; 5612ae4e1adbSChing-Te Ku u8 val = 0; 5613e3ec7017SPing-Ke Shih 5614ae4e1adbSChing-Te Ku if (chip->chip_id == RTL8852C) 5615ae4e1adbSChing-Te Ku return false; 56163ac4b57cSChing-Te Ku else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 56173ac4b57cSChing-Te Ku chip->chip_id == RTL8851B) 5618ae4e1adbSChing-Te Ku val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5619ae4e1adbSChing-Te Ku B_AX_LTE_MUX_CTRL_PATH >> 24); 5620ae4e1adbSChing-Te Ku 5621ae4e1adbSChing-Te Ku return !!val; 5622e3ec7017SPing-Ke Shih } 5623e3ec7017SPing-Ke Shih 56248c7e9cebSChing-Te Ku u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 56258c7e9cebSChing-Te Ku { 56268c7e9cebSChing-Te Ku u32 reg; 56278c7e9cebSChing-Te Ku u16 cnt; 56288c7e9cebSChing-Te Ku 5629c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 56308c7e9cebSChing-Te Ku cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 56318c7e9cebSChing-Te Ku rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 56328c7e9cebSChing-Te Ku 56338c7e9cebSChing-Te Ku return cnt; 56348c7e9cebSChing-Te Ku } 56358c7e9cebSChing-Te Ku 56368a66293eSPing-Ke Shih static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 56378a66293eSPing-Ke Shih bool keep) 56388a66293eSPing-Ke Shih { 56398a66293eSPing-Ke Shih u32 reg; 56408a66293eSPing-Ke Shih 5641b6509815SZong-Zhe Yang if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 5642b6509815SZong-Zhe Yang return; 5643b6509815SZong-Zhe Yang 56448a66293eSPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5645c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 56468a66293eSPing-Ke Shih if (keep) { 56478a66293eSPing-Ke Shih set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 56488a66293eSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 56498a66293eSPing-Ke Shih BFRP_RX_STANDBY_TIMER_KEEP); 56508a66293eSPing-Ke Shih } else { 56518a66293eSPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 56528a66293eSPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 56538a66293eSPing-Ke Shih BFRP_RX_STANDBY_TIMER_RELEASE); 56548a66293eSPing-Ke Shih } 56558a66293eSPing-Ke Shih } 56568a66293eSPing-Ke Shih 565731b7cd19SZong-Zhe Yang void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5658e3ec7017SPing-Ke Shih { 56595fa1c5d4SZong-Zhe Yang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5660e3ec7017SPing-Ke Shih u32 reg; 56615fa1c5d4SZong-Zhe Yang u32 mask = mac->bfee_ctrl.mask; 5662e3ec7017SPing-Ke Shih 5663e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 56645fa1c5d4SZong-Zhe Yang reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 5665e3ec7017SPing-Ke Shih if (en) { 5666e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5667e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, mask); 5668e3ec7017SPing-Ke Shih } else { 5669e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5670e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, mask); 5671e3ec7017SPing-Ke Shih } 5672e3ec7017SPing-Ke Shih } 5673e3ec7017SPing-Ke Shih 567431b7cd19SZong-Zhe Yang static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 5675e3ec7017SPing-Ke Shih { 5676e3ec7017SPing-Ke Shih u32 reg; 5677e3ec7017SPing-Ke Shih u32 val32; 5678e3ec7017SPing-Ke Shih int ret; 5679e3ec7017SPing-Ke Shih 5680e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5681e3ec7017SPing-Ke Shih if (ret) 5682e3ec7017SPing-Ke Shih return ret; 5683e3ec7017SPing-Ke Shih 5684e3ec7017SPing-Ke Shih /* AP mode set tx gid to 63 */ 5685e3ec7017SPing-Ke Shih /* STA mode set tx gid to 0(default) */ 5686c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 5687e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5688e3ec7017SPing-Ke Shih 5689c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5690e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5691e3ec7017SPing-Ke Shih 5692c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 56938a66293eSPing-Ke Shih val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5694e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 56958a66293eSPing-Ke Shih rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5696e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5697e3ec7017SPing-Ke Shih 5698c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5699e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5700e3ec7017SPing-Ke Shih B_AX_BFMEE_USE_NSTS | 5701e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_GID_SEL | 5702e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_FORCE_RETE_EN); 5703c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5704e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, 5705e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5706e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5707e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5708e3ec7017SPing-Ke Shih 5709c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 571062440fbeSPing-Ke Shih rtw89_write32_set(rtwdev, reg, 571162440fbeSPing-Ke Shih B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 571262440fbeSPing-Ke Shih 5713e3ec7017SPing-Ke Shih return 0; 5714e3ec7017SPing-Ke Shih } 5715e3ec7017SPing-Ke Shih 571631b7cd19SZong-Zhe Yang static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 5717e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 5718e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5719e3ec7017SPing-Ke Shih { 5720e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5721e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 5722e3ec7017SPing-Ke Shih u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5723e3ec7017SPing-Ke Shih u8 port_sel = rtwvif->port; 5724e3ec7017SPing-Ke Shih u8 sound_dim = 3, t; 5725046d2e7cSSriram R u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5726e3ec7017SPing-Ke Shih u32 reg; 5727e3ec7017SPing-Ke Shih u16 val; 5728e3ec7017SPing-Ke Shih int ret; 5729e3ec7017SPing-Ke Shih 5730e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5731e3ec7017SPing-Ke Shih if (ret) 5732e3ec7017SPing-Ke Shih return ret; 5733e3ec7017SPing-Ke Shih 5734e3ec7017SPing-Ke Shih if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5735e3ec7017SPing-Ke Shih (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5736e3ec7017SPing-Ke Shih ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5737e3ec7017SPing-Ke Shih stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5738e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5739e3ec7017SPing-Ke Shih phy_cap[5]); 5740e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 5741e3ec7017SPing-Ke Shih } 5742046d2e7cSSriram R if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5743046d2e7cSSriram R (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5744046d2e7cSSriram R ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5745046d2e7cSSriram R stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5746e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5747046d2e7cSSriram R sta->deflink.vht_cap.cap); 5748e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 5749e3ec7017SPing-Ke Shih } 5750e3ec7017SPing-Ke Shih nc = min(nc, sound_dim); 5751e3ec7017SPing-Ke Shih nr = min(nr, sound_dim); 5752e3ec7017SPing-Ke Shih 5753c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5754e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5755e3ec7017SPing-Ke Shih 5756e3ec7017SPing-Ke Shih val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5757e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5758e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5759e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5760e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5761e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5762e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5763e3ec7017SPing-Ke Shih 5764e3ec7017SPing-Ke Shih if (port_sel == 0) 5765c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5766e3ec7017SPing-Ke Shih else 5767c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5768e3ec7017SPing-Ke Shih 5769e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 5770e3ec7017SPing-Ke Shih 5771e3ec7017SPing-Ke Shih return 0; 5772e3ec7017SPing-Ke Shih } 5773e3ec7017SPing-Ke Shih 577431b7cd19SZong-Zhe Yang static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 5775e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 5776e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5777e3ec7017SPing-Ke Shih { 5778e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5779e3ec7017SPing-Ke Shih u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5780e3ec7017SPing-Ke Shih u32 reg; 5781e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 5782e3ec7017SPing-Ke Shih int ret; 5783e3ec7017SPing-Ke Shih 5784e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5785e3ec7017SPing-Ke Shih if (ret) 5786e3ec7017SPing-Ke Shih return ret; 5787e3ec7017SPing-Ke Shih 5788046d2e7cSSriram R if (sta->deflink.he_cap.has_he) { 5789e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5790e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5791e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5792e3ec7017SPing-Ke Shih } 5793046d2e7cSSriram R if (sta->deflink.vht_cap.vht_supported) { 5794e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5795e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5796e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5797e3ec7017SPing-Ke Shih } 5798046d2e7cSSriram R if (sta->deflink.ht_cap.ht_supported) { 5799e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5800e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5801e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5802e3ec7017SPing-Ke Shih } 5803c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5804e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5805e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5806e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, 5807c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5808e3ec7017SPing-Ke Shih rrsc); 5809e3ec7017SPing-Ke Shih 5810e3ec7017SPing-Ke Shih return 0; 5811e3ec7017SPing-Ke Shih } 5812e3ec7017SPing-Ke Shih 581331b7cd19SZong-Zhe Yang static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 581431b7cd19SZong-Zhe Yang struct ieee80211_vif *vif, 5815e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5816e3ec7017SPing-Ke Shih { 5817e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5818e3ec7017SPing-Ke Shih 5819e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) { 5820e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, 5821e3ec7017SPing-Ke Shih "initialize bfee for new association\n"); 582231b7cd19SZong-Zhe Yang rtw89_mac_init_bfee_ax(rtwdev, rtwvif->mac_idx); 582331b7cd19SZong-Zhe Yang rtw89_mac_set_csi_para_reg_ax(rtwdev, vif, sta); 582431b7cd19SZong-Zhe Yang rtw89_mac_csi_rrsc_ax(rtwdev, vif, sta); 5825e3ec7017SPing-Ke Shih } 5826e3ec7017SPing-Ke Shih } 5827e3ec7017SPing-Ke Shih 5828e3ec7017SPing-Ke Shih void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5829e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 5830e3ec7017SPing-Ke Shih { 5831e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5832e3ec7017SPing-Ke Shih 5833e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 5834e3ec7017SPing-Ke Shih } 5835e3ec7017SPing-Ke Shih 5836e3ec7017SPing-Ke Shih void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5837e3ec7017SPing-Ke Shih struct ieee80211_bss_conf *conf) 5838e3ec7017SPing-Ke Shih { 5839e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5840e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 5841e3ec7017SPing-Ke Shih __le32 *p; 5842e3ec7017SPing-Ke Shih 5843e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 5844e3ec7017SPing-Ke Shih 5845e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.membership; 5846c220d08eSPing-Ke Shih rtw89_write32(rtwdev, 5847c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 5848e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 5849c220d08eSPing-Ke Shih rtw89_write32(rtwdev, 5850c220d08eSPing-Ke Shih rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 5851e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 5852e3ec7017SPing-Ke Shih 5853e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.position; 5854c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 5855e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 5856c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 5857e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 5858c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 5859e3ec7017SPing-Ke Shih le32_to_cpu(p[2])); 5860c220d08eSPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 5861e3ec7017SPing-Ke Shih le32_to_cpu(p[3])); 5862e3ec7017SPing-Ke Shih } 5863e3ec7017SPing-Ke Shih 5864e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data { 5865e3ec7017SPing-Ke Shih struct rtw89_dev *rtwdev; 5866e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta; 5867e3ec7017SPing-Ke Shih int count; 5868e3ec7017SPing-Ke Shih }; 5869e3ec7017SPing-Ke Shih 5870e3ec7017SPing-Ke Shih static 5871e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 5872e3ec7017SPing-Ke Shih { 5873e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data *iter_data = 5874e3ec7017SPing-Ke Shih (struct rtw89_mac_bf_monitor_iter_data *)data; 5875e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta = iter_data->down_sta; 5876e3ec7017SPing-Ke Shih int *count = &iter_data->count; 5877e3ec7017SPing-Ke Shih 5878e3ec7017SPing-Ke Shih if (down_sta == sta) 5879e3ec7017SPing-Ke Shih return; 5880e3ec7017SPing-Ke Shih 5881e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) 5882e3ec7017SPing-Ke Shih (*count)++; 5883e3ec7017SPing-Ke Shih } 5884e3ec7017SPing-Ke Shih 5885e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 5886e3ec7017SPing-Ke Shih struct ieee80211_sta *sta, bool disconnect) 5887e3ec7017SPing-Ke Shih { 5888e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data data; 5889e3ec7017SPing-Ke Shih 5890e3ec7017SPing-Ke Shih data.rtwdev = rtwdev; 5891e3ec7017SPing-Ke Shih data.down_sta = disconnect ? sta : NULL; 5892e3ec7017SPing-Ke Shih data.count = 0; 5893e3ec7017SPing-Ke Shih ieee80211_iterate_stations_atomic(rtwdev->hw, 5894e3ec7017SPing-Ke Shih rtw89_mac_bf_monitor_calc_iter, 5895e3ec7017SPing-Ke Shih &data); 5896e3ec7017SPing-Ke Shih 5897e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 5898e3ec7017SPing-Ke Shih if (data.count) 5899e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5900e3ec7017SPing-Ke Shih else 5901e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5902e3ec7017SPing-Ke Shih } 5903e3ec7017SPing-Ke Shih 5904e3ec7017SPing-Ke Shih void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 5905e3ec7017SPing-Ke Shih { 5906e3ec7017SPing-Ke Shih struct rtw89_traffic_stats *stats = &rtwdev->stats; 5907e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif; 59081646ce8fSYe Guojin bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 5909e3ec7017SPing-Ke Shih bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 59108a66293eSPing-Ke Shih bool keep_timer = true; 59118a66293eSPing-Ke Shih bool old_keep_timer; 59128a66293eSPing-Ke Shih 59138a66293eSPing-Ke Shih old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 59148a66293eSPing-Ke Shih 59158a66293eSPing-Ke Shih if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 59168a66293eSPing-Ke Shih keep_timer = false; 59178a66293eSPing-Ke Shih 59188a66293eSPing-Ke Shih if (keep_timer != old_keep_timer) { 59198a66293eSPing-Ke Shih rtw89_for_each_rtwvif(rtwdev, rtwvif) 59208a66293eSPing-Ke Shih rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 59218a66293eSPing-Ke Shih keep_timer); 59228a66293eSPing-Ke Shih } 5923e3ec7017SPing-Ke Shih 5924e3ec7017SPing-Ke Shih if (en == old) 5925e3ec7017SPing-Ke Shih return; 5926e3ec7017SPing-Ke Shih 5927e3ec7017SPing-Ke Shih rtw89_for_each_rtwvif(rtwdev, rtwvif) 5928e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 5929e3ec7017SPing-Ke Shih } 5930e3ec7017SPing-Ke Shih 5931e3ec7017SPing-Ke Shih static int 5932e3ec7017SPing-Ke Shih __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5933e3ec7017SPing-Ke Shih u32 tx_time) 5934e3ec7017SPing-Ke Shih { 5935e3ec7017SPing-Ke Shih #define MAC_AX_DFLT_TX_TIME 5280 5936e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 5937e3ec7017SPing-Ke Shih u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 5938e3ec7017SPing-Ke Shih u32 reg; 5939e3ec7017SPing-Ke Shih int ret = 0; 5940e3ec7017SPing-Ke Shih 5941e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 5942e3ec7017SPing-Ke Shih rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 5943e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5944e3ec7017SPing-Ke Shih } else { 5945e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5946e3ec7017SPing-Ke Shih if (ret) { 5947e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 5948e3ec7017SPing-Ke Shih return ret; 5949e3ec7017SPing-Ke Shih } 5950e3ec7017SPing-Ke Shih 5951c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 5952e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 5953e3ec7017SPing-Ke Shih max_tx_time >> 5); 5954e3ec7017SPing-Ke Shih } 5955e3ec7017SPing-Ke Shih 5956e3ec7017SPing-Ke Shih return ret; 5957e3ec7017SPing-Ke Shih } 5958e3ec7017SPing-Ke Shih 5959e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5960e3ec7017SPing-Ke Shih bool resume, u32 tx_time) 5961e3ec7017SPing-Ke Shih { 5962e3ec7017SPing-Ke Shih int ret = 0; 5963e3ec7017SPing-Ke Shih 5964e3ec7017SPing-Ke Shih if (!resume) { 5965e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = true; 5966e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5967e3ec7017SPing-Ke Shih } else { 5968e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5969e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = false; 5970e3ec7017SPing-Ke Shih } 5971e3ec7017SPing-Ke Shih 5972e3ec7017SPing-Ke Shih return ret; 5973e3ec7017SPing-Ke Shih } 5974e3ec7017SPing-Ke Shih 5975e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5976e3ec7017SPing-Ke Shih u32 *tx_time) 5977e3ec7017SPing-Ke Shih { 5978e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 5979e3ec7017SPing-Ke Shih u32 reg; 5980e3ec7017SPing-Ke Shih int ret = 0; 5981e3ec7017SPing-Ke Shih 5982e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 5983e3ec7017SPing-Ke Shih *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 5984e3ec7017SPing-Ke Shih } else { 5985e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5986e3ec7017SPing-Ke Shih if (ret) { 5987e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 5988e3ec7017SPing-Ke Shih return ret; 5989e3ec7017SPing-Ke Shih } 5990e3ec7017SPing-Ke Shih 5991c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 5992e3ec7017SPing-Ke Shih *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 5993e3ec7017SPing-Ke Shih } 5994e3ec7017SPing-Ke Shih 5995e3ec7017SPing-Ke Shih return ret; 5996e3ec7017SPing-Ke Shih } 5997e3ec7017SPing-Ke Shih 5998e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 5999e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, 6000e3ec7017SPing-Ke Shih bool resume, u8 tx_retry) 6001e3ec7017SPing-Ke Shih { 6002e3ec7017SPing-Ke Shih int ret = 0; 6003e3ec7017SPing-Ke Shih 6004e3ec7017SPing-Ke Shih rtwsta->data_tx_cnt_lmt = tx_retry; 6005e3ec7017SPing-Ke Shih 6006e3ec7017SPing-Ke Shih if (!resume) { 6007e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = true; 6008e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6009e3ec7017SPing-Ke Shih } else { 6010e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6011e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = false; 6012e3ec7017SPing-Ke Shih } 6013e3ec7017SPing-Ke Shih 6014e3ec7017SPing-Ke Shih return ret; 6015e3ec7017SPing-Ke Shih } 6016e3ec7017SPing-Ke Shih 6017e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 6018e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, u8 *tx_retry) 6019e3ec7017SPing-Ke Shih { 6020e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 6021e3ec7017SPing-Ke Shih u32 reg; 6022e3ec7017SPing-Ke Shih int ret = 0; 6023e3ec7017SPing-Ke Shih 6024e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_retry_limit) { 6025e3ec7017SPing-Ke Shih *tx_retry = rtwsta->data_tx_cnt_lmt; 6026e3ec7017SPing-Ke Shih } else { 6027e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6028e3ec7017SPing-Ke Shih if (ret) { 6029e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 6030e3ec7017SPing-Ke Shih return ret; 6031e3ec7017SPing-Ke Shih } 6032e3ec7017SPing-Ke Shih 6033c220d08eSPing-Ke Shih reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); 6034e3ec7017SPing-Ke Shih *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 6035e3ec7017SPing-Ke Shih } 6036e3ec7017SPing-Ke Shih 6037e3ec7017SPing-Ke Shih return ret; 6038e3ec7017SPing-Ke Shih } 6039e3ec7017SPing-Ke Shih 6040e3ec7017SPing-Ke Shih int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 6041e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 6042e3ec7017SPing-Ke Shih { 60437f69cd42SZong-Zhe Yang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6044e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 60457f69cd42SZong-Zhe Yang u16 set = mac->muedca_ctrl.mask; 6046e3ec7017SPing-Ke Shih u32 reg; 6047e3ec7017SPing-Ke Shih u32 ret; 6048e3ec7017SPing-Ke Shih 6049e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6050e3ec7017SPing-Ke Shih if (ret) 6051e3ec7017SPing-Ke Shih return ret; 6052e3ec7017SPing-Ke Shih 60537f69cd42SZong-Zhe Yang reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 6054e3ec7017SPing-Ke Shih if (en) 6055e3ec7017SPing-Ke Shih rtw89_write16_set(rtwdev, reg, set); 6056e3ec7017SPing-Ke Shih else 6057e3ec7017SPing-Ke Shih rtw89_write16_clr(rtwdev, reg, set); 6058e3ec7017SPing-Ke Shih 6059e3ec7017SPing-Ke Shih return 0; 6060e3ec7017SPing-Ke Shih } 60612a7e54dbSPing-Ke Shih 6062efde4f6dSPing-Ke Shih static 6063efde4f6dSPing-Ke Shih int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 60642a7e54dbSPing-Ke Shih { 60652a7e54dbSPing-Ke Shih u32 val32; 60662a7e54dbSPing-Ke Shih int ret; 60672a7e54dbSPing-Ke Shih 60682a7e54dbSPing-Ke Shih val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 60692a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 60702a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 60712a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 60722a7e54dbSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 60732a7e54dbSPing-Ke Shih rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 60742a7e54dbSPing-Ke Shih 60752a7e54dbSPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 60762a7e54dbSPing-Ke Shih 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 60772a7e54dbSPing-Ke Shih if (ret) { 60782a7e54dbSPing-Ke Shih rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 60792a7e54dbSPing-Ke Shih offset, val, mask); 60802a7e54dbSPing-Ke Shih return ret; 60812a7e54dbSPing-Ke Shih } 60822a7e54dbSPing-Ke Shih 60832a7e54dbSPing-Ke Shih return 0; 60842a7e54dbSPing-Ke Shih } 6085bdfbf06cSPing-Ke Shih 6086efde4f6dSPing-Ke Shih static 6087efde4f6dSPing-Ke Shih int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 6088bdfbf06cSPing-Ke Shih { 6089bdfbf06cSPing-Ke Shih u32 val32; 6090bdfbf06cSPing-Ke Shih int ret; 6091bdfbf06cSPing-Ke Shih 6092bdfbf06cSPing-Ke Shih val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6093bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 6094bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 6095bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 6096bdfbf06cSPing-Ke Shih FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6097bdfbf06cSPing-Ke Shih rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6098bdfbf06cSPing-Ke Shih 6099bdfbf06cSPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6100bdfbf06cSPing-Ke Shih 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6101bdfbf06cSPing-Ke Shih if (ret) { 6102bdfbf06cSPing-Ke Shih rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 6103bdfbf06cSPing-Ke Shih return ret; 6104bdfbf06cSPing-Ke Shih } 6105bdfbf06cSPing-Ke Shih 6106bdfbf06cSPing-Ke Shih *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 6107bdfbf06cSPing-Ke Shih 6108bdfbf06cSPing-Ke Shih return 0; 6109bdfbf06cSPing-Ke Shih } 61109a785583SZong-Zhe Yang 61119a785583SZong-Zhe Yang static 61129a785583SZong-Zhe Yang void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 61139a785583SZong-Zhe Yang { 61149a785583SZong-Zhe Yang static const enum rtw89_pkt_drop_sel sels[] = { 61159a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 61169a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 61179a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 61189a785583SZong-Zhe Yang RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 61199a785583SZong-Zhe Yang }; 61209a785583SZong-Zhe Yang struct rtw89_vif *rtwvif = rtwsta->rtwvif; 61219a785583SZong-Zhe Yang struct rtw89_pkt_drop_params params = {0}; 61229a785583SZong-Zhe Yang int i; 61239a785583SZong-Zhe Yang 61249a785583SZong-Zhe Yang params.mac_band = RTW89_MAC_0; 61259a785583SZong-Zhe Yang params.macid = rtwsta->mac_id; 61269a785583SZong-Zhe Yang params.port = rtwvif->port; 61279a785583SZong-Zhe Yang params.mbssid = 0; 61289a785583SZong-Zhe Yang params.tf_trs = rtwvif->trigger; 61299a785583SZong-Zhe Yang 61309a785583SZong-Zhe Yang for (i = 0; i < ARRAY_SIZE(sels); i++) { 61319a785583SZong-Zhe Yang params.sel = sels[i]; 61329a785583SZong-Zhe Yang rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 61339a785583SZong-Zhe Yang } 61349a785583SZong-Zhe Yang } 61359a785583SZong-Zhe Yang 61369a785583SZong-Zhe Yang static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 61379a785583SZong-Zhe Yang { 61389a785583SZong-Zhe Yang struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 61399a785583SZong-Zhe Yang struct rtw89_vif *rtwvif = rtwsta->rtwvif; 61409a785583SZong-Zhe Yang struct rtw89_dev *rtwdev = rtwvif->rtwdev; 61419a785583SZong-Zhe Yang struct rtw89_vif *target = data; 61429a785583SZong-Zhe Yang 61439a785583SZong-Zhe Yang if (rtwvif != target) 61449a785583SZong-Zhe Yang return; 61459a785583SZong-Zhe Yang 61469a785583SZong-Zhe Yang rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 61479a785583SZong-Zhe Yang } 61489a785583SZong-Zhe Yang 61499a785583SZong-Zhe Yang void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 61509a785583SZong-Zhe Yang { 61519a785583SZong-Zhe Yang ieee80211_iterate_stations_atomic(rtwdev->hw, 61529a785583SZong-Zhe Yang rtw89_mac_pkt_drop_vif_iter, 61539a785583SZong-Zhe Yang rtwvif); 61549a785583SZong-Zhe Yang } 615541d56769SChih-Kang Chang 615641d56769SChih-Kang Chang int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 615741d56769SChih-Kang Chang enum rtw89_mac_idx band) 615841d56769SChih-Kang Chang { 615927ea6be9SZong-Zhe Yang const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 616041d56769SChih-Kang Chang struct rtw89_pkt_drop_params params = {0}; 616141d56769SChih-Kang Chang bool empty; 616241d56769SChih-Kang Chang int i, ret = 0, try_cnt = 3; 616341d56769SChih-Kang Chang 616441d56769SChih-Kang Chang params.mac_band = band; 616541d56769SChih-Kang Chang params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 616641d56769SChih-Kang Chang 616741d56769SChih-Kang Chang for (i = 0; i < try_cnt; i++) { 616827ea6be9SZong-Zhe Yang ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 616941d56769SChih-Kang Chang 50000, false, rtwdev); 61700d1f7ff1SZong-Zhe Yang if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 617141d56769SChih-Kang Chang rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 617241d56769SChih-Kang Chang else 617341d56769SChih-Kang Chang return 0; 617441d56769SChih-Kang Chang } 617541d56769SChih-Kang Chang return ret; 617641d56769SChih-Kang Chang } 6177c220d08eSPing-Ke Shih 6178fa31a8c5SPing-Ke Shih static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 6179ae4dc23dSPing-Ke Shih { 6180ae4dc23dSPing-Ke Shih u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 6181ae4dc23dSPing-Ke Shih 6182ae4dc23dSPing-Ke Shih return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 6183ae4dc23dSPing-Ke Shih } 6184ae4dc23dSPing-Ke Shih 6185ae4dc23dSPing-Ke Shih static 618680e706a8SPing-Ke Shih int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 618780e706a8SPing-Ke Shih bool h2c_or_fwdl) 618880e706a8SPing-Ke Shih { 618980e706a8SPing-Ke Shih u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 619080e706a8SPing-Ke Shih u8 val; 619180e706a8SPing-Ke Shih 619280e706a8SPing-Ke Shih return read_poll_timeout_atomic(rtw89_read8, val, val & check, 619380e706a8SPing-Ke Shih 1, FWDL_WAIT_CNT, false, 619480e706a8SPing-Ke Shih rtwdev, R_AX_WCPU_FW_CTRL); 619580e706a8SPing-Ke Shih } 619680e706a8SPing-Ke Shih 6197c220d08eSPing-Ke Shih const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 6198c220d08eSPing-Ke Shih .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 619960168f6cSPing-Ke Shih .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 620060168f6cSPing-Ke Shih .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 620160168f6cSPing-Ke Shih .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 62029d87e7dcSPing-Ke Shih .rx_fltr = R_AX_RX_FLTR_OPT, 62037c8a55ddSPing-Ke Shih .port_base = &rtw89_port_base_ax, 6204fbd1829dSZong-Zhe Yang .agg_len_ht = R_AX_AGG_LEN_HT_0, 6205f651300cSChin-Yen Lee .ps_status = R_AX_PPWRBIT_SETTING, 6206ae4dc23dSPing-Ke Shih 62077f69cd42SZong-Zhe Yang .muedca_ctrl = { 62087f69cd42SZong-Zhe Yang .addr = R_AX_MUEDCA_EN, 62097f69cd42SZong-Zhe Yang .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 62107f69cd42SZong-Zhe Yang }, 62115fa1c5d4SZong-Zhe Yang .bfee_ctrl = { 62125fa1c5d4SZong-Zhe Yang .addr = R_AX_BFMEE_RESP_OPTION, 62135fa1c5d4SZong-Zhe Yang .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 62145fa1c5d4SZong-Zhe Yang B_AX_BFMEE_HE_NDPA_EN, 62155fa1c5d4SZong-Zhe Yang }, 621649ea9823SZong-Zhe Yang .narrow_bw_ru_dis = { 621749ea9823SZong-Zhe Yang .addr = R_AX_RXTRIG_TEST_USER_2, 621849ea9823SZong-Zhe Yang .mask = B_AX_RXTRIG_RU26_DIS, 621949ea9823SZong-Zhe Yang }, 62207f69cd42SZong-Zhe Yang 6221cfb99433SPing-Ke Shih .check_mac_en = rtw89_mac_check_mac_en_ax, 6222fc663fa0SPing-Ke Shih .sys_init = sys_init_ax, 6223fc663fa0SPing-Ke Shih .trx_init = trx_init_ax, 622439e9b569SPing-Ke Shih .hci_func_en = rtw89_mac_hci_func_en_ax, 622539e9b569SPing-Ke Shih .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 622639e9b569SPing-Ke Shih .dle_func_en = dle_func_en_ax, 622739e9b569SPing-Ke Shih .dle_clk_en = dle_clk_en_ax, 622831b7cd19SZong-Zhe Yang .bf_assoc = rtw89_mac_bf_assoc_ax, 622931b7cd19SZong-Zhe Yang 6230fc663fa0SPing-Ke Shih .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 6231b16daa62SPing-Ke Shih .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 6232fc663fa0SPing-Ke Shih 623339e9b569SPing-Ke Shih .dle_mix_cfg = dle_mix_cfg_ax, 623439e9b569SPing-Ke Shih .chk_dle_rdy = chk_dle_rdy_ax, 623539e9b569SPing-Ke Shih .dle_buf_req = dle_buf_req_ax, 623639e9b569SPing-Ke Shih .hfc_func_en = hfc_func_en_ax, 623739e9b569SPing-Ke Shih .hfc_h2c_cfg = hfc_h2c_cfg_ax, 623839e9b569SPing-Ke Shih .hfc_mix_cfg = hfc_mix_cfg_ax, 623939e9b569SPing-Ke Shih .hfc_get_mix_info = hfc_get_mix_info_ax, 624039e9b569SPing-Ke Shih .wde_quota_cfg = wde_quota_cfg_ax, 624139e9b569SPing-Ke Shih .ple_quota_cfg = ple_quota_cfg_ax, 624239e9b569SPing-Ke Shih .set_cpuio = set_cpuio_ax, 6243b6e65d18SPing-Ke Shih .dle_quota_change = dle_quota_change_ax, 624439e9b569SPing-Ke Shih 6245ae4dc23dSPing-Ke Shih .disable_cpu = rtw89_mac_disable_cpu_ax, 6246ae4dc23dSPing-Ke Shih .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 6247ae4dc23dSPing-Ke Shih .fwdl_get_status = rtw89_fw_get_rdy_ax, 6248ae4dc23dSPing-Ke Shih .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 624988e6a923SPing-Ke Shih .parse_efuse_map = rtw89_parse_efuse_map_ax, 625088e6a923SPing-Ke Shih .parse_phycap_map = rtw89_parse_phycap_map_ax, 625188e6a923SPing-Ke Shih .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 625206b26738SZong-Zhe Yang 625306b26738SZong-Zhe Yang .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 625427ea6be9SZong-Zhe Yang 6255efde4f6dSPing-Ke Shih .write_xtal_si = rtw89_mac_write_xtal_si_ax, 6256efde4f6dSPing-Ke Shih .read_xtal_si = rtw89_mac_read_xtal_si_ax, 6257efde4f6dSPing-Ke Shih 62586f8d3655SChia-Yuan Li .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 62596f8d3655SChia-Yuan Li .dump_err_status = rtw89_mac_dump_err_status_ax, 62606f8d3655SChia-Yuan Li 626127ea6be9SZong-Zhe Yang .is_txq_empty = mac_is_txq_empty_ax, 6262a412920bSPo-Hao Huang 6263a412920bSPo-Hao Huang .add_chan_list = rtw89_hw_scan_add_chan_list, 62644ba24331SPo-Hao Huang .scan_offload = rtw89_fw_h2c_scan_offload, 6265c220d08eSPing-Ke Shih }; 6266c220d08eSPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_gen_ax); 6267