1e3ec7017SPing-Ke Shih // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2e3ec7017SPing-Ke Shih /* Copyright(c) 2019-2020 Realtek Corporation 3e3ec7017SPing-Ke Shih */ 4e3ec7017SPing-Ke Shih 5e3ec7017SPing-Ke Shih #include "cam.h" 6e3ec7017SPing-Ke Shih #include "debug.h" 7e3ec7017SPing-Ke Shih #include "fw.h" 8e3ec7017SPing-Ke Shih #include "mac.h" 9e3ec7017SPing-Ke Shih #include "ps.h" 10e3ec7017SPing-Ke Shih #include "reg.h" 11e3ec7017SPing-Ke Shih #include "util.h" 12e3ec7017SPing-Ke Shih 13e3ec7017SPing-Ke Shih int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 14e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 15e3ec7017SPing-Ke Shih { 16e3ec7017SPing-Ke Shih u32 val, r_val; 17e3ec7017SPing-Ke Shih 18e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 19e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 20e3ec7017SPing-Ke Shih val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 21e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 22e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 23e3ec7017SPing-Ke Shih val = B_AX_CMAC_EN; 24e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 25e3ec7017SPing-Ke Shih r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 26e3ec7017SPing-Ke Shih val = B_AX_CMAC1_FEN; 27e3ec7017SPing-Ke Shih } else { 28e3ec7017SPing-Ke Shih return -EINVAL; 29e3ec7017SPing-Ke Shih } 30e3ec7017SPing-Ke Shih if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 31e3ec7017SPing-Ke Shih (val & r_val) != val) 32e3ec7017SPing-Ke Shih return -EFAULT; 33e3ec7017SPing-Ke Shih 34e3ec7017SPing-Ke Shih return 0; 35e3ec7017SPing-Ke Shih } 36e3ec7017SPing-Ke Shih 37e3ec7017SPing-Ke Shih int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 38e3ec7017SPing-Ke Shih { 39e3ec7017SPing-Ke Shih u8 lte_ctrl; 40e3ec7017SPing-Ke Shih int ret; 41e3ec7017SPing-Ke Shih 42e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 43e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 44e3ec7017SPing-Ke Shih if (ret) 45e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 46e3ec7017SPing-Ke Shih 47e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 48e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 49e3ec7017SPing-Ke Shih 50e3ec7017SPing-Ke Shih return ret; 51e3ec7017SPing-Ke Shih } 52e3ec7017SPing-Ke Shih 53e3ec7017SPing-Ke Shih int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 54e3ec7017SPing-Ke Shih { 55e3ec7017SPing-Ke Shih u8 lte_ctrl; 56e3ec7017SPing-Ke Shih int ret; 57e3ec7017SPing-Ke Shih 58e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 59e3ec7017SPing-Ke Shih 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 60e3ec7017SPing-Ke Shih if (ret) 61e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 62e3ec7017SPing-Ke Shih 63e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 64e3ec7017SPing-Ke Shih *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 65e3ec7017SPing-Ke Shih 66e3ec7017SPing-Ke Shih return ret; 67e3ec7017SPing-Ke Shih } 68e3ec7017SPing-Ke Shih 69e3ec7017SPing-Ke Shih static 70e3ec7017SPing-Ke Shih int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 71e3ec7017SPing-Ke Shih { 72e3ec7017SPing-Ke Shih u32 ctrl_reg, data_reg, ctrl_data; 73e3ec7017SPing-Ke Shih u32 val; 74e3ec7017SPing-Ke Shih int ret; 75e3ec7017SPing-Ke Shih 76e3ec7017SPing-Ke Shih switch (ctrl->type) { 77e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_WDE: 78e3ec7017SPing-Ke Shih ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 79e3ec7017SPing-Ke Shih data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 80e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 81e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 82e3ec7017SPing-Ke Shih B_AX_WDE_DFI_ACTIVE; 83e3ec7017SPing-Ke Shih break; 84e3ec7017SPing-Ke Shih case DLE_CTRL_TYPE_PLE: 85e3ec7017SPing-Ke Shih ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 86e3ec7017SPing-Ke Shih data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 87e3ec7017SPing-Ke Shih ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 88e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 89e3ec7017SPing-Ke Shih B_AX_PLE_DFI_ACTIVE; 90e3ec7017SPing-Ke Shih break; 91e3ec7017SPing-Ke Shih default: 92e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 93e3ec7017SPing-Ke Shih return -EINVAL; 94e3ec7017SPing-Ke Shih } 95e3ec7017SPing-Ke Shih 96e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 97e3ec7017SPing-Ke Shih 98e3ec7017SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 99e3ec7017SPing-Ke Shih 1, 1000, false, rtwdev, ctrl_reg); 100e3ec7017SPing-Ke Shih if (ret) { 101e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 102e3ec7017SPing-Ke Shih ctrl_reg, ctrl_data); 103e3ec7017SPing-Ke Shih return ret; 104e3ec7017SPing-Ke Shih } 105e3ec7017SPing-Ke Shih 106e3ec7017SPing-Ke Shih ctrl->out_data = rtw89_read32(rtwdev, data_reg); 107e3ec7017SPing-Ke Shih return 0; 108e3ec7017SPing-Ke Shih } 109e3ec7017SPing-Ke Shih 110e3ec7017SPing-Ke Shih static int dle_dfi_quota(struct rtw89_dev *rtwdev, 111e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota *quota) 112e3ec7017SPing-Ke Shih { 113e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 114e3ec7017SPing-Ke Shih int ret; 115e3ec7017SPing-Ke Shih 116e3ec7017SPing-Ke Shih ctrl.type = quota->dle_type; 117e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QUOTA; 118e3ec7017SPing-Ke Shih ctrl.addr = quota->qtaid; 119e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 120e3ec7017SPing-Ke Shih if (ret) { 121e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 122e3ec7017SPing-Ke Shih return ret; 123e3ec7017SPing-Ke Shih } 124e3ec7017SPing-Ke Shih 125e3ec7017SPing-Ke Shih quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 126e3ec7017SPing-Ke Shih quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 127e3ec7017SPing-Ke Shih return 0; 128e3ec7017SPing-Ke Shih } 129e3ec7017SPing-Ke Shih 130e3ec7017SPing-Ke Shih static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 131e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty *qempty) 132e3ec7017SPing-Ke Shih { 133e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 134e3ec7017SPing-Ke Shih u32 ret; 135e3ec7017SPing-Ke Shih 136e3ec7017SPing-Ke Shih ctrl.type = qempty->dle_type; 137e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QEMPTY; 138e3ec7017SPing-Ke Shih ctrl.addr = qempty->grpsel; 139e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 140e3ec7017SPing-Ke Shih if (ret) { 141e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 142e3ec7017SPing-Ke Shih return ret; 143e3ec7017SPing-Ke Shih } 144e3ec7017SPing-Ke Shih 145e3ec7017SPing-Ke Shih qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 146e3ec7017SPing-Ke Shih return 0; 147e3ec7017SPing-Ke Shih } 148e3ec7017SPing-Ke Shih 149e3ec7017SPing-Ke Shih static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 150e3ec7017SPing-Ke Shih { 151e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 152e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 153e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 154e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 155e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 156e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 157e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 158e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 159e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 160e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 161e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 162e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 163e3ec7017SPing-Ke Shih } 164e3ec7017SPing-Ke Shih 165e3ec7017SPing-Ke Shih static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 166e3ec7017SPing-Ke Shih { 167e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_qempty qempty; 168e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_quota quota; 169e3ec7017SPing-Ke Shih struct rtw89_mac_dle_dfi_ctrl ctrl; 170e3ec7017SPing-Ke Shih u32 val, not_empty, i; 171e3ec7017SPing-Ke Shih int ret; 172e3ec7017SPing-Ke Shih 173e3ec7017SPing-Ke Shih qempty.dle_type = DLE_CTRL_TYPE_PLE; 174e3ec7017SPing-Ke Shih qempty.grpsel = 0; 175e3ec7017SPing-Ke Shih ret = dle_dfi_qempty(rtwdev, &qempty); 176e3ec7017SPing-Ke Shih if (ret) 177e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 178e3ec7017SPing-Ke Shih else 179e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 180e3ec7017SPing-Ke Shih 181e3ec7017SPing-Ke Shih for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 182e3ec7017SPing-Ke Shih if (!(not_empty & BIT(0))) 183e3ec7017SPing-Ke Shih continue; 184e3ec7017SPing-Ke Shih ctrl.type = DLE_CTRL_TYPE_PLE; 185e3ec7017SPing-Ke Shih ctrl.target = DLE_DFI_TYPE_QLNKTBL; 186e3ec7017SPing-Ke Shih ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 187e3ec7017SPing-Ke Shih FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 188e3ec7017SPing-Ke Shih ret = dle_dfi_ctrl(rtwdev, &ctrl); 189e3ec7017SPing-Ke Shih if (ret) 190e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 191e3ec7017SPing-Ke Shih else 192e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 193e3ec7017SPing-Ke Shih FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 194e3ec7017SPing-Ke Shih ctrl.out_data)); 195e3ec7017SPing-Ke Shih } 196e3ec7017SPing-Ke Shih 197e3ec7017SPing-Ke Shih quota.dle_type = DLE_CTRL_TYPE_PLE; 198e3ec7017SPing-Ke Shih quota.qtaid = 6; 199e3ec7017SPing-Ke Shih ret = dle_dfi_quota(rtwdev, "a); 200e3ec7017SPing-Ke Shih if (ret) 201e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 202e3ec7017SPing-Ke Shih else 203e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 204e3ec7017SPing-Ke Shih quota.rsv_pgnum, quota.use_pgnum); 205e3ec7017SPing-Ke Shih 206e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 207e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 208e3ec7017SPing-Ke Shih FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 209e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 210e3ec7017SPing-Ke Shih FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 211e3ec7017SPing-Ke Shih 212e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 213e3ec7017SPing-Ke Shih } 214e3ec7017SPing-Ke Shih 215e3ec7017SPing-Ke Shih static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 216e3ec7017SPing-Ke Shih enum mac_ax_err_info err) 217e3ec7017SPing-Ke Shih { 218e3ec7017SPing-Ke Shih u32 dbg, event; 219e3ec7017SPing-Ke Shih 220e3ec7017SPing-Ke Shih dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 221e3ec7017SPing-Ke Shih event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 222e3ec7017SPing-Ke Shih 223e3ec7017SPing-Ke Shih switch (event) { 224e3ec7017SPing-Ke Shih case MAC_AX_L0_TO_L1_RX_QTA_LOST: 225e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "quota lost!\n"); 226e3ec7017SPing-Ke Shih rtw89_mac_dump_qta_lost(rtwdev); 227e3ec7017SPing-Ke Shih break; 228e3ec7017SPing-Ke Shih default: 229e3ec7017SPing-Ke Shih break; 230e3ec7017SPing-Ke Shih } 231e3ec7017SPing-Ke Shih } 232e3ec7017SPing-Ke Shih 233e3ec7017SPing-Ke Shih static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 234e3ec7017SPing-Ke Shih enum mac_ax_err_info err) 235e3ec7017SPing-Ke Shih { 236e3ec7017SPing-Ke Shih u32 dmac_err, cmac_err; 237e3ec7017SPing-Ke Shih 238e3ec7017SPing-Ke Shih if (err != MAC_AX_ERR_L1_ERR_DMAC && 239e3ec7017SPing-Ke Shih err != MAC_AX_ERR_L0_PROMOTE_TO_L1) 240e3ec7017SPing-Ke Shih return; 241e3ec7017SPing-Ke Shih 242e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 243e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 244e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 245e3ec7017SPing-Ke Shih 246e3ec7017SPing-Ke Shih cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR); 247e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err); 248e3ec7017SPing-Ke Shih dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 249e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err); 250e3ec7017SPing-Ke Shih 251e3ec7017SPing-Ke Shih if (dmac_err) { 252e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ", 253e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG)); 254e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n", 255e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG)); 256e3ec7017SPing-Ke Shih } 257e3ec7017SPing-Ke Shih 258e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 259e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ", 260e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 261e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n", 262e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 263e3ec7017SPing-Ke Shih } 264e3ec7017SPing-Ke Shih 265e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WSEC_ERR_FLAG) { 266e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n", 267e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 268e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n", 269e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 270e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n", 271e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 272e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n", 273e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 274e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n", 275e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 276e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n", 277e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 278e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n", 279e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 280e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n", 281e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 282e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n", 283e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 284e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n", 285e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 286e3ec7017SPing-Ke Shih } 287e3ec7017SPing-Ke Shih 288e3ec7017SPing-Ke Shih if (dmac_err & B_AX_MPDU_ERR_FLAG) { 289e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ", 290e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 291e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n", 292e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 293e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ", 294e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 295e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n", 296e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 297e3ec7017SPing-Ke Shih } 298e3ec7017SPing-Ke Shih 299e3ec7017SPing-Ke Shih if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 300e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ", 301e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 302e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n", 303e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 304e3ec7017SPing-Ke Shih } 305e3ec7017SPing-Ke Shih 306e3ec7017SPing-Ke Shih if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 307e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", 308e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 309e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 310e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 311e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", 312e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 313e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 314e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 315e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 316e3ec7017SPing-Ke Shih } 317e3ec7017SPing-Ke Shih 318e3ec7017SPing-Ke Shih if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 319e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 320e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 321e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 322e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 323e3ec7017SPing-Ke Shih } 324e3ec7017SPing-Ke Shih 325e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 326e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", 327e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 328e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 329e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 330e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", 331e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 332e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 333e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 334e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 335e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 336e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 337e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 338e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 339e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 340e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 341e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 342e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 343e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 344e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 345e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 346e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 347e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 348e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 349e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 350e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 351e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 352e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 353e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 354e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 355e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 356e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 357e3ec7017SPing-Ke Shih } 358e3ec7017SPing-Ke Shih 359e3ec7017SPing-Ke Shih if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 360e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", 361e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 362e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", 363e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 364e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", 365e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 366e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", 367e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 368e3ec7017SPing-Ke Shih } 369e3ec7017SPing-Ke Shih 370e3ec7017SPing-Ke Shih if (dmac_err & B_AX_DISPATCH_ERR_FLAG) 371e3ec7017SPing-Ke Shih dump_err_status_dispatcher(rtwdev); 372e3ec7017SPing-Ke Shih 373e3ec7017SPing-Ke Shih if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) { 374e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ", 375e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR)); 376e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n", 377e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); 378e3ec7017SPing-Ke Shih } 379e3ec7017SPing-Ke Shih 380e3ec7017SPing-Ke Shih if (dmac_err & BIT(11)) { 381e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 382e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 383e3ec7017SPing-Ke Shih } 384e3ec7017SPing-Ke Shih 385e3ec7017SPing-Ke Shih if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 386e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ", 387e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR)); 388e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n", 389e3ec7017SPing-Ke Shih rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR)); 390e3ec7017SPing-Ke Shih } 391e3ec7017SPing-Ke Shih 392e3ec7017SPing-Ke Shih if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 393e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ", 394e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PTCL_IMR0)); 395e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n", 396e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); 397e3ec7017SPing-Ke Shih } 398e3ec7017SPing-Ke Shih 399e3ec7017SPing-Ke Shih if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 400e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n", 401e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_DLE_CTRL)); 402e3ec7017SPing-Ke Shih } 403e3ec7017SPing-Ke Shih 404e3ec7017SPing-Ke Shih if (cmac_err & B_AX_PHYINTF_ERR_IND) { 405e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n", 406e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR)); 407e3ec7017SPing-Ke Shih } 408e3ec7017SPing-Ke Shih 409e3ec7017SPing-Ke Shih if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 410e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ", 411e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPWR_IMR)); 412e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n", 413e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); 414e3ec7017SPing-Ke Shih } 415e3ec7017SPing-Ke Shih 416e3ec7017SPing-Ke Shih if (cmac_err & B_AX_WMAC_RX_ERR_IND) { 417e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ", 418e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); 419e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n", 420e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); 421e3ec7017SPing-Ke Shih } 422e3ec7017SPing-Ke Shih 423e3ec7017SPing-Ke Shih if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 424e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ", 425e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); 426e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n", 427e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); 428e3ec7017SPing-Ke Shih } 429e3ec7017SPing-Ke Shih 430e3ec7017SPing-Ke Shih rtwdev->hci.ops->dump_err_status(rtwdev); 431e3ec7017SPing-Ke Shih 432e3ec7017SPing-Ke Shih if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 433e3ec7017SPing-Ke Shih rtw89_mac_dump_l0_to_l1(rtwdev, err); 434e3ec7017SPing-Ke Shih 435e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "<---\n"); 436e3ec7017SPing-Ke Shih } 437e3ec7017SPing-Ke Shih 438e3ec7017SPing-Ke Shih u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 439e3ec7017SPing-Ke Shih { 440e3ec7017SPing-Ke Shih u32 err; 441e3ec7017SPing-Ke Shih int ret; 442e3ec7017SPing-Ke Shih 443e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 444e3ec7017SPing-Ke Shih false, rtwdev, R_AX_HALT_C2H_CTRL); 445e3ec7017SPing-Ke Shih if (ret) { 446e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "Polling FW err status fail\n"); 447e3ec7017SPing-Ke Shih return ret; 448e3ec7017SPing-Ke Shih } 449e3ec7017SPing-Ke Shih 450e3ec7017SPing-Ke Shih err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 451e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 452e3ec7017SPing-Ke Shih 453e3ec7017SPing-Ke Shih rtw89_fw_st_dbg_dump(rtwdev); 454e3ec7017SPing-Ke Shih rtw89_mac_dump_err_status(rtwdev, err); 455e3ec7017SPing-Ke Shih 456e3ec7017SPing-Ke Shih return err; 457e3ec7017SPing-Ke Shih } 458e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_get_err_status); 459e3ec7017SPing-Ke Shih 460e3ec7017SPing-Ke Shih int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 461e3ec7017SPing-Ke Shih { 462e3ec7017SPing-Ke Shih u32 halt; 463e3ec7017SPing-Ke Shih int ret = 0; 464e3ec7017SPing-Ke Shih 465e3ec7017SPing-Ke Shih if (err > MAC_AX_SET_ERR_MAX) { 466e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 467e3ec7017SPing-Ke Shih return -EINVAL; 468e3ec7017SPing-Ke Shih } 469e3ec7017SPing-Ke Shih 470e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 471e3ec7017SPing-Ke Shih 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 472e3ec7017SPing-Ke Shih if (ret) { 473e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 474e3ec7017SPing-Ke Shih return -EFAULT; 475e3ec7017SPing-Ke Shih } 476e3ec7017SPing-Ke Shih 477e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 478e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 479e3ec7017SPing-Ke Shih 480e3ec7017SPing-Ke Shih return 0; 481e3ec7017SPing-Ke Shih } 482e3ec7017SPing-Ke Shih EXPORT_SYMBOL(rtw89_mac_set_err_status); 483e3ec7017SPing-Ke Shih 484e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg rtw_hfc_preccfg_pcie = { 485e3ec7017SPing-Ke Shih 2, 40, 0, 0, 1, 0, 0, 0 486e3ec7017SPing-Ke Shih }; 487e3ec7017SPing-Ke Shih 488e3ec7017SPing-Ke Shih static int hfc_reset_param(struct rtw89_dev *rtwdev) 489e3ec7017SPing-Ke Shih { 490e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 491e3ec7017SPing-Ke Shih struct rtw89_hfc_param_ini param_ini = {NULL}; 492e3ec7017SPing-Ke Shih u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 493e3ec7017SPing-Ke Shih 494e3ec7017SPing-Ke Shih switch (rtwdev->hci.type) { 495e3ec7017SPing-Ke Shih case RTW89_HCI_TYPE_PCIE: 496e3ec7017SPing-Ke Shih param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 497e3ec7017SPing-Ke Shih param->en = 0; 498e3ec7017SPing-Ke Shih break; 499e3ec7017SPing-Ke Shih default: 500e3ec7017SPing-Ke Shih return -EINVAL; 501e3ec7017SPing-Ke Shih } 502e3ec7017SPing-Ke Shih 503e3ec7017SPing-Ke Shih if (param_ini.pub_cfg) 504e3ec7017SPing-Ke Shih param->pub_cfg = *param_ini.pub_cfg; 505e3ec7017SPing-Ke Shih 506e3ec7017SPing-Ke Shih if (param_ini.prec_cfg) { 507e3ec7017SPing-Ke Shih param->prec_cfg = *param_ini.prec_cfg; 508e3ec7017SPing-Ke Shih rtwdev->hal.sw_amsdu_max_size = 509e3ec7017SPing-Ke Shih param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; 510e3ec7017SPing-Ke Shih } 511e3ec7017SPing-Ke Shih 512e3ec7017SPing-Ke Shih if (param_ini.ch_cfg) 513e3ec7017SPing-Ke Shih param->ch_cfg = param_ini.ch_cfg; 514e3ec7017SPing-Ke Shih 515e3ec7017SPing-Ke Shih memset(¶m->ch_info, 0, sizeof(param->ch_info)); 516e3ec7017SPing-Ke Shih memset(¶m->pub_info, 0, sizeof(param->pub_info)); 517e3ec7017SPing-Ke Shih param->mode = param_ini.mode; 518e3ec7017SPing-Ke Shih 519e3ec7017SPing-Ke Shih return 0; 520e3ec7017SPing-Ke Shih } 521e3ec7017SPing-Ke Shih 522e3ec7017SPing-Ke Shih static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 523e3ec7017SPing-Ke Shih { 524e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 525e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 526e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 527e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 528e3ec7017SPing-Ke Shih 529e3ec7017SPing-Ke Shih if (ch >= RTW89_DMA_CH_NUM) 530e3ec7017SPing-Ke Shih return -EINVAL; 531e3ec7017SPing-Ke Shih 532e3ec7017SPing-Ke Shih if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 533e3ec7017SPing-Ke Shih ch_cfg[ch].max > pub_cfg->pub_max) 534e3ec7017SPing-Ke Shih return -EINVAL; 535e3ec7017SPing-Ke Shih if (ch_cfg[ch].grp >= grp_num) 536e3ec7017SPing-Ke Shih return -EINVAL; 537e3ec7017SPing-Ke Shih 538e3ec7017SPing-Ke Shih return 0; 539e3ec7017SPing-Ke Shih } 540e3ec7017SPing-Ke Shih 541e3ec7017SPing-Ke Shih static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 542e3ec7017SPing-Ke Shih { 543e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 544e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 545e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 546e3ec7017SPing-Ke Shih 547e3ec7017SPing-Ke Shih if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 548e3ec7017SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852A) 549e3ec7017SPing-Ke Shih return 0; 550e3ec7017SPing-Ke Shih else 551e3ec7017SPing-Ke Shih return -EFAULT; 552e3ec7017SPing-Ke Shih } 553e3ec7017SPing-Ke Shih 554e3ec7017SPing-Ke Shih return 0; 555e3ec7017SPing-Ke Shih } 556e3ec7017SPing-Ke Shih 557e3ec7017SPing-Ke Shih static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 558e3ec7017SPing-Ke Shih { 559e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 560e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 561e3ec7017SPing-Ke Shih 562e3ec7017SPing-Ke Shih if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 563c6477cb2SKevin Lo return -EFAULT; 564e3ec7017SPing-Ke Shih 565e3ec7017SPing-Ke Shih return 0; 566e3ec7017SPing-Ke Shih } 567e3ec7017SPing-Ke Shih 568e3ec7017SPing-Ke Shih static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 569e3ec7017SPing-Ke Shih { 570e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 571e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 572e3ec7017SPing-Ke Shih int ret = 0; 573e3ec7017SPing-Ke Shih u32 val = 0; 574e3ec7017SPing-Ke Shih 575e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 576e3ec7017SPing-Ke Shih if (ret) 577e3ec7017SPing-Ke Shih return ret; 578e3ec7017SPing-Ke Shih 579e3ec7017SPing-Ke Shih ret = hfc_ch_cfg_chk(rtwdev, ch); 580e3ec7017SPing-Ke Shih if (ret) 581e3ec7017SPing-Ke Shih return ret; 582e3ec7017SPing-Ke Shih 583e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_B1HI) 584e3ec7017SPing-Ke Shih return -EINVAL; 585e3ec7017SPing-Ke Shih 586e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 587e3ec7017SPing-Ke Shih u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 588e3ec7017SPing-Ke Shih (cfg[ch].grp ? B_AX_GRP : 0); 589e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_ACH0_PAGE_CTRL + ch * 4, val); 590e3ec7017SPing-Ke Shih 591e3ec7017SPing-Ke Shih return 0; 592e3ec7017SPing-Ke Shih } 593e3ec7017SPing-Ke Shih 594e3ec7017SPing-Ke Shih static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 595e3ec7017SPing-Ke Shih { 596e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 597e3ec7017SPing-Ke Shih struct rtw89_hfc_ch_info *info = param->ch_info; 598e3ec7017SPing-Ke Shih const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 599e3ec7017SPing-Ke Shih u32 val; 600e3ec7017SPing-Ke Shih u32 ret; 601e3ec7017SPing-Ke Shih 602e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 603e3ec7017SPing-Ke Shih if (ret) 604e3ec7017SPing-Ke Shih return ret; 605e3ec7017SPing-Ke Shih 606e3ec7017SPing-Ke Shih if (ch > RTW89_DMA_H2C) 607e3ec7017SPing-Ke Shih return -EINVAL; 608e3ec7017SPing-Ke Shih 609e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_ACH0_PAGE_INFO + ch * 4); 610e3ec7017SPing-Ke Shih info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 611e3ec7017SPing-Ke Shih if (ch < RTW89_DMA_H2C) 612e3ec7017SPing-Ke Shih info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 613e3ec7017SPing-Ke Shih else 614e3ec7017SPing-Ke Shih info[ch].used = cfg[ch].min - info[ch].aval; 615e3ec7017SPing-Ke Shih 616e3ec7017SPing-Ke Shih return 0; 617e3ec7017SPing-Ke Shih } 618e3ec7017SPing-Ke Shih 619e3ec7017SPing-Ke Shih static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 620e3ec7017SPing-Ke Shih { 621e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 622e3ec7017SPing-Ke Shih u32 val; 623e3ec7017SPing-Ke Shih int ret; 624e3ec7017SPing-Ke Shih 625e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 626e3ec7017SPing-Ke Shih if (ret) 627e3ec7017SPing-Ke Shih return ret; 628e3ec7017SPing-Ke Shih 629e3ec7017SPing-Ke Shih ret = hfc_pub_cfg_chk(rtwdev); 630e3ec7017SPing-Ke Shih if (ret) 631e3ec7017SPing-Ke Shih return ret; 632e3ec7017SPing-Ke Shih 633e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 634e3ec7017SPing-Ke Shih u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 635e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_PUB_PAGE_CTRL1, val); 636e3ec7017SPing-Ke Shih 637e3ec7017SPing-Ke Shih val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 638e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WP_PAGE_CTRL2, val); 639e3ec7017SPing-Ke Shih 640e3ec7017SPing-Ke Shih return 0; 641e3ec7017SPing-Ke Shih } 642e3ec7017SPing-Ke Shih 643e3ec7017SPing-Ke Shih static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 644e3ec7017SPing-Ke Shih { 645e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 646e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 647e3ec7017SPing-Ke Shih struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 648e3ec7017SPing-Ke Shih struct rtw89_hfc_pub_info *info = ¶m->pub_info; 649e3ec7017SPing-Ke Shih u32 val; 650e3ec7017SPing-Ke Shih int ret; 651e3ec7017SPing-Ke Shih 652e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 653e3ec7017SPing-Ke Shih if (ret) 654e3ec7017SPing-Ke Shih return ret; 655e3ec7017SPing-Ke Shih 656e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PUB_PAGE_INFO1); 657e3ec7017SPing-Ke Shih info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 658e3ec7017SPing-Ke Shih info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 659e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PUB_PAGE_INFO3); 660e3ec7017SPing-Ke Shih info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 661e3ec7017SPing-Ke Shih info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 662e3ec7017SPing-Ke Shih info->pub_aval = 663e3ec7017SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, R_AX_PUB_PAGE_INFO2), 664e3ec7017SPing-Ke Shih B_AX_PUB_AVAL_PG_MASK); 665e3ec7017SPing-Ke Shih info->wp_aval = 666e3ec7017SPing-Ke Shih u32_get_bits(rtw89_read32(rtwdev, R_AX_WP_PAGE_INFO1), 667e3ec7017SPing-Ke Shih B_AX_WP_AVAL_PG_MASK); 668e3ec7017SPing-Ke Shih 669e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_HCI_FC_CTRL); 670e3ec7017SPing-Ke Shih param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 671e3ec7017SPing-Ke Shih param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 672e3ec7017SPing-Ke Shih param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 673e3ec7017SPing-Ke Shih prec_cfg->ch011_full_cond = 674e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 675e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond = 676e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 677e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_full_cond = 678e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 679e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_full_cond = 680e3ec7017SPing-Ke Shih u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 681e3ec7017SPing-Ke Shih 682e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_CH_PAGE_CTRL); 683e3ec7017SPing-Ke Shih prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 684e3ec7017SPing-Ke Shih prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 685e3ec7017SPing-Ke Shih 686e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PUB_PAGE_CTRL2); 687e3ec7017SPing-Ke Shih pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 688e3ec7017SPing-Ke Shih 689e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WP_PAGE_CTRL1); 690e3ec7017SPing-Ke Shih prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 691e3ec7017SPing-Ke Shih prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 692e3ec7017SPing-Ke Shih 693e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WP_PAGE_CTRL2); 694e3ec7017SPing-Ke Shih pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 695e3ec7017SPing-Ke Shih 696e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PUB_PAGE_CTRL1); 697e3ec7017SPing-Ke Shih pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 698e3ec7017SPing-Ke Shih pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 699e3ec7017SPing-Ke Shih 700e3ec7017SPing-Ke Shih ret = hfc_pub_info_chk(rtwdev); 701e3ec7017SPing-Ke Shih if (param->en && ret) 702e3ec7017SPing-Ke Shih return ret; 703e3ec7017SPing-Ke Shih 704e3ec7017SPing-Ke Shih return 0; 705e3ec7017SPing-Ke Shih } 706e3ec7017SPing-Ke Shih 707e3ec7017SPing-Ke Shih static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 708e3ec7017SPing-Ke Shih { 709e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 710e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 711e3ec7017SPing-Ke Shih u32 val; 712e3ec7017SPing-Ke Shih 713e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 714e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CH_PAGE_CTRL, val); 715e3ec7017SPing-Ke Shih 716e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_HCI_FC_CTRL, 717e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK, 718e3ec7017SPing-Ke Shih prec_cfg->h2c_full_cond); 719e3ec7017SPing-Ke Shih } 720e3ec7017SPing-Ke Shih 721e3ec7017SPing-Ke Shih static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 722e3ec7017SPing-Ke Shih { 723e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 724e3ec7017SPing-Ke Shih const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 725e3ec7017SPing-Ke Shih const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 726e3ec7017SPing-Ke Shih u32 val; 727e3ec7017SPing-Ke Shih 728e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 729e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 730e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CH_PAGE_CTRL, val); 731e3ec7017SPing-Ke Shih 732e3ec7017SPing-Ke Shih val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 733e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_PUB_PAGE_CTRL2, val); 734e3ec7017SPing-Ke Shih 735e3ec7017SPing-Ke Shih val = u32_encode_bits(prec_cfg->wp_ch07_prec, 736e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH07_MASK) | 737e3ec7017SPing-Ke Shih u32_encode_bits(prec_cfg->wp_ch811_prec, 738e3ec7017SPing-Ke Shih B_AX_PREC_PAGE_WP_CH811_MASK); 739e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WP_PAGE_CTRL1, val); 740e3ec7017SPing-Ke Shih 741e3ec7017SPing-Ke Shih val = u32_replace_bits(rtw89_read32(rtwdev, R_AX_HCI_FC_CTRL), 742e3ec7017SPing-Ke Shih param->mode, B_AX_HCI_FC_MODE_MASK); 743e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 744e3ec7017SPing-Ke Shih B_AX_HCI_FC_WD_FULL_COND_MASK); 745e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 746e3ec7017SPing-Ke Shih B_AX_HCI_FC_CH12_FULL_COND_MASK); 747e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 748e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 749e3ec7017SPing-Ke Shih val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 750e3ec7017SPing-Ke Shih B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 751e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HCI_FC_CTRL, val); 752e3ec7017SPing-Ke Shih } 753e3ec7017SPing-Ke Shih 754e3ec7017SPing-Ke Shih static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 755e3ec7017SPing-Ke Shih { 756e3ec7017SPing-Ke Shih struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 757e3ec7017SPing-Ke Shih u32 val; 758e3ec7017SPing-Ke Shih 759e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_HCI_FC_CTRL); 760e3ec7017SPing-Ke Shih param->en = en; 761e3ec7017SPing-Ke Shih param->h2c_en = h2c_en; 762e3ec7017SPing-Ke Shih val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 763e3ec7017SPing-Ke Shih val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 764e3ec7017SPing-Ke Shih (val & ~B_AX_HCI_FC_CH12_EN); 765e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HCI_FC_CTRL, val); 766e3ec7017SPing-Ke Shih } 767e3ec7017SPing-Ke Shih 768e3ec7017SPing-Ke Shih static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 769e3ec7017SPing-Ke Shih { 770e3ec7017SPing-Ke Shih u8 ch; 771e3ec7017SPing-Ke Shih u32 ret = 0; 772e3ec7017SPing-Ke Shih 773e3ec7017SPing-Ke Shih if (reset) 774e3ec7017SPing-Ke Shih ret = hfc_reset_param(rtwdev); 775e3ec7017SPing-Ke Shih if (ret) 776e3ec7017SPing-Ke Shih return ret; 777e3ec7017SPing-Ke Shih 778e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 779e3ec7017SPing-Ke Shih if (ret) 780e3ec7017SPing-Ke Shih return ret; 781e3ec7017SPing-Ke Shih 782e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, false, false); 783e3ec7017SPing-Ke Shih 784e3ec7017SPing-Ke Shih if (!en && h2c_en) { 785e3ec7017SPing-Ke Shih hfc_h2c_cfg(rtwdev); 786e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, en, h2c_en); 787e3ec7017SPing-Ke Shih return ret; 788e3ec7017SPing-Ke Shih } 789e3ec7017SPing-Ke Shih 790e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 791e3ec7017SPing-Ke Shih ret = hfc_ch_ctrl(rtwdev, ch); 792e3ec7017SPing-Ke Shih if (ret) 793e3ec7017SPing-Ke Shih return ret; 794e3ec7017SPing-Ke Shih } 795e3ec7017SPing-Ke Shih 796e3ec7017SPing-Ke Shih ret = hfc_pub_ctrl(rtwdev); 797e3ec7017SPing-Ke Shih if (ret) 798e3ec7017SPing-Ke Shih return ret; 799e3ec7017SPing-Ke Shih 800e3ec7017SPing-Ke Shih hfc_mix_cfg(rtwdev); 801e3ec7017SPing-Ke Shih if (en || h2c_en) { 802e3ec7017SPing-Ke Shih hfc_func_en(rtwdev, en, h2c_en); 803e3ec7017SPing-Ke Shih udelay(10); 804e3ec7017SPing-Ke Shih } 805e3ec7017SPing-Ke Shih for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 806e3ec7017SPing-Ke Shih ret = hfc_upd_ch_info(rtwdev, ch); 807e3ec7017SPing-Ke Shih if (ret) 808e3ec7017SPing-Ke Shih return ret; 809e3ec7017SPing-Ke Shih } 810e3ec7017SPing-Ke Shih ret = hfc_upd_mix_info(rtwdev); 811e3ec7017SPing-Ke Shih 812e3ec7017SPing-Ke Shih return ret; 813e3ec7017SPing-Ke Shih } 814e3ec7017SPing-Ke Shih 815e3ec7017SPing-Ke Shih #define PWR_POLL_CNT 2000 816e3ec7017SPing-Ke Shih static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 817e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cfg) 818e3ec7017SPing-Ke Shih { 819e3ec7017SPing-Ke Shih u8 val = 0; 820e3ec7017SPing-Ke Shih int ret; 821e3ec7017SPing-Ke Shih u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 822e3ec7017SPing-Ke Shih cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 823e3ec7017SPing-Ke Shih 824e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 825e3ec7017SPing-Ke Shih 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 826e3ec7017SPing-Ke Shih 827e3ec7017SPing-Ke Shih if (!ret) 828e3ec7017SPing-Ke Shih return 0; 829e3ec7017SPing-Ke Shih 830e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 831e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 832e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 833e3ec7017SPing-Ke Shih 834e3ec7017SPing-Ke Shih return -EBUSY; 835e3ec7017SPing-Ke Shih } 836e3ec7017SPing-Ke Shih 837e3ec7017SPing-Ke Shih static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 838e3ec7017SPing-Ke Shih u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 839e3ec7017SPing-Ke Shih { 840e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg *cur_cfg; 841e3ec7017SPing-Ke Shih u32 addr; 842e3ec7017SPing-Ke Shih u8 val; 843e3ec7017SPing-Ke Shih 844e3ec7017SPing-Ke Shih for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 845e3ec7017SPing-Ke Shih if (!(cur_cfg->intf_msk & intf_msk) || 846e3ec7017SPing-Ke Shih !(cur_cfg->cv_msk & cv_msk)) 847e3ec7017SPing-Ke Shih continue; 848e3ec7017SPing-Ke Shih 849e3ec7017SPing-Ke Shih switch (cur_cfg->cmd) { 850e3ec7017SPing-Ke Shih case PWR_CMD_WRITE: 851e3ec7017SPing-Ke Shih addr = cur_cfg->addr; 852e3ec7017SPing-Ke Shih 853e3ec7017SPing-Ke Shih if (cur_cfg->base == PWR_BASE_SDIO) 854e3ec7017SPing-Ke Shih addr |= SDIO_LOCAL_BASE_ADDR; 855e3ec7017SPing-Ke Shih 856e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, addr); 857e3ec7017SPing-Ke Shih val &= ~(cur_cfg->msk); 858e3ec7017SPing-Ke Shih val |= (cur_cfg->val & cur_cfg->msk); 859e3ec7017SPing-Ke Shih 860e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, addr, val); 861e3ec7017SPing-Ke Shih break; 862e3ec7017SPing-Ke Shih case PWR_CMD_POLL: 863e3ec7017SPing-Ke Shih if (pwr_cmd_poll(rtwdev, cur_cfg)) 864e3ec7017SPing-Ke Shih return -EBUSY; 865e3ec7017SPing-Ke Shih break; 866e3ec7017SPing-Ke Shih case PWR_CMD_DELAY: 867e3ec7017SPing-Ke Shih if (cur_cfg->val == PWR_DELAY_US) 868e3ec7017SPing-Ke Shih udelay(cur_cfg->addr); 869e3ec7017SPing-Ke Shih else 870e3ec7017SPing-Ke Shih fsleep(cur_cfg->addr * 1000); 871e3ec7017SPing-Ke Shih break; 872e3ec7017SPing-Ke Shih default: 873e3ec7017SPing-Ke Shih return -EINVAL; 874e3ec7017SPing-Ke Shih } 875e3ec7017SPing-Ke Shih } 876e3ec7017SPing-Ke Shih 877e3ec7017SPing-Ke Shih return 0; 878e3ec7017SPing-Ke Shih } 879e3ec7017SPing-Ke Shih 880e3ec7017SPing-Ke Shih static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 881e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq) 882e3ec7017SPing-Ke Shih { 883e3ec7017SPing-Ke Shih int ret; 884e3ec7017SPing-Ke Shih 885e3ec7017SPing-Ke Shih for (; *cfg_seq; cfg_seq++) { 886e3ec7017SPing-Ke Shih ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 887e3ec7017SPing-Ke Shih PWR_INTF_MSK_PCIE, *cfg_seq); 888e3ec7017SPing-Ke Shih if (ret) 889e3ec7017SPing-Ke Shih return -EBUSY; 890e3ec7017SPing-Ke Shih } 891e3ec7017SPing-Ke Shih 892e3ec7017SPing-Ke Shih return 0; 893e3ec7017SPing-Ke Shih } 894e3ec7017SPing-Ke Shih 895e3ec7017SPing-Ke Shih static enum rtw89_rpwm_req_pwr_state 896e3ec7017SPing-Ke Shih rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 897e3ec7017SPing-Ke Shih { 898e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 899e3ec7017SPing-Ke Shih 900e3ec7017SPing-Ke Shih switch (rtwdev->ps_mode) { 901e3ec7017SPing-Ke Shih case RTW89_PS_MODE_RFOFF: 902e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 903e3ec7017SPing-Ke Shih break; 904e3ec7017SPing-Ke Shih case RTW89_PS_MODE_CLK_GATED: 905e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 906e3ec7017SPing-Ke Shih break; 907e3ec7017SPing-Ke Shih case RTW89_PS_MODE_PWR_GATED: 908e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 909e3ec7017SPing-Ke Shih break; 910e3ec7017SPing-Ke Shih default: 911e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 912e3ec7017SPing-Ke Shih break; 913e3ec7017SPing-Ke Shih } 914e3ec7017SPing-Ke Shih return state; 915e3ec7017SPing-Ke Shih } 916e3ec7017SPing-Ke Shih 917e3ec7017SPing-Ke Shih static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 918e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state req_pwr_state) 919e3ec7017SPing-Ke Shih { 920e3ec7017SPing-Ke Shih u16 request; 921e3ec7017SPing-Ke Shih 922e3ec7017SPing-Ke Shih request = rtw89_read16(rtwdev, R_AX_RPWM); 923e3ec7017SPing-Ke Shih request ^= request | PS_RPWM_TOGGLE; 924e3ec7017SPing-Ke Shih 925e3ec7017SPing-Ke Shih rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 926e3ec7017SPing-Ke Shih RPWM_SEQ_NUM_MAX; 927e3ec7017SPing-Ke Shih request |= FIELD_PREP(PS_RPWM_SEQ_NUM, rtwdev->mac.rpwm_seq_num); 928e3ec7017SPing-Ke Shih 929e3ec7017SPing-Ke Shih request |= req_pwr_state; 930e3ec7017SPing-Ke Shih 931e3ec7017SPing-Ke Shih if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 932e3ec7017SPing-Ke Shih request |= PS_RPWM_ACK; 933e3ec7017SPing-Ke Shih 934e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 935e3ec7017SPing-Ke Shih } 936e3ec7017SPing-Ke Shih 937e3ec7017SPing-Ke Shih static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 938e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state req_pwr_state) 939e3ec7017SPing-Ke Shih { 940e3ec7017SPing-Ke Shih bool request_deep_mode; 941e3ec7017SPing-Ke Shih bool in_deep_mode; 942e3ec7017SPing-Ke Shih u8 rpwm_req_num; 943e3ec7017SPing-Ke Shih u8 cpwm_rsp_seq; 944e3ec7017SPing-Ke Shih u8 cpwm_seq; 945e3ec7017SPing-Ke Shih u8 cpwm_status; 946e3ec7017SPing-Ke Shih 947e3ec7017SPing-Ke Shih if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 948e3ec7017SPing-Ke Shih request_deep_mode = true; 949e3ec7017SPing-Ke Shih else 950e3ec7017SPing-Ke Shih request_deep_mode = false; 951e3ec7017SPing-Ke Shih 952e3ec7017SPing-Ke Shih if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 953e3ec7017SPing-Ke Shih in_deep_mode = true; 954e3ec7017SPing-Ke Shih else 955e3ec7017SPing-Ke Shih in_deep_mode = false; 956e3ec7017SPing-Ke Shih 957e3ec7017SPing-Ke Shih if (request_deep_mode != in_deep_mode) 958e3ec7017SPing-Ke Shih return -EPERM; 959e3ec7017SPing-Ke Shih 960e3ec7017SPing-Ke Shih if (request_deep_mode) 961e3ec7017SPing-Ke Shih return 0; 962e3ec7017SPing-Ke Shih 963e3ec7017SPing-Ke Shih rpwm_req_num = rtwdev->mac.rpwm_seq_num; 964e3ec7017SPing-Ke Shih cpwm_rsp_seq = rtw89_read16_mask(rtwdev, R_AX_CPWM, 965e3ec7017SPing-Ke Shih PS_CPWM_RSP_SEQ_NUM); 966e3ec7017SPing-Ke Shih 967e3ec7017SPing-Ke Shih if (rpwm_req_num != cpwm_rsp_seq) 968e3ec7017SPing-Ke Shih return -EPERM; 969e3ec7017SPing-Ke Shih 970e3ec7017SPing-Ke Shih rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 971e3ec7017SPing-Ke Shih CPWM_SEQ_NUM_MAX; 972e3ec7017SPing-Ke Shih 973e3ec7017SPing-Ke Shih cpwm_seq = rtw89_read16_mask(rtwdev, R_AX_CPWM, PS_CPWM_SEQ_NUM); 974e3ec7017SPing-Ke Shih if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 975e3ec7017SPing-Ke Shih return -EPERM; 976e3ec7017SPing-Ke Shih 977e3ec7017SPing-Ke Shih cpwm_status = rtw89_read16_mask(rtwdev, R_AX_CPWM, PS_CPWM_STATE); 978e3ec7017SPing-Ke Shih if (cpwm_status != req_pwr_state) 979e3ec7017SPing-Ke Shih return -EPERM; 980e3ec7017SPing-Ke Shih 981e3ec7017SPing-Ke Shih return 0; 982e3ec7017SPing-Ke Shih } 983e3ec7017SPing-Ke Shih 984e3ec7017SPing-Ke Shih void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 985e3ec7017SPing-Ke Shih { 986e3ec7017SPing-Ke Shih enum rtw89_rpwm_req_pwr_state state; 987e3ec7017SPing-Ke Shih int ret; 988e3ec7017SPing-Ke Shih 989e3ec7017SPing-Ke Shih if (enter) 990e3ec7017SPing-Ke Shih state = rtw89_mac_get_req_pwr_state(rtwdev); 991e3ec7017SPing-Ke Shih else 992e3ec7017SPing-Ke Shih state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 993e3ec7017SPing-Ke Shih 994e3ec7017SPing-Ke Shih rtw89_mac_send_rpwm(rtwdev, state); 995e3ec7017SPing-Ke Shih ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, !ret, 996e3ec7017SPing-Ke Shih 1000, 15000, false, rtwdev, state); 997e3ec7017SPing-Ke Shih if (ret) 998e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 999e3ec7017SPing-Ke Shih enter ? "entering" : "leaving"); 1000e3ec7017SPing-Ke Shih } 1001e3ec7017SPing-Ke Shih 1002e3ec7017SPing-Ke Shih static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1003e3ec7017SPing-Ke Shih { 1004e3ec7017SPing-Ke Shih #define PWR_ACT 1 1005e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 1006e3ec7017SPing-Ke Shih const struct rtw89_pwr_cfg * const *cfg_seq; 1007e3ec7017SPing-Ke Shih struct rtw89_hal *hal = &rtwdev->hal; 1008e3ec7017SPing-Ke Shih int ret; 1009e3ec7017SPing-Ke Shih u8 val; 1010e3ec7017SPing-Ke Shih 1011e3ec7017SPing-Ke Shih if (on) 1012e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_on_seq; 1013e3ec7017SPing-Ke Shih else 1014e3ec7017SPing-Ke Shih cfg_seq = chip->pwr_off_seq; 1015e3ec7017SPing-Ke Shih 1016e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1017e3ec7017SPing-Ke Shih __rtw89_leave_ps_mode(rtwdev); 1018e3ec7017SPing-Ke Shih 1019e3ec7017SPing-Ke Shih val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1020e3ec7017SPing-Ke Shih if (on && val == PWR_ACT) { 1021e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC has already powered on\n"); 1022e3ec7017SPing-Ke Shih return -EBUSY; 1023e3ec7017SPing-Ke Shih } 1024e3ec7017SPing-Ke Shih 1025e3ec7017SPing-Ke Shih ret = rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1026e3ec7017SPing-Ke Shih if (ret) 1027e3ec7017SPing-Ke Shih return ret; 1028e3ec7017SPing-Ke Shih 1029e3ec7017SPing-Ke Shih if (on) { 1030e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1031e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1032e3ec7017SPing-Ke Shih } else { 1033e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1034e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1035e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1036e3ec7017SPing-Ke Shih hal->current_channel = 0; 1037e3ec7017SPing-Ke Shih } 1038e3ec7017SPing-Ke Shih 1039e3ec7017SPing-Ke Shih return 0; 1040e3ec7017SPing-Ke Shih #undef PWR_ACT 1041e3ec7017SPing-Ke Shih } 1042e3ec7017SPing-Ke Shih 1043e3ec7017SPing-Ke Shih void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1044e3ec7017SPing-Ke Shih { 1045e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 1046e3ec7017SPing-Ke Shih } 1047e3ec7017SPing-Ke Shih 1048e3ec7017SPing-Ke Shih static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1049e3ec7017SPing-Ke Shih { 1050e3ec7017SPing-Ke Shih u32 func_en = 0; 1051e3ec7017SPing-Ke Shih u32 ck_en = 0; 1052e3ec7017SPing-Ke Shih u32 c1pc_en = 0; 1053e3ec7017SPing-Ke Shih u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1054e3ec7017SPing-Ke Shih u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1055e3ec7017SPing-Ke Shih 1056e3ec7017SPing-Ke Shih func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1057e3ec7017SPing-Ke Shih B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1058e3ec7017SPing-Ke Shih B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN; 1059e3ec7017SPing-Ke Shih ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1060e3ec7017SPing-Ke Shih B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1061e3ec7017SPing-Ke Shih B_AX_RMAC_CKEN; 1062e3ec7017SPing-Ke Shih c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1063e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1064e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1065e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1066e3ec7017SPing-Ke Shih B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1067e3ec7017SPing-Ke Shih 1068e3ec7017SPing-Ke Shih if (en) { 1069e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1070e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1071e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1072e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1073e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1074e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1075e3ec7017SPing-Ke Shih } 1076e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1077e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1078e3ec7017SPing-Ke Shih } else { 1079e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1080e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1081e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_1) { 1082e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1083e3ec7017SPing-Ke Shih B_AX_CMAC1_FEN); 1084e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1085e3ec7017SPing-Ke Shih B_AX_R_SYM_ISO_CMAC12PP); 1086e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1087e3ec7017SPing-Ke Shih } 1088e3ec7017SPing-Ke Shih } 1089e3ec7017SPing-Ke Shih 1090e3ec7017SPing-Ke Shih return 0; 1091e3ec7017SPing-Ke Shih } 1092e3ec7017SPing-Ke Shih 1093e3ec7017SPing-Ke Shih static int dmac_func_en(struct rtw89_dev *rtwdev) 1094e3ec7017SPing-Ke Shih { 1095e3ec7017SPing-Ke Shih u32 val32; 1096e3ec7017SPing-Ke Shih 1097e3ec7017SPing-Ke Shih val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MAC_SEC_EN | 1098e3ec7017SPing-Ke Shih B_AX_DISPATCHER_EN | B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1099e3ec7017SPing-Ke Shih B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | B_AX_STA_SCH_EN | 1100e3ec7017SPing-Ke Shih B_AX_TXPKT_CTRL_EN | B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN); 1101e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1102e3ec7017SPing-Ke Shih 1103e3ec7017SPing-Ke Shih val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1104e3ec7017SPing-Ke Shih B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1105e3ec7017SPing-Ke Shih B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1106e3ec7017SPing-Ke Shih B_AX_WD_RLS_CLK_EN); 1107e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1108e3ec7017SPing-Ke Shih 1109*43863efeSChangcheng Deng return 0; 1110e3ec7017SPing-Ke Shih } 1111e3ec7017SPing-Ke Shih 1112e3ec7017SPing-Ke Shih static int chip_func_en(struct rtw89_dev *rtwdev) 1113e3ec7017SPing-Ke Shih { 1114e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL0, B_AX_OCP_L1_MASK); 1115e3ec7017SPing-Ke Shih 1116e3ec7017SPing-Ke Shih return 0; 1117e3ec7017SPing-Ke Shih } 1118e3ec7017SPing-Ke Shih 1119e3ec7017SPing-Ke Shih static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1120e3ec7017SPing-Ke Shih { 1121e3ec7017SPing-Ke Shih int ret; 1122e3ec7017SPing-Ke Shih 1123e3ec7017SPing-Ke Shih ret = dmac_func_en(rtwdev); 1124e3ec7017SPing-Ke Shih if (ret) 1125e3ec7017SPing-Ke Shih return ret; 1126e3ec7017SPing-Ke Shih 1127e3ec7017SPing-Ke Shih ret = cmac_func_en(rtwdev, 0, true); 1128e3ec7017SPing-Ke Shih if (ret) 1129e3ec7017SPing-Ke Shih return ret; 1130e3ec7017SPing-Ke Shih 1131e3ec7017SPing-Ke Shih ret = chip_func_en(rtwdev); 1132e3ec7017SPing-Ke Shih if (ret) 1133e3ec7017SPing-Ke Shih return ret; 1134e3ec7017SPing-Ke Shih 1135e3ec7017SPing-Ke Shih return ret; 1136e3ec7017SPing-Ke Shih } 1137e3ec7017SPing-Ke Shih 1138e3ec7017SPing-Ke Shih /* PCIE 64 */ 1139e3ec7017SPing-Ke Shih const struct rtw89_dle_size wde_size0 = { 1140e3ec7017SPing-Ke Shih RTW89_WDE_PG_64, 4095, 1, 1141e3ec7017SPing-Ke Shih }; 1142e3ec7017SPing-Ke Shih 1143e3ec7017SPing-Ke Shih /* DLFW */ 1144e3ec7017SPing-Ke Shih const struct rtw89_dle_size wde_size4 = { 1145e3ec7017SPing-Ke Shih RTW89_WDE_PG_64, 0, 4096, 1146e3ec7017SPing-Ke Shih }; 1147e3ec7017SPing-Ke Shih 1148e3ec7017SPing-Ke Shih /* PCIE */ 1149e3ec7017SPing-Ke Shih const struct rtw89_dle_size ple_size0 = { 1150e3ec7017SPing-Ke Shih RTW89_PLE_PG_128, 1520, 16, 1151e3ec7017SPing-Ke Shih }; 1152e3ec7017SPing-Ke Shih 1153e3ec7017SPing-Ke Shih /* DLFW */ 1154e3ec7017SPing-Ke Shih const struct rtw89_dle_size ple_size4 = { 1155e3ec7017SPing-Ke Shih RTW89_PLE_PG_128, 64, 1472, 1156e3ec7017SPing-Ke Shih }; 1157e3ec7017SPing-Ke Shih 1158e3ec7017SPing-Ke Shih /* PCIE 64 */ 1159e3ec7017SPing-Ke Shih const struct rtw89_wde_quota wde_qt0 = { 1160e3ec7017SPing-Ke Shih 3792, 196, 0, 107, 1161e3ec7017SPing-Ke Shih }; 1162e3ec7017SPing-Ke Shih 1163e3ec7017SPing-Ke Shih /* DLFW */ 1164e3ec7017SPing-Ke Shih const struct rtw89_wde_quota wde_qt4 = { 1165e3ec7017SPing-Ke Shih 0, 0, 0, 0, 1166e3ec7017SPing-Ke Shih }; 1167e3ec7017SPing-Ke Shih 1168e3ec7017SPing-Ke Shih /* PCIE SCC */ 1169e3ec7017SPing-Ke Shih const struct rtw89_ple_quota ple_qt4 = { 1170e3ec7017SPing-Ke Shih 264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8, 1171e3ec7017SPing-Ke Shih }; 1172e3ec7017SPing-Ke Shih 1173e3ec7017SPing-Ke Shih /* PCIE SCC */ 1174e3ec7017SPing-Ke Shih const struct rtw89_ple_quota ple_qt5 = { 1175e3ec7017SPing-Ke Shih 264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120, 1176e3ec7017SPing-Ke Shih }; 1177e3ec7017SPing-Ke Shih 1178e3ec7017SPing-Ke Shih /* DLFW */ 1179e3ec7017SPing-Ke Shih const struct rtw89_ple_quota ple_qt13 = { 1180e3ec7017SPing-Ke Shih 0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0 1181e3ec7017SPing-Ke Shih }; 1182e3ec7017SPing-Ke Shih 1183e3ec7017SPing-Ke Shih static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1184e3ec7017SPing-Ke Shih enum rtw89_qta_mode mode) 1185e3ec7017SPing-Ke Shih { 1186e3ec7017SPing-Ke Shih struct rtw89_mac_info *mac = &rtwdev->mac; 1187e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 1188e3ec7017SPing-Ke Shih 1189e3ec7017SPing-Ke Shih cfg = &rtwdev->chip->dle_mem[mode]; 1190e3ec7017SPing-Ke Shih if (!cfg) 1191e3ec7017SPing-Ke Shih return NULL; 1192e3ec7017SPing-Ke Shih 1193e3ec7017SPing-Ke Shih if (cfg->mode != mode) { 1194e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1195e3ec7017SPing-Ke Shih return NULL; 1196e3ec7017SPing-Ke Shih } 1197e3ec7017SPing-Ke Shih 1198e3ec7017SPing-Ke Shih mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; 1199e3ec7017SPing-Ke Shih mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1200e3ec7017SPing-Ke Shih mac->dle_info.qta_mode = mode; 1201e3ec7017SPing-Ke Shih mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1202e3ec7017SPing-Ke Shih mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1203e3ec7017SPing-Ke Shih 1204e3ec7017SPing-Ke Shih return cfg; 1205e3ec7017SPing-Ke Shih } 1206e3ec7017SPing-Ke Shih 1207e3ec7017SPing-Ke Shih static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1208e3ec7017SPing-Ke Shih const struct rtw89_dle_size *ple) 1209e3ec7017SPing-Ke Shih { 1210e3ec7017SPing-Ke Shih return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1211e3ec7017SPing-Ke Shih ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1212e3ec7017SPing-Ke Shih } 1213e3ec7017SPing-Ke Shih 1214e3ec7017SPing-Ke Shih static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1215e3ec7017SPing-Ke Shih { 1216e3ec7017SPing-Ke Shih if (enable) 1217e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1218e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1219e3ec7017SPing-Ke Shih else 1220e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1221e3ec7017SPing-Ke Shih B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1222e3ec7017SPing-Ke Shih } 1223e3ec7017SPing-Ke Shih 1224e3ec7017SPing-Ke Shih static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1225e3ec7017SPing-Ke Shih { 1226e3ec7017SPing-Ke Shih if (enable) 1227e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, 1228e3ec7017SPing-Ke Shih B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1229e3ec7017SPing-Ke Shih else 1230e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, 1231e3ec7017SPing-Ke Shih B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1232e3ec7017SPing-Ke Shih } 1233e3ec7017SPing-Ke Shih 1234e3ec7017SPing-Ke Shih static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1235e3ec7017SPing-Ke Shih { 1236e3ec7017SPing-Ke Shih const struct rtw89_dle_size *size_cfg; 1237e3ec7017SPing-Ke Shih u32 val; 1238e3ec7017SPing-Ke Shih u8 bound = 0; 1239e3ec7017SPing-Ke Shih 1240e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1241e3ec7017SPing-Ke Shih size_cfg = cfg->wde_size; 1242e3ec7017SPing-Ke Shih 1243e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1244e3ec7017SPing-Ke Shih default: 1245e3ec7017SPing-Ke Shih case RTW89_WDE_PG_64: 1246e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1247e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1248e3ec7017SPing-Ke Shih break; 1249e3ec7017SPing-Ke Shih case RTW89_WDE_PG_128: 1250e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1251e3ec7017SPing-Ke Shih B_AX_WDE_PAGE_SEL_MASK); 1252e3ec7017SPing-Ke Shih break; 1253e3ec7017SPing-Ke Shih case RTW89_WDE_PG_256: 1254e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1255e3ec7017SPing-Ke Shih return -EINVAL; 1256e3ec7017SPing-Ke Shih } 1257e3ec7017SPing-Ke Shih 1258e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1259e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1260e3ec7017SPing-Ke Shih B_AX_WDE_FREE_PAGE_NUM_MASK); 1261e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1262e3ec7017SPing-Ke Shih 1263e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1264e3ec7017SPing-Ke Shih bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1265e3ec7017SPing-Ke Shih * size_cfg->pge_size / DLE_BOUND_UNIT; 1266e3ec7017SPing-Ke Shih size_cfg = cfg->ple_size; 1267e3ec7017SPing-Ke Shih 1268e3ec7017SPing-Ke Shih switch (size_cfg->pge_size) { 1269e3ec7017SPing-Ke Shih default: 1270e3ec7017SPing-Ke Shih case RTW89_PLE_PG_64: 1271e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1272e3ec7017SPing-Ke Shih return -EINVAL; 1273e3ec7017SPing-Ke Shih case RTW89_PLE_PG_128: 1274e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1275e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1276e3ec7017SPing-Ke Shih break; 1277e3ec7017SPing-Ke Shih case RTW89_PLE_PG_256: 1278e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1279e3ec7017SPing-Ke Shih B_AX_PLE_PAGE_SEL_MASK); 1280e3ec7017SPing-Ke Shih break; 1281e3ec7017SPing-Ke Shih } 1282e3ec7017SPing-Ke Shih 1283e3ec7017SPing-Ke Shih val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1284e3ec7017SPing-Ke Shih val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1285e3ec7017SPing-Ke Shih B_AX_PLE_FREE_PAGE_NUM_MASK); 1286e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1287e3ec7017SPing-Ke Shih 1288e3ec7017SPing-Ke Shih return 0; 1289e3ec7017SPing-Ke Shih } 1290e3ec7017SPing-Ke Shih 1291e3ec7017SPing-Ke Shih #define INVALID_QT_WCPU U16_MAX 1292e3ec7017SPing-Ke Shih #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1293e3ec7017SPing-Ke Shih do { \ 1294e3ec7017SPing-Ke Shih val = ((_min_x) & \ 1295e3ec7017SPing-Ke Shih B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1296e3ec7017SPing-Ke Shih (((_max_x) << 16) & \ 1297e3ec7017SPing-Ke Shih B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1298e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, \ 1299e3ec7017SPing-Ke Shih R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1300e3ec7017SPing-Ke Shih val); \ 1301e3ec7017SPing-Ke Shih } while (0) 1302e3ec7017SPing-Ke Shih #define SET_QUOTA(_x, _module, _idx) \ 1303e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1304e3ec7017SPing-Ke Shih 1305e3ec7017SPing-Ke Shih static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1306e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *min_cfg, 1307e3ec7017SPing-Ke Shih const struct rtw89_wde_quota *max_cfg, 1308e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 1309e3ec7017SPing-Ke Shih { 1310e3ec7017SPing-Ke Shih u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1311e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu : min_cfg->wcpu; 1312e3ec7017SPing-Ke Shih u32 val; 1313e3ec7017SPing-Ke Shih 1314e3ec7017SPing-Ke Shih SET_QUOTA(hif, WDE, 0); 1315e3ec7017SPing-Ke Shih SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1316e3ec7017SPing-Ke Shih SET_QUOTA(pkt_in, WDE, 3); 1317e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, WDE, 4); 1318e3ec7017SPing-Ke Shih } 1319e3ec7017SPing-Ke Shih 1320e3ec7017SPing-Ke Shih static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1321e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *min_cfg, 1322e3ec7017SPing-Ke Shih const struct rtw89_ple_quota *max_cfg) 1323e3ec7017SPing-Ke Shih { 1324e3ec7017SPing-Ke Shih u32 val; 1325e3ec7017SPing-Ke Shih 1326e3ec7017SPing-Ke Shih SET_QUOTA(cma0_tx, PLE, 0); 1327e3ec7017SPing-Ke Shih SET_QUOTA(cma1_tx, PLE, 1); 1328e3ec7017SPing-Ke Shih SET_QUOTA(c2h, PLE, 2); 1329e3ec7017SPing-Ke Shih SET_QUOTA(h2c, PLE, 3); 1330e3ec7017SPing-Ke Shih SET_QUOTA(wcpu, PLE, 4); 1331e3ec7017SPing-Ke Shih SET_QUOTA(mpdu_proc, PLE, 5); 1332e3ec7017SPing-Ke Shih SET_QUOTA(cma0_dma, PLE, 6); 1333e3ec7017SPing-Ke Shih SET_QUOTA(cma1_dma, PLE, 7); 1334e3ec7017SPing-Ke Shih SET_QUOTA(bb_rpt, PLE, 8); 1335e3ec7017SPing-Ke Shih SET_QUOTA(wd_rel, PLE, 9); 1336e3ec7017SPing-Ke Shih SET_QUOTA(cpu_io, PLE, 10); 1337e3ec7017SPing-Ke Shih } 1338e3ec7017SPing-Ke Shih 1339e3ec7017SPing-Ke Shih #undef SET_QUOTA 1340e3ec7017SPing-Ke Shih 1341e3ec7017SPing-Ke Shih static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1342e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, 1343e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu) 1344e3ec7017SPing-Ke Shih { 1345e3ec7017SPing-Ke Shih wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1346e3ec7017SPing-Ke Shih ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1347e3ec7017SPing-Ke Shih } 1348e3ec7017SPing-Ke Shih 1349e3ec7017SPing-Ke Shih static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1350e3ec7017SPing-Ke Shih enum rtw89_qta_mode ext_mode) 1351e3ec7017SPing-Ke Shih { 1352e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg, *ext_cfg; 1353e3ec7017SPing-Ke Shih u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1354e3ec7017SPing-Ke Shih int ret = 0; 1355e3ec7017SPing-Ke Shih u32 ini; 1356e3ec7017SPing-Ke Shih 1357e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1358e3ec7017SPing-Ke Shih if (ret) 1359e3ec7017SPing-Ke Shih return ret; 1360e3ec7017SPing-Ke Shih 1361e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 1362e3ec7017SPing-Ke Shih if (!cfg) { 1363e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1364e3ec7017SPing-Ke Shih ret = -EINVAL; 1365e3ec7017SPing-Ke Shih goto error; 1366e3ec7017SPing-Ke Shih } 1367e3ec7017SPing-Ke Shih 1368e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_DLFW) { 1369e3ec7017SPing-Ke Shih ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1370e3ec7017SPing-Ke Shih if (!ext_cfg) { 1371e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1372e3ec7017SPing-Ke Shih ext_mode); 1373e3ec7017SPing-Ke Shih ret = -EINVAL; 1374e3ec7017SPing-Ke Shih goto error; 1375e3ec7017SPing-Ke Shih } 1376e3ec7017SPing-Ke Shih ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1377e3ec7017SPing-Ke Shih } 1378e3ec7017SPing-Ke Shih 1379e3ec7017SPing-Ke Shih if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { 1380e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1381e3ec7017SPing-Ke Shih ret = -EINVAL; 1382e3ec7017SPing-Ke Shih goto error; 1383e3ec7017SPing-Ke Shih } 1384e3ec7017SPing-Ke Shih 1385e3ec7017SPing-Ke Shih dle_func_en(rtwdev, false); 1386e3ec7017SPing-Ke Shih dle_clk_en(rtwdev, true); 1387e3ec7017SPing-Ke Shih 1388e3ec7017SPing-Ke Shih ret = dle_mix_cfg(rtwdev, cfg); 1389e3ec7017SPing-Ke Shih if (ret) { 1390e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1391e3ec7017SPing-Ke Shih goto error; 1392e3ec7017SPing-Ke Shih } 1393e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1394e3ec7017SPing-Ke Shih 1395e3ec7017SPing-Ke Shih dle_func_en(rtwdev, true); 1396e3ec7017SPing-Ke Shih 1397e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, ini, 1398e3ec7017SPing-Ke Shih (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1399e3ec7017SPing-Ke Shih 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1400e3ec7017SPing-Ke Shih if (ret) { 1401e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1402e3ec7017SPing-Ke Shih return ret; 1403e3ec7017SPing-Ke Shih } 1404e3ec7017SPing-Ke Shih 1405e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, ini, 1406e3ec7017SPing-Ke Shih (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1407e3ec7017SPing-Ke Shih 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1408e3ec7017SPing-Ke Shih if (ret) { 1409e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1410e3ec7017SPing-Ke Shih return ret; 1411e3ec7017SPing-Ke Shih } 1412e3ec7017SPing-Ke Shih 1413e3ec7017SPing-Ke Shih return 0; 1414e3ec7017SPing-Ke Shih error: 1415e3ec7017SPing-Ke Shih dle_func_en(rtwdev, false); 1416e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1417e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1418e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1419e3ec7017SPing-Ke Shih rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1420e3ec7017SPing-Ke Shih 1421e3ec7017SPing-Ke Shih return ret; 1422e3ec7017SPing-Ke Shih } 1423e3ec7017SPing-Ke Shih 1424e3ec7017SPing-Ke Shih static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1425e3ec7017SPing-Ke Shih { 1426e3ec7017SPing-Ke Shih u32 msk32; 1427e3ec7017SPing-Ke Shih u32 val32; 1428e3ec7017SPing-Ke Shih 1429e3ec7017SPing-Ke Shih msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1430e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1431e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1432e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1433e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1434e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1435e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1436e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1437e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1438e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1439e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1440e3ec7017SPing-Ke Shih B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1441e3ec7017SPing-Ke Shih B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1442e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1443e3ec7017SPing-Ke Shih 1444e3ec7017SPing-Ke Shih if ((val32 & msk32) == msk32) 1445e3ec7017SPing-Ke Shih return true; 1446e3ec7017SPing-Ke Shih 1447e3ec7017SPing-Ke Shih return false; 1448e3ec7017SPing-Ke Shih } 1449e3ec7017SPing-Ke Shih 1450e3ec7017SPing-Ke Shih static int sta_sch_init(struct rtw89_dev *rtwdev) 1451e3ec7017SPing-Ke Shih { 1452e3ec7017SPing-Ke Shih u32 p_val; 1453e3ec7017SPing-Ke Shih u8 val; 1454e3ec7017SPing-Ke Shih int ret; 1455e3ec7017SPing-Ke Shih 1456e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1457e3ec7017SPing-Ke Shih if (ret) 1458e3ec7017SPing-Ke Shih return ret; 1459e3ec7017SPing-Ke Shih 1460e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1461e3ec7017SPing-Ke Shih val |= B_AX_SS_EN; 1462e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1463e3ec7017SPing-Ke Shih 1464e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1465e3ec7017SPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1466e3ec7017SPing-Ke Shih if (ret) { 1467e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1468e3ec7017SPing-Ke Shih return ret; 1469e3ec7017SPing-Ke Shih } 1470e3ec7017SPing-Ke Shih 1471e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 1472e3ec7017SPing-Ke Shih 1473e3ec7017SPing-Ke Shih return 0; 1474e3ec7017SPing-Ke Shih } 1475e3ec7017SPing-Ke Shih 1476e3ec7017SPing-Ke Shih static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1477e3ec7017SPing-Ke Shih { 1478e3ec7017SPing-Ke Shih int ret; 1479e3ec7017SPing-Ke Shih 1480e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1481e3ec7017SPing-Ke Shih if (ret) 1482e3ec7017SPing-Ke Shih return ret; 1483e3ec7017SPing-Ke Shih 1484e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1485e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1486e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1487e3ec7017SPing-Ke Shih B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1488e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1489e3ec7017SPing-Ke Shih 1490e3ec7017SPing-Ke Shih return 0; 1491e3ec7017SPing-Ke Shih } 1492e3ec7017SPing-Ke Shih 1493e3ec7017SPing-Ke Shih static int sec_eng_init(struct rtw89_dev *rtwdev) 1494e3ec7017SPing-Ke Shih { 1495e3ec7017SPing-Ke Shih u32 val = 0; 1496e3ec7017SPing-Ke Shih int ret; 1497e3ec7017SPing-Ke Shih 1498e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1499e3ec7017SPing-Ke Shih if (ret) 1500e3ec7017SPing-Ke Shih return ret; 1501e3ec7017SPing-Ke Shih 1502e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 1503e3ec7017SPing-Ke Shih /* init clock */ 1504e3ec7017SPing-Ke Shih val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 1505e3ec7017SPing-Ke Shih /* init TX encryption */ 1506e3ec7017SPing-Ke Shih val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 1507e3ec7017SPing-Ke Shih val |= (B_AX_MC_DEC | B_AX_BC_DEC); 1508e3ec7017SPing-Ke Shih val &= ~B_AX_TX_PARTIAL_MODE; 1509e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 1510e3ec7017SPing-Ke Shih 1511e3ec7017SPing-Ke Shih /* init MIC ICV append */ 1512e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 1513e3ec7017SPing-Ke Shih val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 1514e3ec7017SPing-Ke Shih 1515e3ec7017SPing-Ke Shih /* option init */ 1516e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 1517e3ec7017SPing-Ke Shih 1518e3ec7017SPing-Ke Shih return 0; 1519e3ec7017SPing-Ke Shih } 1520e3ec7017SPing-Ke Shih 1521e3ec7017SPing-Ke Shih static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1522e3ec7017SPing-Ke Shih { 1523e3ec7017SPing-Ke Shih int ret; 1524e3ec7017SPing-Ke Shih 1525e3ec7017SPing-Ke Shih ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 1526e3ec7017SPing-Ke Shih if (ret) { 1527e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 1528e3ec7017SPing-Ke Shih return ret; 1529e3ec7017SPing-Ke Shih } 1530e3ec7017SPing-Ke Shih 1531e3ec7017SPing-Ke Shih ret = hfc_init(rtwdev, true, true, true); 1532e3ec7017SPing-Ke Shih if (ret) { 1533e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 1534e3ec7017SPing-Ke Shih return ret; 1535e3ec7017SPing-Ke Shih } 1536e3ec7017SPing-Ke Shih 1537e3ec7017SPing-Ke Shih ret = sta_sch_init(rtwdev); 1538e3ec7017SPing-Ke Shih if (ret) { 1539e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 1540e3ec7017SPing-Ke Shih return ret; 1541e3ec7017SPing-Ke Shih } 1542e3ec7017SPing-Ke Shih 1543e3ec7017SPing-Ke Shih ret = mpdu_proc_init(rtwdev); 1544e3ec7017SPing-Ke Shih if (ret) { 1545e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 1546e3ec7017SPing-Ke Shih return ret; 1547e3ec7017SPing-Ke Shih } 1548e3ec7017SPing-Ke Shih 1549e3ec7017SPing-Ke Shih ret = sec_eng_init(rtwdev); 1550e3ec7017SPing-Ke Shih if (ret) { 1551e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 1552e3ec7017SPing-Ke Shih return ret; 1553e3ec7017SPing-Ke Shih } 1554e3ec7017SPing-Ke Shih 1555e3ec7017SPing-Ke Shih return ret; 1556e3ec7017SPing-Ke Shih } 1557e3ec7017SPing-Ke Shih 1558e3ec7017SPing-Ke Shih static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1559e3ec7017SPing-Ke Shih { 1560e3ec7017SPing-Ke Shih u32 val, reg; 1561e3ec7017SPing-Ke Shih u16 p_val; 1562e3ec7017SPing-Ke Shih int ret; 1563e3ec7017SPing-Ke Shih 1564e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1565e3ec7017SPing-Ke Shih if (ret) 1566e3ec7017SPing-Ke Shih return ret; 1567e3ec7017SPing-Ke Shih 1568e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); 1569e3ec7017SPing-Ke Shih 1570e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1571e3ec7017SPing-Ke Shih val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 1572e3ec7017SPing-Ke Shih B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 1573e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1574e3ec7017SPing-Ke Shih 1575e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 1576e3ec7017SPing-Ke Shih 1, TRXCFG_WAIT_CNT, false, rtwdev, B_AX_ADDR_CAM_CLR); 1577e3ec7017SPing-Ke Shih if (ret) { 1578e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 1579e3ec7017SPing-Ke Shih return ret; 1580e3ec7017SPing-Ke Shih } 1581e3ec7017SPing-Ke Shih 1582e3ec7017SPing-Ke Shih return 0; 1583e3ec7017SPing-Ke Shih } 1584e3ec7017SPing-Ke Shih 1585e3ec7017SPing-Ke Shih static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1586e3ec7017SPing-Ke Shih { 1587e3ec7017SPing-Ke Shih u32 ret; 1588e3ec7017SPing-Ke Shih u32 reg; 1589e3ec7017SPing-Ke Shih 1590e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1591e3ec7017SPing-Ke Shih if (ret) 1592e3ec7017SPing-Ke Shih return ret; 1593e3ec7017SPing-Ke Shih 1594e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); 1595e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, SCH_PREBKF_24US); 1596e3ec7017SPing-Ke Shih 1597e3ec7017SPing-Ke Shih return 0; 1598e3ec7017SPing-Ke Shih } 1599e3ec7017SPing-Ke Shih 1600e3ec7017SPing-Ke Shih static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 1601e3ec7017SPing-Ke Shih enum rtw89_machdr_frame_type type, 1602e3ec7017SPing-Ke Shih enum rtw89_mac_fwd_target fwd_target, 1603e3ec7017SPing-Ke Shih u8 mac_idx) 1604e3ec7017SPing-Ke Shih { 1605e3ec7017SPing-Ke Shih u32 reg; 1606e3ec7017SPing-Ke Shih u32 val; 1607e3ec7017SPing-Ke Shih 1608e3ec7017SPing-Ke Shih switch (fwd_target) { 1609e3ec7017SPing-Ke Shih case RTW89_FWD_DONT_CARE: 1610e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_DROP; 1611e3ec7017SPing-Ke Shih break; 1612e3ec7017SPing-Ke Shih case RTW89_FWD_TO_HOST: 1613e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_HOST; 1614e3ec7017SPing-Ke Shih break; 1615e3ec7017SPing-Ke Shih case RTW89_FWD_TO_WLAN_CPU: 1616e3ec7017SPing-Ke Shih val = RX_FLTR_FRAME_TO_WLCPU; 1617e3ec7017SPing-Ke Shih break; 1618e3ec7017SPing-Ke Shih default: 1619e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 1620e3ec7017SPing-Ke Shih return -EINVAL; 1621e3ec7017SPing-Ke Shih } 1622e3ec7017SPing-Ke Shih 1623e3ec7017SPing-Ke Shih switch (type) { 1624e3ec7017SPing-Ke Shih case RTW89_MGNT: 1625e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); 1626e3ec7017SPing-Ke Shih break; 1627e3ec7017SPing-Ke Shih case RTW89_CTRL: 1628e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); 1629e3ec7017SPing-Ke Shih break; 1630e3ec7017SPing-Ke Shih case RTW89_DATA: 1631e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); 1632e3ec7017SPing-Ke Shih break; 1633e3ec7017SPing-Ke Shih default: 1634e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 1635e3ec7017SPing-Ke Shih return -EINVAL; 1636e3ec7017SPing-Ke Shih } 1637e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1638e3ec7017SPing-Ke Shih 1639e3ec7017SPing-Ke Shih return 0; 1640e3ec7017SPing-Ke Shih } 1641e3ec7017SPing-Ke Shih 1642e3ec7017SPing-Ke Shih static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1643e3ec7017SPing-Ke Shih { 1644e3ec7017SPing-Ke Shih int ret, i; 1645e3ec7017SPing-Ke Shih u32 mac_ftlr, plcp_ftlr; 1646e3ec7017SPing-Ke Shih 1647e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1648e3ec7017SPing-Ke Shih if (ret) 1649e3ec7017SPing-Ke Shih return ret; 1650e3ec7017SPing-Ke Shih 1651e3ec7017SPing-Ke Shih for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 1652e3ec7017SPing-Ke Shih ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 1653e3ec7017SPing-Ke Shih mac_idx); 1654e3ec7017SPing-Ke Shih if (ret) 1655e3ec7017SPing-Ke Shih return ret; 1656e3ec7017SPing-Ke Shih } 1657e3ec7017SPing-Ke Shih mac_ftlr = rtwdev->hal.rx_fltr; 1658e3ec7017SPing-Ke Shih plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 1659e3ec7017SPing-Ke Shih B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 1660e3ec7017SPing-Ke Shih B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 1661e3ec7017SPing-Ke Shih B_AX_HE_SIGB_CRC_CHK; 1662e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), 1663e3ec7017SPing-Ke Shih mac_ftlr); 1664e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), 1665e3ec7017SPing-Ke Shih plcp_ftlr); 1666e3ec7017SPing-Ke Shih 1667e3ec7017SPing-Ke Shih return 0; 1668e3ec7017SPing-Ke Shih } 1669e3ec7017SPing-Ke Shih 1670e3ec7017SPing-Ke Shih static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 1671e3ec7017SPing-Ke Shih { 1672e3ec7017SPing-Ke Shih u32 reg, val32; 1673e3ec7017SPing-Ke Shih u32 b_rsp_chk_nav, b_rsp_chk_cca; 1674e3ec7017SPing-Ke Shih 1675e3ec7017SPing-Ke Shih b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 1676e3ec7017SPing-Ke Shih B_AX_RSP_CHK_BASIC_NAV; 1677e3ec7017SPing-Ke Shih b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 1678e3ec7017SPing-Ke Shih B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 1679e3ec7017SPing-Ke Shih B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 1680e3ec7017SPing-Ke Shih 1681e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 1682e3ec7017SPing-Ke Shih case RTL8852A: 1683e3ec7017SPing-Ke Shih case RTL8852B: 1684e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 1685e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 1686e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 1687e3ec7017SPing-Ke Shih 1688e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1689e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 1690e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 1691e3ec7017SPing-Ke Shih break; 1692e3ec7017SPing-Ke Shih default: 1693e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 1694e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 1695e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 1696e3ec7017SPing-Ke Shih 1697e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1698e3ec7017SPing-Ke Shih val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 1699e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 1700e3ec7017SPing-Ke Shih break; 1701e3ec7017SPing-Ke Shih } 1702e3ec7017SPing-Ke Shih } 1703e3ec7017SPing-Ke Shih 1704e3ec7017SPing-Ke Shih static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1705e3ec7017SPing-Ke Shih { 1706e3ec7017SPing-Ke Shih u32 val, reg; 1707e3ec7017SPing-Ke Shih int ret; 1708e3ec7017SPing-Ke Shih 1709e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1710e3ec7017SPing-Ke Shih if (ret) 1711e3ec7017SPing-Ke Shih return ret; 1712e3ec7017SPing-Ke Shih 1713e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); 1714e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1715e3ec7017SPing-Ke Shih val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 1716e3ec7017SPing-Ke Shih B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 1717e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 1718e3ec7017SPing-Ke Shih B_AX_CTN_CHK_INTRA_NAV | 1719e3ec7017SPing-Ke Shih B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 1720e3ec7017SPing-Ke Shih B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 1721e3ec7017SPing-Ke Shih B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 1722e3ec7017SPing-Ke Shih B_AX_CTN_CHK_CCA_P20 | B_AX_SIFS_CHK_EDCCA); 1723e3ec7017SPing-Ke Shih val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 1724e3ec7017SPing-Ke Shih B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 1725e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 1726e3ec7017SPing-Ke Shih B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV); 1727e3ec7017SPing-Ke Shih 1728e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1729e3ec7017SPing-Ke Shih 1730e3ec7017SPing-Ke Shih _patch_dis_resp_chk(rtwdev, mac_idx); 1731e3ec7017SPing-Ke Shih 1732e3ec7017SPing-Ke Shih return 0; 1733e3ec7017SPing-Ke Shih } 1734e3ec7017SPing-Ke Shih 1735e3ec7017SPing-Ke Shih static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1736e3ec7017SPing-Ke Shih { 1737e3ec7017SPing-Ke Shih u32 reg; 1738e3ec7017SPing-Ke Shih int ret; 1739e3ec7017SPing-Ke Shih 1740e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1741e3ec7017SPing-Ke Shih if (ret) 1742e3ec7017SPing-Ke Shih return ret; 1743e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); 1744e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 1745e3ec7017SPing-Ke Shih 1746e3ec7017SPing-Ke Shih return 0; 1747e3ec7017SPing-Ke Shih } 1748e3ec7017SPing-Ke Shih 1749e3ec7017SPing-Ke Shih static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1750e3ec7017SPing-Ke Shih { 1751e3ec7017SPing-Ke Shih u32 reg; 1752e3ec7017SPing-Ke Shih int ret; 1753e3ec7017SPing-Ke Shih 1754e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1755e3ec7017SPing-Ke Shih if (ret) 1756e3ec7017SPing-Ke Shih return ret; 1757e3ec7017SPing-Ke Shih 1758e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); 1759e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 1760e3ec7017SPing-Ke Shih 1761e3ec7017SPing-Ke Shih return 0; 1762e3ec7017SPing-Ke Shih } 1763e3ec7017SPing-Ke Shih 1764e3ec7017SPing-Ke Shih static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1765e3ec7017SPing-Ke Shih { 1766e3ec7017SPing-Ke Shih u32 reg, val, sifs; 1767e3ec7017SPing-Ke Shih int ret; 1768e3ec7017SPing-Ke Shih 1769e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1770e3ec7017SPing-Ke Shih if (ret) 1771e3ec7017SPing-Ke Shih return ret; 1772e3ec7017SPing-Ke Shih 1773e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1774e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1775e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 1776e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 1777e3ec7017SPing-Ke Shih 1778e3ec7017SPing-Ke Shih switch (rtwdev->chip->chip_id) { 1779e3ec7017SPing-Ke Shih case RTL8852A: 1780e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52A; 1781e3ec7017SPing-Ke Shih break; 1782e3ec7017SPing-Ke Shih case RTL8852B: 1783e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52B; 1784e3ec7017SPing-Ke Shih break; 1785e3ec7017SPing-Ke Shih default: 1786e3ec7017SPing-Ke Shih sifs = WMAC_SPEC_SIFS_OFDM_52C; 1787e3ec7017SPing-Ke Shih break; 1788e3ec7017SPing-Ke Shih } 1789e3ec7017SPing-Ke Shih val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 1790e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 1791e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1792e3ec7017SPing-Ke Shih 1793e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); 1794e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 1795e3ec7017SPing-Ke Shih 1796e3ec7017SPing-Ke Shih return 0; 1797e3ec7017SPing-Ke Shih } 1798e3ec7017SPing-Ke Shih 1799e3ec7017SPing-Ke Shih static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1800e3ec7017SPing-Ke Shih { 1801e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_CCA_TO 32 1802e3ec7017SPing-Ke Shih #define TRXCFG_RMAC_DATA_TO 15 1803e3ec7017SPing-Ke Shih #define RX_MAX_LEN_UNIT 512 1804e3ec7017SPing-Ke Shih #define PLD_RLS_MAX_PG 127 1805e3ec7017SPing-Ke Shih int ret; 1806e3ec7017SPing-Ke Shih u32 reg, rx_max_len, rx_qta; 1807e3ec7017SPing-Ke Shih u16 val; 1808e3ec7017SPing-Ke Shih 1809e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1810e3ec7017SPing-Ke Shih if (ret) 1811e3ec7017SPing-Ke Shih return ret; 1812e3ec7017SPing-Ke Shih 1813e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); 1814e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 1815e3ec7017SPing-Ke Shih 1816e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); 1817e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 1818e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 1819e3ec7017SPing-Ke Shih B_AX_RX_DLK_DATA_TIME_MASK); 1820e3ec7017SPing-Ke Shih val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 1821e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK); 1822e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 1823e3ec7017SPing-Ke Shih 1824e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); 1825e3ec7017SPing-Ke Shih rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 1826e3ec7017SPing-Ke Shih 1827e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); 1828e3ec7017SPing-Ke Shih if (mac_idx == RTW89_MAC_0) 1829e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 1830e3ec7017SPing-Ke Shih else 1831e3ec7017SPing-Ke Shih rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 1832e3ec7017SPing-Ke Shih rx_qta = rx_qta > PLD_RLS_MAX_PG ? PLD_RLS_MAX_PG : rx_qta; 1833e3ec7017SPing-Ke Shih rx_max_len = (rx_qta - 1) * rtwdev->mac.dle_info.ple_pg_size / 1834e3ec7017SPing-Ke Shih RX_MAX_LEN_UNIT; 1835e3ec7017SPing-Ke Shih rx_max_len = rx_max_len > B_AX_RX_MPDU_MAX_LEN_SIZE ? 1836e3ec7017SPing-Ke Shih B_AX_RX_MPDU_MAX_LEN_SIZE : rx_max_len; 1837e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 1838e3ec7017SPing-Ke Shih 1839e3ec7017SPing-Ke Shih if (rtwdev->chip->chip_id == RTL8852A && 1840e3ec7017SPing-Ke Shih rtwdev->hal.cv == CHIP_CBV) { 1841e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, 1842e3ec7017SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), 1843e3ec7017SPing-Ke Shih B_AX_RX_DLK_CCA_TIME_MASK, 0); 1844e3ec7017SPing-Ke Shih rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), 1845e3ec7017SPing-Ke Shih BIT(12)); 1846e3ec7017SPing-Ke Shih } 1847e3ec7017SPing-Ke Shih 1848e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); 1849e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 1850e3ec7017SPing-Ke Shih 1851e3ec7017SPing-Ke Shih return ret; 1852e3ec7017SPing-Ke Shih } 1853e3ec7017SPing-Ke Shih 1854e3ec7017SPing-Ke Shih static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1855e3ec7017SPing-Ke Shih { 1856e3ec7017SPing-Ke Shih u32 val, reg; 1857e3ec7017SPing-Ke Shih int ret; 1858e3ec7017SPing-Ke Shih 1859e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1860e3ec7017SPing-Ke Shih if (ret) 1861e3ec7017SPing-Ke Shih return ret; 1862e3ec7017SPing-Ke Shih 1863e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 1864e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1865e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 1866e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 1867e3ec7017SPing-Ke Shih val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 1868e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1869e3ec7017SPing-Ke Shih 1870e3ec7017SPing-Ke Shih return 0; 1871e3ec7017SPing-Ke Shih } 1872e3ec7017SPing-Ke Shih 1873e3ec7017SPing-Ke Shih static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 1874e3ec7017SPing-Ke Shih { 1875e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 1876e3ec7017SPing-Ke Shih 1877e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 1878e3ec7017SPing-Ke Shih if (!cfg) { 1879e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1880e3ec7017SPing-Ke Shih return false; 1881e3ec7017SPing-Ke Shih } 1882e3ec7017SPing-Ke Shih 1883e3ec7017SPing-Ke Shih return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 1884e3ec7017SPing-Ke Shih } 1885e3ec7017SPing-Ke Shih 1886e3ec7017SPing-Ke Shih static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1887e3ec7017SPing-Ke Shih { 1888e3ec7017SPing-Ke Shih u32 val, reg; 1889e3ec7017SPing-Ke Shih int ret; 1890e3ec7017SPing-Ke Shih 1891e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1892e3ec7017SPing-Ke Shih if (ret) 1893e3ec7017SPing-Ke Shih return ret; 1894e3ec7017SPing-Ke Shih 1895e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 1896e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 1897e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1898e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 1899e3ec7017SPing-Ke Shih B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 1900e3ec7017SPing-Ke Shih val |= B_AX_HW_CTS2SELF_EN; 1901e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1902e3ec7017SPing-Ke Shih 1903e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); 1904e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1905e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 1906e3ec7017SPing-Ke Shih val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 1907e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1908e3ec7017SPing-Ke Shih } 1909e3ec7017SPing-Ke Shih 1910e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 1911e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 1912e3ec7017SPing-Ke Shih val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 1913e3ec7017SPing-Ke Shih val |= B_AX_HW_CTS2SELF_EN; 1914e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 1915e3ec7017SPing-Ke Shih 1916e3ec7017SPing-Ke Shih return 0; 1917e3ec7017SPing-Ke Shih } 1918e3ec7017SPing-Ke Shih 1919e3ec7017SPing-Ke Shih static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1920e3ec7017SPing-Ke Shih { 1921e3ec7017SPing-Ke Shih int ret; 1922e3ec7017SPing-Ke Shih 1923e3ec7017SPing-Ke Shih ret = scheduler_init(rtwdev, mac_idx); 1924e3ec7017SPing-Ke Shih if (ret) { 1925e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 1926e3ec7017SPing-Ke Shih return ret; 1927e3ec7017SPing-Ke Shih } 1928e3ec7017SPing-Ke Shih 1929e3ec7017SPing-Ke Shih ret = addr_cam_init(rtwdev, mac_idx); 1930e3ec7017SPing-Ke Shih if (ret) { 1931e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 1932e3ec7017SPing-Ke Shih ret); 1933e3ec7017SPing-Ke Shih return ret; 1934e3ec7017SPing-Ke Shih } 1935e3ec7017SPing-Ke Shih 1936e3ec7017SPing-Ke Shih ret = rx_fltr_init(rtwdev, mac_idx); 1937e3ec7017SPing-Ke Shih if (ret) { 1938e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 1939e3ec7017SPing-Ke Shih ret); 1940e3ec7017SPing-Ke Shih return ret; 1941e3ec7017SPing-Ke Shih } 1942e3ec7017SPing-Ke Shih 1943e3ec7017SPing-Ke Shih ret = cca_ctrl_init(rtwdev, mac_idx); 1944e3ec7017SPing-Ke Shih if (ret) { 1945e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 1946e3ec7017SPing-Ke Shih ret); 1947e3ec7017SPing-Ke Shih return ret; 1948e3ec7017SPing-Ke Shih } 1949e3ec7017SPing-Ke Shih 1950e3ec7017SPing-Ke Shih ret = spatial_reuse_init(rtwdev, mac_idx); 1951e3ec7017SPing-Ke Shih if (ret) { 1952e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 1953e3ec7017SPing-Ke Shih mac_idx, ret); 1954e3ec7017SPing-Ke Shih return ret; 1955e3ec7017SPing-Ke Shih } 1956e3ec7017SPing-Ke Shih 1957e3ec7017SPing-Ke Shih ret = tmac_init(rtwdev, mac_idx); 1958e3ec7017SPing-Ke Shih if (ret) { 1959e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 1960e3ec7017SPing-Ke Shih return ret; 1961e3ec7017SPing-Ke Shih } 1962e3ec7017SPing-Ke Shih 1963e3ec7017SPing-Ke Shih ret = trxptcl_init(rtwdev, mac_idx); 1964e3ec7017SPing-Ke Shih if (ret) { 1965e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 1966e3ec7017SPing-Ke Shih return ret; 1967e3ec7017SPing-Ke Shih } 1968e3ec7017SPing-Ke Shih 1969e3ec7017SPing-Ke Shih ret = rmac_init(rtwdev, mac_idx); 1970e3ec7017SPing-Ke Shih if (ret) { 1971e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 1972e3ec7017SPing-Ke Shih return ret; 1973e3ec7017SPing-Ke Shih } 1974e3ec7017SPing-Ke Shih 1975e3ec7017SPing-Ke Shih ret = cmac_com_init(rtwdev, mac_idx); 1976e3ec7017SPing-Ke Shih if (ret) { 1977e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 1978e3ec7017SPing-Ke Shih return ret; 1979e3ec7017SPing-Ke Shih } 1980e3ec7017SPing-Ke Shih 1981e3ec7017SPing-Ke Shih ret = ptcl_init(rtwdev, mac_idx); 1982e3ec7017SPing-Ke Shih if (ret) { 1983e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 1984e3ec7017SPing-Ke Shih return ret; 1985e3ec7017SPing-Ke Shih } 1986e3ec7017SPing-Ke Shih 1987e3ec7017SPing-Ke Shih return ret; 1988e3ec7017SPing-Ke Shih } 1989e3ec7017SPing-Ke Shih 1990e3ec7017SPing-Ke Shih static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 1991e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info *c2h_info) 1992e3ec7017SPing-Ke Shih { 1993e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 1994e3ec7017SPing-Ke Shih u32 ret; 1995e3ec7017SPing-Ke Shih 1996e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 1997e3ec7017SPing-Ke Shih h2c_info.content_len = 0; 1998e3ec7017SPing-Ke Shih 1999e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2000e3ec7017SPing-Ke Shih if (ret) 2001e3ec7017SPing-Ke Shih return ret; 2002e3ec7017SPing-Ke Shih 2003e3ec7017SPing-Ke Shih if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2004e3ec7017SPing-Ke Shih return -EINVAL; 2005e3ec7017SPing-Ke Shih 2006e3ec7017SPing-Ke Shih return 0; 2007e3ec7017SPing-Ke Shih } 2008e3ec7017SPing-Ke Shih 2009e3ec7017SPing-Ke Shih int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2010e3ec7017SPing-Ke Shih { 2011e3ec7017SPing-Ke Shih struct rtw89_hal *hal = &rtwdev->hal; 2012e3ec7017SPing-Ke Shih const struct rtw89_chip_info *chip = rtwdev->chip; 2013e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 2014e3ec7017SPing-Ke Shih struct rtw89_c2h_phy_cap *cap = 2015e3ec7017SPing-Ke Shih (struct rtw89_c2h_phy_cap *)&c2h_info.c2hreg[0]; 2016e3ec7017SPing-Ke Shih u32 ret; 2017e3ec7017SPing-Ke Shih 2018e3ec7017SPing-Ke Shih ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2019e3ec7017SPing-Ke Shih if (ret) 2020e3ec7017SPing-Ke Shih return ret; 2021e3ec7017SPing-Ke Shih 2022e3ec7017SPing-Ke Shih hal->tx_nss = cap->tx_nss ? 2023e3ec7017SPing-Ke Shih min_t(u8, cap->tx_nss, chip->tx_nss) : chip->tx_nss; 2024e3ec7017SPing-Ke Shih hal->rx_nss = cap->rx_nss ? 2025e3ec7017SPing-Ke Shih min_t(u8, cap->rx_nss, chip->rx_nss) : chip->rx_nss; 2026e3ec7017SPing-Ke Shih 2027e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 2028e3ec7017SPing-Ke Shih "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2029e3ec7017SPing-Ke Shih hal->tx_nss, cap->tx_nss, chip->tx_nss, 2030e3ec7017SPing-Ke Shih hal->rx_nss, cap->rx_nss, chip->rx_nss); 2031e3ec7017SPing-Ke Shih 2032e3ec7017SPing-Ke Shih return 0; 2033e3ec7017SPing-Ke Shih } 2034e3ec7017SPing-Ke Shih 2035e3ec7017SPing-Ke Shih static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2036e3ec7017SPing-Ke Shih u16 tx_en_u16, u16 mask_u16) 2037e3ec7017SPing-Ke Shih { 2038e3ec7017SPing-Ke Shih u32 ret; 2039e3ec7017SPing-Ke Shih struct rtw89_mac_c2h_info c2h_info = {0}; 2040e3ec7017SPing-Ke Shih struct rtw89_mac_h2c_info h2c_info = {0}; 2041e3ec7017SPing-Ke Shih struct rtw89_h2creg_sch_tx_en *h2creg = 2042e3ec7017SPing-Ke Shih (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; 2043e3ec7017SPing-Ke Shih 2044e3ec7017SPing-Ke Shih h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2045e3ec7017SPing-Ke Shih h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; 2046e3ec7017SPing-Ke Shih h2creg->tx_en = tx_en_u16; 2047e3ec7017SPing-Ke Shih h2creg->mask = mask_u16; 2048e3ec7017SPing-Ke Shih h2creg->band = band; 2049e3ec7017SPing-Ke Shih 2050e3ec7017SPing-Ke Shih ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2051e3ec7017SPing-Ke Shih if (ret) 2052e3ec7017SPing-Ke Shih return ret; 2053e3ec7017SPing-Ke Shih 2054e3ec7017SPing-Ke Shih if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2055e3ec7017SPing-Ke Shih return -EINVAL; 2056e3ec7017SPing-Ke Shih 2057e3ec7017SPing-Ke Shih return 0; 2058e3ec7017SPing-Ke Shih } 2059e3ec7017SPing-Ke Shih 2060e3ec7017SPing-Ke Shih static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2061e3ec7017SPing-Ke Shih u16 tx_en, u16 tx_en_mask) 2062e3ec7017SPing-Ke Shih { 2063e3ec7017SPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); 2064e3ec7017SPing-Ke Shih u16 val; 2065e3ec7017SPing-Ke Shih int ret; 2066e3ec7017SPing-Ke Shih 2067e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2068e3ec7017SPing-Ke Shih if (ret) 2069e3ec7017SPing-Ke Shih return ret; 2070e3ec7017SPing-Ke Shih 2071e3ec7017SPing-Ke Shih if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2072e3ec7017SPing-Ke Shih return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2073e3ec7017SPing-Ke Shih tx_en, tx_en_mask); 2074e3ec7017SPing-Ke Shih 2075e3ec7017SPing-Ke Shih val = rtw89_read16(rtwdev, reg); 2076e3ec7017SPing-Ke Shih val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2077e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 2078e3ec7017SPing-Ke Shih 2079e3ec7017SPing-Ke Shih return 0; 2080e3ec7017SPing-Ke Shih } 2081e3ec7017SPing-Ke Shih 2082e3ec7017SPing-Ke Shih int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2083e3ec7017SPing-Ke Shih u16 *tx_en, enum rtw89_sch_tx_sel sel) 2084e3ec7017SPing-Ke Shih { 2085e3ec7017SPing-Ke Shih int ret; 2086e3ec7017SPing-Ke Shih 2087e3ec7017SPing-Ke Shih *tx_en = rtw89_read16(rtwdev, 2088e3ec7017SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); 2089e3ec7017SPing-Ke Shih 2090e3ec7017SPing-Ke Shih switch (sel) { 2091e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_ALL: 2092e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 0xffff); 2093e3ec7017SPing-Ke Shih if (ret) 2094e3ec7017SPing-Ke Shih return ret; 2095e3ec7017SPing-Ke Shih break; 2096e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_HIQ: 2097e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2098e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_HGQ); 2099e3ec7017SPing-Ke Shih if (ret) 2100e3ec7017SPing-Ke Shih return ret; 2101e3ec7017SPing-Ke Shih break; 2102e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MG0: 2103e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2104e3ec7017SPing-Ke Shih 0, B_AX_CTN_TXEN_MGQ); 2105e3ec7017SPing-Ke Shih if (ret) 2106e3ec7017SPing-Ke Shih return ret; 2107e3ec7017SPing-Ke Shih break; 2108e3ec7017SPing-Ke Shih case RTW89_SCH_TX_SEL_MACID: 2109e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 0xffff); 2110e3ec7017SPing-Ke Shih if (ret) 2111e3ec7017SPing-Ke Shih return ret; 2112e3ec7017SPing-Ke Shih break; 2113e3ec7017SPing-Ke Shih default: 2114e3ec7017SPing-Ke Shih return 0; 2115e3ec7017SPing-Ke Shih } 2116e3ec7017SPing-Ke Shih 2117e3ec7017SPing-Ke Shih return 0; 2118e3ec7017SPing-Ke Shih } 2119e3ec7017SPing-Ke Shih 2120e3ec7017SPing-Ke Shih int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u16 tx_en) 2121e3ec7017SPing-Ke Shih { 2122e3ec7017SPing-Ke Shih int ret; 2123e3ec7017SPing-Ke Shih 2124e3ec7017SPing-Ke Shih ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, 0xffff); 2125e3ec7017SPing-Ke Shih if (ret) 2126e3ec7017SPing-Ke Shih return ret; 2127e3ec7017SPing-Ke Shih 2128e3ec7017SPing-Ke Shih return 0; 2129e3ec7017SPing-Ke Shih } 2130e3ec7017SPing-Ke Shih 2131e3ec7017SPing-Ke Shih static u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, 2132e3ec7017SPing-Ke Shih bool wd) 2133e3ec7017SPing-Ke Shih { 2134e3ec7017SPing-Ke Shih u32 val, reg; 2135e3ec7017SPing-Ke Shih int ret; 2136e3ec7017SPing-Ke Shih 2137e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2138e3ec7017SPing-Ke Shih val = buf_len; 2139e3ec7017SPing-Ke Shih val |= B_AX_WD_BUF_REQ_EXEC; 2140e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2141e3ec7017SPing-Ke Shih 2142e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2143e3ec7017SPing-Ke Shih 2144e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2145e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 2146e3ec7017SPing-Ke Shih if (ret) 2147e3ec7017SPing-Ke Shih return 0xffff; 2148e3ec7017SPing-Ke Shih 2149e3ec7017SPing-Ke Shih return FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2150e3ec7017SPing-Ke Shih } 2151e3ec7017SPing-Ke Shih 2152e3ec7017SPing-Ke Shih static int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2153e3ec7017SPing-Ke Shih struct rtw89_cpuio_ctrl *ctrl_para, 2154e3ec7017SPing-Ke Shih bool wd) 2155e3ec7017SPing-Ke Shih { 2156e3ec7017SPing-Ke Shih u32 val, cmd_type, reg; 2157e3ec7017SPing-Ke Shih int ret; 2158e3ec7017SPing-Ke Shih 2159e3ec7017SPing-Ke Shih cmd_type = ctrl_para->cmd_type; 2160e3ec7017SPing-Ke Shih 2161e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2162e3ec7017SPing-Ke Shih val = 0; 2163e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->start_pktid, 2164e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2165e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->end_pktid, 2166e3ec7017SPing-Ke Shih B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2167e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2168e3ec7017SPing-Ke Shih 2169e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2170e3ec7017SPing-Ke Shih val = 0; 2171e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_pid, 2172e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_PID_MASK); 2173e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->src_qid, 2174e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_SRC_QID_MASK); 2175e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_pid, 2176e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_PID_MASK); 2177e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->dst_qid, 2178e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_DST_QID_MASK); 2179e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2180e3ec7017SPing-Ke Shih 2181e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2182e3ec7017SPing-Ke Shih val = 0; 2183e3ec7017SPing-Ke Shih val = u32_replace_bits(val, cmd_type, 2184e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_CMD_TYPE_MASK); 2185e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->macid, 2186e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_MACID_MASK); 2187e3ec7017SPing-Ke Shih val = u32_replace_bits(val, ctrl_para->pkt_num, 2188e3ec7017SPing-Ke Shih B_AX_CPUQ_OP_PKTNUM_MASK); 2189e3ec7017SPing-Ke Shih val |= B_AX_WD_CPUQ_OP_EXEC; 2190e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2191e3ec7017SPing-Ke Shih 2192e3ec7017SPing-Ke Shih reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2193e3ec7017SPing-Ke Shih 2194e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2195e3ec7017SPing-Ke Shih 1, 2000, false, rtwdev, reg); 2196e3ec7017SPing-Ke Shih if (ret) 2197e3ec7017SPing-Ke Shih return ret; 2198e3ec7017SPing-Ke Shih 2199e3ec7017SPing-Ke Shih if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2200e3ec7017SPing-Ke Shih cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2201e3ec7017SPing-Ke Shih ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2202e3ec7017SPing-Ke Shih 2203e3ec7017SPing-Ke Shih return 0; 2204e3ec7017SPing-Ke Shih } 2205e3ec7017SPing-Ke Shih 2206e3ec7017SPing-Ke Shih static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2207e3ec7017SPing-Ke Shih { 2208e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *cfg; 2209e3ec7017SPing-Ke Shih struct rtw89_cpuio_ctrl ctrl_para = {0}; 2210e3ec7017SPing-Ke Shih u16 pkt_id; 2211e3ec7017SPing-Ke Shih int ret; 2212e3ec7017SPing-Ke Shih 2213e3ec7017SPing-Ke Shih cfg = get_dle_mem_cfg(rtwdev, mode); 2214e3ec7017SPing-Ke Shih if (!cfg) { 2215e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2216e3ec7017SPing-Ke Shih return -EINVAL; 2217e3ec7017SPing-Ke Shih } 2218e3ec7017SPing-Ke Shih 2219e3ec7017SPing-Ke Shih if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { 2220e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2221e3ec7017SPing-Ke Shih return -EINVAL; 2222e3ec7017SPing-Ke Shih } 2223e3ec7017SPing-Ke Shih 2224e3ec7017SPing-Ke Shih dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2225e3ec7017SPing-Ke Shih 2226e3ec7017SPing-Ke Shih pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true); 2227e3ec7017SPing-Ke Shih if (pkt_id == 0xffff) { 2228e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2229e3ec7017SPing-Ke Shih return -ENOMEM; 2230e3ec7017SPing-Ke Shih } 2231e3ec7017SPing-Ke Shih 2232e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2233e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 2234e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 2235e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 2236e3ec7017SPing-Ke Shih ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2237e3ec7017SPing-Ke Shih ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2238e3ec7017SPing-Ke Shih ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2239e3ec7017SPing-Ke Shih if (ret) { 2240e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2241e3ec7017SPing-Ke Shih return -EFAULT; 2242e3ec7017SPing-Ke Shih } 2243e3ec7017SPing-Ke Shih 2244e3ec7017SPing-Ke Shih pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, false); 2245e3ec7017SPing-Ke Shih if (pkt_id == 0xffff) { 2246e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2247e3ec7017SPing-Ke Shih return -ENOMEM; 2248e3ec7017SPing-Ke Shih } 2249e3ec7017SPing-Ke Shih 2250e3ec7017SPing-Ke Shih ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2251e3ec7017SPing-Ke Shih ctrl_para.start_pktid = pkt_id; 2252e3ec7017SPing-Ke Shih ctrl_para.end_pktid = pkt_id; 2253e3ec7017SPing-Ke Shih ctrl_para.pkt_num = 0; 2254e3ec7017SPing-Ke Shih ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 2255e3ec7017SPing-Ke Shih ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 2256e3ec7017SPing-Ke Shih ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 2257e3ec7017SPing-Ke Shih if (ret) { 2258e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 2259e3ec7017SPing-Ke Shih return -EFAULT; 2260e3ec7017SPing-Ke Shih } 2261e3ec7017SPing-Ke Shih 2262e3ec7017SPing-Ke Shih return 0; 2263e3ec7017SPing-Ke Shih } 2264e3ec7017SPing-Ke Shih 2265e3ec7017SPing-Ke Shih static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 2266e3ec7017SPing-Ke Shih { 2267e3ec7017SPing-Ke Shih int ret; 2268e3ec7017SPing-Ke Shih u32 reg; 2269e3ec7017SPing-Ke Shih u8 val; 2270e3ec7017SPing-Ke Shih 2271e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2272e3ec7017SPing-Ke Shih if (ret) 2273e3ec7017SPing-Ke Shih return ret; 2274e3ec7017SPing-Ke Shih 2275e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); 2276e3ec7017SPing-Ke Shih 2277e3ec7017SPing-Ke Shih ret = read_poll_timeout(rtw89_read8, val, 2278e3ec7017SPing-Ke Shih (val & B_AX_PTCL_TX_ON_STAT) == 0, 2279e3ec7017SPing-Ke Shih SW_CVR_DUR_US, 2280e3ec7017SPing-Ke Shih SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 2281e3ec7017SPing-Ke Shih false, rtwdev, reg); 2282e3ec7017SPing-Ke Shih if (ret) 2283e3ec7017SPing-Ke Shih return ret; 2284e3ec7017SPing-Ke Shih 2285e3ec7017SPing-Ke Shih return 0; 2286e3ec7017SPing-Ke Shih } 2287e3ec7017SPing-Ke Shih 2288e3ec7017SPing-Ke Shih static int band1_enable(struct rtw89_dev *rtwdev) 2289e3ec7017SPing-Ke Shih { 2290e3ec7017SPing-Ke Shih int ret, i; 2291e3ec7017SPing-Ke Shih u32 sleep_bak[4] = {0}; 2292e3ec7017SPing-Ke Shih u32 pause_bak[4] = {0}; 2293e3ec7017SPing-Ke Shih u16 tx_en; 2294e3ec7017SPing-Ke Shih 2295e3ec7017SPing-Ke Shih ret = rtw89_mac_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 2296e3ec7017SPing-Ke Shih if (ret) { 2297e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 2298e3ec7017SPing-Ke Shih return ret; 2299e3ec7017SPing-Ke Shih } 2300e3ec7017SPing-Ke Shih 2301e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 2302e3ec7017SPing-Ke Shih sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 2303e3ec7017SPing-Ke Shih pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 2304e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 2305e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 2306e3ec7017SPing-Ke Shih } 2307e3ec7017SPing-Ke Shih 2308e3ec7017SPing-Ke Shih ret = band_idle_ck_b(rtwdev, 0); 2309e3ec7017SPing-Ke Shih if (ret) { 2310e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 2311e3ec7017SPing-Ke Shih return ret; 2312e3ec7017SPing-Ke Shih } 2313e3ec7017SPing-Ke Shih 2314e3ec7017SPing-Ke Shih ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 2315e3ec7017SPing-Ke Shih if (ret) { 2316e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 2317e3ec7017SPing-Ke Shih return ret; 2318e3ec7017SPing-Ke Shih } 2319e3ec7017SPing-Ke Shih 2320e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 2321e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 2322e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 2323e3ec7017SPing-Ke Shih } 2324e3ec7017SPing-Ke Shih 2325e3ec7017SPing-Ke Shih ret = rtw89_mac_resume_sch_tx(rtwdev, 0, tx_en); 2326e3ec7017SPing-Ke Shih if (ret) { 2327e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 2328e3ec7017SPing-Ke Shih return ret; 2329e3ec7017SPing-Ke Shih } 2330e3ec7017SPing-Ke Shih 2331e3ec7017SPing-Ke Shih ret = cmac_func_en(rtwdev, 1, true); 2332e3ec7017SPing-Ke Shih if (ret) { 2333e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 2334e3ec7017SPing-Ke Shih return ret; 2335e3ec7017SPing-Ke Shih } 2336e3ec7017SPing-Ke Shih 2337e3ec7017SPing-Ke Shih ret = cmac_init(rtwdev, 1); 2338e3ec7017SPing-Ke Shih if (ret) { 2339e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 2340e3ec7017SPing-Ke Shih return ret; 2341e3ec7017SPing-Ke Shih } 2342e3ec7017SPing-Ke Shih 2343e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 2344e3ec7017SPing-Ke Shih B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 2345e3ec7017SPing-Ke Shih 2346e3ec7017SPing-Ke Shih return 0; 2347e3ec7017SPing-Ke Shih } 2348e3ec7017SPing-Ke Shih 2349e3ec7017SPing-Ke Shih static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 2350e3ec7017SPing-Ke Shih enum rtw89_mac_hwmod_sel sel) 2351e3ec7017SPing-Ke Shih { 2352e3ec7017SPing-Ke Shih u32 reg, val; 2353e3ec7017SPing-Ke Shih int ret; 2354e3ec7017SPing-Ke Shih 2355e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 2356e3ec7017SPing-Ke Shih if (ret) { 2357e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 2358e3ec7017SPing-Ke Shih sel, mac_idx); 2359e3ec7017SPing-Ke Shih return ret; 2360e3ec7017SPing-Ke Shih } 2361e3ec7017SPing-Ke Shih 2362e3ec7017SPing-Ke Shih if (sel == RTW89_DMAC_SEL) { 2363e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR, 2364e3ec7017SPing-Ke Shih B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | 2365e3ec7017SPing-Ke Shih B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | 2366e3ec7017SPing-Ke Shih B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN); 2367e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 2368e3ec7017SPing-Ke Shih B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | 2369e3ec7017SPing-Ke Shih B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN); 2370e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 2371e3ec7017SPing-Ke Shih B_AX_HDT_PKT_FAIL_DBG_INT_EN | 2372e3ec7017SPing-Ke Shih B_AX_HDT_OFFSET_UNMATCH_INT_EN); 2373e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 2374e3ec7017SPing-Ke Shih B_AX_CPU_SHIFT_EN_ERR_INT_EN); 2375e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, 2376e3ec7017SPing-Ke Shih B_AX_PLE_GETNPG_STRPG_ERR_INT_EN); 2377e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, 2378e3ec7017SPing-Ke Shih B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN); 2379e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_HD0IMR, B_AX_WDT_PTFM_INT_EN); 2380e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR, 2381e3ec7017SPing-Ke Shih B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN); 2382e3ec7017SPing-Ke Shih } else if (sel == RTW89_CMAC_SEL) { 2383e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); 2384e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, 2385e3ec7017SPing-Ke Shih B_AX_SORT_NON_IDLE_ERR_INT_EN); 2386e3ec7017SPing-Ke Shih 2387e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_DLE_CTRL, mac_idx); 2388e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, 2389e3ec7017SPing-Ke Shih B_AX_NO_RESERVE_PAGE_ERR_IMR | 2390e3ec7017SPing-Ke Shih B_AX_RXDATA_FSM_HANG_ERROR_IMR); 2391e3ec7017SPing-Ke Shih 2392e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); 2393e3ec7017SPing-Ke Shih val = B_AX_F2PCMD_USER_ALLC_ERR_INT_EN | 2394e3ec7017SPing-Ke Shih B_AX_TX_RECORD_PKTID_ERR_INT_EN | 2395e3ec7017SPing-Ke Shih B_AX_FSM_TIMEOUT_ERR_INT_EN; 2396e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2397e3ec7017SPing-Ke Shih 2398e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_PHYINFO_ERR_IMR, mac_idx); 2399e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, 2400e3ec7017SPing-Ke Shih B_AX_PHY_TXON_TIMEOUT_INT_EN | 2401e3ec7017SPing-Ke Shih B_AX_CCK_CCA_TIMEOUT_INT_EN | 2402e3ec7017SPing-Ke Shih B_AX_OFDM_CCA_TIMEOUT_INT_EN | 2403e3ec7017SPing-Ke Shih B_AX_DATA_ON_TIMEOUT_INT_EN | 2404e3ec7017SPing-Ke Shih B_AX_STS_ON_TIMEOUT_INT_EN | 2405e3ec7017SPing-Ke Shih B_AX_CSI_ON_TIMEOUT_INT_EN); 2406e3ec7017SPing-Ke Shih 2407e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_RMAC_ERR_ISR, mac_idx); 2408e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2409e3ec7017SPing-Ke Shih val |= (B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN | 2410e3ec7017SPing-Ke Shih B_AX_RMAC_RX_TIMEOUT_INT_EN | 2411e3ec7017SPing-Ke Shih B_AX_RMAC_CSI_TIMEOUT_INT_EN); 2412e3ec7017SPing-Ke Shih val &= ~(B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN | 2413e3ec7017SPing-Ke Shih B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN | 2414e3ec7017SPing-Ke Shih B_AX_RMAC_CCA_TIMEOUT_INT_EN | 2415e3ec7017SPing-Ke Shih B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN); 2416e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2417e3ec7017SPing-Ke Shih } else { 2418e3ec7017SPing-Ke Shih return -EINVAL; 2419e3ec7017SPing-Ke Shih } 2420e3ec7017SPing-Ke Shih 2421e3ec7017SPing-Ke Shih return 0; 2422e3ec7017SPing-Ke Shih } 2423e3ec7017SPing-Ke Shih 2424e3ec7017SPing-Ke Shih static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 2425e3ec7017SPing-Ke Shih { 2426e3ec7017SPing-Ke Shih int ret = 0; 2427e3ec7017SPing-Ke Shih 2428e3ec7017SPing-Ke Shih if (enable) { 2429e3ec7017SPing-Ke Shih ret = band1_enable(rtwdev); 2430e3ec7017SPing-Ke Shih if (ret) { 2431e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 2432e3ec7017SPing-Ke Shih return ret; 2433e3ec7017SPing-Ke Shih } 2434e3ec7017SPing-Ke Shih 2435e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 2436e3ec7017SPing-Ke Shih if (ret) { 2437e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 2438e3ec7017SPing-Ke Shih return ret; 2439e3ec7017SPing-Ke Shih } 2440e3ec7017SPing-Ke Shih } else { 2441e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 2442e3ec7017SPing-Ke Shih return -EINVAL; 2443e3ec7017SPing-Ke Shih } 2444e3ec7017SPing-Ke Shih 2445e3ec7017SPing-Ke Shih return 0; 2446e3ec7017SPing-Ke Shih } 2447e3ec7017SPing-Ke Shih 2448e3ec7017SPing-Ke Shih static int set_host_rpr(struct rtw89_dev *rtwdev) 2449e3ec7017SPing-Ke Shih { 2450e3ec7017SPing-Ke Shih if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2451e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 2452e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 2453e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 2454e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 2455e3ec7017SPing-Ke Shih } else { 2456e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 2457e3ec7017SPing-Ke Shih B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 2458e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 2459e3ec7017SPing-Ke Shih B_AX_RLSRPT0_FLTR_MAP_MASK); 2460e3ec7017SPing-Ke Shih } 2461e3ec7017SPing-Ke Shih 2462e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 2463e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 2464e3ec7017SPing-Ke Shih 2465e3ec7017SPing-Ke Shih return 0; 2466e3ec7017SPing-Ke Shih } 2467e3ec7017SPing-Ke Shih 2468e3ec7017SPing-Ke Shih static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 2469e3ec7017SPing-Ke Shih { 2470e3ec7017SPing-Ke Shih enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 2471e3ec7017SPing-Ke Shih int ret; 2472e3ec7017SPing-Ke Shih 2473e3ec7017SPing-Ke Shih ret = dmac_init(rtwdev, 0); 2474e3ec7017SPing-Ke Shih if (ret) { 2475e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 2476e3ec7017SPing-Ke Shih return ret; 2477e3ec7017SPing-Ke Shih } 2478e3ec7017SPing-Ke Shih 2479e3ec7017SPing-Ke Shih ret = cmac_init(rtwdev, 0); 2480e3ec7017SPing-Ke Shih if (ret) { 2481e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 2482e3ec7017SPing-Ke Shih return ret; 2483e3ec7017SPing-Ke Shih } 2484e3ec7017SPing-Ke Shih 2485e3ec7017SPing-Ke Shih if (is_qta_dbcc(rtwdev, qta_mode)) { 2486e3ec7017SPing-Ke Shih ret = rtw89_mac_dbcc_enable(rtwdev, true); 2487e3ec7017SPing-Ke Shih if (ret) { 2488e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 2489e3ec7017SPing-Ke Shih return ret; 2490e3ec7017SPing-Ke Shih } 2491e3ec7017SPing-Ke Shih } 2492e3ec7017SPing-Ke Shih 2493e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2494e3ec7017SPing-Ke Shih if (ret) { 2495e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 2496e3ec7017SPing-Ke Shih return ret; 2497e3ec7017SPing-Ke Shih } 2498e3ec7017SPing-Ke Shih 2499e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 2500e3ec7017SPing-Ke Shih if (ret) { 2501e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 2502e3ec7017SPing-Ke Shih return ret; 2503e3ec7017SPing-Ke Shih } 2504e3ec7017SPing-Ke Shih 2505e3ec7017SPing-Ke Shih ret = set_host_rpr(rtwdev); 2506e3ec7017SPing-Ke Shih if (ret) { 2507e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 2508e3ec7017SPing-Ke Shih return ret; 2509e3ec7017SPing-Ke Shih } 2510e3ec7017SPing-Ke Shih 2511e3ec7017SPing-Ke Shih return 0; 2512e3ec7017SPing-Ke Shih } 2513e3ec7017SPing-Ke Shih 2514e3ec7017SPing-Ke Shih static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) 2515e3ec7017SPing-Ke Shih { 2516e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 2517e3ec7017SPing-Ke Shih 2518e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 2519e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 2520e3ec7017SPing-Ke Shih } 2521e3ec7017SPing-Ke Shih 2522e3ec7017SPing-Ke Shih static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, 2523e3ec7017SPing-Ke Shih bool dlfw) 2524e3ec7017SPing-Ke Shih { 2525e3ec7017SPing-Ke Shih u32 val; 2526e3ec7017SPing-Ke Shih int ret; 2527e3ec7017SPing-Ke Shih 2528e3ec7017SPing-Ke Shih if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 2529e3ec7017SPing-Ke Shih return -EFAULT; 2530e3ec7017SPing-Ke Shih 2531e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 2532e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 2533e3ec7017SPing-Ke Shih 2534e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 2535e3ec7017SPing-Ke Shih 2536e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 2537e3ec7017SPing-Ke Shih val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 2538e3ec7017SPing-Ke Shih val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 2539e3ec7017SPing-Ke Shih B_AX_WCPU_FWDL_STS_MASK); 2540e3ec7017SPing-Ke Shih 2541e3ec7017SPing-Ke Shih if (dlfw) 2542e3ec7017SPing-Ke Shih val |= B_AX_WCPU_FWDL_EN; 2543e3ec7017SPing-Ke Shih 2544e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 2545e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 2546e3ec7017SPing-Ke Shih boot_reason); 2547e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 2548e3ec7017SPing-Ke Shih 2549e3ec7017SPing-Ke Shih if (!dlfw) { 2550e3ec7017SPing-Ke Shih mdelay(5); 2551e3ec7017SPing-Ke Shih 2552e3ec7017SPing-Ke Shih ret = rtw89_fw_check_rdy(rtwdev); 2553e3ec7017SPing-Ke Shih if (ret) 2554e3ec7017SPing-Ke Shih return ret; 2555e3ec7017SPing-Ke Shih } 2556e3ec7017SPing-Ke Shih 2557e3ec7017SPing-Ke Shih return 0; 2558e3ec7017SPing-Ke Shih } 2559e3ec7017SPing-Ke Shih 2560e3ec7017SPing-Ke Shih static int rtw89_mac_fw_dl_pre_init(struct rtw89_dev *rtwdev) 2561e3ec7017SPing-Ke Shih { 2562e3ec7017SPing-Ke Shih u32 val; 2563e3ec7017SPing-Ke Shih int ret; 2564e3ec7017SPing-Ke Shih 2565e3ec7017SPing-Ke Shih val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 2566e3ec7017SPing-Ke Shih B_AX_PKT_BUF_EN; 2567e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 2568e3ec7017SPing-Ke Shih 2569e3ec7017SPing-Ke Shih val = B_AX_DISPATCHER_CLK_EN; 2570e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 2571e3ec7017SPing-Ke Shih 2572e3ec7017SPing-Ke Shih ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 2573e3ec7017SPing-Ke Shih if (ret) { 2574e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 2575e3ec7017SPing-Ke Shih return ret; 2576e3ec7017SPing-Ke Shih } 2577e3ec7017SPing-Ke Shih 2578e3ec7017SPing-Ke Shih ret = hfc_init(rtwdev, true, false, true); 2579e3ec7017SPing-Ke Shih if (ret) { 2580e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 2581e3ec7017SPing-Ke Shih return ret; 2582e3ec7017SPing-Ke Shih } 2583e3ec7017SPing-Ke Shih 2584e3ec7017SPing-Ke Shih return ret; 2585e3ec7017SPing-Ke Shih } 2586e3ec7017SPing-Ke Shih 2587e3ec7017SPing-Ke Shih static void rtw89_mac_hci_func_en(struct rtw89_dev *rtwdev) 2588e3ec7017SPing-Ke Shih { 2589e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_HCI_FUNC_EN, 2590e3ec7017SPing-Ke Shih B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 2591e3ec7017SPing-Ke Shih } 2592e3ec7017SPing-Ke Shih 2593e3ec7017SPing-Ke Shih void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2594e3ec7017SPing-Ke Shih { 2595e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2596e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2597e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 2598e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 2599e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 2600e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 2601e3ec7017SPing-Ke Shih } 2602e3ec7017SPing-Ke Shih 2603e3ec7017SPing-Ke Shih void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2604e3ec7017SPing-Ke Shih { 2605e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2606e3ec7017SPing-Ke Shih B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2607e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 2608e3ec7017SPing-Ke Shih B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 2609e3ec7017SPing-Ke Shih B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 2610e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 2611e3ec7017SPing-Ke Shih } 2612e3ec7017SPing-Ke Shih 2613e3ec7017SPing-Ke Shih int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) 2614e3ec7017SPing-Ke Shih { 2615e3ec7017SPing-Ke Shih int ret; 2616e3ec7017SPing-Ke Shih 2617e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 2618e3ec7017SPing-Ke Shih if (ret) { 2619e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 2620e3ec7017SPing-Ke Shih ret = rtw89_mac_power_switch(rtwdev, true); 2621e3ec7017SPing-Ke Shih if (ret) 2622e3ec7017SPing-Ke Shih return ret; 2623e3ec7017SPing-Ke Shih } 2624e3ec7017SPing-Ke Shih 2625e3ec7017SPing-Ke Shih rtw89_mac_hci_func_en(rtwdev); 2626e3ec7017SPing-Ke Shih 2627e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_pre_init) { 2628e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 2629e3ec7017SPing-Ke Shih if (ret) 2630e3ec7017SPing-Ke Shih return ret; 2631e3ec7017SPing-Ke Shih } 2632e3ec7017SPing-Ke Shih 2633e3ec7017SPing-Ke Shih ret = rtw89_mac_fw_dl_pre_init(rtwdev); 2634e3ec7017SPing-Ke Shih if (ret) 2635e3ec7017SPing-Ke Shih return ret; 2636e3ec7017SPing-Ke Shih 2637e3ec7017SPing-Ke Shih rtw89_mac_disable_cpu(rtwdev); 2638e3ec7017SPing-Ke Shih ret = rtw89_mac_enable_cpu(rtwdev, 0, true); 2639e3ec7017SPing-Ke Shih if (ret) 2640e3ec7017SPing-Ke Shih return ret; 2641e3ec7017SPing-Ke Shih 2642e3ec7017SPing-Ke Shih ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); 2643e3ec7017SPing-Ke Shih if (ret) 2644e3ec7017SPing-Ke Shih return ret; 2645e3ec7017SPing-Ke Shih 2646e3ec7017SPing-Ke Shih return 0; 2647e3ec7017SPing-Ke Shih } 2648e3ec7017SPing-Ke Shih 2649e3ec7017SPing-Ke Shih int rtw89_mac_init(struct rtw89_dev *rtwdev) 2650e3ec7017SPing-Ke Shih { 2651e3ec7017SPing-Ke Shih int ret; 2652e3ec7017SPing-Ke Shih 2653e3ec7017SPing-Ke Shih ret = rtw89_mac_partial_init(rtwdev); 2654e3ec7017SPing-Ke Shih if (ret) 2655e3ec7017SPing-Ke Shih goto fail; 2656e3ec7017SPing-Ke Shih 2657e3ec7017SPing-Ke Shih rtw89_mac_enable_bb_rf(rtwdev); 2658e3ec7017SPing-Ke Shih 2659e3ec7017SPing-Ke Shih ret = rtw89_mac_sys_init(rtwdev); 2660e3ec7017SPing-Ke Shih if (ret) 2661e3ec7017SPing-Ke Shih goto fail; 2662e3ec7017SPing-Ke Shih 2663e3ec7017SPing-Ke Shih ret = rtw89_mac_trx_init(rtwdev); 2664e3ec7017SPing-Ke Shih if (ret) 2665e3ec7017SPing-Ke Shih goto fail; 2666e3ec7017SPing-Ke Shih 2667e3ec7017SPing-Ke Shih if (rtwdev->hci.ops->mac_post_init) { 2668e3ec7017SPing-Ke Shih ret = rtwdev->hci.ops->mac_post_init(rtwdev); 2669e3ec7017SPing-Ke Shih if (ret) 2670e3ec7017SPing-Ke Shih goto fail; 2671e3ec7017SPing-Ke Shih } 2672e3ec7017SPing-Ke Shih 2673e3ec7017SPing-Ke Shih rtw89_fw_send_all_early_h2c(rtwdev); 2674e3ec7017SPing-Ke Shih rtw89_fw_h2c_set_ofld_cfg(rtwdev); 2675e3ec7017SPing-Ke Shih 2676e3ec7017SPing-Ke Shih return ret; 2677e3ec7017SPing-Ke Shih fail: 2678e3ec7017SPing-Ke Shih rtw89_mac_power_switch(rtwdev, false); 2679e3ec7017SPing-Ke Shih 2680e3ec7017SPing-Ke Shih return ret; 2681e3ec7017SPing-Ke Shih } 2682e3ec7017SPing-Ke Shih 2683e3ec7017SPing-Ke Shih static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 2684e3ec7017SPing-Ke Shih { 2685e3ec7017SPing-Ke Shih u8 i; 2686e3ec7017SPing-Ke Shih 2687e3ec7017SPing-Ke Shih for (i = 0; i < 4; i++) { 2688e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 2689e3ec7017SPing-Ke Shih DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 2690e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 2691e3ec7017SPing-Ke Shih } 2692e3ec7017SPing-Ke Shih } 2693e3ec7017SPing-Ke Shih 2694e3ec7017SPing-Ke Shih static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 2695e3ec7017SPing-Ke Shih { 2696e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 2697e3ec7017SPing-Ke Shih CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 2698e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 2699e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 2700e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 2701e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 2702e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 2703e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 2704e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 2705e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 2706e3ec7017SPing-Ke Shih } 2707e3ec7017SPing-Ke Shih 2708e3ec7017SPing-Ke Shih static int rtw89_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 2709e3ec7017SPing-Ke Shih { 2710e3ec7017SPing-Ke Shih u8 sh = FIELD_GET(GENMASK(4, 0), macid); 2711e3ec7017SPing-Ke Shih u8 grp = macid >> 5; 2712e3ec7017SPing-Ke Shih int ret; 2713e3ec7017SPing-Ke Shih 2714e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 2715e3ec7017SPing-Ke Shih if (ret) 2716e3ec7017SPing-Ke Shih return ret; 2717e3ec7017SPing-Ke Shih 2718e3ec7017SPing-Ke Shih rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 2719e3ec7017SPing-Ke Shih 2720e3ec7017SPing-Ke Shih return 0; 2721e3ec7017SPing-Ke Shih } 2722e3ec7017SPing-Ke Shih 2723e3ec7017SPing-Ke Shih static const struct rtw89_port_reg rtw_port_base = { 2724e3ec7017SPing-Ke Shih .port_cfg = R_AX_PORT_CFG_P0, 2725e3ec7017SPing-Ke Shih .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 2726e3ec7017SPing-Ke Shih .bcn_area = R_AX_BCN_AREA_P0, 2727e3ec7017SPing-Ke Shih .bcn_early = R_AX_BCNERLYINT_CFG_P0, 2728e3ec7017SPing-Ke Shih .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 2729e3ec7017SPing-Ke Shih .tbtt_agg = R_AX_TBTT_AGG_P0, 2730e3ec7017SPing-Ke Shih .bcn_space = R_AX_BCN_SPACE_CFG_P0, 2731e3ec7017SPing-Ke Shih .bcn_forcetx = R_AX_BCN_FORCETX_P0, 2732e3ec7017SPing-Ke Shih .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 2733e3ec7017SPing-Ke Shih .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 2734e3ec7017SPing-Ke Shih .dtim_ctrl = R_AX_DTIM_CTRL_P0, 2735e3ec7017SPing-Ke Shih .tbtt_shift = R_AX_TBTT_SHIFT_P0, 2736e3ec7017SPing-Ke Shih .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 2737e3ec7017SPing-Ke Shih .tsftr_l = R_AX_TSFTR_LOW_P0, 2738e3ec7017SPing-Ke Shih .tsftr_h = R_AX_TSFTR_HIGH_P0 2739e3ec7017SPing-Ke Shih }; 2740e3ec7017SPing-Ke Shih 2741e3ec7017SPing-Ke Shih #define BCN_INTERVAL 100 2742e3ec7017SPing-Ke Shih #define BCN_ERLY_DEF 160 2743e3ec7017SPing-Ke Shih #define BCN_SETUP_DEF 2 2744e3ec7017SPing-Ke Shih #define BCN_HOLD_DEF 200 2745e3ec7017SPing-Ke Shih #define BCN_MASK_DEF 0 2746e3ec7017SPing-Ke Shih #define TBTT_ERLY_DEF 5 2747e3ec7017SPing-Ke Shih #define BCN_SET_UNIT 32 2748e3ec7017SPing-Ke Shih #define BCN_ERLY_SET_DLY (10 * 2) 2749e3ec7017SPing-Ke Shih 2750e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 2751e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2752e3ec7017SPing-Ke Shih { 2753e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2754e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2755e3ec7017SPing-Ke Shih 2756e3ec7017SPing-Ke Shih if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 2757e3ec7017SPing-Ke Shih return; 2758e3ec7017SPing-Ke Shih 2759e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 2760e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 2761e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 2762e3ec7017SPing-Ke Shih rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 2763e3ec7017SPing-Ke Shih 2764e3ec7017SPing-Ke Shih msleep(vif->bss_conf.beacon_int + 1); 2765e3ec7017SPing-Ke Shih 2766e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 2767e3ec7017SPing-Ke Shih B_AX_BRK_SETUP); 2768e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 2769e3ec7017SPing-Ke Shih rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 2770e3ec7017SPing-Ke Shih } 2771e3ec7017SPing-Ke Shih 2772e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 2773e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 2774e3ec7017SPing-Ke Shih { 2775e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2776e3ec7017SPing-Ke Shih 2777e3ec7017SPing-Ke Shih if (en) 2778e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 2779e3ec7017SPing-Ke Shih else 2780e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 2781e3ec7017SPing-Ke Shih } 2782e3ec7017SPing-Ke Shih 2783e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 2784e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 2785e3ec7017SPing-Ke Shih { 2786e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2787e3ec7017SPing-Ke Shih 2788e3ec7017SPing-Ke Shih if (en) 2789e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 2790e3ec7017SPing-Ke Shih else 2791e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 2792e3ec7017SPing-Ke Shih } 2793e3ec7017SPing-Ke Shih 2794e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 2795e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2796e3ec7017SPing-Ke Shih { 2797e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2798e3ec7017SPing-Ke Shih 2799e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 2800e3ec7017SPing-Ke Shih rtwvif->net_type); 2801e3ec7017SPing-Ke Shih } 2802e3ec7017SPing-Ke Shih 2803e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 2804e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2805e3ec7017SPing-Ke Shih { 2806e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2807e3ec7017SPing-Ke Shih bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 2808e3ec7017SPing-Ke Shih u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 2809e3ec7017SPing-Ke Shih 2810e3ec7017SPing-Ke Shih if (en) 2811e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 2812e3ec7017SPing-Ke Shih else 2813e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 2814e3ec7017SPing-Ke Shih } 2815e3ec7017SPing-Ke Shih 2816e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 2817e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2818e3ec7017SPing-Ke Shih { 2819e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2820e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 2821e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 2822e3ec7017SPing-Ke Shih u32 bit = B_AX_RX_BSSID_FIT_EN; 2823e3ec7017SPing-Ke Shih 2824e3ec7017SPing-Ke Shih if (en) 2825e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 2826e3ec7017SPing-Ke Shih else 2827e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 2828e3ec7017SPing-Ke Shih } 2829e3ec7017SPing-Ke Shih 2830e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 2831e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2832e3ec7017SPing-Ke Shih { 2833e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2834e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 2835e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 2836e3ec7017SPing-Ke Shih 2837e3ec7017SPing-Ke Shih if (en) 2838e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 2839e3ec7017SPing-Ke Shih else 2840e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 2841e3ec7017SPing-Ke Shih } 2842e3ec7017SPing-Ke Shih 2843e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 2844e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2845e3ec7017SPing-Ke Shih { 2846e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2847e3ec7017SPing-Ke Shih bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 2848e3ec7017SPing-Ke Shih rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 2849e3ec7017SPing-Ke Shih 2850e3ec7017SPing-Ke Shih if (en) 2851e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 2852e3ec7017SPing-Ke Shih else 2853e3ec7017SPing-Ke Shih rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 2854e3ec7017SPing-Ke Shih } 2855e3ec7017SPing-Ke Shih 2856e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 2857e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2858e3ec7017SPing-Ke Shih { 2859e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2860e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2861e3ec7017SPing-Ke Shih u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 2862e3ec7017SPing-Ke Shih 2863e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 2864e3ec7017SPing-Ke Shih bcn_int); 2865e3ec7017SPing-Ke Shih } 2866e3ec7017SPing-Ke Shih 2867e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 2868e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2869e3ec7017SPing-Ke Shih { 2870e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2871e3ec7017SPing-Ke Shih 2872e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 2873e3ec7017SPing-Ke Shih B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 2874e3ec7017SPing-Ke Shih } 2875e3ec7017SPing-Ke Shih 2876e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 2877e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2878e3ec7017SPing-Ke Shih { 2879e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2880e3ec7017SPing-Ke Shih 2881e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 2882e3ec7017SPing-Ke Shih B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 2883e3ec7017SPing-Ke Shih } 2884e3ec7017SPing-Ke Shih 2885e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 2886e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2887e3ec7017SPing-Ke Shih { 2888e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2889e3ec7017SPing-Ke Shih 2890e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 2891e3ec7017SPing-Ke Shih B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 2892e3ec7017SPing-Ke Shih } 2893e3ec7017SPing-Ke Shih 2894e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 2895e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2896e3ec7017SPing-Ke Shih { 2897e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2898e3ec7017SPing-Ke Shih 2899e3ec7017SPing-Ke Shih rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 2900e3ec7017SPing-Ke Shih B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 2901e3ec7017SPing-Ke Shih } 2902e3ec7017SPing-Ke Shih 2903e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 2904e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2905e3ec7017SPing-Ke Shih { 2906e3ec7017SPing-Ke Shih struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2907e3ec7017SPing-Ke Shih static const u32 masks[RTW89_PORT_NUM] = { 2908e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 2909e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 2910e3ec7017SPing-Ke Shih B_AX_BSS_COLOB_AX_PORT_4_MASK, 2911e3ec7017SPing-Ke Shih }; 2912e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 2913e3ec7017SPing-Ke Shih u32 reg_base; 2914e3ec7017SPing-Ke Shih u32 reg; 2915e3ec7017SPing-Ke Shih u8 bss_color; 2916e3ec7017SPing-Ke Shih 2917e3ec7017SPing-Ke Shih bss_color = vif->bss_conf.he_bss_color.color; 2918e3ec7017SPing-Ke Shih reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; 2919e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); 2920e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 2921e3ec7017SPing-Ke Shih } 2922e3ec7017SPing-Ke Shih 2923e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 2924e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2925e3ec7017SPing-Ke Shih { 2926e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 2927e3ec7017SPing-Ke Shih u32 reg; 2928e3ec7017SPing-Ke Shih 2929e3ec7017SPing-Ke Shih if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 2930e3ec7017SPing-Ke Shih return; 2931e3ec7017SPing-Ke Shih 2932e3ec7017SPing-Ke Shih if (port == 0) { 2933e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); 2934e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 2935e3ec7017SPing-Ke Shih } 2936e3ec7017SPing-Ke Shih } 2937e3ec7017SPing-Ke Shih 2938e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 2939e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2940e3ec7017SPing-Ke Shih { 2941e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 2942e3ec7017SPing-Ke Shih u32 reg; 2943e3ec7017SPing-Ke Shih u32 val; 2944e3ec7017SPing-Ke Shih 2945e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); 2946e3ec7017SPing-Ke Shih val = rtw89_read32(rtwdev, reg); 2947e3ec7017SPing-Ke Shih val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 2948e3ec7017SPing-Ke Shih if (port == 0) 2949e3ec7017SPing-Ke Shih val &= ~BIT(0); 2950e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val); 2951e3ec7017SPing-Ke Shih } 2952e3ec7017SPing-Ke Shih 2953e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 2954e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2955e3ec7017SPing-Ke Shih { 2956e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2957e3ec7017SPing-Ke Shih 2958e3ec7017SPing-Ke Shih rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN); 2959e3ec7017SPing-Ke Shih } 2960e3ec7017SPing-Ke Shih 2961e3ec7017SPing-Ke Shih static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 2962e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif) 2963e3ec7017SPing-Ke Shih { 2964e3ec7017SPing-Ke Shih const struct rtw89_port_reg *p = &rtw_port_base; 2965e3ec7017SPing-Ke Shih 2966e3ec7017SPing-Ke Shih rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 2967e3ec7017SPing-Ke Shih BCN_ERLY_DEF); 2968e3ec7017SPing-Ke Shih } 2969e3ec7017SPing-Ke Shih 2970e3ec7017SPing-Ke Shih int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2971e3ec7017SPing-Ke Shih { 2972e3ec7017SPing-Ke Shih int ret; 2973e3ec7017SPing-Ke Shih 2974e3ec7017SPing-Ke Shih ret = rtw89_mac_port_update(rtwdev, rtwvif); 2975e3ec7017SPing-Ke Shih if (ret) 2976e3ec7017SPing-Ke Shih return ret; 2977e3ec7017SPing-Ke Shih 2978e3ec7017SPing-Ke Shih rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 2979e3ec7017SPing-Ke Shih rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 2980e3ec7017SPing-Ke Shih 2981e3ec7017SPing-Ke Shih ret = rtw89_set_macid_pause(rtwdev, rtwvif->mac_id, false); 2982e3ec7017SPing-Ke Shih if (ret) 2983e3ec7017SPing-Ke Shih return ret; 2984e3ec7017SPing-Ke Shih 2985e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_vif_maintain(rtwdev, rtwvif, RTW89_VIF_CREATE); 2986e3ec7017SPing-Ke Shih if (ret) 2987e3ec7017SPing-Ke Shih return ret; 2988e3ec7017SPing-Ke Shih 2989e3ec7017SPing-Ke Shih ret = rtw89_cam_init(rtwdev, rtwvif); 2990e3ec7017SPing-Ke Shih if (ret) 2991e3ec7017SPing-Ke Shih return ret; 2992e3ec7017SPing-Ke Shih 2993e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); 2994e3ec7017SPing-Ke Shih if (ret) 2995e3ec7017SPing-Ke Shih return ret; 2996e3ec7017SPing-Ke Shih 2997e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif->mac_id); 2998e3ec7017SPing-Ke Shih if (ret) 2999e3ec7017SPing-Ke Shih return ret; 3000e3ec7017SPing-Ke Shih 3001e3ec7017SPing-Ke Shih return 0; 3002e3ec7017SPing-Ke Shih } 3003e3ec7017SPing-Ke Shih 3004e3ec7017SPing-Ke Shih int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3005e3ec7017SPing-Ke Shih { 3006e3ec7017SPing-Ke Shih int ret; 3007e3ec7017SPing-Ke Shih 3008e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_vif_maintain(rtwdev, rtwvif, RTW89_VIF_REMOVE); 3009e3ec7017SPing-Ke Shih if (ret) 3010e3ec7017SPing-Ke Shih return ret; 3011e3ec7017SPing-Ke Shih 3012e3ec7017SPing-Ke Shih rtw89_cam_deinit(rtwdev, rtwvif); 3013e3ec7017SPing-Ke Shih 3014e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); 3015e3ec7017SPing-Ke Shih if (ret) 3016e3ec7017SPing-Ke Shih return ret; 3017e3ec7017SPing-Ke Shih 3018e3ec7017SPing-Ke Shih return 0; 3019e3ec7017SPing-Ke Shih } 3020e3ec7017SPing-Ke Shih 3021e3ec7017SPing-Ke Shih int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3022e3ec7017SPing-Ke Shih { 3023e3ec7017SPing-Ke Shih u8 port = rtwvif->port; 3024e3ec7017SPing-Ke Shih 3025e3ec7017SPing-Ke Shih if (port >= RTW89_PORT_NUM) 3026e3ec7017SPing-Ke Shih return -EINVAL; 3027e3ec7017SPing-Ke Shih 3028e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 3029e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 3030e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 3031e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 3032e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 3033e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 3034e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 3035e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 3036e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 3037e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 3038e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 3039e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 3040e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 3041e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 3042e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 3043e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 3044e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_func_en(rtwdev, rtwvif); 3045e3ec7017SPing-Ke Shih fsleep(BCN_ERLY_SET_DLY); 3046e3ec7017SPing-Ke Shih rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 3047e3ec7017SPing-Ke Shih 3048e3ec7017SPing-Ke Shih return 0; 3049e3ec7017SPing-Ke Shih } 3050e3ec7017SPing-Ke Shih 3051e3ec7017SPing-Ke Shih int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3052e3ec7017SPing-Ke Shih { 3053e3ec7017SPing-Ke Shih int ret; 3054e3ec7017SPing-Ke Shih 3055e3ec7017SPing-Ke Shih rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 3056e3ec7017SPing-Ke Shih RTW89_MAX_MAC_ID_NUM); 3057e3ec7017SPing-Ke Shih if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 3058e3ec7017SPing-Ke Shih return -ENOSPC; 3059e3ec7017SPing-Ke Shih 3060e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_init(rtwdev, rtwvif); 3061e3ec7017SPing-Ke Shih if (ret) 3062e3ec7017SPing-Ke Shih goto release_mac_id; 3063e3ec7017SPing-Ke Shih 3064e3ec7017SPing-Ke Shih return 0; 3065e3ec7017SPing-Ke Shih 3066e3ec7017SPing-Ke Shih release_mac_id: 3067e3ec7017SPing-Ke Shih rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 3068e3ec7017SPing-Ke Shih 3069e3ec7017SPing-Ke Shih return ret; 3070e3ec7017SPing-Ke Shih } 3071e3ec7017SPing-Ke Shih 3072e3ec7017SPing-Ke Shih int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3073e3ec7017SPing-Ke Shih { 3074e3ec7017SPing-Ke Shih int ret; 3075e3ec7017SPing-Ke Shih 3076e3ec7017SPing-Ke Shih ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 3077e3ec7017SPing-Ke Shih rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 3078e3ec7017SPing-Ke Shih 3079e3ec7017SPing-Ke Shih return ret; 3080e3ec7017SPing-Ke Shih } 3081e3ec7017SPing-Ke Shih 3082e3ec7017SPing-Ke Shih static void 3083e3ec7017SPing-Ke Shih rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3084e3ec7017SPing-Ke Shih { 3085e3ec7017SPing-Ke Shih } 3086e3ec7017SPing-Ke Shih 3087e3ec7017SPing-Ke Shih static void 3088e3ec7017SPing-Ke Shih rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3089e3ec7017SPing-Ke Shih { 3090e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 3091e3ec7017SPing-Ke Shih "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 3092e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 3093e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 3094e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 3095e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 3096e3ec7017SPing-Ke Shih } 3097e3ec7017SPing-Ke Shih 3098e3ec7017SPing-Ke Shih static void 3099e3ec7017SPing-Ke Shih rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3100e3ec7017SPing-Ke Shih { 3101e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_FW, 3102e3ec7017SPing-Ke Shih "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 3103e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data), 3104e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data), 3105e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data), 3106e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data), 3107e3ec7017SPing-Ke Shih RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data)); 3108e3ec7017SPing-Ke Shih } 3109e3ec7017SPing-Ke Shih 3110e3ec7017SPing-Ke Shih static void 3111e3ec7017SPing-Ke Shih rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3112e3ec7017SPing-Ke Shih { 3113e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), 3114e3ec7017SPing-Ke Shih RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); 3115e3ec7017SPing-Ke Shih } 3116e3ec7017SPing-Ke Shih 3117e3ec7017SPing-Ke Shih static 3118e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 3119e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 3120e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 3121e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 3122e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = NULL, 3123e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 3124e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 3125e3ec7017SPing-Ke Shih }; 3126e3ec7017SPing-Ke Shih 3127e3ec7017SPing-Ke Shih static 3128e3ec7017SPing-Ke Shih void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 3129e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = { 3130e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 3131e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 3132e3ec7017SPing-Ke Shih [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 3133e3ec7017SPing-Ke Shih }; 3134e3ec7017SPing-Ke Shih 3135e3ec7017SPing-Ke Shih void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3136e3ec7017SPing-Ke Shih u32 len, u8 class, u8 func) 3137e3ec7017SPing-Ke Shih { 3138e3ec7017SPing-Ke Shih void (*handler)(struct rtw89_dev *rtwdev, 3139e3ec7017SPing-Ke Shih struct sk_buff *c2h, u32 len) = NULL; 3140e3ec7017SPing-Ke Shih 3141e3ec7017SPing-Ke Shih switch (class) { 3142e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_INFO: 3143e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 3144e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_info_handler[func]; 3145e3ec7017SPing-Ke Shih break; 3146e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_OFLD: 3147e3ec7017SPing-Ke Shih if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 3148e3ec7017SPing-Ke Shih handler = rtw89_mac_c2h_ofld_handler[func]; 3149e3ec7017SPing-Ke Shih break; 3150e3ec7017SPing-Ke Shih case RTW89_MAC_C2H_CLASS_FWDBG: 3151e3ec7017SPing-Ke Shih return; 3152e3ec7017SPing-Ke Shih default: 3153e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d not support\n", class); 3154e3ec7017SPing-Ke Shih return; 3155e3ec7017SPing-Ke Shih } 3156e3ec7017SPing-Ke Shih if (!handler) { 3157e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 3158e3ec7017SPing-Ke Shih func); 3159e3ec7017SPing-Ke Shih return; 3160e3ec7017SPing-Ke Shih } 3161e3ec7017SPing-Ke Shih handler(rtwdev, skb, len); 3162e3ec7017SPing-Ke Shih } 3163e3ec7017SPing-Ke Shih 3164e3ec7017SPing-Ke Shih bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 3165e3ec7017SPing-Ke Shih enum rtw89_phy_idx phy_idx, 3166e3ec7017SPing-Ke Shih u32 reg_base, u32 *cr) 3167e3ec7017SPing-Ke Shih { 3168e3ec7017SPing-Ke Shih const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 3169e3ec7017SPing-Ke Shih enum rtw89_qta_mode mode = dle_mem->mode; 3170e3ec7017SPing-Ke Shih u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); 3171e3ec7017SPing-Ke Shih 3172e3ec7017SPing-Ke Shih if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { 3173e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 3174e3ec7017SPing-Ke Shih addr); 3175e3ec7017SPing-Ke Shih goto error; 3176e3ec7017SPing-Ke Shih } 3177e3ec7017SPing-Ke Shih 3178e3ec7017SPing-Ke Shih if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) 3179e3ec7017SPing-Ke Shih if (mode == RTW89_QTA_SCC) { 3180e3ec7017SPing-Ke Shih rtw89_err(rtwdev, 3181e3ec7017SPing-Ke Shih "[TXPWR] addr=0x%x but hw not enable\n", 3182e3ec7017SPing-Ke Shih addr); 3183e3ec7017SPing-Ke Shih goto error; 3184e3ec7017SPing-Ke Shih } 3185e3ec7017SPing-Ke Shih 3186e3ec7017SPing-Ke Shih *cr = addr; 3187e3ec7017SPing-Ke Shih return true; 3188e3ec7017SPing-Ke Shih 3189e3ec7017SPing-Ke Shih error: 3190e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 3191e3ec7017SPing-Ke Shih addr, phy_idx); 3192e3ec7017SPing-Ke Shih 3193e3ec7017SPing-Ke Shih return false; 3194e3ec7017SPing-Ke Shih } 3195e3ec7017SPing-Ke Shih 3196e3ec7017SPing-Ke Shih int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 3197e3ec7017SPing-Ke Shih { 3198e3ec7017SPing-Ke Shih u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); 3199e3ec7017SPing-Ke Shih int ret = 0; 3200e3ec7017SPing-Ke Shih 3201e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3202e3ec7017SPing-Ke Shih if (ret) 3203e3ec7017SPing-Ke Shih return ret; 3204e3ec7017SPing-Ke Shih 3205e3ec7017SPing-Ke Shih if (!enable) { 3206e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 3207e3ec7017SPing-Ke Shih return ret; 3208e3ec7017SPing-Ke Shih } 3209e3ec7017SPing-Ke Shih 3210e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 3211e3ec7017SPing-Ke Shih B_AX_APP_MAC_INFO_RPT | 3212e3ec7017SPing-Ke Shih B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 3213e3ec7017SPing-Ke Shih B_AX_PPDU_STAT_RPT_CRC32); 3214e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 3215e3ec7017SPing-Ke Shih RTW89_PRPT_DEST_HOST); 3216e3ec7017SPing-Ke Shih 3217e3ec7017SPing-Ke Shih return ret; 3218e3ec7017SPing-Ke Shih } 3219e3ec7017SPing-Ke Shih 3220e3ec7017SPing-Ke Shih void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 3221e3ec7017SPing-Ke Shih { 3222e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_SH 5 3223e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_SH 4 3224e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_MAX 255 3225e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_MAX 255 3226e3ec7017SPing-Ke Shih #define MAC_AX_TIME_TH_DEF 88 3227e3ec7017SPing-Ke Shih #define MAC_AX_LEN_TH_DEF 4080 3228e3ec7017SPing-Ke Shih struct ieee80211_hw *hw = rtwdev->hw; 3229e3ec7017SPing-Ke Shih u32 rts_threshold = hw->wiphy->rts_threshold; 3230e3ec7017SPing-Ke Shih u32 time_th, len_th; 3231e3ec7017SPing-Ke Shih u32 reg; 3232e3ec7017SPing-Ke Shih 3233e3ec7017SPing-Ke Shih if (rts_threshold == (u32)-1) { 3234e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_DEF; 3235e3ec7017SPing-Ke Shih len_th = MAC_AX_LEN_TH_DEF; 3236e3ec7017SPing-Ke Shih } else { 3237e3ec7017SPing-Ke Shih time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 3238e3ec7017SPing-Ke Shih len_th = rts_threshold; 3239e3ec7017SPing-Ke Shih } 3240e3ec7017SPing-Ke Shih 3241e3ec7017SPing-Ke Shih time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 3242e3ec7017SPing-Ke Shih len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 3243e3ec7017SPing-Ke Shih 3244e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); 3245e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 3246e3ec7017SPing-Ke Shih rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 3247e3ec7017SPing-Ke Shih } 3248e3ec7017SPing-Ke Shih 3249e3ec7017SPing-Ke Shih void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 3250e3ec7017SPing-Ke Shih { 3251e3ec7017SPing-Ke Shih bool empty; 3252e3ec7017SPing-Ke Shih int ret; 3253e3ec7017SPing-Ke Shih 3254e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3255e3ec7017SPing-Ke Shih return; 3256e3ec7017SPing-Ke Shih 3257e3ec7017SPing-Ke Shih ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 3258e3ec7017SPing-Ke Shih 10000, 200000, false, rtwdev); 3259e3ec7017SPing-Ke Shih if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 3260e3ec7017SPing-Ke Shih rtw89_info(rtwdev, "timed out to flush queues\n"); 3261e3ec7017SPing-Ke Shih } 3262e3ec7017SPing-Ke Shih 3263e3ec7017SPing-Ke Shih int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 3264e3ec7017SPing-Ke Shih { 3265e3ec7017SPing-Ke Shih u8 val; 3266e3ec7017SPing-Ke Shih u16 val16; 3267e3ec7017SPing-Ke Shih u32 val32; 3268e3ec7017SPing-Ke Shih int ret; 3269e3ec7017SPing-Ke Shih 3270e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 3271e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 3272e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 3273e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 3274e3ec7017SPing-Ke Shih rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 3275e3ec7017SPing-Ke Shih rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 3276e3ec7017SPing-Ke Shih 3277e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 3278e3ec7017SPing-Ke Shih val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 3279e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 3280e3ec7017SPing-Ke Shih 3281e3ec7017SPing-Ke Shih ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 3282e3ec7017SPing-Ke Shih if (ret) { 3283e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 3284e3ec7017SPing-Ke Shih return ret; 3285e3ec7017SPing-Ke Shih } 3286e3ec7017SPing-Ke Shih val32 = val32 & B_AX_WL_RX_CTRL; 3287e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 3288e3ec7017SPing-Ke Shih if (ret) { 3289e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 3290e3ec7017SPing-Ke Shih return ret; 3291e3ec7017SPing-Ke Shih } 3292e3ec7017SPing-Ke Shih 3293e3ec7017SPing-Ke Shih switch (coex->pta_mode) { 3294e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_RTK_MODE: 3295e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 3296e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 3297e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 3298e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 3299e3ec7017SPing-Ke Shih 3300e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 3301e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 3302e3ec7017SPing-Ke Shih 3303e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 3304e3ec7017SPing-Ke Shih val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 3305e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 3306e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 3307e3ec7017SPing-Ke Shih break; 3308e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_CSR_MODE: 3309e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 3310e3ec7017SPing-Ke Shih val &= ~B_AX_BTMODE_MASK; 3311e3ec7017SPing-Ke Shih val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 3312e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 3313e3ec7017SPing-Ke Shih 3314e3ec7017SPing-Ke Shih val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 3315e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 3316e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 3317e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 3318e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 3319e3ec7017SPing-Ke Shih val16 &= ~B_AX_BT_STAT_DELAY_MASK; 3320e3ec7017SPing-Ke Shih val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 3321e3ec7017SPing-Ke Shih val16 |= B_AX_ENHANCED_BT; 3322e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 3323e3ec7017SPing-Ke Shih 3324e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 3325e3ec7017SPing-Ke Shih break; 3326e3ec7017SPing-Ke Shih default: 3327e3ec7017SPing-Ke Shih return -EINVAL; 3328e3ec7017SPing-Ke Shih } 3329e3ec7017SPing-Ke Shih 3330e3ec7017SPing-Ke Shih switch (coex->direction) { 3331e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INNER: 3332e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3333e3ec7017SPing-Ke Shih val = (val & ~BIT(2)) | BIT(1); 3334e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3335e3ec7017SPing-Ke Shih break; 3336e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_OUTPUT: 3337e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3338e3ec7017SPing-Ke Shih val = val | BIT(1) | BIT(0); 3339e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3340e3ec7017SPing-Ke Shih break; 3341e3ec7017SPing-Ke Shih case RTW89_MAC_AX_COEX_INPUT: 3342e3ec7017SPing-Ke Shih val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3343e3ec7017SPing-Ke Shih val = val & ~(BIT(2) | BIT(1)); 3344e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3345e3ec7017SPing-Ke Shih break; 3346e3ec7017SPing-Ke Shih default: 3347e3ec7017SPing-Ke Shih return -EINVAL; 3348e3ec7017SPing-Ke Shih } 3349e3ec7017SPing-Ke Shih 3350e3ec7017SPing-Ke Shih return 0; 3351e3ec7017SPing-Ke Shih } 3352e3ec7017SPing-Ke Shih 3353e3ec7017SPing-Ke Shih int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 3354e3ec7017SPing-Ke Shih const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 3355e3ec7017SPing-Ke Shih { 3356e3ec7017SPing-Ke Shih u32 val, ret; 3357e3ec7017SPing-Ke Shih 3358e3ec7017SPing-Ke Shih ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_1, &val); 3359e3ec7017SPing-Ke Shih if (ret) { 3360e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Read LTE fail!\n"); 3361e3ec7017SPing-Ke Shih return ret; 3362e3ec7017SPing-Ke Shih } 3363e3ec7017SPing-Ke Shih val = (gnt_cfg->band[0].gnt_bt ? 3364e3ec7017SPing-Ke Shih B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL : 0) | 3365e3ec7017SPing-Ke Shih (gnt_cfg->band[0].gnt_bt_sw_en ? 3366e3ec7017SPing-Ke Shih B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL : 0) | 3367e3ec7017SPing-Ke Shih (gnt_cfg->band[0].gnt_wl ? 3368e3ec7017SPing-Ke Shih B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL : 0) | 3369e3ec7017SPing-Ke Shih (gnt_cfg->band[0].gnt_wl_sw_en ? 3370e3ec7017SPing-Ke Shih B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL : 0) | 3371e3ec7017SPing-Ke Shih (gnt_cfg->band[1].gnt_bt ? 3372e3ec7017SPing-Ke Shih B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL : 0) | 3373e3ec7017SPing-Ke Shih (gnt_cfg->band[1].gnt_bt_sw_en ? 3374e3ec7017SPing-Ke Shih B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL : 0) | 3375e3ec7017SPing-Ke Shih (gnt_cfg->band[1].gnt_wl ? 3376e3ec7017SPing-Ke Shih B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL : 0) | 3377e3ec7017SPing-Ke Shih (gnt_cfg->band[1].gnt_wl_sw_en ? 3378e3ec7017SPing-Ke Shih B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL : 0); 3379e3ec7017SPing-Ke Shih ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 3380e3ec7017SPing-Ke Shih if (ret) { 3381e3ec7017SPing-Ke Shih rtw89_err(rtwdev, "Write LTE fail!\n"); 3382e3ec7017SPing-Ke Shih return ret; 3383e3ec7017SPing-Ke Shih } 3384e3ec7017SPing-Ke Shih 3385e3ec7017SPing-Ke Shih return 0; 3386e3ec7017SPing-Ke Shih } 3387e3ec7017SPing-Ke Shih 3388e3ec7017SPing-Ke Shih int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 3389e3ec7017SPing-Ke Shih { 3390e3ec7017SPing-Ke Shih u32 reg; 3391e3ec7017SPing-Ke Shih u8 val; 3392e3ec7017SPing-Ke Shih int ret; 3393e3ec7017SPing-Ke Shih 3394e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 3395e3ec7017SPing-Ke Shih if (ret) 3396e3ec7017SPing-Ke Shih return ret; 3397e3ec7017SPing-Ke Shih 3398e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); 3399e3ec7017SPing-Ke Shih val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 3400e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 3401e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 3402e3ec7017SPing-Ke Shih (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 3403e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 3404e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 3405e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 3406e3ec7017SPing-Ke Shih (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0); 3407e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, reg, val); 3408e3ec7017SPing-Ke Shih 3409e3ec7017SPing-Ke Shih return 0; 3410e3ec7017SPing-Ke Shih } 3411e3ec7017SPing-Ke Shih 3412e3ec7017SPing-Ke Shih void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 3413e3ec7017SPing-Ke Shih { 3414e3ec7017SPing-Ke Shih u32 fw_sb; 3415e3ec7017SPing-Ke Shih 3416e3ec7017SPing-Ke Shih fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 3417e3ec7017SPing-Ke Shih fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 3418e3ec7017SPing-Ke Shih fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 3419e3ec7017SPing-Ke Shih if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3420e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 3421e3ec7017SPing-Ke Shih else 3422e3ec7017SPing-Ke Shih fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 3423e3ec7017SPing-Ke Shih val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 3424e3ec7017SPing-Ke Shih val = B_AX_TOGGLE | 3425e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 3426e3ec7017SPing-Ke Shih FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 3427e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 3428e3ec7017SPing-Ke Shih fsleep(1000); /* avoid BT FW loss information */ 3429e3ec7017SPing-Ke Shih } 3430e3ec7017SPing-Ke Shih 3431e3ec7017SPing-Ke Shih u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 3432e3ec7017SPing-Ke Shih { 3433e3ec7017SPing-Ke Shih return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 3434e3ec7017SPing-Ke Shih } 3435e3ec7017SPing-Ke Shih 3436e3ec7017SPing-Ke Shih int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 3437e3ec7017SPing-Ke Shih { 3438e3ec7017SPing-Ke Shih u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 3439e3ec7017SPing-Ke Shih 3440e3ec7017SPing-Ke Shih val = wl ? val | BIT(2) : val & ~BIT(2); 3441e3ec7017SPing-Ke Shih rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 3442e3ec7017SPing-Ke Shih 3443e3ec7017SPing-Ke Shih return 0; 3444e3ec7017SPing-Ke Shih } 3445e3ec7017SPing-Ke Shih 3446e3ec7017SPing-Ke Shih bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 3447e3ec7017SPing-Ke Shih { 3448e3ec7017SPing-Ke Shih u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 3449e3ec7017SPing-Ke Shih 3450e3ec7017SPing-Ke Shih return FIELD_GET(B_AX_LTE_MUX_CTRL_PATH >> 24, val); 3451e3ec7017SPing-Ke Shih } 3452e3ec7017SPing-Ke Shih 3453e3ec7017SPing-Ke Shih static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 3454e3ec7017SPing-Ke Shih { 3455e3ec7017SPing-Ke Shih u32 reg; 3456e3ec7017SPing-Ke Shih u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 3457e3ec7017SPing-Ke Shih B_AX_BFMEE_HE_NDPA_EN; 3458e3ec7017SPing-Ke Shih 3459e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 3460e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 3461e3ec7017SPing-Ke Shih if (en) { 3462e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 3463e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, mask); 3464e3ec7017SPing-Ke Shih } else { 3465e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 3466e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, mask); 3467e3ec7017SPing-Ke Shih } 3468e3ec7017SPing-Ke Shih } 3469e3ec7017SPing-Ke Shih 3470e3ec7017SPing-Ke Shih static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 3471e3ec7017SPing-Ke Shih { 3472e3ec7017SPing-Ke Shih u32 reg; 3473e3ec7017SPing-Ke Shih u32 val32; 3474e3ec7017SPing-Ke Shih int ret; 3475e3ec7017SPing-Ke Shih 3476e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3477e3ec7017SPing-Ke Shih if (ret) 3478e3ec7017SPing-Ke Shih return ret; 3479e3ec7017SPing-Ke Shih 3480e3ec7017SPing-Ke Shih /* AP mode set tx gid to 63 */ 3481e3ec7017SPing-Ke Shih /* STA mode set tx gid to 0(default) */ 3482e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); 3483e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 3484e3ec7017SPing-Ke Shih 3485e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 3486e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 3487e3ec7017SPing-Ke Shih 3488e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 3489e3ec7017SPing-Ke Shih val32 = FIELD_PREP(B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, BFRP_RX_STANDBY_TIMER); 3490e3ec7017SPing-Ke Shih val32 |= FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 3491e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, val32); 3492e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 3493e3ec7017SPing-Ke Shih 3494e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 3495e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 3496e3ec7017SPing-Ke Shih B_AX_BFMEE_USE_NSTS | 3497e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_GID_SEL | 3498e3ec7017SPing-Ke Shih B_AX_BFMEE_CSI_FORCE_RETE_EN); 3499e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 3500e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, reg, 3501e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 3502e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 3503e3ec7017SPing-Ke Shih u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 3504e3ec7017SPing-Ke Shih 3505e3ec7017SPing-Ke Shih return 0; 3506e3ec7017SPing-Ke Shih } 3507e3ec7017SPing-Ke Shih 3508e3ec7017SPing-Ke Shih static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 3509e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 3510e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 3511e3ec7017SPing-Ke Shih { 3512e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3513e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 3514e3ec7017SPing-Ke Shih u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 3515e3ec7017SPing-Ke Shih u8 port_sel = rtwvif->port; 3516e3ec7017SPing-Ke Shih u8 sound_dim = 3, t; 3517e3ec7017SPing-Ke Shih u8 *phy_cap = sta->he_cap.he_cap_elem.phy_cap_info; 3518e3ec7017SPing-Ke Shih u32 reg; 3519e3ec7017SPing-Ke Shih u16 val; 3520e3ec7017SPing-Ke Shih int ret; 3521e3ec7017SPing-Ke Shih 3522e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3523e3ec7017SPing-Ke Shih if (ret) 3524e3ec7017SPing-Ke Shih return ret; 3525e3ec7017SPing-Ke Shih 3526e3ec7017SPing-Ke Shih if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 3527e3ec7017SPing-Ke Shih (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 3528e3ec7017SPing-Ke Shih ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 3529e3ec7017SPing-Ke Shih stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 3530e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 3531e3ec7017SPing-Ke Shih phy_cap[5]); 3532e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 3533e3ec7017SPing-Ke Shih } 3534e3ec7017SPing-Ke Shih if ((sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 3535e3ec7017SPing-Ke Shih (sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 3536e3ec7017SPing-Ke Shih ldpc_en &= !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 3537e3ec7017SPing-Ke Shih stbc_en &= !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 3538e3ec7017SPing-Ke Shih t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 3539e3ec7017SPing-Ke Shih sta->vht_cap.cap); 3540e3ec7017SPing-Ke Shih sound_dim = min(sound_dim, t); 3541e3ec7017SPing-Ke Shih } 3542e3ec7017SPing-Ke Shih nc = min(nc, sound_dim); 3543e3ec7017SPing-Ke Shih nr = min(nr, sound_dim); 3544e3ec7017SPing-Ke Shih 3545e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 3546e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 3547e3ec7017SPing-Ke Shih 3548e3ec7017SPing-Ke Shih val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 3549e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 3550e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 3551e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 3552e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 3553e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 3554e3ec7017SPing-Ke Shih FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 3555e3ec7017SPing-Ke Shih 3556e3ec7017SPing-Ke Shih if (port_sel == 0) 3557e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 3558e3ec7017SPing-Ke Shih else 3559e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 3560e3ec7017SPing-Ke Shih 3561e3ec7017SPing-Ke Shih rtw89_write16(rtwdev, reg, val); 3562e3ec7017SPing-Ke Shih 3563e3ec7017SPing-Ke Shih return 0; 3564e3ec7017SPing-Ke Shih } 3565e3ec7017SPing-Ke Shih 3566e3ec7017SPing-Ke Shih static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 3567e3ec7017SPing-Ke Shih struct ieee80211_vif *vif, 3568e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 3569e3ec7017SPing-Ke Shih { 3570e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3571e3ec7017SPing-Ke Shih u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 3572e3ec7017SPing-Ke Shih u32 reg; 3573e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 3574e3ec7017SPing-Ke Shih int ret; 3575e3ec7017SPing-Ke Shih 3576e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3577e3ec7017SPing-Ke Shih if (ret) 3578e3ec7017SPing-Ke Shih return ret; 3579e3ec7017SPing-Ke Shih 3580e3ec7017SPing-Ke Shih if (sta->he_cap.has_he) { 3581e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 3582e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 3583e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 3584e3ec7017SPing-Ke Shih } 3585e3ec7017SPing-Ke Shih if (sta->vht_cap.vht_supported) { 3586e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 3587e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 3588e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 3589e3ec7017SPing-Ke Shih } 3590e3ec7017SPing-Ke Shih if (sta->ht_cap.ht_supported) { 3591e3ec7017SPing-Ke Shih rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 3592e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 3593e3ec7017SPing-Ke Shih BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 3594e3ec7017SPing-Ke Shih } 3595e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 3596e3ec7017SPing-Ke Shih rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 3597e3ec7017SPing-Ke Shih rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 3598e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, 3599e3ec7017SPing-Ke Shih rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 3600e3ec7017SPing-Ke Shih rrsc); 3601e3ec7017SPing-Ke Shih 3602e3ec7017SPing-Ke Shih return 0; 3603e3ec7017SPing-Ke Shih } 3604e3ec7017SPing-Ke Shih 3605e3ec7017SPing-Ke Shih void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3606e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 3607e3ec7017SPing-Ke Shih { 3608e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3609e3ec7017SPing-Ke Shih 3610e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) { 3611e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, 3612e3ec7017SPing-Ke Shih "initialize bfee for new association\n"); 3613e3ec7017SPing-Ke Shih rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 3614e3ec7017SPing-Ke Shih rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 3615e3ec7017SPing-Ke Shih rtw89_mac_csi_rrsc(rtwdev, vif, sta); 3616e3ec7017SPing-Ke Shih } 3617e3ec7017SPing-Ke Shih } 3618e3ec7017SPing-Ke Shih 3619e3ec7017SPing-Ke Shih void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3620e3ec7017SPing-Ke Shih struct ieee80211_sta *sta) 3621e3ec7017SPing-Ke Shih { 3622e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3623e3ec7017SPing-Ke Shih 3624e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 3625e3ec7017SPing-Ke Shih } 3626e3ec7017SPing-Ke Shih 3627e3ec7017SPing-Ke Shih void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3628e3ec7017SPing-Ke Shih struct ieee80211_bss_conf *conf) 3629e3ec7017SPing-Ke Shih { 3630e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3631e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 3632e3ec7017SPing-Ke Shih __le32 *p; 3633e3ec7017SPing-Ke Shih 3634e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 3635e3ec7017SPing-Ke Shih 3636e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.membership; 3637e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), 3638e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 3639e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), 3640e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 3641e3ec7017SPing-Ke Shih 3642e3ec7017SPing-Ke Shih p = (__le32 *)conf->mu_group.position; 3643e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), 3644e3ec7017SPing-Ke Shih le32_to_cpu(p[0])); 3645e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), 3646e3ec7017SPing-Ke Shih le32_to_cpu(p[1])); 3647e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), 3648e3ec7017SPing-Ke Shih le32_to_cpu(p[2])); 3649e3ec7017SPing-Ke Shih rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), 3650e3ec7017SPing-Ke Shih le32_to_cpu(p[3])); 3651e3ec7017SPing-Ke Shih } 3652e3ec7017SPing-Ke Shih 3653e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data { 3654e3ec7017SPing-Ke Shih struct rtw89_dev *rtwdev; 3655e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta; 3656e3ec7017SPing-Ke Shih int count; 3657e3ec7017SPing-Ke Shih }; 3658e3ec7017SPing-Ke Shih 3659e3ec7017SPing-Ke Shih static 3660e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 3661e3ec7017SPing-Ke Shih { 3662e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data *iter_data = 3663e3ec7017SPing-Ke Shih (struct rtw89_mac_bf_monitor_iter_data *)data; 3664e3ec7017SPing-Ke Shih struct ieee80211_sta *down_sta = iter_data->down_sta; 3665e3ec7017SPing-Ke Shih int *count = &iter_data->count; 3666e3ec7017SPing-Ke Shih 3667e3ec7017SPing-Ke Shih if (down_sta == sta) 3668e3ec7017SPing-Ke Shih return; 3669e3ec7017SPing-Ke Shih 3670e3ec7017SPing-Ke Shih if (rtw89_sta_has_beamformer_cap(sta)) 3671e3ec7017SPing-Ke Shih (*count)++; 3672e3ec7017SPing-Ke Shih } 3673e3ec7017SPing-Ke Shih 3674e3ec7017SPing-Ke Shih void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 3675e3ec7017SPing-Ke Shih struct ieee80211_sta *sta, bool disconnect) 3676e3ec7017SPing-Ke Shih { 3677e3ec7017SPing-Ke Shih struct rtw89_mac_bf_monitor_iter_data data; 3678e3ec7017SPing-Ke Shih 3679e3ec7017SPing-Ke Shih data.rtwdev = rtwdev; 3680e3ec7017SPing-Ke Shih data.down_sta = disconnect ? sta : NULL; 3681e3ec7017SPing-Ke Shih data.count = 0; 3682e3ec7017SPing-Ke Shih ieee80211_iterate_stations_atomic(rtwdev->hw, 3683e3ec7017SPing-Ke Shih rtw89_mac_bf_monitor_calc_iter, 3684e3ec7017SPing-Ke Shih &data); 3685e3ec7017SPing-Ke Shih 3686e3ec7017SPing-Ke Shih rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 3687e3ec7017SPing-Ke Shih if (data.count) 3688e3ec7017SPing-Ke Shih set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 3689e3ec7017SPing-Ke Shih else 3690e3ec7017SPing-Ke Shih clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 3691e3ec7017SPing-Ke Shih } 3692e3ec7017SPing-Ke Shih 3693e3ec7017SPing-Ke Shih void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 3694e3ec7017SPing-Ke Shih { 3695e3ec7017SPing-Ke Shih struct rtw89_traffic_stats *stats = &rtwdev->stats; 3696e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif; 36971646ce8fSYe Guojin bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 3698e3ec7017SPing-Ke Shih bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 3699e3ec7017SPing-Ke Shih 3700e3ec7017SPing-Ke Shih if (en == old) 3701e3ec7017SPing-Ke Shih return; 3702e3ec7017SPing-Ke Shih 3703e3ec7017SPing-Ke Shih rtw89_for_each_rtwvif(rtwdev, rtwvif) 3704e3ec7017SPing-Ke Shih rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 3705e3ec7017SPing-Ke Shih } 3706e3ec7017SPing-Ke Shih 3707e3ec7017SPing-Ke Shih static int 3708e3ec7017SPing-Ke Shih __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3709e3ec7017SPing-Ke Shih u32 tx_time) 3710e3ec7017SPing-Ke Shih { 3711e3ec7017SPing-Ke Shih #define MAC_AX_DFLT_TX_TIME 5280 3712e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 3713e3ec7017SPing-Ke Shih u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 3714e3ec7017SPing-Ke Shih u32 reg; 3715e3ec7017SPing-Ke Shih int ret = 0; 3716e3ec7017SPing-Ke Shih 3717e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 3718e3ec7017SPing-Ke Shih rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 3719e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 3720e3ec7017SPing-Ke Shih } else { 3721e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3722e3ec7017SPing-Ke Shih if (ret) { 3723e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 3724e3ec7017SPing-Ke Shih return ret; 3725e3ec7017SPing-Ke Shih } 3726e3ec7017SPing-Ke Shih 3727e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 3728e3ec7017SPing-Ke Shih rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 3729e3ec7017SPing-Ke Shih max_tx_time >> 5); 3730e3ec7017SPing-Ke Shih } 3731e3ec7017SPing-Ke Shih 3732e3ec7017SPing-Ke Shih return ret; 3733e3ec7017SPing-Ke Shih } 3734e3ec7017SPing-Ke Shih 3735e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3736e3ec7017SPing-Ke Shih bool resume, u32 tx_time) 3737e3ec7017SPing-Ke Shih { 3738e3ec7017SPing-Ke Shih int ret = 0; 3739e3ec7017SPing-Ke Shih 3740e3ec7017SPing-Ke Shih if (!resume) { 3741e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = true; 3742e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 3743e3ec7017SPing-Ke Shih } else { 3744e3ec7017SPing-Ke Shih ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 3745e3ec7017SPing-Ke Shih rtwsta->cctl_tx_time = false; 3746e3ec7017SPing-Ke Shih } 3747e3ec7017SPing-Ke Shih 3748e3ec7017SPing-Ke Shih return ret; 3749e3ec7017SPing-Ke Shih } 3750e3ec7017SPing-Ke Shih 3751e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3752e3ec7017SPing-Ke Shih u32 *tx_time) 3753e3ec7017SPing-Ke Shih { 3754e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 3755e3ec7017SPing-Ke Shih u32 reg; 3756e3ec7017SPing-Ke Shih int ret = 0; 3757e3ec7017SPing-Ke Shih 3758e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_time) { 3759e3ec7017SPing-Ke Shih *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 3760e3ec7017SPing-Ke Shih } else { 3761e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3762e3ec7017SPing-Ke Shih if (ret) { 3763e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 3764e3ec7017SPing-Ke Shih return ret; 3765e3ec7017SPing-Ke Shih } 3766e3ec7017SPing-Ke Shih 3767e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 3768e3ec7017SPing-Ke Shih *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 3769e3ec7017SPing-Ke Shih } 3770e3ec7017SPing-Ke Shih 3771e3ec7017SPing-Ke Shih return ret; 3772e3ec7017SPing-Ke Shih } 3773e3ec7017SPing-Ke Shih 3774e3ec7017SPing-Ke Shih int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 3775e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, 3776e3ec7017SPing-Ke Shih bool resume, u8 tx_retry) 3777e3ec7017SPing-Ke Shih { 3778e3ec7017SPing-Ke Shih int ret = 0; 3779e3ec7017SPing-Ke Shih 3780e3ec7017SPing-Ke Shih rtwsta->data_tx_cnt_lmt = tx_retry; 3781e3ec7017SPing-Ke Shih 3782e3ec7017SPing-Ke Shih if (!resume) { 3783e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = true; 3784e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 3785e3ec7017SPing-Ke Shih } else { 3786e3ec7017SPing-Ke Shih ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 3787e3ec7017SPing-Ke Shih rtwsta->cctl_tx_retry_limit = false; 3788e3ec7017SPing-Ke Shih } 3789e3ec7017SPing-Ke Shih 3790e3ec7017SPing-Ke Shih return ret; 3791e3ec7017SPing-Ke Shih } 3792e3ec7017SPing-Ke Shih 3793e3ec7017SPing-Ke Shih int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 3794e3ec7017SPing-Ke Shih struct rtw89_sta *rtwsta, u8 *tx_retry) 3795e3ec7017SPing-Ke Shih { 3796e3ec7017SPing-Ke Shih u8 mac_idx = rtwsta->rtwvif->mac_idx; 3797e3ec7017SPing-Ke Shih u32 reg; 3798e3ec7017SPing-Ke Shih int ret = 0; 3799e3ec7017SPing-Ke Shih 3800e3ec7017SPing-Ke Shih if (rtwsta->cctl_tx_retry_limit) { 3801e3ec7017SPing-Ke Shih *tx_retry = rtwsta->data_tx_cnt_lmt; 3802e3ec7017SPing-Ke Shih } else { 3803e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3804e3ec7017SPing-Ke Shih if (ret) { 3805e3ec7017SPing-Ke Shih rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 3806e3ec7017SPing-Ke Shih return ret; 3807e3ec7017SPing-Ke Shih } 3808e3ec7017SPing-Ke Shih 3809e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); 3810e3ec7017SPing-Ke Shih *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 3811e3ec7017SPing-Ke Shih } 3812e3ec7017SPing-Ke Shih 3813e3ec7017SPing-Ke Shih return ret; 3814e3ec7017SPing-Ke Shih } 3815e3ec7017SPing-Ke Shih 3816e3ec7017SPing-Ke Shih int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 3817e3ec7017SPing-Ke Shih struct rtw89_vif *rtwvif, bool en) 3818e3ec7017SPing-Ke Shih { 3819e3ec7017SPing-Ke Shih u8 mac_idx = rtwvif->mac_idx; 3820e3ec7017SPing-Ke Shih u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; 3821e3ec7017SPing-Ke Shih u32 reg; 3822e3ec7017SPing-Ke Shih u32 ret; 3823e3ec7017SPing-Ke Shih 3824e3ec7017SPing-Ke Shih ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3825e3ec7017SPing-Ke Shih if (ret) 3826e3ec7017SPing-Ke Shih return ret; 3827e3ec7017SPing-Ke Shih 3828e3ec7017SPing-Ke Shih reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); 3829e3ec7017SPing-Ke Shih if (en) 3830e3ec7017SPing-Ke Shih rtw89_write16_set(rtwdev, reg, set); 3831e3ec7017SPing-Ke Shih else 3832e3ec7017SPing-Ke Shih rtw89_write16_clr(rtwdev, reg, set); 3833e3ec7017SPing-Ke Shih 3834e3ec7017SPing-Ke Shih return 0; 3835e3ec7017SPing-Ke Shih } 3836