1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_FW_H__ 6 #define __RTW89_FW_H__ 7 8 #include "core.h" 9 10 enum rtw89_fw_dl_status { 11 RTW89_FWDL_INITIAL_STATE = 0, 12 RTW89_FWDL_FWDL_ONGOING = 1, 13 RTW89_FWDL_CHECKSUM_FAIL = 2, 14 RTW89_FWDL_SECURITY_FAIL = 3, 15 RTW89_FWDL_CV_NOT_MATCH = 4, 16 RTW89_FWDL_RSVD0 = 5, 17 RTW89_FWDL_WCPU_FWDL_RDY = 6, 18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7 19 }; 20 21 struct rtw89_c2hreg_hdr { 22 u32 w0; 23 }; 24 25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0) 26 #define RTW89_C2HREG_HDR_ACK BIT(7) 27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8) 28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12) 29 30 struct rtw89_c2hreg_phycap { 31 u32 w0; 32 u32 w1; 33 u32 w2; 34 u32 w3; 35 } __packed; 36 37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0) 38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7) 39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8) 40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12) 41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16) 42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24) 43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0) 44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8) 45 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16) 46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24) 47 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0) 48 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8) 49 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16) 50 51 struct rtw89_h2creg_hdr { 52 u32 w0; 53 }; 54 55 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0) 56 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8) 57 58 struct rtw89_h2creg_sch_tx_en { 59 u32 w0; 60 u32 w1; 61 } __packed; 62 63 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16) 64 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0) 65 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16) 66 67 #define RTW89_H2CREG_MAX 4 68 #define RTW89_C2HREG_MAX 4 69 #define RTW89_C2HREG_HDR_LEN 2 70 #define RTW89_H2CREG_HDR_LEN 2 71 #define RTW89_C2H_TIMEOUT 1000000 72 struct rtw89_mac_c2h_info { 73 u8 id; 74 u8 content_len; 75 union { 76 u32 c2hreg[RTW89_C2HREG_MAX]; 77 struct rtw89_c2hreg_hdr hdr; 78 struct rtw89_c2hreg_phycap phycap; 79 } u; 80 }; 81 82 struct rtw89_mac_h2c_info { 83 u8 id; 84 u8 content_len; 85 union { 86 u32 h2creg[RTW89_H2CREG_MAX]; 87 struct rtw89_h2creg_hdr hdr; 88 struct rtw89_h2creg_sch_tx_en sch_tx_en; 89 } u; 90 }; 91 92 enum rtw89_mac_h2c_type { 93 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, 94 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, 95 RTW89_FWCMD_H2CREG_FUNC_FWERR, 96 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, 97 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, 98 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN 99 }; 100 101 enum rtw89_mac_c2h_type { 102 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, 103 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, 104 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, 105 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, 106 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, 107 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF 108 }; 109 110 enum rtw89_fw_c2h_category { 111 RTW89_C2H_CAT_TEST, 112 RTW89_C2H_CAT_MAC, 113 RTW89_C2H_CAT_OUTSRC, 114 }; 115 116 enum rtw89_fw_log_level { 117 RTW89_FW_LOG_LEVEL_OFF, 118 RTW89_FW_LOG_LEVEL_CRT, 119 RTW89_FW_LOG_LEVEL_SER, 120 RTW89_FW_LOG_LEVEL_WARN, 121 RTW89_FW_LOG_LEVEL_LOUD, 122 RTW89_FW_LOG_LEVEL_TR, 123 }; 124 125 enum rtw89_fw_log_path { 126 RTW89_FW_LOG_LEVEL_UART, 127 RTW89_FW_LOG_LEVEL_C2H, 128 RTW89_FW_LOG_LEVEL_SNI, 129 }; 130 131 enum rtw89_fw_log_comp { 132 RTW89_FW_LOG_COMP_VER, 133 RTW89_FW_LOG_COMP_INIT, 134 RTW89_FW_LOG_COMP_TASK, 135 RTW89_FW_LOG_COMP_CNS, 136 RTW89_FW_LOG_COMP_H2C, 137 RTW89_FW_LOG_COMP_C2H, 138 RTW89_FW_LOG_COMP_TX, 139 RTW89_FW_LOG_COMP_RX, 140 RTW89_FW_LOG_COMP_IPSEC, 141 RTW89_FW_LOG_COMP_TIMER, 142 RTW89_FW_LOG_COMP_DBGPKT, 143 RTW89_FW_LOG_COMP_PS, 144 RTW89_FW_LOG_COMP_ERROR, 145 RTW89_FW_LOG_COMP_WOWLAN, 146 RTW89_FW_LOG_COMP_SECURE_BOOT, 147 RTW89_FW_LOG_COMP_BTC, 148 RTW89_FW_LOG_COMP_BB, 149 RTW89_FW_LOG_COMP_TWT, 150 RTW89_FW_LOG_COMP_RF, 151 RTW89_FW_LOG_COMP_MCC = 20, 152 RTW89_FW_LOG_COMP_SCAN = 28, 153 }; 154 155 enum rtw89_pkt_offload_op { 156 RTW89_PKT_OFLD_OP_ADD, 157 RTW89_PKT_OFLD_OP_DEL, 158 RTW89_PKT_OFLD_OP_READ, 159 160 NUM_OF_RTW89_PKT_OFFLOAD_OP, 161 }; 162 163 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \ 164 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op)) 165 166 enum rtw89_scanofld_notify_reason { 167 RTW89_SCAN_DWELL_NOTIFY, 168 RTW89_SCAN_PRE_TX_NOTIFY, 169 RTW89_SCAN_POST_TX_NOTIFY, 170 RTW89_SCAN_ENTER_CH_NOTIFY, 171 RTW89_SCAN_LEAVE_CH_NOTIFY, 172 RTW89_SCAN_END_SCAN_NOTIFY, 173 RTW89_SCAN_REPORT_NOTIFY, 174 RTW89_SCAN_CHKPT_NOTIFY, 175 RTW89_SCAN_ENTER_OP_NOTIFY, 176 RTW89_SCAN_LEAVE_OP_NOTIFY, 177 }; 178 179 enum rtw89_scanofld_status { 180 RTW89_SCAN_STATUS_NOTIFY, 181 RTW89_SCAN_STATUS_SUCCESS, 182 RTW89_SCAN_STATUS_FAIL, 183 }; 184 185 enum rtw89_chan_type { 186 RTW89_CHAN_OPERATE = 0, 187 RTW89_CHAN_ACTIVE, 188 RTW89_CHAN_DFS, 189 }; 190 191 enum rtw89_p2pps_action { 192 RTW89_P2P_ACT_INIT = 0, 193 RTW89_P2P_ACT_UPDATE = 1, 194 RTW89_P2P_ACT_REMOVE = 2, 195 RTW89_P2P_ACT_TERMINATE = 3, 196 }; 197 198 #define RTW89_DEFAULT_CQM_HYST 4 199 #define RTW89_DEFAULT_CQM_THOLD -70 200 201 enum rtw89_bcn_fltr_offload_mode { 202 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0, 203 RTW89_BCN_FLTR_OFFLOAD_MODE_1, 204 RTW89_BCN_FLTR_OFFLOAD_MODE_2, 205 RTW89_BCN_FLTR_OFFLOAD_MODE_3, 206 207 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0, 208 }; 209 210 enum rtw89_bcn_fltr_type { 211 RTW89_BCN_FLTR_BEACON_LOSS, 212 RTW89_BCN_FLTR_RSSI, 213 RTW89_BCN_FLTR_NOTIFY, 214 }; 215 216 enum rtw89_bcn_fltr_rssi_event { 217 RTW89_BCN_FLTR_RSSI_NOT_CHANGED, 218 RTW89_BCN_FLTR_RSSI_HIGH, 219 RTW89_BCN_FLTR_RSSI_LOW, 220 }; 221 222 #define FWDL_SECTION_MAX_NUM 10 223 #define FWDL_SECTION_CHKSUM_LEN 8 224 #define FWDL_SECTION_PER_PKT_LEN 2020 225 226 struct rtw89_fw_hdr_section_info { 227 u8 redl; 228 const u8 *addr; 229 u32 len; 230 u32 dladdr; 231 u32 mssc; 232 u8 type; 233 bool ignore; 234 const u8 *key_addr; 235 u32 key_len; 236 u32 key_idx; 237 }; 238 239 struct rtw89_fw_bin_info { 240 u8 section_num; 241 u32 hdr_len; 242 bool dynamic_hdr_en; 243 u32 dynamic_hdr_len; 244 bool dsp_checksum; 245 bool secure_section_exist; 246 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; 247 }; 248 249 struct rtw89_fw_macid_pause_grp { 250 __le32 pause_grp[4]; 251 __le32 mask_grp[4]; 252 } __packed; 253 254 struct rtw89_fw_macid_pause_sleep_grp { 255 struct { 256 __le32 pause_grp[4]; 257 __le32 pause_mask_grp[4]; 258 __le32 sleep_grp[4]; 259 __le32 sleep_mask_grp[4]; 260 } __packed n[4]; 261 } __packed; 262 263 #define RTW89_H2C_MAX_SIZE 2048 264 #define RTW89_CHANNEL_TIME 45 265 #define RTW89_CHANNEL_TIME_6G 20 266 #define RTW89_DFS_CHAN_TIME 105 267 #define RTW89_OFF_CHAN_TIME 100 268 #define RTW89_DWELL_TIME 20 269 #define RTW89_DWELL_TIME_6G 10 270 #define RTW89_SCAN_WIDTH 0 271 #define RTW89_SCANOFLD_MAX_SSID 8 272 #define RTW89_SCANOFLD_MAX_IE_LEN 512 273 #define RTW89_SCANOFLD_PKT_NONE 0xFF 274 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F 275 #define RTW89_CHAN_INVALID 0xFF 276 #define RTW89_MAC_CHINFO_SIZE 28 277 #define RTW89_SCAN_LIST_GUARD 4 278 #define RTW89_SCAN_LIST_LIMIT \ 279 ((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD) 280 281 #define RTW89_BCN_LOSS_CNT 10 282 283 struct rtw89_mac_chinfo { 284 u8 period; 285 u8 dwell_time; 286 u8 central_ch; 287 u8 pri_ch; 288 u8 bw:3; 289 u8 notify_action:5; 290 u8 num_pkt:4; 291 u8 tx_pkt:1; 292 u8 pause_data:1; 293 u8 ch_band:2; 294 u8 probe_id; 295 u8 dfs_ch:1; 296 u8 tx_null:1; 297 u8 rand_seq_num:1; 298 u8 cfg_tx_pwr:1; 299 u8 rsvd0: 4; 300 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID]; 301 u16 tx_pwr_idx; 302 u8 rsvd1; 303 struct list_head list; 304 bool is_psc; 305 }; 306 307 struct rtw89_mac_chinfo_be { 308 u8 period; 309 u8 dwell_time; 310 u8 central_ch; 311 u8 pri_ch; 312 u8 bw:3; 313 u8 ch_band:2; 314 u8 dfs_ch:1; 315 u8 pause_data:1; 316 u8 tx_null:1; 317 u8 rand_seq_num:1; 318 u8 notify_action:5; 319 u8 probe_id; 320 u8 leave_crit; 321 u8 chkpt_timer; 322 u8 leave_time; 323 u8 leave_th; 324 u16 tx_pkt_ctrl; 325 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID]; 326 u8 sw_def; 327 u16 fw_probe0_ssids; 328 u16 fw_probe0_shortssids; 329 u16 fw_probe0_bssids; 330 331 struct list_head list; 332 bool is_psc; 333 }; 334 335 struct rtw89_pktofld_info { 336 struct list_head list; 337 u8 id; 338 339 /* Below fields are for 6 GHz RNR use only */ 340 u8 ssid[IEEE80211_MAX_SSID_LEN]; 341 u8 ssid_len; 342 u8 bssid[ETH_ALEN]; 343 u16 channel_6ghz; 344 bool cancel; 345 }; 346 347 struct rtw89_h2c_ra { 348 __le32 w0; 349 __le32 w1; 350 __le32 w2; 351 __le32 w3; 352 } __packed; 353 354 #define RTW89_H2C_RA_W0_IS_DIS BIT(0) 355 #define RTW89_H2C_RA_W0_MODE GENMASK(5, 1) 356 #define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6) 357 #define RTW89_H2C_RA_W0_MACID GENMASK(15, 8) 358 #define RTW89_H2C_RA_W0_DCM BIT(16) 359 #define RTW89_H2C_RA_W0_ER BIT(17) 360 #define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18) 361 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20) 362 #define RTW89_H2C_RA_W0_SGI BIT(21) 363 #define RTW89_H2C_RA_W0_LDPC BIT(22) 364 #define RTW89_H2C_RA_W0_STBC BIT(23) 365 #define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24) 366 #define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27) 367 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30) 368 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31) 369 #define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0) 370 #define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0) 371 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31) 372 #define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0) 373 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8) 374 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9) 375 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10) 376 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11) 377 #define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12) 378 #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16) 379 #define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24) 380 #define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26) 381 #define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29) 382 383 struct rtw89_h2c_ra_v1 { 384 struct rtw89_h2c_ra v0; 385 __le32 w4; 386 __le32 w5; 387 } __packed; 388 389 #define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0) 390 #define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8) 391 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16) 392 #define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0) 393 394 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) 395 { 396 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); 397 } 398 399 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) 400 { 401 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 402 } 403 404 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) 405 { 406 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); 407 } 408 409 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) 410 { 411 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); 412 } 413 414 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) 415 { 416 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); 417 } 418 419 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) 420 { 421 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)); 422 } 423 424 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) 425 { 426 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)); 427 } 428 429 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) 430 { 431 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)); 432 } 433 434 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) 435 { 436 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)); 437 } 438 439 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) 440 { 441 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)); 442 } 443 444 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val) 445 { 446 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)); 447 } 448 449 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val) 450 { 451 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)); 452 } 453 454 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val) 455 { 456 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)); 457 } 458 459 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val) 460 { 461 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)); 462 } 463 464 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val) 465 { 466 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)); 467 } 468 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) 469 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) 470 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) 471 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) 472 473 #define FWDL_SECURITY_SECTION_TYPE 9 474 #define FWDL_SECURITY_SIGLEN 512 475 #define FWDL_SECURITY_CHKSUM_LEN 8 476 477 struct rtw89_fw_dynhdr_sec { 478 __le32 w0; 479 u8 content[]; 480 } __packed; 481 482 struct rtw89_fw_dynhdr_hdr { 483 __le32 hdr_len; 484 __le32 setcion_count; 485 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */ 486 } __packed; 487 488 struct rtw89_fw_hdr_section { 489 __le32 w0; 490 __le32 w1; 491 __le32 w2; 492 __le32 w3; 493 } __packed; 494 495 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0) 496 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24) 497 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24) 498 #define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0) 499 #define FWSECTION_HDR_W1_CHECKSUM BIT(28) 500 #define FWSECTION_HDR_W1_REDL BIT(29) 501 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0) 502 503 struct rtw89_fw_hdr { 504 __le32 w0; 505 __le32 w1; 506 __le32 w2; 507 __le32 w3; 508 __le32 w4; 509 __le32 w5; 510 __le32 w6; 511 __le32 w7; 512 struct rtw89_fw_hdr_section sections[]; 513 /* struct rtw89_fw_dynhdr_hdr (optional) */ 514 } __packed; 515 516 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0) 517 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8) 518 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16) 519 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24) 520 #define FW_HDR_W2_COMMITID GENMASK(31, 0) 521 #define FW_HDR_W3_LEN GENMASK(23, 16) 522 #define FW_HDR_W3_HDR_VER GENMASK(31, 24) 523 #define FW_HDR_W4_MONTH GENMASK(7, 0) 524 #define FW_HDR_W4_DATE GENMASK(15, 8) 525 #define FW_HDR_W4_HOUR GENMASK(23, 16) 526 #define FW_HDR_W4_MIN GENMASK(31, 24) 527 #define FW_HDR_W5_YEAR GENMASK(31, 0) 528 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8) 529 #define FW_HDR_W7_PART_SIZE GENMASK(15, 0) 530 #define FW_HDR_W7_DYN_HDR BIT(16) 531 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24) 532 533 struct rtw89_fw_hdr_section_v1 { 534 __le32 w0; 535 __le32 w1; 536 __le32 w2; 537 __le32 w3; 538 } __packed; 539 540 #define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0) 541 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24) 542 #define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24) 543 #define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0) 544 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28) 545 #define FWSECTION_HDR_V1_W1_REDL BIT(29) 546 #define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0) 547 #define FORMATTED_MSSC 0xFF 548 #define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24) 549 550 struct rtw89_fw_hdr_v1 { 551 __le32 w0; 552 __le32 w1; 553 __le32 w2; 554 __le32 w3; 555 __le32 w4; 556 __le32 w5; 557 __le32 w6; 558 __le32 w7; 559 __le32 w8; 560 __le32 w9; 561 __le32 w10; 562 __le32 w11; 563 struct rtw89_fw_hdr_section_v1 sections[]; 564 } __packed; 565 566 #define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0) 567 #define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8) 568 #define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16) 569 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24) 570 #define FW_HDR_V1_W2_COMMITID GENMASK(31, 0) 571 #define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16) 572 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24) 573 #define FW_HDR_V1_W4_MONTH GENMASK(7, 0) 574 #define FW_HDR_V1_W4_DATE GENMASK(15, 8) 575 #define FW_HDR_V1_W4_HOUR GENMASK(23, 16) 576 #define FW_HDR_V1_W4_MIN GENMASK(31, 24) 577 #define FW_HDR_V1_W5_YEAR GENMASK(15, 0) 578 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16) 579 #define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8) 580 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24) 581 #define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0) 582 #define FW_HDR_V1_W7_DYN_HDR BIT(16) 583 584 enum rtw89_fw_mss_pool_rmp_tbl_type { 585 MSS_POOL_RMP_TBL_BITMASK = 0x0, 586 MSS_POOL_RMP_TBL_RECORD = 0x1, 587 }; 588 589 #define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8 590 591 struct rtw89_fw_mss_pool_hdr { 592 u8 signature[8]; /* equal to mss_signature[] */ 593 __le32 rmp_tbl_offset; 594 __le32 key_raw_offset; 595 u8 defen; 596 u8 rsvd[3]; 597 u8 rmpfmt; /* enum rtw89_fw_mss_pool_rmp_tbl_type */ 598 u8 mssdev_max; 599 __le16 keypair_num; 600 __le16 msscust_max; 601 __le16 msskey_num_max; 602 __le32 rsvd3; 603 u8 rmp_tbl[]; 604 } __packed; 605 606 union rtw89_fw_section_mssc_content { 607 struct { 608 u8 pad[58]; 609 __le32 v; 610 } __packed sb_sel_ver; 611 struct { 612 u8 pad[60]; 613 __le16 v; 614 } __packed key_sign_len; 615 } __packed; 616 617 static inline void SET_CTRL_INFO_MACID(void *table, u32 val) 618 { 619 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 620 } 621 622 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val) 623 { 624 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 625 } 626 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) 627 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val) 628 { 629 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); 630 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, 631 GENMASK(8, 0)); 632 } 633 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) 634 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) 635 { 636 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); 637 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, 638 BIT(9)); 639 } 640 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) 641 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val) 642 { 643 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); 644 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, 645 GENMASK(11, 10)); 646 } 647 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) 648 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) 649 { 650 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); 651 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, 652 GENMASK(14, 12)); 653 } 654 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) 655 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) 656 { 657 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 658 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, 659 BIT(15)); 660 } 661 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) 662 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) 663 { 664 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); 665 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, 666 GENMASK(19, 16)); 667 } 668 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) 669 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) 670 { 671 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); 672 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, 673 BIT(20)); 674 } 675 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) 676 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) 677 { 678 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); 679 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, 680 BIT(21)); 681 } 682 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) 683 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) 684 { 685 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); 686 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, 687 BIT(22)); 688 } 689 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) 690 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) 691 { 692 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); 693 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, 694 BIT(23)); 695 } 696 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0) 697 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val) 698 { 699 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); 700 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, 701 BIT(25)); 702 } 703 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0) 704 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val) 705 { 706 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); 707 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, 708 BIT(26)); 709 } 710 #define SET_CMC_TBL_MASK_TRYRATE BIT(0) 711 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val) 712 { 713 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); 714 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, 715 BIT(27)); 716 } 717 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) 718 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) 719 { 720 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); 721 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, 722 GENMASK(31, 28)); 723 } 724 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) 725 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) 726 { 727 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); 728 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, 729 GENMASK(8, 0)); 730 } 731 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) 732 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) 733 { 734 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); 735 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, 736 BIT(9)); 737 } 738 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) 739 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) 740 { 741 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); 742 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, 743 BIT(10)); 744 } 745 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) 746 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) 747 { 748 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); 749 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, 750 BIT(11)); 751 } 752 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) 753 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) 754 { 755 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); 756 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, 757 GENMASK(15, 12)); 758 } 759 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) 760 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val) 761 { 762 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); 763 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, 764 GENMASK(24, 16)); 765 } 766 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0) 767 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val) 768 { 769 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); 770 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, 771 BIT(27)); 772 } 773 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) 774 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) 775 { 776 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); 777 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, 778 GENMASK(31, 28)); 779 } 780 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) 781 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) 782 { 783 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); 784 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, 785 GENMASK(5, 0)); 786 } 787 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) 788 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) 789 { 790 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); 791 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, 792 BIT(6)); 793 } 794 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) 795 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) 796 { 797 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); 798 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, 799 BIT(7)); 800 } 801 #define SET_CMC_TBL_MASK_RTS_EN BIT(0) 802 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val) 803 { 804 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); 805 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, 806 BIT(8)); 807 } 808 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) 809 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) 810 { 811 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); 812 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, 813 BIT(9)); 814 } 815 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) 816 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val) 817 { 818 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); 819 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, 820 GENMASK(11, 10)); 821 } 822 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) 823 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) 824 { 825 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); 826 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, 827 BIT(12)); 828 } 829 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) 830 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) 831 { 832 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); 833 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, 834 GENMASK(14, 13)); 835 } 836 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) 837 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) 838 { 839 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); 840 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, 841 GENMASK(26, 16)); 842 } 843 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) 844 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) 845 { 846 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 847 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, 848 BIT(27)); 849 } 850 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) 851 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) 852 { 853 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); 854 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, 855 GENMASK(31, 28)); 856 } 857 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) 858 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) 859 { 860 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); 861 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, 862 GENMASK(7, 0)); 863 } 864 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) 865 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val) 866 { 867 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); 868 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, 869 GENMASK(9, 8)); 870 } 871 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) 872 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) 873 { 874 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); 875 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, 876 GENMASK(18, 16)); 877 } 878 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) 879 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) 880 { 881 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); 882 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, 883 GENMASK(21, 19)); 884 } 885 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) 886 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) 887 { 888 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); 889 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, 890 GENMASK(24, 22)); 891 } 892 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) 893 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) 894 { 895 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); 896 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, 897 GENMASK(27, 25)); 898 } 899 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) 900 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val) 901 { 902 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); 903 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, 904 GENMASK(31, 28)); 905 } 906 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) 907 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) 908 { 909 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); 910 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, 911 GENMASK(2, 0)); 912 } 913 #define SET_CMC_TBL_MASK_BMC BIT(0) 914 static inline void SET_CMC_TBL_BMC(void *table, u32 val) 915 { 916 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); 917 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, 918 BIT(3)); 919 } 920 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) 921 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val) 922 { 923 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); 924 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, 925 GENMASK(7, 4)); 926 } 927 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) 928 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) 929 { 930 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 931 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, 932 BIT(8)); 933 } 934 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) 935 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) 936 { 937 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); 938 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, 939 GENMASK(11, 9)); 940 } 941 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0) 942 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val) 943 { 944 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); 945 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, 946 BIT(12)); 947 } 948 #define SET_CMC_TBL_MASK_DATA_ER BIT(0) 949 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val) 950 { 951 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); 952 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, 953 BIT(13)); 954 } 955 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) 956 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val) 957 { 958 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); 959 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, 960 BIT(14)); 961 } 962 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0) 963 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val) 964 { 965 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 966 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, 967 BIT(15)); 968 } 969 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) 970 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) 971 { 972 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); 973 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, 974 BIT(16)); 975 } 976 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) 977 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) 978 { 979 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); 980 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, 981 BIT(17)); 982 } 983 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) 984 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) 985 { 986 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); 987 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, 988 BIT(18)); 989 } 990 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) 991 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) 992 { 993 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); 994 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, 995 BIT(19)); 996 } 997 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) 998 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) 999 { 1000 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); 1001 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, 1002 BIT(20)); 1003 } 1004 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) 1005 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) 1006 { 1007 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); 1008 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, 1009 BIT(21)); 1010 } 1011 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) 1012 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) 1013 { 1014 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); 1015 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, 1016 BIT(27)); 1017 } 1018 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) 1019 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val) 1020 { 1021 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); 1022 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, 1023 GENMASK(31, 28)); 1024 } 1025 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) 1026 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) 1027 { 1028 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); 1029 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, 1030 GENMASK(8, 0)); 1031 } 1032 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) 1033 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) 1034 { 1035 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); 1036 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, 1037 BIT(12)); 1038 } 1039 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) 1040 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) 1041 { 1042 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); 1043 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, 1044 BIT(13)); 1045 } 1046 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) 1047 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) 1048 { 1049 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); 1050 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, 1051 GENMASK(19, 16)); 1052 } 1053 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) 1054 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) 1055 { 1056 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); 1057 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, 1058 GENMASK(21, 20)); 1059 } 1060 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) 1061 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) 1062 { 1063 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); 1064 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, 1065 GENMASK(23, 22)); 1066 } 1067 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) 1068 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) 1069 { 1070 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); 1071 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, 1072 GENMASK(25, 24)); 1073 } 1074 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) 1075 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) 1076 { 1077 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); 1078 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, 1079 GENMASK(27, 26)); 1080 } 1081 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) 1082 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val) 1083 { 1084 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); 1085 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, 1086 BIT(28)); 1087 } 1088 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) 1089 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val) 1090 { 1091 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); 1092 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, 1093 BIT(29)); 1094 } 1095 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) 1096 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val) 1097 { 1098 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); 1099 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, 1100 BIT(30)); 1101 } 1102 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) 1103 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val) 1104 { 1105 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); 1106 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, 1107 BIT(31)); 1108 } 1109 1110 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) 1111 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val) 1112 { 1113 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0)); 1114 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1115 GENMASK(1, 0)); 1116 } 1117 1118 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val) 1119 { 1120 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2)); 1121 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1122 GENMASK(3, 2)); 1123 } 1124 1125 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val) 1126 { 1127 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4)); 1128 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1129 GENMASK(5, 4)); 1130 } 1131 1132 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val) 1133 { 1134 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6)); 1135 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1136 GENMASK(7, 6)); 1137 } 1138 1139 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) 1140 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) 1141 { 1142 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1143 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, 1144 GENMASK(7, 0)); 1145 } 1146 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) 1147 static inline void SET_CMC_TBL_PAID(void *table, u32 val) 1148 { 1149 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); 1150 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, 1151 GENMASK(16, 8)); 1152 } 1153 #define SET_CMC_TBL_MASK_ULDL BIT(0) 1154 static inline void SET_CMC_TBL_ULDL(void *table, u32 val) 1155 { 1156 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); 1157 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, 1158 BIT(17)); 1159 } 1160 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) 1161 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) 1162 { 1163 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); 1164 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, 1165 GENMASK(19, 18)); 1166 } 1167 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) 1168 { 1169 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); 1170 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1171 GENMASK(21, 20)); 1172 } 1173 1174 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) 1175 { 1176 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); 1177 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1178 GENMASK(23, 22)); 1179 } 1180 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) 1181 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) 1182 { 1183 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); 1184 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, 1185 GENMASK(27, 24)); 1186 } 1187 1188 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) 1189 { 1190 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); 1191 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1192 GENMASK(31, 30)); 1193 } 1194 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0) 1195 static inline void SET_CMC_TBL_NC(void *table, u32 val) 1196 { 1197 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); 1198 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, 1199 GENMASK(2, 0)); 1200 } 1201 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0) 1202 static inline void SET_CMC_TBL_NR(void *table, u32 val) 1203 { 1204 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); 1205 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, 1206 GENMASK(5, 3)); 1207 } 1208 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0) 1209 static inline void SET_CMC_TBL_NG(void *table, u32 val) 1210 { 1211 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); 1212 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, 1213 GENMASK(7, 6)); 1214 } 1215 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0) 1216 static inline void SET_CMC_TBL_CB(void *table, u32 val) 1217 { 1218 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); 1219 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, 1220 GENMASK(9, 8)); 1221 } 1222 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0) 1223 static inline void SET_CMC_TBL_CS(void *table, u32 val) 1224 { 1225 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); 1226 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, 1227 GENMASK(11, 10)); 1228 } 1229 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) 1230 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) 1231 { 1232 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); 1233 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, 1234 BIT(12)); 1235 } 1236 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) 1237 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) 1238 { 1239 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); 1240 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, 1241 BIT(13)); 1242 } 1243 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) 1244 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) 1245 { 1246 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); 1247 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, 1248 BIT(14)); 1249 } 1250 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) 1251 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) 1252 { 1253 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); 1254 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, 1255 BIT(15)); 1256 } 1257 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) 1258 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) 1259 { 1260 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); 1261 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, 1262 GENMASK(24, 16)); 1263 } 1264 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) 1265 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) 1266 { 1267 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); 1268 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, 1269 GENMASK(27, 25)); 1270 } 1271 1272 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val) 1273 { 1274 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28)); 1275 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1276 GENMASK(29, 28)); 1277 } 1278 1279 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) 1280 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val) 1281 { 1282 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); 1283 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, 1284 GENMASK(31, 30)); 1285 } 1286 1287 struct rtw89_h2c_cctlinfo_ud_g7 { 1288 __le32 c0; 1289 __le32 w0; 1290 __le32 w1; 1291 __le32 w2; 1292 __le32 w3; 1293 __le32 w4; 1294 __le32 w5; 1295 __le32 w6; 1296 __le32 w7; 1297 __le32 w8; 1298 __le32 w9; 1299 __le32 w10; 1300 __le32 w11; 1301 __le32 w12; 1302 __le32 w13; 1303 __le32 w14; 1304 __le32 w15; 1305 __le32 m0; 1306 __le32 m1; 1307 __le32 m2; 1308 __le32 m3; 1309 __le32 m4; 1310 __le32 m5; 1311 __le32 m6; 1312 __le32 m7; 1313 __le32 m8; 1314 __le32 m9; 1315 __le32 m10; 1316 __le32 m11; 1317 __le32 m12; 1318 __le32 m13; 1319 __le32 m14; 1320 __le32 m15; 1321 } __packed; 1322 1323 #define CCTLINFO_G7_C0_MACID GENMASK(6, 0) 1324 #define CCTLINFO_G7_C0_OP BIT(7) 1325 1326 #define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0) 1327 #define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12) 1328 #define CCTLINFO_G7_W0_TRYRATE BIT(15) 1329 #define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16) 1330 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18) 1331 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20) 1332 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21) 1333 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22) 1334 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23) 1335 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24) 1336 #define CCTLINFO_G7_W0_DISRTSFB BIT(25) 1337 #define CCTLINFO_G7_W0_DISDATAFB BIT(26) 1338 #define CCTLINFO_G7_W0_NSTR_EN BIT(27) 1339 #define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28) 1340 #define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0)) 1341 #define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0) 1342 #define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12) 1343 #define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16) 1344 #define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28) 1345 #define CCTLINFO_G7_W1_ALL GENMASK(31, 0) 1346 #define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0) 1347 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6) 1348 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7) 1349 #define CCTLINFO_G7_W2_RTS_EN BIT(8) 1350 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9) 1351 #define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10) 1352 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12) 1353 #define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13) 1354 #define CCTLINFO_G7_W2_PRELD_EN BIT(15) 1355 #define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16) 1356 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27) 1357 #define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28) 1358 #define CCTLINFO_G7_W2_ALL GENMASK(31, 0) 1359 #define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0) 1360 #define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8) 1361 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11) 1362 #define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12) 1363 #define CCTLINFO_G7_W3_VCS_STBC BIT(15) 1364 #define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16) 1365 #define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19) 1366 #define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22) 1367 #define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25) 1368 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28) 1369 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29) 1370 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30) 1371 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31) 1372 #define CCTLINFO_G7_W3_ALL GENMASK(31, 0) 1373 #define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0) 1374 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3) 1375 #define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4) 1376 #define CCTLINFO_G7_W4_DATA_DCM BIT(8) 1377 #define CCTLINFO_G7_W4_DATA_ER BIT(9) 1378 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10) 1379 #define CCTLINFO_G7_W4_DATA_STBC BIT(11) 1380 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12) 1381 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14) 1382 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15) 1383 #define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16) 1384 #define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0)) 1385 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0) 1386 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2) 1387 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4) 1388 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6) 1389 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8) 1390 #define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10) 1391 #define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16) 1392 #define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24) 1393 #define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0)) 1394 #define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0) 1395 #define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12) 1396 #define CCTLINFO_G7_W6_ULDL BIT(31) 1397 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0)) 1398 #define CCTLINFO_G7_W7_NC GENMASK(2, 0) 1399 #define CCTLINFO_G7_W7_NR GENMASK(5, 3) 1400 #define CCTLINFO_G7_W7_NG GENMASK(7, 6) 1401 #define CCTLINFO_G7_W7_CB GENMASK(9, 8) 1402 #define CCTLINFO_G7_W7_CS GENMASK(11, 10) 1403 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13) 1404 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14) 1405 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15) 1406 #define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16) 1407 #define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29) 1408 #define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0)) 1409 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0) 1410 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1) 1411 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2) 1412 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3) 1413 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4) 1414 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5) 1415 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6) 1416 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7) 1417 #define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8) 1418 #define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12) 1419 #define CCTLINFO_G7_W8_ALL GENMASK(15, 0) 1420 /* W9~13 are reserved */ 1421 #define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0) 1422 #define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12) 1423 #define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24) 1424 #define CCTLINFO_G7_W14_ALL GENMASK(31, 0) 1425 #define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0) 1426 #define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4) 1427 #define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16) 1428 #define CCTLINFO_G7_W15_ALL GENMASK(27, 0) 1429 1430 static inline void SET_DCTL_MACID_V1(void *table, u32 val) 1431 { 1432 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 1433 } 1434 1435 static inline void SET_DCTL_OPERATION_V1(void *table, u32 val) 1436 { 1437 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 1438 } 1439 1440 #define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0) 1441 static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val) 1442 { 1443 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0)); 1444 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1, 1445 GENMASK(7, 0)); 1446 } 1447 1448 #define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0) 1449 static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val) 1450 { 1451 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8)); 1452 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID, 1453 GENMASK(14, 8)); 1454 } 1455 1456 #define SET_DCTL_MASK_QOS_DATA BIT(0) 1457 static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val) 1458 { 1459 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 1460 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA, 1461 BIT(15)); 1462 } 1463 1464 #define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0) 1465 static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val) 1466 { 1467 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16)); 1468 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L, 1469 GENMASK(31, 16)); 1470 } 1471 1472 #define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0) 1473 static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val) 1474 { 1475 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0)); 1476 le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H, 1477 GENMASK(31, 0)); 1478 } 1479 1480 #define SET_DCTL_MASK_SEQ0 GENMASK(11, 0) 1481 static inline void SET_DCTL_SEQ0_V1(void *table, u32 val) 1482 { 1483 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0)); 1484 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0, 1485 GENMASK(11, 0)); 1486 } 1487 1488 #define SET_DCTL_MASK_SEQ1 GENMASK(11, 0) 1489 static inline void SET_DCTL_SEQ1_V1(void *table, u32 val) 1490 { 1491 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12)); 1492 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1, 1493 GENMASK(23, 12)); 1494 } 1495 1496 #define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0) 1497 static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val) 1498 { 1499 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24)); 1500 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN, 1501 GENMASK(26, 24)); 1502 } 1503 1504 #define SET_DCTL_MASK_STA_AMSDU_EN BIT(0) 1505 static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val) 1506 { 1507 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 1508 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN, 1509 BIT(27)); 1510 } 1511 1512 #define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0) 1513 static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val) 1514 { 1515 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28)); 1516 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN, 1517 BIT(28)); 1518 } 1519 1520 #define SET_DCTL_MASK_WITH_LLC BIT(0) 1521 static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val) 1522 { 1523 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29)); 1524 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC, 1525 BIT(29)); 1526 } 1527 1528 #define SET_DCTL_MASK_SEQ2 GENMASK(11, 0) 1529 static inline void SET_DCTL_SEQ2_V1(void *table, u32 val) 1530 { 1531 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0)); 1532 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2, 1533 GENMASK(11, 0)); 1534 } 1535 1536 #define SET_DCTL_MASK_SEQ3 GENMASK(11, 0) 1537 static inline void SET_DCTL_SEQ3_V1(void *table, u32 val) 1538 { 1539 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12)); 1540 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3, 1541 GENMASK(23, 12)); 1542 } 1543 1544 #define SET_DCTL_MASK_TGT_IND GENMASK(3, 0) 1545 static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val) 1546 { 1547 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24)); 1548 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND, 1549 GENMASK(27, 24)); 1550 } 1551 1552 #define SET_DCTL_MASK_TGT_IND_EN BIT(0) 1553 static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val) 1554 { 1555 le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28)); 1556 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN, 1557 BIT(28)); 1558 } 1559 1560 #define SET_DCTL_MASK_HTC_LB GENMASK(2, 0) 1561 static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val) 1562 { 1563 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29)); 1564 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB, 1565 GENMASK(31, 29)); 1566 } 1567 1568 #define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0) 1569 static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val) 1570 { 1571 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0)); 1572 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN, 1573 GENMASK(4, 0)); 1574 } 1575 1576 #define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0) 1577 static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val) 1578 { 1579 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5)); 1580 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID, 1581 BIT(5)); 1582 } 1583 1584 #define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0) 1585 static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val) 1586 { 1587 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6)); 1588 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL, 1589 GENMASK(7, 6)); 1590 } 1591 1592 #define SET_DCTL_MASK_HTC_ORDER BIT(0) 1593 static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val) 1594 { 1595 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 1596 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER, 1597 BIT(8)); 1598 } 1599 1600 #define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0) 1601 static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val) 1602 { 1603 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9)); 1604 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID, 1605 GENMASK(10, 9)); 1606 } 1607 1608 #define SET_DCTL_MASK_WAPI BIT(0) 1609 static inline void SET_DCTL_WAPI_V1(void *table, u32 val) 1610 { 1611 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 1612 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI, 1613 BIT(15)); 1614 } 1615 1616 #define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0) 1617 static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val) 1618 { 1619 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16)); 1620 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE, 1621 GENMASK(17, 16)); 1622 } 1623 1624 #define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0) 1625 static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val) 1626 { 1627 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18)); 1628 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1629 GENMASK(19, 18)); 1630 } 1631 1632 static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val) 1633 { 1634 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20)); 1635 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1636 GENMASK(21, 20)); 1637 } 1638 1639 static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val) 1640 { 1641 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22)); 1642 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1643 GENMASK(23, 22)); 1644 } 1645 1646 static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val) 1647 { 1648 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24)); 1649 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1650 GENMASK(25, 24)); 1651 } 1652 1653 static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val) 1654 { 1655 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26)); 1656 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1657 GENMASK(27, 26)); 1658 } 1659 1660 static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val) 1661 { 1662 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28)); 1663 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1664 GENMASK(29, 28)); 1665 } 1666 1667 static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val) 1668 { 1669 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30)); 1670 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1671 GENMASK(31, 30)); 1672 } 1673 1674 #define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0) 1675 static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val) 1676 { 1677 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0)); 1678 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID, 1679 GENMASK(7, 0)); 1680 } 1681 1682 #define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0) 1683 static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val) 1684 { 1685 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8)); 1686 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1687 GENMASK(15, 8)); 1688 } 1689 1690 static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val) 1691 { 1692 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16)); 1693 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1694 GENMASK(23, 16)); 1695 } 1696 1697 static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val) 1698 { 1699 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24)); 1700 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1701 GENMASK(31, 24)); 1702 } 1703 1704 static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val) 1705 { 1706 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1707 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1708 GENMASK(7, 0)); 1709 } 1710 1711 static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val) 1712 { 1713 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8)); 1714 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1715 GENMASK(15, 8)); 1716 } 1717 1718 static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val) 1719 { 1720 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16)); 1721 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1722 GENMASK(23, 16)); 1723 } 1724 1725 static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val) 1726 { 1727 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24)); 1728 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1729 GENMASK(31, 24)); 1730 } 1731 1732 struct rtw89_h2c_bcn_upd { 1733 __le32 w0; 1734 __le32 w1; 1735 __le32 w2; 1736 } __packed; 1737 1738 #define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0) 1739 #define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8) 1740 #define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16) 1741 #define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24) 1742 #define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0) 1743 #define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8) 1744 #define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10) 1745 #define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12) 1746 #define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21) 1747 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0) 1748 #define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1) 1749 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5) 1750 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7) 1751 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9) 1752 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11) 1753 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13) 1754 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14) 1755 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15) 1756 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16) 1757 #define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17) 1758 1759 struct rtw89_h2c_bcn_upd_be { 1760 __le32 w0; 1761 __le32 w1; 1762 __le32 w2; 1763 __le32 w3; 1764 __le32 w4; 1765 __le32 w5; 1766 __le32 w6; 1767 __le32 w7; 1768 __le32 w8; 1769 __le32 w9; 1770 __le32 w10; 1771 __le32 w11; 1772 __le32 w12; 1773 __le32 w13; 1774 __le32 w14; 1775 __le32 w15; 1776 __le32 w16; 1777 __le32 w17; 1778 __le32 w18; 1779 __le32 w19; 1780 __le32 w20; 1781 __le32 w21; 1782 __le32 w22; 1783 __le32 w23; 1784 __le32 w24; 1785 __le32 w25; 1786 __le32 w26; 1787 __le32 w27; 1788 __le32 w28; 1789 __le32 w29; 1790 } __packed; 1791 1792 #define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0) 1793 #define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8) 1794 #define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16) 1795 #define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24) 1796 #define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0) 1797 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8) 1798 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10) 1799 #define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12) 1800 #define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21) 1801 #define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24) 1802 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0) 1803 #define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1) 1804 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5) 1805 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7) 1806 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9) 1807 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11) 1808 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13) 1809 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14) 1810 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15) 1811 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16) 1812 #define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17) 1813 #define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0) 1814 #define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16) 1815 #define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0) 1816 #define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16) 1817 #define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0) 1818 #define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16) 1819 #define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0) 1820 #define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16) 1821 #define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0) 1822 #define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16) 1823 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31) 1824 1825 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val) 1826 { 1827 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1828 } 1829 1830 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val) 1831 { 1832 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)); 1833 } 1834 1835 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val) 1836 { 1837 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)); 1838 } 1839 1840 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val) 1841 { 1842 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)); 1843 } 1844 1845 enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */ 1846 RTW89_FW_N_AC_STA = 0, 1847 RTW89_FW_AX_STA = 1, 1848 RTW89_FW_BE_STA = 2, 1849 }; 1850 1851 struct rtw89_h2c_join { 1852 __le32 w0; 1853 } __packed; 1854 1855 struct rtw89_h2c_join_v1 { 1856 __le32 w0; 1857 __le32 w1; 1858 __le32 w2; 1859 } __packed; 1860 1861 #define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0) 1862 #define RTW89_H2C_JOININFO_W0_OP BIT(8) 1863 #define RTW89_H2C_JOININFO_W0_BAND BIT(9) 1864 #define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10) 1865 #define RTW89_H2C_JOININFO_W0_TGR BIT(12) 1866 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13) 1867 #define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14) 1868 #define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16) 1869 #define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18) 1870 #define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21) 1871 #define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24) 1872 #define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26) 1873 #define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30) 1874 #define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0) 1875 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3) 1876 #define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4) 1877 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12) 1878 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13) 1879 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14) 1880 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15) 1881 #define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16) 1882 #define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19) 1883 #define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0) 1884 #define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8) 1885 1886 struct rtw89_h2c_notify_dbcc { 1887 __le32 w0; 1888 } __packed; 1889 1890 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0) 1891 1892 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val) 1893 { 1894 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1895 } 1896 1897 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) 1898 { 1899 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1900 } 1901 1902 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) 1903 { 1904 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1905 } 1906 1907 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) 1908 { 1909 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1910 } 1911 1912 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) 1913 { 1914 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1915 } 1916 1917 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) 1918 { 1919 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1920 } 1921 1922 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val) 1923 { 1924 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1925 } 1926 1927 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val) 1928 { 1929 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1930 } 1931 1932 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val) 1933 { 1934 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 1935 } 1936 1937 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) 1938 { 1939 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)); 1940 } 1941 1942 struct rtw89_h2c_ba_cam { 1943 __le32 w0; 1944 __le32 w1; 1945 } __packed; 1946 1947 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0) 1948 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1) 1949 #define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2) 1950 #define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4) 1951 #define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8) 1952 #define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16) 1953 #define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20) 1954 #define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0) 1955 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8) 1956 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9) 1957 #define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28) 1958 1959 struct rtw89_h2c_ba_cam_v1 { 1960 __le32 w0; 1961 __le32 w1; 1962 } __packed; 1963 1964 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0) 1965 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1) 1966 #define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4) 1967 #define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8) 1968 #define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16) 1969 #define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20) 1970 #define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0) 1971 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8) 1972 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9) 1973 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10) 1974 #define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24) 1975 1976 struct rtw89_h2c_ba_cam_init { 1977 __le32 w0; 1978 } __packed; 1979 1980 #define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0) 1981 #define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12) 1982 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24) 1983 1984 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val) 1985 { 1986 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1987 } 1988 1989 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val) 1990 { 1991 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1992 } 1993 1994 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val) 1995 { 1996 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1997 } 1998 1999 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val) 2000 { 2001 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)); 2002 } 2003 2004 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) 2005 { 2006 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2007 } 2008 2009 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) 2010 { 2011 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)); 2012 } 2013 2014 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) 2015 { 2016 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)); 2017 } 2018 2019 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) 2020 { 2021 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)); 2022 } 2023 2024 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) 2025 { 2026 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)); 2027 } 2028 2029 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) 2030 { 2031 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 2032 } 2033 2034 struct rtw89_h2c_lps_ch_info { 2035 struct { 2036 u8 pri_ch; 2037 u8 central_ch; 2038 u8 bw; 2039 u8 band; 2040 } __packed info[2]; 2041 2042 __le32 mlo_dbcc_mode_lps; 2043 } __packed; 2044 2045 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val) 2046 { 2047 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0)); 2048 } 2049 2050 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val) 2051 { 2052 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2053 } 2054 2055 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val) 2056 { 2057 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 2058 } 2059 2060 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val) 2061 { 2062 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 2063 } 2064 2065 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val) 2066 { 2067 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 2068 } 2069 2070 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val) 2071 { 2072 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0)); 2073 } 2074 2075 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val) 2076 { 2077 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8)); 2078 } 2079 2080 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val) 2081 { 2082 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 2083 } 2084 2085 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val) 2086 { 2087 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 2088 } 2089 2090 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val) 2091 { 2092 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 2093 } 2094 2095 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val) 2096 { 2097 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0)); 2098 } 2099 2100 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val) 2101 { 2102 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0)); 2103 } 2104 2105 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val) 2106 { 2107 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 2108 } 2109 2110 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val) 2111 { 2112 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16)); 2113 } 2114 2115 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val) 2116 { 2117 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2118 } 2119 2120 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val) 2121 { 2122 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2123 } 2124 2125 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val) 2126 { 2127 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 2128 } 2129 2130 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val) 2131 { 2132 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 2133 } 2134 2135 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val) 2136 { 2137 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 2138 } 2139 2140 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val) 2141 { 2142 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 2143 } 2144 2145 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val) 2146 { 2147 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2148 } 2149 2150 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val) 2151 { 2152 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 2153 } 2154 2155 static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val) 2156 { 2157 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2158 } 2159 2160 static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val) 2161 { 2162 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 2163 } 2164 2165 static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val) 2166 { 2167 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 2168 } 2169 2170 static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val) 2171 { 2172 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); 2173 } 2174 2175 static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val) 2176 { 2177 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 2178 } 2179 2180 static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val) 2181 { 2182 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 2183 } 2184 2185 static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val) 2186 { 2187 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2188 } 2189 2190 static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val) 2191 { 2192 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 2193 } 2194 2195 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val) 2196 { 2197 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2198 } 2199 2200 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val) 2201 { 2202 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 2203 } 2204 2205 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val) 2206 { 2207 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 2208 } 2209 2210 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val) 2211 { 2212 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); 2213 } 2214 2215 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val) 2216 { 2217 le32p_replace_bits((__le32 *)h2c, val, BIT(4)); 2218 } 2219 2220 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val) 2221 { 2222 le32p_replace_bits((__le32 *)h2c, val, BIT(5)); 2223 } 2224 2225 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val) 2226 { 2227 le32p_replace_bits((__le32 *)h2c, val, BIT(6)); 2228 } 2229 2230 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val) 2231 { 2232 le32p_replace_bits((__le32 *)h2c, val, BIT(7)); 2233 } 2234 2235 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val) 2236 { 2237 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2238 } 2239 2240 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val) 2241 { 2242 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2243 } 2244 2245 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val) 2246 { 2247 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1)); 2248 } 2249 2250 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val) 2251 { 2252 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0)); 2253 } 2254 2255 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val) 2256 { 2257 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0)); 2258 } 2259 2260 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val) 2261 { 2262 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0)); 2263 } 2264 2265 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val) 2266 { 2267 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0)); 2268 } 2269 2270 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val) 2271 { 2272 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0)); 2273 } 2274 2275 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val) 2276 { 2277 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22)); 2278 } 2279 2280 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val) 2281 { 2282 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23)); 2283 } 2284 2285 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val) 2286 { 2287 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24)); 2288 } 2289 2290 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val) 2291 { 2292 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25)); 2293 } 2294 2295 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val) 2296 { 2297 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26)); 2298 } 2299 2300 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val) 2301 { 2302 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31)); 2303 } 2304 2305 enum rtw89_btc_btf_h2c_class { 2306 BTFC_SET = 0x10, 2307 BTFC_GET = 0x11, 2308 BTFC_FW_EVENT = 0x12, 2309 }; 2310 2311 enum rtw89_btc_btf_set { 2312 SET_REPORT_EN = 0x0, 2313 SET_SLOT_TABLE, 2314 SET_MREG_TABLE, 2315 SET_CX_POLICY, 2316 SET_GPIO_DBG, 2317 SET_DRV_INFO, 2318 SET_DRV_EVENT, 2319 SET_BT_WREG_ADDR, 2320 SET_BT_WREG_VAL, 2321 SET_BT_RREG_ADDR, 2322 SET_BT_WL_CH_INFO, 2323 SET_BT_INFO_REPORT, 2324 SET_BT_IGNORE_WLAN_ACT, 2325 SET_BT_TX_PWR, 2326 SET_BT_LNA_CONSTRAIN, 2327 SET_BT_GOLDEN_RX_RANGE, 2328 SET_BT_PSD_REPORT, 2329 SET_H2C_TEST, 2330 SET_MAX1, 2331 }; 2332 2333 enum rtw89_btc_cxdrvinfo { 2334 CXDRVINFO_INIT = 0, 2335 CXDRVINFO_ROLE, 2336 CXDRVINFO_DBCC, 2337 CXDRVINFO_SMAP, 2338 CXDRVINFO_RFK, 2339 CXDRVINFO_RUN, 2340 CXDRVINFO_CTRL, 2341 CXDRVINFO_SCAN, 2342 CXDRVINFO_TRX, /* WL traffic to WL fw */ 2343 CXDRVINFO_MAX, 2344 }; 2345 2346 enum rtw89_scan_mode { 2347 RTW89_SCAN_IMMEDIATE, 2348 }; 2349 2350 enum rtw89_scan_type { 2351 RTW89_SCAN_ONCE, 2352 }; 2353 2354 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) 2355 { 2356 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)); 2357 } 2358 2359 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) 2360 { 2361 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)); 2362 } 2363 2364 struct rtw89_h2c_cxhdr { 2365 u8 type; 2366 u8 len; 2367 } __packed; 2368 2369 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr) 2370 2371 struct rtw89_h2c_cxinit { 2372 struct rtw89_h2c_cxhdr hdr; 2373 u8 ant_type; 2374 u8 ant_num; 2375 u8 ant_iso; 2376 u8 ant_info; 2377 u8 mod_rfe; 2378 u8 mod_cv; 2379 u8 mod_info; 2380 u8 mod_adie_kt; 2381 u8 wl_gch; 2382 u8 info; 2383 u8 rsvd; 2384 u8 rsvd1; 2385 } __packed; 2386 2387 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0) 2388 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1) 2389 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2) 2390 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4) 2391 2392 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0) 2393 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1) 2394 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2) 2395 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3) 2396 2397 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0) 2398 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1) 2399 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2) 2400 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3) 2401 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4) 2402 2403 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) 2404 { 2405 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 2406 } 2407 2408 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) 2409 { 2410 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 2411 } 2412 2413 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) 2414 { 2415 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)); 2416 } 2417 2418 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) 2419 { 2420 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)); 2421 } 2422 2423 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) 2424 { 2425 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)); 2426 } 2427 2428 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) 2429 { 2430 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)); 2431 } 2432 2433 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) 2434 { 2435 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)); 2436 } 2437 2438 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) 2439 { 2440 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)); 2441 } 2442 2443 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) 2444 { 2445 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)); 2446 } 2447 2448 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) 2449 { 2450 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); 2451 } 2452 2453 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) 2454 { 2455 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)); 2456 } 2457 2458 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) 2459 { 2460 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)); 2461 } 2462 2463 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) 2464 { 2465 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)); 2466 } 2467 2468 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) 2469 { 2470 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)); 2471 } 2472 2473 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset) 2474 { 2475 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); 2476 } 2477 2478 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset) 2479 { 2480 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1)); 2481 } 2482 2483 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset) 2484 { 2485 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); 2486 } 2487 2488 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset) 2489 { 2490 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); 2491 } 2492 2493 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset) 2494 { 2495 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); 2496 } 2497 2498 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset) 2499 { 2500 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); 2501 } 2502 2503 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset) 2504 { 2505 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); 2506 } 2507 2508 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset) 2509 { 2510 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); 2511 } 2512 2513 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset) 2514 { 2515 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); 2516 } 2517 2518 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset) 2519 { 2520 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0)); 2521 } 2522 2523 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset) 2524 { 2525 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0)); 2526 } 2527 2528 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset) 2529 { 2530 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0)); 2531 } 2532 2533 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset) 2534 { 2535 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0)); 2536 } 2537 2538 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset) 2539 { 2540 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0)); 2541 } 2542 2543 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset) 2544 { 2545 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); 2546 } 2547 2548 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset) 2549 { 2550 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1)); 2551 } 2552 2553 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset) 2554 { 2555 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); 2556 } 2557 2558 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset) 2559 { 2560 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); 2561 } 2562 2563 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset) 2564 { 2565 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); 2566 } 2567 2568 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset) 2569 { 2570 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); 2571 } 2572 2573 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset) 2574 { 2575 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); 2576 } 2577 2578 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset) 2579 { 2580 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); 2581 } 2582 2583 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset) 2584 { 2585 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); 2586 } 2587 2588 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset) 2589 { 2590 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0)); 2591 } 2592 2593 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset) 2594 { 2595 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0)); 2596 } 2597 2598 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset) 2599 { 2600 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0)); 2601 } 2602 2603 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset) 2604 { 2605 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0)); 2606 } 2607 2608 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset) 2609 { 2610 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1)); 2611 } 2612 2613 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset) 2614 { 2615 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2)); 2616 } 2617 2618 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset) 2619 { 2620 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4)); 2621 } 2622 2623 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) 2624 { 2625 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)); 2626 } 2627 2628 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) 2629 { 2630 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)); 2631 } 2632 2633 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) 2634 { 2635 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)); 2636 } 2637 2638 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) 2639 { 2640 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)); 2641 } 2642 2643 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val) 2644 { 2645 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0)); 2646 } 2647 2648 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val) 2649 { 2650 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0)); 2651 } 2652 2653 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val) 2654 { 2655 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0)); 2656 } 2657 2658 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val) 2659 { 2660 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0)); 2661 } 2662 2663 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val) 2664 { 2665 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0)); 2666 } 2667 2668 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val) 2669 { 2670 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0)); 2671 } 2672 2673 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val) 2674 { 2675 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0)); 2676 } 2677 2678 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val) 2679 { 2680 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0)); 2681 } 2682 2683 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val) 2684 { 2685 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0)); 2686 } 2687 2688 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val) 2689 { 2690 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0)); 2691 } 2692 2693 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val) 2694 { 2695 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0)); 2696 } 2697 2698 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val) 2699 { 2700 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0)); 2701 } 2702 2703 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val) 2704 { 2705 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0)); 2706 } 2707 2708 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val) 2709 { 2710 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0)); 2711 } 2712 2713 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val) 2714 { 2715 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0)); 2716 } 2717 2718 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val) 2719 { 2720 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0)); 2721 } 2722 2723 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val) 2724 { 2725 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0)); 2726 } 2727 2728 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) 2729 { 2730 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)); 2731 } 2732 2733 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) 2734 { 2735 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)); 2736 } 2737 2738 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) 2739 { 2740 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)); 2741 } 2742 2743 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) 2744 { 2745 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)); 2746 } 2747 2748 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) 2749 { 2750 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)); 2751 } 2752 2753 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val) 2754 { 2755 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2756 } 2757 2758 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val) 2759 { 2760 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8)); 2761 } 2762 2763 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val) 2764 { 2765 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16)); 2766 } 2767 2768 struct rtw89_h2c_chinfo_elem { 2769 __le32 w0; 2770 __le32 w1; 2771 __le32 w2; 2772 __le32 w3; 2773 __le32 w4; 2774 __le32 w5; 2775 __le32 w6; 2776 } __packed; 2777 2778 #define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0) 2779 #define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8) 2780 #define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16) 2781 #define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24) 2782 #define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0) 2783 #define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3) 2784 #define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8) 2785 #define RTW89_H2C_CHINFO_W1_TX BIT(12) 2786 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13) 2787 #define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14) 2788 #define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16) 2789 #define RTW89_H2C_CHINFO_W1_DFS BIT(24) 2790 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25) 2791 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26) 2792 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27) 2793 #define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0) 2794 #define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8) 2795 #define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16) 2796 #define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24) 2797 #define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0) 2798 #define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8) 2799 #define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16) 2800 #define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24) 2801 #define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0) 2802 2803 struct rtw89_h2c_chinfo_elem_be { 2804 __le32 w0; 2805 __le32 w1; 2806 __le32 w2; 2807 __le32 w3; 2808 __le32 w4; 2809 __le32 w5; 2810 __le32 w6; 2811 } __packed; 2812 2813 #define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0) 2814 #define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8) 2815 #define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16) 2816 #define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24) 2817 #define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0) 2818 #define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3) 2819 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5) 2820 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6) 2821 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7) 2822 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8) 2823 #define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9) 2824 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14) 2825 #define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15) 2826 #define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24) 2827 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0) 2828 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8) 2829 #define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16) 2830 #define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0) 2831 #define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8) 2832 #define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16) 2833 #define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24) 2834 #define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0) 2835 #define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8) 2836 #define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16) 2837 #define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24) 2838 #define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0) 2839 #define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16) 2840 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0) 2841 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16) 2842 2843 struct rtw89_h2c_chinfo { 2844 u8 ch_num; 2845 u8 elem_size; 2846 u8 arg; 2847 u8 rsvd0; 2848 struct rtw89_h2c_chinfo_elem elem[] __counted_by(ch_num); 2849 } __packed; 2850 2851 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0) 2852 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1) 2853 2854 struct rtw89_h2c_scanofld { 2855 __le32 w0; 2856 __le32 w1; 2857 __le32 w2; 2858 __le32 tsf_high; 2859 __le32 tsf_low; 2860 __le32 w5; 2861 __le32 w6; 2862 } __packed; 2863 2864 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0) 2865 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8) 2866 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16) 2867 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19) 2868 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20) 2869 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22) 2870 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0) 2871 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1) 2872 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2) 2873 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3) 2874 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5) 2875 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8) 2876 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16) 2877 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24) 2878 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0) 2879 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16) 2880 2881 struct rtw89_h2c_scanofld_be_macc_role { 2882 __le32 w0; 2883 } __packed; 2884 2885 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0) 2886 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2) 2887 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8) 2888 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24) 2889 2890 struct rtw89_h2c_scanofld_be_opch { 2891 __le32 w0; 2892 __le32 w1; 2893 __le32 w2; 2894 __le32 w3; 2895 } __packed; 2896 2897 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0) 2898 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16) 2899 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18) 2900 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21) 2901 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23) 2902 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24) 2903 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0) 2904 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8) 2905 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10) 2906 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13) 2907 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16) 2908 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24) 2909 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0) 2910 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8) 2911 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16) 2912 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0) 2913 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8) 2914 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16) 2915 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24) 2916 2917 struct rtw89_h2c_scanofld_be { 2918 __le32 w0; 2919 __le32 w1; 2920 __le32 w2; 2921 __le32 w3; 2922 __le32 w4; 2923 __le32 w5; 2924 __le32 w6; 2925 __le32 w7; 2926 struct rtw89_h2c_scanofld_be_macc_role role[]; 2927 } __packed; 2928 2929 #define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0) 2930 #define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2) 2931 #define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4) 2932 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6) 2933 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7) 2934 #define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8) 2935 #define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24) 2936 #define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27) 2937 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0) 2938 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8) 2939 #define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16) 2940 #define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0) 2941 #define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16) 2942 #define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24) 2943 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0) 2944 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8) 2945 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16) 2946 #define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24) 2947 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0) 2948 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8) 2949 #define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16) 2950 #define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0) 2951 #define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0) 2952 #define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0) 2953 2954 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val) 2955 { 2956 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2957 } 2958 2959 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val) 2960 { 2961 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8)); 2962 } 2963 2964 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val) 2965 { 2966 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12)); 2967 } 2968 2969 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val) 2970 { 2971 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16)); 2972 } 2973 2974 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val) 2975 { 2976 le32p_replace_bits((__le32 *)cmd, val, BIT(20)); 2977 } 2978 2979 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val) 2980 { 2981 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 2982 } 2983 2984 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val) 2985 { 2986 *((__le32 *)cmd + 1) = val; 2987 } 2988 2989 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val) 2990 { 2991 *((__le32 *)cmd + 2) = val; 2992 } 2993 2994 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val) 2995 { 2996 *((__le32 *)cmd + 3) = val; 2997 } 2998 2999 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val) 3000 { 3001 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0)); 3002 } 3003 3004 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val) 3005 { 3006 u8 ctwnd; 3007 3008 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT)) 3009 return; 3010 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val); 3011 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8)); 3012 } 3013 3014 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val) 3015 { 3016 le32p_replace_bits((__le32 *)cmd, val, BIT(0)); 3017 } 3018 3019 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val) 3020 { 3021 le32p_replace_bits((__le32 *)cmd, val, BIT(1)); 3022 } 3023 3024 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val) 3025 { 3026 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2)); 3027 } 3028 3029 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val) 3030 { 3031 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16)); 3032 } 3033 3034 enum rtw89_fw_mcc_c2h_rpt_cfg { 3035 RTW89_FW_MCC_C2H_RPT_OFF = 0, 3036 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1, 3037 RTW89_FW_MCC_C2H_RPT_ALL = 2, 3038 }; 3039 3040 struct rtw89_fw_mcc_add_req { 3041 u8 macid; 3042 u8 central_ch_seg0; 3043 u8 central_ch_seg1; 3044 u8 primary_ch; 3045 enum rtw89_bandwidth bandwidth: 4; 3046 u32 group: 2; 3047 u32 c2h_rpt: 2; 3048 u32 dis_tx_null: 1; 3049 u32 dis_sw_retry: 1; 3050 u32 in_curr_ch: 1; 3051 u32 sw_retry_count: 3; 3052 u32 tx_null_early: 4; 3053 u32 btc_in_2g: 1; 3054 u32 pta_en: 1; 3055 u32 rfk_by_pass: 1; 3056 u32 ch_band_type: 2; 3057 u32 rsvd0: 9; 3058 u32 duration; 3059 u8 courtesy_en; 3060 u8 courtesy_num; 3061 u8 courtesy_target; 3062 u8 rsvd1; 3063 }; 3064 3065 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val) 3066 { 3067 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 3068 } 3069 3070 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val) 3071 { 3072 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3073 } 3074 3075 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val) 3076 { 3077 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3078 } 3079 3080 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val) 3081 { 3082 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3083 } 3084 3085 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val) 3086 { 3087 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0)); 3088 } 3089 3090 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val) 3091 { 3092 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4)); 3093 } 3094 3095 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val) 3096 { 3097 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6)); 3098 } 3099 3100 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val) 3101 { 3102 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8)); 3103 } 3104 3105 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val) 3106 { 3107 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9)); 3108 } 3109 3110 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val) 3111 { 3112 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10)); 3113 } 3114 3115 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val) 3116 { 3117 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11)); 3118 } 3119 3120 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val) 3121 { 3122 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14)); 3123 } 3124 3125 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val) 3126 { 3127 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18)); 3128 } 3129 3130 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val) 3131 { 3132 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19)); 3133 } 3134 3135 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val) 3136 { 3137 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20)); 3138 } 3139 3140 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val) 3141 { 3142 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21)); 3143 } 3144 3145 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val) 3146 { 3147 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 3148 } 3149 3150 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val) 3151 { 3152 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0)); 3153 } 3154 3155 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val) 3156 { 3157 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8)); 3158 } 3159 3160 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val) 3161 { 3162 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16)); 3163 } 3164 3165 enum rtw89_fw_mcc_old_group_actions { 3166 RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0, 3167 RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1, 3168 }; 3169 3170 struct rtw89_fw_mcc_start_req { 3171 u32 group: 2; 3172 u32 btc_in_group: 1; 3173 u32 old_group_action: 2; 3174 u32 old_group: 2; 3175 u32 rsvd0: 9; 3176 u32 notify_cnt: 3; 3177 u32 rsvd1: 2; 3178 u32 notify_rxdbg_en: 1; 3179 u32 rsvd2: 2; 3180 u32 macid: 8; 3181 u32 tsf_low; 3182 u32 tsf_high; 3183 }; 3184 3185 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val) 3186 { 3187 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3188 } 3189 3190 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val) 3191 { 3192 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3193 } 3194 3195 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val) 3196 { 3197 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3)); 3198 } 3199 3200 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val) 3201 { 3202 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5)); 3203 } 3204 3205 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val) 3206 { 3207 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16)); 3208 } 3209 3210 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val) 3211 { 3212 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 3213 } 3214 3215 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val) 3216 { 3217 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3218 } 3219 3220 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val) 3221 { 3222 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 3223 } 3224 3225 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val) 3226 { 3227 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 3228 } 3229 3230 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val) 3231 { 3232 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 3233 } 3234 3235 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val) 3236 { 3237 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8)); 3238 } 3239 3240 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val) 3241 { 3242 le32p_replace_bits((__le32 *)cmd, val, BIT(10)); 3243 } 3244 3245 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val) 3246 { 3247 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3248 } 3249 3250 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val) 3251 { 3252 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3253 } 3254 3255 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val) 3256 { 3257 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3258 } 3259 3260 struct rtw89_fw_mcc_tsf_req { 3261 u8 group: 2; 3262 u8 rsvd0: 6; 3263 u8 macid_x; 3264 u8 macid_y; 3265 u8 rsvd1; 3266 }; 3267 3268 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val) 3269 { 3270 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3271 } 3272 3273 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val) 3274 { 3275 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3276 } 3277 3278 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val) 3279 { 3280 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3281 } 3282 3283 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val) 3284 { 3285 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3286 } 3287 3288 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val) 3289 { 3290 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3291 } 3292 3293 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val) 3294 { 3295 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3296 } 3297 3298 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd, 3299 u8 *bitmap, u8 len) 3300 { 3301 memcpy((__le32 *)cmd + 1, bitmap, len); 3302 } 3303 3304 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val) 3305 { 3306 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3307 } 3308 3309 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val) 3310 { 3311 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3312 } 3313 3314 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val) 3315 { 3316 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3317 } 3318 3319 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val) 3320 { 3321 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3322 } 3323 3324 struct rtw89_fw_mcc_duration { 3325 u32 group: 2; 3326 u32 btc_in_group: 1; 3327 u32 rsvd0: 5; 3328 u32 start_macid: 8; 3329 u32 macid_x: 8; 3330 u32 macid_y: 8; 3331 u32 start_tsf_low; 3332 u32 start_tsf_high; 3333 u32 duration_x; 3334 u32 duration_y; 3335 }; 3336 3337 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val) 3338 { 3339 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3340 } 3341 3342 static 3343 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val) 3344 { 3345 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3346 } 3347 3348 static 3349 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val) 3350 { 3351 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3352 } 3353 3354 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val) 3355 { 3356 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3357 } 3358 3359 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val) 3360 { 3361 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3362 } 3363 3364 static 3365 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val) 3366 { 3367 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 3368 } 3369 3370 static 3371 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val) 3372 { 3373 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 3374 } 3375 3376 static 3377 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val) 3378 { 3379 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 3380 } 3381 3382 static 3383 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val) 3384 { 3385 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 3386 } 3387 3388 enum rtw89_h2c_mrc_sch_types { 3389 RTW89_H2C_MRC_SCH_BAND0_ONLY = 0, 3390 RTW89_H2C_MRC_SCH_BAND1_ONLY = 1, 3391 RTW89_H2C_MRC_SCH_DUAL_BAND = 2, 3392 }; 3393 3394 enum rtw89_h2c_mrc_role_types { 3395 RTW89_H2C_MRC_ROLE_WIFI = 0, 3396 RTW89_H2C_MRC_ROLE_BT = 1, 3397 RTW89_H2C_MRC_ROLE_EMPTY = 2, 3398 }; 3399 3400 #define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM 3 3401 #define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT 1 /* before MLO */ 3402 3403 struct rtw89_fw_mrc_add_slot_arg { 3404 u16 duration; /* unit: TU */ 3405 bool courtesy_en; 3406 u8 courtesy_period; 3407 u8 courtesy_target; /* slot idx */ 3408 3409 unsigned int role_num; 3410 struct { 3411 enum rtw89_h2c_mrc_role_types role_type; 3412 bool is_master; 3413 bool en_tx_null; 3414 enum rtw89_band band; 3415 enum rtw89_bandwidth bw; 3416 u8 macid; 3417 u8 central_ch; 3418 u8 primary_ch; 3419 u8 null_early; /* unit: TU */ 3420 3421 /* if MLD, for macid: [0, chip::support_mld_num) 3422 * otherwise, for macid: [0, 32) 3423 */ 3424 u32 macid_main_bitmap; 3425 /* for MLD, bit X maps to macid: X + chip::support_mld_num */ 3426 u32 macid_paired_bitmap; 3427 } roles[RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT]; 3428 }; 3429 3430 struct rtw89_fw_mrc_add_arg { 3431 u8 sch_idx; 3432 enum rtw89_h2c_mrc_sch_types sch_type; 3433 bool btc_in_sch; 3434 3435 unsigned int slot_num; 3436 struct rtw89_fw_mrc_add_slot_arg slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM]; 3437 }; 3438 3439 struct rtw89_h2c_mrc_add_role { 3440 __le32 w0; 3441 __le32 w1; 3442 __le32 w2; 3443 __le32 macid_main_bitmap; 3444 __le32 macid_paired_bitmap; 3445 } __packed; 3446 3447 #define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0) 3448 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16) 3449 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24) 3450 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25) 3451 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26) 3452 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27) 3453 #define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0) 3454 #define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8) 3455 #define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16) 3456 #define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20) 3457 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22) 3458 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23) 3459 #define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24) 3460 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0) 3461 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8) 3462 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16) 3463 3464 struct rtw89_h2c_mrc_add_slot { 3465 __le32 w0; 3466 __le32 w1; 3467 struct rtw89_h2c_mrc_add_role roles[]; 3468 } __packed; 3469 3470 #define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0) 3471 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17) 3472 #define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24) 3473 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0) 3474 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8) 3475 3476 struct rtw89_h2c_mrc_add { 3477 __le32 w0; 3478 /* Logically append flexible struct rtw89_h2c_mrc_add_slot, but there 3479 * are other flexible array inside it. We cannot access them correctly 3480 * through this struct. So, in case misusing, we don't really declare 3481 * it here. 3482 */ 3483 } __packed; 3484 3485 #define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0) 3486 #define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4) 3487 #define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8) 3488 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16) 3489 3490 enum rtw89_h2c_mrc_start_actions { 3491 RTW89_H2C_MRC_START_ACTION_START_NEW = 0, 3492 RTW89_H2C_MRC_START_ACTION_REPLACE_OLD = 1, 3493 }; 3494 3495 struct rtw89_fw_mrc_start_arg { 3496 u8 sch_idx; 3497 u8 old_sch_idx; 3498 u64 start_tsf; 3499 enum rtw89_h2c_mrc_start_actions action; 3500 }; 3501 3502 struct rtw89_h2c_mrc_start { 3503 __le32 w0; 3504 __le32 start_tsf_low; 3505 __le32 start_tsf_high; 3506 } __packed; 3507 3508 #define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0) 3509 #define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4) 3510 #define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8) 3511 3512 struct rtw89_h2c_mrc_del { 3513 __le32 w0; 3514 } __packed; 3515 3516 #define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0) 3517 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4) 3518 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5) 3519 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6) 3520 #define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8) 3521 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16) 3522 3523 #define RTW89_MAC_MRC_MAX_REQ_TSF_NUM 2 3524 3525 struct rtw89_fw_mrc_req_tsf_arg { 3526 unsigned int num; 3527 struct { 3528 u8 band; 3529 u8 port; 3530 } infos[RTW89_MAC_MRC_MAX_REQ_TSF_NUM]; 3531 }; 3532 3533 struct rtw89_h2c_mrc_req_tsf { 3534 u8 req_tsf_num; 3535 u8 infos[] __counted_by(req_tsf_num); 3536 } __packed; 3537 3538 #define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0) 3539 #define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4) 3540 3541 enum rtw89_h2c_mrc_upd_bitmap_actions { 3542 RTW89_H2C_MRC_UPD_BITMAP_ACTION_DEL = 0, 3543 RTW89_H2C_MRC_UPD_BITMAP_ACTION_ADD = 1, 3544 }; 3545 3546 struct rtw89_fw_mrc_upd_bitmap_arg { 3547 u8 sch_idx; 3548 u8 macid; 3549 u8 client_macid; 3550 enum rtw89_h2c_mrc_upd_bitmap_actions action; 3551 }; 3552 3553 struct rtw89_h2c_mrc_upd_bitmap { 3554 __le32 w0; 3555 __le32 w1; 3556 } __packed; 3557 3558 #define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0) 3559 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4) 3560 #define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16) 3561 #define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0) 3562 3563 struct rtw89_fw_mrc_sync_arg { 3564 u8 offset; /* unit: TU */ 3565 struct { 3566 u8 band; 3567 u8 port; 3568 } src, dest; 3569 }; 3570 3571 struct rtw89_h2c_mrc_sync { 3572 __le32 w0; 3573 __le32 w1; 3574 } __packed; 3575 3576 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0) 3577 #define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8) 3578 #define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12) 3579 #define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16) 3580 #define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20) 3581 #define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0) 3582 3583 struct rtw89_fw_mrc_upd_duration_arg { 3584 u8 sch_idx; 3585 u64 start_tsf; 3586 3587 unsigned int slot_num; 3588 struct { 3589 u8 slot_idx; 3590 u16 duration; /* unit: TU */ 3591 } slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM]; 3592 }; 3593 3594 struct rtw89_h2c_mrc_upd_duration { 3595 __le32 w0; 3596 __le32 start_tsf_low; 3597 __le32 start_tsf_high; 3598 __le32 slots[]; 3599 } __packed; 3600 3601 #define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0) 3602 #define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8) 3603 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16) 3604 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0) 3605 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16) 3606 3607 #define RTW89_C2H_HEADER_LEN 8 3608 3609 struct rtw89_c2h_hdr { 3610 __le32 w0; 3611 __le32 w1; 3612 } __packed; 3613 3614 #define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0) 3615 #define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2) 3616 #define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8) 3617 #define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0) 3618 3619 struct rtw89_fw_c2h_attr { 3620 u8 category; 3621 u8 class; 3622 u8 func; 3623 u16 len; 3624 }; 3625 3626 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb) 3627 { 3628 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr)); 3629 3630 return (struct rtw89_fw_c2h_attr *)skb->cb; 3631 } 3632 3633 struct rtw89_c2h_done_ack { 3634 __le32 w0; 3635 __le32 w1; 3636 __le32 w2; 3637 } __packed; 3638 3639 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0) 3640 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2) 3641 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8) 3642 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16) 3643 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24) 3644 3645 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ 3646 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3647 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ 3648 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3649 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ 3650 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3651 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ 3652 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3653 3654 struct rtw89_fw_c2h_log_fmt { 3655 __le16 signature; 3656 u8 feature; 3657 u8 syntax; 3658 __le32 fmt_id; 3659 u8 file_num; 3660 __le16 line_num; 3661 u8 argc; 3662 union { 3663 DECLARE_FLEX_ARRAY(u8, raw); 3664 DECLARE_FLEX_ARRAY(__le32, argv); 3665 } __packed u; 3666 } __packed; 3667 3668 #define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11 3669 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2) 3670 #define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16 3671 #define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5 3672 #define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512 3673 3674 struct rtw89_c2h_mac_bcnfltr_rpt { 3675 __le32 w0; 3676 __le32 w1; 3677 __le32 w2; 3678 } __packed; 3679 3680 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0) 3681 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8) 3682 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10) 3683 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16) 3684 3685 struct rtw89_c2h_ra_rpt { 3686 struct rtw89_c2h_hdr hdr; 3687 __le32 w2; 3688 __le32 w3; 3689 } __packed; 3690 3691 #define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0) 3692 #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16) 3693 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31) 3694 #define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0) 3695 #define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8) 3696 #define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10) 3697 #define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13) 3698 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15) 3699 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16) 3700 3701 /* For WiFi 6 chips: 3702 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS 3703 * HT-new: [6:5]: NA, [4:0]: MCS 3704 * For WiFi 7 chips (V1): 3705 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS 3706 */ 3707 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) 3708 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) 3709 #define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5) 3710 #define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0) 3711 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0) 3712 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ 3713 FIELD_PREP(GENMASK(2, 0), mcs)) 3714 3715 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \ 3716 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3717 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \ 3718 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8)) 3719 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \ 3720 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16)) 3721 3722 struct rtw89_c2h_scanofld { 3723 __le32 w0; 3724 __le32 w1; 3725 __le32 w2; 3726 __le32 w3; 3727 __le32 w4; 3728 __le32 w5; 3729 __le32 w6; 3730 __le32 w7; 3731 } __packed; 3732 3733 #define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0) 3734 #define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16) 3735 #define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20) 3736 #define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24) 3737 #define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0) 3738 #define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4) 3739 #define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24) 3740 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26) 3741 #define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0) 3742 #define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8) 3743 #define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16) 3744 #define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0) 3745 3746 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \ 3747 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3748 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \ 3749 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3750 3751 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \ 3752 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3753 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \ 3754 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3755 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \ 3756 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3757 3758 struct rtw89_mac_mcc_tsf_rpt { 3759 u32 macid_x; 3760 u32 macid_y; 3761 u32 tsf_x_low; 3762 u32 tsf_x_high; 3763 u32 tsf_y_low; 3764 u32 tsf_y_high; 3765 }; 3766 3767 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE); 3768 3769 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \ 3770 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3771 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \ 3772 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3773 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \ 3774 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16)) 3775 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \ 3776 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0)) 3777 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \ 3778 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0)) 3779 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \ 3780 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0)) 3781 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \ 3782 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0)) 3783 3784 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \ 3785 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0)) 3786 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \ 3787 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6)) 3788 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \ 3789 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3790 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \ 3791 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0)) 3792 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \ 3793 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0)) 3794 3795 struct rtw89_mac_mrc_tsf_rpt { 3796 unsigned int num; 3797 u64 tsfs[RTW89_MAC_MRC_MAX_REQ_TSF_NUM]; 3798 }; 3799 3800 static_assert(sizeof(struct rtw89_mac_mrc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE); 3801 3802 struct rtw89_c2h_mrc_tsf_rpt_info { 3803 __le32 tsf_low; 3804 __le32 tsf_high; 3805 } __packed; 3806 3807 struct rtw89_c2h_mrc_tsf_rpt { 3808 struct rtw89_c2h_hdr hdr; 3809 __le32 w2; 3810 struct rtw89_c2h_mrc_tsf_rpt_info infos[]; 3811 } __packed; 3812 3813 #define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0) 3814 3815 struct rtw89_c2h_mrc_status_rpt { 3816 struct rtw89_c2h_hdr hdr; 3817 __le32 w2; 3818 __le32 tsf_low; 3819 __le32 tsf_high; 3820 } __packed; 3821 3822 #define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0) 3823 #define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6) 3824 3825 struct rtw89_c2h_pkt_ofld_rsp { 3826 __le32 w0; 3827 __le32 w1; 3828 __le32 w2; 3829 } __packed; 3830 3831 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0) 3832 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8) 3833 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16) 3834 3835 struct rtw89_h2c_bcnfltr { 3836 __le32 w0; 3837 } __packed; 3838 3839 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0) 3840 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1) 3841 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2) 3842 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3) 3843 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8) 3844 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12) 3845 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16) 3846 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24) 3847 3848 struct rtw89_h2c_ofld_rssi { 3849 __le32 w0; 3850 __le32 w1; 3851 } __packed; 3852 3853 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0) 3854 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8) 3855 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0) 3856 3857 struct rtw89_h2c_ofld { 3858 __le32 w0; 3859 } __packed; 3860 3861 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0) 3862 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8) 3863 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18) 3864 3865 #define RTW89_MFW_SIG 0xFF 3866 3867 struct rtw89_mfw_info { 3868 u8 cv; 3869 u8 type; /* enum rtw89_fw_type */ 3870 u8 mp; 3871 u8 rsvd; 3872 __le32 shift; 3873 __le32 size; 3874 u8 rsvd2[4]; 3875 } __packed; 3876 3877 struct rtw89_mfw_hdr { 3878 u8 sig; /* RTW89_MFW_SIG */ 3879 u8 fw_nr; 3880 u8 rsvd0[2]; 3881 struct { 3882 u8 major; 3883 u8 minor; 3884 u8 sub; 3885 u8 idx; 3886 } ver; 3887 u8 rsvd1[8]; 3888 struct rtw89_mfw_info info[]; 3889 } __packed; 3890 3891 struct rtw89_fw_logsuit_hdr { 3892 __le32 rsvd; 3893 __le32 count; 3894 __le32 ids[]; 3895 } __packed; 3896 3897 #define RTW89_FW_ELEMENT_ALIGN 16 3898 3899 enum rtw89_fw_element_id { 3900 RTW89_FW_ELEMENT_ID_BBMCU0 = 0, 3901 RTW89_FW_ELEMENT_ID_BBMCU1 = 1, 3902 RTW89_FW_ELEMENT_ID_BB_REG = 2, 3903 RTW89_FW_ELEMENT_ID_BB_GAIN = 3, 3904 RTW89_FW_ELEMENT_ID_RADIO_A = 4, 3905 RTW89_FW_ELEMENT_ID_RADIO_B = 5, 3906 RTW89_FW_ELEMENT_ID_RADIO_C = 6, 3907 RTW89_FW_ELEMENT_ID_RADIO_D = 7, 3908 RTW89_FW_ELEMENT_ID_RF_NCTL = 8, 3909 RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9, 3910 RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10, 3911 RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11, 3912 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12, 3913 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13, 3914 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14, 3915 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15, 3916 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16, 3917 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17, 3918 RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18, 3919 RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19, 3920 3921 RTW89_FW_ELEMENT_ID_NUM, 3922 }; 3923 3924 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \ 3925 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \ 3926 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \ 3927 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \ 3928 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \ 3929 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \ 3930 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \ 3931 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ) | \ 3932 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \ 3933 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU)) 3934 3935 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \ 3936 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \ 3937 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \ 3938 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \ 3939 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \ 3940 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \ 3941 BITS_OF_RTW89_TXPWR_FW_ELEMENTS) 3942 3943 struct __rtw89_fw_txpwr_element { 3944 u8 rsvd0; 3945 u8 rsvd1; 3946 u8 rfe_type; 3947 u8 ent_sz; 3948 __le32 num_ents; 3949 u8 content[]; 3950 } __packed; 3951 3952 enum rtw89_fw_txpwr_trk_type { 3953 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0, 3954 RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0, 3955 RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1, 3956 RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2, 3957 RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3, 3958 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3, 3959 3960 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4, 3961 RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4, 3962 RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5, 3963 RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6, 3964 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7, 3965 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7, 3966 3967 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8, 3968 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8, 3969 RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9, 3970 RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10, 3971 RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11, 3972 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12, 3973 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13, 3974 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14, 3975 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15, 3976 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15, 3977 3978 RTW89_FW_TXPWR_TRK_TYPE_NR, 3979 }; 3980 3981 struct rtw89_fw_txpwr_track_cfg { 3982 const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE]; 3983 }; 3984 3985 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \ 3986 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \ 3987 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \ 3988 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \ 3989 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P)) 3990 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \ 3991 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \ 3992 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \ 3993 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \ 3994 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P)) 3995 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \ 3996 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \ 3997 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \ 3998 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \ 3999 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \ 4000 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \ 4001 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \ 4002 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \ 4003 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P)) 4004 4005 struct rtw89_fw_element_hdr { 4006 __le32 id; /* enum rtw89_fw_element_id */ 4007 __le32 size; /* exclude header size */ 4008 u8 ver[4]; 4009 __le32 rsvd0; 4010 __le32 rsvd1; 4011 __le32 rsvd2; 4012 union { 4013 struct { 4014 u8 priv[8]; 4015 u8 contents[]; 4016 } __packed common; 4017 struct { 4018 u8 idx; 4019 u8 rsvd[7]; 4020 struct { 4021 __le32 addr; 4022 __le32 data; 4023 } __packed regs[]; 4024 } __packed reg2; 4025 struct { 4026 u8 cv; 4027 u8 priv[7]; 4028 u8 contents[]; 4029 } __packed bbmcu; 4030 struct { 4031 __le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */ 4032 __le32 rsvd; 4033 s8 contents[][DELTA_SWINGIDX_SIZE]; 4034 } __packed txpwr_trk; 4035 struct { 4036 u8 nr; 4037 u8 rsvd[3]; 4038 u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */ 4039 u8 rsvd1[3]; 4040 __le16 offset[]; 4041 } __packed rfk_log_fmt; 4042 struct __rtw89_fw_txpwr_element txpwr; 4043 } __packed u; 4044 } __packed; 4045 4046 struct fwcmd_hdr { 4047 __le32 hdr0; 4048 __le32 hdr1; 4049 }; 4050 4051 union rtw89_compat_fw_hdr { 4052 struct rtw89_mfw_hdr mfw_hdr; 4053 struct rtw89_fw_hdr fw_hdr; 4054 }; 4055 4056 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf) 4057 { 4058 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf; 4059 4060 if (compat->mfw_hdr.sig == RTW89_MFW_SIG) 4061 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr); 4062 else 4063 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr); 4064 } 4065 4066 static inline void rtw89_fw_get_filename(char *buf, size_t size, 4067 const char *fw_basename, int fw_format) 4068 { 4069 if (fw_format <= 0) 4070 snprintf(buf, size, "%s.bin", fw_basename); 4071 else 4072 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format); 4073 } 4074 4075 #define RTW89_H2C_RF_PAGE_SIZE 500 4076 #define RTW89_H2C_RF_PAGE_NUM 3 4077 struct rtw89_fw_h2c_rf_reg_info { 4078 enum rtw89_rf_path rf_path; 4079 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; 4080 u16 curr_idx; 4081 }; 4082 4083 #define H2C_SEC_CAM_LEN 24 4084 4085 #define H2C_HEADER_LEN 8 4086 #define H2C_HDR_CAT GENMASK(1, 0) 4087 #define H2C_HDR_CLASS GENMASK(7, 2) 4088 #define H2C_HDR_FUNC GENMASK(15, 8) 4089 #define H2C_HDR_DEL_TYPE GENMASK(19, 16) 4090 #define H2C_HDR_H2C_SEQ GENMASK(31, 24) 4091 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0) 4092 #define H2C_HDR_REC_ACK BIT(14) 4093 #define H2C_HDR_DONE_ACK BIT(15) 4094 4095 #define FWCMD_TYPE_H2C 0 4096 4097 #define H2C_CAT_TEST 0x0 4098 4099 /* CLASS 5 - FW STATUS TEST */ 4100 #define H2C_CL_FW_STATUS_TEST 0x5 4101 #define H2C_FUNC_CPU_EXCEPTION 0x1 4102 4103 #define H2C_CAT_MAC 0x1 4104 4105 /* CLASS 0 - FW INFO */ 4106 #define H2C_CL_FW_INFO 0x0 4107 #define H2C_FUNC_LOG_CFG 0x0 4108 #define H2C_FUNC_MAC_GENERAL_PKT 0x1 4109 4110 /* CLASS 1 - WOW */ 4111 #define H2C_CL_MAC_WOW 0x1 4112 #define H2C_FUNC_KEEP_ALIVE 0x0 4113 #define H2C_FUNC_DISCONNECT_DETECT 0x1 4114 #define H2C_FUNC_WOW_GLOBAL 0x2 4115 #define H2C_FUNC_WAKEUP_CTRL 0x8 4116 #define H2C_FUNC_WOW_CAM_UPD 0xC 4117 4118 /* CLASS 2 - PS */ 4119 #define H2C_CL_MAC_PS 0x2 4120 #define H2C_FUNC_MAC_LPS_PARM 0x0 4121 #define H2C_FUNC_P2P_ACT 0x1 4122 4123 /* CLASS 3 - FW download */ 4124 #define H2C_CL_MAC_FWDL 0x3 4125 #define H2C_FUNC_MAC_FWHDR_DL 0x0 4126 4127 /* CLASS 5 - Frame Exchange */ 4128 #define H2C_CL_MAC_FR_EXCHG 0x5 4129 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2 4130 #define H2C_FUNC_MAC_BCN_UPD 0x5 4131 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9 4132 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa 4133 #define H2C_FUNC_MAC_DCTLINFO_UD_V2 0xc 4134 #define H2C_FUNC_MAC_BCN_UPD_BE 0xd 4135 #define H2C_FUNC_MAC_CCTLINFO_UD_G7 0x11 4136 4137 /* CLASS 6 - Address CAM */ 4138 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 4139 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 4140 4141 /* CLASS 8 - Media Status Report */ 4142 #define H2C_CL_MAC_MEDIA_RPT 0x8 4143 #define H2C_FUNC_MAC_JOININFO 0x0 4144 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 4145 #define H2C_FUNC_NOTIFY_DBCC 0x5 4146 4147 /* CLASS 9 - FW offload */ 4148 #define H2C_CL_MAC_FW_OFLD 0x9 4149 enum rtw89_fw_ofld_h2c_func { 4150 H2C_FUNC_PACKET_OFLD = 0x1, 4151 H2C_FUNC_MAC_MACID_PAUSE = 0x8, 4152 H2C_FUNC_USR_EDCA = 0xF, 4153 H2C_FUNC_TSF32_TOGL = 0x10, 4154 H2C_FUNC_OFLD_CFG = 0x14, 4155 H2C_FUNC_ADD_SCANOFLD_CH = 0x16, 4156 H2C_FUNC_SCANOFLD = 0x17, 4157 H2C_FUNC_PKT_DROP = 0x1b, 4158 H2C_FUNC_CFG_BCNFLTR = 0x1e, 4159 H2C_FUNC_OFLD_RSSI = 0x1f, 4160 H2C_FUNC_OFLD_TP = 0x20, 4161 H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28, 4162 H2C_FUNC_SCANOFLD_BE = 0x2c, 4163 4164 NUM_OF_RTW89_FW_OFLD_H2C_FUNC, 4165 }; 4166 4167 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \ 4168 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func)) 4169 4170 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \ 4171 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \ 4172 H2C_FUNC_PACKET_OFLD) 4173 4174 #define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH) 4175 4176 #define RTW89_SCANOFLD_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD) 4177 #define RTW89_SCANOFLD_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD) 4178 #define RTW89_SCANOFLD_BE_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD_BE) 4179 #define RTW89_SCANOFLD_BE_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD_BE) 4180 4181 4182 /* CLASS 10 - Security CAM */ 4183 #define H2C_CL_MAC_SEC_CAM 0xa 4184 #define H2C_FUNC_MAC_SEC_UPD 0x1 4185 4186 /* CLASS 12 - BA CAM */ 4187 #define H2C_CL_BA_CAM 0xc 4188 #define H2C_FUNC_MAC_BA_CAM 0x0 4189 #define H2C_FUNC_MAC_BA_CAM_V1 0x1 4190 #define H2C_FUNC_MAC_BA_CAM_INIT 0x2 4191 4192 /* CLASS 14 - MCC */ 4193 #define H2C_CL_MCC 0xe 4194 enum rtw89_mcc_h2c_func { 4195 H2C_FUNC_ADD_MCC = 0x0, 4196 H2C_FUNC_START_MCC = 0x1, 4197 H2C_FUNC_STOP_MCC = 0x2, 4198 H2C_FUNC_DEL_MCC_GROUP = 0x3, 4199 H2C_FUNC_RESET_MCC_GROUP = 0x4, 4200 H2C_FUNC_MCC_REQ_TSF = 0x5, 4201 H2C_FUNC_MCC_MACID_BITMAP = 0x6, 4202 H2C_FUNC_MCC_SYNC = 0x7, 4203 H2C_FUNC_MCC_SET_DURATION = 0x8, 4204 4205 NUM_OF_RTW89_MCC_H2C_FUNC, 4206 }; 4207 4208 #define RTW89_MCC_WAIT_COND(group, func) \ 4209 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func)) 4210 4211 /* CLASS 24 - MRC */ 4212 #define H2C_CL_MRC 0x18 4213 enum rtw89_mrc_h2c_func { 4214 H2C_FUNC_MRC_REQ_TSF = 0x0, 4215 H2C_FUNC_ADD_MRC = 0x1, 4216 H2C_FUNC_START_MRC = 0x2, 4217 H2C_FUNC_DEL_MRC = 0x3, 4218 H2C_FUNC_MRC_SYNC = 0x4, 4219 H2C_FUNC_MRC_UPD_DURATION = 0x5, 4220 H2C_FUNC_MRC_UPD_BITMAP = 0x6, 4221 4222 NUM_OF_RTW89_MRC_H2C_FUNC, 4223 }; 4224 4225 /* can consider MRC's sch_idx as MCC's group */ 4226 #define RTW89_MRC_WAIT_COND(sch_idx, func) \ 4227 ((sch_idx) * NUM_OF_RTW89_MRC_H2C_FUNC + (func)) 4228 4229 #define RTW89_MRC_WAIT_COND_REQ_TSF \ 4230 RTW89_MRC_WAIT_COND(0 /* don't care */, H2C_FUNC_MRC_REQ_TSF) 4231 4232 #define H2C_CAT_OUTSRC 0x2 4233 4234 #define H2C_CL_OUTSRC_RA 0x1 4235 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 4236 4237 #define H2C_CL_OUTSRC_DM 0x2 4238 #define H2C_FUNC_FW_LPS_CH_INFO 0xb 4239 4240 #define H2C_CL_OUTSRC_RF_REG_A 0x8 4241 #define H2C_CL_OUTSRC_RF_REG_B 0x9 4242 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa 4243 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2 4244 #define H2C_CL_OUTSRC_RF_FW_RFK 0xb 4245 4246 enum rtw89_rfk_offload_h2c_func { 4247 H2C_FUNC_RFK_TSSI_OFFLOAD = 0x0, 4248 H2C_FUNC_RFK_IQK_OFFLOAD = 0x1, 4249 H2C_FUNC_RFK_DPK_OFFLOAD = 0x3, 4250 H2C_FUNC_RFK_TXGAPK_OFFLOAD = 0x4, 4251 H2C_FUNC_RFK_DACK_OFFLOAD = 0x5, 4252 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6, 4253 H2C_FUNC_RFK_PRE_NOTIFY = 0x8, 4254 }; 4255 4256 struct rtw89_fw_h2c_rf_get_mccch { 4257 __le32 ch_0; 4258 __le32 ch_1; 4259 __le32 band_0; 4260 __le32 band_1; 4261 __le32 current_channel; 4262 __le32 current_band_type; 4263 } __packed; 4264 4265 #define NUM_OF_RTW89_FW_RFK_PATH 2 4266 #define NUM_OF_RTW89_FW_RFK_TBL 3 4267 4268 struct rtw89_fw_h2c_rfk_pre_info { 4269 struct { 4270 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL]; 4271 __le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL]; 4272 } __packed dbcc; 4273 4274 __le32 mlo_mode; 4275 struct { 4276 __le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH]; 4277 __le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH]; 4278 } __packed tbl; 4279 4280 __le32 phy_idx; 4281 __le32 cur_band; 4282 __le32 cur_bw; 4283 __le32 cur_center_ch; 4284 4285 __le32 ktbl_sel0; 4286 __le32 ktbl_sel1; 4287 __le32 rfmod0; 4288 __le32 rfmod1; 4289 4290 __le32 mlo_1_1; 4291 __le32 rfe_type; 4292 __le32 drv_mode; 4293 4294 struct { 4295 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH]; 4296 __le32 band[NUM_OF_RTW89_FW_RFK_PATH]; 4297 } __packed mlo; 4298 } __packed; 4299 4300 struct rtw89_h2c_rf_tssi { 4301 __le16 len; 4302 u8 phy; 4303 u8 ch; 4304 u8 bw; 4305 u8 band; 4306 u8 hwtx_en; 4307 u8 cv; 4308 s8 curr_tssi_cck_de[2]; 4309 s8 curr_tssi_cck_de_20m[2]; 4310 s8 curr_tssi_cck_de_40m[2]; 4311 s8 curr_tssi_efuse_cck_de[2]; 4312 s8 curr_tssi_ofdm_de[2]; 4313 s8 curr_tssi_ofdm_de_20m[2]; 4314 s8 curr_tssi_ofdm_de_40m[2]; 4315 s8 curr_tssi_ofdm_de_80m[2]; 4316 s8 curr_tssi_ofdm_de_160m[2]; 4317 s8 curr_tssi_ofdm_de_320m[2]; 4318 s8 curr_tssi_efuse_ofdm_de[2]; 4319 s8 curr_tssi_ofdm_de_diff_20m[2]; 4320 s8 curr_tssi_ofdm_de_diff_80m[2]; 4321 s8 curr_tssi_ofdm_de_diff_160m[2]; 4322 s8 curr_tssi_ofdm_de_diff_320m[2]; 4323 s8 curr_tssi_trim_de[2]; 4324 u8 pg_thermal[2]; 4325 u8 ftable[2][128]; 4326 u8 tssi_mode; 4327 } __packed; 4328 4329 struct rtw89_h2c_rf_iqk { 4330 __le32 phy_idx; 4331 __le32 dbcc; 4332 } __packed; 4333 4334 struct rtw89_h2c_rf_dpk { 4335 u8 len; 4336 u8 phy; 4337 u8 dpk_enable; 4338 u8 kpath; 4339 u8 cur_band; 4340 u8 cur_bw; 4341 u8 cur_ch; 4342 u8 dpk_dbg_en; 4343 } __packed; 4344 4345 struct rtw89_h2c_rf_txgapk { 4346 u8 len; 4347 u8 ktype; 4348 u8 phy; 4349 u8 kpath; 4350 u8 band; 4351 u8 bw; 4352 u8 ch; 4353 u8 cv; 4354 } __packed; 4355 4356 struct rtw89_h2c_rf_dack { 4357 __le32 len; 4358 __le32 phy; 4359 __le32 type; 4360 } __packed; 4361 4362 struct rtw89_h2c_rf_rxdck { 4363 u8 len; 4364 u8 phy; 4365 u8 is_afe; 4366 u8 kpath; 4367 u8 cur_band; 4368 u8 cur_bw; 4369 u8 cur_ch; 4370 u8 rxdck_dbg_en; 4371 } __packed; 4372 4373 enum rtw89_rf_log_type { 4374 RTW89_RF_RUN_LOG = 0, 4375 RTW89_RF_RPT_LOG = 1, 4376 }; 4377 4378 struct rtw89_c2h_rf_log_hdr { 4379 u8 type; /* enum rtw89_rf_log_type */ 4380 __le16 len; 4381 u8 content[]; 4382 } __packed; 4383 4384 struct rtw89_c2h_rf_run_log { 4385 __le32 fmt_idx; 4386 __le32 arg[4]; 4387 } __packed; 4388 4389 struct rtw89_c2h_rf_dpk_rpt_log { 4390 u8 ver; 4391 u8 idx[2]; 4392 u8 band[2]; 4393 u8 bw[2]; 4394 u8 ch[2]; 4395 u8 path_ok[2]; 4396 u8 txagc[2]; 4397 u8 ther[2]; 4398 u8 gs[2]; 4399 u8 dc_i[4]; 4400 u8 dc_q[4]; 4401 u8 corr_val[2]; 4402 u8 corr_idx[2]; 4403 u8 is_timeout[2]; 4404 u8 rxbb_ov[2]; 4405 u8 rsvd; 4406 } __packed; 4407 4408 struct rtw89_c2h_rf_dack_rpt_log { 4409 u8 fwdack_ver; 4410 u8 fwdack_rpt_ver; 4411 u8 msbk_d[2][2][16]; 4412 u8 dadck_d[2][2]; 4413 u8 cdack_d[2][2][2]; 4414 __le16 addck2_d[2][2][2]; 4415 u8 adgaink_d[2][2]; 4416 __le16 biask_d[2][2]; 4417 u8 addck_timeout; 4418 u8 cdack_timeout; 4419 u8 dadck_timeout; 4420 u8 msbk_timeout; 4421 u8 adgaink_timeout; 4422 u8 dack_fail; 4423 } __packed; 4424 4425 struct rtw89_c2h_rf_rxdck_rpt_log { 4426 u8 ver; 4427 u8 band[2]; 4428 u8 bw[2]; 4429 u8 ch[2]; 4430 u8 timeout[2]; 4431 } __packed; 4432 4433 struct rtw89_c2h_rf_txgapk_rpt_log { 4434 __le32 r0x8010[2]; 4435 __le32 chk_cnt; 4436 u8 track_d[2][17]; 4437 u8 power_d[2][17]; 4438 u8 is_txgapk_ok; 4439 u8 chk_id; 4440 u8 ver; 4441 u8 rsv1; 4442 } __packed; 4443 4444 struct rtw89_c2h_rfk_report { 4445 struct rtw89_c2h_hdr hdr; 4446 u8 state; /* enum rtw89_rfk_report_state */ 4447 u8 version; 4448 } __packed; 4449 4450 #define RTW89_FW_RSVD_PLE_SIZE 0x800 4451 4452 #define RTW89_FW_BACKTRACE_INFO_SIZE 8 4453 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \ 4454 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0) 4455 4456 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */ 4457 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE 4458 4459 #define FWDL_WAIT_CNT 400000 4460 4461 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type); 4462 int rtw89_fw_recognize(struct rtw89_dev *rtwdev); 4463 int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev); 4464 const struct firmware * 4465 rtw89_early_fw_feature_recognize(struct device *device, 4466 const struct rtw89_chip_info *chip, 4467 struct rtw89_fw_info *early_fw, 4468 int *used_fw_format); 4469 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type, 4470 bool include_bb); 4471 void rtw89_load_firmware_work(struct work_struct *work); 4472 void rtw89_unload_firmware(struct rtw89_dev *rtwdev); 4473 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); 4474 int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev); 4475 void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len); 4476 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4477 u8 type, u8 cat, u8 class, u8 func, 4478 bool rack, bool dack, u32 len); 4479 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, 4480 struct rtw89_vif *rtwvif, 4481 struct rtw89_sta *rtwsta); 4482 int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev, 4483 struct rtw89_vif *rtwvif, 4484 struct rtw89_sta *rtwsta); 4485 int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev, 4486 struct rtw89_vif *rtwvif, 4487 struct rtw89_sta *rtwsta); 4488 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 4489 struct ieee80211_vif *vif, 4490 struct ieee80211_sta *sta); 4491 int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev, 4492 struct ieee80211_vif *vif, 4493 struct ieee80211_sta *sta); 4494 int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev, 4495 struct ieee80211_vif *vif, 4496 struct ieee80211_sta *sta); 4497 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, 4498 struct rtw89_sta *rtwsta); 4499 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev, 4500 struct rtw89_sta *rtwsta); 4501 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev, 4502 struct rtw89_vif *rtwvif); 4503 int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev, 4504 struct rtw89_vif *rtwvif); 4505 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif, 4506 struct rtw89_sta *rtwsta, const u8 *scan_mac_addr); 4507 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev, 4508 struct rtw89_vif *rtwvif, 4509 struct rtw89_sta *rtwsta); 4510 int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev, 4511 struct rtw89_vif *rtwvif, 4512 struct rtw89_sta *rtwsta); 4513 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); 4514 void rtw89_fw_c2h_work(struct work_struct *work); 4515 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev, 4516 struct rtw89_vif *rtwvif, 4517 struct rtw89_sta *rtwsta, 4518 enum rtw89_upd_mode upd_mode); 4519 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4520 struct rtw89_sta *rtwsta, bool dis_conn); 4521 int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en); 4522 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, 4523 bool pause); 4524 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4525 u8 ac, u32 val); 4526 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); 4527 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev, 4528 struct ieee80211_vif *vif, 4529 bool connect); 4530 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev, 4531 struct rtw89_rx_phy_ppdu *phy_ppdu); 4532 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 4533 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); 4534 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); 4535 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); 4536 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev); 4537 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev); 4538 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); 4539 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev); 4540 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); 4541 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id); 4542 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id, 4543 struct sk_buff *skb_ofld); 4544 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int ch_num, 4545 struct list_head *chan_list); 4546 int rtw89_fw_h2c_scan_list_offload_be(struct rtw89_dev *rtwdev, int ch_num, 4547 struct list_head *chan_list); 4548 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev, 4549 struct rtw89_scan_option *opt, 4550 struct rtw89_vif *vif); 4551 int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev, 4552 struct rtw89_scan_option *opt, 4553 struct rtw89_vif *vif); 4554 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, 4555 struct rtw89_fw_h2c_rf_reg_info *info, 4556 u16 len, u8 page); 4557 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev); 4558 int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev, 4559 enum rtw89_phy_idx phy_idx); 4560 int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 4561 enum rtw89_tssi_mode tssi_mode); 4562 int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 4563 int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 4564 int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 4565 int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 4566 int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 4567 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 4568 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 4569 bool rack, bool dack); 4570 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); 4571 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); 4572 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); 4573 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4574 u8 macid); 4575 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev, 4576 struct rtw89_vif *rtwvif, bool notify_fw); 4577 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw); 4578 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4579 bool valid, struct ieee80211_ampdu_params *params); 4580 int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4581 bool valid, struct ieee80211_ampdu_params *params); 4582 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev); 4583 int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users, 4584 u8 offset, u8 mac_idx); 4585 4586 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, 4587 struct rtw89_lps_parm *lps_param); 4588 int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev, 4589 struct rtw89_vif *rtwvif); 4590 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len); 4591 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len); 4592 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, 4593 struct rtw89_mac_h2c_info *h2c_info, 4594 struct rtw89_mac_c2h_info *c2h_info); 4595 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); 4596 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); 4597 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4598 struct ieee80211_scan_request *req); 4599 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4600 bool aborted); 4601 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4602 bool enable); 4603 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 4604 int rtw89_hw_scan_add_chan_list(struct rtw89_dev *rtwdev, 4605 struct rtw89_vif *rtwvif, bool connected); 4606 int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev, 4607 struct rtw89_vif *rtwvif, bool connected); 4608 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev); 4609 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev, 4610 const struct rtw89_pkt_drop_params *params); 4611 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4612 struct ieee80211_p2p_noa_desc *desc, 4613 u8 act, u8 noa_id); 4614 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4615 bool en); 4616 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4617 bool enable); 4618 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 4619 struct rtw89_vif *rtwvif, bool enable); 4620 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4621 bool enable); 4622 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev, 4623 struct rtw89_vif *rtwvif, bool enable); 4624 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4625 bool enable); 4626 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 4627 struct rtw89_vif *rtwvif, bool enable); 4628 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev, 4629 struct rtw89_wow_cam_info *cam_info); 4630 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev, 4631 const struct rtw89_fw_mcc_add_req *p); 4632 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev, 4633 const struct rtw89_fw_mcc_start_req *p); 4634 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid, 4635 bool prev_groups); 4636 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group, 4637 bool prev_groups); 4638 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group); 4639 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev, 4640 const struct rtw89_fw_mcc_tsf_req *req, 4641 struct rtw89_mac_mcc_tsf_rpt *rpt); 4642 int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid, 4643 u8 *bitmap); 4644 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source, 4645 u8 target, u8 offset); 4646 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev, 4647 const struct rtw89_fw_mcc_duration *p); 4648 int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev, 4649 const struct rtw89_fw_mrc_add_arg *arg); 4650 int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev, 4651 const struct rtw89_fw_mrc_start_arg *arg); 4652 int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx); 4653 int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev, 4654 const struct rtw89_fw_mrc_req_tsf_arg *arg, 4655 struct rtw89_mac_mrc_tsf_rpt *rpt); 4656 int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev, 4657 const struct rtw89_fw_mrc_upd_bitmap_arg *arg); 4658 int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev, 4659 const struct rtw89_fw_mrc_sync_arg *arg); 4660 int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev, 4661 const struct rtw89_fw_mrc_upd_duration_arg *arg); 4662 4663 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev) 4664 { 4665 const struct rtw89_chip_info *chip = rtwdev->chip; 4666 4667 if (chip->bacam_ver == RTW89_BACAM_V0_EXT) 4668 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev); 4669 } 4670 4671 static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, 4672 struct rtw89_vif *rtwvif, 4673 struct rtw89_sta *rtwsta) 4674 { 4675 const struct rtw89_chip_info *chip = rtwdev->chip; 4676 4677 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif, rtwsta); 4678 } 4679 4680 static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev, 4681 struct rtw89_vif *rtwvif, 4682 struct rtw89_sta *rtwsta) 4683 { 4684 const struct rtw89_chip_info *chip = rtwdev->chip; 4685 4686 if (chip->ops->h2c_default_dmac_tbl) 4687 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif, rtwsta); 4688 4689 return 0; 4690 } 4691 4692 static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev, 4693 struct rtw89_vif *rtwvif) 4694 { 4695 const struct rtw89_chip_info *chip = rtwdev->chip; 4696 4697 return chip->ops->h2c_update_beacon(rtwdev, rtwvif); 4698 } 4699 4700 static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 4701 struct ieee80211_vif *vif, 4702 struct ieee80211_sta *sta) 4703 { 4704 const struct rtw89_chip_info *chip = rtwdev->chip; 4705 4706 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, vif, sta); 4707 } 4708 4709 static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev, 4710 struct ieee80211_vif *vif, 4711 struct ieee80211_sta *sta) 4712 { 4713 const struct rtw89_chip_info *chip = rtwdev->chip; 4714 4715 if (chip->ops->h2c_ampdu_cmac_tbl) 4716 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, vif, sta); 4717 4718 return 0; 4719 } 4720 4721 static inline 4722 int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4723 bool valid, struct ieee80211_ampdu_params *params) 4724 { 4725 const struct rtw89_chip_info *chip = rtwdev->chip; 4726 4727 return chip->ops->h2c_ba_cam(rtwdev, rtwsta, valid, params); 4728 } 4729 4730 /* must consider compatibility; don't insert new in the mid */ 4731 struct rtw89_fw_txpwr_byrate_entry { 4732 u8 band; 4733 u8 nss; 4734 u8 rs; 4735 u8 shf; 4736 u8 len; 4737 __le32 data; 4738 u8 bw; 4739 u8 ofdma; 4740 } __packed; 4741 4742 /* must consider compatibility; don't insert new in the mid */ 4743 struct rtw89_fw_txpwr_lmt_2ghz_entry { 4744 u8 bw; 4745 u8 nt; 4746 u8 rs; 4747 u8 bf; 4748 u8 regd; 4749 u8 ch_idx; 4750 s8 v; 4751 } __packed; 4752 4753 /* must consider compatibility; don't insert new in the mid */ 4754 struct rtw89_fw_txpwr_lmt_5ghz_entry { 4755 u8 bw; 4756 u8 nt; 4757 u8 rs; 4758 u8 bf; 4759 u8 regd; 4760 u8 ch_idx; 4761 s8 v; 4762 } __packed; 4763 4764 /* must consider compatibility; don't insert new in the mid */ 4765 struct rtw89_fw_txpwr_lmt_6ghz_entry { 4766 u8 bw; 4767 u8 nt; 4768 u8 rs; 4769 u8 bf; 4770 u8 regd; 4771 u8 reg_6ghz_power; 4772 u8 ch_idx; 4773 s8 v; 4774 } __packed; 4775 4776 /* must consider compatibility; don't insert new in the mid */ 4777 struct rtw89_fw_txpwr_lmt_ru_2ghz_entry { 4778 u8 ru; 4779 u8 nt; 4780 u8 regd; 4781 u8 ch_idx; 4782 s8 v; 4783 } __packed; 4784 4785 /* must consider compatibility; don't insert new in the mid */ 4786 struct rtw89_fw_txpwr_lmt_ru_5ghz_entry { 4787 u8 ru; 4788 u8 nt; 4789 u8 regd; 4790 u8 ch_idx; 4791 s8 v; 4792 } __packed; 4793 4794 /* must consider compatibility; don't insert new in the mid */ 4795 struct rtw89_fw_txpwr_lmt_ru_6ghz_entry { 4796 u8 ru; 4797 u8 nt; 4798 u8 regd; 4799 u8 reg_6ghz_power; 4800 u8 ch_idx; 4801 s8 v; 4802 } __packed; 4803 4804 /* must consider compatibility; don't insert new in the mid */ 4805 struct rtw89_fw_tx_shape_lmt_entry { 4806 u8 band; 4807 u8 tx_shape_rs; 4808 u8 regd; 4809 u8 v; 4810 } __packed; 4811 4812 /* must consider compatibility; don't insert new in the mid */ 4813 struct rtw89_fw_tx_shape_lmt_ru_entry { 4814 u8 band; 4815 u8 regd; 4816 u8 v; 4817 } __packed; 4818 4819 const struct rtw89_rfe_parms * 4820 rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev, 4821 const struct rtw89_rfe_parms *init); 4822 4823 #endif 4824