1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_FW_H__ 6 #define __RTW89_FW_H__ 7 8 #include "core.h" 9 10 enum rtw89_fw_dl_status { 11 RTW89_FWDL_INITIAL_STATE = 0, 12 RTW89_FWDL_FWDL_ONGOING = 1, 13 RTW89_FWDL_CHECKSUM_FAIL = 2, 14 RTW89_FWDL_SECURITY_FAIL = 3, 15 RTW89_FWDL_CV_NOT_MATCH = 4, 16 RTW89_FWDL_RSVD0 = 5, 17 RTW89_FWDL_WCPU_FWDL_RDY = 6, 18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7 19 }; 20 21 #define RTW89_GET_C2H_HDR_FUNC(info) \ 22 u32_get_bits(info, GENMASK(6, 0)) 23 #define RTW89_GET_C2H_HDR_LEN(info) \ 24 u32_get_bits(info, GENMASK(11, 8)) 25 26 #define RTW89_SET_H2CREG_HDR_FUNC(info, val) \ 27 u32p_replace_bits(info, val, GENMASK(6, 0)) 28 #define RTW89_SET_H2CREG_HDR_LEN(info, val) \ 29 u32p_replace_bits(info, val, GENMASK(11, 8)) 30 31 #define RTW89_H2CREG_MAX 4 32 #define RTW89_C2HREG_MAX 4 33 #define RTW89_C2HREG_HDR_LEN 2 34 #define RTW89_H2CREG_HDR_LEN 2 35 #define RTW89_C2H_TIMEOUT 1000000 36 struct rtw89_mac_c2h_info { 37 u8 id; 38 u8 content_len; 39 u32 c2hreg[RTW89_C2HREG_MAX]; 40 }; 41 42 struct rtw89_mac_h2c_info { 43 u8 id; 44 u8 content_len; 45 u32 h2creg[RTW89_H2CREG_MAX]; 46 }; 47 48 enum rtw89_mac_h2c_type { 49 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, 50 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, 51 RTW89_FWCMD_H2CREG_FUNC_FWERR, 52 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, 53 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, 54 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN 55 }; 56 57 enum rtw89_mac_c2h_type { 58 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, 59 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, 60 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, 61 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, 62 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, 63 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF 64 }; 65 66 #define RTW89_GET_C2H_PHYCAP_FUNC(info) \ 67 u32_get_bits(*((const u32 *)(info)), GENMASK(6, 0)) 68 #define RTW89_GET_C2H_PHYCAP_ACK(info) \ 69 u32_get_bits(*((const u32 *)(info)), BIT(7)) 70 #define RTW89_GET_C2H_PHYCAP_LEN(info) \ 71 u32_get_bits(*((const u32 *)(info)), GENMASK(11, 8)) 72 #define RTW89_GET_C2H_PHYCAP_SEQ(info) \ 73 u32_get_bits(*((const u32 *)(info)), GENMASK(15, 12)) 74 #define RTW89_GET_C2H_PHYCAP_RX_NSS(info) \ 75 u32_get_bits(*((const u32 *)(info)), GENMASK(23, 16)) 76 #define RTW89_GET_C2H_PHYCAP_BW(info) \ 77 u32_get_bits(*((const u32 *)(info)), GENMASK(31, 24)) 78 #define RTW89_GET_C2H_PHYCAP_TX_NSS(info) \ 79 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(7, 0)) 80 #define RTW89_GET_C2H_PHYCAP_PROT(info) \ 81 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(15, 8)) 82 #define RTW89_GET_C2H_PHYCAP_NIC(info) \ 83 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(23, 16)) 84 #define RTW89_GET_C2H_PHYCAP_WL_FUNC(info) \ 85 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(31, 24)) 86 #define RTW89_GET_C2H_PHYCAP_HW_TYPE(info) \ 87 u32_get_bits(*((const u32 *)(info) + 2), GENMASK(7, 0)) 88 #define RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(info) \ 89 u32_get_bits(*((const u32 *)(info) + 3), GENMASK(15, 8)) 90 #define RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(info) \ 91 u32_get_bits(*((const u32 *)(info) + 3), GENMASK(23, 16)) 92 93 enum rtw89_fw_c2h_category { 94 RTW89_C2H_CAT_TEST, 95 RTW89_C2H_CAT_MAC, 96 RTW89_C2H_CAT_OUTSRC, 97 }; 98 99 enum rtw89_fw_log_level { 100 RTW89_FW_LOG_LEVEL_OFF, 101 RTW89_FW_LOG_LEVEL_CRT, 102 RTW89_FW_LOG_LEVEL_SER, 103 RTW89_FW_LOG_LEVEL_WARN, 104 RTW89_FW_LOG_LEVEL_LOUD, 105 RTW89_FW_LOG_LEVEL_TR, 106 }; 107 108 enum rtw89_fw_log_path { 109 RTW89_FW_LOG_LEVEL_UART, 110 RTW89_FW_LOG_LEVEL_C2H, 111 RTW89_FW_LOG_LEVEL_SNI, 112 }; 113 114 enum rtw89_fw_log_comp { 115 RTW89_FW_LOG_COMP_VER, 116 RTW89_FW_LOG_COMP_INIT, 117 RTW89_FW_LOG_COMP_TASK, 118 RTW89_FW_LOG_COMP_CNS, 119 RTW89_FW_LOG_COMP_H2C, 120 RTW89_FW_LOG_COMP_C2H, 121 RTW89_FW_LOG_COMP_TX, 122 RTW89_FW_LOG_COMP_RX, 123 RTW89_FW_LOG_COMP_IPSEC, 124 RTW89_FW_LOG_COMP_TIMER, 125 RTW89_FW_LOG_COMP_DBGPKT, 126 RTW89_FW_LOG_COMP_PS, 127 RTW89_FW_LOG_COMP_ERROR, 128 RTW89_FW_LOG_COMP_WOWLAN, 129 RTW89_FW_LOG_COMP_SECURE_BOOT, 130 RTW89_FW_LOG_COMP_BTC, 131 RTW89_FW_LOG_COMP_BB, 132 RTW89_FW_LOG_COMP_TWT, 133 RTW89_FW_LOG_COMP_RF, 134 RTW89_FW_LOG_COMP_MCC = 20, 135 }; 136 137 enum rtw89_pkt_offload_op { 138 RTW89_PKT_OFLD_OP_ADD, 139 RTW89_PKT_OFLD_OP_DEL, 140 RTW89_PKT_OFLD_OP_READ, 141 }; 142 143 enum rtw89_scanofld_notify_reason { 144 RTW89_SCAN_DWELL_NOTIFY, 145 RTW89_SCAN_PRE_TX_NOTIFY, 146 RTW89_SCAN_POST_TX_NOTIFY, 147 RTW89_SCAN_ENTER_CH_NOTIFY, 148 RTW89_SCAN_LEAVE_CH_NOTIFY, 149 RTW89_SCAN_END_SCAN_NOTIFY, 150 }; 151 152 enum rtw89_chan_type { 153 RTW89_CHAN_OPERATE = 0, 154 RTW89_CHAN_ACTIVE, 155 RTW89_CHAN_DFS, 156 }; 157 158 enum rtw89_p2pps_action { 159 RTW89_P2P_ACT_INIT = 0, 160 RTW89_P2P_ACT_UPDATE = 1, 161 RTW89_P2P_ACT_REMOVE = 2, 162 RTW89_P2P_ACT_TERMINATE = 3, 163 }; 164 165 #define FWDL_SECTION_MAX_NUM 10 166 #define FWDL_SECTION_CHKSUM_LEN 8 167 #define FWDL_SECTION_PER_PKT_LEN 2020 168 169 struct rtw89_fw_hdr_section_info { 170 u8 redl; 171 const u8 *addr; 172 u32 len; 173 u32 dladdr; 174 u32 mssc; 175 u8 type; 176 }; 177 178 struct rtw89_fw_bin_info { 179 u8 section_num; 180 u32 hdr_len; 181 bool dynamic_hdr_en; 182 u32 dynamic_hdr_len; 183 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; 184 }; 185 186 struct rtw89_fw_macid_pause_grp { 187 __le32 pause_grp[4]; 188 __le32 mask_grp[4]; 189 } __packed; 190 191 struct rtw89_h2creg_sch_tx_en { 192 u8 func:7; 193 u8 ack:1; 194 u8 total_len:4; 195 u8 seq_num:4; 196 u16 tx_en:16; 197 u16 mask:16; 198 u8 band:1; 199 u16 rsvd:15; 200 } __packed; 201 202 #define RTW89_H2C_MAX_SIZE 2048 203 #define RTW89_CHANNEL_TIME 45 204 #define RTW89_CHANNEL_TIME_6G 20 205 #define RTW89_DFS_CHAN_TIME 105 206 #define RTW89_OFF_CHAN_TIME 100 207 #define RTW89_DWELL_TIME 20 208 #define RTW89_DWELL_TIME_6G 10 209 #define RTW89_SCAN_WIDTH 0 210 #define RTW89_SCANOFLD_MAX_SSID 8 211 #define RTW89_SCANOFLD_MAX_IE_LEN 512 212 #define RTW89_SCANOFLD_PKT_NONE 0xFF 213 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F 214 #define RTW89_MAC_CHINFO_SIZE 24 215 #define RTW89_SCAN_LIST_GUARD 4 216 #define RTW89_SCAN_LIST_LIMIT \ 217 ((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD) 218 219 struct rtw89_mac_chinfo { 220 u8 period; 221 u8 dwell_time; 222 u8 central_ch; 223 u8 pri_ch; 224 u8 bw:3; 225 u8 notify_action:5; 226 u8 num_pkt:4; 227 u8 tx_pkt:1; 228 u8 pause_data:1; 229 u8 ch_band:2; 230 u8 probe_id; 231 u8 dfs_ch:1; 232 u8 tx_null:1; 233 u8 rand_seq_num:1; 234 u8 cfg_tx_pwr:1; 235 u8 rsvd0: 4; 236 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID]; 237 u16 tx_pwr_idx; 238 u8 rsvd1; 239 struct list_head list; 240 bool is_psc; 241 }; 242 243 struct rtw89_scan_option { 244 bool enable; 245 bool target_ch_mode; 246 }; 247 248 struct rtw89_pktofld_info { 249 struct list_head list; 250 u8 id; 251 252 /* Below fields are for 6 GHz RNR use only */ 253 u8 ssid[IEEE80211_MAX_SSID_LEN]; 254 u8 ssid_len; 255 u8 bssid[ETH_ALEN]; 256 u16 channel_6ghz; 257 }; 258 259 static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val) 260 { 261 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)); 262 } 263 264 static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val) 265 { 266 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)); 267 } 268 269 static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val) 270 { 271 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)); 272 } 273 274 static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val) 275 { 276 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 277 } 278 279 static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val) 280 { 281 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16)); 282 } 283 284 static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val) 285 { 286 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17)); 287 } 288 289 static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val) 290 { 291 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18)); 292 } 293 294 static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val) 295 { 296 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20)); 297 } 298 299 static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val) 300 { 301 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21)); 302 } 303 304 static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val) 305 { 306 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22)); 307 } 308 309 static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val) 310 { 311 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23)); 312 } 313 314 static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val) 315 { 316 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24)); 317 } 318 319 static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val) 320 { 321 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27)); 322 } 323 324 static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val) 325 { 326 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30)); 327 } 328 329 static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val) 330 { 331 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31)); 332 } 333 334 static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val) 335 { 336 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0)); 337 } 338 339 static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val) 340 { 341 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8)); 342 } 343 344 static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val) 345 { 346 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16)); 347 } 348 349 static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val) 350 { 351 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24)); 352 } 353 354 static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val) 355 { 356 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0)); 357 } 358 359 static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val) 360 { 361 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31)); 362 } 363 364 static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val) 365 { 366 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0)); 367 } 368 369 static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val) 370 { 371 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8)); 372 } 373 374 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val) 375 { 376 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9)); 377 } 378 379 static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val) 380 { 381 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10)); 382 } 383 384 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF_EN(void *cmd, u32 val) 385 { 386 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(11)); 387 } 388 389 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF(void *cmd, u32 val) 390 { 391 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(14, 12)); 392 } 393 394 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val) 395 { 396 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16)); 397 } 398 399 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val) 400 { 401 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24)); 402 } 403 404 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val) 405 { 406 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26)); 407 } 408 409 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val) 410 { 411 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29)); 412 } 413 414 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) 415 { 416 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); 417 } 418 419 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) 420 { 421 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 422 } 423 424 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) 425 { 426 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); 427 } 428 429 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) 430 { 431 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); 432 } 433 434 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) 435 { 436 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); 437 } 438 439 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) 440 { 441 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)); 442 } 443 444 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) 445 { 446 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)); 447 } 448 449 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) 450 { 451 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)); 452 } 453 454 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) 455 { 456 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)); 457 } 458 459 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) 460 { 461 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)); 462 } 463 464 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val) 465 { 466 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)); 467 } 468 469 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val) 470 { 471 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)); 472 } 473 474 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val) 475 { 476 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)); 477 } 478 479 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val) 480 { 481 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)); 482 } 483 484 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val) 485 { 486 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)); 487 } 488 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) 489 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) 490 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) 491 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) 492 493 #define FWDL_SECURITY_SECTION_TYPE 9 494 #define FWDL_SECURITY_SIGLEN 512 495 496 #define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \ 497 le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0)) 498 #define GET_FWSECTION_HDR_SECTIONTYPE(fwhdr) \ 499 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(27, 24)) 500 #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \ 501 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0)) 502 #define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \ 503 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28)) 504 #define GET_FWSECTION_HDR_REDL(fwhdr) \ 505 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29)) 506 #define GET_FWSECTION_HDR_MSSC(fwhdr) \ 507 le32_get_bits(*((const __le32 *)(fwhdr) + 2), GENMASK(31, 0)) 508 509 #define GET_FW_HDR_MAJOR_VERSION(fwhdr) \ 510 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0)) 511 #define GET_FW_HDR_MINOR_VERSION(fwhdr) \ 512 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8)) 513 #define GET_FW_HDR_SUBVERSION(fwhdr) \ 514 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16)) 515 #define GET_FW_HDR_SUBINDEX(fwhdr) \ 516 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24)) 517 #define GET_FW_HDR_LEN(fwhdr) \ 518 le32_get_bits(*((const __le32 *)(fwhdr) + 3), GENMASK(23, 16)) 519 #define GET_FW_HDR_MONTH(fwhdr) \ 520 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0)) 521 #define GET_FW_HDR_DATE(fwhdr) \ 522 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8)) 523 #define GET_FW_HDR_HOUR(fwhdr) \ 524 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16)) 525 #define GET_FW_HDR_MIN(fwhdr) \ 526 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24)) 527 #define GET_FW_HDR_YEAR(fwhdr) \ 528 le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0)) 529 #define GET_FW_HDR_SEC_NUM(fwhdr) \ 530 le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8)) 531 #define GET_FW_HDR_DYN_HDR(fwhdr) \ 532 le32_get_bits(*((const __le32 *)(fwhdr) + 7), BIT(16)) 533 #define GET_FW_HDR_CMD_VERSERION(fwhdr) \ 534 le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24)) 535 536 #define GET_FW_DYNHDR_LEN(fwdynhdr) \ 537 le32_get_bits(*((const __le32 *)(fwdynhdr)), GENMASK(31, 0)) 538 #define GET_FW_DYNHDR_COUNT(fwdynhdr) \ 539 le32_get_bits(*((const __le32 *)(fwdynhdr) + 1), GENMASK(31, 0)) 540 541 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val) 542 { 543 le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0)); 544 } 545 546 static inline void SET_CTRL_INFO_MACID(void *table, u32 val) 547 { 548 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 549 } 550 551 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val) 552 { 553 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 554 } 555 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) 556 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val) 557 { 558 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); 559 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, 560 GENMASK(8, 0)); 561 } 562 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) 563 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) 564 { 565 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); 566 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, 567 BIT(9)); 568 } 569 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) 570 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val) 571 { 572 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); 573 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, 574 GENMASK(11, 10)); 575 } 576 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) 577 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) 578 { 579 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); 580 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, 581 GENMASK(14, 12)); 582 } 583 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) 584 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) 585 { 586 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 587 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, 588 BIT(15)); 589 } 590 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) 591 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) 592 { 593 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); 594 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, 595 GENMASK(19, 16)); 596 } 597 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) 598 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) 599 { 600 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); 601 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, 602 BIT(20)); 603 } 604 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) 605 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) 606 { 607 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); 608 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, 609 BIT(21)); 610 } 611 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) 612 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) 613 { 614 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); 615 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, 616 BIT(22)); 617 } 618 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) 619 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) 620 { 621 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); 622 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, 623 BIT(23)); 624 } 625 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0) 626 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val) 627 { 628 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); 629 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, 630 BIT(25)); 631 } 632 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0) 633 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val) 634 { 635 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); 636 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, 637 BIT(26)); 638 } 639 #define SET_CMC_TBL_MASK_TRYRATE BIT(0) 640 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val) 641 { 642 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); 643 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, 644 BIT(27)); 645 } 646 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) 647 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) 648 { 649 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); 650 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, 651 GENMASK(31, 28)); 652 } 653 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) 654 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) 655 { 656 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); 657 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, 658 GENMASK(8, 0)); 659 } 660 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) 661 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) 662 { 663 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); 664 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, 665 BIT(9)); 666 } 667 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) 668 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) 669 { 670 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); 671 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, 672 BIT(10)); 673 } 674 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) 675 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) 676 { 677 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); 678 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, 679 BIT(11)); 680 } 681 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) 682 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) 683 { 684 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); 685 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, 686 GENMASK(15, 12)); 687 } 688 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) 689 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val) 690 { 691 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); 692 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, 693 GENMASK(24, 16)); 694 } 695 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0) 696 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val) 697 { 698 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); 699 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, 700 BIT(27)); 701 } 702 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) 703 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) 704 { 705 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); 706 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, 707 GENMASK(31, 28)); 708 } 709 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) 710 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) 711 { 712 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); 713 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, 714 GENMASK(5, 0)); 715 } 716 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) 717 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) 718 { 719 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); 720 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, 721 BIT(6)); 722 } 723 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) 724 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) 725 { 726 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); 727 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, 728 BIT(7)); 729 } 730 #define SET_CMC_TBL_MASK_RTS_EN BIT(0) 731 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val) 732 { 733 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); 734 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, 735 BIT(8)); 736 } 737 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) 738 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) 739 { 740 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); 741 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, 742 BIT(9)); 743 } 744 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) 745 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val) 746 { 747 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); 748 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, 749 GENMASK(11, 10)); 750 } 751 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) 752 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) 753 { 754 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); 755 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, 756 BIT(12)); 757 } 758 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) 759 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) 760 { 761 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); 762 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, 763 GENMASK(14, 13)); 764 } 765 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) 766 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) 767 { 768 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); 769 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, 770 GENMASK(26, 16)); 771 } 772 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) 773 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) 774 { 775 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 776 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, 777 BIT(27)); 778 } 779 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) 780 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) 781 { 782 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); 783 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, 784 GENMASK(31, 28)); 785 } 786 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) 787 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) 788 { 789 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); 790 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, 791 GENMASK(7, 0)); 792 } 793 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) 794 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val) 795 { 796 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); 797 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, 798 GENMASK(9, 8)); 799 } 800 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) 801 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) 802 { 803 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); 804 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, 805 GENMASK(18, 16)); 806 } 807 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) 808 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) 809 { 810 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); 811 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, 812 GENMASK(21, 19)); 813 } 814 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) 815 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) 816 { 817 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); 818 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, 819 GENMASK(24, 22)); 820 } 821 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) 822 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) 823 { 824 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); 825 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, 826 GENMASK(27, 25)); 827 } 828 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) 829 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val) 830 { 831 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); 832 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, 833 GENMASK(31, 28)); 834 } 835 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) 836 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) 837 { 838 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); 839 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, 840 GENMASK(2, 0)); 841 } 842 #define SET_CMC_TBL_MASK_BMC BIT(0) 843 static inline void SET_CMC_TBL_BMC(void *table, u32 val) 844 { 845 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); 846 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, 847 BIT(3)); 848 } 849 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) 850 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val) 851 { 852 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); 853 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, 854 GENMASK(7, 4)); 855 } 856 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) 857 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) 858 { 859 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 860 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, 861 BIT(8)); 862 } 863 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) 864 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) 865 { 866 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); 867 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, 868 GENMASK(11, 9)); 869 } 870 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0) 871 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val) 872 { 873 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); 874 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, 875 BIT(12)); 876 } 877 #define SET_CMC_TBL_MASK_DATA_ER BIT(0) 878 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val) 879 { 880 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); 881 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, 882 BIT(13)); 883 } 884 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) 885 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val) 886 { 887 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); 888 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, 889 BIT(14)); 890 } 891 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0) 892 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val) 893 { 894 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 895 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, 896 BIT(15)); 897 } 898 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) 899 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) 900 { 901 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); 902 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, 903 BIT(16)); 904 } 905 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) 906 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) 907 { 908 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); 909 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, 910 BIT(17)); 911 } 912 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) 913 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) 914 { 915 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); 916 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, 917 BIT(18)); 918 } 919 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) 920 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) 921 { 922 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); 923 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, 924 BIT(19)); 925 } 926 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) 927 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) 928 { 929 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); 930 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, 931 BIT(20)); 932 } 933 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) 934 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) 935 { 936 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); 937 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, 938 BIT(21)); 939 } 940 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) 941 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) 942 { 943 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); 944 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, 945 BIT(27)); 946 } 947 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) 948 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val) 949 { 950 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); 951 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, 952 GENMASK(31, 28)); 953 } 954 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) 955 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) 956 { 957 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); 958 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, 959 GENMASK(8, 0)); 960 } 961 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) 962 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) 963 { 964 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); 965 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, 966 BIT(12)); 967 } 968 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) 969 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) 970 { 971 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); 972 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, 973 BIT(13)); 974 } 975 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) 976 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) 977 { 978 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); 979 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, 980 GENMASK(19, 16)); 981 } 982 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) 983 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) 984 { 985 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); 986 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, 987 GENMASK(21, 20)); 988 } 989 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) 990 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) 991 { 992 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); 993 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, 994 GENMASK(23, 22)); 995 } 996 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) 997 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) 998 { 999 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); 1000 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, 1001 GENMASK(25, 24)); 1002 } 1003 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) 1004 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) 1005 { 1006 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); 1007 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, 1008 GENMASK(27, 26)); 1009 } 1010 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) 1011 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val) 1012 { 1013 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); 1014 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, 1015 BIT(28)); 1016 } 1017 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) 1018 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val) 1019 { 1020 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); 1021 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, 1022 BIT(29)); 1023 } 1024 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) 1025 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val) 1026 { 1027 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); 1028 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, 1029 BIT(30)); 1030 } 1031 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) 1032 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val) 1033 { 1034 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); 1035 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, 1036 BIT(31)); 1037 } 1038 1039 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) 1040 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val) 1041 { 1042 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0)); 1043 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1044 GENMASK(1, 0)); 1045 } 1046 1047 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val) 1048 { 1049 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2)); 1050 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1051 GENMASK(3, 2)); 1052 } 1053 1054 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val) 1055 { 1056 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4)); 1057 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1058 GENMASK(5, 4)); 1059 } 1060 1061 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val) 1062 { 1063 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6)); 1064 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1065 GENMASK(7, 6)); 1066 } 1067 1068 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) 1069 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) 1070 { 1071 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1072 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, 1073 GENMASK(7, 0)); 1074 } 1075 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) 1076 static inline void SET_CMC_TBL_PAID(void *table, u32 val) 1077 { 1078 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); 1079 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, 1080 GENMASK(16, 8)); 1081 } 1082 #define SET_CMC_TBL_MASK_ULDL BIT(0) 1083 static inline void SET_CMC_TBL_ULDL(void *table, u32 val) 1084 { 1085 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); 1086 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, 1087 BIT(17)); 1088 } 1089 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) 1090 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) 1091 { 1092 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); 1093 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, 1094 GENMASK(19, 18)); 1095 } 1096 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) 1097 { 1098 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); 1099 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1100 GENMASK(21, 20)); 1101 } 1102 1103 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) 1104 { 1105 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); 1106 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1107 GENMASK(23, 22)); 1108 } 1109 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) 1110 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) 1111 { 1112 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); 1113 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, 1114 GENMASK(27, 24)); 1115 } 1116 1117 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) 1118 { 1119 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); 1120 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1121 GENMASK(31, 30)); 1122 } 1123 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0) 1124 static inline void SET_CMC_TBL_NC(void *table, u32 val) 1125 { 1126 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); 1127 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, 1128 GENMASK(2, 0)); 1129 } 1130 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0) 1131 static inline void SET_CMC_TBL_NR(void *table, u32 val) 1132 { 1133 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); 1134 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, 1135 GENMASK(5, 3)); 1136 } 1137 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0) 1138 static inline void SET_CMC_TBL_NG(void *table, u32 val) 1139 { 1140 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); 1141 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, 1142 GENMASK(7, 6)); 1143 } 1144 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0) 1145 static inline void SET_CMC_TBL_CB(void *table, u32 val) 1146 { 1147 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); 1148 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, 1149 GENMASK(9, 8)); 1150 } 1151 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0) 1152 static inline void SET_CMC_TBL_CS(void *table, u32 val) 1153 { 1154 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); 1155 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, 1156 GENMASK(11, 10)); 1157 } 1158 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) 1159 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) 1160 { 1161 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); 1162 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, 1163 BIT(12)); 1164 } 1165 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) 1166 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) 1167 { 1168 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); 1169 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, 1170 BIT(13)); 1171 } 1172 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) 1173 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) 1174 { 1175 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); 1176 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, 1177 BIT(14)); 1178 } 1179 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) 1180 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) 1181 { 1182 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); 1183 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, 1184 BIT(15)); 1185 } 1186 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) 1187 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) 1188 { 1189 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); 1190 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, 1191 GENMASK(24, 16)); 1192 } 1193 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) 1194 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) 1195 { 1196 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); 1197 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, 1198 GENMASK(27, 25)); 1199 } 1200 1201 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val) 1202 { 1203 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28)); 1204 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1205 GENMASK(29, 28)); 1206 } 1207 1208 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) 1209 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val) 1210 { 1211 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); 1212 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, 1213 GENMASK(31, 30)); 1214 } 1215 1216 static inline void SET_DCTL_MACID_V1(void *table, u32 val) 1217 { 1218 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 1219 } 1220 1221 static inline void SET_DCTL_OPERATION_V1(void *table, u32 val) 1222 { 1223 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 1224 } 1225 1226 #define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0) 1227 static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val) 1228 { 1229 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0)); 1230 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1, 1231 GENMASK(7, 0)); 1232 } 1233 1234 #define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0) 1235 static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val) 1236 { 1237 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8)); 1238 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID, 1239 GENMASK(14, 8)); 1240 } 1241 1242 #define SET_DCTL_MASK_QOS_DATA BIT(0) 1243 static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val) 1244 { 1245 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 1246 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA, 1247 BIT(15)); 1248 } 1249 1250 #define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0) 1251 static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val) 1252 { 1253 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16)); 1254 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L, 1255 GENMASK(31, 16)); 1256 } 1257 1258 #define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0) 1259 static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val) 1260 { 1261 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0)); 1262 le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H, 1263 GENMASK(31, 0)); 1264 } 1265 1266 #define SET_DCTL_MASK_SEQ0 GENMASK(11, 0) 1267 static inline void SET_DCTL_SEQ0_V1(void *table, u32 val) 1268 { 1269 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0)); 1270 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0, 1271 GENMASK(11, 0)); 1272 } 1273 1274 #define SET_DCTL_MASK_SEQ1 GENMASK(11, 0) 1275 static inline void SET_DCTL_SEQ1_V1(void *table, u32 val) 1276 { 1277 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12)); 1278 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1, 1279 GENMASK(23, 12)); 1280 } 1281 1282 #define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0) 1283 static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val) 1284 { 1285 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24)); 1286 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN, 1287 GENMASK(26, 24)); 1288 } 1289 1290 #define SET_DCTL_MASK_STA_AMSDU_EN BIT(0) 1291 static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val) 1292 { 1293 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 1294 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN, 1295 BIT(27)); 1296 } 1297 1298 #define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0) 1299 static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val) 1300 { 1301 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28)); 1302 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN, 1303 BIT(28)); 1304 } 1305 1306 #define SET_DCTL_MASK_WITH_LLC BIT(0) 1307 static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val) 1308 { 1309 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29)); 1310 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC, 1311 BIT(29)); 1312 } 1313 1314 #define SET_DCTL_MASK_SEQ2 GENMASK(11, 0) 1315 static inline void SET_DCTL_SEQ2_V1(void *table, u32 val) 1316 { 1317 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0)); 1318 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2, 1319 GENMASK(11, 0)); 1320 } 1321 1322 #define SET_DCTL_MASK_SEQ3 GENMASK(11, 0) 1323 static inline void SET_DCTL_SEQ3_V1(void *table, u32 val) 1324 { 1325 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12)); 1326 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3, 1327 GENMASK(23, 12)); 1328 } 1329 1330 #define SET_DCTL_MASK_TGT_IND GENMASK(3, 0) 1331 static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val) 1332 { 1333 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24)); 1334 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND, 1335 GENMASK(27, 24)); 1336 } 1337 1338 #define SET_DCTL_MASK_TGT_IND_EN BIT(0) 1339 static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val) 1340 { 1341 le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28)); 1342 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN, 1343 BIT(28)); 1344 } 1345 1346 #define SET_DCTL_MASK_HTC_LB GENMASK(2, 0) 1347 static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val) 1348 { 1349 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29)); 1350 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB, 1351 GENMASK(31, 29)); 1352 } 1353 1354 #define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0) 1355 static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val) 1356 { 1357 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0)); 1358 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN, 1359 GENMASK(4, 0)); 1360 } 1361 1362 #define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0) 1363 static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val) 1364 { 1365 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5)); 1366 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID, 1367 BIT(5)); 1368 } 1369 1370 #define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0) 1371 static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val) 1372 { 1373 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6)); 1374 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL, 1375 GENMASK(7, 6)); 1376 } 1377 1378 #define SET_DCTL_MASK_HTC_ORDER BIT(0) 1379 static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val) 1380 { 1381 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 1382 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER, 1383 BIT(8)); 1384 } 1385 1386 #define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0) 1387 static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val) 1388 { 1389 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9)); 1390 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID, 1391 GENMASK(10, 9)); 1392 } 1393 1394 #define SET_DCTL_MASK_WAPI BIT(0) 1395 static inline void SET_DCTL_WAPI_V1(void *table, u32 val) 1396 { 1397 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 1398 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI, 1399 BIT(15)); 1400 } 1401 1402 #define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0) 1403 static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val) 1404 { 1405 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16)); 1406 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE, 1407 GENMASK(17, 16)); 1408 } 1409 1410 #define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0) 1411 static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val) 1412 { 1413 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18)); 1414 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1415 GENMASK(19, 18)); 1416 } 1417 1418 static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val) 1419 { 1420 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20)); 1421 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1422 GENMASK(21, 20)); 1423 } 1424 1425 static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val) 1426 { 1427 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22)); 1428 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1429 GENMASK(23, 22)); 1430 } 1431 1432 static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val) 1433 { 1434 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24)); 1435 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1436 GENMASK(25, 24)); 1437 } 1438 1439 static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val) 1440 { 1441 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26)); 1442 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1443 GENMASK(27, 26)); 1444 } 1445 1446 static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val) 1447 { 1448 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28)); 1449 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1450 GENMASK(29, 28)); 1451 } 1452 1453 static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val) 1454 { 1455 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30)); 1456 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1457 GENMASK(31, 30)); 1458 } 1459 1460 #define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0) 1461 static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val) 1462 { 1463 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0)); 1464 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID, 1465 GENMASK(7, 0)); 1466 } 1467 1468 #define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0) 1469 static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val) 1470 { 1471 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8)); 1472 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1473 GENMASK(15, 8)); 1474 } 1475 1476 static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val) 1477 { 1478 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16)); 1479 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1480 GENMASK(23, 16)); 1481 } 1482 1483 static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val) 1484 { 1485 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24)); 1486 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1487 GENMASK(31, 24)); 1488 } 1489 1490 static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val) 1491 { 1492 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1493 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1494 GENMASK(7, 0)); 1495 } 1496 1497 static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val) 1498 { 1499 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8)); 1500 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1501 GENMASK(15, 8)); 1502 } 1503 1504 static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val) 1505 { 1506 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16)); 1507 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1508 GENMASK(23, 16)); 1509 } 1510 1511 static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val) 1512 { 1513 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24)); 1514 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1515 GENMASK(31, 24)); 1516 } 1517 1518 static inline void SET_BCN_UPD_PORT(void *h2c, u32 val) 1519 { 1520 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1521 } 1522 1523 static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val) 1524 { 1525 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1526 } 1527 1528 static inline void SET_BCN_UPD_BAND(void *h2c, u32 val) 1529 { 1530 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1531 } 1532 1533 static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val) 1534 { 1535 le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24)); 1536 } 1537 1538 static inline void SET_BCN_UPD_MACID(void *h2c, u32 val) 1539 { 1540 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1541 } 1542 1543 static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val) 1544 { 1545 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8)); 1546 } 1547 1548 static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val) 1549 { 1550 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10)); 1551 } 1552 1553 static inline void SET_BCN_UPD_RATE(void *h2c, u32 val) 1554 { 1555 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12)); 1556 } 1557 1558 static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val) 1559 { 1560 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21)); 1561 } 1562 1563 static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val) 1564 { 1565 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0)); 1566 } 1567 1568 static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val) 1569 { 1570 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(4, 1)); 1571 } 1572 1573 static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val) 1574 { 1575 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(6, 5)); 1576 } 1577 1578 static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val) 1579 { 1580 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(8, 7)); 1581 } 1582 1583 static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val) 1584 { 1585 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(10, 9)); 1586 } 1587 1588 static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val) 1589 { 1590 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(12, 11)); 1591 } 1592 1593 static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val) 1594 { 1595 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(13)); 1596 } 1597 1598 static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val) 1599 { 1600 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(14)); 1601 } 1602 1603 static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val) 1604 { 1605 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(15)); 1606 } 1607 1608 static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val) 1609 { 1610 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(16)); 1611 } 1612 1613 static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val) 1614 { 1615 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 17)); 1616 } 1617 1618 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val) 1619 { 1620 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1621 } 1622 1623 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val) 1624 { 1625 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)); 1626 } 1627 1628 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val) 1629 { 1630 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)); 1631 } 1632 1633 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val) 1634 { 1635 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)); 1636 } 1637 1638 static inline void SET_JOININFO_MACID(void *h2c, u32 val) 1639 { 1640 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1641 } 1642 1643 static inline void SET_JOININFO_OP(void *h2c, u32 val) 1644 { 1645 le32p_replace_bits((__le32 *)h2c, val, BIT(8)); 1646 } 1647 1648 static inline void SET_JOININFO_BAND(void *h2c, u32 val) 1649 { 1650 le32p_replace_bits((__le32 *)h2c, val, BIT(9)); 1651 } 1652 1653 static inline void SET_JOININFO_WMM(void *h2c, u32 val) 1654 { 1655 le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)); 1656 } 1657 1658 static inline void SET_JOININFO_TGR(void *h2c, u32 val) 1659 { 1660 le32p_replace_bits((__le32 *)h2c, val, BIT(12)); 1661 } 1662 1663 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val) 1664 { 1665 le32p_replace_bits((__le32 *)h2c, val, BIT(13)); 1666 } 1667 1668 static inline void SET_JOININFO_DLBW(void *h2c, u32 val) 1669 { 1670 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)); 1671 } 1672 1673 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val) 1674 { 1675 le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)); 1676 } 1677 1678 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val) 1679 { 1680 le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)); 1681 } 1682 1683 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val) 1684 { 1685 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)); 1686 } 1687 1688 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val) 1689 { 1690 le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)); 1691 } 1692 1693 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val) 1694 { 1695 le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)); 1696 } 1697 1698 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val) 1699 { 1700 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)); 1701 } 1702 1703 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val) 1704 { 1705 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1706 } 1707 1708 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) 1709 { 1710 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1711 } 1712 1713 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) 1714 { 1715 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1716 } 1717 1718 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) 1719 { 1720 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1721 } 1722 1723 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) 1724 { 1725 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1726 } 1727 1728 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) 1729 { 1730 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1731 } 1732 1733 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val) 1734 { 1735 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1736 } 1737 1738 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val) 1739 { 1740 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1741 } 1742 1743 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val) 1744 { 1745 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 1746 } 1747 1748 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) 1749 { 1750 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)); 1751 } 1752 1753 static inline void SET_BA_CAM_VALID(void *h2c, u32 val) 1754 { 1755 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1756 } 1757 1758 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val) 1759 { 1760 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1761 } 1762 1763 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val) 1764 { 1765 le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)); 1766 } 1767 1768 static inline void SET_BA_CAM_TID(void *h2c, u32 val) 1769 { 1770 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)); 1771 } 1772 1773 static inline void SET_BA_CAM_MACID(void *h2c, u32 val) 1774 { 1775 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1776 } 1777 1778 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val) 1779 { 1780 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1781 } 1782 1783 static inline void SET_BA_CAM_SSN(void *h2c, u32 val) 1784 { 1785 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)); 1786 } 1787 1788 static inline void SET_BA_CAM_UID(void *h2c, u32 val) 1789 { 1790 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0)); 1791 } 1792 1793 static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val) 1794 { 1795 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8)); 1796 } 1797 1798 static inline void SET_BA_CAM_BAND(void *h2c, u32 val) 1799 { 1800 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9)); 1801 } 1802 1803 static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val) 1804 { 1805 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28)); 1806 } 1807 1808 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val) 1809 { 1810 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1811 } 1812 1813 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val) 1814 { 1815 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1816 } 1817 1818 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val) 1819 { 1820 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1821 } 1822 1823 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val) 1824 { 1825 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)); 1826 } 1827 1828 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) 1829 { 1830 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1831 } 1832 1833 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) 1834 { 1835 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)); 1836 } 1837 1838 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) 1839 { 1840 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)); 1841 } 1842 1843 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) 1844 { 1845 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)); 1846 } 1847 1848 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) 1849 { 1850 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)); 1851 } 1852 1853 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) 1854 { 1855 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1856 } 1857 1858 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val) 1859 { 1860 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0)); 1861 } 1862 1863 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val) 1864 { 1865 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 1866 } 1867 1868 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val) 1869 { 1870 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 1871 } 1872 1873 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val) 1874 { 1875 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 1876 } 1877 1878 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val) 1879 { 1880 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 1881 } 1882 1883 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val) 1884 { 1885 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0)); 1886 } 1887 1888 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val) 1889 { 1890 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8)); 1891 } 1892 1893 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val) 1894 { 1895 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 1896 } 1897 1898 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val) 1899 { 1900 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 1901 } 1902 1903 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val) 1904 { 1905 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 1906 } 1907 1908 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val) 1909 { 1910 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0)); 1911 } 1912 1913 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val) 1914 { 1915 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0)); 1916 } 1917 1918 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val) 1919 { 1920 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1921 } 1922 1923 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val) 1924 { 1925 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16)); 1926 } 1927 1928 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val) 1929 { 1930 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1931 } 1932 1933 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val) 1934 { 1935 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1936 } 1937 1938 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val) 1939 { 1940 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1941 } 1942 1943 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val) 1944 { 1945 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 1946 } 1947 1948 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val) 1949 { 1950 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1951 } 1952 1953 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val) 1954 { 1955 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1956 } 1957 1958 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val) 1959 { 1960 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1961 } 1962 1963 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val) 1964 { 1965 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1966 } 1967 1968 static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val) 1969 { 1970 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1971 } 1972 1973 static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val) 1974 { 1975 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1976 } 1977 1978 static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val) 1979 { 1980 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 1981 } 1982 1983 static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val) 1984 { 1985 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); 1986 } 1987 1988 static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val) 1989 { 1990 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1991 } 1992 1993 static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val) 1994 { 1995 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1996 } 1997 1998 static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val) 1999 { 2000 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2001 } 2002 2003 static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val) 2004 { 2005 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 2006 } 2007 2008 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val) 2009 { 2010 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2011 } 2012 2013 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val) 2014 { 2015 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 2016 } 2017 2018 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val) 2019 { 2020 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 2021 } 2022 2023 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val) 2024 { 2025 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); 2026 } 2027 2028 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val) 2029 { 2030 le32p_replace_bits((__le32 *)h2c, val, BIT(4)); 2031 } 2032 2033 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val) 2034 { 2035 le32p_replace_bits((__le32 *)h2c, val, BIT(5)); 2036 } 2037 2038 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val) 2039 { 2040 le32p_replace_bits((__le32 *)h2c, val, BIT(6)); 2041 } 2042 2043 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val) 2044 { 2045 le32p_replace_bits((__le32 *)h2c, val, BIT(7)); 2046 } 2047 2048 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val) 2049 { 2050 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2051 } 2052 2053 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val) 2054 { 2055 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2056 } 2057 2058 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val) 2059 { 2060 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1)); 2061 } 2062 2063 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val) 2064 { 2065 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0)); 2066 } 2067 2068 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val) 2069 { 2070 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0)); 2071 } 2072 2073 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val) 2074 { 2075 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0)); 2076 } 2077 2078 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val) 2079 { 2080 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0)); 2081 } 2082 2083 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val) 2084 { 2085 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0)); 2086 } 2087 2088 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val) 2089 { 2090 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22)); 2091 } 2092 2093 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val) 2094 { 2095 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23)); 2096 } 2097 2098 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val) 2099 { 2100 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24)); 2101 } 2102 2103 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val) 2104 { 2105 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25)); 2106 } 2107 2108 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val) 2109 { 2110 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26)); 2111 } 2112 2113 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val) 2114 { 2115 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31)); 2116 } 2117 2118 enum rtw89_btc_btf_h2c_class { 2119 BTFC_SET = 0x10, 2120 BTFC_GET = 0x11, 2121 BTFC_FW_EVENT = 0x12, 2122 }; 2123 2124 enum rtw89_btc_btf_set { 2125 SET_REPORT_EN = 0x0, 2126 SET_SLOT_TABLE, 2127 SET_MREG_TABLE, 2128 SET_CX_POLICY, 2129 SET_GPIO_DBG, 2130 SET_DRV_INFO, 2131 SET_DRV_EVENT, 2132 SET_BT_WREG_ADDR, 2133 SET_BT_WREG_VAL, 2134 SET_BT_RREG_ADDR, 2135 SET_BT_WL_CH_INFO, 2136 SET_BT_INFO_REPORT, 2137 SET_BT_IGNORE_WLAN_ACT, 2138 SET_BT_TX_PWR, 2139 SET_BT_LNA_CONSTRAIN, 2140 SET_BT_GOLDEN_RX_RANGE, 2141 SET_BT_PSD_REPORT, 2142 SET_H2C_TEST, 2143 SET_MAX1, 2144 }; 2145 2146 enum rtw89_btc_cxdrvinfo { 2147 CXDRVINFO_INIT = 0, 2148 CXDRVINFO_ROLE, 2149 CXDRVINFO_DBCC, 2150 CXDRVINFO_SMAP, 2151 CXDRVINFO_RFK, 2152 CXDRVINFO_RUN, 2153 CXDRVINFO_CTRL, 2154 CXDRVINFO_SCAN, 2155 CXDRVINFO_MAX, 2156 }; 2157 2158 enum rtw89_scan_mode { 2159 RTW89_SCAN_IMMEDIATE, 2160 }; 2161 2162 enum rtw89_scan_type { 2163 RTW89_SCAN_ONCE, 2164 }; 2165 2166 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) 2167 { 2168 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)); 2169 } 2170 2171 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) 2172 { 2173 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)); 2174 } 2175 2176 static inline void RTW89_SET_FWCMD_CXINIT_ANT_TYPE(void *cmd, u8 val) 2177 { 2178 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 2179 } 2180 2181 static inline void RTW89_SET_FWCMD_CXINIT_ANT_NUM(void *cmd, u8 val) 2182 { 2183 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 2184 } 2185 2186 static inline void RTW89_SET_FWCMD_CXINIT_ANT_ISO(void *cmd, u8 val) 2187 { 2188 u8p_replace_bits((u8 *)(cmd) + 4, val, GENMASK(7, 0)); 2189 } 2190 2191 static inline void RTW89_SET_FWCMD_CXINIT_ANT_POS(void *cmd, u8 val) 2192 { 2193 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(0)); 2194 } 2195 2196 static inline void RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(void *cmd, u8 val) 2197 { 2198 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(1)); 2199 } 2200 2201 static inline void RTW89_SET_FWCMD_CXINIT_MOD_RFE(void *cmd, u8 val) 2202 { 2203 u8p_replace_bits((u8 *)(cmd) + 6, val, GENMASK(7, 0)); 2204 } 2205 2206 static inline void RTW89_SET_FWCMD_CXINIT_MOD_CV(void *cmd, u8 val) 2207 { 2208 u8p_replace_bits((u8 *)(cmd) + 7, val, GENMASK(7, 0)); 2209 } 2210 2211 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(void *cmd, u8 val) 2212 { 2213 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(0)); 2214 } 2215 2216 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(void *cmd, u8 val) 2217 { 2218 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(1)); 2219 } 2220 2221 static inline void RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(void *cmd, u8 val) 2222 { 2223 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(2)); 2224 } 2225 2226 static inline void RTW89_SET_FWCMD_CXINIT_WL_GCH(void *cmd, u8 val) 2227 { 2228 u8p_replace_bits((u8 *)(cmd) + 10, val, GENMASK(7, 0)); 2229 } 2230 2231 static inline void RTW89_SET_FWCMD_CXINIT_WL_ONLY(void *cmd, u8 val) 2232 { 2233 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(0)); 2234 } 2235 2236 static inline void RTW89_SET_FWCMD_CXINIT_WL_INITOK(void *cmd, u8 val) 2237 { 2238 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(1)); 2239 } 2240 2241 static inline void RTW89_SET_FWCMD_CXINIT_DBCC_EN(void *cmd, u8 val) 2242 { 2243 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(2)); 2244 } 2245 2246 static inline void RTW89_SET_FWCMD_CXINIT_CX_OTHER(void *cmd, u8 val) 2247 { 2248 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(3)); 2249 } 2250 2251 static inline void RTW89_SET_FWCMD_CXINIT_BT_ONLY(void *cmd, u8 val) 2252 { 2253 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(4)); 2254 } 2255 2256 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) 2257 { 2258 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 2259 } 2260 2261 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) 2262 { 2263 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 2264 } 2265 2266 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) 2267 { 2268 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)); 2269 } 2270 2271 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) 2272 { 2273 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)); 2274 } 2275 2276 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) 2277 { 2278 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)); 2279 } 2280 2281 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) 2282 { 2283 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)); 2284 } 2285 2286 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) 2287 { 2288 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)); 2289 } 2290 2291 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) 2292 { 2293 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)); 2294 } 2295 2296 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) 2297 { 2298 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)); 2299 } 2300 2301 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) 2302 { 2303 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); 2304 } 2305 2306 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) 2307 { 2308 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)); 2309 } 2310 2311 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) 2312 { 2313 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)); 2314 } 2315 2316 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) 2317 { 2318 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)); 2319 } 2320 2321 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) 2322 { 2323 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)); 2324 } 2325 2326 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset) 2327 { 2328 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); 2329 } 2330 2331 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset) 2332 { 2333 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1)); 2334 } 2335 2336 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset) 2337 { 2338 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); 2339 } 2340 2341 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset) 2342 { 2343 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); 2344 } 2345 2346 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset) 2347 { 2348 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); 2349 } 2350 2351 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset) 2352 { 2353 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); 2354 } 2355 2356 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset) 2357 { 2358 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); 2359 } 2360 2361 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset) 2362 { 2363 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); 2364 } 2365 2366 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset) 2367 { 2368 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); 2369 } 2370 2371 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset) 2372 { 2373 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0)); 2374 } 2375 2376 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset) 2377 { 2378 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0)); 2379 } 2380 2381 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset) 2382 { 2383 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0)); 2384 } 2385 2386 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset) 2387 { 2388 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0)); 2389 } 2390 2391 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset) 2392 { 2393 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0)); 2394 } 2395 2396 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset) 2397 { 2398 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0)); 2399 } 2400 2401 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset) 2402 { 2403 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0)); 2404 } 2405 2406 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset) 2407 { 2408 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0)); 2409 } 2410 2411 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset) 2412 { 2413 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1)); 2414 } 2415 2416 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset) 2417 { 2418 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2)); 2419 } 2420 2421 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset) 2422 { 2423 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4)); 2424 } 2425 2426 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) 2427 { 2428 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)); 2429 } 2430 2431 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) 2432 { 2433 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)); 2434 } 2435 2436 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) 2437 { 2438 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)); 2439 } 2440 2441 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) 2442 { 2443 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)); 2444 } 2445 2446 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) 2447 { 2448 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)); 2449 } 2450 2451 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) 2452 { 2453 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)); 2454 } 2455 2456 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) 2457 { 2458 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)); 2459 } 2460 2461 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) 2462 { 2463 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)); 2464 } 2465 2466 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) 2467 { 2468 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)); 2469 } 2470 2471 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val) 2472 { 2473 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2474 } 2475 2476 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val) 2477 { 2478 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8)); 2479 } 2480 2481 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val) 2482 { 2483 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16)); 2484 } 2485 2486 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val) 2487 { 2488 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2489 } 2490 2491 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val) 2492 { 2493 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2494 } 2495 2496 static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val) 2497 { 2498 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2499 } 2500 2501 static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val) 2502 { 2503 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2504 } 2505 2506 static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val) 2507 { 2508 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16)); 2509 } 2510 2511 static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val) 2512 { 2513 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24)); 2514 } 2515 2516 static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val) 2517 { 2518 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0)); 2519 } 2520 2521 static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val) 2522 { 2523 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3)); 2524 } 2525 2526 static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val) 2527 { 2528 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8)); 2529 } 2530 2531 static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val) 2532 { 2533 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12)); 2534 } 2535 2536 static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val) 2537 { 2538 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13)); 2539 } 2540 2541 static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val) 2542 { 2543 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14)); 2544 } 2545 2546 static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val) 2547 { 2548 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16)); 2549 } 2550 2551 static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val) 2552 { 2553 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24)); 2554 } 2555 2556 static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val) 2557 { 2558 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25)); 2559 } 2560 2561 static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val) 2562 { 2563 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26)); 2564 } 2565 2566 static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val) 2567 { 2568 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27)); 2569 } 2570 2571 static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val) 2572 { 2573 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0)); 2574 } 2575 2576 static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val) 2577 { 2578 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8)); 2579 } 2580 2581 static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val) 2582 { 2583 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16)); 2584 } 2585 2586 static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val) 2587 { 2588 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24)); 2589 } 2590 2591 static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val) 2592 { 2593 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0)); 2594 } 2595 2596 static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val) 2597 { 2598 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8)); 2599 } 2600 2601 static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val) 2602 { 2603 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16)); 2604 } 2605 2606 static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val) 2607 { 2608 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24)); 2609 } 2610 2611 static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val) 2612 { 2613 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0)); 2614 } 2615 2616 static inline void RTW89_SET_FWCMD_SCANOFLD_MACID(void *cmd, u32 val) 2617 { 2618 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2619 } 2620 2621 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_CY(void *cmd, u32 val) 2622 { 2623 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2624 } 2625 2626 static inline void RTW89_SET_FWCMD_SCANOFLD_PORT_ID(void *cmd, u32 val) 2627 { 2628 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(18, 16)); 2629 } 2630 2631 static inline void RTW89_SET_FWCMD_SCANOFLD_BAND(void *cmd, u32 val) 2632 { 2633 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, BIT(19)); 2634 } 2635 2636 static inline void RTW89_SET_FWCMD_SCANOFLD_OPERATION(void *cmd, u32 val) 2637 { 2638 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(21, 20)); 2639 } 2640 2641 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BAND(void *cmd, u32 val) 2642 { 2643 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 22)); 2644 } 2645 2646 static inline void RTW89_SET_FWCMD_SCANOFLD_NOTIFY_END(void *cmd, u32 val) 2647 { 2648 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(0)); 2649 } 2650 2651 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_MODE(void *cmd, u32 val) 2652 { 2653 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(1)); 2654 } 2655 2656 static inline void RTW89_SET_FWCMD_SCANOFLD_START_MODE(void *cmd, u32 val) 2657 { 2658 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(2)); 2659 } 2660 2661 static inline void RTW89_SET_FWCMD_SCANOFLD_SCAN_TYPE(void *cmd, u32 val) 2662 { 2663 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(4, 3)); 2664 } 2665 2666 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BW(void *cmd, u32 val) 2667 { 2668 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 5)); 2669 } 2670 2671 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_PRI_CH(void *cmd, u32 val) 2672 { 2673 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 8)); 2674 } 2675 2676 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CENTRAL_CH(void *cmd, 2677 u32 val) 2678 { 2679 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16)); 2680 } 2681 2682 static inline void RTW89_SET_FWCMD_SCANOFLD_PROBE_REQ_PKT_ID(void *cmd, u32 val) 2683 { 2684 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(31, 24)); 2685 } 2686 2687 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_PD(void *cmd, u32 val) 2688 { 2689 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 0)); 2690 } 2691 2692 static inline void RTW89_SET_FWCMD_SCANOFLD_SLOW_PD(void *cmd, u32 val) 2693 { 2694 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16)); 2695 } 2696 2697 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_HIGH(void *cmd, u32 val) 2698 { 2699 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 0)); 2700 } 2701 2702 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_SLOW(void *cmd, u32 val) 2703 { 2704 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(31, 0)); 2705 } 2706 2707 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val) 2708 { 2709 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2710 } 2711 2712 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val) 2713 { 2714 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8)); 2715 } 2716 2717 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val) 2718 { 2719 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12)); 2720 } 2721 2722 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val) 2723 { 2724 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16)); 2725 } 2726 2727 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val) 2728 { 2729 le32p_replace_bits((__le32 *)cmd, val, BIT(20)); 2730 } 2731 2732 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val) 2733 { 2734 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 2735 } 2736 2737 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val) 2738 { 2739 *((__le32 *)cmd + 1) = val; 2740 } 2741 2742 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val) 2743 { 2744 *((__le32 *)cmd + 2) = val; 2745 } 2746 2747 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val) 2748 { 2749 *((__le32 *)cmd + 3) = val; 2750 } 2751 2752 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val) 2753 { 2754 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0)); 2755 } 2756 2757 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val) 2758 { 2759 u8 ctwnd; 2760 2761 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT)) 2762 return; 2763 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val); 2764 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8)); 2765 } 2766 2767 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val) 2768 { 2769 le32p_replace_bits((__le32 *)cmd, val, BIT(0)); 2770 } 2771 2772 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val) 2773 { 2774 le32p_replace_bits((__le32 *)cmd, val, BIT(1)); 2775 } 2776 2777 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val) 2778 { 2779 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2)); 2780 } 2781 2782 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val) 2783 { 2784 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16)); 2785 } 2786 2787 enum rtw89_fw_mcc_c2h_rpt_cfg { 2788 RTW89_FW_MCC_C2H_RPT_OFF = 0, 2789 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1, 2790 RTW89_FW_MCC_C2H_RPT_ALL = 2, 2791 }; 2792 2793 struct rtw89_fw_mcc_add_req { 2794 u8 macid; 2795 u8 central_ch_seg0; 2796 u8 central_ch_seg1; 2797 u8 primary_ch; 2798 enum rtw89_bandwidth bandwidth: 4; 2799 u32 group: 2; 2800 u32 c2h_rpt: 2; 2801 u32 dis_tx_null: 1; 2802 u32 dis_sw_retry: 1; 2803 u32 in_curr_ch: 1; 2804 u32 sw_retry_count: 3; 2805 u32 tx_null_early: 4; 2806 u32 btc_in_2g: 1; 2807 u32 pta_en: 1; 2808 u32 rfk_by_pass: 1; 2809 u32 ch_band_type: 2; 2810 u32 rsvd0: 9; 2811 u32 duration; 2812 u8 courtesy_en; 2813 u8 courtesy_num; 2814 u8 courtesy_target; 2815 u8 rsvd1; 2816 }; 2817 2818 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val) 2819 { 2820 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2821 } 2822 2823 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val) 2824 { 2825 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 2826 } 2827 2828 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val) 2829 { 2830 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 2831 } 2832 2833 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val) 2834 { 2835 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 2836 } 2837 2838 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val) 2839 { 2840 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0)); 2841 } 2842 2843 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val) 2844 { 2845 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4)); 2846 } 2847 2848 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val) 2849 { 2850 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6)); 2851 } 2852 2853 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val) 2854 { 2855 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8)); 2856 } 2857 2858 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val) 2859 { 2860 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9)); 2861 } 2862 2863 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val) 2864 { 2865 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10)); 2866 } 2867 2868 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val) 2869 { 2870 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11)); 2871 } 2872 2873 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val) 2874 { 2875 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14)); 2876 } 2877 2878 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val) 2879 { 2880 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18)); 2881 } 2882 2883 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val) 2884 { 2885 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19)); 2886 } 2887 2888 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val) 2889 { 2890 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20)); 2891 } 2892 2893 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val) 2894 { 2895 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21)); 2896 } 2897 2898 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val) 2899 { 2900 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 2901 } 2902 2903 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val) 2904 { 2905 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0)); 2906 } 2907 2908 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val) 2909 { 2910 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8)); 2911 } 2912 2913 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val) 2914 { 2915 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16)); 2916 } 2917 2918 struct rtw89_fw_mcc_start_req { 2919 u32 group: 2; 2920 u32 btc_in_group: 1; 2921 u32 old_group_action: 2; 2922 u32 old_group: 2; 2923 u32 rsvd0: 9; 2924 u32 notify_cnt: 3; 2925 u32 rsvd1: 2; 2926 u32 notify_rxdbg_en: 1; 2927 u32 rsvd2: 2; 2928 u32 macid: 8; 2929 u32 tsf_low; 2930 u32 tsf_high; 2931 }; 2932 2933 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val) 2934 { 2935 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 2936 } 2937 2938 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val) 2939 { 2940 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 2941 } 2942 2943 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val) 2944 { 2945 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3)); 2946 } 2947 2948 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val) 2949 { 2950 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5)); 2951 } 2952 2953 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val) 2954 { 2955 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16)); 2956 } 2957 2958 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val) 2959 { 2960 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 2961 } 2962 2963 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val) 2964 { 2965 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 2966 } 2967 2968 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val) 2969 { 2970 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 2971 } 2972 2973 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val) 2974 { 2975 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 2976 } 2977 2978 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val) 2979 { 2980 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2981 } 2982 2983 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val) 2984 { 2985 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8)); 2986 } 2987 2988 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val) 2989 { 2990 le32p_replace_bits((__le32 *)cmd, val, BIT(10)); 2991 } 2992 2993 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val) 2994 { 2995 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 2996 } 2997 2998 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val) 2999 { 3000 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3001 } 3002 3003 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val) 3004 { 3005 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3006 } 3007 3008 struct rtw89_fw_mcc_tsf_req { 3009 u8 group: 2; 3010 u8 rsvd0: 6; 3011 u8 macid_x; 3012 u8 macid_y; 3013 u8 rsvd1; 3014 }; 3015 3016 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val) 3017 { 3018 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3019 } 3020 3021 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val) 3022 { 3023 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3024 } 3025 3026 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val) 3027 { 3028 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3029 } 3030 3031 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val) 3032 { 3033 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3034 } 3035 3036 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val) 3037 { 3038 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3039 } 3040 3041 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val) 3042 { 3043 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3044 } 3045 3046 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd, 3047 u8 *bitmap, u8 len) 3048 { 3049 memcpy((__le32 *)cmd + 1, bitmap, len); 3050 } 3051 3052 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val) 3053 { 3054 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3055 } 3056 3057 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val) 3058 { 3059 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3060 } 3061 3062 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val) 3063 { 3064 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3065 } 3066 3067 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val) 3068 { 3069 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3070 } 3071 3072 struct rtw89_fw_mcc_duration { 3073 u32 group: 2; 3074 u32 btc_in_group: 1; 3075 u32 rsvd0: 5; 3076 u32 start_macid: 8; 3077 u32 macid_x: 8; 3078 u32 macid_y: 8; 3079 u32 start_tsf_low; 3080 u32 start_tsf_high; 3081 u32 duration_x; 3082 u32 duration_y; 3083 }; 3084 3085 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val) 3086 { 3087 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3088 } 3089 3090 static 3091 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val) 3092 { 3093 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3094 } 3095 3096 static 3097 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val) 3098 { 3099 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3100 } 3101 3102 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val) 3103 { 3104 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3105 } 3106 3107 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val) 3108 { 3109 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3110 } 3111 3112 static 3113 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val) 3114 { 3115 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 3116 } 3117 3118 static 3119 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val) 3120 { 3121 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 3122 } 3123 3124 static 3125 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val) 3126 { 3127 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 3128 } 3129 3130 static 3131 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val) 3132 { 3133 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 3134 } 3135 3136 #define RTW89_C2H_HEADER_LEN 8 3137 3138 #define RTW89_GET_C2H_CATEGORY(c2h) \ 3139 le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0)) 3140 #define RTW89_GET_C2H_CLASS(c2h) \ 3141 le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2)) 3142 #define RTW89_GET_C2H_FUNC(c2h) \ 3143 le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8)) 3144 #define RTW89_GET_C2H_LEN(c2h) \ 3145 le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0)) 3146 3147 struct rtw89_fw_c2h_attr { 3148 u8 category; 3149 u8 class; 3150 u8 func; 3151 u16 len; 3152 }; 3153 3154 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb) 3155 { 3156 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr)); 3157 3158 return (struct rtw89_fw_c2h_attr *)skb->cb; 3159 } 3160 3161 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2) 3162 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN) 3163 3164 #define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \ 3165 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3166 #define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \ 3167 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3168 #define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \ 3169 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3170 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \ 3171 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3172 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \ 3173 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24)) 3174 3175 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ 3176 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3177 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ 3178 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3179 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ 3180 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3181 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ 3182 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3183 3184 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \ 3185 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0)) 3186 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \ 3187 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3188 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \ 3189 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0)) 3190 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \ 3191 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8)) 3192 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \ 3193 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10)) 3194 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \ 3195 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13)) 3196 3197 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS 3198 * HT-new: [6:5]: NA, [4:0]: MCS 3199 */ 3200 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) 3201 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) 3202 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0) 3203 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ 3204 FIELD_PREP(GENMASK(2, 0), mcs)) 3205 3206 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \ 3207 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3208 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \ 3209 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8)) 3210 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \ 3211 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16)) 3212 3213 #define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \ 3214 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3215 #define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \ 3216 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16)) 3217 #define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \ 3218 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20)) 3219 #define RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h) \ 3220 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24)) 3221 #define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \ 3222 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0)) 3223 #define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \ 3224 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4)) 3225 #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \ 3226 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24)) 3227 3228 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \ 3229 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3230 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \ 3231 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3232 3233 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \ 3234 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3235 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \ 3236 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3237 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \ 3238 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3239 3240 struct rtw89_mac_mcc_tsf_rpt { 3241 u32 macid_x; 3242 u32 macid_y; 3243 u32 tsf_x_low; 3244 u32 tsf_x_high; 3245 u32 tsf_y_low; 3246 u32 tsf_y_high; 3247 }; 3248 3249 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE); 3250 3251 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \ 3252 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3253 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \ 3254 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3255 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \ 3256 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16)) 3257 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \ 3258 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0)) 3259 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \ 3260 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0)) 3261 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \ 3262 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0)) 3263 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \ 3264 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0)) 3265 3266 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \ 3267 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0)) 3268 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \ 3269 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6)) 3270 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \ 3271 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3272 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \ 3273 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0)) 3274 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \ 3275 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0)) 3276 3277 #define RTW89_FW_HDR_SIZE 32 3278 #define RTW89_FW_SECTION_HDR_SIZE 16 3279 3280 #define RTW89_MFW_SIG 0xFF 3281 3282 struct rtw89_mfw_info { 3283 u8 cv; 3284 u8 type; /* enum rtw89_fw_type */ 3285 u8 mp; 3286 u8 rsvd; 3287 __le32 shift; 3288 __le32 size; 3289 u8 rsvd2[4]; 3290 } __packed; 3291 3292 struct rtw89_mfw_hdr { 3293 u8 sig; /* RTW89_MFW_SIG */ 3294 u8 fw_nr; 3295 u8 rsvd0[2]; 3296 struct { 3297 u8 major; 3298 u8 minor; 3299 u8 sub; 3300 u8 idx; 3301 } ver; 3302 u8 rsvd1[8]; 3303 struct rtw89_mfw_info info[]; 3304 } __packed; 3305 3306 struct fwcmd_hdr { 3307 __le32 hdr0; 3308 __le32 hdr1; 3309 }; 3310 3311 union rtw89_compat_fw_hdr { 3312 struct rtw89_mfw_hdr mfw_hdr; 3313 u8 fw_hdr[RTW89_FW_HDR_SIZE]; 3314 }; 3315 3316 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf) 3317 { 3318 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf; 3319 3320 if (compat->mfw_hdr.sig == RTW89_MFW_SIG) 3321 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr); 3322 else 3323 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr); 3324 } 3325 3326 #define RTW89_H2C_RF_PAGE_SIZE 500 3327 #define RTW89_H2C_RF_PAGE_NUM 3 3328 struct rtw89_fw_h2c_rf_reg_info { 3329 enum rtw89_rf_path rf_path; 3330 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; 3331 u16 curr_idx; 3332 }; 3333 3334 #define H2C_SEC_CAM_LEN 24 3335 3336 #define H2C_HEADER_LEN 8 3337 #define H2C_HDR_CAT GENMASK(1, 0) 3338 #define H2C_HDR_CLASS GENMASK(7, 2) 3339 #define H2C_HDR_FUNC GENMASK(15, 8) 3340 #define H2C_HDR_DEL_TYPE GENMASK(19, 16) 3341 #define H2C_HDR_H2C_SEQ GENMASK(31, 24) 3342 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0) 3343 #define H2C_HDR_REC_ACK BIT(14) 3344 #define H2C_HDR_DONE_ACK BIT(15) 3345 3346 #define FWCMD_TYPE_H2C 0 3347 3348 #define H2C_CAT_TEST 0x0 3349 3350 /* CLASS 5 - FW STATUS TEST */ 3351 #define H2C_CL_FW_STATUS_TEST 0x5 3352 #define H2C_FUNC_CPU_EXCEPTION 0x1 3353 3354 #define H2C_CAT_MAC 0x1 3355 3356 /* CLASS 0 - FW INFO */ 3357 #define H2C_CL_FW_INFO 0x0 3358 #define H2C_FUNC_LOG_CFG 0x0 3359 #define H2C_FUNC_MAC_GENERAL_PKT 0x1 3360 3361 /* CLASS 1 - WOW */ 3362 #define H2C_CL_MAC_WOW 0x1 3363 #define H2C_FUNC_KEEP_ALIVE 0x0 3364 #define H2C_FUNC_DISCONNECT_DETECT 0x1 3365 #define H2C_FUNC_WOW_GLOBAL 0x2 3366 #define H2C_FUNC_WAKEUP_CTRL 0x8 3367 #define H2C_FUNC_WOW_CAM_UPD 0xC 3368 3369 /* CLASS 2 - PS */ 3370 #define H2C_CL_MAC_PS 0x2 3371 #define H2C_FUNC_MAC_LPS_PARM 0x0 3372 #define H2C_FUNC_P2P_ACT 0x1 3373 3374 /* CLASS 3 - FW download */ 3375 #define H2C_CL_MAC_FWDL 0x3 3376 #define H2C_FUNC_MAC_FWHDR_DL 0x0 3377 3378 /* CLASS 5 - Frame Exchange */ 3379 #define H2C_CL_MAC_FR_EXCHG 0x5 3380 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2 3381 #define H2C_FUNC_MAC_BCN_UPD 0x5 3382 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9 3383 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa 3384 3385 /* CLASS 6 - Address CAM */ 3386 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 3387 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 3388 3389 /* CLASS 8 - Media Status Report */ 3390 #define H2C_CL_MAC_MEDIA_RPT 0x8 3391 #define H2C_FUNC_MAC_JOININFO 0x0 3392 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 3393 3394 /* CLASS 9 - FW offload */ 3395 #define H2C_CL_MAC_FW_OFLD 0x9 3396 #define H2C_FUNC_PACKET_OFLD 0x1 3397 #define H2C_FUNC_MAC_MACID_PAUSE 0x8 3398 #define H2C_FUNC_USR_EDCA 0xF 3399 #define H2C_FUNC_TSF32_TOGL 0x10 3400 #define H2C_FUNC_OFLD_CFG 0x14 3401 #define H2C_FUNC_ADD_SCANOFLD_CH 0x16 3402 #define H2C_FUNC_SCANOFLD 0x17 3403 #define H2C_FUNC_PKT_DROP 0x1b 3404 3405 /* CLASS 10 - Security CAM */ 3406 #define H2C_CL_MAC_SEC_CAM 0xa 3407 #define H2C_FUNC_MAC_SEC_UPD 0x1 3408 3409 /* CLASS 12 - BA CAM */ 3410 #define H2C_CL_BA_CAM 0xc 3411 #define H2C_FUNC_MAC_BA_CAM 0x0 3412 3413 /* CLASS 14 - MCC */ 3414 #define H2C_CL_MCC 0xe 3415 enum rtw89_mcc_h2c_func { 3416 H2C_FUNC_ADD_MCC = 0x0, 3417 H2C_FUNC_START_MCC = 0x1, 3418 H2C_FUNC_STOP_MCC = 0x2, 3419 H2C_FUNC_DEL_MCC_GROUP = 0x3, 3420 H2C_FUNC_RESET_MCC_GROUP = 0x4, 3421 H2C_FUNC_MCC_REQ_TSF = 0x5, 3422 H2C_FUNC_MCC_MACID_BITMAP = 0x6, 3423 H2C_FUNC_MCC_SYNC = 0x7, 3424 H2C_FUNC_MCC_SET_DURATION = 0x8, 3425 3426 NUM_OF_RTW89_MCC_H2C_FUNC, 3427 }; 3428 3429 #define RTW89_MCC_WAIT_COND(group, func) \ 3430 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func)) 3431 3432 #define H2C_CAT_OUTSRC 0x2 3433 3434 #define H2C_CL_OUTSRC_RA 0x1 3435 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 3436 3437 #define H2C_CL_OUTSRC_RF_REG_A 0x8 3438 #define H2C_CL_OUTSRC_RF_REG_B 0x9 3439 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa 3440 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2 3441 3442 struct rtw89_fw_h2c_rf_get_mccch { 3443 __le32 ch_0; 3444 __le32 ch_1; 3445 __le32 band_0; 3446 __le32 band_1; 3447 __le32 current_channel; 3448 __le32 current_band_type; 3449 } __packed; 3450 3451 #define RTW89_FW_RSVD_PLE_SIZE 0x800 3452 3453 #define RTW89_WCPU_BASE_MASK GENMASK(27, 0) 3454 3455 #define RTW89_FW_BACKTRACE_INFO_SIZE 8 3456 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \ 3457 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0) 3458 3459 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */ 3460 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE 3461 3462 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev); 3463 int rtw89_fw_recognize(struct rtw89_dev *rtwdev); 3464 const struct firmware * 3465 rtw89_early_fw_feature_recognize(struct device *device, 3466 const struct rtw89_chip_info *chip, 3467 u32 *early_feat_map); 3468 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type); 3469 int rtw89_load_firmware(struct rtw89_dev *rtwdev); 3470 void rtw89_unload_firmware(struct rtw89_dev *rtwdev); 3471 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); 3472 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3473 u8 type, u8 cat, u8 class, u8 func, 3474 bool rack, bool dack, u32 len); 3475 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, 3476 struct rtw89_vif *rtwvif); 3477 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 3478 struct ieee80211_vif *vif, 3479 struct ieee80211_sta *sta); 3480 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, 3481 struct rtw89_sta *rtwsta); 3482 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev, 3483 struct rtw89_sta *rtwsta); 3484 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev, 3485 struct rtw89_vif *rtwvif); 3486 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif, 3487 struct rtw89_sta *rtwsta, const u8 *scan_mac_addr); 3488 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev, 3489 struct rtw89_vif *rtwvif, 3490 struct rtw89_sta *rtwsta); 3491 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); 3492 void rtw89_fw_c2h_work(struct work_struct *work); 3493 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev, 3494 struct rtw89_vif *rtwvif, 3495 struct rtw89_sta *rtwsta, 3496 enum rtw89_upd_mode upd_mode); 3497 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3498 struct rtw89_sta *rtwsta, bool dis_conn); 3499 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, 3500 bool pause); 3501 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3502 u8 ac, u32 val); 3503 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); 3504 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); 3505 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); 3506 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); 3507 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev); 3508 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); 3509 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); 3510 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id); 3511 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id, 3512 struct sk_buff *skb_ofld); 3513 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len, 3514 struct list_head *chan_list); 3515 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev, 3516 struct rtw89_scan_option *opt, 3517 struct rtw89_vif *vif); 3518 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, 3519 struct rtw89_fw_h2c_rf_reg_info *info, 3520 u16 len, u8 page); 3521 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev); 3522 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 3523 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 3524 bool rack, bool dack); 3525 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); 3526 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); 3527 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); 3528 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3529 u8 macid); 3530 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev, 3531 struct rtw89_vif *rtwvif, bool notify_fw); 3532 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw); 3533 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3534 bool valid, struct ieee80211_ampdu_params *params); 3535 void rtw89_fw_h2c_init_ba_cam_v1(struct rtw89_dev *rtwdev); 3536 3537 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, 3538 struct rtw89_lps_parm *lps_param); 3539 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len); 3540 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len); 3541 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, 3542 struct rtw89_mac_h2c_info *h2c_info, 3543 struct rtw89_mac_c2h_info *c2h_info); 3544 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); 3545 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); 3546 void rtw89_store_op_chan(struct rtw89_dev *rtwdev, bool backup); 3547 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3548 struct ieee80211_scan_request *req); 3549 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3550 bool aborted); 3551 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3552 bool enable); 3553 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 3554 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev); 3555 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev, 3556 const struct rtw89_pkt_drop_params *params); 3557 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3558 struct ieee80211_p2p_noa_desc *desc, 3559 u8 act, u8 noa_id); 3560 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3561 bool en); 3562 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3563 bool enable); 3564 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 3565 struct rtw89_vif *rtwvif, bool enable); 3566 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3567 bool enable); 3568 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev, 3569 struct rtw89_vif *rtwvif, bool enable); 3570 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3571 bool enable); 3572 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 3573 struct rtw89_vif *rtwvif, bool enable); 3574 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev, 3575 struct rtw89_wow_cam_info *cam_info); 3576 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev, 3577 const struct rtw89_fw_mcc_add_req *p); 3578 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev, 3579 const struct rtw89_fw_mcc_start_req *p); 3580 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid, 3581 bool prev_groups); 3582 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group, 3583 bool prev_groups); 3584 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group); 3585 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev, 3586 const struct rtw89_fw_mcc_tsf_req *req, 3587 struct rtw89_mac_mcc_tsf_rpt *rpt); 3588 int rtw89_fw_h2c_mcc_macid_bitamp(struct rtw89_dev *rtwdev, u8 group, u8 macid, 3589 u8 *bitmap); 3590 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source, 3591 u8 target, u8 offset); 3592 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev, 3593 const struct rtw89_fw_mcc_duration *p); 3594 3595 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev) 3596 { 3597 const struct rtw89_chip_info *chip = rtwdev->chip; 3598 3599 if (chip->bacam_v1) 3600 rtw89_fw_h2c_init_ba_cam_v1(rtwdev); 3601 } 3602 3603 #endif 3604