xref: /linux/drivers/net/wireless/realtek/rtw89/fw.h (revision c5288cda69ee2d8607f5026bd599a5cebf0ee783)
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7 
8 #include "core.h"
9 
10 enum rtw89_fw_dl_status {
11 	RTW89_FWDL_INITIAL_STATE = 0,
12 	RTW89_FWDL_FWDL_ONGOING = 1,
13 	RTW89_FWDL_CHECKSUM_FAIL = 2,
14 	RTW89_FWDL_SECURITY_FAIL = 3,
15 	RTW89_FWDL_CV_NOT_MATCH = 4,
16 	RTW89_FWDL_RSVD0 = 5,
17 	RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 	RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20 
21 struct rtw89_c2hreg_hdr {
22 	u32 w0;
23 };
24 
25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
29 
30 struct rtw89_c2hreg_phycap {
31 	u32 w0;
32 	u32 w1;
33 	u32 w2;
34 	u32 w3;
35 } __packed;
36 
37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
47 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
48 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
49 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
50 
51 #define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)
52 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)
53 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8)
54 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16)
55 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)
56 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0)
57 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8)
58 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16)
59 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)
60 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0)
61 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8)
62 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16)
63 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)
64 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16)
65 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)
66 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0)
67 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8)
68 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16)
69 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)
70 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0)
71 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8)
72 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16)
73 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)
74 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0)
75 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8)
76 
77 struct rtw89_h2creg_hdr {
78 	u32 w0;
79 };
80 
81 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
82 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
83 
84 struct rtw89_h2creg_sch_tx_en {
85 	u32 w0;
86 	u32 w1;
87 } __packed;
88 
89 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
90 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
91 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
92 
93 #define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
94 
95 #define RTW89_H2CREG_MAX 4
96 #define RTW89_C2HREG_MAX 4
97 #define RTW89_C2HREG_HDR_LEN 2
98 #define RTW89_H2CREG_HDR_LEN 2
99 #define RTW89_C2H_TIMEOUT 1000000
100 struct rtw89_mac_c2h_info {
101 	u8 id;
102 	u8 content_len;
103 	union {
104 		u32 c2hreg[RTW89_C2HREG_MAX];
105 		struct rtw89_c2hreg_hdr hdr;
106 		struct rtw89_c2hreg_phycap phycap;
107 	} u;
108 };
109 
110 struct rtw89_mac_h2c_info {
111 	u8 id;
112 	u8 content_len;
113 	union {
114 		u32 h2creg[RTW89_H2CREG_MAX];
115 		struct rtw89_h2creg_hdr hdr;
116 		struct rtw89_h2creg_sch_tx_en sch_tx_en;
117 	} u;
118 };
119 
120 enum rtw89_mac_h2c_type {
121 	RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
122 	RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
123 	RTW89_FWCMD_H2CREG_FUNC_FWERR,
124 	RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
125 	RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
126 	RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN,
127 	RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP,
128 	RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_1,
129 	RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_2,
130 	RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_3_REQ,
131 	RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL,
132 };
133 
134 enum rtw89_mac_c2h_type {
135 	RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
136 	RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
137 	RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
138 	RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
139 	RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
140 	RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA,
141 	RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF,
142 };
143 
144 enum rtw89_fw_c2h_category {
145 	RTW89_C2H_CAT_TEST,
146 	RTW89_C2H_CAT_MAC,
147 	RTW89_C2H_CAT_OUTSRC,
148 };
149 
150 enum rtw89_fw_log_level {
151 	RTW89_FW_LOG_LEVEL_OFF,
152 	RTW89_FW_LOG_LEVEL_CRT,
153 	RTW89_FW_LOG_LEVEL_SER,
154 	RTW89_FW_LOG_LEVEL_WARN,
155 	RTW89_FW_LOG_LEVEL_LOUD,
156 	RTW89_FW_LOG_LEVEL_TR,
157 };
158 
159 enum rtw89_fw_log_path {
160 	RTW89_FW_LOG_LEVEL_UART,
161 	RTW89_FW_LOG_LEVEL_C2H,
162 	RTW89_FW_LOG_LEVEL_SNI,
163 };
164 
165 enum rtw89_fw_log_comp {
166 	RTW89_FW_LOG_COMP_VER,
167 	RTW89_FW_LOG_COMP_INIT,
168 	RTW89_FW_LOG_COMP_TASK,
169 	RTW89_FW_LOG_COMP_CNS,
170 	RTW89_FW_LOG_COMP_H2C,
171 	RTW89_FW_LOG_COMP_C2H,
172 	RTW89_FW_LOG_COMP_TX,
173 	RTW89_FW_LOG_COMP_RX,
174 	RTW89_FW_LOG_COMP_IPSEC,
175 	RTW89_FW_LOG_COMP_TIMER,
176 	RTW89_FW_LOG_COMP_DBGPKT,
177 	RTW89_FW_LOG_COMP_PS,
178 	RTW89_FW_LOG_COMP_ERROR,
179 	RTW89_FW_LOG_COMP_WOWLAN,
180 	RTW89_FW_LOG_COMP_SECURE_BOOT,
181 	RTW89_FW_LOG_COMP_BTC,
182 	RTW89_FW_LOG_COMP_BB,
183 	RTW89_FW_LOG_COMP_TWT,
184 	RTW89_FW_LOG_COMP_RF,
185 	RTW89_FW_LOG_COMP_MCC = 20,
186 	RTW89_FW_LOG_COMP_SCAN = 28,
187 };
188 
189 enum rtw89_pkt_offload_op {
190 	RTW89_PKT_OFLD_OP_ADD,
191 	RTW89_PKT_OFLD_OP_DEL,
192 	RTW89_PKT_OFLD_OP_READ,
193 
194 	NUM_OF_RTW89_PKT_OFFLOAD_OP,
195 };
196 
197 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
198 	((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
199 
200 enum rtw89_scanofld_notify_reason {
201 	RTW89_SCAN_DWELL_NOTIFY,
202 	RTW89_SCAN_PRE_TX_NOTIFY,
203 	RTW89_SCAN_POST_TX_NOTIFY,
204 	RTW89_SCAN_ENTER_CH_NOTIFY,
205 	RTW89_SCAN_LEAVE_CH_NOTIFY,
206 	RTW89_SCAN_END_SCAN_NOTIFY,
207 	RTW89_SCAN_REPORT_NOTIFY,
208 	RTW89_SCAN_CHKPT_NOTIFY,
209 	RTW89_SCAN_ENTER_OP_NOTIFY,
210 	RTW89_SCAN_LEAVE_OP_NOTIFY,
211 };
212 
213 enum rtw89_scanofld_status {
214 	RTW89_SCAN_STATUS_NOTIFY,
215 	RTW89_SCAN_STATUS_SUCCESS,
216 	RTW89_SCAN_STATUS_FAIL,
217 };
218 
219 enum rtw89_chan_type {
220 	RTW89_CHAN_OPERATE = 0,
221 	RTW89_CHAN_ACTIVE,
222 	RTW89_CHAN_DFS,
223 };
224 
225 enum rtw89_p2pps_action {
226 	RTW89_P2P_ACT_INIT = 0,
227 	RTW89_P2P_ACT_UPDATE = 1,
228 	RTW89_P2P_ACT_REMOVE = 2,
229 	RTW89_P2P_ACT_TERMINATE = 3,
230 };
231 
232 #define RTW89_DEFAULT_CQM_HYST 4
233 #define RTW89_DEFAULT_CQM_THOLD -70
234 
235 enum rtw89_bcn_fltr_offload_mode {
236 	RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
237 	RTW89_BCN_FLTR_OFFLOAD_MODE_1,
238 	RTW89_BCN_FLTR_OFFLOAD_MODE_2,
239 	RTW89_BCN_FLTR_OFFLOAD_MODE_3,
240 
241 	RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
242 };
243 
244 enum rtw89_bcn_fltr_type {
245 	RTW89_BCN_FLTR_BEACON_LOSS,
246 	RTW89_BCN_FLTR_RSSI,
247 	RTW89_BCN_FLTR_NOTIFY,
248 };
249 
250 enum rtw89_bcn_fltr_rssi_event {
251 	RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
252 	RTW89_BCN_FLTR_RSSI_HIGH,
253 	RTW89_BCN_FLTR_RSSI_LOW,
254 };
255 
256 #define FWDL_SECTION_MAX_NUM 10
257 #define FWDL_SECTION_CHKSUM_LEN	8
258 #define FWDL_SECTION_PER_PKT_LEN 2020
259 
260 struct rtw89_fw_hdr_section_info {
261 	u8 redl;
262 	const u8 *addr;
263 	u32 len;
264 	u32 dladdr;
265 	u32 mssc;
266 	u8 type;
267 	bool ignore;
268 	const u8 *key_addr;
269 	u32 key_len;
270 	u32 key_idx;
271 };
272 
273 struct rtw89_fw_bin_info {
274 	u8 section_num;
275 	u32 hdr_len;
276 	bool dynamic_hdr_en;
277 	u32 dynamic_hdr_len;
278 	bool dsp_checksum;
279 	bool secure_section_exist;
280 	struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
281 };
282 
283 struct rtw89_fw_macid_pause_grp {
284 	__le32 pause_grp[4];
285 	__le32 mask_grp[4];
286 } __packed;
287 
288 struct rtw89_fw_macid_pause_sleep_grp {
289 	struct {
290 		__le32 pause_grp[4];
291 		__le32 pause_mask_grp[4];
292 		__le32 sleep_grp[4];
293 		__le32 sleep_mask_grp[4];
294 	} __packed n[4];
295 } __packed;
296 
297 #define RTW89_H2C_MAX_SIZE 2048
298 #define RTW89_CHANNEL_TIME 45
299 #define RTW89_CHANNEL_TIME_6G 20
300 #define RTW89_DFS_CHAN_TIME 105
301 #define RTW89_OFF_CHAN_TIME 100
302 #define RTW89_DWELL_TIME 20
303 #define RTW89_DWELL_TIME_6G 10
304 #define RTW89_SCAN_WIDTH 0
305 #define RTW89_SCANOFLD_MAX_SSID 8
306 #define RTW89_SCANOFLD_MAX_IE_LEN 512
307 #define RTW89_SCANOFLD_PKT_NONE 0xFF
308 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
309 #define RTW89_CHAN_INVALID 0xFF
310 #define RTW89_MAC_CHINFO_SIZE 28
311 #define RTW89_SCAN_LIST_GUARD 4
312 #define RTW89_SCAN_LIST_LIMIT \
313 		((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD)
314 
315 #define RTW89_BCN_LOSS_CNT 10
316 
317 struct rtw89_mac_chinfo {
318 	u8 period;
319 	u8 dwell_time;
320 	u8 central_ch;
321 	u8 pri_ch;
322 	u8 bw:3;
323 	u8 notify_action:5;
324 	u8 num_pkt:4;
325 	u8 tx_pkt:1;
326 	u8 pause_data:1;
327 	u8 ch_band:2;
328 	u8 probe_id;
329 	u8 dfs_ch:1;
330 	u8 tx_null:1;
331 	u8 rand_seq_num:1;
332 	u8 cfg_tx_pwr:1;
333 	u8 rsvd0: 4;
334 	u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
335 	u16 tx_pwr_idx;
336 	u8 rsvd1;
337 	struct list_head list;
338 	bool is_psc;
339 };
340 
341 struct rtw89_mac_chinfo_be {
342 	u8 period;
343 	u8 dwell_time;
344 	u8 central_ch;
345 	u8 pri_ch;
346 	u8 bw:3;
347 	u8 ch_band:2;
348 	u8 dfs_ch:1;
349 	u8 pause_data:1;
350 	u8 tx_null:1;
351 	u8 rand_seq_num:1;
352 	u8 notify_action:5;
353 	u8 probe_id;
354 	u8 leave_crit;
355 	u8 chkpt_timer;
356 	u8 leave_time;
357 	u8 leave_th;
358 	u16 tx_pkt_ctrl;
359 	u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
360 	u8 sw_def;
361 	u16 fw_probe0_ssids;
362 	u16 fw_probe0_shortssids;
363 	u16 fw_probe0_bssids;
364 
365 	struct list_head list;
366 	bool is_psc;
367 };
368 
369 struct rtw89_pktofld_info {
370 	struct list_head list;
371 	u8 id;
372 	bool wildcard_6ghz;
373 
374 	/* Below fields are for WiFi 6 chips 6 GHz RNR use only */
375 	u8 ssid[IEEE80211_MAX_SSID_LEN];
376 	u8 ssid_len;
377 	u8 bssid[ETH_ALEN];
378 	u16 channel_6ghz;
379 	bool cancel;
380 };
381 
382 struct rtw89_h2c_ra {
383 	__le32 w0;
384 	__le32 w1;
385 	__le32 w2;
386 	__le32 w3;
387 } __packed;
388 
389 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
390 #define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)
391 #define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
392 #define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
393 #define RTW89_H2C_RA_W0_DCM BIT(16)
394 #define RTW89_H2C_RA_W0_ER BIT(17)
395 #define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)
396 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
397 #define RTW89_H2C_RA_W0_SGI BIT(21)
398 #define RTW89_H2C_RA_W0_LDPC BIT(22)
399 #define RTW89_H2C_RA_W0_STBC BIT(23)
400 #define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
401 #define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)
402 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
403 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
404 #define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
405 #define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)
406 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
407 #define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
408 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
409 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
410 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
411 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
412 #define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
413 #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
414 #define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
415 #define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
416 #define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
417 
418 struct rtw89_h2c_ra_v1 {
419 	struct rtw89_h2c_ra v0;
420 	__le32 w4;
421 	__le32 w5;
422 } __packed;
423 
424 #define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)
425 #define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
426 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
427 #define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
428 
429 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
430 {
431 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
432 }
433 
434 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
435 {
436 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
437 }
438 
439 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
440 {
441 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
442 }
443 
444 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
445 {
446 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
447 }
448 
449 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
450 {
451 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
452 }
453 
454 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
455 {
456 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
457 }
458 
459 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
460 {
461 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
462 }
463 
464 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
465 {
466 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
467 }
468 
469 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
470 {
471 	le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
472 }
473 
474 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
475 {
476 	le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
477 }
478 
479 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
480 {
481 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
482 }
483 
484 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
485 {
486 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
487 }
488 
489 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
490 {
491 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
492 }
493 
494 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
495 {
496 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
497 }
498 
499 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
500 {
501 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
502 }
503 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
504 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
505 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
506 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
507 
508 #define FWDL_SECURITY_SECTION_TYPE 9
509 #define FWDL_SECURITY_SIGLEN 512
510 #define FWDL_SECURITY_CHKSUM_LEN 8
511 
512 struct rtw89_fw_dynhdr_sec {
513 	__le32 w0;
514 	u8 content[];
515 } __packed;
516 
517 struct rtw89_fw_dynhdr_hdr {
518 	__le32 hdr_len;
519 	__le32 setcion_count;
520 	/* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
521 } __packed;
522 
523 struct rtw89_fw_hdr_section {
524 	__le32 w0;
525 	__le32 w1;
526 	__le32 w2;
527 	__le32 w3;
528 } __packed;
529 
530 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
531 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
532 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
533 #define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
534 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
535 #define FWSECTION_HDR_W1_REDL BIT(29)
536 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
537 
538 struct rtw89_fw_hdr {
539 	__le32 w0;
540 	__le32 w1;
541 	__le32 w2;
542 	__le32 w3;
543 	__le32 w4;
544 	__le32 w5;
545 	__le32 w6;
546 	__le32 w7;
547 	struct rtw89_fw_hdr_section sections[];
548 	/* struct rtw89_fw_dynhdr_hdr (optional) */
549 } __packed;
550 
551 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
552 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
553 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
554 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
555 #define FW_HDR_W2_COMMITID GENMASK(31, 0)
556 #define FW_HDR_W3_LEN GENMASK(23, 16)
557 #define FW_HDR_W3_HDR_VER GENMASK(31, 24)
558 #define FW_HDR_W4_MONTH GENMASK(7, 0)
559 #define FW_HDR_W4_DATE GENMASK(15, 8)
560 #define FW_HDR_W4_HOUR GENMASK(23, 16)
561 #define FW_HDR_W4_MIN GENMASK(31, 24)
562 #define FW_HDR_W5_YEAR GENMASK(31, 0)
563 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
564 #define FW_HDR_W7_PART_SIZE GENMASK(15, 0)
565 #define FW_HDR_W7_DYN_HDR BIT(16)
566 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
567 
568 struct rtw89_fw_hdr_section_v1 {
569 	__le32 w0;
570 	__le32 w1;
571 	__le32 w2;
572 	__le32 w3;
573 } __packed;
574 
575 #define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
576 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
577 #define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
578 #define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)
579 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
580 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
581 #define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
582 #define FORMATTED_MSSC 0xFF
583 #define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
584 
585 struct rtw89_fw_hdr_v1 {
586 	__le32 w0;
587 	__le32 w1;
588 	__le32 w2;
589 	__le32 w3;
590 	__le32 w4;
591 	__le32 w5;
592 	__le32 w6;
593 	__le32 w7;
594 	__le32 w8;
595 	__le32 w9;
596 	__le32 w10;
597 	__le32 w11;
598 	struct rtw89_fw_hdr_section_v1 sections[];
599 } __packed;
600 
601 #define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
602 #define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
603 #define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
604 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
605 #define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
606 #define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
607 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
608 #define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
609 #define FW_HDR_V1_W4_DATE GENMASK(15, 8)
610 #define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
611 #define FW_HDR_V1_W4_MIN GENMASK(31, 24)
612 #define FW_HDR_V1_W5_YEAR GENMASK(15, 0)
613 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
614 #define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
615 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
616 #define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0)
617 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
618 
619 enum rtw89_fw_mss_pool_rmp_tbl_type {
620 	MSS_POOL_RMP_TBL_BITMASK = 0x0,
621 	MSS_POOL_RMP_TBL_RECORD = 0x1,
622 };
623 
624 #define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8
625 
626 struct rtw89_fw_mss_pool_hdr {
627 	u8 signature[8]; /* equal to mss_signature[] */
628 	__le32 rmp_tbl_offset;
629 	__le32 key_raw_offset;
630 	u8 defen;
631 	u8 rsvd[3];
632 	u8 rmpfmt; /* enum rtw89_fw_mss_pool_rmp_tbl_type */
633 	u8 mssdev_max;
634 	__le16 keypair_num;
635 	__le16 msscust_max;
636 	__le16 msskey_num_max;
637 	__le32 rsvd3;
638 	u8 rmp_tbl[];
639 } __packed;
640 
641 union rtw89_fw_section_mssc_content {
642 	struct {
643 		u8 pad[58];
644 		__le32 v;
645 	} __packed sb_sel_ver;
646 	struct {
647 		u8 pad[60];
648 		__le16 v;
649 	} __packed key_sign_len;
650 } __packed;
651 
652 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
653 {
654 	le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
655 }
656 
657 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
658 {
659 	le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
660 }
661 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
662 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
663 {
664 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
665 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
666 			   GENMASK(8, 0));
667 }
668 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
669 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
670 {
671 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
672 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
673 			   BIT(9));
674 }
675 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
676 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
677 {
678 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
679 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
680 			   GENMASK(11, 10));
681 }
682 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
683 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
684 {
685 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
686 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
687 			   GENMASK(14, 12));
688 }
689 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
690 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
691 {
692 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
693 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
694 			   BIT(15));
695 }
696 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
697 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
698 {
699 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
700 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
701 			   GENMASK(19, 16));
702 }
703 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
704 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
705 {
706 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
707 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
708 			   BIT(20));
709 }
710 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
711 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
712 {
713 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
714 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
715 			   BIT(21));
716 }
717 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
718 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
719 {
720 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
721 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
722 			   BIT(22));
723 }
724 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
725 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
726 {
727 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
728 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
729 			   BIT(23));
730 }
731 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
732 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
733 {
734 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
735 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
736 			   BIT(25));
737 }
738 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
739 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
740 {
741 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
742 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
743 			   BIT(26));
744 }
745 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
746 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
747 {
748 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
749 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
750 			   BIT(27));
751 }
752 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
753 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
754 {
755 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
756 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
757 			   GENMASK(31, 28));
758 }
759 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
760 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
761 {
762 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
763 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
764 			   GENMASK(8, 0));
765 }
766 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
767 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
768 {
769 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
770 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
771 			   BIT(9));
772 }
773 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
774 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
775 {
776 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
777 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
778 			   BIT(10));
779 }
780 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
781 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
782 {
783 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
784 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
785 			   BIT(11));
786 }
787 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
788 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
789 {
790 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
791 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
792 			   GENMASK(15, 12));
793 }
794 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
795 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
796 {
797 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
798 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
799 			   GENMASK(24, 16));
800 }
801 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
802 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
803 {
804 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
805 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
806 			   BIT(27));
807 }
808 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
809 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
810 {
811 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
812 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
813 			   GENMASK(31, 28));
814 }
815 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
816 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
817 {
818 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
819 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
820 			   GENMASK(5, 0));
821 }
822 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
823 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
824 {
825 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
826 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
827 			   BIT(6));
828 }
829 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
830 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
831 {
832 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
833 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
834 			   BIT(7));
835 }
836 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
837 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
838 {
839 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
840 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
841 			   BIT(8));
842 }
843 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
844 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
845 {
846 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
847 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
848 			   BIT(9));
849 }
850 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
851 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
852 {
853 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
854 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
855 			   GENMASK(11, 10));
856 }
857 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
858 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
859 {
860 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
861 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
862 			   BIT(12));
863 }
864 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
865 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
866 {
867 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
868 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
869 			   GENMASK(14, 13));
870 }
871 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
872 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
873 {
874 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
875 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
876 			   GENMASK(26, 16));
877 }
878 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
879 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
880 {
881 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
882 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
883 			   BIT(27));
884 }
885 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
886 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
887 {
888 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
889 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
890 			   GENMASK(31, 28));
891 }
892 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
893 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
894 {
895 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
896 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
897 			   GENMASK(7, 0));
898 }
899 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
900 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
901 {
902 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
903 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
904 			   GENMASK(9, 8));
905 }
906 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
907 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
908 {
909 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
910 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
911 			   GENMASK(18, 16));
912 }
913 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
914 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
915 {
916 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
917 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
918 			   GENMASK(21, 19));
919 }
920 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
921 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
922 {
923 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
924 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
925 			   GENMASK(24, 22));
926 }
927 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
928 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
929 {
930 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
931 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
932 			   GENMASK(27, 25));
933 }
934 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
935 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
936 {
937 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
938 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
939 			   GENMASK(31, 28));
940 }
941 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
942 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
943 {
944 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
945 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
946 			   GENMASK(2, 0));
947 }
948 #define SET_CMC_TBL_MASK_BMC BIT(0)
949 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
950 {
951 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
952 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
953 			   BIT(3));
954 }
955 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
956 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
957 {
958 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
959 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
960 			   GENMASK(7, 4));
961 }
962 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
963 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
964 {
965 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
966 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
967 			   BIT(8));
968 }
969 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
970 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
971 {
972 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
973 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
974 			   GENMASK(11, 9));
975 }
976 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
977 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
978 {
979 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
980 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
981 			   BIT(12));
982 }
983 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
984 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
985 {
986 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
987 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
988 			   BIT(13));
989 }
990 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
991 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
992 {
993 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
994 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
995 			   BIT(14));
996 }
997 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
998 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
999 {
1000 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1001 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
1002 			   BIT(15));
1003 }
1004 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
1005 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
1006 {
1007 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
1008 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
1009 			   BIT(16));
1010 }
1011 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
1012 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
1013 {
1014 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
1015 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
1016 			   BIT(17));
1017 }
1018 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
1019 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
1020 {
1021 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
1022 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
1023 			   BIT(18));
1024 }
1025 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
1026 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
1027 {
1028 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
1029 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
1030 			   BIT(19));
1031 }
1032 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
1033 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
1034 {
1035 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
1036 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
1037 			   BIT(20));
1038 }
1039 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
1040 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
1041 {
1042 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
1043 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
1044 			   BIT(21));
1045 }
1046 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
1047 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
1048 {
1049 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
1050 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
1051 			   BIT(27));
1052 }
1053 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
1054 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
1055 {
1056 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
1057 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
1058 			   GENMASK(31, 28));
1059 }
1060 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
1061 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
1062 {
1063 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
1064 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
1065 			   GENMASK(8, 0));
1066 }
1067 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
1068 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
1069 {
1070 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
1071 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
1072 			   BIT(12));
1073 }
1074 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
1075 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
1076 {
1077 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
1078 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
1079 			   BIT(13));
1080 }
1081 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
1082 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1083 {
1084 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
1085 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1086 			   GENMASK(19, 16));
1087 }
1088 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
1089 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1090 {
1091 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
1092 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1093 			   GENMASK(21, 20));
1094 }
1095 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
1096 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1097 {
1098 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
1099 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1100 			   GENMASK(23, 22));
1101 }
1102 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
1103 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1104 {
1105 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1106 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1107 			   GENMASK(25, 24));
1108 }
1109 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
1110 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1111 {
1112 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
1113 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1114 			   GENMASK(27, 26));
1115 }
1116 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
1117 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1118 {
1119 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1120 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1121 			   BIT(28));
1122 }
1123 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
1124 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1125 {
1126 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1127 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1128 			   BIT(29));
1129 }
1130 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
1131 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1132 {
1133 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1134 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1135 			   BIT(30));
1136 }
1137 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
1138 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1139 {
1140 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1141 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1142 			   BIT(31));
1143 }
1144 
1145 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
1146 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1147 {
1148 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1149 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1150 			   GENMASK(1, 0));
1151 }
1152 
1153 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1154 {
1155 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1156 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1157 			   GENMASK(3, 2));
1158 }
1159 
1160 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1161 {
1162 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1163 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1164 			   GENMASK(5, 4));
1165 }
1166 
1167 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1168 {
1169 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1170 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1171 			   GENMASK(7, 6));
1172 }
1173 
1174 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
1175 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1176 {
1177 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1178 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1179 			   GENMASK(7, 0));
1180 }
1181 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
1182 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1183 {
1184 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1185 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1186 			   GENMASK(16, 8));
1187 }
1188 #define SET_CMC_TBL_MASK_ULDL BIT(0)
1189 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1190 {
1191 	le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1192 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1193 			   BIT(17));
1194 }
1195 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
1196 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1197 {
1198 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1199 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1200 			   GENMASK(19, 18));
1201 }
1202 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1203 {
1204 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1205 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1206 			   GENMASK(21, 20));
1207 }
1208 
1209 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1210 {
1211 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1212 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1213 			   GENMASK(23, 22));
1214 }
1215 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
1216 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1217 {
1218 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1219 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1220 			   GENMASK(27, 24));
1221 }
1222 
1223 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1224 {
1225 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1226 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1227 			   GENMASK(31, 30));
1228 }
1229 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
1230 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1231 {
1232 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1233 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1234 			   GENMASK(2, 0));
1235 }
1236 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
1237 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1238 {
1239 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1240 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1241 			   GENMASK(5, 3));
1242 }
1243 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
1244 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1245 {
1246 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1247 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1248 			   GENMASK(7, 6));
1249 }
1250 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
1251 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1252 {
1253 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1254 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1255 			   GENMASK(9, 8));
1256 }
1257 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
1258 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1259 {
1260 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1261 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1262 			   GENMASK(11, 10));
1263 }
1264 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
1265 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1266 {
1267 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1268 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1269 			   BIT(12));
1270 }
1271 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
1272 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1273 {
1274 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1275 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1276 			   BIT(13));
1277 }
1278 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
1279 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1280 {
1281 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1282 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1283 			   BIT(14));
1284 }
1285 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
1286 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1287 {
1288 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1289 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1290 			   BIT(15));
1291 }
1292 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
1293 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1294 {
1295 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1296 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1297 			   GENMASK(24, 16));
1298 }
1299 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
1300 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1301 {
1302 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1303 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1304 			   GENMASK(27, 25));
1305 }
1306 
1307 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1308 {
1309 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1310 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1311 			   GENMASK(29, 28));
1312 }
1313 
1314 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
1315 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1316 {
1317 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1318 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1319 			   GENMASK(31, 30));
1320 }
1321 
1322 struct rtw89_h2c_cctlinfo_ud_g7 {
1323 	__le32 c0;
1324 	__le32 w0;
1325 	__le32 w1;
1326 	__le32 w2;
1327 	__le32 w3;
1328 	__le32 w4;
1329 	__le32 w5;
1330 	__le32 w6;
1331 	__le32 w7;
1332 	__le32 w8;
1333 	__le32 w9;
1334 	__le32 w10;
1335 	__le32 w11;
1336 	__le32 w12;
1337 	__le32 w13;
1338 	__le32 w14;
1339 	__le32 w15;
1340 	__le32 m0;
1341 	__le32 m1;
1342 	__le32 m2;
1343 	__le32 m3;
1344 	__le32 m4;
1345 	__le32 m5;
1346 	__le32 m6;
1347 	__le32 m7;
1348 	__le32 m8;
1349 	__le32 m9;
1350 	__le32 m10;
1351 	__le32 m11;
1352 	__le32 m12;
1353 	__le32 m13;
1354 	__le32 m14;
1355 	__le32 m15;
1356 } __packed;
1357 
1358 #define CCTLINFO_G7_C0_MACID GENMASK(6, 0)
1359 #define CCTLINFO_G7_C0_OP BIT(7)
1360 
1361 #define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0)
1362 #define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)
1363 #define CCTLINFO_G7_W0_TRYRATE BIT(15)
1364 #define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)
1365 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1366 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1367 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1368 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1369 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1370 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1371 #define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1372 #define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1373 #define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1374 #define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)
1375 #define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1376 #define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1377 #define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1378 #define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)
1379 #define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1380 #define CCTLINFO_G7_W1_ALL GENMASK(31, 0)
1381 #define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1382 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1383 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1384 #define CCTLINFO_G7_W2_RTS_EN BIT(8)
1385 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1386 #define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10)
1387 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1388 #define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1389 #define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1390 #define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1391 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1392 #define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1393 #define CCTLINFO_G7_W2_ALL GENMASK(31, 0)
1394 #define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)
1395 #define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)
1396 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1397 #define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)
1398 #define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1399 #define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)
1400 #define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19)
1401 #define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)
1402 #define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25)
1403 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1404 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1405 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1406 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1407 #define CCTLINFO_G7_W3_ALL GENMASK(31, 0)
1408 #define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0)
1409 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1410 #define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)
1411 #define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1412 #define CCTLINFO_G7_W4_DATA_ER BIT(9)
1413 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1414 #define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1415 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1416 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1417 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1418 #define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1419 #define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1420 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0)
1421 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2)
1422 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4)
1423 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)
1424 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)
1425 #define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10)
1426 #define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)
1427 #define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)
1428 #define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
1429 #define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0)
1430 #define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)
1431 #define CCTLINFO_G7_W6_ULDL BIT(31)
1432 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1433 #define CCTLINFO_G7_W7_NC GENMASK(2, 0)
1434 #define CCTLINFO_G7_W7_NR GENMASK(5, 3)
1435 #define CCTLINFO_G7_W7_NG GENMASK(7, 6)
1436 #define CCTLINFO_G7_W7_CB GENMASK(9, 8)
1437 #define CCTLINFO_G7_W7_CS GENMASK(11, 10)
1438 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1439 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1440 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1441 #define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)
1442 #define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)
1443 #define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))
1444 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1445 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1446 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1447 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1448 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1449 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1450 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1451 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1452 #define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)
1453 #define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)
1454 #define CCTLINFO_G7_W8_ALL GENMASK(15, 0)
1455 /* W9~13 are reserved */
1456 #define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0)
1457 #define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)
1458 #define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)
1459 #define CCTLINFO_G7_W14_ALL GENMASK(31, 0)
1460 #define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0)
1461 #define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4)
1462 #define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)
1463 #define CCTLINFO_G7_W15_ALL GENMASK(27, 0)
1464 
1465 struct rtw89_h2c_bcn_upd {
1466 	__le32 w0;
1467 	__le32 w1;
1468 	__le32 w2;
1469 } __packed;
1470 
1471 #define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)
1472 #define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)
1473 #define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)
1474 #define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)
1475 #define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)
1476 #define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)
1477 #define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10)
1478 #define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)
1479 #define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21)
1480 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1481 #define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1)
1482 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5)
1483 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)
1484 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9)
1485 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)
1486 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1487 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1488 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1489 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1490 #define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)
1491 
1492 struct rtw89_h2c_bcn_upd_be {
1493 	__le32 w0;
1494 	__le32 w1;
1495 	__le32 w2;
1496 	__le32 w3;
1497 	__le32 w4;
1498 	__le32 w5;
1499 	__le32 w6;
1500 	__le32 w7;
1501 	__le32 w8;
1502 	__le32 w9;
1503 	__le32 w10;
1504 	__le32 w11;
1505 	__le32 w12;
1506 	__le32 w13;
1507 	__le32 w14;
1508 	__le32 w15;
1509 	__le32 w16;
1510 	__le32 w17;
1511 	__le32 w18;
1512 	__le32 w19;
1513 	__le32 w20;
1514 	__le32 w21;
1515 	__le32 w22;
1516 	__le32 w23;
1517 	__le32 w24;
1518 	__le32 w25;
1519 	__le32 w26;
1520 	__le32 w27;
1521 	__le32 w28;
1522 	__le32 w29;
1523 } __packed;
1524 
1525 #define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)
1526 #define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)
1527 #define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)
1528 #define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)
1529 #define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)
1530 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)
1531 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10)
1532 #define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)
1533 #define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21)
1534 #define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)
1535 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1536 #define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1)
1537 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5)
1538 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)
1539 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9)
1540 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)
1541 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1542 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1543 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1544 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1545 #define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)
1546 #define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0)
1547 #define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)
1548 #define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0)
1549 #define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)
1550 #define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0)
1551 #define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)
1552 #define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0)
1553 #define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)
1554 #define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0)
1555 #define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)
1556 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1557 
1558 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val)
1559 {
1560 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1561 }
1562 
1563 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val)
1564 {
1565 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8));
1566 }
1567 
1568 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val)
1569 {
1570 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10));
1571 }
1572 
1573 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val)
1574 {
1575 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13));
1576 }
1577 
1578 enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */
1579 	RTW89_FW_N_AC_STA = 0,
1580 	RTW89_FW_AX_STA = 1,
1581 	RTW89_FW_BE_STA = 2,
1582 };
1583 
1584 struct rtw89_h2c_join {
1585 	__le32 w0;
1586 } __packed;
1587 
1588 struct rtw89_h2c_join_v1 {
1589 	__le32 w0;
1590 	__le32 w1;
1591 	__le32 w2;
1592 } __packed;
1593 
1594 #define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)
1595 #define RTW89_H2C_JOININFO_W0_OP BIT(8)
1596 #define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1597 #define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10)
1598 #define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1599 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1600 #define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14)
1601 #define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)
1602 #define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18)
1603 #define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21)
1604 #define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)
1605 #define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26)
1606 #define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)
1607 #define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0)
1608 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1609 #define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4)
1610 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1611 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1612 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1613 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1614 #define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)
1615 #define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19)
1616 #define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)
1617 #define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)
1618 
1619 struct rtw89_h2c_notify_dbcc {
1620 	__le32 w0;
1621 } __packed;
1622 
1623 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1624 
1625 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1626 {
1627 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1628 }
1629 
1630 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1631 {
1632 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1633 }
1634 
1635 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1636 {
1637 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1638 }
1639 
1640 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1641 {
1642 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1643 }
1644 
1645 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1646 {
1647 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1648 }
1649 
1650 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1651 {
1652 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1653 }
1654 
1655 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1656 {
1657 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1658 }
1659 
1660 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1661 {
1662 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1663 }
1664 
1665 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1666 {
1667 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1668 }
1669 
1670 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1671 {
1672 	le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1673 }
1674 
1675 struct rtw89_h2c_ba_cam {
1676 	__le32 w0;
1677 	__le32 w1;
1678 } __packed;
1679 
1680 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1681 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1682 #define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2)
1683 #define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)
1684 #define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)
1685 #define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)
1686 #define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)
1687 #define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)
1688 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1689 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1690 #define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)
1691 
1692 struct rtw89_h2c_ba_cam_v1 {
1693 	__le32 w0;
1694 	__le32 w1;
1695 } __packed;
1696 
1697 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1698 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1699 #define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)
1700 #define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)
1701 #define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)
1702 #define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)
1703 #define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)
1704 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1705 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1706 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1707 #define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)
1708 
1709 struct rtw89_h2c_ba_cam_init {
1710 	__le32 w0;
1711 } __packed;
1712 
1713 #define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)
1714 #define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)
1715 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1716 
1717 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1718 {
1719 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1720 }
1721 
1722 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1723 {
1724 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1725 }
1726 
1727 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1728 {
1729 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1730 }
1731 
1732 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1733 {
1734 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1735 }
1736 
1737 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1738 {
1739 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1740 }
1741 
1742 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1743 {
1744 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1745 }
1746 
1747 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1748 {
1749 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1750 }
1751 
1752 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1753 {
1754 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1755 }
1756 
1757 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1758 {
1759 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1760 }
1761 
1762 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1763 {
1764 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1765 }
1766 
1767 struct rtw89_h2c_lps_ch_info {
1768 	struct {
1769 		u8 pri_ch;
1770 		u8 central_ch;
1771 		u8 bw;
1772 		u8 band;
1773 	} __packed info[2];
1774 
1775 	__le32 mlo_dbcc_mode_lps;
1776 } __packed;
1777 
1778 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val)
1779 {
1780 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0));
1781 }
1782 
1783 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1784 {
1785 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1786 }
1787 
1788 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1789 {
1790 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1791 }
1792 
1793 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1794 {
1795 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1796 }
1797 
1798 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1799 {
1800 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1801 }
1802 
1803 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1804 {
1805 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1806 }
1807 
1808 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1809 {
1810 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1811 }
1812 
1813 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
1814 {
1815 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
1816 }
1817 
1818 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
1819 {
1820 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
1821 }
1822 
1823 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
1824 {
1825 	le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
1826 }
1827 
1828 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
1829 {
1830 	le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
1831 }
1832 
1833 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
1834 {
1835 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
1836 }
1837 
1838 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
1839 {
1840 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1841 }
1842 
1843 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
1844 {
1845 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1846 }
1847 
1848 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
1849 {
1850 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1851 }
1852 
1853 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
1854 {
1855 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1856 }
1857 
1858 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
1859 {
1860 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1861 }
1862 
1863 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
1864 {
1865 	le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1866 }
1867 
1868 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
1869 {
1870 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1871 }
1872 
1873 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
1874 {
1875 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1876 }
1877 
1878 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
1879 {
1880 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1881 }
1882 
1883 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
1884 {
1885 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1886 }
1887 
1888 struct rtw89_h2c_wow_global {
1889 	__le32 w0;
1890 	struct rtw89_wow_key_info key_info;
1891 } __packed;
1892 
1893 #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
1894 #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
1895 #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
1896 #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
1897 #define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8)
1898 #define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16)
1899 #define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)
1900 
1901 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
1902 {
1903 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1904 }
1905 
1906 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
1907 {
1908 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1909 }
1910 
1911 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
1912 {
1913 	le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1914 }
1915 
1916 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
1917 {
1918 	le32p_replace_bits((__le32 *)h2c, val, BIT(3));
1919 }
1920 
1921 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
1922 {
1923 	le32p_replace_bits((__le32 *)h2c, val, BIT(4));
1924 }
1925 
1926 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
1927 {
1928 	le32p_replace_bits((__le32 *)h2c, val, BIT(5));
1929 }
1930 
1931 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
1932 {
1933 	le32p_replace_bits((__le32 *)h2c, val, BIT(6));
1934 }
1935 
1936 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
1937 {
1938 	le32p_replace_bits((__le32 *)h2c, val, BIT(7));
1939 }
1940 
1941 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
1942 {
1943 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1944 }
1945 
1946 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
1947 {
1948 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1949 }
1950 
1951 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
1952 {
1953 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
1954 }
1955 
1956 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
1957 {
1958 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
1959 }
1960 
1961 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
1962 {
1963 	le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
1964 }
1965 
1966 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
1967 {
1968 	le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
1969 }
1970 
1971 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
1972 {
1973 	le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
1974 }
1975 
1976 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
1977 {
1978 	le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
1979 }
1980 
1981 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
1982 {
1983 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
1984 }
1985 
1986 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
1987 {
1988 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
1989 }
1990 
1991 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
1992 {
1993 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
1994 }
1995 
1996 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
1997 {
1998 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
1999 }
2000 
2001 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2002 {
2003 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2004 }
2005 
2006 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2007 {
2008 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2009 }
2010 
2011 struct rtw89_h2c_wow_gtk_ofld {
2012 	__le32 w0;
2013 	__le32 w1;
2014 	struct rtw89_wow_gtk_info gtk_info;
2015 } __packed;
2016 
2017 #define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2018 #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2019 #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2020 #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2021 #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2022 #define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID GENMASK(23, 16)
2023 #define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24)
2024 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID GENMASK(7, 0)
2025 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO GENMASK(9, 8)
2026 #define RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT GENMASK(17, 10)
2027 
2028 struct rtw89_h2c_arp_offload {
2029 	__le32 w0;
2030 	__le32 w1;
2031 } __packed;
2032 
2033 #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2034 #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2035 #define RTW89_H2C_ARP_OFFLOAD_W0_MACID GENMASK(23, 16)
2036 #define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24)
2037 #define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT GENMASK(31, 0)
2038 
2039 enum rtw89_btc_btf_h2c_class {
2040 	BTFC_SET = 0x10,
2041 	BTFC_GET = 0x11,
2042 	BTFC_FW_EVENT = 0x12,
2043 };
2044 
2045 enum rtw89_btc_btf_set {
2046 	SET_REPORT_EN = 0x0,
2047 	SET_SLOT_TABLE,
2048 	SET_MREG_TABLE,
2049 	SET_CX_POLICY,
2050 	SET_GPIO_DBG,
2051 	SET_DRV_INFO,
2052 	SET_DRV_EVENT,
2053 	SET_BT_WREG_ADDR,
2054 	SET_BT_WREG_VAL,
2055 	SET_BT_RREG_ADDR,
2056 	SET_BT_WL_CH_INFO,
2057 	SET_BT_INFO_REPORT,
2058 	SET_BT_IGNORE_WLAN_ACT,
2059 	SET_BT_TX_PWR,
2060 	SET_BT_LNA_CONSTRAIN,
2061 	SET_BT_QUERY_DEV_LIST,
2062 	SET_BT_QUERY_DEV_INFO,
2063 	SET_BT_PSD_REPORT,
2064 	SET_H2C_TEST,
2065 	SET_IOFLD_RF,
2066 	SET_IOFLD_BB,
2067 	SET_IOFLD_MAC,
2068 	SET_IOFLD_SCBD,
2069 	SET_H2C_MACRO,
2070 	SET_MAX1,
2071 };
2072 
2073 enum rtw89_btc_cxdrvinfo {
2074 	CXDRVINFO_INIT = 0,
2075 	CXDRVINFO_ROLE,
2076 	CXDRVINFO_DBCC,
2077 	CXDRVINFO_SMAP,
2078 	CXDRVINFO_RFK,
2079 	CXDRVINFO_RUN,
2080 	CXDRVINFO_CTRL,
2081 	CXDRVINFO_SCAN,
2082 	CXDRVINFO_TRX,  /* WL traffic to WL fw */
2083 	CXDRVINFO_TXPWR,
2084 	CXDRVINFO_FDDT,
2085 	CXDRVINFO_MLO,
2086 	CXDRVINFO_OSI,
2087 	CXDRVINFO_MAX,
2088 };
2089 
2090 enum rtw89_scan_mode {
2091 	RTW89_SCAN_IMMEDIATE,
2092 };
2093 
2094 enum rtw89_scan_type {
2095 	RTW89_SCAN_ONCE,
2096 };
2097 
2098 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2099 {
2100 	u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2101 }
2102 
2103 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2104 {
2105 	u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2106 }
2107 
2108 struct rtw89_h2c_cxhdr {
2109 	u8 type;
2110 	u8 len;
2111 } __packed;
2112 
2113 struct rtw89_h2c_cxhdr_v7 {
2114 	u8 type;
2115 	u8 ver;
2116 	u8 len;
2117 } __packed;
2118 
2119 struct rtw89_h2c_cxctrl_v7 {
2120 	struct rtw89_h2c_cxhdr_v7 hdr;
2121 	struct rtw89_btc_ctrl_v7 ctrl;
2122 } __packed;
2123 
2124 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2125 #define H2C_LEN_CXDRVHDR_V7 sizeof(struct rtw89_h2c_cxhdr_v7)
2126 
2127 struct rtw89_btc_wl_role_info_v8_u8 {
2128 	u8 connect_cnt;
2129 	u8 link_mode;
2130 	u8 link_mode_chg;
2131 	u8 p2p_2g;
2132 
2133 	u8 pta_req_band;
2134 	u8 dbcc_en;
2135 	u8 dbcc_chg;
2136 	u8 dbcc_2g_phy;
2137 
2138 	struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
2139 } __packed;
2140 
2141 struct rtw89_btc_wl_role_info_v8_u32 {
2142 	__le32 role_map;
2143 	__le32 mrole_type;
2144 	__le32 mrole_noa_duration;
2145 } __packed;
2146 
2147 struct rtw89_h2c_cxrole_v8 {
2148 	struct rtw89_h2c_cxhdr hdr;
2149 	struct rtw89_btc_wl_role_info_v8_u8 _u8;
2150 	struct rtw89_btc_wl_role_info_v8_u32 _u32;
2151 } __packed;
2152 
2153 struct rtw89_h2c_cxinit {
2154 	struct rtw89_h2c_cxhdr hdr;
2155 	u8 ant_type;
2156 	u8 ant_num;
2157 	u8 ant_iso;
2158 	u8 ant_info;
2159 	u8 mod_rfe;
2160 	u8 mod_cv;
2161 	u8 mod_info;
2162 	u8 mod_adie_kt;
2163 	u8 wl_gch;
2164 	u8 info;
2165 	u8 rsvd;
2166 	u8 rsvd1;
2167 } __packed;
2168 
2169 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2170 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2171 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2172 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2173 
2174 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2175 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2176 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2177 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2178 
2179 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2180 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2181 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2182 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2183 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2184 
2185 struct rtw89_h2c_cxinit_v7 {
2186 	struct rtw89_h2c_cxhdr_v7 hdr;
2187 	struct rtw89_btc_init_info_v7 init;
2188 } __packed;
2189 
2190 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2191 {
2192 	u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2193 }
2194 
2195 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2196 {
2197 	u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2198 }
2199 
2200 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2201 {
2202 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2203 }
2204 
2205 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2206 {
2207 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2208 }
2209 
2210 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2211 {
2212 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2213 }
2214 
2215 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2216 {
2217 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2218 }
2219 
2220 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2221 {
2222 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2223 }
2224 
2225 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2226 {
2227 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2228 }
2229 
2230 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2231 {
2232 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2233 }
2234 
2235 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2236 {
2237 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2238 }
2239 
2240 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2241 {
2242 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2243 }
2244 
2245 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2246 {
2247 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2248 }
2249 
2250 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2251 {
2252 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2253 }
2254 
2255 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2256 {
2257 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2258 }
2259 
2260 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2261 {
2262 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2263 }
2264 
2265 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2266 {
2267 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2268 }
2269 
2270 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2271 {
2272 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2273 }
2274 
2275 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2276 {
2277 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2278 }
2279 
2280 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2281 {
2282 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2283 }
2284 
2285 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2286 {
2287 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2288 }
2289 
2290 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2291 {
2292 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2293 }
2294 
2295 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2296 {
2297 	u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2298 }
2299 
2300 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2301 {
2302 	u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2303 }
2304 
2305 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2306 {
2307 	le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2308 }
2309 
2310 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2311 {
2312 	le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2313 }
2314 
2315 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2316 {
2317 	le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2318 }
2319 
2320 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2321 {
2322 	le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2323 }
2324 
2325 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2326 {
2327 	le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2328 }
2329 
2330 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2331 {
2332 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2333 }
2334 
2335 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2336 {
2337 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2338 }
2339 
2340 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2341 {
2342 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2343 }
2344 
2345 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2346 {
2347 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2348 }
2349 
2350 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2351 {
2352 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2353 }
2354 
2355 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2356 {
2357 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2358 }
2359 
2360 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2361 {
2362 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2363 }
2364 
2365 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2366 {
2367 	u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2368 }
2369 
2370 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2371 {
2372 	u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2373 }
2374 
2375 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2376 {
2377 	le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2378 }
2379 
2380 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2381 {
2382 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2383 }
2384 
2385 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2386 {
2387 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2388 }
2389 
2390 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2391 {
2392 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2393 }
2394 
2395 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2396 {
2397 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2398 }
2399 
2400 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2401 {
2402 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2403 }
2404 
2405 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2406 {
2407 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2408 }
2409 
2410 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2411 {
2412 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2413 }
2414 
2415 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2416 {
2417 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2418 }
2419 
2420 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2421 {
2422 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2423 }
2424 
2425 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2426 {
2427 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2428 }
2429 
2430 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2431 {
2432 	u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2433 }
2434 
2435 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2436 {
2437 	u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2438 }
2439 
2440 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2441 {
2442 	u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2443 }
2444 
2445 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2446 {
2447 	u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2448 }
2449 
2450 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2451 {
2452 	u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2453 }
2454 
2455 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2456 {
2457 	u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2458 }
2459 
2460 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2461 {
2462 	u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2463 }
2464 
2465 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2466 {
2467 	u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2468 }
2469 
2470 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2471 {
2472 	u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2473 }
2474 
2475 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2476 {
2477 	u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2478 }
2479 
2480 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2481 {
2482 	u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2483 }
2484 
2485 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2486 {
2487 	u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2488 }
2489 
2490 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2491 {
2492 	le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2493 }
2494 
2495 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2496 {
2497 	le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2498 }
2499 
2500 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2501 {
2502 	le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2503 }
2504 
2505 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2506 {
2507 	le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2508 }
2509 
2510 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2511 {
2512 	le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2513 }
2514 
2515 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2516 {
2517 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2518 }
2519 
2520 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2521 {
2522 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2523 }
2524 
2525 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2526 {
2527 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2528 }
2529 
2530 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2531 {
2532 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2533 }
2534 
2535 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2536 {
2537 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2538 }
2539 
2540 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2541 {
2542 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2543 }
2544 
2545 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2546 {
2547 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2548 }
2549 
2550 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2551 {
2552 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2553 }
2554 
2555 struct rtw89_h2c_chinfo_elem {
2556 	__le32 w0;
2557 	__le32 w1;
2558 	__le32 w2;
2559 	__le32 w3;
2560 	__le32 w4;
2561 	__le32 w5;
2562 	__le32 w6;
2563 } __packed;
2564 
2565 #define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0)
2566 #define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8)
2567 #define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16)
2568 #define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)
2569 #define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0)
2570 #define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3)
2571 #define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8)
2572 #define RTW89_H2C_CHINFO_W1_TX BIT(12)
2573 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2574 #define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14)
2575 #define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16)
2576 #define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2577 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2578 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2579 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2580 #define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0)
2581 #define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8)
2582 #define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16)
2583 #define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)
2584 #define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0)
2585 #define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8)
2586 #define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16)
2587 #define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)
2588 #define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0)
2589 
2590 struct rtw89_h2c_chinfo_elem_be {
2591 	__le32 w0;
2592 	__le32 w1;
2593 	__le32 w2;
2594 	__le32 w3;
2595 	__le32 w4;
2596 	__le32 w5;
2597 	__le32 w6;
2598 } __packed;
2599 
2600 #define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0)
2601 #define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8)
2602 #define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16)
2603 #define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)
2604 #define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0)
2605 #define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3)
2606 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2607 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2608 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2609 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2610 #define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9)
2611 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2612 #define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15)
2613 #define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)
2614 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0)
2615 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8)
2616 #define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)
2617 #define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0)
2618 #define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8)
2619 #define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16)
2620 #define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)
2621 #define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0)
2622 #define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8)
2623 #define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16)
2624 #define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)
2625 #define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0)
2626 #define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)
2627 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0)
2628 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)
2629 
2630 struct rtw89_h2c_chinfo {
2631 	u8 ch_num;
2632 	u8 elem_size;
2633 	u8 arg;
2634 	u8 rsvd0;
2635 	struct rtw89_h2c_chinfo_elem elem[] __counted_by(ch_num);
2636 } __packed;
2637 
2638 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2639 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2640 
2641 struct rtw89_h2c_scanofld {
2642 	__le32 w0;
2643 	__le32 w1;
2644 	__le32 w2;
2645 	__le32 tsf_high;
2646 	__le32 tsf_low;
2647 	__le32 w5;
2648 	__le32 w6;
2649 } __packed;
2650 
2651 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2652 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2653 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2654 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2655 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
2656 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
2657 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2658 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2659 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2660 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
2661 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2662 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2663 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2664 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2665 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
2666 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2667 
2668 struct rtw89_h2c_scanofld_be_macc_role {
2669 	__le32 w0;
2670 } __packed;
2671 
2672 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0)
2673 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2)
2674 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)
2675 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)
2676 
2677 struct rtw89_h2c_scanofld_be_opch {
2678 	__le32 w0;
2679 	__le32 w1;
2680 	__le32 w2;
2681 	__le32 w3;
2682 } __packed;
2683 
2684 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0)
2685 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16)
2686 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18)
2687 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21)
2688 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
2689 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)
2690 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0)
2691 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8)
2692 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10)
2693 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13)
2694 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16)
2695 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)
2696 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0)
2697 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8)
2698 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16)
2699 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0)
2700 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8)
2701 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16)
2702 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)
2703 
2704 struct rtw89_h2c_scanofld_be {
2705 	__le32 w0;
2706 	__le32 w1;
2707 	__le32 w2;
2708 	__le32 w3;
2709 	__le32 w4;
2710 	__le32 w5;
2711 	__le32 w6;
2712 	__le32 w7;
2713 	__le32 w8;
2714 	struct rtw89_h2c_scanofld_be_macc_role role[];
2715 } __packed;
2716 
2717 #define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0)
2718 #define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2)
2719 #define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4)
2720 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
2721 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2722 #define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8)
2723 #define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24)
2724 #define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27)
2725 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0)
2726 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8)
2727 #define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)
2728 #define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0)
2729 #define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16)
2730 #define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)
2731 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0)
2732 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8)
2733 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16)
2734 #define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)
2735 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0)
2736 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8)
2737 #define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)
2738 #define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0)
2739 #define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0)
2740 #define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0)
2741 
2742 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2743 {
2744 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2745 }
2746 
2747 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2748 {
2749 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2750 }
2751 
2752 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2753 {
2754 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2755 }
2756 
2757 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2758 {
2759 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2760 }
2761 
2762 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2763 {
2764 	le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2765 }
2766 
2767 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2768 {
2769 	le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2770 }
2771 
2772 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2773 {
2774 	*((__le32 *)cmd + 1) = val;
2775 }
2776 
2777 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2778 {
2779 	*((__le32 *)cmd + 2) = val;
2780 }
2781 
2782 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2783 {
2784 	*((__le32 *)cmd + 3) = val;
2785 }
2786 
2787 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2788 {
2789 	le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2790 }
2791 
2792 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2793 {
2794 	u8 ctwnd;
2795 
2796 	if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2797 		return;
2798 	ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2799 	le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2800 }
2801 
2802 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2803 {
2804 	le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2805 }
2806 
2807 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2808 {
2809 	le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2810 }
2811 
2812 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2813 {
2814 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2815 }
2816 
2817 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
2818 {
2819 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
2820 }
2821 
2822 enum rtw89_fw_mcc_c2h_rpt_cfg {
2823 	RTW89_FW_MCC_C2H_RPT_OFF	= 0,
2824 	RTW89_FW_MCC_C2H_RPT_FAIL_ONLY	= 1,
2825 	RTW89_FW_MCC_C2H_RPT_ALL	= 2,
2826 };
2827 
2828 struct rtw89_fw_mcc_add_req {
2829 	u8 macid;
2830 	u8 central_ch_seg0;
2831 	u8 central_ch_seg1;
2832 	u8 primary_ch;
2833 	enum rtw89_bandwidth bandwidth: 4;
2834 	u32 group: 2;
2835 	u32 c2h_rpt: 2;
2836 	u32 dis_tx_null: 1;
2837 	u32 dis_sw_retry: 1;
2838 	u32 in_curr_ch: 1;
2839 	u32 sw_retry_count: 3;
2840 	u32 tx_null_early: 4;
2841 	u32 btc_in_2g: 1;
2842 	u32 pta_en: 1;
2843 	u32 rfk_by_pass: 1;
2844 	u32 ch_band_type: 2;
2845 	u32 rsvd0: 9;
2846 	u32 duration;
2847 	u8 courtesy_en;
2848 	u8 courtesy_num;
2849 	u8 courtesy_target;
2850 	u8 rsvd1;
2851 };
2852 
2853 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
2854 {
2855 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2856 }
2857 
2858 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
2859 {
2860 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
2861 }
2862 
2863 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
2864 {
2865 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
2866 }
2867 
2868 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
2869 {
2870 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2871 }
2872 
2873 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
2874 {
2875 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
2876 }
2877 
2878 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
2879 {
2880 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
2881 }
2882 
2883 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
2884 {
2885 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
2886 }
2887 
2888 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
2889 {
2890 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
2891 }
2892 
2893 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
2894 {
2895 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
2896 }
2897 
2898 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
2899 {
2900 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
2901 }
2902 
2903 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
2904 {
2905 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
2906 }
2907 
2908 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
2909 {
2910 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
2911 }
2912 
2913 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
2914 {
2915 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
2916 }
2917 
2918 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
2919 {
2920 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
2921 }
2922 
2923 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
2924 {
2925 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
2926 }
2927 
2928 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
2929 {
2930 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
2931 }
2932 
2933 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
2934 {
2935 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
2936 }
2937 
2938 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
2939 {
2940 	le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
2941 }
2942 
2943 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
2944 {
2945 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
2946 }
2947 
2948 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
2949 {
2950 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
2951 }
2952 
2953 enum rtw89_fw_mcc_old_group_actions {
2954 	RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0,
2955 	RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1,
2956 };
2957 
2958 struct rtw89_fw_mcc_start_req {
2959 	u32 group: 2;
2960 	u32 btc_in_group: 1;
2961 	u32 old_group_action: 2;
2962 	u32 old_group: 2;
2963 	u32 rsvd0: 9;
2964 	u32 notify_cnt: 3;
2965 	u32 rsvd1: 2;
2966 	u32 notify_rxdbg_en: 1;
2967 	u32 rsvd2: 2;
2968 	u32 macid: 8;
2969 	u32 tsf_low;
2970 	u32 tsf_high;
2971 };
2972 
2973 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
2974 {
2975 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
2976 }
2977 
2978 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
2979 {
2980 	le32p_replace_bits((__le32 *)cmd, val, BIT(2));
2981 }
2982 
2983 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
2984 {
2985 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
2986 }
2987 
2988 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
2989 {
2990 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
2991 }
2992 
2993 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
2994 {
2995 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
2996 }
2997 
2998 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
2999 {
3000 	le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3001 }
3002 
3003 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3004 {
3005 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3006 }
3007 
3008 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3009 {
3010 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3011 }
3012 
3013 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3014 {
3015 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3016 }
3017 
3018 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3019 {
3020 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3021 }
3022 
3023 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3024 {
3025 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3026 }
3027 
3028 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3029 {
3030 	le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3031 }
3032 
3033 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3034 {
3035 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3036 }
3037 
3038 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3039 {
3040 	le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3041 }
3042 
3043 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3044 {
3045 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3046 }
3047 
3048 struct rtw89_fw_mcc_tsf_req {
3049 	u8 group: 2;
3050 	u8 rsvd0: 6;
3051 	u8 macid_x;
3052 	u8 macid_y;
3053 	u8 rsvd1;
3054 };
3055 
3056 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3057 {
3058 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3059 }
3060 
3061 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3062 {
3063 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3064 }
3065 
3066 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3067 {
3068 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3069 }
3070 
3071 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3072 {
3073 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3074 }
3075 
3076 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3077 {
3078 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3079 }
3080 
3081 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3082 {
3083 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3084 }
3085 
3086 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3087 							   u8 *bitmap, u8 len)
3088 {
3089 	memcpy((__le32 *)cmd + 1, bitmap, len);
3090 }
3091 
3092 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3093 {
3094 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3095 }
3096 
3097 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3098 {
3099 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3100 }
3101 
3102 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3103 {
3104 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3105 }
3106 
3107 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3108 {
3109 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3110 }
3111 
3112 struct rtw89_fw_mcc_duration {
3113 	u32 group: 2;
3114 	u32 btc_in_group: 1;
3115 	u32 rsvd0: 5;
3116 	u32 start_macid: 8;
3117 	u32 macid_x: 8;
3118 	u32 macid_y: 8;
3119 	u32 start_tsf_low;
3120 	u32 start_tsf_high;
3121 	u32 duration_x;
3122 	u32 duration_y;
3123 };
3124 
3125 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3126 {
3127 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3128 }
3129 
3130 static
3131 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3132 {
3133 	le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3134 }
3135 
3136 static
3137 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3138 {
3139 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3140 }
3141 
3142 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3143 {
3144 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3145 }
3146 
3147 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3148 {
3149 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3150 }
3151 
3152 static
3153 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3154 {
3155 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3156 }
3157 
3158 static
3159 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3160 {
3161 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3162 }
3163 
3164 static
3165 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3166 {
3167 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3168 }
3169 
3170 static
3171 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3172 {
3173 	le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3174 }
3175 
3176 enum rtw89_h2c_mrc_sch_types {
3177 	RTW89_H2C_MRC_SCH_BAND0_ONLY = 0,
3178 	RTW89_H2C_MRC_SCH_BAND1_ONLY = 1,
3179 	RTW89_H2C_MRC_SCH_DUAL_BAND = 2,
3180 };
3181 
3182 enum rtw89_h2c_mrc_role_types {
3183 	RTW89_H2C_MRC_ROLE_WIFI = 0,
3184 	RTW89_H2C_MRC_ROLE_BT = 1,
3185 	RTW89_H2C_MRC_ROLE_EMPTY = 2,
3186 };
3187 
3188 #define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM 3
3189 #define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT 1 /* before MLO */
3190 
3191 struct rtw89_fw_mrc_add_slot_arg {
3192 	u16 duration; /* unit: TU */
3193 	bool courtesy_en;
3194 	u8 courtesy_period;
3195 	u8 courtesy_target; /* slot idx */
3196 
3197 	unsigned int role_num;
3198 	struct {
3199 		enum rtw89_h2c_mrc_role_types role_type;
3200 		bool is_master;
3201 		bool en_tx_null;
3202 		enum rtw89_band band;
3203 		enum rtw89_bandwidth bw;
3204 		u8 macid;
3205 		u8 central_ch;
3206 		u8 primary_ch;
3207 		u8 null_early; /* unit: TU */
3208 
3209 		/* if MLD, for macid: [0, chip::support_mld_num)
3210 		 * otherwise, for macid: [0, 32)
3211 		 */
3212 		u32 macid_main_bitmap;
3213 		/* for MLD, bit X maps to macid: X + chip::support_mld_num */
3214 		u32 macid_paired_bitmap;
3215 	} roles[RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT];
3216 };
3217 
3218 struct rtw89_fw_mrc_add_arg {
3219 	u8 sch_idx;
3220 	enum rtw89_h2c_mrc_sch_types sch_type;
3221 	bool btc_in_sch;
3222 
3223 	unsigned int slot_num;
3224 	struct rtw89_fw_mrc_add_slot_arg slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3225 };
3226 
3227 struct rtw89_h2c_mrc_add_role {
3228 	__le32 w0;
3229 	__le32 w1;
3230 	__le32 w2;
3231 	__le32 macid_main_bitmap;
3232 	__le32 macid_paired_bitmap;
3233 } __packed;
3234 
3235 #define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0)
3236 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16)
3237 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3238 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3239 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3240 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3241 #define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0)
3242 #define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8)
3243 #define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16)
3244 #define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20)
3245 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3246 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3247 #define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)
3248 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0)
3249 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8)
3250 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16)
3251 
3252 struct rtw89_h2c_mrc_add_slot {
3253 	__le32 w0;
3254 	__le32 w1;
3255 	struct rtw89_h2c_mrc_add_role roles[];
3256 } __packed;
3257 
3258 #define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0)
3259 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3260 #define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)
3261 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0)
3262 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8)
3263 
3264 struct rtw89_h2c_mrc_add {
3265 	__le32 w0;
3266 	/* Logically append flexible struct rtw89_h2c_mrc_add_slot, but there
3267 	 * are other flexible array inside it. We cannot access them correctly
3268 	 * through this struct. So, in case misusing, we don't really declare
3269 	 * it here.
3270 	 */
3271 } __packed;
3272 
3273 #define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0)
3274 #define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4)
3275 #define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8)
3276 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3277 
3278 enum rtw89_h2c_mrc_start_actions {
3279 	RTW89_H2C_MRC_START_ACTION_START_NEW = 0,
3280 	RTW89_H2C_MRC_START_ACTION_REPLACE_OLD = 1,
3281 };
3282 
3283 struct rtw89_fw_mrc_start_arg {
3284 	u8 sch_idx;
3285 	u8 old_sch_idx;
3286 	u64 start_tsf;
3287 	enum rtw89_h2c_mrc_start_actions action;
3288 };
3289 
3290 struct rtw89_h2c_mrc_start {
3291 	__le32 w0;
3292 	__le32 start_tsf_low;
3293 	__le32 start_tsf_high;
3294 } __packed;
3295 
3296 #define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0)
3297 #define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4)
3298 #define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8)
3299 
3300 struct rtw89_h2c_mrc_del {
3301 	__le32 w0;
3302 } __packed;
3303 
3304 #define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0)
3305 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3306 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3307 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3308 #define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8)
3309 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)
3310 
3311 #define RTW89_MAC_MRC_MAX_REQ_TSF_NUM 2
3312 
3313 struct rtw89_fw_mrc_req_tsf_arg {
3314 	unsigned int num;
3315 	struct {
3316 		u8 band;
3317 		u8 port;
3318 	} infos[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3319 };
3320 
3321 struct rtw89_h2c_mrc_req_tsf {
3322 	u8 req_tsf_num;
3323 	u8 infos[] __counted_by(req_tsf_num);
3324 } __packed;
3325 
3326 #define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0)
3327 #define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4)
3328 
3329 enum rtw89_h2c_mrc_upd_bitmap_actions {
3330 	RTW89_H2C_MRC_UPD_BITMAP_ACTION_DEL = 0,
3331 	RTW89_H2C_MRC_UPD_BITMAP_ACTION_ADD = 1,
3332 };
3333 
3334 struct rtw89_fw_mrc_upd_bitmap_arg {
3335 	u8 sch_idx;
3336 	u8 macid;
3337 	u8 client_macid;
3338 	enum rtw89_h2c_mrc_upd_bitmap_actions action;
3339 };
3340 
3341 struct rtw89_h2c_mrc_upd_bitmap {
3342 	__le32 w0;
3343 	__le32 w1;
3344 } __packed;
3345 
3346 #define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0)
3347 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3348 #define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)
3349 #define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0)
3350 
3351 struct rtw89_fw_mrc_sync_arg {
3352 	u8 offset; /* unit: TU */
3353 	struct {
3354 		u8 band;
3355 		u8 port;
3356 	} src, dest;
3357 };
3358 
3359 struct rtw89_h2c_mrc_sync {
3360 	__le32 w0;
3361 	__le32 w1;
3362 } __packed;
3363 
3364 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3365 #define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8)
3366 #define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12)
3367 #define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16)
3368 #define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20)
3369 #define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0)
3370 
3371 struct rtw89_fw_mrc_upd_duration_arg {
3372 	u8 sch_idx;
3373 	u64 start_tsf;
3374 
3375 	unsigned int slot_num;
3376 	struct {
3377 		u8 slot_idx;
3378 		u16 duration; /* unit: TU */
3379 	} slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3380 };
3381 
3382 struct rtw89_h2c_mrc_upd_duration {
3383 	__le32 w0;
3384 	__le32 start_tsf_low;
3385 	__le32 start_tsf_high;
3386 	__le32 slots[];
3387 } __packed;
3388 
3389 #define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0)
3390 #define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8)
3391 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3392 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0)
3393 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)
3394 
3395 struct rtw89_h2c_wow_aoac {
3396 	__le32 w0;
3397 } __packed;
3398 
3399 #define RTW89_C2H_HEADER_LEN 8
3400 
3401 struct rtw89_c2h_hdr {
3402 	__le32 w0;
3403 	__le32 w1;
3404 } __packed;
3405 
3406 #define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)
3407 #define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3408 #define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3409 #define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)
3410 
3411 struct rtw89_fw_c2h_attr {
3412 	u8 category;
3413 	u8 class;
3414 	u8 func;
3415 	u16 len;
3416 };
3417 
3418 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3419 {
3420 	static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3421 
3422 	return (struct rtw89_fw_c2h_attr *)skb->cb;
3423 }
3424 
3425 struct rtw89_c2h_done_ack {
3426 	__le32 w0;
3427 	__le32 w1;
3428 	__le32 w2;
3429 } __packed;
3430 
3431 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3432 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3433 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3434 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3435 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3436 
3437 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3438 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3439 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3440 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3441 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3442 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3443 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3444 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3445 
3446 struct rtw89_fw_c2h_log_fmt {
3447 	__le16 signature;
3448 	u8 feature;
3449 	u8 syntax;
3450 	__le32 fmt_id;
3451 	u8 file_num;
3452 	__le16 line_num;
3453 	u8 argc;
3454 	union {
3455 		DECLARE_FLEX_ARRAY(u8, raw);
3456 		DECLARE_FLEX_ARRAY(__le32, argv);
3457 	} __packed u;
3458 } __packed;
3459 
3460 #define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11
3461 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3462 #define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3463 #define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3464 #define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3465 
3466 struct rtw89_c2h_mac_bcnfltr_rpt {
3467 	__le32 w0;
3468 	__le32 w1;
3469 	__le32 w2;
3470 } __packed;
3471 
3472 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3473 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3474 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3475 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3476 
3477 struct rtw89_c2h_ra_rpt {
3478 	struct rtw89_c2h_hdr hdr;
3479 	__le32 w2;
3480 	__le32 w3;
3481 } __packed;
3482 
3483 #define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3484 #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3485 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3486 #define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3487 #define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3488 #define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3489 #define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3490 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3491 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3492 
3493 /* For WiFi 6 chips:
3494  *   VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3495  *   HT-new: [6:5]: NA, [4:0]: MCS
3496  * For WiFi 7 chips (V1):
3497  *   HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3498  */
3499 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3500 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3501 #define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3502 #define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
3503 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3504 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3505 				    FIELD_PREP(GENMASK(2, 0), mcs))
3506 
3507 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3508 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3509 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3510 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3511 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3512 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3513 
3514 struct rtw89_c2h_scanofld {
3515 	__le32 w0;
3516 	__le32 w1;
3517 	__le32 w2;
3518 	__le32 w3;
3519 	__le32 w4;
3520 	__le32 w5;
3521 	__le32 w6;
3522 	__le32 w7;
3523 } __packed;
3524 
3525 #define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0)
3526 #define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16)
3527 #define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20)
3528 #define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)
3529 #define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0)
3530 #define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4)
3531 #define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24)
3532 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3533 #define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0)
3534 #define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8)
3535 #define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16)
3536 #define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0)
3537 
3538 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3539 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3540 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3541 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3542 
3543 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3544 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3545 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3546 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3547 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3548 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3549 
3550 struct rtw89_mac_mcc_tsf_rpt {
3551 	u32 macid_x;
3552 	u32 macid_y;
3553 	u32 tsf_x_low;
3554 	u32 tsf_x_high;
3555 	u32 tsf_y_low;
3556 	u32 tsf_y_high;
3557 };
3558 
3559 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3560 
3561 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
3562 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3563 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
3564 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3565 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
3566 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3567 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
3568 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3569 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
3570 	le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3571 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
3572 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3573 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
3574 	le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3575 
3576 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
3577 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
3578 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
3579 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3580 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
3581 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3582 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
3583 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3584 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
3585 	le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3586 
3587 struct rtw89_mac_mrc_tsf_rpt {
3588 	unsigned int num;
3589 	u64 tsfs[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3590 };
3591 
3592 static_assert(sizeof(struct rtw89_mac_mrc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3593 
3594 struct rtw89_c2h_mrc_tsf_rpt_info {
3595 	__le32 tsf_low;
3596 	__le32 tsf_high;
3597 } __packed;
3598 
3599 struct rtw89_c2h_mrc_tsf_rpt {
3600 	struct rtw89_c2h_hdr hdr;
3601 	__le32 w2;
3602 	struct rtw89_c2h_mrc_tsf_rpt_info infos[];
3603 } __packed;
3604 
3605 #define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0)
3606 
3607 struct rtw89_c2h_mrc_status_rpt {
3608 	struct rtw89_c2h_hdr hdr;
3609 	__le32 w2;
3610 	__le32 tsf_low;
3611 	__le32 tsf_high;
3612 } __packed;
3613 
3614 #define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0)
3615 #define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6)
3616 
3617 struct rtw89_c2h_pkt_ofld_rsp {
3618 	__le32 w0;
3619 	__le32 w1;
3620 	__le32 w2;
3621 } __packed;
3622 
3623 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
3624 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
3625 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3626 
3627 struct rtw89_c2h_wow_aoac_report {
3628 	struct rtw89_c2h_hdr c2h_hdr;
3629 	u8 rpt_ver;
3630 	u8 sec_type;
3631 	u8 key_idx;
3632 	u8 pattern_idx;
3633 	u8 rekey_ok;
3634 	u8 rsvd1[3];
3635 	u8 ptk_tx_iv[8];
3636 	u8 eapol_key_replay_count[8];
3637 	u8 gtk[32];
3638 	u8 ptk_rx_iv[8];
3639 	u8 gtk_rx_iv[4][8];
3640 	__le64 igtk_key_id;
3641 	__le64 igtk_ipn;
3642 	u8 igtk[32];
3643 	u8 csa_pri_ch;
3644 	u8 csa_bw_ch_offset;
3645 	u8 csa_ch_band_chsw_failed;
3646 	u8 csa_rsvd1;
3647 } __packed;
3648 
3649 #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
3650 
3651 struct rtw89_h2c_bcnfltr {
3652 	__le32 w0;
3653 } __packed;
3654 
3655 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3656 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3657 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3658 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3659 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8)
3660 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3661 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3662 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3663 
3664 struct rtw89_h2c_ofld_rssi {
3665 	__le32 w0;
3666 	__le32 w1;
3667 } __packed;
3668 
3669 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3670 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3671 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3672 
3673 struct rtw89_h2c_ofld {
3674 	__le32 w0;
3675 } __packed;
3676 
3677 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3678 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3679 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
3680 
3681 #define RTW89_MFW_SIG	0xFF
3682 
3683 struct rtw89_mfw_info {
3684 	u8 cv;
3685 	u8 type; /* enum rtw89_fw_type */
3686 	u8 mp;
3687 	u8 rsvd;
3688 	__le32 shift;
3689 	__le32 size;
3690 	u8 rsvd2[4];
3691 } __packed;
3692 
3693 struct rtw89_mfw_hdr {
3694 	u8 sig;	/* RTW89_MFW_SIG */
3695 	u8 fw_nr;
3696 	u8 rsvd0[2];
3697 	struct {
3698 		u8 major;
3699 		u8 minor;
3700 		u8 sub;
3701 		u8 idx;
3702 	} ver;
3703 	u8 rsvd1[8];
3704 	struct rtw89_mfw_info info[];
3705 } __packed;
3706 
3707 struct rtw89_fw_logsuit_hdr {
3708 	__le32 rsvd;
3709 	__le32 count;
3710 	__le32 ids[];
3711 } __packed;
3712 
3713 #define RTW89_FW_ELEMENT_ALIGN 16
3714 
3715 enum rtw89_fw_element_id {
3716 	RTW89_FW_ELEMENT_ID_BBMCU0 = 0,
3717 	RTW89_FW_ELEMENT_ID_BBMCU1 = 1,
3718 	RTW89_FW_ELEMENT_ID_BB_REG = 2,
3719 	RTW89_FW_ELEMENT_ID_BB_GAIN = 3,
3720 	RTW89_FW_ELEMENT_ID_RADIO_A = 4,
3721 	RTW89_FW_ELEMENT_ID_RADIO_B = 5,
3722 	RTW89_FW_ELEMENT_ID_RADIO_C = 6,
3723 	RTW89_FW_ELEMENT_ID_RADIO_D = 7,
3724 	RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
3725 	RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9,
3726 	RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10,
3727 	RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11,
3728 	RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12,
3729 	RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13,
3730 	RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14,
3731 	RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15,
3732 	RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16,
3733 	RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17,
3734 	RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18,
3735 	RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19,
3736 
3737 	RTW89_FW_ELEMENT_ID_NUM,
3738 };
3739 
3740 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \
3741 	(BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
3742 	 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
3743 	 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
3744 	 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
3745 	 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
3746 	 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
3747 	 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ) | \
3748 	 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
3749 	 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
3750 
3751 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
3752 					     BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3753 					     BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3754 					     BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3755 					     BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3756 					     BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3757 					     BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
3758 
3759 struct __rtw89_fw_txpwr_element {
3760 	u8 rsvd0;
3761 	u8 rsvd1;
3762 	u8 rfe_type;
3763 	u8 ent_sz;
3764 	__le32 num_ents;
3765 	u8 content[];
3766 } __packed;
3767 
3768 enum rtw89_fw_txpwr_trk_type {
3769 	__RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0,
3770 	RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0,
3771 	RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1,
3772 	RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2,
3773 	RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3,
3774 	__RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3,
3775 
3776 	__RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4,
3777 	RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4,
3778 	RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5,
3779 	RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6,
3780 	RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7,
3781 	__RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7,
3782 
3783 	__RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8,
3784 	RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8,
3785 	RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9,
3786 	RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10,
3787 	RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11,
3788 	RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12,
3789 	RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13,
3790 	RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14,
3791 	RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15,
3792 	__RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15,
3793 
3794 	RTW89_FW_TXPWR_TRK_TYPE_NR,
3795 };
3796 
3797 struct rtw89_fw_txpwr_track_cfg {
3798 	const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE];
3799 };
3800 
3801 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \
3802 	(BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
3803 	 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
3804 	 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
3805 	 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
3806 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \
3807 	(BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
3808 	 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
3809 	 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
3810 	 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
3811 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \
3812 	(BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
3813 	 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
3814 	 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
3815 	 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
3816 	 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
3817 	 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
3818 	 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
3819 	 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
3820 
3821 struct rtw89_fw_element_hdr {
3822 	__le32 id; /* enum rtw89_fw_element_id */
3823 	__le32 size; /* exclude header size */
3824 	u8 ver[4];
3825 	__le32 rsvd0;
3826 	__le32 rsvd1;
3827 	__le32 rsvd2;
3828 	union {
3829 		struct {
3830 			u8 priv[8];
3831 			u8 contents[];
3832 		} __packed common;
3833 		struct {
3834 			u8 idx;
3835 			u8 rsvd[7];
3836 			struct {
3837 				__le32 addr;
3838 				__le32 data;
3839 			} __packed regs[];
3840 		} __packed reg2;
3841 		struct {
3842 			u8 cv;
3843 			u8 priv[7];
3844 			u8 contents[];
3845 		} __packed bbmcu;
3846 		struct {
3847 			__le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */
3848 			__le32 rsvd;
3849 			s8 contents[][DELTA_SWINGIDX_SIZE];
3850 		} __packed txpwr_trk;
3851 		struct {
3852 			u8 nr;
3853 			u8 rsvd[3];
3854 			u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */
3855 			u8 rsvd1[3];
3856 			__le16 offset[];
3857 		} __packed rfk_log_fmt;
3858 		struct __rtw89_fw_txpwr_element txpwr;
3859 	} __packed u;
3860 } __packed;
3861 
3862 struct fwcmd_hdr {
3863 	__le32 hdr0;
3864 	__le32 hdr1;
3865 };
3866 
3867 union rtw89_compat_fw_hdr {
3868 	struct rtw89_mfw_hdr mfw_hdr;
3869 	struct rtw89_fw_hdr fw_hdr;
3870 };
3871 
3872 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
3873 {
3874 	const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
3875 
3876 	if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
3877 		return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
3878 	else
3879 		return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
3880 }
3881 
3882 static inline void rtw89_fw_get_filename(char *buf, size_t size,
3883 					 const char *fw_basename, int fw_format)
3884 {
3885 	if (fw_format <= 0)
3886 		snprintf(buf, size, "%s.bin", fw_basename);
3887 	else
3888 		snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
3889 }
3890 
3891 #define RTW89_H2C_RF_PAGE_SIZE 500
3892 #define RTW89_H2C_RF_PAGE_NUM 3
3893 struct rtw89_fw_h2c_rf_reg_info {
3894 	enum rtw89_rf_path rf_path;
3895 	__le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
3896 	u16 curr_idx;
3897 };
3898 
3899 #define H2C_SEC_CAM_LEN			24
3900 
3901 #define H2C_HEADER_LEN			8
3902 #define H2C_HDR_CAT			GENMASK(1, 0)
3903 #define H2C_HDR_CLASS			GENMASK(7, 2)
3904 #define H2C_HDR_FUNC			GENMASK(15, 8)
3905 #define H2C_HDR_DEL_TYPE		GENMASK(19, 16)
3906 #define H2C_HDR_H2C_SEQ			GENMASK(31, 24)
3907 #define H2C_HDR_TOTAL_LEN		GENMASK(13, 0)
3908 #define H2C_HDR_REC_ACK			BIT(14)
3909 #define H2C_HDR_DONE_ACK		BIT(15)
3910 
3911 #define FWCMD_TYPE_H2C			0
3912 
3913 #define H2C_CAT_TEST		0x0
3914 
3915 /* CLASS 5 - FW STATUS TEST */
3916 #define H2C_CL_FW_STATUS_TEST		0x5
3917 #define H2C_FUNC_CPU_EXCEPTION		0x1
3918 
3919 #define H2C_CAT_MAC		0x1
3920 
3921 /* CLASS 0 - FW INFO */
3922 #define H2C_CL_FW_INFO			0x0
3923 #define H2C_FUNC_LOG_CFG		0x0
3924 #define H2C_FUNC_MAC_GENERAL_PKT	0x1
3925 
3926 /* CLASS 1 - WOW */
3927 #define H2C_CL_MAC_WOW			0x1
3928 enum rtw89_wow_h2c_func {
3929 	H2C_FUNC_KEEP_ALIVE		= 0x0,
3930 	H2C_FUNC_DISCONNECT_DETECT	= 0x1,
3931 	H2C_FUNC_WOW_GLOBAL		= 0x2,
3932 	H2C_FUNC_GTK_OFLD		= 0x3,
3933 	H2C_FUNC_ARP_OFLD		= 0x4,
3934 	H2C_FUNC_WAKEUP_CTRL		= 0x8,
3935 	H2C_FUNC_WOW_CAM_UPD		= 0xC,
3936 	H2C_FUNC_AOAC_REPORT_REQ	= 0xD,
3937 
3938 	NUM_OF_RTW89_WOW_H2C_FUNC,
3939 };
3940 
3941 #define RTW89_WOW_WAIT_COND(func) \
3942 	(NUM_OF_RTW89_WOW_H2C_FUNC + (func))
3943 
3944 /* CLASS 2 - PS */
3945 #define H2C_CL_MAC_PS			0x2
3946 #define H2C_FUNC_MAC_LPS_PARM		0x0
3947 #define H2C_FUNC_P2P_ACT		0x1
3948 
3949 /* CLASS 3 - FW download */
3950 #define H2C_CL_MAC_FWDL		0x3
3951 #define H2C_FUNC_MAC_FWHDR_DL		0x0
3952 
3953 /* CLASS 5 - Frame Exchange */
3954 #define H2C_CL_MAC_FR_EXCHG		0x5
3955 #define H2C_FUNC_MAC_CCTLINFO_UD	0x2
3956 #define H2C_FUNC_MAC_BCN_UPD		0x5
3957 #define H2C_FUNC_MAC_DCTLINFO_UD_V1	0x9
3958 #define H2C_FUNC_MAC_CCTLINFO_UD_V1	0xa
3959 #define H2C_FUNC_MAC_DCTLINFO_UD_V2	0xc
3960 #define H2C_FUNC_MAC_BCN_UPD_BE		0xd
3961 #define H2C_FUNC_MAC_CCTLINFO_UD_G7	0x11
3962 
3963 /* CLASS 6 - Address CAM */
3964 #define H2C_CL_MAC_ADDR_CAM_UPDATE	0x6
3965 #define H2C_FUNC_MAC_ADDR_CAM_UPD	0x0
3966 
3967 /* CLASS 8 - Media Status Report */
3968 #define H2C_CL_MAC_MEDIA_RPT		0x8
3969 #define H2C_FUNC_MAC_JOININFO		0x0
3970 #define H2C_FUNC_MAC_FWROLE_MAINTAIN	0x4
3971 #define H2C_FUNC_NOTIFY_DBCC		0x5
3972 
3973 /* CLASS 9 - FW offload */
3974 #define H2C_CL_MAC_FW_OFLD		0x9
3975 enum rtw89_fw_ofld_h2c_func {
3976 	H2C_FUNC_PACKET_OFLD		= 0x1,
3977 	H2C_FUNC_MAC_MACID_PAUSE	= 0x8,
3978 	H2C_FUNC_USR_EDCA		= 0xF,
3979 	H2C_FUNC_TSF32_TOGL		= 0x10,
3980 	H2C_FUNC_OFLD_CFG		= 0x14,
3981 	H2C_FUNC_ADD_SCANOFLD_CH	= 0x16,
3982 	H2C_FUNC_SCANOFLD		= 0x17,
3983 	H2C_FUNC_PKT_DROP		= 0x1b,
3984 	H2C_FUNC_CFG_BCNFLTR		= 0x1e,
3985 	H2C_FUNC_OFLD_RSSI		= 0x1f,
3986 	H2C_FUNC_OFLD_TP		= 0x20,
3987 	H2C_FUNC_MAC_MACID_PAUSE_SLEEP	= 0x28,
3988 	H2C_FUNC_SCANOFLD_BE		= 0x2c,
3989 
3990 	NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
3991 };
3992 
3993 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \
3994 	((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
3995 
3996 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
3997 	RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
3998 				H2C_FUNC_PACKET_OFLD)
3999 
4000 #define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH)
4001 
4002 #define RTW89_SCANOFLD_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD)
4003 #define RTW89_SCANOFLD_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD)
4004 #define RTW89_SCANOFLD_BE_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD_BE)
4005 #define RTW89_SCANOFLD_BE_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD_BE)
4006 
4007 
4008 /* CLASS 10 - Security CAM */
4009 #define H2C_CL_MAC_SEC_CAM		0xa
4010 #define H2C_FUNC_MAC_SEC_UPD		0x1
4011 
4012 /* CLASS 12 - BA CAM */
4013 #define H2C_CL_BA_CAM			0xc
4014 #define H2C_FUNC_MAC_BA_CAM		0x0
4015 #define H2C_FUNC_MAC_BA_CAM_V1		0x1
4016 #define H2C_FUNC_MAC_BA_CAM_INIT	0x2
4017 
4018 /* CLASS 14 - MCC */
4019 #define H2C_CL_MCC			0xe
4020 enum rtw89_mcc_h2c_func {
4021 	H2C_FUNC_ADD_MCC		= 0x0,
4022 	H2C_FUNC_START_MCC		= 0x1,
4023 	H2C_FUNC_STOP_MCC		= 0x2,
4024 	H2C_FUNC_DEL_MCC_GROUP		= 0x3,
4025 	H2C_FUNC_RESET_MCC_GROUP	= 0x4,
4026 	H2C_FUNC_MCC_REQ_TSF		= 0x5,
4027 	H2C_FUNC_MCC_MACID_BITMAP	= 0x6,
4028 	H2C_FUNC_MCC_SYNC		= 0x7,
4029 	H2C_FUNC_MCC_SET_DURATION	= 0x8,
4030 
4031 	NUM_OF_RTW89_MCC_H2C_FUNC,
4032 };
4033 
4034 #define RTW89_MCC_WAIT_COND(group, func) \
4035 	((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
4036 
4037 /* CLASS 24 - MRC */
4038 #define H2C_CL_MRC			0x18
4039 enum rtw89_mrc_h2c_func {
4040 	H2C_FUNC_MRC_REQ_TSF		= 0x0,
4041 	H2C_FUNC_ADD_MRC		= 0x1,
4042 	H2C_FUNC_START_MRC		= 0x2,
4043 	H2C_FUNC_DEL_MRC		= 0x3,
4044 	H2C_FUNC_MRC_SYNC		= 0x4,
4045 	H2C_FUNC_MRC_UPD_DURATION	= 0x5,
4046 	H2C_FUNC_MRC_UPD_BITMAP		= 0x6,
4047 
4048 	NUM_OF_RTW89_MRC_H2C_FUNC,
4049 };
4050 
4051 /* can consider MRC's sch_idx as MCC's group */
4052 #define RTW89_MRC_WAIT_COND(sch_idx, func) \
4053 	((sch_idx) * NUM_OF_RTW89_MRC_H2C_FUNC + (func))
4054 
4055 #define RTW89_MRC_WAIT_COND_REQ_TSF \
4056 	RTW89_MRC_WAIT_COND(0 /* don't care */, H2C_FUNC_MRC_REQ_TSF)
4057 
4058 #define H2C_CAT_OUTSRC			0x2
4059 
4060 #define H2C_CL_OUTSRC_RA		0x1
4061 #define H2C_FUNC_OUTSRC_RA_MACIDCFG	0x0
4062 
4063 #define H2C_CL_OUTSRC_DM		0x2
4064 #define H2C_FUNC_FW_LPS_CH_INFO		0xb
4065 
4066 #define H2C_CL_OUTSRC_RF_REG_A		0x8
4067 #define H2C_CL_OUTSRC_RF_REG_B		0x9
4068 #define H2C_CL_OUTSRC_RF_FW_NOTIFY	0xa
4069 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH	0x2
4070 #define H2C_CL_OUTSRC_RF_FW_RFK		0xb
4071 
4072 enum rtw89_rfk_offload_h2c_func {
4073 	H2C_FUNC_RFK_TSSI_OFFLOAD = 0x0,
4074 	H2C_FUNC_RFK_IQK_OFFLOAD = 0x1,
4075 	H2C_FUNC_RFK_DPK_OFFLOAD = 0x3,
4076 	H2C_FUNC_RFK_TXGAPK_OFFLOAD = 0x4,
4077 	H2C_FUNC_RFK_DACK_OFFLOAD = 0x5,
4078 	H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6,
4079 	H2C_FUNC_RFK_PRE_NOTIFY = 0x8,
4080 };
4081 
4082 struct rtw89_fw_h2c_rf_get_mccch {
4083 	__le32 ch_0;
4084 	__le32 ch_1;
4085 	__le32 band_0;
4086 	__le32 band_1;
4087 	__le32 current_channel;
4088 	__le32 current_band_type;
4089 } __packed;
4090 
4091 #define NUM_OF_RTW89_FW_RFK_PATH 2
4092 #define NUM_OF_RTW89_FW_RFK_TBL 3
4093 
4094 struct rtw89_fw_h2c_rfk_pre_info {
4095 	struct {
4096 		__le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4097 		__le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4098 	} __packed dbcc;
4099 
4100 	__le32 mlo_mode;
4101 	struct {
4102 		__le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH];
4103 		__le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH];
4104 	} __packed tbl;
4105 
4106 	__le32 phy_idx;
4107 	__le32 cur_band;
4108 	__le32 cur_bw;
4109 	__le32 cur_center_ch;
4110 
4111 	__le32 ktbl_sel0;
4112 	__le32 ktbl_sel1;
4113 	__le32 rfmod0;
4114 	__le32 rfmod1;
4115 
4116 	__le32 mlo_1_1;
4117 	__le32 rfe_type;
4118 	__le32 drv_mode;
4119 
4120 	struct {
4121 		__le32 ch[NUM_OF_RTW89_FW_RFK_PATH];
4122 		__le32 band[NUM_OF_RTW89_FW_RFK_PATH];
4123 	} __packed mlo;
4124 } __packed;
4125 
4126 struct rtw89_h2c_rf_tssi {
4127 	__le16 len;
4128 	u8 phy;
4129 	u8 ch;
4130 	u8 bw;
4131 	u8 band;
4132 	u8 hwtx_en;
4133 	u8 cv;
4134 	s8 curr_tssi_cck_de[2];
4135 	s8 curr_tssi_cck_de_20m[2];
4136 	s8 curr_tssi_cck_de_40m[2];
4137 	s8 curr_tssi_efuse_cck_de[2];
4138 	s8 curr_tssi_ofdm_de[2];
4139 	s8 curr_tssi_ofdm_de_20m[2];
4140 	s8 curr_tssi_ofdm_de_40m[2];
4141 	s8 curr_tssi_ofdm_de_80m[2];
4142 	s8 curr_tssi_ofdm_de_160m[2];
4143 	s8 curr_tssi_ofdm_de_320m[2];
4144 	s8 curr_tssi_efuse_ofdm_de[2];
4145 	s8 curr_tssi_ofdm_de_diff_20m[2];
4146 	s8 curr_tssi_ofdm_de_diff_80m[2];
4147 	s8 curr_tssi_ofdm_de_diff_160m[2];
4148 	s8 curr_tssi_ofdm_de_diff_320m[2];
4149 	s8 curr_tssi_trim_de[2];
4150 	u8 pg_thermal[2];
4151 	u8 ftable[2][128];
4152 	u8 tssi_mode;
4153 } __packed;
4154 
4155 struct rtw89_h2c_rf_iqk {
4156 	__le32 phy_idx;
4157 	__le32 dbcc;
4158 } __packed;
4159 
4160 struct rtw89_h2c_rf_dpk {
4161 	u8 len;
4162 	u8 phy;
4163 	u8 dpk_enable;
4164 	u8 kpath;
4165 	u8 cur_band;
4166 	u8 cur_bw;
4167 	u8 cur_ch;
4168 	u8 dpk_dbg_en;
4169 } __packed;
4170 
4171 struct rtw89_h2c_rf_txgapk {
4172 	u8 len;
4173 	u8 ktype;
4174 	u8 phy;
4175 	u8 kpath;
4176 	u8 band;
4177 	u8 bw;
4178 	u8 ch;
4179 	u8 cv;
4180 } __packed;
4181 
4182 struct rtw89_h2c_rf_dack {
4183 	__le32 len;
4184 	__le32 phy;
4185 	__le32 type;
4186 } __packed;
4187 
4188 struct rtw89_h2c_rf_rxdck {
4189 	u8 len;
4190 	u8 phy;
4191 	u8 is_afe;
4192 	u8 kpath;
4193 	u8 cur_band;
4194 	u8 cur_bw;
4195 	u8 cur_ch;
4196 	u8 rxdck_dbg_en;
4197 } __packed;
4198 
4199 enum rtw89_rf_log_type {
4200 	RTW89_RF_RUN_LOG = 0,
4201 	RTW89_RF_RPT_LOG = 1,
4202 };
4203 
4204 struct rtw89_c2h_rf_log_hdr {
4205 	u8 type; /* enum rtw89_rf_log_type */
4206 	__le16 len;
4207 	u8 content[];
4208 } __packed;
4209 
4210 struct rtw89_c2h_rf_run_log {
4211 	__le32 fmt_idx;
4212 	__le32 arg[4];
4213 } __packed;
4214 
4215 struct rtw89_c2h_rf_dpk_rpt_log {
4216 	u8 ver;
4217 	u8 idx[2];
4218 	u8 band[2];
4219 	u8 bw[2];
4220 	u8 ch[2];
4221 	u8 path_ok[2];
4222 	u8 txagc[2];
4223 	u8 ther[2];
4224 	u8 gs[2];
4225 	u8 dc_i[4];
4226 	u8 dc_q[4];
4227 	u8 corr_val[2];
4228 	u8 corr_idx[2];
4229 	u8 is_timeout[2];
4230 	u8 rxbb_ov[2];
4231 	u8 rsvd;
4232 } __packed;
4233 
4234 struct rtw89_c2h_rf_dack_rpt_log {
4235 	u8 fwdack_ver;
4236 	u8 fwdack_rpt_ver;
4237 	u8 msbk_d[2][2][16];
4238 	u8 dadck_d[2][2];
4239 	u8 cdack_d[2][2][2];
4240 	__le16 addck2_d[2][2][2];
4241 	u8 adgaink_d[2][2];
4242 	__le16 biask_d[2][2];
4243 	u8 addck_timeout;
4244 	u8 cdack_timeout;
4245 	u8 dadck_timeout;
4246 	u8 msbk_timeout;
4247 	u8 adgaink_timeout;
4248 	u8 dack_fail;
4249 } __packed;
4250 
4251 struct rtw89_c2h_rf_rxdck_rpt_log {
4252 	u8 ver;
4253 	u8 band[2];
4254 	u8 bw[2];
4255 	u8 ch[2];
4256 	u8 timeout[2];
4257 } __packed;
4258 
4259 struct rtw89_c2h_rf_txgapk_rpt_log {
4260 	__le32 r0x8010[2];
4261 	__le32 chk_cnt;
4262 	u8 track_d[2][17];
4263 	u8 power_d[2][17];
4264 	u8 is_txgapk_ok;
4265 	u8 chk_id;
4266 	u8 ver;
4267 	u8 rsv1;
4268 } __packed;
4269 
4270 struct rtw89_c2h_rfk_report {
4271 	struct rtw89_c2h_hdr hdr;
4272 	u8 state; /* enum rtw89_rfk_report_state */
4273 	u8 version;
4274 } __packed;
4275 
4276 #define RTW89_FW_RSVD_PLE_SIZE 0x800
4277 
4278 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
4279 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
4280 	((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
4281 
4282 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
4283 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
4284 
4285 #define FWDL_WAIT_CNT 400000
4286 
4287 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
4288 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
4289 int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
4290 const struct firmware *
4291 rtw89_early_fw_feature_recognize(struct device *device,
4292 				 const struct rtw89_chip_info *chip,
4293 				 struct rtw89_fw_info *early_fw,
4294 				 int *used_fw_format);
4295 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
4296 		      bool include_bb);
4297 void rtw89_load_firmware_work(struct work_struct *work);
4298 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
4299 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
4300 int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev);
4301 void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len);
4302 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4303 			   u8 type, u8 cat, u8 class, u8 func,
4304 			   bool rack, bool dack, u32 len);
4305 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4306 				  struct rtw89_vif *rtwvif,
4307 				  struct rtw89_sta *rtwsta);
4308 int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4309 				     struct rtw89_vif *rtwvif,
4310 				     struct rtw89_sta *rtwsta);
4311 int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
4312 				     struct rtw89_vif *rtwvif,
4313 				     struct rtw89_sta *rtwsta);
4314 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4315 				struct ieee80211_vif *vif,
4316 				struct ieee80211_sta *sta);
4317 int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4318 				   struct ieee80211_vif *vif,
4319 				   struct ieee80211_sta *sta);
4320 int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4321 				   struct ieee80211_vif *vif,
4322 				   struct ieee80211_sta *sta);
4323 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
4324 				 struct rtw89_sta *rtwsta);
4325 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
4326 				 struct rtw89_sta *rtwsta);
4327 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
4328 			       struct rtw89_vif *rtwvif);
4329 int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev,
4330 				  struct rtw89_vif *rtwvif);
4331 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif,
4332 		     struct rtw89_sta *rtwsta, const u8 *scan_mac_addr);
4333 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
4334 				 struct rtw89_vif *rtwvif,
4335 				 struct rtw89_sta *rtwsta);
4336 int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev,
4337 				 struct rtw89_vif *rtwvif,
4338 				 struct rtw89_sta *rtwsta);
4339 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
4340 void rtw89_fw_c2h_work(struct work_struct *work);
4341 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
4342 			       struct rtw89_vif *rtwvif,
4343 			       struct rtw89_sta *rtwsta,
4344 			       enum rtw89_upd_mode upd_mode);
4345 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4346 			   struct rtw89_sta *rtwsta, bool dis_conn);
4347 int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en);
4348 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
4349 			     bool pause);
4350 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4351 			  u8 ac, u32 val);
4352 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
4353 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
4354 				  struct ieee80211_vif *vif,
4355 				  bool connect);
4356 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
4357 			      struct rtw89_rx_phy_ppdu *phy_ppdu);
4358 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
4359 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
4360 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type);
4361 int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type);
4362 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type);
4363 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type);
4364 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type);
4365 int rtw89_fw_h2c_cxdrv_role_v8(struct rtw89_dev *rtwdev, u8 type);
4366 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type);
4367 int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type);
4368 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type);
4369 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type);
4370 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
4371 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
4372 				 struct sk_buff *skb_ofld);
4373 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int ch_num,
4374 				   struct list_head *chan_list);
4375 int rtw89_fw_h2c_scan_list_offload_be(struct rtw89_dev *rtwdev, int ch_num,
4376 				      struct list_head *chan_list);
4377 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev,
4378 			      struct rtw89_scan_option *opt,
4379 			      struct rtw89_vif *vif);
4380 int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
4381 				 struct rtw89_scan_option *opt,
4382 				 struct rtw89_vif *vif);
4383 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
4384 			struct rtw89_fw_h2c_rf_reg_info *info,
4385 			u16 len, u8 page);
4386 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
4387 int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
4388 			     enum rtw89_phy_idx phy_idx);
4389 int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4390 			 enum rtw89_tssi_mode tssi_mode);
4391 int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
4392 int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
4393 int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
4394 int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
4395 int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
4396 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
4397 			      u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
4398 			      bool rack, bool dack);
4399 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
4400 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
4401 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
4402 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4403 			     u8 macid);
4404 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
4405 					   struct rtw89_vif *rtwvif, bool notify_fw);
4406 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
4407 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4408 			bool valid, struct ieee80211_ampdu_params *params);
4409 int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4410 			   bool valid, struct ieee80211_ampdu_params *params);
4411 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
4412 int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users,
4413 				   u8 offset, u8 mac_idx);
4414 
4415 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
4416 			  struct rtw89_lps_parm *lps_param);
4417 int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev,
4418 			     struct rtw89_vif *rtwvif);
4419 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
4420 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
4421 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
4422 		     struct rtw89_mac_h2c_info *h2c_info,
4423 		     struct rtw89_mac_c2h_info *c2h_info);
4424 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
4425 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
4426 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4427 			 struct ieee80211_scan_request *req);
4428 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4429 			    bool aborted);
4430 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4431 			  bool enable);
4432 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
4433 int rtw89_hw_scan_add_chan_list(struct rtw89_dev *rtwdev,
4434 				struct rtw89_vif *rtwvif, bool connected);
4435 int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4436 				   struct rtw89_vif *rtwvif, bool connected);
4437 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
4438 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
4439 			  const struct rtw89_pkt_drop_params *params);
4440 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4441 			 struct ieee80211_p2p_noa_desc *desc,
4442 			 u8 act, u8 noa_id);
4443 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4444 			      bool en);
4445 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4446 			    bool enable);
4447 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4448 				 struct rtw89_vif *rtwvif, bool enable);
4449 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4450 			    bool enable);
4451 int rtw89_fw_h2c_arp_offload(struct rtw89_dev *rtwdev,
4452 			     struct rtw89_vif *rtwvif, bool enable);
4453 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
4454 				   struct rtw89_vif *rtwvif, bool enable);
4455 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4456 			    bool enable);
4457 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4458 				 struct rtw89_vif *rtwvif, bool enable);
4459 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
4460 			    struct rtw89_wow_cam_info *cam_info);
4461 int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev,
4462 			      struct rtw89_vif *rtwvif,
4463 			      bool enable);
4464 int rtw89_fw_h2c_wow_request_aoac(struct rtw89_dev *rtwdev);
4465 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
4466 			 const struct rtw89_fw_mcc_add_req *p);
4467 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
4468 			   const struct rtw89_fw_mcc_start_req *p);
4469 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4470 			  bool prev_groups);
4471 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
4472 			       bool prev_groups);
4473 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
4474 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
4475 			     const struct rtw89_fw_mcc_tsf_req *req,
4476 			     struct rtw89_mac_mcc_tsf_rpt *rpt);
4477 int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4478 				  u8 *bitmap);
4479 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
4480 			  u8 target, u8 offset);
4481 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
4482 				  const struct rtw89_fw_mcc_duration *p);
4483 int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev,
4484 			 const struct rtw89_fw_mrc_add_arg *arg);
4485 int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev,
4486 			   const struct rtw89_fw_mrc_start_arg *arg);
4487 int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx);
4488 int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev,
4489 			     const struct rtw89_fw_mrc_req_tsf_arg *arg,
4490 			     struct rtw89_mac_mrc_tsf_rpt *rpt);
4491 int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev,
4492 				const struct rtw89_fw_mrc_upd_bitmap_arg *arg);
4493 int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev,
4494 			  const struct rtw89_fw_mrc_sync_arg *arg);
4495 int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev,
4496 				  const struct rtw89_fw_mrc_upd_duration_arg *arg);
4497 
4498 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
4499 {
4500 	const struct rtw89_chip_info *chip = rtwdev->chip;
4501 
4502 	if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
4503 		rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
4504 }
4505 
4506 static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4507 						  struct rtw89_vif *rtwvif,
4508 						  struct rtw89_sta *rtwsta)
4509 {
4510 	const struct rtw89_chip_info *chip = rtwdev->chip;
4511 
4512 	return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif, rtwsta);
4513 }
4514 
4515 static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev,
4516 						  struct rtw89_vif *rtwvif,
4517 						  struct rtw89_sta *rtwsta)
4518 {
4519 	const struct rtw89_chip_info *chip = rtwdev->chip;
4520 
4521 	if (chip->ops->h2c_default_dmac_tbl)
4522 		return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif, rtwsta);
4523 
4524 	return 0;
4525 }
4526 
4527 static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev,
4528 					       struct rtw89_vif *rtwvif)
4529 {
4530 	const struct rtw89_chip_info *chip = rtwdev->chip;
4531 
4532 	return chip->ops->h2c_update_beacon(rtwdev, rtwvif);
4533 }
4534 
4535 static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4536 						struct ieee80211_vif *vif,
4537 						struct ieee80211_sta *sta)
4538 {
4539 	const struct rtw89_chip_info *chip = rtwdev->chip;
4540 
4541 	return chip->ops->h2c_assoc_cmac_tbl(rtwdev, vif, sta);
4542 }
4543 
4544 static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev,
4545 						struct ieee80211_vif *vif,
4546 						struct ieee80211_sta *sta)
4547 {
4548 	const struct rtw89_chip_info *chip = rtwdev->chip;
4549 
4550 	if (chip->ops->h2c_ampdu_cmac_tbl)
4551 		return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, vif, sta);
4552 
4553 	return 0;
4554 }
4555 
4556 static inline
4557 int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4558 			  bool valid, struct ieee80211_ampdu_params *params)
4559 {
4560 	const struct rtw89_chip_info *chip = rtwdev->chip;
4561 
4562 	return chip->ops->h2c_ba_cam(rtwdev, rtwsta, valid, params);
4563 }
4564 
4565 /* must consider compatibility; don't insert new in the mid */
4566 struct rtw89_fw_txpwr_byrate_entry {
4567 	u8 band;
4568 	u8 nss;
4569 	u8 rs;
4570 	u8 shf;
4571 	u8 len;
4572 	__le32 data;
4573 	u8 bw;
4574 	u8 ofdma;
4575 } __packed;
4576 
4577 /* must consider compatibility; don't insert new in the mid */
4578 struct rtw89_fw_txpwr_lmt_2ghz_entry {
4579 	u8 bw;
4580 	u8 nt;
4581 	u8 rs;
4582 	u8 bf;
4583 	u8 regd;
4584 	u8 ch_idx;
4585 	s8 v;
4586 } __packed;
4587 
4588 /* must consider compatibility; don't insert new in the mid */
4589 struct rtw89_fw_txpwr_lmt_5ghz_entry {
4590 	u8 bw;
4591 	u8 nt;
4592 	u8 rs;
4593 	u8 bf;
4594 	u8 regd;
4595 	u8 ch_idx;
4596 	s8 v;
4597 } __packed;
4598 
4599 /* must consider compatibility; don't insert new in the mid */
4600 struct rtw89_fw_txpwr_lmt_6ghz_entry {
4601 	u8 bw;
4602 	u8 nt;
4603 	u8 rs;
4604 	u8 bf;
4605 	u8 regd;
4606 	u8 reg_6ghz_power;
4607 	u8 ch_idx;
4608 	s8 v;
4609 } __packed;
4610 
4611 /* must consider compatibility; don't insert new in the mid */
4612 struct rtw89_fw_txpwr_lmt_ru_2ghz_entry {
4613 	u8 ru;
4614 	u8 nt;
4615 	u8 regd;
4616 	u8 ch_idx;
4617 	s8 v;
4618 } __packed;
4619 
4620 /* must consider compatibility; don't insert new in the mid */
4621 struct rtw89_fw_txpwr_lmt_ru_5ghz_entry {
4622 	u8 ru;
4623 	u8 nt;
4624 	u8 regd;
4625 	u8 ch_idx;
4626 	s8 v;
4627 } __packed;
4628 
4629 /* must consider compatibility; don't insert new in the mid */
4630 struct rtw89_fw_txpwr_lmt_ru_6ghz_entry {
4631 	u8 ru;
4632 	u8 nt;
4633 	u8 regd;
4634 	u8 reg_6ghz_power;
4635 	u8 ch_idx;
4636 	s8 v;
4637 } __packed;
4638 
4639 /* must consider compatibility; don't insert new in the mid */
4640 struct rtw89_fw_tx_shape_lmt_entry {
4641 	u8 band;
4642 	u8 tx_shape_rs;
4643 	u8 regd;
4644 	u8 v;
4645 } __packed;
4646 
4647 /* must consider compatibility; don't insert new in the mid */
4648 struct rtw89_fw_tx_shape_lmt_ru_entry {
4649 	u8 band;
4650 	u8 regd;
4651 	u8 v;
4652 } __packed;
4653 
4654 const struct rtw89_rfe_parms *
4655 rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
4656 			    const struct rtw89_rfe_parms *init);
4657 
4658 #endif
4659