1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/hex.h> 6 #include <linux/vmalloc.h> 7 8 #include "coex.h" 9 #include "debug.h" 10 #include "fw.h" 11 #include "mac.h" 12 #include "pci.h" 13 #include "phy.h" 14 #include "ps.h" 15 #include "reg.h" 16 #include "sar.h" 17 #include "util.h" 18 19 #ifdef CONFIG_RTW89_DEBUGMSG 20 unsigned int rtw89_debug_mask; 21 EXPORT_SYMBOL(rtw89_debug_mask); 22 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 23 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 24 #endif 25 26 #ifdef CONFIG_RTW89_DEBUGFS 27 struct rtw89_debugfs_priv_opt { 28 bool rlock:1; 29 bool wlock:1; 30 size_t rsize; 31 }; 32 33 struct rtw89_debugfs_priv { 34 struct rtw89_dev *rtwdev; 35 ssize_t (*cb_read)(struct rtw89_dev *rtwdev, 36 struct rtw89_debugfs_priv *debugfs_priv, 37 char *buf, size_t bufsz); 38 ssize_t (*cb_write)(struct rtw89_dev *rtwdev, 39 struct rtw89_debugfs_priv *debugfs_priv, 40 const char *buf, size_t count); 41 struct rtw89_debugfs_priv_opt opt; 42 union { 43 u32 cb_data; 44 struct { 45 u32 addr; 46 u32 len; 47 } read_reg; 48 struct { 49 u32 addr; 50 u32 mask; 51 u8 path; 52 } read_rf; 53 struct { 54 u8 ss_dbg:1; 55 u8 dle_dbg:1; 56 u8 dmac_dbg:1; 57 u8 cmac_dbg:1; 58 u8 dbg_port:1; 59 } dbgpkg_en; 60 struct { 61 u32 start; 62 u32 len; 63 u8 sel; 64 } mac_mem; 65 }; 66 ssize_t rused; 67 char *rbuf; 68 }; 69 70 struct rtw89_debugfs { 71 struct rtw89_debugfs_priv read_reg; 72 struct rtw89_debugfs_priv write_reg; 73 struct rtw89_debugfs_priv read_rf; 74 struct rtw89_debugfs_priv write_rf; 75 struct rtw89_debugfs_priv rf_reg_dump; 76 struct rtw89_debugfs_priv txpwr_table; 77 struct rtw89_debugfs_priv mac_reg_dump; 78 struct rtw89_debugfs_priv mac_mem_dump; 79 struct rtw89_debugfs_priv mac_dbg_port_dump; 80 struct rtw89_debugfs_priv send_h2c; 81 struct rtw89_debugfs_priv early_h2c; 82 struct rtw89_debugfs_priv fw_crash; 83 struct rtw89_debugfs_priv ser_counters; 84 struct rtw89_debugfs_priv btc_info; 85 struct rtw89_debugfs_priv btc_manual; 86 struct rtw89_debugfs_priv fw_log_manual; 87 struct rtw89_debugfs_priv phy_info; 88 struct rtw89_debugfs_priv bb_info; 89 struct rtw89_debugfs_priv stations; 90 struct rtw89_debugfs_priv disable_dm; 91 struct rtw89_debugfs_priv static_pd_th; 92 struct rtw89_debugfs_priv mlo_mode; 93 struct rtw89_debugfs_priv beacon_info; 94 struct rtw89_debugfs_priv diag_mac; 95 struct rtw89_debugfs_priv diag_bb; 96 struct rtw89_debugfs_priv diag_rf; 97 struct rtw89_debugfs_priv monitor_opts; 98 }; 99 100 struct rtw89_debugfs_iter_data { 101 char *buf; 102 size_t bufsz; 103 int written_sz; 104 }; 105 106 static void rtw89_debugfs_iter_data_setup(struct rtw89_debugfs_iter_data *iter_data, 107 char *buf, size_t bufsz) 108 { 109 iter_data->buf = buf; 110 iter_data->bufsz = bufsz; 111 iter_data->written_sz = 0; 112 } 113 114 static void rtw89_debugfs_iter_data_next(struct rtw89_debugfs_iter_data *iter_data, 115 char *buf, size_t bufsz, int written_sz) 116 { 117 iter_data->buf = buf; 118 iter_data->bufsz = bufsz; 119 iter_data->written_sz += written_sz; 120 } 121 122 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 123 [RATE_INFO_BW_20] = 20, 124 [RATE_INFO_BW_40] = 40, 125 [RATE_INFO_BW_80] = 80, 126 [RATE_INFO_BW_160] = 160, 127 [RATE_INFO_BW_320] = 320, 128 }; 129 130 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 131 { 132 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 133 return rtw89_rate_info_bw_to_mhz_map[bw]; 134 135 return 0; 136 } 137 138 static ssize_t rtw89_debugfs_file_read_helper(struct wiphy *wiphy, struct file *file, 139 char *buf, size_t bufsz, void *data) 140 { 141 struct rtw89_debugfs_priv *debugfs_priv = data; 142 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 143 ssize_t n; 144 145 n = debugfs_priv->cb_read(rtwdev, debugfs_priv, buf, bufsz); 146 rtw89_might_trailing_ellipsis(buf, bufsz, n); 147 148 return n; 149 } 150 151 static ssize_t rtw89_debugfs_file_read(struct file *file, char __user *userbuf, 152 size_t count, loff_t *ppos) 153 { 154 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 155 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 156 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 157 size_t bufsz = opt->rsize ? opt->rsize : PAGE_SIZE; 158 char *buf; 159 ssize_t n; 160 161 if (!debugfs_priv->rbuf) 162 debugfs_priv->rbuf = devm_kzalloc(rtwdev->dev, bufsz, GFP_KERNEL); 163 164 buf = debugfs_priv->rbuf; 165 if (!buf) 166 return -ENOMEM; 167 168 if (*ppos) { 169 n = debugfs_priv->rused; 170 goto out; 171 } 172 173 if (opt->rlock) { 174 n = wiphy_locked_debugfs_read(rtwdev->hw->wiphy, file, buf, bufsz, 175 userbuf, count, ppos, 176 rtw89_debugfs_file_read_helper, 177 debugfs_priv); 178 debugfs_priv->rused = n; 179 180 return n; 181 } 182 183 n = rtw89_debugfs_file_read_helper(rtwdev->hw->wiphy, file, buf, bufsz, 184 debugfs_priv); 185 debugfs_priv->rused = n; 186 187 out: 188 return simple_read_from_buffer(userbuf, count, ppos, buf, n); 189 } 190 191 static ssize_t rtw89_debugfs_file_write_helper(struct wiphy *wiphy, struct file *file, 192 char *buf, size_t count, void *data) 193 { 194 struct rtw89_debugfs_priv *debugfs_priv = data; 195 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 196 197 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 198 } 199 200 static ssize_t rtw89_debugfs_file_write(struct file *file, 201 const char __user *userbuf, 202 size_t count, loff_t *loff) 203 { 204 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 205 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 206 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 207 char *buf __free(kfree) = kmalloc(count + 1, GFP_KERNEL); 208 ssize_t n; 209 210 if (!buf) 211 return -ENOMEM; 212 213 if (opt->wlock) { 214 n = wiphy_locked_debugfs_write(rtwdev->hw->wiphy, 215 file, buf, count + 1, 216 userbuf, count, 217 rtw89_debugfs_file_write_helper, 218 debugfs_priv); 219 return n; 220 } 221 222 if (copy_from_user(buf, userbuf, count)) 223 return -EFAULT; 224 225 buf[count] = '\0'; 226 227 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 228 } 229 230 static const struct debugfs_short_fops file_ops_single_r = { 231 .read = rtw89_debugfs_file_read, 232 .llseek = generic_file_llseek, 233 }; 234 235 static const struct debugfs_short_fops file_ops_common_rw = { 236 .read = rtw89_debugfs_file_read, 237 .write = rtw89_debugfs_file_write, 238 .llseek = generic_file_llseek, 239 }; 240 241 static const struct debugfs_short_fops file_ops_single_w = { 242 .write = rtw89_debugfs_file_write, 243 .llseek = generic_file_llseek, 244 }; 245 246 static ssize_t 247 rtw89_debug_priv_read_reg_select(struct rtw89_dev *rtwdev, 248 struct rtw89_debugfs_priv *debugfs_priv, 249 const char *buf, size_t count) 250 { 251 u32 addr, len; 252 int num; 253 254 num = sscanf(buf, "%x %x", &addr, &len); 255 if (num != 2) { 256 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 257 return -EINVAL; 258 } 259 260 debugfs_priv->read_reg.addr = addr; 261 debugfs_priv->read_reg.len = len; 262 263 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 264 265 return count; 266 } 267 268 static 269 ssize_t rtw89_debug_priv_read_reg_get(struct rtw89_dev *rtwdev, 270 struct rtw89_debugfs_priv *debugfs_priv, 271 char *buf, size_t bufsz) 272 { 273 char *p = buf, *end = buf + bufsz; 274 u32 addr, addr_end, data, k; 275 u32 len; 276 277 len = debugfs_priv->read_reg.len; 278 addr = debugfs_priv->read_reg.addr; 279 280 if (len > 4) 281 goto ndata; 282 283 switch (len) { 284 case 1: 285 data = rtw89_read8(rtwdev, addr); 286 break; 287 case 2: 288 data = rtw89_read16(rtwdev, addr); 289 break; 290 case 4: 291 data = rtw89_read32(rtwdev, addr); 292 break; 293 default: 294 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 295 return -EINVAL; 296 } 297 298 p += scnprintf(p, end - p, "get %d bytes at 0x%08x=0x%08x\n", len, 299 addr, data); 300 301 return p - buf; 302 303 ndata: 304 addr_end = addr + len; 305 306 for (; addr < addr_end; addr += 16) { 307 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + addr); 308 for (k = 0; k < 16; k += 4) { 309 data = rtw89_read32(rtwdev, addr + k); 310 p += scnprintf(p, end - p, "%08x ", data); 311 } 312 p += scnprintf(p, end - p, "\n"); 313 } 314 315 return p - buf; 316 } 317 318 static 319 ssize_t rtw89_debug_priv_write_reg_set(struct rtw89_dev *rtwdev, 320 struct rtw89_debugfs_priv *debugfs_priv, 321 const char *buf, size_t count) 322 { 323 u32 addr, val, len; 324 int num; 325 326 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 327 if (num != 3) { 328 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 329 return -EINVAL; 330 } 331 332 switch (len) { 333 case 1: 334 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 335 rtw89_write8(rtwdev, addr, (u8)val); 336 break; 337 case 2: 338 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 339 rtw89_write16(rtwdev, addr, (u16)val); 340 break; 341 case 4: 342 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 343 rtw89_write32(rtwdev, addr, (u32)val); 344 break; 345 default: 346 rtw89_info(rtwdev, "invalid read write len %d\n", len); 347 break; 348 } 349 350 return count; 351 } 352 353 static ssize_t 354 rtw89_debug_priv_read_rf_select(struct rtw89_dev *rtwdev, 355 struct rtw89_debugfs_priv *debugfs_priv, 356 const char *buf, size_t count) 357 { 358 u32 addr, mask; 359 u8 path; 360 int num; 361 362 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 363 if (num != 3) { 364 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 365 return -EINVAL; 366 } 367 368 if (path >= rtwdev->chip->rf_path_num) { 369 rtw89_info(rtwdev, "wrong rf path\n"); 370 return -EINVAL; 371 } 372 debugfs_priv->read_rf.addr = addr; 373 debugfs_priv->read_rf.mask = mask; 374 debugfs_priv->read_rf.path = path; 375 376 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 377 378 return count; 379 } 380 381 static 382 ssize_t rtw89_debug_priv_read_rf_get(struct rtw89_dev *rtwdev, 383 struct rtw89_debugfs_priv *debugfs_priv, 384 char *buf, size_t bufsz) 385 { 386 char *p = buf, *end = buf + bufsz; 387 u32 addr, data, mask; 388 u8 path; 389 390 addr = debugfs_priv->read_rf.addr; 391 mask = debugfs_priv->read_rf.mask; 392 path = debugfs_priv->read_rf.path; 393 394 data = rtw89_read_rf(rtwdev, path, addr, mask); 395 396 p += scnprintf(p, end - p, "path %d, rf register 0x%08x=0x%08x\n", 397 path, addr, data); 398 399 return p - buf; 400 } 401 402 static 403 ssize_t rtw89_debug_priv_write_rf_set(struct rtw89_dev *rtwdev, 404 struct rtw89_debugfs_priv *debugfs_priv, 405 const char *buf, size_t count) 406 { 407 u32 addr, val, mask; 408 u8 path; 409 int num; 410 411 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 412 if (num != 4) { 413 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 414 return -EINVAL; 415 } 416 417 if (path >= rtwdev->chip->rf_path_num) { 418 rtw89_info(rtwdev, "wrong rf path\n"); 419 return -EINVAL; 420 } 421 422 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 423 path, addr, val, mask); 424 rtw89_write_rf(rtwdev, path, addr, mask, val); 425 426 return count; 427 } 428 429 static 430 ssize_t rtw89_debug_priv_rf_reg_dump_get(struct rtw89_dev *rtwdev, 431 struct rtw89_debugfs_priv *debugfs_priv, 432 char *buf, size_t bufsz) 433 { 434 const struct rtw89_chip_info *chip = rtwdev->chip; 435 char *p = buf, *end = buf + bufsz; 436 u32 addr, offset, data; 437 u8 path; 438 439 for (path = 0; path < chip->rf_path_num; path++) { 440 p += scnprintf(p, end - p, "RF path %d:\n\n", path); 441 for (addr = 0; addr < 0x100; addr += 4) { 442 p += scnprintf(p, end - p, "0x%08x: ", addr); 443 for (offset = 0; offset < 4; offset++) { 444 data = rtw89_read_rf(rtwdev, path, 445 addr + offset, RFREG_MASK); 446 p += scnprintf(p, end - p, "0x%05x ", data); 447 } 448 p += scnprintf(p, end - p, "\n"); 449 } 450 p += scnprintf(p, end - p, "\n"); 451 } 452 453 return p - buf; 454 } 455 456 struct txpwr_ent { 457 bool nested; 458 union { 459 const char *txt; 460 const struct txpwr_ent *ptr; 461 }; 462 u8 len; 463 }; 464 465 struct txpwr_map { 466 const struct txpwr_ent *ent; 467 u8 size; 468 u32 addr_from; 469 u32 addr_to; 470 u32 addr_to_1ss; 471 }; 472 473 #define __GEN_TXPWR_ENT_NESTED(_e) \ 474 { .nested = true, .ptr = __txpwr_ent_##_e, \ 475 .len = ARRAY_SIZE(__txpwr_ent_##_e) } 476 477 #define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t } 478 479 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 480 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 481 482 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 483 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 484 485 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 486 { .len = 8, .txt = _t "\t- " \ 487 _e0 " " _e1 " " _e2 " " _e3 " " \ 488 _e4 " " _e5 " " _e6 " " _e7 } 489 490 static const struct txpwr_ent __txpwr_ent_byr_ax[] = { 491 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 492 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 493 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 494 /* 1NSS */ 495 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 496 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 497 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 498 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 499 /* 2NSS */ 500 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 501 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 502 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 503 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 504 }; 505 506 static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) == 507 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 508 509 static const struct txpwr_map __txpwr_map_byr_ax = { 510 .ent = __txpwr_ent_byr_ax, 511 .size = ARRAY_SIZE(__txpwr_ent_byr_ax), 512 .addr_from = R_AX_PWR_BY_RATE, 513 .addr_to = R_AX_PWR_BY_RATE_MAX, 514 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX, 515 }; 516 517 static const struct txpwr_ent __txpwr_ent_lmt_ax[] = { 518 /* 1TX */ 519 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 520 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 521 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 522 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 523 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 524 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 525 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 526 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 527 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 528 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 529 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 530 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 531 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 532 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 533 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 534 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 535 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 536 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 537 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 538 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 539 /* 2TX */ 540 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 541 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 542 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 543 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 544 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 545 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 546 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 547 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 548 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 549 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 550 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 551 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 552 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 553 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 554 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 555 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 556 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 557 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 558 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 559 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 560 }; 561 562 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) == 563 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 564 565 static const struct txpwr_map __txpwr_map_lmt_ax = { 566 .ent = __txpwr_ent_lmt_ax, 567 .size = ARRAY_SIZE(__txpwr_ent_lmt_ax), 568 .addr_from = R_AX_PWR_LMT, 569 .addr_to = R_AX_PWR_LMT_MAX, 570 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX, 571 }; 572 573 static const struct txpwr_ent __txpwr_ent_lmt_ru_ax[] = { 574 /* 1TX */ 575 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 576 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 577 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 578 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 579 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 580 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 581 /* 2TX */ 582 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 583 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 584 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 585 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 586 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 587 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 588 }; 589 590 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) == 591 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 592 593 static const struct txpwr_map __txpwr_map_lmt_ru_ax = { 594 .ent = __txpwr_ent_lmt_ru_ax, 595 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_ax), 596 .addr_from = R_AX_PWR_RU_LMT, 597 .addr_to = R_AX_PWR_RU_LMT_MAX, 598 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX, 599 }; 600 601 static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = { 602 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 603 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 604 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 605 __GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"), 606 __GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 607 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 608 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 609 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 610 __GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"), 611 __GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 612 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 613 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 614 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 615 __GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"), 616 __GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 617 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 618 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 619 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 620 __GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"), 621 __GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 622 }; 623 624 static const struct txpwr_ent __txpwr_ent_byr_be[] = { 625 __GEN_TXPWR_ENT0("BW20"), 626 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 627 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 628 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 629 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 630 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 631 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 632 633 __GEN_TXPWR_ENT0("BW40"), 634 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 635 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 636 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 637 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 638 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 639 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 640 641 /* there is no CCK section after BW80 */ 642 __GEN_TXPWR_ENT0("BW80"), 643 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 644 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 645 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 646 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 647 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 648 649 __GEN_TXPWR_ENT0("BW160"), 650 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 651 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 652 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 653 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 654 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 655 656 __GEN_TXPWR_ENT0("BW320"), 657 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 658 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 659 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 660 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 661 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 662 }; 663 664 static const struct txpwr_map __txpwr_map_byr_be = { 665 .ent = __txpwr_ent_byr_be, 666 .size = ARRAY_SIZE(__txpwr_ent_byr_be), 667 .addr_from = R_BE_PWR_BY_RATE, 668 .addr_to = R_BE_PWR_BY_RATE_MAX, 669 .addr_to_1ss = 0, /* not support */ 670 }; 671 672 static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = { 673 __GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"), 674 __GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"), 675 __GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"), 676 __GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"), 677 __GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"), 678 __GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"), 679 __GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"), 680 __GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"), 681 __GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"), 682 __GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"), 683 __GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"), 684 __GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"), 685 __GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"), 686 __GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"), 687 __GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"), 688 __GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"), 689 __GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"), 690 __GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"), 691 __GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"), 692 __GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"), 693 __GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"), 694 __GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"), 695 __GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"), 696 __GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"), 697 __GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"), 698 __GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"), 699 __GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"), 700 __GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"), 701 __GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"), 702 __GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"), 703 __GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"), 704 __GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"), 705 __GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"), 706 __GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"), 707 __GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"), 708 }; 709 710 static const struct txpwr_ent __txpwr_ent_lmt_be[] = { 711 __GEN_TXPWR_ENT0("1TX"), 712 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 713 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 714 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 715 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 716 717 __GEN_TXPWR_ENT0("2TX"), 718 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 719 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 720 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 721 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 722 }; 723 724 static const struct txpwr_map __txpwr_map_lmt_be = { 725 .ent = __txpwr_ent_lmt_be, 726 .size = ARRAY_SIZE(__txpwr_ent_lmt_be), 727 .addr_from = R_BE_PWR_LMT, 728 .addr_to = R_BE_PWR_LMT_MAX, 729 .addr_to_1ss = 0, /* not support */ 730 }; 731 732 static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = { 733 __GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 734 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 735 __GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 736 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 737 __GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 738 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 739 __GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 740 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 741 __GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 742 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 743 __GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 744 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 745 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 746 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 747 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 748 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 749 __GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 750 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 751 __GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 752 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 753 }; 754 755 static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = { 756 __GEN_TXPWR_ENT0("1TX"), 757 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 758 759 __GEN_TXPWR_ENT0("2TX"), 760 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 761 }; 762 763 static const struct txpwr_map __txpwr_map_lmt_ru_be = { 764 .ent = __txpwr_ent_lmt_ru_be, 765 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be), 766 .addr_from = R_BE_PWR_RU_LMT, 767 .addr_to = R_BE_PWR_RU_LMT_MAX, 768 .addr_to_1ss = 0, /* not support */ 769 }; 770 771 static const struct txpwr_ent __txpwr_ent_lmt_ru484_242_be[] = { 772 __GEN_TXPWR_ENT4("RU484_242 1TX ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 "), 773 __GEN_TXPWR_ENT4("RU484_242 2TX ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 "), 774 }; 775 776 static const struct txpwr_map __txpwr_map_lmt_ru484_242_be = { 777 .ent = __txpwr_ent_lmt_ru484_242_be, 778 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru484_242_be), 779 .addr_from = R_BE_TXAGC_MAX_1TX_RU484_242_0, 780 .addr_to = R_BE_TXAGC_MAX_1TX_RU484_242_0 + 4, 781 .addr_to_1ss = 0, /* not support */ 782 }; 783 784 static const struct txpwr_ent __txpwr_ent_lmt_ru996_484_be[] = { 785 __GEN_TXPWR_ENT2("RU996_484 1TX ", "IDX_0 ", "IDX_1 "), 786 __GEN_TXPWR_ENT2("RU996_484 2TX ", "IDX_0 ", "IDX_1 "), 787 }; 788 789 static const struct txpwr_map __txpwr_map_lmt_ru996_484_be = { 790 .ent = __txpwr_ent_lmt_ru996_484_be, 791 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru996_484_be), 792 .addr_from = R_BE_TXAGC_MAX_1TX_RU996_484_0, 793 .addr_to = R_BE_TXAGC_MAX_1TX_RU996_484_0, 794 .addr_to_1ss = 0, /* not support */ 795 }; 796 797 static const struct txpwr_ent __txpwr_ent_lmt_ru996_484_242_be[] = { 798 __GEN_TXPWR_ENT2("RU996_484_242 1TX ", "IDX_0 ", "IDX_1 "), 799 __GEN_TXPWR_ENT2("RU996_484_242 2TX ", "IDX_0 ", "IDX_1 "), 800 }; 801 802 static const struct txpwr_map __txpwr_map_lmt_ru996_484_242_be = { 803 .ent = __txpwr_ent_lmt_ru996_484_242_be, 804 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru996_484_242_be), 805 .addr_from = R_BE_TXAGC_MAX_1TX_RU996_484_242_0, 806 .addr_to = R_BE_TXAGC_MAX_1TX_RU996_484_242_0, 807 .addr_to_1ss = 0, /* not support */ 808 }; 809 810 static unsigned int 811 __print_txpwr_ent(char *buf, size_t bufsz, const struct txpwr_ent *ent, 812 const s8 *bufp, const unsigned int cur, unsigned int *ate) 813 { 814 char *p = buf, *end = buf + bufsz; 815 unsigned int cnt, i; 816 unsigned int eaten; 817 char *fmt; 818 819 if (ent->nested) { 820 for (cnt = 0, i = 0; i < ent->len; i++, cnt += eaten) 821 p += __print_txpwr_ent(p, end - p, ent->ptr + i, bufp, 822 cur + cnt, &eaten); 823 *ate = cnt; 824 goto out; 825 } 826 827 switch (ent->len) { 828 case 0: 829 p += scnprintf(p, end - p, "\t<< %s >>\n", ent->txt); 830 *ate = 0; 831 goto out; 832 case 2: 833 fmt = "%s\t| %3d, %3d,\t\tdBm\n"; 834 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 835 bufp[cur + 1]); 836 *ate = 2; 837 goto out; 838 case 4: 839 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 840 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 841 bufp[cur + 1], 842 bufp[cur + 2], bufp[cur + 3]); 843 *ate = 4; 844 goto out; 845 case 8: 846 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 847 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 848 bufp[cur + 1], 849 bufp[cur + 2], bufp[cur + 3], bufp[cur + 4], 850 bufp[cur + 5], bufp[cur + 6], bufp[cur + 7]); 851 *ate = 8; 852 goto out; 853 default: 854 return 0; 855 } 856 857 out: 858 return p - buf; 859 } 860 861 static ssize_t __print_txpwr_map(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 862 const struct txpwr_map *map) 863 { 864 u8 fct = rtwdev->chip->txpwr_factor_mac; 865 u8 path_num = rtwdev->chip->rf_path_num; 866 char *p = buf, *end = buf + bufsz; 867 unsigned int cur, i; 868 unsigned int eaten; 869 u32 max_valid_addr; 870 u32 val, addr; 871 s8 *bufp, tmp; 872 int ret; 873 874 if (path_num == 1) 875 max_valid_addr = map->addr_to_1ss; 876 else 877 max_valid_addr = map->addr_to; 878 879 if (max_valid_addr == 0) 880 return -EOPNOTSUPP; 881 882 bufp = vzalloc(map->addr_to - map->addr_from + 4); 883 if (!bufp) 884 return -ENOMEM; 885 886 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 887 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 888 if (ret) 889 val = MASKDWORD; 890 891 cur = addr - map->addr_from; 892 for (i = 0; i < 4; i++, val >>= 8) { 893 /* signed 7 bits, and reserved BIT(7) */ 894 tmp = sign_extend32(val, 6); 895 bufp[cur + i] = tmp >> fct; 896 } 897 } 898 899 for (cur = 0, i = 0; i < map->size; i++, cur += eaten) 900 p += __print_txpwr_ent(p, end - p, &map->ent[i], bufp, cur, &eaten); 901 902 vfree(bufp); 903 return p - buf; 904 } 905 906 static int __print_regd(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 907 const struct rtw89_chan *chan) 908 { 909 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 910 char *p = buf, *end = buf + bufsz; 911 u8 band = chan->band_type; 912 u8 regd = rtw89_regd_get(rtwdev, band); 913 914 p += scnprintf(p, end - p, "%s\n", rtw89_regd_get_string(regd)); 915 p += scnprintf(p, end - p, "\t(txpwr UK follow ETSI: %s)\n", 916 str_yes_no(regulatory->txpwr_uk_follow_etsi)); 917 918 return p - buf; 919 } 920 921 struct dbgfs_txpwr_table { 922 const struct txpwr_map *byr; 923 const struct txpwr_map *lmt; 924 const struct txpwr_map *lmt_ru; 925 const struct txpwr_map *lmt_ru484_242; 926 const struct txpwr_map *lmt_ru996_484; 927 const struct txpwr_map *lmt_ru996_484_242; 928 }; 929 930 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = { 931 .byr = &__txpwr_map_byr_ax, 932 .lmt = &__txpwr_map_lmt_ax, 933 .lmt_ru = &__txpwr_map_lmt_ru_ax, 934 }; 935 936 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = { 937 .byr = &__txpwr_map_byr_be, 938 .lmt = &__txpwr_map_lmt_be, 939 .lmt_ru = &__txpwr_map_lmt_ru_be, 940 .lmt_ru484_242 = &__txpwr_map_lmt_ru484_242_be, 941 .lmt_ru996_484 = &__txpwr_map_lmt_ru996_484_be, 942 .lmt_ru996_484_242 = &__txpwr_map_lmt_ru996_484_242_be, 943 }; 944 945 static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = { 946 [RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax, 947 [RTW89_CHIP_BE] = &dbgfs_txpwr_table_be, 948 }; 949 950 static 951 int rtw89_debug_priv_txpwr_table_get_regd(struct rtw89_dev *rtwdev, 952 char *buf, size_t bufsz, 953 const struct rtw89_chan *chan) 954 { 955 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 956 const struct rtw89_reg_6ghz_tpe *tpe6 = ®ulatory->reg_6ghz_tpe; 957 char *p = buf, *end = buf + bufsz; 958 959 p += scnprintf(p, end - p, "[Chanctx] band %u, ch %u, bw %u\n", 960 chan->band_type, chan->channel, chan->band_width); 961 962 p += scnprintf(p, end - p, "[Regulatory] "); 963 p += __print_regd(rtwdev, p, end - p, chan); 964 965 if (chan->band_type == RTW89_BAND_6G) { 966 p += scnprintf(p, end - p, "[reg6_pwr_type] %u\n", 967 regulatory->reg_6ghz_power); 968 969 if (tpe6->valid) 970 p += scnprintf(p, end - p, "[TPE] %d dBm\n", 971 tpe6->constraint); 972 } 973 974 return p - buf; 975 } 976 977 static 978 ssize_t rtw89_debug_priv_txpwr_table_get(struct rtw89_dev *rtwdev, 979 struct rtw89_debugfs_priv *debugfs_priv, 980 char *buf, size_t bufsz) 981 { 982 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 983 const struct rtw89_chip_info *chip = rtwdev->chip; 984 struct rtw89_hal *hal = &rtwdev->hal; 985 struct rtw89_sar_parm sar_parm = {}; 986 const struct dbgfs_txpwr_table *tbl; 987 const struct rtw89_chan *chan; 988 char *p = buf, *end = buf + bufsz; 989 ssize_t n; 990 991 lockdep_assert_wiphy(rtwdev->hw->wiphy); 992 993 rtw89_leave_ps_mode(rtwdev); 994 chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 995 sar_parm.center_freq = chan->freq; 996 997 p += rtw89_debug_priv_txpwr_table_get_regd(rtwdev, p, end - p, chan); 998 999 p += scnprintf(p, end - p, "[SAR]\n"); 1000 p += rtw89_print_sar(rtwdev, p, end - p, &sar_parm); 1001 1002 p += scnprintf(p, end - p, "[TAS]\n"); 1003 p += rtw89_print_tas(rtwdev, p, end - p); 1004 1005 p += scnprintf(p, end - p, "[DAG]\n"); 1006 p += rtw89_print_ant_gain(rtwdev, p, end - p, chan); 1007 1008 tbl = dbgfs_txpwr_tables[chip_gen]; 1009 if (!tbl) 1010 return -EOPNOTSUPP; 1011 1012 p += scnprintf(p, end - p, "\n[TX power byrate]\n"); 1013 n = __print_txpwr_map(rtwdev, p, end - p, tbl->byr); 1014 if (n < 0) 1015 return n; 1016 p += n; 1017 1018 p += scnprintf(p, end - p, "\n[TX power limit]\n"); 1019 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt); 1020 if (n < 0) 1021 return n; 1022 p += n; 1023 1024 p += scnprintf(p, end - p, "\n[TX power limit_ru]\n"); 1025 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru); 1026 if (n < 0) 1027 return n; 1028 p += n; 1029 1030 switch (chip_gen) { 1031 case RTW89_CHIP_AX: 1032 goto out; 1033 case RTW89_CHIP_BE: 1034 if (!(chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7090)) 1035 goto out; 1036 break; 1037 default: 1038 return -EOPNOTSUPP; 1039 } 1040 1041 p += scnprintf(p, end - p, "\n[TX power limit_large_mru]\n"); 1042 1043 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru484_242); 1044 if (n < 0) 1045 return n; 1046 p += n; 1047 1048 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru996_484); 1049 if (n < 0) 1050 return n; 1051 p += n; 1052 1053 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru996_484_242); 1054 if (n < 0) 1055 return n; 1056 p += n; 1057 1058 out: 1059 return p - buf; 1060 } 1061 1062 static ssize_t 1063 rtw89_debug_priv_mac_reg_dump_select(struct rtw89_dev *rtwdev, 1064 struct rtw89_debugfs_priv *debugfs_priv, 1065 const char *buf, size_t count) 1066 { 1067 const struct rtw89_chip_info *chip = rtwdev->chip; 1068 int sel; 1069 int ret; 1070 1071 ret = kstrtoint(buf, 0, &sel); 1072 if (ret) 1073 return ret; 1074 1075 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 1076 rtw89_info(rtwdev, "invalid args: %d\n", sel); 1077 return -EINVAL; 1078 } 1079 1080 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 1081 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 1082 chip->chip_id); 1083 return -EINVAL; 1084 } 1085 1086 debugfs_priv->cb_data = sel; 1087 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 1088 1089 return count; 1090 } 1091 1092 #define RTW89_MAC_PAGE_SIZE 0x100 1093 1094 static 1095 ssize_t rtw89_debug_priv_mac_reg_dump_get(struct rtw89_dev *rtwdev, 1096 struct rtw89_debugfs_priv *debugfs_priv, 1097 char *buf, size_t bufsz) 1098 { 1099 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 1100 char *p = buf, *end = buf + bufsz; 1101 u32 start, end_addr; 1102 u32 i, j, k, page; 1103 u32 val; 1104 1105 switch (reg_sel) { 1106 case RTW89_DBG_SEL_MAC_00: 1107 p += scnprintf(p, end - p, "Debug selected MAC page 0x00\n"); 1108 start = 0x000; 1109 end_addr = 0x014; 1110 break; 1111 case RTW89_DBG_SEL_MAC_30: 1112 p += scnprintf(p, end - p, "Debug selected MAC page 0x30\n"); 1113 start = 0x030; 1114 end_addr = 0x033; 1115 break; 1116 case RTW89_DBG_SEL_MAC_40: 1117 p += scnprintf(p, end - p, "Debug selected MAC page 0x40\n"); 1118 start = 0x040; 1119 end_addr = 0x07f; 1120 break; 1121 case RTW89_DBG_SEL_MAC_80: 1122 p += scnprintf(p, end - p, "Debug selected MAC page 0x80\n"); 1123 start = 0x080; 1124 end_addr = 0x09f; 1125 break; 1126 case RTW89_DBG_SEL_MAC_C0: 1127 p += scnprintf(p, end - p, "Debug selected MAC page 0xc0\n"); 1128 start = 0x0c0; 1129 end_addr = 0x0df; 1130 break; 1131 case RTW89_DBG_SEL_MAC_E0: 1132 p += scnprintf(p, end - p, "Debug selected MAC page 0xe0\n"); 1133 start = 0x0e0; 1134 end_addr = 0x0ff; 1135 break; 1136 case RTW89_DBG_SEL_BB: 1137 p += scnprintf(p, end - p, "Debug selected BB register\n"); 1138 start = 0x100; 1139 end_addr = 0x17f; 1140 break; 1141 case RTW89_DBG_SEL_IQK: 1142 p += scnprintf(p, end - p, "Debug selected IQK register\n"); 1143 start = 0x180; 1144 end_addr = 0x1bf; 1145 break; 1146 case RTW89_DBG_SEL_RFC: 1147 p += scnprintf(p, end - p, "Debug selected RFC register\n"); 1148 start = 0x1c0; 1149 end_addr = 0x1ff; 1150 break; 1151 default: 1152 p += scnprintf(p, end - p, "Selected invalid register page\n"); 1153 return -EINVAL; 1154 } 1155 1156 for (i = start; i <= end_addr; i++) { 1157 page = i << 8; 1158 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 1159 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + j); 1160 for (k = 0; k < 4; k++) { 1161 val = rtw89_read32(rtwdev, j + (k << 2)); 1162 p += scnprintf(p, end - p, "%08x ", val); 1163 } 1164 p += scnprintf(p, end - p, "\n"); 1165 } 1166 } 1167 1168 return p - buf; 1169 } 1170 1171 static ssize_t 1172 rtw89_debug_priv_mac_mem_dump_select(struct rtw89_dev *rtwdev, 1173 struct rtw89_debugfs_priv *debugfs_priv, 1174 const char *buf, size_t count) 1175 { 1176 u32 sel, start_addr, len; 1177 int num; 1178 1179 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 1180 if (num != 3) { 1181 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 1182 return -EINVAL; 1183 } 1184 1185 debugfs_priv->mac_mem.sel = sel; 1186 debugfs_priv->mac_mem.start = start_addr; 1187 debugfs_priv->mac_mem.len = len; 1188 1189 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 1190 sel, start_addr, len); 1191 1192 return count; 1193 } 1194 1195 static int rtw89_debug_dump_mac_mem(struct rtw89_dev *rtwdev, 1196 char *buf, size_t bufsz, 1197 u8 sel, u32 start_addr, u32 len) 1198 { 1199 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1200 u32 filter_model_addr = mac->filter_model_addr; 1201 u32 indir_access_addr = mac->indir_access_addr; 1202 u32 mem_page_size = mac->mem_page_size; 1203 u32 base_addr, start_page, residue; 1204 char *p = buf, *end = buf + bufsz; 1205 u32 i, j, pp, pages; 1206 u32 dump_len, remain; 1207 u32 val; 1208 1209 remain = len; 1210 pages = len / mem_page_size + 1; 1211 start_page = start_addr / mem_page_size; 1212 residue = start_addr % mem_page_size; 1213 base_addr = rtw89_mac_mem_base_addrs(rtwdev, sel); 1214 base_addr += start_page * mem_page_size; 1215 1216 for (pp = 0; pp < pages; pp++) { 1217 dump_len = min_t(u32, remain, mem_page_size); 1218 rtw89_write32(rtwdev, filter_model_addr, base_addr); 1219 for (i = indir_access_addr + residue; 1220 i < indir_access_addr + dump_len;) { 1221 p += scnprintf(p, end - p, "%08xh:", i); 1222 for (j = 0; 1223 j < 4 && i < indir_access_addr + dump_len; 1224 j++, i += 4) { 1225 val = rtw89_read32(rtwdev, i); 1226 p += scnprintf(p, end - p, " %08x", val); 1227 remain -= 4; 1228 } 1229 p += scnprintf(p, end - p, "\n"); 1230 } 1231 base_addr += mem_page_size; 1232 } 1233 1234 return p - buf; 1235 } 1236 1237 static ssize_t 1238 rtw89_debug_priv_mac_mem_dump_get(struct rtw89_dev *rtwdev, 1239 struct rtw89_debugfs_priv *debugfs_priv, 1240 char *buf, size_t bufsz) 1241 { 1242 char *p = buf, *end = buf + bufsz; 1243 bool grant_read = false; 1244 1245 lockdep_assert_wiphy(rtwdev->hw->wiphy); 1246 1247 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 1248 return -ENOENT; 1249 1250 if (rtwdev->chip->chip_id == RTL8852C) { 1251 switch (debugfs_priv->mac_mem.sel) { 1252 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 1253 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 1254 case RTW89_MAC_MEM_TXDATA_FIFO_0: 1255 case RTW89_MAC_MEM_TXDATA_FIFO_1: 1256 grant_read = true; 1257 break; 1258 default: 1259 break; 1260 } 1261 } 1262 1263 rtw89_leave_ps_mode(rtwdev); 1264 if (grant_read) 1265 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1266 p += rtw89_debug_dump_mac_mem(rtwdev, p, end - p, 1267 debugfs_priv->mac_mem.sel, 1268 debugfs_priv->mac_mem.start, 1269 debugfs_priv->mac_mem.len); 1270 if (grant_read) 1271 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1272 1273 return p - buf; 1274 } 1275 1276 static ssize_t 1277 rtw89_debug_priv_mac_dbg_port_dump_select(struct rtw89_dev *rtwdev, 1278 struct rtw89_debugfs_priv *debugfs_priv, 1279 const char *buf, size_t count) 1280 { 1281 int sel, set; 1282 int num; 1283 bool enable; 1284 1285 num = sscanf(buf, "%d %d", &sel, &set); 1286 if (num != 2) { 1287 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 1288 return -EINVAL; 1289 } 1290 1291 enable = set != 0; 1292 switch (sel) { 1293 case 0: 1294 debugfs_priv->dbgpkg_en.ss_dbg = enable; 1295 break; 1296 case 1: 1297 debugfs_priv->dbgpkg_en.dle_dbg = enable; 1298 break; 1299 case 2: 1300 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 1301 break; 1302 case 3: 1303 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 1304 break; 1305 case 4: 1306 debugfs_priv->dbgpkg_en.dbg_port = enable; 1307 break; 1308 default: 1309 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 1310 return -EINVAL; 1311 } 1312 1313 rtw89_info(rtwdev, "%s debug port dump %d\n", 1314 enable ? "Enable" : "Disable", sel); 1315 1316 return count; 1317 } 1318 1319 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 1320 char *buf, size_t bufsz) 1321 { 1322 return 0; 1323 } 1324 1325 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 1326 char *buf, size_t bufsz) 1327 { 1328 #define DLE_DFI_DUMP(__type, __target, __sel) \ 1329 ({ \ 1330 u32 __ctrl; \ 1331 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 1332 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 1333 u32 __data, __val32; \ 1334 int __ret; \ 1335 \ 1336 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 1337 DLE_DFI_TYPE_##__target) | \ 1338 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 1339 B_AX_WDE_DFI_ACTIVE; \ 1340 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 1341 __ret = read_poll_timeout(rtw89_read32, __val32, \ 1342 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 1343 1000, 50000, false, \ 1344 rtwdev, __reg_ctrl); \ 1345 if (__ret) { \ 1346 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 1347 #__type, #__target, __sel); \ 1348 return __ret; \ 1349 } \ 1350 \ 1351 __data = rtw89_read32(rtwdev, __reg_data); \ 1352 __data; \ 1353 }) 1354 1355 #define DLE_DFI_FREE_PAGE_DUMP(__p, __end, __type) \ 1356 ({ \ 1357 u32 __freepg, __pubpg; \ 1358 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 1359 \ 1360 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 1361 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 1362 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 1363 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 1364 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 1365 __p += scnprintf(__p, __end - __p, "[%s] freepg head: %d\n", \ 1366 #__type, __freepg_head); \ 1367 __p += scnprintf(__p, __end - __p, "[%s] freepg tail: %d\n", \ 1368 #__type, __freepg_tail); \ 1369 __p += scnprintf(__p, __end - __p, "[%s] pubpg num : %d\n", \ 1370 #__type, __pubpg_num); \ 1371 }) 1372 1373 #define case_QUOTA(__p, __end, __type, __id) \ 1374 case __type##_QTAID_##__id: \ 1375 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 1376 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 1377 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 1378 __p += scnprintf(__p, __end - __p, "[%s][%s] rsv_pgnum: %d\n", \ 1379 #__type, #__id, rsv_pgnum); \ 1380 __p += scnprintf(__p, __end - __p, "[%s][%s] use_pgnum: %d\n", \ 1381 #__type, #__id, use_pgnum); \ 1382 break 1383 char *p = buf, *end = buf + bufsz; 1384 u32 quota_id; 1385 u32 val32; 1386 u16 rsv_pgnum, use_pgnum; 1387 int ret; 1388 1389 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1390 if (ret) { 1391 p += scnprintf(p, end - p, "[DLE] : DMAC not enabled\n"); 1392 goto out; 1393 } 1394 1395 DLE_DFI_FREE_PAGE_DUMP(p, end, WDE); 1396 DLE_DFI_FREE_PAGE_DUMP(p, end, PLE); 1397 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 1398 switch (quota_id) { 1399 case_QUOTA(p, end, WDE, HOST_IF); 1400 case_QUOTA(p, end, WDE, WLAN_CPU); 1401 case_QUOTA(p, end, WDE, DATA_CPU); 1402 case_QUOTA(p, end, WDE, PKTIN); 1403 case_QUOTA(p, end, WDE, CPUIO); 1404 } 1405 } 1406 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 1407 switch (quota_id) { 1408 case_QUOTA(p, end, PLE, B0_TXPL); 1409 case_QUOTA(p, end, PLE, B1_TXPL); 1410 case_QUOTA(p, end, PLE, C2H); 1411 case_QUOTA(p, end, PLE, H2C); 1412 case_QUOTA(p, end, PLE, WLAN_CPU); 1413 case_QUOTA(p, end, PLE, MPDU); 1414 case_QUOTA(p, end, PLE, CMAC0_RX); 1415 case_QUOTA(p, end, PLE, CMAC1_RX); 1416 case_QUOTA(p, end, PLE, CMAC1_BBRPT); 1417 case_QUOTA(p, end, PLE, WDRLS); 1418 case_QUOTA(p, end, PLE, CPUIO); 1419 } 1420 } 1421 1422 out: 1423 return p - buf; 1424 1425 #undef case_QUOTA 1426 #undef DLE_DFI_DUMP 1427 #undef DLE_DFI_FREE_PAGE_DUMP 1428 } 1429 1430 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 1431 char *buf, size_t bufsz) 1432 { 1433 const struct rtw89_chip_info *chip = rtwdev->chip; 1434 char *p = buf, *end = buf + bufsz; 1435 u32 dmac_err; 1436 int i, ret; 1437 1438 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1439 if (ret) { 1440 p += scnprintf(p, end - p, "[DMAC] : DMAC not enabled\n"); 1441 goto out; 1442 } 1443 1444 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1445 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1446 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1447 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1448 1449 if (dmac_err) { 1450 p += scnprintf(p, end - p, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1451 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1452 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1453 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1454 if (chip->chip_id == RTL8852C) { 1455 p += scnprintf(p, end - p, 1456 "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1457 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1458 p += scnprintf(p, end - p, 1459 "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1460 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1461 p += scnprintf(p, end - p, 1462 "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1463 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1464 p += scnprintf(p, end - p, 1465 "R_AX_PLE_DBGERR_STS=0x%08x\n", 1466 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1467 } 1468 } 1469 1470 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1471 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1472 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1473 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1474 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1475 if (chip->chip_id == RTL8852C) 1476 p += scnprintf(p, end - p, 1477 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1478 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1479 else 1480 p += scnprintf(p, end - p, 1481 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1482 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1483 } 1484 1485 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1486 if (chip->chip_id == RTL8852C) { 1487 p += scnprintf(p, end - p, 1488 "R_AX_SEC_ERR_IMR=0x%08x\n", 1489 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1490 p += scnprintf(p, end - p, 1491 "R_AX_SEC_ERR_ISR=0x%08x\n", 1492 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1493 p += scnprintf(p, end - p, 1494 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1495 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1496 p += scnprintf(p, end - p, 1497 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1498 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1499 p += scnprintf(p, end - p, 1500 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1501 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1502 p += scnprintf(p, end - p, 1503 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1504 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1505 p += scnprintf(p, end - p, "R_AX_SEC_DEBUG1=0x%08x\n", 1506 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1507 p += scnprintf(p, end - p, 1508 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1509 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1510 p += scnprintf(p, end - p, 1511 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1512 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1513 1514 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1515 B_AX_DBG_SEL0, 0x8B); 1516 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1517 B_AX_DBG_SEL1, 0x8B); 1518 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1519 B_AX_SEL_0XC0_MASK, 1); 1520 for (i = 0; i < 0x10; i++) { 1521 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1522 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1523 p += scnprintf(p, end - p, 1524 "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1525 i, 1526 rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1527 } 1528 } else { 1529 p += scnprintf(p, end - p, 1530 "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1531 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1532 p += scnprintf(p, end - p, 1533 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1534 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1535 p += scnprintf(p, end - p, 1536 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1537 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1538 p += scnprintf(p, end - p, 1539 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1540 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1541 p += scnprintf(p, end - p, 1542 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1543 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1544 p += scnprintf(p, end - p, 1545 "R_AX_SEC_CAM_WDATA=0x%08x\n", 1546 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1547 p += scnprintf(p, end - p, 1548 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1549 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1550 p += scnprintf(p, end - p, 1551 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1552 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1553 p += scnprintf(p, end - p, 1554 "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1555 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1556 p += scnprintf(p, end - p, 1557 "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1558 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1559 } 1560 } 1561 1562 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1563 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1564 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1565 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1566 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1567 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1568 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1569 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1570 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1571 } 1572 1573 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1574 p += scnprintf(p, end - p, 1575 "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1576 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1577 p += scnprintf(p, end - p, 1578 "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1579 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1580 } 1581 1582 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1583 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1584 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1585 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1586 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1587 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1588 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1589 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1590 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1591 } 1592 1593 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1594 if (chip->chip_id == RTL8852C) { 1595 p += scnprintf(p, end - p, 1596 "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1597 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1598 p += scnprintf(p, end - p, 1599 "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1600 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1601 p += scnprintf(p, end - p, 1602 "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1603 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1604 p += scnprintf(p, end - p, 1605 "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1606 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1607 } else { 1608 p += scnprintf(p, end - p, 1609 "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1610 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1611 p += scnprintf(p, end - p, 1612 "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1613 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1614 } 1615 } 1616 1617 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1618 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1619 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1620 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1621 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1622 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1623 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1624 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1625 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1626 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1627 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1628 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1629 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1630 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1631 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1632 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1633 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1634 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1635 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1636 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1637 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1638 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1639 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1640 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1641 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1642 if (chip->chip_id == RTL8852C) { 1643 p += scnprintf(p, end - p, "R_AX_RX_CTRL0=0x%08x\n", 1644 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1645 p += scnprintf(p, end - p, "R_AX_RX_CTRL1=0x%08x\n", 1646 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1647 p += scnprintf(p, end - p, "R_AX_RX_CTRL2=0x%08x\n", 1648 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1649 } else { 1650 p += scnprintf(p, end - p, 1651 "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1652 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1653 p += scnprintf(p, end - p, 1654 "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1655 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1656 p += scnprintf(p, end - p, 1657 "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1658 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1659 } 1660 } 1661 1662 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1663 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1664 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1665 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1666 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1667 } 1668 1669 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1670 p += scnprintf(p, end - p, 1671 "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1672 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1673 p += scnprintf(p, end - p, 1674 "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1675 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1676 p += scnprintf(p, end - p, 1677 "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1678 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1679 p += scnprintf(p, end - p, 1680 "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1681 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1682 p += scnprintf(p, end - p, 1683 "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1684 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1685 p += scnprintf(p, end - p, 1686 "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1687 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1688 } 1689 1690 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1691 if (chip->chip_id == RTL8852C) { 1692 p += scnprintf(p, end - p, 1693 "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1694 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1695 p += scnprintf(p, end - p, 1696 "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1697 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1698 p += scnprintf(p, end - p, 1699 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1700 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1701 p += scnprintf(p, end - p, 1702 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1703 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1704 p += scnprintf(p, end - p, 1705 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1706 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1707 p += scnprintf(p, end - p, 1708 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1709 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1710 } else { 1711 p += scnprintf(p, end - p, 1712 "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1713 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1714 p += scnprintf(p, end - p, 1715 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1716 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1717 p += scnprintf(p, end - p, 1718 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1719 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1720 p += scnprintf(p, end - p, 1721 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1722 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1723 p += scnprintf(p, end - p, 1724 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1725 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1726 } 1727 } 1728 1729 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1730 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1731 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1732 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1733 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1734 } 1735 1736 out: 1737 return p - buf; 1738 } 1739 1740 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1741 char *buf, size_t bufsz, 1742 enum rtw89_mac_idx band) 1743 { 1744 const struct rtw89_chip_info *chip = rtwdev->chip; 1745 char *p = buf, *end = buf + bufsz; 1746 u32 offset = 0; 1747 u32 cmac_err; 1748 int ret; 1749 1750 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1751 if (ret) { 1752 if (band) 1753 p += scnprintf(p, end - p, 1754 "[CMAC] : CMAC1 not enabled\n"); 1755 else 1756 p += scnprintf(p, end - p, 1757 "[CMAC] : CMAC0 not enabled\n"); 1758 goto out; 1759 } 1760 1761 if (band) 1762 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1763 1764 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1765 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1766 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1767 p += scnprintf(p, end - p, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1768 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1769 p += scnprintf(p, end - p, "R_AX_CK_EN [%d]=0x%08x\n", band, 1770 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1771 1772 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1773 p += scnprintf(p, end - p, 1774 "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1775 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1776 p += scnprintf(p, end - p, 1777 "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1778 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1779 } 1780 1781 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1782 p += scnprintf(p, end - p, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", 1783 band, 1784 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1785 p += scnprintf(p, end - p, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", 1786 band, 1787 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1788 } 1789 1790 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1791 if (chip->chip_id == RTL8852C) { 1792 p += scnprintf(p, end - p, 1793 "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1794 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1795 p += scnprintf(p, end - p, 1796 "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", 1797 band, 1798 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1799 } else { 1800 p += scnprintf(p, end - p, 1801 "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1802 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1803 } 1804 } 1805 1806 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1807 if (chip->chip_id == RTL8852C) { 1808 p += scnprintf(p, end - p, 1809 "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", 1810 band, 1811 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1812 p += scnprintf(p, end - p, 1813 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1814 band, 1815 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1816 } else { 1817 p += scnprintf(p, end - p, 1818 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1819 band, 1820 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1821 } 1822 } 1823 1824 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1825 p += scnprintf(p, end - p, "R_AX_TXPWR_IMR [%d]=0x%08x\n", 1826 band, 1827 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1828 p += scnprintf(p, end - p, "R_AX_TXPWR_ISR [%d]=0x%08x\n", 1829 band, 1830 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1831 } 1832 1833 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1834 if (chip->chip_id == RTL8852C) { 1835 p += scnprintf(p, end - p, 1836 "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", 1837 band, 1838 rtw89_read32(rtwdev, 1839 R_AX_TRXPTCL_ERROR_INDICA + offset)); 1840 p += scnprintf(p, end - p, 1841 "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", 1842 band, 1843 rtw89_read32(rtwdev, 1844 R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1845 } else { 1846 p += scnprintf(p, end - p, 1847 "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", 1848 band, 1849 rtw89_read32(rtwdev, 1850 R_AX_TMAC_ERR_IMR_ISR + offset)); 1851 } 1852 p += scnprintf(p, end - p, 1853 "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1854 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1855 } 1856 1857 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1858 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1859 1860 out: 1861 return p - buf; 1862 } 1863 1864 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1865 char *buf, size_t bufsz) 1866 { 1867 char *p = buf, *end = buf + bufsz; 1868 1869 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_0); 1870 if (rtwdev->dbcc_en) 1871 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_1); 1872 1873 return p - buf; 1874 } 1875 1876 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1877 .sel_addr = R_AX_PTCL_DBG, 1878 .sel_byte = 1, 1879 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1880 .srt = 0x00, 1881 .end = 0x3F, 1882 .rd_addr = R_AX_PTCL_DBG_INFO, 1883 .rd_byte = 4, 1884 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1885 }; 1886 1887 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1888 .sel_addr = R_AX_PTCL_DBG_C1, 1889 .sel_byte = 1, 1890 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1891 .srt = 0x00, 1892 .end = 0x3F, 1893 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1894 .rd_byte = 4, 1895 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1896 }; 1897 1898 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1899 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1900 .sel_byte = 2, 1901 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1902 .srt = 0x0, 1903 .end = 0xD, 1904 .rd_addr = R_AX_DBG_PORT_SEL, 1905 .rd_byte = 4, 1906 .rd_msk = B_AX_DEBUG_ST_MASK 1907 }; 1908 1909 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1910 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1911 .sel_byte = 2, 1912 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1913 .srt = 0x0, 1914 .end = 0x5, 1915 .rd_addr = R_AX_DBG_PORT_SEL, 1916 .rd_byte = 4, 1917 .rd_msk = B_AX_DEBUG_ST_MASK 1918 }; 1919 1920 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1921 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1922 .sel_byte = 2, 1923 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1924 .srt = 0x0, 1925 .end = 0x9, 1926 .rd_addr = R_AX_DBG_PORT_SEL, 1927 .rd_byte = 4, 1928 .rd_msk = B_AX_DEBUG_ST_MASK 1929 }; 1930 1931 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1932 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1933 .sel_byte = 2, 1934 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1935 .srt = 0x0, 1936 .end = 0x3, 1937 .rd_addr = R_AX_DBG_PORT_SEL, 1938 .rd_byte = 4, 1939 .rd_msk = B_AX_DEBUG_ST_MASK 1940 }; 1941 1942 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1943 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1944 .sel_byte = 2, 1945 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1946 .srt = 0x0, 1947 .end = 0x1, 1948 .rd_addr = R_AX_DBG_PORT_SEL, 1949 .rd_byte = 4, 1950 .rd_msk = B_AX_DEBUG_ST_MASK 1951 }; 1952 1953 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1954 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1955 .sel_byte = 2, 1956 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1957 .srt = 0x0, 1958 .end = 0x0, 1959 .rd_addr = R_AX_DBG_PORT_SEL, 1960 .rd_byte = 4, 1961 .rd_msk = B_AX_DEBUG_ST_MASK 1962 }; 1963 1964 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1965 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1966 .sel_byte = 2, 1967 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1968 .srt = 0x0, 1969 .end = 0xB, 1970 .rd_addr = R_AX_DBG_PORT_SEL, 1971 .rd_byte = 4, 1972 .rd_msk = B_AX_DEBUG_ST_MASK 1973 }; 1974 1975 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1976 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1977 .sel_byte = 2, 1978 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1979 .srt = 0x0, 1980 .end = 0x4, 1981 .rd_addr = R_AX_DBG_PORT_SEL, 1982 .rd_byte = 4, 1983 .rd_msk = B_AX_DEBUG_ST_MASK 1984 }; 1985 1986 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1987 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1988 .sel_byte = 2, 1989 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1990 .srt = 0x0, 1991 .end = 0x8, 1992 .rd_addr = R_AX_DBG_PORT_SEL, 1993 .rd_byte = 4, 1994 .rd_msk = B_AX_DEBUG_ST_MASK 1995 }; 1996 1997 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1998 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1999 .sel_byte = 2, 2000 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2001 .srt = 0x0, 2002 .end = 0x7, 2003 .rd_addr = R_AX_DBG_PORT_SEL, 2004 .rd_byte = 4, 2005 .rd_msk = B_AX_DEBUG_ST_MASK 2006 }; 2007 2008 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 2009 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2010 .sel_byte = 2, 2011 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2012 .srt = 0x0, 2013 .end = 0x1, 2014 .rd_addr = R_AX_DBG_PORT_SEL, 2015 .rd_byte = 4, 2016 .rd_msk = B_AX_DEBUG_ST_MASK 2017 }; 2018 2019 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 2020 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2021 .sel_byte = 2, 2022 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2023 .srt = 0x0, 2024 .end = 0x3, 2025 .rd_addr = R_AX_DBG_PORT_SEL, 2026 .rd_byte = 4, 2027 .rd_msk = B_AX_DEBUG_ST_MASK 2028 }; 2029 2030 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 2031 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2032 .sel_byte = 2, 2033 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2034 .srt = 0x0, 2035 .end = 0x0, 2036 .rd_addr = R_AX_DBG_PORT_SEL, 2037 .rd_byte = 4, 2038 .rd_msk = B_AX_DEBUG_ST_MASK 2039 }; 2040 2041 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 2042 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2043 .sel_byte = 2, 2044 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2045 .srt = 0x0, 2046 .end = 0x8, 2047 .rd_addr = R_AX_DBG_PORT_SEL, 2048 .rd_byte = 4, 2049 .rd_msk = B_AX_DEBUG_ST_MASK 2050 }; 2051 2052 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 2053 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2054 .sel_byte = 2, 2055 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2056 .srt = 0x0, 2057 .end = 0x0, 2058 .rd_addr = R_AX_DBG_PORT_SEL, 2059 .rd_byte = 4, 2060 .rd_msk = B_AX_DEBUG_ST_MASK 2061 }; 2062 2063 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 2064 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2065 .sel_byte = 2, 2066 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2067 .srt = 0x0, 2068 .end = 0x6, 2069 .rd_addr = R_AX_DBG_PORT_SEL, 2070 .rd_byte = 4, 2071 .rd_msk = B_AX_DEBUG_ST_MASK 2072 }; 2073 2074 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 2075 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2076 .sel_byte = 2, 2077 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2078 .srt = 0x0, 2079 .end = 0x0, 2080 .rd_addr = R_AX_DBG_PORT_SEL, 2081 .rd_byte = 4, 2082 .rd_msk = B_AX_DEBUG_ST_MASK 2083 }; 2084 2085 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 2086 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2087 .sel_byte = 2, 2088 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2089 .srt = 0x0, 2090 .end = 0x0, 2091 .rd_addr = R_AX_DBG_PORT_SEL, 2092 .rd_byte = 4, 2093 .rd_msk = B_AX_DEBUG_ST_MASK 2094 }; 2095 2096 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 2097 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2098 .sel_byte = 1, 2099 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2100 .srt = 0x0, 2101 .end = 0x3, 2102 .rd_addr = R_AX_DBG_PORT_SEL, 2103 .rd_byte = 4, 2104 .rd_msk = B_AX_DEBUG_ST_MASK 2105 }; 2106 2107 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 2108 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2109 .sel_byte = 1, 2110 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2111 .srt = 0x0, 2112 .end = 0x6, 2113 .rd_addr = R_AX_DBG_PORT_SEL, 2114 .rd_byte = 4, 2115 .rd_msk = B_AX_DEBUG_ST_MASK 2116 }; 2117 2118 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 2119 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2120 .sel_byte = 1, 2121 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2122 .srt = 0x0, 2123 .end = 0x0, 2124 .rd_addr = R_AX_DBG_PORT_SEL, 2125 .rd_byte = 4, 2126 .rd_msk = B_AX_DEBUG_ST_MASK 2127 }; 2128 2129 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 2130 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2131 .sel_byte = 1, 2132 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2133 .srt = 0x8, 2134 .end = 0xE, 2135 .rd_addr = R_AX_DBG_PORT_SEL, 2136 .rd_byte = 4, 2137 .rd_msk = B_AX_DEBUG_ST_MASK 2138 }; 2139 2140 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 2141 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2142 .sel_byte = 1, 2143 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2144 .srt = 0x0, 2145 .end = 0x5, 2146 .rd_addr = R_AX_DBG_PORT_SEL, 2147 .rd_byte = 4, 2148 .rd_msk = B_AX_DEBUG_ST_MASK 2149 }; 2150 2151 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 2152 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2153 .sel_byte = 1, 2154 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2155 .srt = 0x0, 2156 .end = 0x6, 2157 .rd_addr = R_AX_DBG_PORT_SEL, 2158 .rd_byte = 4, 2159 .rd_msk = B_AX_DEBUG_ST_MASK 2160 }; 2161 2162 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 2163 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2164 .sel_byte = 1, 2165 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2166 .srt = 0x0, 2167 .end = 0xF, 2168 .rd_addr = R_AX_DBG_PORT_SEL, 2169 .rd_byte = 4, 2170 .rd_msk = B_AX_DEBUG_ST_MASK 2171 }; 2172 2173 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 2174 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2175 .sel_byte = 1, 2176 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2177 .srt = 0x0, 2178 .end = 0x9, 2179 .rd_addr = R_AX_DBG_PORT_SEL, 2180 .rd_byte = 4, 2181 .rd_msk = B_AX_DEBUG_ST_MASK 2182 }; 2183 2184 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 2185 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2186 .sel_byte = 1, 2187 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2188 .srt = 0x0, 2189 .end = 0x3, 2190 .rd_addr = R_AX_DBG_PORT_SEL, 2191 .rd_byte = 4, 2192 .rd_msk = B_AX_DEBUG_ST_MASK 2193 }; 2194 2195 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 2196 .sel_addr = R_AX_SCH_DBG_SEL, 2197 .sel_byte = 1, 2198 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2199 .srt = 0x00, 2200 .end = 0x2F, 2201 .rd_addr = R_AX_SCH_DBG, 2202 .rd_byte = 4, 2203 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2204 }; 2205 2206 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 2207 .sel_addr = R_AX_SCH_DBG_SEL_C1, 2208 .sel_byte = 1, 2209 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2210 .srt = 0x00, 2211 .end = 0x2F, 2212 .rd_addr = R_AX_SCH_DBG_C1, 2213 .rd_byte = 4, 2214 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2215 }; 2216 2217 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 2218 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 2219 .sel_byte = 1, 2220 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2221 .srt = 0x00, 2222 .end = 0x19, 2223 .rd_addr = R_AX_DBG_PORT_SEL, 2224 .rd_byte = 4, 2225 .rd_msk = B_AX_DEBUG_ST_MASK 2226 }; 2227 2228 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 2229 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 2230 .sel_byte = 1, 2231 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2232 .srt = 0x00, 2233 .end = 0x19, 2234 .rd_addr = R_AX_DBG_PORT_SEL, 2235 .rd_byte = 4, 2236 .rd_msk = B_AX_DEBUG_ST_MASK 2237 }; 2238 2239 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 2240 .sel_addr = R_AX_RX_DEBUG_SELECT, 2241 .sel_byte = 1, 2242 .sel_msk = B_AX_DEBUG_SEL_MASK, 2243 .srt = 0x00, 2244 .end = 0x58, 2245 .rd_addr = R_AX_DBG_PORT_SEL, 2246 .rd_byte = 4, 2247 .rd_msk = B_AX_DEBUG_ST_MASK 2248 }; 2249 2250 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 2251 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 2252 .sel_byte = 1, 2253 .sel_msk = B_AX_DEBUG_SEL_MASK, 2254 .srt = 0x00, 2255 .end = 0x58, 2256 .rd_addr = R_AX_DBG_PORT_SEL, 2257 .rd_byte = 4, 2258 .rd_msk = B_AX_DEBUG_ST_MASK 2259 }; 2260 2261 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 2262 .sel_addr = R_AX_RX_STATE_MONITOR, 2263 .sel_byte = 1, 2264 .sel_msk = B_AX_STATE_SEL_MASK, 2265 .srt = 0x00, 2266 .end = 0x17, 2267 .rd_addr = R_AX_RX_STATE_MONITOR, 2268 .rd_byte = 4, 2269 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2270 }; 2271 2272 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 2273 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 2274 .sel_byte = 1, 2275 .sel_msk = B_AX_STATE_SEL_MASK, 2276 .srt = 0x00, 2277 .end = 0x17, 2278 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 2279 .rd_byte = 4, 2280 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2281 }; 2282 2283 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 2284 .sel_addr = R_AX_RMAC_PLCP_MON, 2285 .sel_byte = 4, 2286 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2287 .srt = 0x0, 2288 .end = 0xF, 2289 .rd_addr = R_AX_RMAC_PLCP_MON, 2290 .rd_byte = 4, 2291 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2292 }; 2293 2294 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 2295 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 2296 .sel_byte = 4, 2297 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2298 .srt = 0x0, 2299 .end = 0xF, 2300 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 2301 .rd_byte = 4, 2302 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2303 }; 2304 2305 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 2306 .sel_addr = R_AX_DBGSEL_TRXPTCL, 2307 .sel_byte = 1, 2308 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2309 .srt = 0x08, 2310 .end = 0x10, 2311 .rd_addr = R_AX_DBG_PORT_SEL, 2312 .rd_byte = 4, 2313 .rd_msk = B_AX_DEBUG_ST_MASK 2314 }; 2315 2316 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 2317 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 2318 .sel_byte = 1, 2319 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2320 .srt = 0x08, 2321 .end = 0x10, 2322 .rd_addr = R_AX_DBG_PORT_SEL, 2323 .rd_byte = 4, 2324 .rd_msk = B_AX_DEBUG_ST_MASK 2325 }; 2326 2327 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 2328 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2329 .sel_byte = 1, 2330 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2331 .srt = 0x00, 2332 .end = 0x07, 2333 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 2334 .rd_byte = 4, 2335 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2336 }; 2337 2338 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 2339 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2340 .sel_byte = 1, 2341 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2342 .srt = 0x00, 2343 .end = 0x07, 2344 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 2345 .rd_byte = 4, 2346 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2347 }; 2348 2349 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 2350 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2351 .sel_byte = 1, 2352 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2353 .srt = 0x00, 2354 .end = 0x07, 2355 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 2356 .rd_byte = 4, 2357 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2358 }; 2359 2360 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 2361 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2362 .sel_byte = 1, 2363 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2364 .srt = 0x00, 2365 .end = 0x07, 2366 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 2367 .rd_byte = 4, 2368 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2369 }; 2370 2371 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 2372 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2373 .sel_byte = 1, 2374 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2375 .srt = 0x00, 2376 .end = 0x04, 2377 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 2378 .rd_byte = 4, 2379 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2380 }; 2381 2382 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 2383 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2384 .sel_byte = 1, 2385 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2386 .srt = 0x00, 2387 .end = 0x04, 2388 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 2389 .rd_byte = 4, 2390 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2391 }; 2392 2393 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 2394 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2395 .sel_byte = 1, 2396 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2397 .srt = 0x00, 2398 .end = 0x04, 2399 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 2400 .rd_byte = 4, 2401 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2402 }; 2403 2404 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 2405 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2406 .sel_byte = 1, 2407 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2408 .srt = 0x00, 2409 .end = 0x04, 2410 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 2411 .rd_byte = 4, 2412 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2413 }; 2414 2415 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 2416 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2417 .sel_byte = 4, 2418 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2419 .srt = 0x80000000, 2420 .end = 0x80000001, 2421 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2422 .rd_byte = 4, 2423 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2424 }; 2425 2426 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 2427 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2428 .sel_byte = 4, 2429 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2430 .srt = 0x80010000, 2431 .end = 0x80010004, 2432 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2433 .rd_byte = 4, 2434 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2435 }; 2436 2437 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 2438 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2439 .sel_byte = 4, 2440 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2441 .srt = 0x80020000, 2442 .end = 0x80020FFF, 2443 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2444 .rd_byte = 4, 2445 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2446 }; 2447 2448 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 2449 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2450 .sel_byte = 4, 2451 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2452 .srt = 0x80030000, 2453 .end = 0x80030FFF, 2454 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2455 .rd_byte = 4, 2456 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2457 }; 2458 2459 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 2460 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2461 .sel_byte = 4, 2462 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2463 .srt = 0x80040000, 2464 .end = 0x80040FFF, 2465 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2466 .rd_byte = 4, 2467 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2468 }; 2469 2470 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 2471 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2472 .sel_byte = 4, 2473 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2474 .srt = 0x80050000, 2475 .end = 0x80050FFF, 2476 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2477 .rd_byte = 4, 2478 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2479 }; 2480 2481 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 2482 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2483 .sel_byte = 4, 2484 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2485 .srt = 0x80060000, 2486 .end = 0x80060453, 2487 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2488 .rd_byte = 4, 2489 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2490 }; 2491 2492 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 2493 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2494 .sel_byte = 4, 2495 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2496 .srt = 0x80070000, 2497 .end = 0x80070011, 2498 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2499 .rd_byte = 4, 2500 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2501 }; 2502 2503 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 2504 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2505 .sel_byte = 4, 2506 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2507 .srt = 0x80000000, 2508 .end = 0x80000001, 2509 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2510 .rd_byte = 4, 2511 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2512 }; 2513 2514 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 2515 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2516 .sel_byte = 4, 2517 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2518 .srt = 0x80010000, 2519 .end = 0x8001000A, 2520 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2521 .rd_byte = 4, 2522 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2523 }; 2524 2525 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2526 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2527 .sel_byte = 4, 2528 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2529 .srt = 0x80020000, 2530 .end = 0x80020DBF, 2531 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2532 .rd_byte = 4, 2533 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2534 }; 2535 2536 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2537 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2538 .sel_byte = 4, 2539 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2540 .srt = 0x80030000, 2541 .end = 0x80030DBF, 2542 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2543 .rd_byte = 4, 2544 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2545 }; 2546 2547 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2548 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2549 .sel_byte = 4, 2550 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2551 .srt = 0x80040000, 2552 .end = 0x80040DBF, 2553 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2554 .rd_byte = 4, 2555 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2556 }; 2557 2558 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2559 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2560 .sel_byte = 4, 2561 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2562 .srt = 0x80050000, 2563 .end = 0x80050DBF, 2564 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2565 .rd_byte = 4, 2566 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2567 }; 2568 2569 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2570 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2571 .sel_byte = 4, 2572 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2573 .srt = 0x80060000, 2574 .end = 0x80060041, 2575 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2576 .rd_byte = 4, 2577 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2578 }; 2579 2580 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2581 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2582 .sel_byte = 4, 2583 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2584 .srt = 0x80070000, 2585 .end = 0x80070001, 2586 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2587 .rd_byte = 4, 2588 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2589 }; 2590 2591 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2592 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2593 .sel_byte = 4, 2594 .sel_msk = B_AX_DFI_DATA_MASK, 2595 .srt = 0x80000000, 2596 .end = 0x8000017f, 2597 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2598 .rd_byte = 4, 2599 .rd_msk = B_AX_DFI_DATA_MASK 2600 }; 2601 2602 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2603 .sel_addr = R_AX_PCIE_DBG_CTRL, 2604 .sel_byte = 2, 2605 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2606 .srt = 0x00, 2607 .end = 0x03, 2608 .rd_addr = R_AX_DBG_PORT_SEL, 2609 .rd_byte = 4, 2610 .rd_msk = B_AX_DEBUG_ST_MASK 2611 }; 2612 2613 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2614 .sel_addr = R_AX_PCIE_DBG_CTRL, 2615 .sel_byte = 2, 2616 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2617 .srt = 0x00, 2618 .end = 0x04, 2619 .rd_addr = R_AX_DBG_PORT_SEL, 2620 .rd_byte = 4, 2621 .rd_msk = B_AX_DEBUG_ST_MASK 2622 }; 2623 2624 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2625 .sel_addr = R_AX_PCIE_DBG_CTRL, 2626 .sel_byte = 2, 2627 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2628 .srt = 0x00, 2629 .end = 0x01, 2630 .rd_addr = R_AX_DBG_PORT_SEL, 2631 .rd_byte = 4, 2632 .rd_msk = B_AX_DEBUG_ST_MASK 2633 }; 2634 2635 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2636 .sel_addr = R_AX_PCIE_DBG_CTRL, 2637 .sel_byte = 2, 2638 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2639 .srt = 0x00, 2640 .end = 0x05, 2641 .rd_addr = R_AX_DBG_PORT_SEL, 2642 .rd_byte = 4, 2643 .rd_msk = B_AX_DEBUG_ST_MASK 2644 }; 2645 2646 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2647 .sel_addr = R_AX_PCIE_DBG_CTRL, 2648 .sel_byte = 2, 2649 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2650 .srt = 0x00, 2651 .end = 0x05, 2652 .rd_addr = R_AX_DBG_PORT_SEL, 2653 .rd_byte = 4, 2654 .rd_msk = B_AX_DEBUG_ST_MASK 2655 }; 2656 2657 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2658 .sel_addr = R_AX_PCIE_DBG_CTRL, 2659 .sel_byte = 2, 2660 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2661 .srt = 0x00, 2662 .end = 0x06, 2663 .rd_addr = R_AX_DBG_PORT_SEL, 2664 .rd_byte = 4, 2665 .rd_msk = B_AX_DEBUG_ST_MASK 2666 }; 2667 2668 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2669 .sel_addr = R_AX_DBG_CTRL, 2670 .sel_byte = 1, 2671 .sel_msk = B_AX_DBG_SEL0, 2672 .srt = 0x34, 2673 .end = 0x3C, 2674 .rd_addr = R_AX_DBG_PORT_SEL, 2675 .rd_byte = 4, 2676 .rd_msk = B_AX_DEBUG_ST_MASK 2677 }; 2678 2679 static int 2680 rtw89_debug_mac_dbg_port_sel(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 2681 u32 sel, const struct rtw89_mac_dbg_port_info **ppinfo) 2682 { 2683 const struct rtw89_mac_dbg_port_info *info = NULL; 2684 char *p = buf, *end = buf + bufsz; 2685 u32 index; 2686 u32 val32; 2687 u16 val16; 2688 u8 val8; 2689 2690 switch (sel) { 2691 case RTW89_DBG_PORT_SEL_PTCL_C0: 2692 info = &dbg_port_ptcl_c0; 2693 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2694 val16 |= B_AX_PTCL_DBG_EN; 2695 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2696 p += scnprintf(p, end - p, "Enable PTCL C0 dbgport.\n"); 2697 break; 2698 case RTW89_DBG_PORT_SEL_PTCL_C1: 2699 info = &dbg_port_ptcl_c1; 2700 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2701 val16 |= B_AX_PTCL_DBG_EN; 2702 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2703 p += scnprintf(p, end - p, "Enable PTCL C1 dbgport.\n"); 2704 break; 2705 case RTW89_DBG_PORT_SEL_SCH_C0: 2706 info = &dbg_port_sch_c0; 2707 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2708 val32 |= B_AX_SCH_DBG_EN; 2709 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2710 p += scnprintf(p, end - p, "Enable SCH C0 dbgport.\n"); 2711 break; 2712 case RTW89_DBG_PORT_SEL_SCH_C1: 2713 info = &dbg_port_sch_c1; 2714 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2715 val32 |= B_AX_SCH_DBG_EN; 2716 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2717 p += scnprintf(p, end - p, "Enable SCH C1 dbgport.\n"); 2718 break; 2719 case RTW89_DBG_PORT_SEL_TMAC_C0: 2720 info = &dbg_port_tmac_c0; 2721 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2722 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2723 B_AX_DBGSEL_TRXPTCL_MASK); 2724 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2725 2726 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2727 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2728 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2729 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2730 2731 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2732 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2733 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2734 p += scnprintf(p, end - p, "Enable TMAC C0 dbgport.\n"); 2735 break; 2736 case RTW89_DBG_PORT_SEL_TMAC_C1: 2737 info = &dbg_port_tmac_c1; 2738 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2739 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2740 B_AX_DBGSEL_TRXPTCL_MASK); 2741 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2742 2743 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2744 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2745 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2746 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2747 2748 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2749 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2750 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2751 p += scnprintf(p, end - p, "Enable TMAC C1 dbgport.\n"); 2752 break; 2753 case RTW89_DBG_PORT_SEL_RMAC_C0: 2754 info = &dbg_port_rmac_c0; 2755 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2756 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2757 B_AX_DBGSEL_TRXPTCL_MASK); 2758 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2759 2760 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2761 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2762 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2763 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2764 2765 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2766 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2767 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2768 2769 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2770 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2771 B_AX_DBGSEL_TRXPTCL_MASK); 2772 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2773 p += scnprintf(p, end - p, "Enable RMAC C0 dbgport.\n"); 2774 break; 2775 case RTW89_DBG_PORT_SEL_RMAC_C1: 2776 info = &dbg_port_rmac_c1; 2777 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2778 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2779 B_AX_DBGSEL_TRXPTCL_MASK); 2780 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2781 2782 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2783 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2784 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2785 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2786 2787 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2788 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2789 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2790 2791 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2792 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2793 B_AX_DBGSEL_TRXPTCL_MASK); 2794 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2795 p += scnprintf(p, end - p, "Enable RMAC C1 dbgport.\n"); 2796 break; 2797 case RTW89_DBG_PORT_SEL_RMACST_C0: 2798 info = &dbg_port_rmacst_c0; 2799 p += scnprintf(p, end - p, "Enable RMAC state C0 dbgport.\n"); 2800 break; 2801 case RTW89_DBG_PORT_SEL_RMACST_C1: 2802 info = &dbg_port_rmacst_c1; 2803 p += scnprintf(p, end - p, "Enable RMAC state C1 dbgport.\n"); 2804 break; 2805 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2806 info = &dbg_port_rmac_plcp_c0; 2807 p += scnprintf(p, end - p, "Enable RMAC PLCP C0 dbgport.\n"); 2808 break; 2809 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2810 info = &dbg_port_rmac_plcp_c1; 2811 p += scnprintf(p, end - p, "Enable RMAC PLCP C1 dbgport.\n"); 2812 break; 2813 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2814 info = &dbg_port_trxptcl_c0; 2815 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2816 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2817 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2818 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2819 2820 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2821 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2822 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2823 p += scnprintf(p, end - p, "Enable TRXPTCL C0 dbgport.\n"); 2824 break; 2825 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2826 info = &dbg_port_trxptcl_c1; 2827 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2828 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2829 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2830 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2831 2832 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2833 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2834 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2835 p += scnprintf(p, end - p, "Enable TRXPTCL C1 dbgport.\n"); 2836 break; 2837 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2838 info = &dbg_port_tx_infol_c0; 2839 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2840 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2841 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2842 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2843 break; 2844 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2845 info = &dbg_port_tx_infoh_c0; 2846 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2847 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2848 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2849 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2850 break; 2851 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2852 info = &dbg_port_tx_infol_c1; 2853 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2854 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2855 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2856 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2857 break; 2858 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2859 info = &dbg_port_tx_infoh_c1; 2860 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2861 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2862 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2863 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2864 break; 2865 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2866 info = &dbg_port_txtf_infol_c0; 2867 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2868 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2869 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2870 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2871 break; 2872 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2873 info = &dbg_port_txtf_infoh_c0; 2874 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2875 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2876 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2877 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2878 break; 2879 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2880 info = &dbg_port_txtf_infol_c1; 2881 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2882 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2883 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2884 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2885 break; 2886 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2887 info = &dbg_port_txtf_infoh_c1; 2888 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2889 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2890 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2891 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2892 break; 2893 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2894 info = &dbg_port_wde_bufmgn_freepg; 2895 p += scnprintf(p, end - p, "Enable wde bufmgn freepg dump.\n"); 2896 break; 2897 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2898 info = &dbg_port_wde_bufmgn_quota; 2899 p += scnprintf(p, end - p, "Enable wde bufmgn quota dump.\n"); 2900 break; 2901 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2902 info = &dbg_port_wde_bufmgn_pagellt; 2903 p += scnprintf(p, end - p, 2904 "Enable wde bufmgn pagellt dump.\n"); 2905 break; 2906 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2907 info = &dbg_port_wde_bufmgn_pktinfo; 2908 p += scnprintf(p, end - p, 2909 "Enable wde bufmgn pktinfo dump.\n"); 2910 break; 2911 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2912 info = &dbg_port_wde_quemgn_prepkt; 2913 p += scnprintf(p, end - p, "Enable wde quemgn prepkt dump.\n"); 2914 break; 2915 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2916 info = &dbg_port_wde_quemgn_nxtpkt; 2917 p += scnprintf(p, end - p, "Enable wde quemgn nxtpkt dump.\n"); 2918 break; 2919 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2920 info = &dbg_port_wde_quemgn_qlnktbl; 2921 p += scnprintf(p, end - p, 2922 "Enable wde quemgn qlnktbl dump.\n"); 2923 break; 2924 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2925 info = &dbg_port_wde_quemgn_qempty; 2926 p += scnprintf(p, end - p, "Enable wde quemgn qempty dump.\n"); 2927 break; 2928 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2929 info = &dbg_port_ple_bufmgn_freepg; 2930 p += scnprintf(p, end - p, "Enable ple bufmgn freepg dump.\n"); 2931 break; 2932 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2933 info = &dbg_port_ple_bufmgn_quota; 2934 p += scnprintf(p, end - p, "Enable ple bufmgn quota dump.\n"); 2935 break; 2936 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2937 info = &dbg_port_ple_bufmgn_pagellt; 2938 p += scnprintf(p, end - p, 2939 "Enable ple bufmgn pagellt dump.\n"); 2940 break; 2941 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2942 info = &dbg_port_ple_bufmgn_pktinfo; 2943 p += scnprintf(p, end - p, 2944 "Enable ple bufmgn pktinfo dump.\n"); 2945 break; 2946 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2947 info = &dbg_port_ple_quemgn_prepkt; 2948 p += scnprintf(p, end - p, "Enable ple quemgn prepkt dump.\n"); 2949 break; 2950 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2951 info = &dbg_port_ple_quemgn_nxtpkt; 2952 p += scnprintf(p, end - p, "Enable ple quemgn nxtpkt dump.\n"); 2953 break; 2954 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2955 info = &dbg_port_ple_quemgn_qlnktbl; 2956 p += scnprintf(p, end - p, 2957 "Enable ple quemgn qlnktbl dump.\n"); 2958 break; 2959 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2960 info = &dbg_port_ple_quemgn_qempty; 2961 p += scnprintf(p, end - p, "Enable ple quemgn qempty dump.\n"); 2962 break; 2963 case RTW89_DBG_PORT_SEL_PKTINFO: 2964 info = &dbg_port_pktinfo; 2965 p += scnprintf(p, end - p, "Enable pktinfo dump.\n"); 2966 break; 2967 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2968 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2969 B_AX_DBG_SEL0, 0x80); 2970 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2971 B_AX_SEL_0XC0_MASK, 1); 2972 fallthrough; 2973 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2974 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2975 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2976 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2977 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2978 info = &dbg_port_dspt_hdt_tx0_5; 2979 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2980 rtw89_write16_mask(rtwdev, info->sel_addr, 2981 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2982 rtw89_write16_mask(rtwdev, info->sel_addr, 2983 B_AX_DISPATCHER_CH_SEL_MASK, index); 2984 p += scnprintf(p, end - p, 2985 "Enable Dispatcher hdt tx%x dump.\n", index); 2986 break; 2987 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2988 info = &dbg_port_dspt_hdt_tx6; 2989 rtw89_write16_mask(rtwdev, info->sel_addr, 2990 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2991 rtw89_write16_mask(rtwdev, info->sel_addr, 2992 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2993 p += scnprintf(p, end - p, 2994 "Enable Dispatcher hdt tx6 dump.\n"); 2995 break; 2996 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2997 info = &dbg_port_dspt_hdt_tx7; 2998 rtw89_write16_mask(rtwdev, info->sel_addr, 2999 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 3000 rtw89_write16_mask(rtwdev, info->sel_addr, 3001 B_AX_DISPATCHER_CH_SEL_MASK, 7); 3002 p += scnprintf(p, end - p, 3003 "Enable Dispatcher hdt tx7 dump.\n"); 3004 break; 3005 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 3006 info = &dbg_port_dspt_hdt_tx8; 3007 rtw89_write16_mask(rtwdev, info->sel_addr, 3008 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 3009 rtw89_write16_mask(rtwdev, info->sel_addr, 3010 B_AX_DISPATCHER_CH_SEL_MASK, 8); 3011 p += scnprintf(p, end - p, 3012 "Enable Dispatcher hdt tx8 dump.\n"); 3013 break; 3014 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 3015 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 3016 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 3017 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 3018 info = &dbg_port_dspt_hdt_tx9_C; 3019 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 3020 rtw89_write16_mask(rtwdev, info->sel_addr, 3021 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 3022 rtw89_write16_mask(rtwdev, info->sel_addr, 3023 B_AX_DISPATCHER_CH_SEL_MASK, index); 3024 p += scnprintf(p, end - p, 3025 "Enable Dispatcher hdt tx%x dump.\n", index); 3026 break; 3027 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 3028 info = &dbg_port_dspt_hdt_txD; 3029 rtw89_write16_mask(rtwdev, info->sel_addr, 3030 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 3031 rtw89_write16_mask(rtwdev, info->sel_addr, 3032 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 3033 p += scnprintf(p, end - p, 3034 "Enable Dispatcher hdt txD dump.\n"); 3035 break; 3036 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 3037 info = &dbg_port_dspt_cdt_tx0; 3038 rtw89_write16_mask(rtwdev, info->sel_addr, 3039 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3040 rtw89_write16_mask(rtwdev, info->sel_addr, 3041 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3042 p += scnprintf(p, end - p, 3043 "Enable Dispatcher cdt tx0 dump.\n"); 3044 break; 3045 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 3046 info = &dbg_port_dspt_cdt_tx1; 3047 rtw89_write16_mask(rtwdev, info->sel_addr, 3048 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3049 rtw89_write16_mask(rtwdev, info->sel_addr, 3050 B_AX_DISPATCHER_CH_SEL_MASK, 1); 3051 p += scnprintf(p, end - p, 3052 "Enable Dispatcher cdt tx1 dump.\n"); 3053 break; 3054 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 3055 info = &dbg_port_dspt_cdt_tx3; 3056 rtw89_write16_mask(rtwdev, info->sel_addr, 3057 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3058 rtw89_write16_mask(rtwdev, info->sel_addr, 3059 B_AX_DISPATCHER_CH_SEL_MASK, 3); 3060 p += scnprintf(p, end - p, 3061 "Enable Dispatcher cdt tx3 dump.\n"); 3062 break; 3063 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 3064 info = &dbg_port_dspt_cdt_tx4; 3065 rtw89_write16_mask(rtwdev, info->sel_addr, 3066 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3067 rtw89_write16_mask(rtwdev, info->sel_addr, 3068 B_AX_DISPATCHER_CH_SEL_MASK, 4); 3069 p += scnprintf(p, end - p, 3070 "Enable Dispatcher cdt tx4 dump.\n"); 3071 break; 3072 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 3073 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 3074 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 3075 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 3076 info = &dbg_port_dspt_cdt_tx5_8; 3077 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 3078 rtw89_write16_mask(rtwdev, info->sel_addr, 3079 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3080 rtw89_write16_mask(rtwdev, info->sel_addr, 3081 B_AX_DISPATCHER_CH_SEL_MASK, index); 3082 p += scnprintf(p, end - p, 3083 "Enable Dispatcher cdt tx%x dump.\n", index); 3084 break; 3085 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 3086 info = &dbg_port_dspt_cdt_tx9; 3087 rtw89_write16_mask(rtwdev, info->sel_addr, 3088 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3089 rtw89_write16_mask(rtwdev, info->sel_addr, 3090 B_AX_DISPATCHER_CH_SEL_MASK, 9); 3091 p += scnprintf(p, end - p, 3092 "Enable Dispatcher cdt tx9 dump.\n"); 3093 break; 3094 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 3095 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 3096 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 3097 info = &dbg_port_dspt_cdt_txA_C; 3098 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 3099 rtw89_write16_mask(rtwdev, info->sel_addr, 3100 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3101 rtw89_write16_mask(rtwdev, info->sel_addr, 3102 B_AX_DISPATCHER_CH_SEL_MASK, index); 3103 p += scnprintf(p, end - p, 3104 "Enable Dispatcher cdt tx%x dump.\n", index); 3105 break; 3106 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 3107 info = &dbg_port_dspt_hdt_rx0; 3108 rtw89_write16_mask(rtwdev, info->sel_addr, 3109 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3110 rtw89_write16_mask(rtwdev, info->sel_addr, 3111 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3112 p += scnprintf(p, end - p, 3113 "Enable Dispatcher hdt rx0 dump.\n"); 3114 break; 3115 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 3116 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 3117 info = &dbg_port_dspt_hdt_rx1_2; 3118 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 3119 rtw89_write16_mask(rtwdev, info->sel_addr, 3120 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3121 rtw89_write16_mask(rtwdev, info->sel_addr, 3122 B_AX_DISPATCHER_CH_SEL_MASK, index); 3123 p += scnprintf(p, end - p, 3124 "Enable Dispatcher hdt rx%x dump.\n", index); 3125 break; 3126 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 3127 info = &dbg_port_dspt_hdt_rx3; 3128 rtw89_write16_mask(rtwdev, info->sel_addr, 3129 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3130 rtw89_write16_mask(rtwdev, info->sel_addr, 3131 B_AX_DISPATCHER_CH_SEL_MASK, 3); 3132 p += scnprintf(p, end - p, 3133 "Enable Dispatcher hdt rx3 dump.\n"); 3134 break; 3135 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 3136 info = &dbg_port_dspt_hdt_rx4; 3137 rtw89_write16_mask(rtwdev, info->sel_addr, 3138 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3139 rtw89_write16_mask(rtwdev, info->sel_addr, 3140 B_AX_DISPATCHER_CH_SEL_MASK, 4); 3141 p += scnprintf(p, end - p, 3142 "Enable Dispatcher hdt rx4 dump.\n"); 3143 break; 3144 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 3145 info = &dbg_port_dspt_hdt_rx5; 3146 rtw89_write16_mask(rtwdev, info->sel_addr, 3147 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3148 rtw89_write16_mask(rtwdev, info->sel_addr, 3149 B_AX_DISPATCHER_CH_SEL_MASK, 5); 3150 p += scnprintf(p, end - p, 3151 "Enable Dispatcher hdt rx5 dump.\n"); 3152 break; 3153 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 3154 info = &dbg_port_dspt_cdt_rx_p0_0; 3155 rtw89_write16_mask(rtwdev, info->sel_addr, 3156 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3157 rtw89_write16_mask(rtwdev, info->sel_addr, 3158 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3159 p += scnprintf(p, end - p, 3160 "Enable Dispatcher cdt rx part0 0 dump.\n"); 3161 break; 3162 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 3163 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 3164 info = &dbg_port_dspt_cdt_rx_p0_1; 3165 rtw89_write16_mask(rtwdev, info->sel_addr, 3166 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3167 rtw89_write16_mask(rtwdev, info->sel_addr, 3168 B_AX_DISPATCHER_CH_SEL_MASK, 1); 3169 p += scnprintf(p, end - p, 3170 "Enable Dispatcher cdt rx part0 1 dump.\n"); 3171 break; 3172 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 3173 info = &dbg_port_dspt_cdt_rx_p0_2; 3174 rtw89_write16_mask(rtwdev, info->sel_addr, 3175 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3176 rtw89_write16_mask(rtwdev, info->sel_addr, 3177 B_AX_DISPATCHER_CH_SEL_MASK, 2); 3178 p += scnprintf(p, end - p, 3179 "Enable Dispatcher cdt rx part0 2 dump.\n"); 3180 break; 3181 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 3182 info = &dbg_port_dspt_cdt_rx_p1; 3183 rtw89_write8_mask(rtwdev, info->sel_addr, 3184 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3185 p += scnprintf(p, end - p, 3186 "Enable Dispatcher cdt rx part1 dump.\n"); 3187 break; 3188 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 3189 info = &dbg_port_dspt_stf_ctrl; 3190 rtw89_write8_mask(rtwdev, info->sel_addr, 3191 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 3192 p += scnprintf(p, end - p, 3193 "Enable Dispatcher stf control dump.\n"); 3194 break; 3195 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 3196 info = &dbg_port_dspt_addr_ctrl; 3197 rtw89_write8_mask(rtwdev, info->sel_addr, 3198 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 3199 p += scnprintf(p, end - p, 3200 "Enable Dispatcher addr control dump.\n"); 3201 break; 3202 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 3203 info = &dbg_port_dspt_wde_intf; 3204 rtw89_write8_mask(rtwdev, info->sel_addr, 3205 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 3206 p += scnprintf(p, end - p, 3207 "Enable Dispatcher wde interface dump.\n"); 3208 break; 3209 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 3210 info = &dbg_port_dspt_ple_intf; 3211 rtw89_write8_mask(rtwdev, info->sel_addr, 3212 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 3213 p += scnprintf(p, end - p, 3214 "Enable Dispatcher ple interface dump.\n"); 3215 break; 3216 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 3217 info = &dbg_port_dspt_flow_ctrl; 3218 rtw89_write8_mask(rtwdev, info->sel_addr, 3219 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 3220 p += scnprintf(p, end - p, 3221 "Enable Dispatcher flow control dump.\n"); 3222 break; 3223 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 3224 info = &dbg_port_pcie_txdma; 3225 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3226 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 3227 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 3228 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3229 p += scnprintf(p, end - p, "Enable pcie txdma dump.\n"); 3230 break; 3231 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 3232 info = &dbg_port_pcie_rxdma; 3233 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3234 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 3235 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 3236 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3237 p += scnprintf(p, end - p, "Enable pcie rxdma dump.\n"); 3238 break; 3239 case RTW89_DBG_PORT_SEL_PCIE_CVT: 3240 info = &dbg_port_pcie_cvt; 3241 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3242 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 3243 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 3244 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3245 p += scnprintf(p, end - p, "Enable pcie cvt dump.\n"); 3246 break; 3247 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 3248 info = &dbg_port_pcie_cxpl; 3249 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3250 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 3251 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 3252 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3253 p += scnprintf(p, end - p, "Enable pcie cxpl dump.\n"); 3254 break; 3255 case RTW89_DBG_PORT_SEL_PCIE_IO: 3256 info = &dbg_port_pcie_io; 3257 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3258 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 3259 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 3260 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3261 p += scnprintf(p, end - p, "Enable pcie io dump.\n"); 3262 break; 3263 case RTW89_DBG_PORT_SEL_PCIE_MISC: 3264 info = &dbg_port_pcie_misc; 3265 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3266 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 3267 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 3268 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3269 p += scnprintf(p, end - p, "Enable pcie misc dump.\n"); 3270 break; 3271 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 3272 info = &dbg_port_pcie_misc2; 3273 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 3274 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 3275 B_AX_PCIE_DBG_SEL_MASK); 3276 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 3277 p += scnprintf(p, end - p, "Enable pcie misc2 dump.\n"); 3278 break; 3279 default: 3280 p += scnprintf(p, end - p, "Dbg port select err\n"); 3281 break; 3282 } 3283 3284 *ppinfo = info; 3285 3286 return p - buf; 3287 } 3288 3289 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 3290 { 3291 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 3292 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 3293 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 3294 return false; 3295 if (rtw89_is_rtl885xb(rtwdev) && 3296 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3297 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3298 return false; 3299 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3300 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 3301 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 3302 return false; 3303 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3304 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 3305 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 3306 return false; 3307 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 3308 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 3309 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 3310 return false; 3311 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 3312 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3313 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3314 return false; 3315 3316 return true; 3317 } 3318 3319 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 3320 char *buf, size_t bufsz, u32 sel) 3321 { 3322 const struct rtw89_mac_dbg_port_info *info = NULL; 3323 char *p = buf, *end = buf + bufsz; 3324 u32 val32; 3325 u16 val16; 3326 u8 val8; 3327 u32 i; 3328 3329 p += rtw89_debug_mac_dbg_port_sel(rtwdev, p, end - p, sel, &info); 3330 3331 if (!info) { 3332 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 3333 goto out; 3334 } 3335 3336 #define case_DBG_SEL(__sel) \ 3337 case RTW89_DBG_PORT_SEL_##__sel: \ 3338 p += scnprintf(p, end - p, "Dump debug port " #__sel ":\n"); \ 3339 break 3340 3341 switch (sel) { 3342 case_DBG_SEL(PTCL_C0); 3343 case_DBG_SEL(PTCL_C1); 3344 case_DBG_SEL(SCH_C0); 3345 case_DBG_SEL(SCH_C1); 3346 case_DBG_SEL(TMAC_C0); 3347 case_DBG_SEL(TMAC_C1); 3348 case_DBG_SEL(RMAC_C0); 3349 case_DBG_SEL(RMAC_C1); 3350 case_DBG_SEL(RMACST_C0); 3351 case_DBG_SEL(RMACST_C1); 3352 case_DBG_SEL(TRXPTCL_C0); 3353 case_DBG_SEL(TRXPTCL_C1); 3354 case_DBG_SEL(TX_INFOL_C0); 3355 case_DBG_SEL(TX_INFOH_C0); 3356 case_DBG_SEL(TX_INFOL_C1); 3357 case_DBG_SEL(TX_INFOH_C1); 3358 case_DBG_SEL(TXTF_INFOL_C0); 3359 case_DBG_SEL(TXTF_INFOH_C0); 3360 case_DBG_SEL(TXTF_INFOL_C1); 3361 case_DBG_SEL(TXTF_INFOH_C1); 3362 case_DBG_SEL(WDE_BUFMGN_FREEPG); 3363 case_DBG_SEL(WDE_BUFMGN_QUOTA); 3364 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 3365 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 3366 case_DBG_SEL(WDE_QUEMGN_PREPKT); 3367 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 3368 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 3369 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 3370 case_DBG_SEL(PLE_BUFMGN_FREEPG); 3371 case_DBG_SEL(PLE_BUFMGN_QUOTA); 3372 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 3373 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 3374 case_DBG_SEL(PLE_QUEMGN_PREPKT); 3375 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 3376 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 3377 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 3378 case_DBG_SEL(PKTINFO); 3379 case_DBG_SEL(DSPT_HDT_TX0); 3380 case_DBG_SEL(DSPT_HDT_TX1); 3381 case_DBG_SEL(DSPT_HDT_TX2); 3382 case_DBG_SEL(DSPT_HDT_TX3); 3383 case_DBG_SEL(DSPT_HDT_TX4); 3384 case_DBG_SEL(DSPT_HDT_TX5); 3385 case_DBG_SEL(DSPT_HDT_TX6); 3386 case_DBG_SEL(DSPT_HDT_TX7); 3387 case_DBG_SEL(DSPT_HDT_TX8); 3388 case_DBG_SEL(DSPT_HDT_TX9); 3389 case_DBG_SEL(DSPT_HDT_TXA); 3390 case_DBG_SEL(DSPT_HDT_TXB); 3391 case_DBG_SEL(DSPT_HDT_TXC); 3392 case_DBG_SEL(DSPT_HDT_TXD); 3393 case_DBG_SEL(DSPT_HDT_TXE); 3394 case_DBG_SEL(DSPT_HDT_TXF); 3395 case_DBG_SEL(DSPT_CDT_TX0); 3396 case_DBG_SEL(DSPT_CDT_TX1); 3397 case_DBG_SEL(DSPT_CDT_TX3); 3398 case_DBG_SEL(DSPT_CDT_TX4); 3399 case_DBG_SEL(DSPT_CDT_TX5); 3400 case_DBG_SEL(DSPT_CDT_TX6); 3401 case_DBG_SEL(DSPT_CDT_TX7); 3402 case_DBG_SEL(DSPT_CDT_TX8); 3403 case_DBG_SEL(DSPT_CDT_TX9); 3404 case_DBG_SEL(DSPT_CDT_TXA); 3405 case_DBG_SEL(DSPT_CDT_TXB); 3406 case_DBG_SEL(DSPT_CDT_TXC); 3407 case_DBG_SEL(DSPT_HDT_RX0); 3408 case_DBG_SEL(DSPT_HDT_RX1); 3409 case_DBG_SEL(DSPT_HDT_RX2); 3410 case_DBG_SEL(DSPT_HDT_RX3); 3411 case_DBG_SEL(DSPT_HDT_RX4); 3412 case_DBG_SEL(DSPT_HDT_RX5); 3413 case_DBG_SEL(DSPT_CDT_RX_P0); 3414 case_DBG_SEL(DSPT_CDT_RX_P0_0); 3415 case_DBG_SEL(DSPT_CDT_RX_P0_1); 3416 case_DBG_SEL(DSPT_CDT_RX_P0_2); 3417 case_DBG_SEL(DSPT_CDT_RX_P1); 3418 case_DBG_SEL(DSPT_STF_CTRL); 3419 case_DBG_SEL(DSPT_ADDR_CTRL); 3420 case_DBG_SEL(DSPT_WDE_INTF); 3421 case_DBG_SEL(DSPT_PLE_INTF); 3422 case_DBG_SEL(DSPT_FLOW_CTRL); 3423 case_DBG_SEL(PCIE_TXDMA); 3424 case_DBG_SEL(PCIE_RXDMA); 3425 case_DBG_SEL(PCIE_CVT); 3426 case_DBG_SEL(PCIE_CXPL); 3427 case_DBG_SEL(PCIE_IO); 3428 case_DBG_SEL(PCIE_MISC); 3429 case_DBG_SEL(PCIE_MISC2); 3430 } 3431 3432 #undef case_DBG_SEL 3433 3434 p += scnprintf(p, end - p, "Sel addr = 0x%X\n", info->sel_addr); 3435 p += scnprintf(p, end - p, "Read addr = 0x%X\n", info->rd_addr); 3436 3437 for (i = info->srt; i <= info->end; i++) { 3438 switch (info->sel_byte) { 3439 case 1: 3440 default: 3441 rtw89_write8_mask(rtwdev, info->sel_addr, 3442 info->sel_msk, i); 3443 p += scnprintf(p, end - p, "0x%02X: ", i); 3444 break; 3445 case 2: 3446 rtw89_write16_mask(rtwdev, info->sel_addr, 3447 info->sel_msk, i); 3448 p += scnprintf(p, end - p, "0x%04X: ", i); 3449 break; 3450 case 4: 3451 rtw89_write32_mask(rtwdev, info->sel_addr, 3452 info->sel_msk, i); 3453 p += scnprintf(p, end - p, "0x%04X: ", i); 3454 break; 3455 } 3456 3457 udelay(10); 3458 3459 switch (info->rd_byte) { 3460 case 1: 3461 default: 3462 val8 = rtw89_read8_mask(rtwdev, 3463 info->rd_addr, info->rd_msk); 3464 p += scnprintf(p, end - p, "0x%02X\n", val8); 3465 break; 3466 case 2: 3467 val16 = rtw89_read16_mask(rtwdev, 3468 info->rd_addr, info->rd_msk); 3469 p += scnprintf(p, end - p, "0x%04X\n", val16); 3470 break; 3471 case 4: 3472 val32 = rtw89_read32_mask(rtwdev, 3473 info->rd_addr, info->rd_msk); 3474 p += scnprintf(p, end - p, "0x%08X\n", val32); 3475 break; 3476 } 3477 } 3478 3479 out: 3480 return p - buf; 3481 } 3482 3483 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 3484 char *buf, size_t bufsz) 3485 { 3486 char *p = buf, *end = buf + bufsz; 3487 ssize_t n; 3488 u32 sel; 3489 3490 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 3491 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 3492 if (!is_dbg_port_valid(rtwdev, sel)) 3493 continue; 3494 n = rtw89_debug_mac_dbg_port_dump(rtwdev, p, end - p, sel); 3495 if (n < 0) { 3496 rtw89_err(rtwdev, 3497 "failed to dump debug port %d\n", sel); 3498 break; 3499 } 3500 p += n; 3501 } 3502 3503 return p - buf; 3504 } 3505 3506 static ssize_t 3507 rtw89_debug_priv_mac_dbg_port_dump_get(struct rtw89_dev *rtwdev, 3508 struct rtw89_debugfs_priv *debugfs_priv, 3509 char *buf, size_t bufsz) 3510 { 3511 char *p = buf, *end = buf + bufsz; 3512 3513 if (debugfs_priv->dbgpkg_en.ss_dbg) 3514 p += rtw89_debug_mac_dump_ss_dbg(rtwdev, p, end - p); 3515 if (debugfs_priv->dbgpkg_en.dle_dbg) 3516 p += rtw89_debug_mac_dump_dle_dbg(rtwdev, p, end - p); 3517 if (debugfs_priv->dbgpkg_en.dmac_dbg) 3518 p += rtw89_debug_mac_dump_dmac_dbg(rtwdev, p, end - p); 3519 if (debugfs_priv->dbgpkg_en.cmac_dbg) 3520 p += rtw89_debug_mac_dump_cmac_dbg(rtwdev, p, end - p); 3521 if (debugfs_priv->dbgpkg_en.dbg_port) 3522 p += rtw89_debug_mac_dump_dbg_port(rtwdev, p, end - p); 3523 3524 return p - buf; 3525 }; 3526 3527 static u8 *rtw89_hex2bin(struct rtw89_dev *rtwdev, const char *buf, size_t count) 3528 { 3529 u8 *bin; 3530 int num; 3531 int err = 0; 3532 3533 num = count / 2; 3534 bin = kmalloc(num, GFP_KERNEL); 3535 if (!bin) { 3536 err = -EFAULT; 3537 goto out; 3538 } 3539 3540 if (hex2bin(bin, buf, num)) { 3541 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 3542 kfree(bin); 3543 err = -EINVAL; 3544 } 3545 3546 out: 3547 return err ? ERR_PTR(err) : bin; 3548 } 3549 3550 static ssize_t rtw89_debug_priv_send_h2c_set(struct rtw89_dev *rtwdev, 3551 struct rtw89_debugfs_priv *debugfs_priv, 3552 const char *buf, size_t count) 3553 { 3554 u8 *h2c; 3555 int ret; 3556 u16 h2c_len = count / 2; 3557 3558 h2c = rtw89_hex2bin(rtwdev, buf, count); 3559 if (IS_ERR(h2c)) 3560 return -EFAULT; 3561 3562 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3563 3564 kfree(h2c); 3565 3566 return ret ? ret : count; 3567 } 3568 3569 static ssize_t 3570 rtw89_debug_priv_early_h2c_get(struct rtw89_dev *rtwdev, 3571 struct rtw89_debugfs_priv *debugfs_priv, 3572 char *buf, size_t bufsz) 3573 { 3574 struct rtw89_early_h2c *early_h2c; 3575 char *p = buf, *end = buf + bufsz; 3576 int seq = 0; 3577 3578 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3579 3580 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3581 p += scnprintf(p, end - p, "%d: %*ph\n", ++seq, 3582 early_h2c->h2c_len, early_h2c->h2c); 3583 3584 return p - buf; 3585 } 3586 3587 static ssize_t 3588 rtw89_debug_priv_early_h2c_set(struct rtw89_dev *rtwdev, 3589 struct rtw89_debugfs_priv *debugfs_priv, 3590 const char *buf, size_t count) 3591 { 3592 struct rtw89_early_h2c *early_h2c; 3593 u8 *h2c; 3594 u16 h2c_len = count / 2; 3595 3596 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3597 3598 h2c = rtw89_hex2bin(rtwdev, buf, count); 3599 if (IS_ERR(h2c)) 3600 return -EFAULT; 3601 3602 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3603 kfree(h2c); 3604 rtw89_fw_free_all_early_h2c(rtwdev); 3605 goto out; 3606 } 3607 3608 early_h2c = kmalloc_obj(*early_h2c); 3609 if (!early_h2c) { 3610 kfree(h2c); 3611 return -EFAULT; 3612 } 3613 3614 early_h2c->h2c = h2c; 3615 early_h2c->h2c_len = h2c_len; 3616 3617 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3618 3619 out: 3620 return count; 3621 } 3622 3623 static int rtw89_dbg_trigger_l1_error_ax(struct rtw89_dev *rtwdev) 3624 { 3625 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3626 struct rtw89_cpuio_ctrl ctrl_para = {}; 3627 u16 pkt_id; 3628 int ret; 3629 3630 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3631 if (ret) 3632 return ret; 3633 3634 /* intentionally, enqueue two pkt, but has only one pkt id */ 3635 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3636 ctrl_para.start_pktid = pkt_id; 3637 ctrl_para.end_pktid = pkt_id; 3638 ctrl_para.pkt_num = 1; /* start from 0 */ 3639 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3640 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3641 3642 if (mac->set_cpuio(rtwdev, &ctrl_para, true)) 3643 return -EFAULT; 3644 3645 return 0; 3646 } 3647 3648 static int rtw89_dbg_trigger_l1_error_be(struct rtw89_dev *rtwdev) 3649 { 3650 int ret; 3651 3652 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3653 if (ret) 3654 return ret; 3655 3656 rtw89_write32_set(rtwdev, R_BE_FW_TRIGGER_IDCT_ISR, 3657 B_BE_DMAC_FW_TRIG_IDCT | B_BE_DMAC_FW_ERR_IDCT_IMR); 3658 3659 return 0; 3660 } 3661 3662 static int rtw89_dbg_trigger_l1_error_by_halt_h2c(struct rtw89_dev *rtwdev) 3663 { 3664 if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3665 return -EBUSY; 3666 3667 return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RESET_FORCE); 3668 } 3669 3670 static int rtw89_dbg_trigger_l1_error(struct rtw89_dev *rtwdev) 3671 { 3672 const struct rtw89_chip_info *chip = rtwdev->chip; 3673 int (*sim_l1)(struct rtw89_dev *rtwdev); 3674 3675 switch (chip->chip_gen) { 3676 case RTW89_CHIP_AX: 3677 sim_l1 = rtw89_dbg_trigger_l1_error_ax; 3678 break; 3679 case RTW89_CHIP_BE: 3680 sim_l1 = rtw89_dbg_trigger_l1_error_be; 3681 break; 3682 default: 3683 return -EOPNOTSUPP; 3684 } 3685 3686 if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw)) 3687 return rtw89_dbg_trigger_l1_error_by_halt_h2c(rtwdev); 3688 3689 rtw89_leave_ps_mode(rtwdev); 3690 3691 return sim_l1(rtwdev); 3692 } 3693 3694 static int rtw89_dbg_trigger_l0_error_ax(struct rtw89_dev *rtwdev) 3695 { 3696 u16 val16; 3697 u8 val8; 3698 int ret; 3699 3700 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3701 if (ret) 3702 return ret; 3703 3704 val8 = rtw89_read8(rtwdev, R_AX_CMAC_FUNC_EN); 3705 rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8 & ~B_AX_TMAC_EN); 3706 mdelay(1); 3707 rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8); 3708 3709 val16 = rtw89_read16(rtwdev, R_AX_PTCL_IMR0); 3710 rtw89_write16(rtwdev, R_AX_PTCL_IMR0, val16 | B_AX_F2PCMD_EMPTY_ERR_INT_EN); 3711 rtw89_write16(rtwdev, R_AX_PTCL_IMR0, val16); 3712 3713 return 0; 3714 } 3715 3716 static int rtw89_dbg_trigger_l0_error_be(struct rtw89_dev *rtwdev) 3717 { 3718 int ret; 3719 3720 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3721 if (ret) 3722 return ret; 3723 3724 rtw89_write32_set(rtwdev, R_BE_CMAC_FW_TRIGGER_IDCT_ISR, 3725 B_BE_CMAC_FW_TRIG_IDCT | B_BE_CMAC_FW_ERR_IDCT_IMR); 3726 3727 return 0; 3728 } 3729 3730 static int rtw89_dbg_trigger_l0_error_by_halt_h2c(struct rtw89_dev *rtwdev) 3731 { 3732 if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3733 return -EBUSY; 3734 3735 return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L0_RESET_FORCE); 3736 } 3737 3738 static int rtw89_dbg_trigger_l0_error(struct rtw89_dev *rtwdev) 3739 { 3740 const struct rtw89_chip_info *chip = rtwdev->chip; 3741 int (*sim_l0)(struct rtw89_dev *rtwdev); 3742 3743 switch (chip->chip_gen) { 3744 case RTW89_CHIP_AX: 3745 sim_l0 = rtw89_dbg_trigger_l0_error_ax; 3746 break; 3747 case RTW89_CHIP_BE: 3748 sim_l0 = rtw89_dbg_trigger_l0_error_be; 3749 break; 3750 default: 3751 return -EOPNOTSUPP; 3752 } 3753 3754 if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw)) 3755 return rtw89_dbg_trigger_l0_error_by_halt_h2c(rtwdev); 3756 3757 rtw89_leave_ps_mode(rtwdev); 3758 3759 return sim_l0(rtwdev); 3760 } 3761 3762 static ssize_t 3763 rtw89_debug_priv_fw_crash_get(struct rtw89_dev *rtwdev, 3764 struct rtw89_debugfs_priv *debugfs_priv, 3765 char *buf, size_t bufsz) 3766 { 3767 char *p = buf, *end = buf + bufsz; 3768 3769 p += scnprintf(p, end - p, "%d\n", 3770 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3771 return p - buf; 3772 } 3773 3774 enum rtw89_dbg_crash_simulation_type { 3775 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3776 RTW89_DBG_SIM_L1_ERROR = 2, 3777 RTW89_DBG_SIM_L0_ERROR = 3, 3778 }; 3779 3780 static ssize_t 3781 rtw89_debug_priv_fw_crash_set(struct rtw89_dev *rtwdev, 3782 struct rtw89_debugfs_priv *debugfs_priv, 3783 const char *buf, size_t count) 3784 { 3785 int (*sim)(struct rtw89_dev *rtwdev); 3786 bool announce = true; 3787 u8 crash_type; 3788 int ret; 3789 3790 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3791 3792 ret = kstrtou8(buf, 0, &crash_type); 3793 if (ret) 3794 return -EINVAL; 3795 3796 switch (crash_type) { 3797 case RTW89_DBG_SIM_CPU_EXCEPTION: 3798 if (!RTW89_CHK_FW_FEATURE_GROUP(CRASH_TRIGGER, &rtwdev->fw)) 3799 return -EOPNOTSUPP; 3800 sim = rtw89_fw_h2c_trigger_cpu_exception; 3801 break; 3802 case RTW89_DBG_SIM_L1_ERROR: 3803 sim = rtw89_dbg_trigger_l1_error; 3804 break; 3805 case RTW89_DBG_SIM_L0_ERROR: 3806 sim = rtw89_dbg_trigger_l0_error; 3807 3808 /* Driver SER flow won't get involved; only FW will. */ 3809 announce = false; 3810 break; 3811 default: 3812 return -EINVAL; 3813 } 3814 3815 if (announce) 3816 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3817 3818 ret = sim(rtwdev); 3819 3820 if (ret) 3821 return ret; 3822 3823 return count; 3824 } 3825 3826 struct rtw89_dbg_ser_counters { 3827 unsigned int l0_sim; 3828 unsigned int l0; 3829 unsigned int l1; 3830 unsigned int l0_to_l1; 3831 }; 3832 3833 static void rtw89_dbg_get_ser_counters_ax(struct rtw89_dev *rtwdev, 3834 struct rtw89_dbg_ser_counters *cnt) 3835 { 3836 const u32 val = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 3837 3838 cnt->l0 = u32_get_bits(val, B_AX_SER_L0_COUNTER_MASK); 3839 cnt->l1 = u32_get_bits(val, B_AX_SER_L1_COUNTER_MASK); 3840 cnt->l0_to_l1 = u32_get_bits(val, B_AX_L0_TO_L1_EVENT_MASK); 3841 } 3842 3843 static void rtw89_dbg_get_ser_counters_be(struct rtw89_dev *rtwdev, 3844 struct rtw89_dbg_ser_counters *cnt) 3845 { 3846 const u32 val = rtw89_read32(rtwdev, R_BE_SER_DBG_INFO); 3847 3848 cnt->l0_sim = rtw89_read8(rtwdev, R_BE_SER_L0_DBG_CNT1 + 3); 3849 cnt->l0 = u32_get_bits(val, B_BE_SER_L0_COUNTER_MASK); 3850 cnt->l1 = u32_get_bits(val, B_BE_SER_L1_COUNTER_MASK); 3851 cnt->l0_to_l1 = u32_get_bits(val, B_BE_SER_L0_PROMOTE_L1_EVENT_MASK); 3852 } 3853 3854 static ssize_t rtw89_debug_priv_ser_counters_get(struct rtw89_dev *rtwdev, 3855 struct rtw89_debugfs_priv *debugfs_priv, 3856 char *buf, size_t bufsz) 3857 { 3858 const struct rtw89_ser_count *sw_cnt = &rtwdev->ser.sw_cnt; 3859 const struct rtw89_chip_info *chip = rtwdev->chip; 3860 struct rtw89_dbg_ser_counters cnt = {}; 3861 char *p = buf, *end = buf + bufsz; 3862 3863 rtw89_leave_ps_mode(rtwdev); 3864 3865 switch (chip->chip_gen) { 3866 case RTW89_CHIP_AX: 3867 rtw89_dbg_get_ser_counters_ax(rtwdev, &cnt); 3868 break; 3869 case RTW89_CHIP_BE: 3870 rtw89_dbg_get_ser_counters_be(rtwdev, &cnt); 3871 break; 3872 default: 3873 return -EOPNOTSUPP; 3874 } 3875 3876 p += scnprintf(p, end - p, "SER L1 SW Count: %u\n", sw_cnt->l1); 3877 p += scnprintf(p, end - p, "SER L2 SW Count: %u\n", sw_cnt->l2); 3878 3879 /* Some chipsets don't have dedicated cnt for SER simulation. */ 3880 p += scnprintf(p, end - p, "---\n"); 3881 p += scnprintf(p, end - p, "SER L0 Simulation Count: %d\n", cnt.l0_sim); 3882 3883 /* Some chipsets won't record SER simulation in HW cnt. */ 3884 p += scnprintf(p, end - p, "---\n"); 3885 p += scnprintf(p, end - p, "SER L0 Count: %d\n", cnt.l0); 3886 p += scnprintf(p, end - p, "SER L1 Count: %d\n", cnt.l1); 3887 p += scnprintf(p, end - p, "SER L0 promote event: %d\n", cnt.l0_to_l1); 3888 3889 return p - buf; 3890 } 3891 3892 static ssize_t rtw89_debug_priv_btc_info_get(struct rtw89_dev *rtwdev, 3893 struct rtw89_debugfs_priv *debugfs_priv, 3894 char *buf, size_t bufsz) 3895 { 3896 return rtw89_btc_dump_info(rtwdev, buf, bufsz); 3897 } 3898 3899 static ssize_t rtw89_debug_priv_btc_manual_set(struct rtw89_dev *rtwdev, 3900 struct rtw89_debugfs_priv *debugfs_priv, 3901 const char *buf, size_t count) 3902 { 3903 struct rtw89_btc *btc = &rtwdev->btc; 3904 int ret; 3905 3906 ret = kstrtobool(buf, &btc->manual_ctrl); 3907 if (ret) 3908 return ret; 3909 3910 btc->ctrl.manual = btc->manual_ctrl; 3911 3912 return count; 3913 } 3914 3915 static ssize_t rtw89_debug_priv_fw_log_manual_set(struct rtw89_dev *rtwdev, 3916 struct rtw89_debugfs_priv *debugfs_priv, 3917 const char *buf, size_t count) 3918 { 3919 struct rtw89_fw_log *log = &rtwdev->fw.log; 3920 bool fw_log_manual; 3921 3922 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3923 3924 if (kstrtobool(buf, &fw_log_manual)) 3925 goto out; 3926 3927 log->enable = fw_log_manual; 3928 if (log->enable) 3929 rtw89_fw_log_prepare(rtwdev); 3930 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3931 out: 3932 return count; 3933 } 3934 3935 static int rtw89_sta_link_info_get_iter(struct rtw89_dev *rtwdev, 3936 char *buf, size_t bufsz, 3937 struct rtw89_sta_link *rtwsta_link) 3938 { 3939 static const char * const he_gi_str[] = { 3940 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3941 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3942 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3943 }; 3944 static const char * const eht_gi_str[] = { 3945 [NL80211_RATE_INFO_EHT_GI_0_8] = "0.8", 3946 [NL80211_RATE_INFO_EHT_GI_1_6] = "1.6", 3947 [NL80211_RATE_INFO_EHT_GI_3_2] = "3.2", 3948 }; 3949 struct rate_info *rate = &rtwsta_link->ra_report.txrate; 3950 struct ieee80211_rx_status *status = &rtwsta_link->rx_status; 3951 struct rtw89_hal *hal = &rtwdev->hal; 3952 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3953 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3954 struct ieee80211_link_sta *link_sta; 3955 char *p = buf, *end = buf + bufsz; 3956 u8 evm_min, evm_max, evm_1ss; 3957 u16 max_rc_amsdu_len; 3958 u8 rssi; 3959 u8 snr; 3960 int i; 3961 3962 rcu_read_lock(); 3963 3964 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3965 max_rc_amsdu_len = link_sta->agg.max_rc_amsdu_len; 3966 3967 rcu_read_unlock(); 3968 3969 p += scnprintf(p, end - p, "TX rate [%u, %u]: ", rtwsta_link->mac_id, 3970 rtwsta_link->link_id); 3971 3972 if (rate->flags & RATE_INFO_FLAGS_MCS) 3973 p += scnprintf(p, end - p, "HT MCS-%d%s", rate->mcs, 3974 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3975 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3976 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", rate->nss, 3977 rate->mcs, 3978 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3979 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3980 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", rate->nss, 3981 rate->mcs, 3982 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3983 he_gi_str[rate->he_gi] : "N/A"); 3984 else if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) 3985 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", rate->nss, 3986 rate->mcs, 3987 rate->eht_gi < ARRAY_SIZE(eht_gi_str) ? 3988 eht_gi_str[rate->eht_gi] : "N/A"); 3989 else 3990 p += scnprintf(p, end - p, "Legacy %d", rate->legacy); 3991 p += scnprintf(p, end - p, "%s", 3992 rtwsta_link->ra_report.might_fallback_legacy ? " FB_G" : ""); 3993 p += scnprintf(p, end - p, " BW:%u", 3994 rtw89_rate_info_bw_to_mhz(rate->bw)); 3995 p += scnprintf(p, end - p, " (hw_rate=0x%x)", 3996 rtwsta_link->ra_report.hw_rate); 3997 p += scnprintf(p, end - p, " PER:%d", rtwsta_link->ra_report.retry_ratio); 3998 p += scnprintf(p, end - p, " ==> agg_wait=%d (%d)\n", 3999 rtwsta_link->max_agg_wait, 4000 max_rc_amsdu_len); 4001 4002 p += scnprintf(p, end - p, "RX rate [%u, %u]: ", rtwsta_link->mac_id, 4003 rtwsta_link->link_id); 4004 4005 switch (status->encoding) { 4006 case RX_ENC_LEGACY: 4007 p += scnprintf(p, end - p, "Legacy %d", status->rate_idx + 4008 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 4009 break; 4010 case RX_ENC_HT: 4011 p += scnprintf(p, end - p, "HT MCS-%d%s", status->rate_idx, 4012 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 4013 break; 4014 case RX_ENC_VHT: 4015 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", status->nss, 4016 status->rate_idx, 4017 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 4018 break; 4019 case RX_ENC_HE: 4020 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", 4021 status->nss, status->rate_idx, 4022 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 4023 he_gi_str[status->he_gi] : "N/A"); 4024 break; 4025 case RX_ENC_EHT: 4026 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", 4027 status->nss, status->rate_idx, 4028 status->eht.gi < ARRAY_SIZE(eht_gi_str) ? 4029 eht_gi_str[status->eht.gi] : "N/A"); 4030 break; 4031 } 4032 p += scnprintf(p, end - p, " BW:%u", 4033 rtw89_rate_info_bw_to_mhz(status->bw)); 4034 p += scnprintf(p, end - p, " (hw_rate=0x%x)\n", 4035 rtwsta_link->rx_hw_rate); 4036 4037 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi); 4038 p += scnprintf(p, end - p, "RSSI: %d dBm (raw=%d, prev=%d) [", 4039 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, 4040 rtwsta_link->prev_rssi); 4041 for (i = 0; i < ant_num; i++) { 4042 rssi = ewma_rssi_read(&rtwsta_link->rssi[i]); 4043 p += scnprintf(p, end - p, "%d%s%s", 4044 RTW89_RSSI_RAW_TO_DBM(rssi), 4045 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 4046 i + 1 == ant_num ? "" : ", "); 4047 } 4048 p += scnprintf(p, end - p, "]\n"); 4049 4050 evm_1ss = ewma_evm_read(&rtwsta_link->evm_1ss); 4051 p += scnprintf(p, end - p, "EVM: [%2u.%02u, ", evm_1ss >> 2, 4052 (evm_1ss & 0x3) * 25); 4053 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 4054 evm_min = ewma_evm_read(&rtwsta_link->evm_min[i]); 4055 evm_max = ewma_evm_read(&rtwsta_link->evm_max[i]); 4056 4057 p += scnprintf(p, end - p, "%s(%2u.%02u, %2u.%02u)", 4058 i == 0 ? "" : " ", 4059 evm_min >> 2, (evm_min & 0x3) * 25, 4060 evm_max >> 2, (evm_max & 0x3) * 25); 4061 } 4062 p += scnprintf(p, end - p, "]\t"); 4063 4064 snr = ewma_snr_read(&rtwsta_link->avg_snr); 4065 p += scnprintf(p, end - p, "SNR: %u\n", snr); 4066 4067 return p - buf; 4068 } 4069 4070 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 4071 { 4072 struct rtw89_debugfs_iter_data *iter_data = 4073 (struct rtw89_debugfs_iter_data *)data; 4074 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4075 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4076 struct rtw89_sta_link *rtwsta_link; 4077 size_t bufsz = iter_data->bufsz; 4078 char *buf = iter_data->buf; 4079 char *p = buf, *end = buf + bufsz; 4080 unsigned int link_id; 4081 4082 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 4083 p += rtw89_sta_link_info_get_iter(rtwdev, p, end - p, rtwsta_link); 4084 4085 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4086 } 4087 4088 static int 4089 rtw89_debug_append_rate(char *buf, size_t bufsz, const u32 *rate_cnt, 4090 int first_rate, int len) 4091 { 4092 char *p = buf, *end = buf + bufsz; 4093 int i; 4094 4095 for (i = 0; i < len; i++) 4096 p += scnprintf(p, end - p, "%s%u", i == 0 ? "" : ", ", 4097 rate_cnt[first_rate + i]); 4098 4099 return p - buf; 4100 } 4101 4102 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate} 4103 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate} 4104 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate} 4105 4106 static const struct rtw89_rx_rate_cnt_info { 4107 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM]; 4108 int len; 4109 int ext; 4110 const char *rate_mode; 4111 } rtw89_rx_rate_cnt_infos[] = { 4112 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"}, 4113 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"}, 4114 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"}, 4115 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"}, 4116 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"}, 4117 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"}, 4118 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"}, 4119 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"}, 4120 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"}, 4121 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"}, 4122 }; 4123 4124 static const struct rtw89_tx_rate_cnt_info { 4125 int first_rate; 4126 int len; 4127 const char *rate_mode; 4128 } rtw89_tx_rate_cnt_infos[] = { 4129 {0, 4, "Legacy:"}, 4130 {4, 8, "OFDM:"}, 4131 {12, 14, "MCS 1SS:"}, 4132 {26, 14, "MCS 2SS:"}, 4133 }; 4134 4135 static int rtw89_get_rx_pkt_stat(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb, 4136 char *buf, size_t bufsz) 4137 { 4138 struct rtw89_pkt_stat *pkt_stat = &bb->last_pkt_stat; 4139 const struct rtw89_chip_info *chip = rtwdev->chip; 4140 const struct rtw89_rx_rate_cnt_info *info; 4141 u8 rssi = ewma_rssi_read(&bb->bcn_rssi); 4142 char *p = buf, *end = buf + bufsz; 4143 enum rtw89_hw_rate first_rate; 4144 int i; 4145 4146 p += scnprintf(p, end - p, "Beacon: %u (%d dBm)\n", 4147 pkt_stat->beacon_nr, 4148 RTW89_RSSI_RAW_TO_DBM(rssi)); 4149 4150 p += scnprintf(p, end - p, "RX count:\n"); 4151 4152 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 4153 info = &rtw89_rx_rate_cnt_infos[i]; 4154 first_rate = info->first_rate[chip->chip_gen]; 4155 if (first_rate >= RTW89_HW_RATE_NR) 4156 continue; 4157 4158 p += scnprintf(p, end - p, "%10s [", info->rate_mode); 4159 p += rtw89_debug_append_rate(p, end - p, pkt_stat->rx_rate_cnt, 4160 first_rate, info->len); 4161 if (info->ext) { 4162 p += scnprintf(p, end - p, "]["); 4163 p += rtw89_debug_append_rate(p, end - p, pkt_stat->rx_rate_cnt, 4164 first_rate + info->len, 4165 info->ext); 4166 } 4167 p += scnprintf(p, end - p, "]\n"); 4168 } 4169 4170 return p - buf; 4171 } 4172 4173 static ssize_t rtw89_debug_priv_phy_info_get(struct rtw89_dev *rtwdev, 4174 struct rtw89_debugfs_priv *debugfs_priv, 4175 char *buf, size_t bufsz) 4176 { 4177 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4178 struct rtw89_debugfs_iter_data iter_data; 4179 struct rtw89_hal *hal = &rtwdev->hal; 4180 char *p = buf, *end = buf + bufsz; 4181 struct rtw89_bb_ctx *bb; 4182 4183 p += scnprintf(p, end - p, "TP TX: %u [%u] Mbps (lv: %d", 4184 stats->tx_throughput, stats->tx_throughput_raw, 4185 stats->tx_tfc_lv); 4186 if (hal->thermal_prot_lv) 4187 p += scnprintf(p, end - p, ", duty: %d%%", 4188 100 - hal->thermal_prot_lv * RTW89_THERMAL_PROT_STEP); 4189 p += scnprintf(p, end - p, "), RX: %u [%u] Mbps (lv: %d)\n", 4190 stats->rx_throughput, stats->rx_throughput_raw, 4191 stats->rx_tfc_lv); 4192 p += scnprintf(p, end - p, "Avg packet length: TX=%u, RX=%u\n", 4193 stats->tx_avg_len, 4194 stats->rx_avg_len); 4195 p += scnprintf(p, end - p, "TF: %u\n", stats->rx_tf_periodic); 4196 4197 rtw89_for_each_active_bb(rtwdev, bb) { 4198 p += scnprintf(p, end - p, "\n[PHY %u]\n", bb->phy_idx); 4199 p += rtw89_get_rx_pkt_stat(rtwdev, bb, p, end - p); 4200 } 4201 p += scnprintf(p, end - p, "\n"); 4202 4203 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4204 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, &iter_data); 4205 p += iter_data.written_sz; 4206 4207 return p - buf; 4208 } 4209 4210 static const char *const lcck[] = {"L_CCK"}; 4211 static const char *const scck[] = {"S_CCK"}; 4212 static const char *const ht_gf[] = {"HT_GF"}; 4213 static const char *const vht_mu[] = {"VHT_MU"}; 4214 static const char *const he_er_su[] = {"HE_ER_SU"}; 4215 static const char *const eht_tb[] = {"EHT_TB"}; 4216 static const char *const legacy_ax[] = {"LEGACY"}; 4217 static const char *const ht_ax[] = {"HT"}; 4218 static const char *const vht_su_ax[] = {"VHT_SU"}; 4219 static const char *const he_su_ax[] = {"HE_SU"}; 4220 static const char *const he_mu_ax[] = {"HE_MU"}; 4221 static const char *const he_tb_ax[] = {"HE_TB"}; 4222 static const char *const legacy_be[] = { 4223 "LEGACY", "LEGACY_DUP", "LEGACY_DUP_PUNC" 4224 }; 4225 4226 static const char *const ht_be[] = { 4227 "HT_MF", "HT_SND_NDP" 4228 }; 4229 4230 static const char *const vht_su_be[] = { 4231 "VHT_SU", "VHT_SND_NDP" 4232 }; 4233 4234 static const char *const he_su_be[] = { 4235 "HE_SU", "HE_SND_NDP", "HE_SND_NDP_PUNC", "HE_RANG_NDP" 4236 }; 4237 4238 static const char *const he_mu_be[] = { 4239 "HE_MU_RU", "HE_MU_MU", "HE_MU_RU_PUNC" 4240 }; 4241 4242 static const char *const he_tb_be[] = { 4243 "HE_TB", "HE_TB_FB_NDP", "HE_MU_RANG_NDP" 4244 }; 4245 4246 static const char *const eht_mu[] = { 4247 "EHT_MU_SU", "EHT_MU_ER", "EHT_MU_RU", "EHT_MU_MU", 4248 "EHT_MU_SND_NDP", "EHT_MU_SU_PUNC", "EHT_MU_RU_PUNC", 4249 "EHT_SND_NDP_PUNC", "EHT_MU_MU_PUNC" 4250 }; 4251 4252 #define PPDU_SAME(ppdu) \ 4253 {.str = {ppdu, ppdu}, \ 4254 .cnt = {ARRAY_SIZE(ppdu), ARRAY_SIZE(ppdu)} } 4255 #define PPDU_VARIANT(ppdu) \ 4256 {.str = {ppdu##_ax, ppdu##_be}, \ 4257 .cnt = {ARRAY_SIZE(ppdu##_ax), ARRAY_SIZE(ppdu##_be)} } 4258 #define PPDU_GEV1(ppdu) \ 4259 {.str = {NULL, ppdu}, \ 4260 .cnt = {0, ARRAY_SIZE(ppdu)} } 4261 4262 static const struct rtw89_ppdu_info { 4263 const char *const *str[RTW89_CHIP_GEN_NUM]; 4264 u8 cnt[RTW89_CHIP_GEN_NUM]; 4265 } rtw89_ppdu_infos[] = { 4266 [0] = PPDU_SAME(lcck), 4267 [1] = PPDU_SAME(scck), 4268 [2] = PPDU_VARIANT(legacy), 4269 [3] = PPDU_VARIANT(ht), 4270 [4] = PPDU_SAME(ht_gf), 4271 [5] = PPDU_VARIANT(vht_su), 4272 [6] = PPDU_SAME(vht_mu), 4273 [7] = PPDU_VARIANT(he_su), 4274 [8] = PPDU_SAME(he_er_su), 4275 [9] = PPDU_VARIANT(he_mu), 4276 [10] = PPDU_VARIANT(he_tb), 4277 [11] = PPDU_GEV1(eht_mu), 4278 [12] = PPDU_GEV1(eht_tb), 4279 }; 4280 4281 #define TXCMD_SAME(txcmd) {txcmd, txcmd} 4282 #define TXCMD_DIFF(txcmd, txcmd_v1) {txcmd, txcmd_v1} 4283 #define TXCMD_GEV1(txcmd) {"RSVD", txcmd} 4284 4285 static const struct rtw89_txcmd_info { 4286 const char *str[RTW89_CHIP_GEN_NUM]; 4287 } rtw89_txcmd_infos[] = { 4288 [0] = {TXCMD_SAME("DATA")}, 4289 [1] = {TXCMD_SAME("BCN")}, 4290 [2] = {TXCMD_SAME("HT_NDPA")}, 4291 [3] = {TXCMD_SAME("VHT_NDPA")}, 4292 [4] = {TXCMD_SAME("HE_NDPA")}, 4293 [5] = {TXCMD_GEV1("EHT_NDPA")}, 4294 [6] = {TXCMD_GEV1("11MC_FTM")}, 4295 [7] = {TXCMD_GEV1("11MC_FTM_ACK")}, 4296 [8] = {TXCMD_SAME("RTS")}, 4297 [9] = {TXCMD_SAME("CTS2S")}, 4298 [10] = {TXCMD_SAME("CF_END")}, 4299 [11] = {TXCMD_SAME("CMP_BAR")}, 4300 [12] = {TXCMD_SAME("BFRP")}, 4301 [13] = {TXCMD_SAME("NDP")}, 4302 [14] = {TXCMD_SAME("QoS_NULL")}, 4303 [15] = {TXCMD_GEV1("CTS_2_MURTS")}, 4304 [16] = {TXCMD_SAME("ACK")}, 4305 [17] = {TXCMD_SAME("CTS")}, 4306 [18] = {TXCMD_SAME("CMP_BA")}, 4307 [19] = {TXCMD_SAME("MSTA_BA")}, 4308 [20] = {TXCMD_SAME("HT_CSI")}, 4309 [21] = {TXCMD_SAME("VHT_CSI")}, 4310 [22] = {TXCMD_SAME("HE_CSI")}, 4311 [23] = {TXCMD_GEV1("EHT_CSI")}, 4312 [24] = {TXCMD_GEV1("NTB_I2R_NDPA")}, 4313 [25] = {TXCMD_GEV1("NTB_I2R_NDP")}, 4314 [26] = {TXCMD_GEV1("NTB_I2R_LMR")}, 4315 [27] = {TXCMD_GEV1("NTB_I2R_NDP")}, 4316 [28] = {TXCMD_GEV1("NTB_I2R_LMR")}, 4317 [29] = {TXCMD_GEV1("NTB_R2I_RANG_NDPA")}, 4318 [30] = {TXCMD_GEV1("NTB_R2I_NDP")}, 4319 [31] = {TXCMD_DIFF("TB_PPDU", "NTB_R2I_LMR")}, 4320 [32] = {TXCMD_SAME("TRIG_BASIC")}, 4321 [33] = {TXCMD_SAME("TRIG_BFRP")}, 4322 [34] = {TXCMD_SAME("TRIG_MUBAR")}, 4323 [35] = {TXCMD_SAME("TRIG_MURTS")}, 4324 [36] = {TXCMD_SAME("TRIG_BSRP")}, 4325 [37] = {TXCMD_SAME("TRIG_BQRP")}, 4326 [38] = {TXCMD_SAME("TRIG_NFRP")}, 4327 [39] = {TXCMD_GEV1("TRIG_BASIC_DATA")}, 4328 [40] = {TXCMD_GEV1("TRIG_RANG_POLL")}, 4329 [41] = {TXCMD_GEV1("TRIG_RANG_SNR")}, 4330 [42] = {TXCMD_GEV1("TRIG_RANG_LMR")}, 4331 [48] = {TXCMD_DIFF("TRIG_BASIC_DATA", "TRIG_TB_CSI")}, 4332 [49] = {TXCMD_GEV1("TRIG_TB_CBA")}, 4333 [50] = {TXCMD_GEV1("TRIG_TB_MBA")}, 4334 [51] = {TXCMD_GEV1("TRIG_TB_BSR")}, 4335 [52] = {TXCMD_GEV1("TRIG_TB_BQR")}, 4336 [53] = {TXCMD_GEV1("TRIG_TB_ACK")}, 4337 [54] = {TXCMD_GEV1("TRIG_TB_PPDU")}, 4338 [55] = {TXCMD_GEV1("TRIG_TB_I2R_CTS2S")}, 4339 [56] = {TXCMD_GEV1("TRIG_TB_I2R_NDP")}, 4340 [57] = {TXCMD_GEV1("TRIG_TB_I2R_LMR")}, 4341 }; 4342 4343 static const char *rtw89_ppdu_str(struct rtw89_dev *rtwdev, u8 type, u8 subtype) 4344 { 4345 const struct rtw89_chip_info *chip = rtwdev->chip; 4346 const struct rtw89_ppdu_info *ppdu_info; 4347 4348 if (type >= ARRAY_SIZE(rtw89_ppdu_infos)) 4349 return "RSVD"; 4350 4351 ppdu_info = &rtw89_ppdu_infos[type]; 4352 4353 if (!ppdu_info->str[chip->chip_gen] || 4354 subtype >= ppdu_info->cnt[chip->chip_gen]) 4355 return "RSVD"; 4356 4357 return ppdu_info->str[chip->chip_gen][subtype]; 4358 } 4359 4360 static const char *rtw89_txcmd_str(struct rtw89_dev *rtwdev, u8 txcmd) 4361 { 4362 const struct rtw89_chip_info *chip = rtwdev->chip; 4363 4364 if (txcmd < ARRAY_SIZE(rtw89_txcmd_infos)) 4365 return rtw89_txcmd_infos[txcmd].str[chip->chip_gen] ?: "RSVD"; 4366 4367 return "RSVD"; 4368 } 4369 4370 static int rtw89_get_bb_stat(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb, 4371 char *buf, size_t bufsz) 4372 { 4373 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4374 struct rtw89_pkt_stat *pkt_stat = &bb->last_pkt_stat; 4375 const struct rtw89_physts_regs *physts = phy->physts; 4376 struct rtw89_pmac_stat_info *pmac = &bb->pmac_stat; 4377 struct rtw89_tx_stat_info *tx_stat = &bb->tx_stat; 4378 const struct rtw89_chip_info *chip = rtwdev->chip; 4379 char *p = buf, *end = buf + bufsz; 4380 u8 factor = chip->txpwr_factor_rf; 4381 u32 reg_nr; 4382 s32 val; 4383 int i; 4384 4385 p += scnprintf(p, end - p, "\n[PHY %u]\n", bb->phy_idx); 4386 4387 p += scnprintf(p, end - p, "== PMAC\n"); 4388 p += scnprintf(p, end - p, 4389 "TX [CCK_TXEN, CCK_TXON, OFDM_TXEN, OFDM_TXON]: [%d, %d, %d, %d]\n", 4390 pmac->cck_mac_txen, pmac->cck_phy_txon, 4391 pmac->ofdm_mac_txen, pmac->ofdm_phy_txon); 4392 p += scnprintf(p, end - p, "CRC [CCK, OFDM, HT, VHT, HE, EHT, ALL, MPDU]\n"); 4393 p += scnprintf(p, end - p, " ok: [%d, %d, %d, %d, %d, %d, %d, %d]\n", 4394 pmac->cnt_cck_crc32_ok, pmac->cnt_ofdm_crc32_ok, 4395 pmac->cnt_ht_crc32_ok, pmac->cnt_vht_crc32_ok, 4396 pmac->cnt_he_crc32_ok, pmac->cnt_eht_crc32_ok, 4397 pmac->cnt_crc32_ok_all, pmac->cnt_ampdu_crc_ok); 4398 p += scnprintf(p, end - p, "err: [%d, %d, %d, %d, %d, %d, %d, %d]\n", 4399 pmac->cnt_cck_crc32_error, pmac->cnt_ofdm_crc32_error, 4400 pmac->cnt_ht_crc32_error, pmac->cnt_vht_crc32_error, 4401 pmac->cnt_he_crc32_error, pmac->cnt_eht_crc32_error, 4402 pmac->cnt_crc32_error_all, pmac->cnt_ampdu_crc_error); 4403 p += scnprintf(p, end - p, "CCA [CCK, OFDM]: [%d, %d]\n", 4404 pmac->cnt_cck_cca, pmac->cnt_ofdm_cca); 4405 p += scnprintf(p, end - p, "FA [CCK, OFDM]: [%d, %d]\n", 4406 pmac->cnt_cck_fail, pmac->cnt_ofdm_fail); 4407 4408 p += scnprintf(p, end - p, "CCA spoofing [CCK, OFDM]: [%d, %d]\n", 4409 pmac->cnt_cck_spoofing, pmac->cnt_ofdm_spoofing); 4410 p += scnprintf(p, end - p, "CCK SFD: %d, SIG_GG: %d\n", 4411 pmac->cnt_sfd_gg, pmac->cnt_sig_gg); 4412 p += scnprintf(p, end - p, 4413 "OFDM Parity: %d, Rate: %d, LSIG_BRK_S: %d, LSIG_BRK_L: %d, SBD: %d\n", 4414 pmac->cnt_parity_fail, pmac->cnt_rate_illegal, 4415 pmac->cnt_lsig_brk_s_th, pmac->cnt_lsig_brk_l_th, 4416 pmac->cnt_sb_search_fail); 4417 p += scnprintf(p, end - p, "AMPDU miss: %d\n\n", pmac->cnt_ampdu_miss); 4418 4419 p += scnprintf(p, end - p, "== TX General\n"); 4420 p += scnprintf(p, end - p, "%s %s\n", 4421 rtw89_ppdu_str(rtwdev, tx_stat->type, tx_stat->subtype), 4422 rtw89_txcmd_str(rtwdev, tx_stat->txcmd)); 4423 4424 p += scnprintf(p, end - p, "BW: %d, TX_SC: %d, TX_PATH_EN: %d, PATH_MAP: 0x%x\n", 4425 20 << tx_stat->bw, tx_stat->txsc, 4426 tx_stat->tx_path_en, tx_stat->path_map); 4427 4428 val = sign_extend32(tx_stat->tmac_txpwr, 8); 4429 p += scnprintf(p, end - p, "TXPWR TMAC: %d,", val >> factor); 4430 4431 reg_nr = min(chip->rf_path_num, ARRAY_SIZE(tx_stat->txpwr)); 4432 for (i = 0; i < reg_nr; i++) { 4433 val = sign_extend32(tx_stat->txpwr[i], 8); 4434 p += scnprintf(p, end - p, " P%d: %d%s", 4435 i, val >> factor, (i < reg_nr - 1) ? "," : ""); 4436 } 4437 p += scnprintf(p, end - p, " dBm\n"); 4438 4439 p += scnprintf(p, end - p, "MCS: %d, STBC: %d\n", 4440 tx_stat->max_mcs, tx_stat->stbc); 4441 4442 p += scnprintf(p, end - p, "Info: ["); 4443 reg_nr = min(physts->tx_info.reg_nr, ARRAY_SIZE(tx_stat->info)); 4444 for (i = 0; i < reg_nr; i++) 4445 p += scnprintf(p, end - p, "0x%08x%s", 4446 tx_stat->info[i], (i < reg_nr - 1) ? ", " : ""); 4447 p += scnprintf(p, end - p, "]\n"); 4448 4449 p += scnprintf(p, end - p, "Common ctrl: ["); 4450 reg_nr = min(physts->tx_common_ctrl.reg_nr, ARRAY_SIZE(tx_stat->common_ctrl)); 4451 for (i = 0; i < reg_nr; i++) 4452 p += scnprintf(p, end - p, "0x%08x%s", 4453 tx_stat->common_ctrl[i], (i < reg_nr - 1) ? ", " : ""); 4454 p += scnprintf(p, end - p, "]\n\n"); 4455 4456 p += scnprintf(p, end - p, "== RX General\n"); 4457 p += scnprintf(p, end - p, 4458 "LDPC: %d, BCC: %d, STBC: %d, SU_NON_BF: %d, SU_BF: %d, MU: %d\n\n", 4459 pkt_stat->rx.ldpc, pkt_stat->rx.bcc, 4460 pkt_stat->rx.stbc, pkt_stat->rx.su_non_bf, 4461 pkt_stat->rx.su_bf, pkt_stat->rx.mu); 4462 4463 p += scnprintf(p, end - p, "== RSSI/RX Rate\n"); 4464 p += rtw89_get_rx_pkt_stat(rtwdev, bb, p, end - p); 4465 4466 return p - buf; 4467 } 4468 4469 static ssize_t 4470 rtw89_debug_priv_bb_info_get(struct rtw89_dev *rtwdev, 4471 struct rtw89_debugfs_priv *debugfs_priv, 4472 char *buf, size_t bufsz) 4473 { 4474 struct rtw89_bb_stat_cfg *bb_stat = &rtwdev->phy_info.bb_stat_cfg; 4475 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4476 const struct rtw89_chip_info *chip = rtwdev->chip; 4477 const struct rtw89_tx_rate_cnt_info *info; 4478 struct rtw89_debugfs_iter_data iter_data; 4479 char *p = buf, *end = buf + bufsz; 4480 struct rtw89_bb_ctx *bb; 4481 int i; 4482 4483 p += scnprintf(p, end - p, "TP TX: %u [%u] Mbps, RX: %u [%u] Mbps\n", 4484 stats->tx_throughput, stats->tx_throughput_raw, 4485 stats->rx_throughput, stats->rx_throughput_raw); 4486 p += scnprintf(p, end - p, "Avg packet length: TX=%u, RX=%u\n", 4487 stats->tx_avg_len, 4488 stats->rx_avg_len); 4489 p += scnprintf(p, end - p, "TF: %u\n", stats->rx_tf_periodic); 4490 4491 if (chip->chip_gen != RTW89_CHIP_AX) { 4492 p += scnprintf(p, end - p, 4493 "TX count [0x%x]:\n", bb_stat->mac_id); 4494 4495 for (i = 0; i < ARRAY_SIZE(rtw89_tx_rate_cnt_infos); i++) { 4496 info = &rtw89_tx_rate_cnt_infos[i]; 4497 4498 p += scnprintf(p, end - p, "%10s [", info->rate_mode); 4499 p += rtw89_debug_append_rate(p, end - p, 4500 rtwdev->phystat.tx_rate_cnt, 4501 info->first_rate, info->len); 4502 p += scnprintf(p, end - p, "]\n"); 4503 } 4504 } 4505 4506 rtw89_for_each_active_bb(rtwdev, bb) 4507 p += rtw89_get_bb_stat(rtwdev, bb, p, end - p); 4508 p += scnprintf(p, end - p, "\n"); 4509 4510 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4511 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, &iter_data); 4512 p += iter_data.written_sz; 4513 4514 return p - buf; 4515 } 4516 4517 static ssize_t 4518 rtw89_debug_priv_bb_info_set(struct rtw89_dev *rtwdev, 4519 struct rtw89_debugfs_priv *debugfs_priv, 4520 const char *buf, size_t count) 4521 { 4522 struct rtw89_bb_stat_cfg *bb_stat = &rtwdev->phy_info.bb_stat_cfg; 4523 int val; 4524 4525 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4526 4527 if (sscanf(buf, "enable %d", &val) == 1) 4528 bb_stat->enable = !!val; 4529 else if (sscanf(buf, "mac_id %x", &val) == 1) 4530 rtw89_fw_h2c_tx_history(rtwdev, val); 4531 else 4532 return -EINVAL; 4533 4534 return count; 4535 } 4536 4537 static int rtw89_dump_addr_cam(struct rtw89_dev *rtwdev, 4538 char *buf, size_t bufsz, 4539 struct rtw89_addr_cam_entry *addr_cam) 4540 { 4541 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4542 const struct rtw89_sec_cam_entry *sec_entry; 4543 char *p = buf, *end = buf + bufsz; 4544 u8 sec_cam_idx; 4545 int i; 4546 4547 p += scnprintf(p, end - p, "\taddr_cam_idx=%u\n", 4548 addr_cam->addr_cam_idx); 4549 p += scnprintf(p, end - p, "\t-> bssid_cam_idx=%u\n", 4550 addr_cam->bssid_cam_idx); 4551 p += scnprintf(p, end - p, "\tsec_cam_bitmap=%*ph\n", 4552 (int)sizeof(addr_cam->sec_cam_map), 4553 addr_cam->sec_cam_map); 4554 for_each_set_bit(i, addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM) { 4555 sec_cam_idx = addr_cam->sec_ent[i]; 4556 sec_entry = cam_info->sec_entries[sec_cam_idx]; 4557 if (!sec_entry) 4558 continue; 4559 p += scnprintf(p, end - p, "\tsec[%d]: sec_cam_idx %u", i, 4560 sec_entry->sec_cam_idx); 4561 if (sec_entry->ext_key) 4562 p += scnprintf(p, end - p, ", %u", 4563 sec_entry->sec_cam_idx + 1); 4564 p += scnprintf(p, end - p, "\n"); 4565 } 4566 4567 return p - buf; 4568 } 4569 4570 __printf(4, 5) 4571 static int rtw89_dump_pkt_offload(char *buf, size_t bufsz, struct list_head *pkt_list, 4572 const char *fmt, ...) 4573 { 4574 char *p = buf, *end = buf + bufsz; 4575 struct rtw89_pktofld_info *info; 4576 struct va_format vaf; 4577 va_list args; 4578 4579 if (list_empty(pkt_list)) 4580 return 0; 4581 4582 va_start(args, fmt); 4583 vaf.va = &args; 4584 vaf.fmt = fmt; 4585 4586 p += scnprintf(p, end - p, "%pV", &vaf); 4587 4588 va_end(args); 4589 4590 list_for_each_entry(info, pkt_list, list) 4591 p += scnprintf(p, end - p, "%d ", info->id); 4592 4593 p += scnprintf(p, end - p, "\n"); 4594 4595 return p - buf; 4596 } 4597 4598 static int rtw89_vif_link_ids_get(struct rtw89_dev *rtwdev, 4599 char *buf, size_t bufsz, u8 *mac, 4600 struct rtw89_vif_link *rtwvif_link, 4601 bool designated) 4602 { 4603 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif_link->bssid_cam; 4604 char *p = buf, *end = buf + bufsz; 4605 4606 p += scnprintf(p, end - p, " [%u] %pM\n", rtwvif_link->mac_id, 4607 rtwvif_link->mac_addr); 4608 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwvif_link->link_id, 4609 designated ? " (*)" : ""); 4610 p += scnprintf(p, end - p, "\tbssid_cam_idx=%u\n", 4611 bssid_cam->bssid_cam_idx); 4612 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwvif_link->addr_cam); 4613 p += rtw89_dump_pkt_offload(p, end - p, &rtwvif_link->general_pkt_list, 4614 "\tpkt_ofld[GENERAL]: "); 4615 4616 return p - buf; 4617 } 4618 4619 static 4620 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 4621 { 4622 struct rtw89_debugfs_iter_data *iter_data = 4623 (struct rtw89_debugfs_iter_data *)data; 4624 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 4625 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 4626 struct rtw89_vif_link *designated_link; 4627 struct rtw89_vif_link *rtwvif_link; 4628 size_t bufsz = iter_data->bufsz; 4629 char *buf = iter_data->buf; 4630 char *p = buf, *end = buf + bufsz; 4631 unsigned int link_id; 4632 4633 designated_link = rtw89_get_designated_link(rtwvif); 4634 4635 p += scnprintf(p, end - p, "VIF %pM\n", rtwvif->mac_addr); 4636 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4637 p += rtw89_vif_link_ids_get(rtwdev, p, end - p, mac, rtwvif_link, 4638 rtwvif_link == designated_link); 4639 4640 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4641 } 4642 4643 static int rtw89_dump_ba_cam(struct rtw89_dev *rtwdev, 4644 char *buf, size_t bufsz, 4645 struct rtw89_sta_link *rtwsta_link) 4646 { 4647 struct rtw89_ba_cam_entry *entry; 4648 char *p = buf, *end = buf + bufsz; 4649 bool first = true; 4650 4651 list_for_each_entry(entry, &rtwsta_link->ba_cam_list, list) { 4652 if (first) { 4653 p += scnprintf(p, end - p, "\tba_cam "); 4654 first = false; 4655 } else { 4656 p += scnprintf(p, end - p, ", "); 4657 } 4658 p += scnprintf(p, end - p, "tid[%u]=%d", entry->tid, 4659 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 4660 } 4661 p += scnprintf(p, end - p, "\n"); 4662 4663 return p - buf; 4664 } 4665 4666 static int rtw89_sta_link_ids_get(struct rtw89_dev *rtwdev, 4667 char *buf, size_t bufsz, 4668 struct rtw89_sta_link *rtwsta_link, 4669 bool designated) 4670 { 4671 struct ieee80211_link_sta *link_sta; 4672 char *p = buf, *end = buf + bufsz; 4673 4674 rcu_read_lock(); 4675 4676 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4677 4678 p += scnprintf(p, end - p, " [%u] %pM\n", rtwsta_link->mac_id, 4679 link_sta->addr); 4680 4681 rcu_read_unlock(); 4682 4683 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwsta_link->link_id, 4684 designated ? " (*)" : ""); 4685 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwsta_link->addr_cam); 4686 p += rtw89_dump_ba_cam(rtwdev, p, end - p, rtwsta_link); 4687 4688 return p - buf; 4689 } 4690 4691 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 4692 { 4693 struct rtw89_debugfs_iter_data *iter_data = 4694 (struct rtw89_debugfs_iter_data *)data; 4695 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4696 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4697 struct rtw89_sta_link *designated_link; 4698 struct rtw89_sta_link *rtwsta_link; 4699 size_t bufsz = iter_data->bufsz; 4700 char *buf = iter_data->buf; 4701 char *p = buf, *end = buf + bufsz; 4702 unsigned int link_id; 4703 4704 designated_link = rtw89_get_designated_link(rtwsta); 4705 4706 p += scnprintf(p, end - p, "STA %pM %s\n", sta->addr, 4707 sta->tdls ? "(TDLS)" : ""); 4708 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 4709 p += rtw89_sta_link_ids_get(rtwdev, p, end - p, rtwsta_link, 4710 rtwsta_link == designated_link); 4711 4712 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4713 } 4714 4715 static ssize_t rtw89_debug_priv_stations_get(struct rtw89_dev *rtwdev, 4716 struct rtw89_debugfs_priv *debugfs_priv, 4717 char *buf, size_t bufsz) 4718 { 4719 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4720 struct rtw89_debugfs_iter_data iter_data; 4721 char *p = buf, *end = buf + bufsz; 4722 u8 idx; 4723 4724 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4725 4726 p += scnprintf(p, end - p, "map:\n"); 4727 p += scnprintf(p, end - p, "\tmac_id: %*ph\n", 4728 (int)sizeof(rtwdev->mac_id_map), 4729 rtwdev->mac_id_map); 4730 p += scnprintf(p, end - p, "\taddr_cam: %*ph\n", 4731 (int)sizeof(cam_info->addr_cam_map), 4732 cam_info->addr_cam_map); 4733 p += scnprintf(p, end - p, "\tbssid_cam: %*ph\n", 4734 (int)sizeof(cam_info->bssid_cam_map), 4735 cam_info->bssid_cam_map); 4736 p += scnprintf(p, end - p, "\tsec_cam: %*ph\n", 4737 (int)sizeof(cam_info->sec_cam_map), 4738 cam_info->sec_cam_map); 4739 p += scnprintf(p, end - p, "\tba_cam: %*ph\n", 4740 (int)sizeof(cam_info->ba_cam_map), 4741 cam_info->ba_cam_map); 4742 p += scnprintf(p, end - p, "\tpkt_ofld: %*ph\n", 4743 (int)sizeof(rtwdev->pkt_offload), 4744 rtwdev->pkt_offload); 4745 4746 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 4747 if (!(rtwdev->chip->support_bands & BIT(idx))) 4748 continue; 4749 p += rtw89_dump_pkt_offload(p, end - p, &rtwdev->scan_info.pkt_list[idx], 4750 "\t\t[SCAN %u]: ", idx); 4751 } 4752 4753 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4754 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 4755 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, &iter_data); 4756 p += iter_data.written_sz; 4757 4758 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4759 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, &iter_data); 4760 p += iter_data.written_sz; 4761 4762 return p - buf; 4763 } 4764 4765 #define DM_INFO(type) {RTW89_DM_ ## type, #type} 4766 4767 static const struct rtw89_disabled_dm_info { 4768 enum rtw89_dm_type type; 4769 const char *name; 4770 } rtw89_disabled_dm_infos[] = { 4771 DM_INFO(DYNAMIC_EDCCA), 4772 DM_INFO(THERMAL_PROTECT), 4773 DM_INFO(TAS), 4774 DM_INFO(MLO), 4775 DM_INFO(HW_SCAN), 4776 DM_INFO(INACTIVE_PS), 4777 DM_INFO(DIG_PD), 4778 DM_INFO(VCORE), 4779 }; 4780 4781 static ssize_t 4782 rtw89_debug_priv_disable_dm_get(struct rtw89_dev *rtwdev, 4783 struct rtw89_debugfs_priv *debugfs_priv, 4784 char *buf, size_t bufsz) 4785 { 4786 const struct rtw89_disabled_dm_info *info; 4787 struct rtw89_hal *hal = &rtwdev->hal; 4788 char *p = buf, *end = buf + bufsz; 4789 u32 disabled; 4790 int i; 4791 4792 p += scnprintf(p, end - p, "Disabled DM: 0x%x\n", 4793 hal->disabled_dm_bitmap); 4794 4795 for (i = 0; i < ARRAY_SIZE(rtw89_disabled_dm_infos); i++) { 4796 info = &rtw89_disabled_dm_infos[i]; 4797 disabled = BIT(info->type) & hal->disabled_dm_bitmap; 4798 4799 p += scnprintf(p, end - p, "[%d] %s: %c\n", info->type, 4800 info->name, 4801 disabled ? 'X' : 'O'); 4802 } 4803 4804 return p - buf; 4805 } 4806 4807 static ssize_t 4808 rtw89_debug_priv_disable_dm_set(struct rtw89_dev *rtwdev, 4809 struct rtw89_debugfs_priv *debugfs_priv, 4810 const char *buf, size_t count) 4811 { 4812 u32 conf; 4813 int ret; 4814 4815 ret = kstrtou32(buf, 0, &conf); 4816 if (ret) 4817 return -EINVAL; 4818 4819 rtw89_core_dm_disable_cfg(rtwdev, conf); 4820 4821 return count; 4822 } 4823 4824 #define RTW89_DIG_PD_TH_MIN_DBM -102 4825 #define RTW89_DIG_PD_TH_MAX_DBM -40 4826 #define RTW89_DIG_PD_TH_STEP 2 4827 4828 static s8 rtw89_dig_pd_th_to_dbm(u8 reg_val) 4829 { 4830 return RTW89_DIG_PD_TH_MIN_DBM + RTW89_DIG_PD_TH_STEP * reg_val; 4831 } 4832 4833 static u8 rtw89_dig_pd_th_dbm_to_reg(s8 dbm) 4834 { 4835 return (dbm - RTW89_DIG_PD_TH_MIN_DBM) / RTW89_DIG_PD_TH_STEP; 4836 } 4837 4838 static ssize_t 4839 rtw89_debug_priv_static_pd_th_get(struct rtw89_dev *rtwdev, 4840 struct rtw89_debugfs_priv *debugfs_priv, 4841 char *buf, size_t bufsz) 4842 { 4843 struct rtw89_hal *hal = &rtwdev->hal; 4844 char *p = buf, *end = buf + bufsz; 4845 bool disabled; 4846 s8 pd_th_dbm; 4847 s8 cck_pd_th; 4848 4849 disabled = hal->disabled_dm_bitmap & BIT(RTW89_DM_DIG_PD); 4850 4851 if (disabled) { 4852 pd_th_dbm = rtw89_dig_pd_th_to_dbm(hal->fixed_dig_pd_th); 4853 cck_pd_th = hal->fixed_dig_cck_pd_th; 4854 4855 p += scnprintf(p, end - p, "DIG: static\n"); 4856 p += scnprintf(p, end - p, "OFDM PD threshold: %d dBm\n", pd_th_dbm); 4857 p += scnprintf(p, end - p, "CCK PD threshold: %d dBm\n", cck_pd_th); 4858 } else { 4859 p += scnprintf(p, end - p, "DIG: dynamic\n"); 4860 } 4861 4862 p += scnprintf(p, end - p, "\nUsage: echo <mode> [pd_th] > static_pd_th\n"); 4863 p += scnprintf(p, end - p, " mode: 0 = dynamic, 1 = static\n"); 4864 p += scnprintf(p, end - p, " pd_th: PD threshold in dBm (-102 ~ -40)\n"); 4865 4866 return p - buf; 4867 } 4868 4869 static ssize_t 4870 rtw89_debug_priv_static_pd_th_set(struct rtw89_dev *rtwdev, 4871 struct rtw89_debugfs_priv *debugfs_priv, 4872 const char *buf, size_t count) 4873 { 4874 struct rtw89_hal *hal = &rtwdev->hal; 4875 int ret; 4876 u32 mode; 4877 s32 pd_th_dbm; 4878 4879 ret = sscanf(buf, "%u %d", &mode, &pd_th_dbm); 4880 if (ret < 1) 4881 return -EINVAL; 4882 4883 if (mode > 1) 4884 return -EINVAL; 4885 4886 if (mode == 0) { 4887 rtw89_core_dm_disable_clr(rtwdev, RTW89_DM_DIG_PD); 4888 hal->fixed_dig_pd_th = 0; 4889 hal->fixed_dig_cck_pd_th = 0; 4890 4891 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4892 "DIG static mode disabled\n"); 4893 } else { 4894 if (ret < 2 || pd_th_dbm < RTW89_DIG_PD_TH_MIN_DBM || 4895 pd_th_dbm > RTW89_DIG_PD_TH_MAX_DBM) 4896 return -EINVAL; 4897 4898 rtw89_core_dm_disable_set(rtwdev, RTW89_DM_DIG_PD); 4899 hal->fixed_dig_pd_th = clamp(rtw89_dig_pd_th_dbm_to_reg(pd_th_dbm), 4900 0, 0x1f); 4901 /* CCK uses dBm directly */ 4902 hal->fixed_dig_cck_pd_th = pd_th_dbm; 4903 4904 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4905 "DIG static mode: PD=0x%02x (%d dBm), CCK=%d dBm\n", 4906 hal->fixed_dig_pd_th, 4907 rtw89_dig_pd_th_to_dbm(hal->fixed_dig_pd_th), 4908 hal->fixed_dig_cck_pd_th); 4909 } 4910 4911 return count; 4912 } 4913 4914 static void rtw89_debug_mlo_mode_set_mlsr(struct rtw89_dev *rtwdev, 4915 unsigned int link_id) 4916 { 4917 struct ieee80211_vif *vif; 4918 struct rtw89_vif *rtwvif; 4919 4920 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4921 vif = rtwvif_to_vif(rtwvif); 4922 if (!ieee80211_vif_is_mld(vif)) 4923 continue; 4924 4925 rtw89_core_mlsr_switch(rtwdev, rtwvif, link_id); 4926 } 4927 } 4928 4929 static ssize_t 4930 rtw89_debug_priv_mlo_mode_get(struct rtw89_dev *rtwdev, 4931 struct rtw89_debugfs_priv *debugfs_priv, 4932 char *buf, size_t bufsz) 4933 { 4934 bool mlo_dm_dis = rtwdev->hal.disabled_dm_bitmap & BIT(RTW89_DM_MLO); 4935 char *p = buf, *end = buf + bufsz; 4936 struct ieee80211_vif *vif; 4937 struct rtw89_vif *rtwvif; 4938 int count = 0; 4939 4940 p += scnprintf(p, end - p, "MLD(s) status: (MLO DM: %s)\n", 4941 str_disable_enable(mlo_dm_dis)); 4942 4943 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4944 vif = rtwvif_to_vif(rtwvif); 4945 if (!ieee80211_vif_is_mld(vif)) 4946 continue; 4947 4948 p += scnprintf(p, end - p, 4949 "\t#%u: MLO mode %x, valid 0x%x, active 0x%x\n", 4950 count++, rtwvif->mlo_mode, vif->valid_links, 4951 vif->active_links); 4952 } 4953 4954 if (count == 0) 4955 p += scnprintf(p, end - p, "\t(None)\n"); 4956 4957 return p - buf; 4958 } 4959 4960 static ssize_t 4961 rtw89_debug_priv_mlo_mode_set(struct rtw89_dev *rtwdev, 4962 struct rtw89_debugfs_priv *debugfs_priv, 4963 const char *buf, size_t count) 4964 { 4965 u8 num, mlo_mode; 4966 u32 argv; 4967 4968 num = sscanf(buf, "%hhx %u", &mlo_mode, &argv); 4969 if (num != 2) 4970 return -EINVAL; 4971 4972 rtw89_core_dm_disable_set(rtwdev, RTW89_DM_MLO); 4973 4974 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Set MLO mode to %x\n", mlo_mode); 4975 4976 switch (mlo_mode) { 4977 case RTW89_MLO_MODE_MLSR: 4978 rtw89_debug_mlo_mode_set_mlsr(rtwdev, argv); 4979 break; 4980 default: 4981 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Unsupported MLO mode\n"); 4982 rtw89_core_dm_disable_clr(rtwdev, RTW89_DM_MLO); 4983 4984 return -EOPNOTSUPP; 4985 } 4986 4987 return count; 4988 } 4989 4990 static int rtw89_get_beacon_info(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb, 4991 char *buf, size_t bufsz) 4992 { 4993 struct rtw89_pkt_stat *pkt_stat = &bb->last_pkt_stat; 4994 char *p = buf, *end = buf + bufsz; 4995 4996 p += scnprintf(p, end - p, "[PHY %u]\n", bb->phy_idx); 4997 p += scnprintf(p, end - p, "Beacon: %u\n", pkt_stat->beacon_nr); 4998 p += scnprintf(p, end - p, "raw rssi: %lu\n", ewma_rssi_read(&bb->bcn_rssi)); 4999 p += scnprintf(p, end - p, "hw rate: %u\n", pkt_stat->beacon_rate); 5000 p += scnprintf(p, end - p, "length: %u\n\n", pkt_stat->beacon_len); 5001 5002 return p - buf; 5003 } 5004 5005 static ssize_t 5006 rtw89_debug_priv_beacon_info_get(struct rtw89_dev *rtwdev, 5007 struct rtw89_debugfs_priv *debugfs_priv, 5008 char *buf, size_t bufsz) 5009 { 5010 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 5011 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 5012 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 5013 u16 upper, lower = bcn_stat->tbtt_tu_min; 5014 char *p = buf, *end = buf + bufsz; 5015 u16 *drift = bcn_stat->drift; 5016 u8 bcn_num = bcn_stat->num; 5017 struct rtw89_bb_ctx *bb; 5018 u8 count; 5019 u8 i; 5020 5021 rtw89_for_each_active_bb(rtwdev, bb) 5022 p += rtw89_get_beacon_info(rtwdev, bb, p, end - p); 5023 5024 p += scnprintf(p, end - p, "[Beacon info]\n"); 5025 p += scnprintf(p, end - p, "interval: %u\n", bcn_track->beacon_int); 5026 p += scnprintf(p, end - p, "dtim: %u\n", bcn_track->dtim); 5027 5028 p += scnprintf(p, end - p, "\n[Distribution]\n"); 5029 p += scnprintf(p, end - p, "tbtt\n"); 5030 for (i = 0; i < RTW89_BCN_TRACK_MAX_BIN_NUM; i++) { 5031 upper = lower + RTW89_BCN_TRACK_BIN_WIDTH - 1; 5032 if (i == RTW89_BCN_TRACK_MAX_BIN_NUM - 1) 5033 upper = max(upper, bcn_stat->tbtt_tu_max); 5034 5035 p += scnprintf(p, end - p, "%02u - %02u: %u\n", 5036 lower, upper, bcn_dist->bins[i]); 5037 5038 lower = upper + 1; 5039 } 5040 5041 p += scnprintf(p, end - p, "\ndrift\n"); 5042 5043 for (i = 0; i < bcn_num; i += count) { 5044 count = 1; 5045 while (i + count < bcn_num && drift[i] == drift[i + count]) 5046 count++; 5047 5048 p += scnprintf(p, end - p, "%u: %u\n", drift[i], count); 5049 } 5050 p += scnprintf(p, end - p, "\nlower bound: %u\n", bcn_dist->lower_bound); 5051 p += scnprintf(p, end - p, "upper bound: %u\n", bcn_dist->upper_bound); 5052 p += scnprintf(p, end - p, "outlier count: %u\n", bcn_dist->outlier_count); 5053 5054 p += scnprintf(p, end - p, "\n[Tracking]\n"); 5055 p += scnprintf(p, end - p, "tbtt offset: %u\n", bcn_track->tbtt_offset); 5056 p += scnprintf(p, end - p, "bcn timeout: %u\n", bcn_track->bcn_timeout); 5057 5058 return p - buf; 5059 } 5060 5061 enum __diag_mac_cmd { 5062 __CMD_EQUALV, 5063 __CMD_EQUALO, 5064 __CMD_NEQUALV, 5065 __CMD_NEQUALO, 5066 __CMD_SETEQUALV, 5067 __CMD_SETEQUALO, 5068 __CMD_CMPWCR, 5069 __CMD_CMPWWD, 5070 __CMD_NEQ_CMPWCR, 5071 __CMD_NEQ_CMPWWD, 5072 __CMD_INCREMENT, 5073 __CMD_MESSAGE, 5074 }; 5075 5076 enum __diag_mac_io { 5077 __IO_NORMAL, 5078 __IO_NORMAL_PCIE, 5079 __IO_NORMAL_USB, 5080 __IO_NORMAL_SDIO, 5081 __IO_PCIE_CFG, 5082 __IO_SDIO_CCCR, 5083 }; 5084 5085 struct __diag_mac_rule_header { 5086 u8 sheet; 5087 u8 cmd; 5088 u8 seq_major; 5089 u8 seq_minor; 5090 u8 io_band; 5091 #define __DIAG_MAC_IO GENMASK(3, 0) 5092 #define __DIAG_MAC_N_BAND BIT(4) 5093 #define __DIAG_MAC_HAS_BAND BIT(5) 5094 u8 len; /* include header. Unit: 4 bytes */ 5095 u8 rsvd[2]; 5096 } __packed; 5097 5098 struct __diag_mac_rule_equal { 5099 struct __diag_mac_rule_header header; 5100 __le32 addr; 5101 __le32 addr_name_offset; 5102 __le32 mask; 5103 __le32 val; 5104 __le32 msg_offset; 5105 u8 rsvd[4]; 5106 } __packed; 5107 5108 struct __diag_mac_rule_increment { 5109 struct __diag_mac_rule_header header; 5110 __le32 addr; 5111 __le32 addr_name_offset; 5112 __le32 mask; 5113 __le16 sel; 5114 __le16 delay; 5115 __le32 msg_offset; 5116 u8 rsvd[4]; 5117 } __packed; 5118 5119 struct __diag_mac_msg_buf { 5120 __le16 len; 5121 char string[]; 5122 } __packed; 5123 5124 static ssize_t rtw89_mac_diag_do_equalv(struct rtw89_dev *rtwdev, 5125 char *buf, size_t bufsz, 5126 const struct __diag_mac_rule_equal *r, 5127 const void *msg_start, 5128 u64 *positive_bmp) 5129 { 5130 const struct __diag_mac_msg_buf *name = msg_start + 5131 le32_to_cpu(r->addr_name_offset); 5132 const struct __diag_mac_msg_buf *msg = msg_start + 5133 le32_to_cpu(r->msg_offset); 5134 bool want_eq = r->header.cmd == __CMD_EQUALV; 5135 char *p = buf, *end = buf + bufsz; 5136 bool equal = false; 5137 u32 val; 5138 5139 *positive_bmp <<= 1; 5140 5141 if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG) 5142 val = rtw89_read32_pci_cfg(rtwdev, le32_to_cpu(r->addr)); 5143 else 5144 val = rtw89_read32(rtwdev, le32_to_cpu(r->addr)); 5145 5146 if ((val & le32_to_cpu(r->mask)) == le32_to_cpu(r->val)) 5147 equal = true; 5148 5149 if (want_eq == equal) { 5150 *positive_bmp |= BIT(0); 5151 return p - buf; 5152 } 5153 5154 p += scnprintf(p, end - p, "sheet: %d, cmd: %d, Reg: %.*s => %x, %.*s\n", 5155 r->header.sheet, r->header.cmd, le16_to_cpu(name->len), 5156 name->string, val, le16_to_cpu(msg->len), msg->string); 5157 5158 return p - buf; 5159 } 5160 5161 static ssize_t rtw89_mac_diag_do_increment(struct rtw89_dev *rtwdev, 5162 char *buf, size_t bufsz, 5163 const struct __diag_mac_rule_increment *r, 5164 const void *msg_start, 5165 u64 *positive_bmp) 5166 { 5167 const struct __diag_mac_msg_buf *name = msg_start + 5168 le32_to_cpu(r->addr_name_offset); 5169 const struct __diag_mac_msg_buf *msg = msg_start + 5170 le32_to_cpu(r->msg_offset); 5171 char *p = buf, *end = buf + bufsz; 5172 u32 addr = le32_to_cpu(r->addr); 5173 u32 mask = le32_to_cpu(r->mask); 5174 u16 sel = le16_to_cpu(r->sel); 5175 u32 val1, val2; 5176 5177 *positive_bmp <<= 1; 5178 5179 rtw89_write32(rtwdev, addr, sel); 5180 5181 if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG) 5182 val1 = rtw89_read32_pci_cfg(rtwdev, addr); 5183 else 5184 val1 = rtw89_read32(rtwdev, addr); 5185 5186 mdelay(le16_to_cpu(r->delay)); 5187 5188 if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG) 5189 val2 = rtw89_read32_pci_cfg(rtwdev, addr); 5190 else 5191 val2 = rtw89_read32(rtwdev, addr); 5192 5193 if ((val2 & mask) > (val1 & mask)) { 5194 *positive_bmp |= BIT(0); 5195 return p - buf; 5196 } 5197 5198 p += scnprintf(p, end - p, "sheet: %d, cmd: %d, Reg: %.*s [%d]=> %x, %.*s\n", 5199 r->header.sheet, r->header.cmd, le16_to_cpu(name->len), 5200 name->string, le16_to_cpu(r->sel), val1, 5201 le16_to_cpu(msg->len), msg->string); 5202 5203 return p - buf; 5204 } 5205 5206 static bool rtw89_mac_diag_match_hci(struct rtw89_dev *rtwdev, 5207 const struct __diag_mac_rule_header *rh) 5208 { 5209 switch (u8_get_bits(rh->io_band, __DIAG_MAC_IO)) { 5210 case __IO_NORMAL: 5211 default: 5212 return true; 5213 case __IO_NORMAL_PCIE: 5214 case __IO_PCIE_CFG: 5215 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) 5216 return true; 5217 break; 5218 case __IO_NORMAL_USB: 5219 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 5220 return true; 5221 break; 5222 case __IO_NORMAL_SDIO: 5223 case __IO_SDIO_CCCR: 5224 if (rtwdev->hci.type == RTW89_HCI_TYPE_SDIO) 5225 return true; 5226 break; 5227 } 5228 5229 return false; 5230 } 5231 5232 static bool rtw89_mac_diag_match_band(struct rtw89_dev *rtwdev, 5233 const struct __diag_mac_rule_header *rh) 5234 { 5235 u8 active_bands; 5236 bool has_band; 5237 u8 band; 5238 5239 has_band = u8_get_bits(rh->io_band, __DIAG_MAC_HAS_BAND); 5240 if (!has_band) 5241 return true; 5242 5243 band = u8_get_bits(rh->io_band, __DIAG_MAC_N_BAND); 5244 active_bands = rtw89_get_active_phy_bitmap(rtwdev); 5245 5246 if (active_bands & BIT(band)) 5247 return true; 5248 5249 return false; 5250 } 5251 5252 static ssize_t rtw89_mac_diag_iter_all(struct rtw89_dev *rtwdev, 5253 char *buf, size_t bufsz) 5254 { 5255 const struct rtw89_fw_element_hdr *elm = rtwdev->fw.elm_info.diag_mac; 5256 u32 n_plains = 0, n_rules = 0, n_positive = 0, n_ignore = 0; 5257 char *p = buf, *end = buf + bufsz, *p_rewind; 5258 const void *rule, *rule_end; 5259 u32 elm_size, rule_size; 5260 const void *msg_start; 5261 u64 positive_bmp = 0; 5262 u8 prev_sheet = 0; 5263 u8 prev_seq = 0; 5264 int limit; 5265 5266 if (!elm) { 5267 p += scnprintf(p, end - p, "No diag_mac entry\n"); 5268 goto out; 5269 } 5270 5271 rule_size = le32_to_cpu(elm->u.diag_mac.rule_size); 5272 elm_size = le32_to_cpu(elm->size); 5273 5274 if (ALIGN(rule_size, 16) > elm_size) { 5275 p += scnprintf(p, end - p, "rule size (%u) exceed elm_size (%u)\n", 5276 ALIGN(rule_size, 16), elm_size); 5277 goto out; 5278 } 5279 5280 rule = &elm->u.diag_mac.rules_and_msgs[0]; 5281 rule_end = &elm->u.diag_mac.rules_and_msgs[rule_size]; 5282 msg_start = &elm->u.diag_mac.rules_and_msgs[ALIGN(rule_size, 16)]; 5283 5284 for (limit = 0; limit < 5000 && rule < rule_end; limit++) { 5285 const struct __diag_mac_rule_header *rh = rule; 5286 u8 sheet = rh->sheet; 5287 u8 seq = rh->seq_major; 5288 5289 if (!rtw89_mac_diag_match_hci(rtwdev, rh) || 5290 !rtw89_mac_diag_match_band(rtwdev, rh)) { 5291 n_ignore++; 5292 goto next; 5293 } 5294 5295 if (!seq || prev_sheet != sheet || prev_seq != seq) { 5296 if (positive_bmp) { 5297 n_positive++; 5298 /* 5299 * discard output for negative results if one in 5300 * a sequence set is positive. 5301 */ 5302 if (p_rewind) 5303 p = p_rewind; 5304 } 5305 p_rewind = seq ? p : NULL; 5306 positive_bmp = 0; 5307 n_rules++; 5308 } 5309 5310 switch (rh->cmd) { 5311 case __CMD_EQUALV: 5312 case __CMD_NEQUALV: 5313 p += rtw89_mac_diag_do_equalv(rtwdev, p, end - p, rule, 5314 msg_start, &positive_bmp); 5315 break; 5316 case __CMD_INCREMENT: 5317 p += rtw89_mac_diag_do_increment(rtwdev, p, end - p, rule, 5318 msg_start, &positive_bmp); 5319 break; 5320 default: 5321 p += scnprintf(p, end - p, "unknown rule cmd %u\n", rh->cmd); 5322 break; 5323 } 5324 5325 next: 5326 n_plains++; 5327 rule += rh->len * 4; 5328 prev_seq = seq; 5329 prev_sheet = sheet; 5330 } 5331 5332 if (positive_bmp) { 5333 n_positive++; 5334 if (p_rewind) 5335 p = p_rewind; 5336 } 5337 5338 p += scnprintf(p, end - p, "\nPlain(Ignore)/Rules/Positive: %u(%u)/%u/%u\n", 5339 n_plains, n_ignore, n_rules, n_positive); 5340 5341 out: 5342 return p - buf; 5343 } 5344 5345 static ssize_t 5346 rtw89_debug_priv_diag_mac_get(struct rtw89_dev *rtwdev, 5347 struct rtw89_debugfs_priv *debugfs_priv, 5348 char *buf, size_t bufsz) 5349 { 5350 lockdep_assert_wiphy(rtwdev->hw->wiphy); 5351 5352 rtw89_leave_lps(rtwdev); 5353 5354 return rtw89_mac_diag_iter_all(rtwdev, buf, bufsz); 5355 } 5356 5357 static int rtw89_get_diag_bb(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb, 5358 char *buf, size_t bufsz) 5359 { 5360 struct rtw89_diag_bb *diag = &bb->diag; 5361 char *p = buf, *end = buf + bufsz; 5362 5363 p += scnprintf(p, end - p, "[PHY %u]\n", bb->phy_idx); 5364 p += scnprintf(p, end - p, "Diag bitmap = 0x%x\n", diag->diag_bb_bitmap); 5365 p += scnprintf(p, end - p, 5366 "Event{Hang, PD MAX, No RX, High FA, High EDCCA Ratio} = "); 5367 p += scnprintf(p, end - p, "{%d, %d, %d, %d, %d}\n", 5368 diag->diag_bb_cnt[RTW89_DIAG_BB_HANG], 5369 diag->diag_bb_cnt[RTW89_DIAG_BB_PD], 5370 diag->diag_bb_cnt[RTW89_DIAG_BB_NO_RX], 5371 diag->diag_bb_cnt[RTW89_DIAG_BB_FA], 5372 diag->diag_bb_cnt[RTW89_DIAG_BB_EDCCA]); 5373 p += scnprintf(p, end - p, 5374 "consecutive_no_tx_cnt=%d, consecutive_no_rx_cnt=%d\n\n", 5375 diag->consecutive_no_tx_cnt, 5376 diag->consecutive_no_rx_cnt); 5377 5378 return p - buf; 5379 } 5380 5381 static ssize_t 5382 rtw89_debug_priv_diag_bb_get(struct rtw89_dev *rtwdev, 5383 struct rtw89_debugfs_priv *debugfs_priv, 5384 char *buf, size_t bufsz) 5385 { 5386 char *p = buf, *end = buf + bufsz; 5387 struct rtw89_bb_ctx *bb; 5388 5389 lockdep_assert_wiphy(rtwdev->hw->wiphy); 5390 5391 rtw89_for_each_active_bb(rtwdev, bb) 5392 p += rtw89_get_diag_bb(rtwdev, bb, p, end - p); 5393 5394 return p - buf; 5395 } 5396 5397 static ssize_t 5398 rtw89_debug_priv_diag_rf_get(struct rtw89_dev *rtwdev, 5399 struct rtw89_debugfs_priv *debugfs_priv, 5400 char *buf, size_t bufsz) 5401 { 5402 struct rtw89_rfk_wait_info *info = &rtwdev->rfk_wait; 5403 char *p = buf, *end = buf + bufsz; 5404 int i, j; 5405 5406 p += scnprintf(p, end - p, "RFK (next index: %d)\n", info->record_idx); 5407 5408 p += scnprintf(p, end - p, " PHY-X ="); 5409 for (i = 0; i < RTW89_RFK_RECORD_HISTORY_NR; i++) { 5410 struct rtw89_rfk_record *record = &info->records[i]; 5411 5412 p += scnprintf(p, end - p, " %4d ", record->phy_idx); 5413 } 5414 p += scnprintf(p, end - p, "\n"); 5415 5416 for (j = 0; j < RTW89_RFK_RECORD_PATH_NR; j++) { 5417 p += scnprintf(p, end - p, " S%d-CH =", j); 5418 for (i = 0; i < RTW89_RFK_RECORD_HISTORY_NR; i++) { 5419 struct rtw89_rfk_record *record = &info->records[i]; 5420 5421 p += scnprintf(p, end - p, " %05x", record->ch[j]); 5422 } 5423 p += scnprintf(p, end - p, "\n"); 5424 5425 p += scnprintf(p, end - p, " S%d-CV =", j); 5426 for (i = 0; i < RTW89_RFK_RECORD_HISTORY_NR; i++) { 5427 struct rtw89_rfk_record *record = &info->records[i]; 5428 5429 p += scnprintf(p, end - p, " %05x", record->cv[j]); 5430 } 5431 p += scnprintf(p, end - p, "\n"); 5432 5433 p += scnprintf(p, end - p, " S%d-C5 =", j); 5434 for (i = 0; i < RTW89_RFK_RECORD_HISTORY_NR; i++) { 5435 struct rtw89_rfk_record *record = &info->records[i]; 5436 5437 p += scnprintf(p, end - p, " %05x", record->c5[j]); 5438 } 5439 p += scnprintf(p, end - p, "\n"); 5440 } 5441 5442 for (j = 0; j < NUM_OF_RTW89_RFK_REPORT_TYPES; j++) { 5443 p += scnprintf(p, end - p, " %-8s =", rtw89_rfk_report_names[j]); 5444 for (i = 0; i < RTW89_RFK_RECORD_HISTORY_NR; i++) { 5445 struct rtw89_rfk_record *record = &info->records[i]; 5446 5447 p += scnprintf(p, end - p, " %4d ", record->states[j]); 5448 } 5449 p += scnprintf(p, end - p, "\n"); 5450 } 5451 5452 p += scnprintf(p, end - p, "TSSI-track (next index: %d)\n", info->record_tssi_idx); 5453 5454 for (j = 0; j < RTW89_RFK_RECORD_PATH_NR; j++) { 5455 p += scnprintf(p, end - p, " S%d =", j); 5456 for (i = 0; i < RTW89_RFK_RECORD_HISTORY_NR; i++) 5457 p += scnprintf(p, end - p, " %03x", info->tssi_code[i][j]); 5458 p += scnprintf(p, end - p, "\n"); 5459 } 5460 5461 return p - buf; 5462 } 5463 5464 static void rtw89_dbg_diag_rf_set_rfk(struct rtw89_dev *rtwdev) 5465 { 5466 struct rtw89_entity_mgnt *mgnt = &rtwdev->hal.entity_mgnt; 5467 struct rtw89_vif_link *rtwvif_link; 5468 struct rtw89_vif *rtwvif; 5469 unsigned int link_id; 5470 5471 list_for_each_entry(rtwvif, &mgnt->active_list, mgnt_entry) 5472 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 5473 rtw89_chip_rfk_channel(rtwdev, rtwvif_link); 5474 } 5475 5476 enum rtw89_dbg_diag_rf_type { 5477 RTW89_DBG_DIAG_RF_RSVD = 0, 5478 RTW89_DBG_DIAG_RF_RFK = 1, 5479 }; 5480 5481 static ssize_t 5482 rtw89_debug_priv_diag_rf_set(struct rtw89_dev *rtwdev, 5483 struct rtw89_debugfs_priv *debugfs_priv, 5484 const char *buf, size_t count) 5485 { 5486 u8 type; 5487 int ret; 5488 5489 ret = kstrtou8(buf, 0, &type); 5490 if (ret) 5491 return -EINVAL; 5492 5493 if (rtwdev->scanning) 5494 rtw89_hw_scan_abort(rtwdev, rtwdev->scan_info.scanning_vif); 5495 5496 rtw89_leave_ps_mode(rtwdev); 5497 5498 switch (type) { 5499 case RTW89_DBG_DIAG_RF_RFK: 5500 rtw89_dbg_diag_rf_set_rfk(rtwdev); 5501 break; 5502 default: 5503 return -EOPNOTSUPP; 5504 } 5505 5506 return count; 5507 } 5508 5509 static ssize_t 5510 rtw89_debug_priv_monitor_opts_get(struct rtw89_dev *rtwdev, 5511 struct rtw89_debugfs_priv *debugfs_priv, 5512 char *buf, size_t bufsz) 5513 { 5514 const struct rtw89_chip_info *chip = rtwdev->chip; 5515 char *p = buf, *end = buf + bufsz; 5516 u32 bss_color; 5517 u32 aid; 5518 5519 lockdep_assert_wiphy(rtwdev->hw->wiphy); 5520 5521 rtw89_leave_ps_mode(rtwdev); 5522 5523 bss_color = rtw89_phy_read32_idx(rtwdev, chip->bss_clr_map_reg, 5524 B_BSS_CLR_MAP_TGT, RTW89_PHY_0); 5525 aid = rtw89_phy_read32_idx(rtwdev, chip->bss_clr_map_reg, 5526 B_BSS_CLR_MAP_STAID, RTW89_PHY_0); 5527 5528 p += scnprintf(p, end - p, "bss_color=0x%x aid=0x%x\n", bss_color, aid); 5529 5530 return p - buf; 5531 } 5532 5533 static ssize_t 5534 rtw89_debug_priv_monitor_opts_set(struct rtw89_dev *rtwdev, 5535 struct rtw89_debugfs_priv *debugfs_priv, 5536 const char *buf, size_t count) 5537 { 5538 u32 bss_color; 5539 u32 aid; 5540 int num; 5541 5542 lockdep_assert_wiphy(rtwdev->hw->wiphy); 5543 5544 num = sscanf(buf, "%x %x", &bss_color, &aid); 5545 if (num != 2) { 5546 rtw89_info(rtwdev, "valid format: <bss color> <aid>\n"); 5547 return -EINVAL; 5548 } 5549 5550 rtw89_leave_ps_mode(rtwdev); 5551 5552 __rtw89_phy_set_bss_color(rtwdev, bss_color, aid, RTW89_PHY_0); 5553 5554 return count; 5555 } 5556 5557 #define rtw89_debug_priv_get(name, opts...) \ 5558 { \ 5559 .cb_read = rtw89_debug_priv_ ##name## _get, \ 5560 .opt = { opts }, \ 5561 } 5562 5563 #define rtw89_debug_priv_set(name, opts...) \ 5564 { \ 5565 .cb_write = rtw89_debug_priv_ ##name## _set, \ 5566 .opt = { opts }, \ 5567 } 5568 5569 #define rtw89_debug_priv_select_and_get(name, opts...) \ 5570 { \ 5571 .cb_write = rtw89_debug_priv_ ##name## _select, \ 5572 .cb_read = rtw89_debug_priv_ ##name## _get, \ 5573 .opt = { opts }, \ 5574 } 5575 5576 #define rtw89_debug_priv_set_and_get(name, opts...) \ 5577 { \ 5578 .cb_write = rtw89_debug_priv_ ##name## _set, \ 5579 .cb_read = rtw89_debug_priv_ ##name## _get, \ 5580 .opt = { opts }, \ 5581 } 5582 5583 #define RSIZE_8K .rsize = 0x2000 5584 #define RSIZE_12K .rsize = 0x3000 5585 #define RSIZE_16K .rsize = 0x4000 5586 #define RSIZE_20K .rsize = 0x5000 5587 #define RSIZE_32K .rsize = 0x8000 5588 #define RSIZE_64K .rsize = 0x10000 5589 #define RSIZE_128K .rsize = 0x20000 5590 #define RSIZE_1M .rsize = 0x100000 5591 #define RLOCK .rlock = 1 5592 #define WLOCK .wlock = 1 5593 #define RWLOCK RLOCK, WLOCK 5594 5595 static const struct rtw89_debugfs rtw89_debugfs_templ = { 5596 .read_reg = rtw89_debug_priv_select_and_get(read_reg), 5597 .write_reg = rtw89_debug_priv_set(write_reg), 5598 .read_rf = rtw89_debug_priv_select_and_get(read_rf, RLOCK), 5599 .write_rf = rtw89_debug_priv_set(write_rf, WLOCK), 5600 .rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump, RSIZE_8K, RLOCK), 5601 .txpwr_table = rtw89_debug_priv_get(txpwr_table, RSIZE_20K, RLOCK), 5602 .mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump, RSIZE_128K), 5603 .mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump, RSIZE_16K, RLOCK), 5604 .mac_dbg_port_dump = rtw89_debug_priv_select_and_get(mac_dbg_port_dump, RSIZE_1M), 5605 .send_h2c = rtw89_debug_priv_set(send_h2c), 5606 .early_h2c = rtw89_debug_priv_set_and_get(early_h2c, RWLOCK), 5607 .fw_crash = rtw89_debug_priv_set_and_get(fw_crash, WLOCK), 5608 .ser_counters = rtw89_debug_priv_get(ser_counters, RLOCK), 5609 .btc_info = rtw89_debug_priv_get(btc_info, RSIZE_12K), 5610 .btc_manual = rtw89_debug_priv_set(btc_manual), 5611 .fw_log_manual = rtw89_debug_priv_set(fw_log_manual, WLOCK), 5612 .phy_info = rtw89_debug_priv_get(phy_info), 5613 .bb_info = rtw89_debug_priv_set_and_get(bb_info, RWLOCK), 5614 .stations = rtw89_debug_priv_get(stations, RLOCK), 5615 .disable_dm = rtw89_debug_priv_set_and_get(disable_dm, RWLOCK), 5616 .static_pd_th = rtw89_debug_priv_set_and_get(static_pd_th, RWLOCK), 5617 .mlo_mode = rtw89_debug_priv_set_and_get(mlo_mode, RWLOCK), 5618 .beacon_info = rtw89_debug_priv_get(beacon_info), 5619 .diag_mac = rtw89_debug_priv_get(diag_mac, RSIZE_16K, RLOCK), 5620 .diag_bb = rtw89_debug_priv_get(diag_bb, RSIZE_8K, RLOCK), 5621 .diag_rf = rtw89_debug_priv_set_and_get(diag_rf, RWLOCK), 5622 .monitor_opts = rtw89_debug_priv_set_and_get(monitor_opts, RWLOCK), 5623 }; 5624 5625 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 5626 do { \ 5627 struct rtw89_debugfs_priv *priv = &rtwdev->debugfs->name; \ 5628 priv->rtwdev = rtwdev; \ 5629 if (IS_ERR(debugfs_create_file(#name, mode, parent, priv, \ 5630 &file_ops_ ##fopname))) \ 5631 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 5632 } while (0) 5633 5634 #define rtw89_debugfs_add_w(name) \ 5635 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 5636 #define rtw89_debugfs_add_rw(name) \ 5637 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 5638 #define rtw89_debugfs_add_r(name) \ 5639 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 5640 5641 static 5642 void rtw89_debugfs_add_sec0(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 5643 { 5644 rtw89_debugfs_add_rw(read_reg); 5645 rtw89_debugfs_add_w(write_reg); 5646 rtw89_debugfs_add_rw(read_rf); 5647 rtw89_debugfs_add_w(write_rf); 5648 rtw89_debugfs_add_r(rf_reg_dump); 5649 rtw89_debugfs_add_r(txpwr_table); 5650 rtw89_debugfs_add_rw(mac_reg_dump); 5651 rtw89_debugfs_add_rw(mac_mem_dump); 5652 rtw89_debugfs_add_rw(mac_dbg_port_dump); 5653 } 5654 5655 static 5656 void rtw89_debugfs_add_sec1(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 5657 { 5658 rtw89_debugfs_add_w(send_h2c); 5659 rtw89_debugfs_add_rw(early_h2c); 5660 rtw89_debugfs_add_rw(fw_crash); 5661 rtw89_debugfs_add_r(ser_counters); 5662 rtw89_debugfs_add_r(btc_info); 5663 rtw89_debugfs_add_w(btc_manual); 5664 rtw89_debugfs_add_w(fw_log_manual); 5665 rtw89_debugfs_add_r(phy_info); 5666 rtw89_debugfs_add_rw(bb_info); 5667 rtw89_debugfs_add_r(stations); 5668 } 5669 5670 static 5671 void rtw89_debugfs_add_sec2(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 5672 { 5673 rtw89_debugfs_add_rw(disable_dm); 5674 rtw89_debugfs_add_rw(static_pd_th); 5675 rtw89_debugfs_add_rw(mlo_mode); 5676 rtw89_debugfs_add_r(beacon_info); 5677 rtw89_debugfs_add_r(diag_mac); 5678 rtw89_debugfs_add_r(diag_bb); 5679 rtw89_debugfs_add_rw(diag_rf); 5680 rtw89_debugfs_add_rw(monitor_opts); 5681 } 5682 5683 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 5684 { 5685 struct dentry *debugfs_topdir; 5686 5687 rtwdev->debugfs = kmemdup(&rtw89_debugfs_templ, 5688 sizeof(rtw89_debugfs_templ), GFP_KERNEL); 5689 if (!rtwdev->debugfs) 5690 return; 5691 5692 debugfs_topdir = debugfs_create_dir("rtw89", 5693 rtwdev->hw->wiphy->debugfsdir); 5694 5695 rtw89_debugfs_add_sec0(rtwdev, debugfs_topdir); 5696 rtw89_debugfs_add_sec1(rtwdev, debugfs_topdir); 5697 rtw89_debugfs_add_sec2(rtwdev, debugfs_topdir); 5698 } 5699 5700 void rtw89_debugfs_deinit(struct rtw89_dev *rtwdev) 5701 { 5702 kfree(rtwdev->debugfs); 5703 } 5704 #endif 5705 5706 #ifdef CONFIG_RTW89_DEBUGMSG 5707 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, 5708 const char *fmt, ...) 5709 { 5710 struct va_format vaf = { 5711 .fmt = fmt, 5712 }; 5713 5714 va_list args; 5715 5716 va_start(args, fmt); 5717 vaf.va = &args; 5718 5719 if (rtw89_debug_mask & mask) 5720 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 5721 5722 va_end(args); 5723 } 5724 EXPORT_SYMBOL(rtw89_debug); 5725 #endif 5726