1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/hex.h> 6 #include <linux/vmalloc.h> 7 8 #include "coex.h" 9 #include "debug.h" 10 #include "fw.h" 11 #include "mac.h" 12 #include "pci.h" 13 #include "phy.h" 14 #include "ps.h" 15 #include "reg.h" 16 #include "sar.h" 17 #include "util.h" 18 19 #ifdef CONFIG_RTW89_DEBUGMSG 20 unsigned int rtw89_debug_mask; 21 EXPORT_SYMBOL(rtw89_debug_mask); 22 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 23 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 24 #endif 25 26 #ifdef CONFIG_RTW89_DEBUGFS 27 struct rtw89_debugfs_priv_opt { 28 bool rlock:1; 29 bool wlock:1; 30 size_t rsize; 31 }; 32 33 struct rtw89_debugfs_priv { 34 struct rtw89_dev *rtwdev; 35 ssize_t (*cb_read)(struct rtw89_dev *rtwdev, 36 struct rtw89_debugfs_priv *debugfs_priv, 37 char *buf, size_t bufsz); 38 ssize_t (*cb_write)(struct rtw89_dev *rtwdev, 39 struct rtw89_debugfs_priv *debugfs_priv, 40 const char *buf, size_t count); 41 struct rtw89_debugfs_priv_opt opt; 42 union { 43 u32 cb_data; 44 struct { 45 u32 addr; 46 u32 len; 47 } read_reg; 48 struct { 49 u32 addr; 50 u32 mask; 51 u8 path; 52 } read_rf; 53 struct { 54 u8 ss_dbg:1; 55 u8 dle_dbg:1; 56 u8 dmac_dbg:1; 57 u8 cmac_dbg:1; 58 u8 dbg_port:1; 59 } dbgpkg_en; 60 struct { 61 u32 start; 62 u32 len; 63 u8 sel; 64 } mac_mem; 65 }; 66 ssize_t rused; 67 char *rbuf; 68 }; 69 70 struct rtw89_debugfs { 71 struct rtw89_debugfs_priv read_reg; 72 struct rtw89_debugfs_priv write_reg; 73 struct rtw89_debugfs_priv read_rf; 74 struct rtw89_debugfs_priv write_rf; 75 struct rtw89_debugfs_priv rf_reg_dump; 76 struct rtw89_debugfs_priv txpwr_table; 77 struct rtw89_debugfs_priv mac_reg_dump; 78 struct rtw89_debugfs_priv mac_mem_dump; 79 struct rtw89_debugfs_priv mac_dbg_port_dump; 80 struct rtw89_debugfs_priv send_h2c; 81 struct rtw89_debugfs_priv early_h2c; 82 struct rtw89_debugfs_priv fw_crash; 83 struct rtw89_debugfs_priv ser_counters; 84 struct rtw89_debugfs_priv btc_info; 85 struct rtw89_debugfs_priv btc_manual; 86 struct rtw89_debugfs_priv fw_log_manual; 87 struct rtw89_debugfs_priv phy_info; 88 struct rtw89_debugfs_priv bb_info; 89 struct rtw89_debugfs_priv stations; 90 struct rtw89_debugfs_priv disable_dm; 91 struct rtw89_debugfs_priv static_pd_th; 92 struct rtw89_debugfs_priv mlo_mode; 93 struct rtw89_debugfs_priv beacon_info; 94 struct rtw89_debugfs_priv diag_mac; 95 struct rtw89_debugfs_priv diag_bb; 96 struct rtw89_debugfs_priv monitor_opts; 97 }; 98 99 struct rtw89_debugfs_iter_data { 100 char *buf; 101 size_t bufsz; 102 int written_sz; 103 }; 104 105 static void rtw89_debugfs_iter_data_setup(struct rtw89_debugfs_iter_data *iter_data, 106 char *buf, size_t bufsz) 107 { 108 iter_data->buf = buf; 109 iter_data->bufsz = bufsz; 110 iter_data->written_sz = 0; 111 } 112 113 static void rtw89_debugfs_iter_data_next(struct rtw89_debugfs_iter_data *iter_data, 114 char *buf, size_t bufsz, int written_sz) 115 { 116 iter_data->buf = buf; 117 iter_data->bufsz = bufsz; 118 iter_data->written_sz += written_sz; 119 } 120 121 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 122 [RATE_INFO_BW_20] = 20, 123 [RATE_INFO_BW_40] = 40, 124 [RATE_INFO_BW_80] = 80, 125 [RATE_INFO_BW_160] = 160, 126 [RATE_INFO_BW_320] = 320, 127 }; 128 129 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 130 { 131 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 132 return rtw89_rate_info_bw_to_mhz_map[bw]; 133 134 return 0; 135 } 136 137 static ssize_t rtw89_debugfs_file_read_helper(struct wiphy *wiphy, struct file *file, 138 char *buf, size_t bufsz, void *data) 139 { 140 struct rtw89_debugfs_priv *debugfs_priv = data; 141 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 142 ssize_t n; 143 144 n = debugfs_priv->cb_read(rtwdev, debugfs_priv, buf, bufsz); 145 rtw89_might_trailing_ellipsis(buf, bufsz, n); 146 147 return n; 148 } 149 150 static ssize_t rtw89_debugfs_file_read(struct file *file, char __user *userbuf, 151 size_t count, loff_t *ppos) 152 { 153 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 154 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 155 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 156 size_t bufsz = opt->rsize ? opt->rsize : PAGE_SIZE; 157 char *buf; 158 ssize_t n; 159 160 if (!debugfs_priv->rbuf) 161 debugfs_priv->rbuf = devm_kzalloc(rtwdev->dev, bufsz, GFP_KERNEL); 162 163 buf = debugfs_priv->rbuf; 164 if (!buf) 165 return -ENOMEM; 166 167 if (*ppos) { 168 n = debugfs_priv->rused; 169 goto out; 170 } 171 172 if (opt->rlock) { 173 n = wiphy_locked_debugfs_read(rtwdev->hw->wiphy, file, buf, bufsz, 174 userbuf, count, ppos, 175 rtw89_debugfs_file_read_helper, 176 debugfs_priv); 177 debugfs_priv->rused = n; 178 179 return n; 180 } 181 182 n = rtw89_debugfs_file_read_helper(rtwdev->hw->wiphy, file, buf, bufsz, 183 debugfs_priv); 184 debugfs_priv->rused = n; 185 186 out: 187 return simple_read_from_buffer(userbuf, count, ppos, buf, n); 188 } 189 190 static ssize_t rtw89_debugfs_file_write_helper(struct wiphy *wiphy, struct file *file, 191 char *buf, size_t count, void *data) 192 { 193 struct rtw89_debugfs_priv *debugfs_priv = data; 194 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 195 196 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 197 } 198 199 static ssize_t rtw89_debugfs_file_write(struct file *file, 200 const char __user *userbuf, 201 size_t count, loff_t *loff) 202 { 203 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 204 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 205 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 206 char *buf __free(kfree) = kmalloc(count + 1, GFP_KERNEL); 207 ssize_t n; 208 209 if (!buf) 210 return -ENOMEM; 211 212 if (opt->wlock) { 213 n = wiphy_locked_debugfs_write(rtwdev->hw->wiphy, 214 file, buf, count + 1, 215 userbuf, count, 216 rtw89_debugfs_file_write_helper, 217 debugfs_priv); 218 return n; 219 } 220 221 if (copy_from_user(buf, userbuf, count)) 222 return -EFAULT; 223 224 buf[count] = '\0'; 225 226 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 227 } 228 229 static const struct debugfs_short_fops file_ops_single_r = { 230 .read = rtw89_debugfs_file_read, 231 .llseek = generic_file_llseek, 232 }; 233 234 static const struct debugfs_short_fops file_ops_common_rw = { 235 .read = rtw89_debugfs_file_read, 236 .write = rtw89_debugfs_file_write, 237 .llseek = generic_file_llseek, 238 }; 239 240 static const struct debugfs_short_fops file_ops_single_w = { 241 .write = rtw89_debugfs_file_write, 242 .llseek = generic_file_llseek, 243 }; 244 245 static ssize_t 246 rtw89_debug_priv_read_reg_select(struct rtw89_dev *rtwdev, 247 struct rtw89_debugfs_priv *debugfs_priv, 248 const char *buf, size_t count) 249 { 250 u32 addr, len; 251 int num; 252 253 num = sscanf(buf, "%x %x", &addr, &len); 254 if (num != 2) { 255 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 256 return -EINVAL; 257 } 258 259 debugfs_priv->read_reg.addr = addr; 260 debugfs_priv->read_reg.len = len; 261 262 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 263 264 return count; 265 } 266 267 static 268 ssize_t rtw89_debug_priv_read_reg_get(struct rtw89_dev *rtwdev, 269 struct rtw89_debugfs_priv *debugfs_priv, 270 char *buf, size_t bufsz) 271 { 272 char *p = buf, *end = buf + bufsz; 273 u32 addr, addr_end, data, k; 274 u32 len; 275 276 len = debugfs_priv->read_reg.len; 277 addr = debugfs_priv->read_reg.addr; 278 279 if (len > 4) 280 goto ndata; 281 282 switch (len) { 283 case 1: 284 data = rtw89_read8(rtwdev, addr); 285 break; 286 case 2: 287 data = rtw89_read16(rtwdev, addr); 288 break; 289 case 4: 290 data = rtw89_read32(rtwdev, addr); 291 break; 292 default: 293 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 294 return -EINVAL; 295 } 296 297 p += scnprintf(p, end - p, "get %d bytes at 0x%08x=0x%08x\n", len, 298 addr, data); 299 300 return p - buf; 301 302 ndata: 303 addr_end = addr + len; 304 305 for (; addr < addr_end; addr += 16) { 306 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + addr); 307 for (k = 0; k < 16; k += 4) { 308 data = rtw89_read32(rtwdev, addr + k); 309 p += scnprintf(p, end - p, "%08x ", data); 310 } 311 p += scnprintf(p, end - p, "\n"); 312 } 313 314 return p - buf; 315 } 316 317 static 318 ssize_t rtw89_debug_priv_write_reg_set(struct rtw89_dev *rtwdev, 319 struct rtw89_debugfs_priv *debugfs_priv, 320 const char *buf, size_t count) 321 { 322 u32 addr, val, len; 323 int num; 324 325 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 326 if (num != 3) { 327 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 328 return -EINVAL; 329 } 330 331 switch (len) { 332 case 1: 333 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 334 rtw89_write8(rtwdev, addr, (u8)val); 335 break; 336 case 2: 337 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 338 rtw89_write16(rtwdev, addr, (u16)val); 339 break; 340 case 4: 341 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 342 rtw89_write32(rtwdev, addr, (u32)val); 343 break; 344 default: 345 rtw89_info(rtwdev, "invalid read write len %d\n", len); 346 break; 347 } 348 349 return count; 350 } 351 352 static ssize_t 353 rtw89_debug_priv_read_rf_select(struct rtw89_dev *rtwdev, 354 struct rtw89_debugfs_priv *debugfs_priv, 355 const char *buf, size_t count) 356 { 357 u32 addr, mask; 358 u8 path; 359 int num; 360 361 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 362 if (num != 3) { 363 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 364 return -EINVAL; 365 } 366 367 if (path >= rtwdev->chip->rf_path_num) { 368 rtw89_info(rtwdev, "wrong rf path\n"); 369 return -EINVAL; 370 } 371 debugfs_priv->read_rf.addr = addr; 372 debugfs_priv->read_rf.mask = mask; 373 debugfs_priv->read_rf.path = path; 374 375 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 376 377 return count; 378 } 379 380 static 381 ssize_t rtw89_debug_priv_read_rf_get(struct rtw89_dev *rtwdev, 382 struct rtw89_debugfs_priv *debugfs_priv, 383 char *buf, size_t bufsz) 384 { 385 char *p = buf, *end = buf + bufsz; 386 u32 addr, data, mask; 387 u8 path; 388 389 addr = debugfs_priv->read_rf.addr; 390 mask = debugfs_priv->read_rf.mask; 391 path = debugfs_priv->read_rf.path; 392 393 data = rtw89_read_rf(rtwdev, path, addr, mask); 394 395 p += scnprintf(p, end - p, "path %d, rf register 0x%08x=0x%08x\n", 396 path, addr, data); 397 398 return p - buf; 399 } 400 401 static 402 ssize_t rtw89_debug_priv_write_rf_set(struct rtw89_dev *rtwdev, 403 struct rtw89_debugfs_priv *debugfs_priv, 404 const char *buf, size_t count) 405 { 406 u32 addr, val, mask; 407 u8 path; 408 int num; 409 410 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 411 if (num != 4) { 412 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 413 return -EINVAL; 414 } 415 416 if (path >= rtwdev->chip->rf_path_num) { 417 rtw89_info(rtwdev, "wrong rf path\n"); 418 return -EINVAL; 419 } 420 421 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 422 path, addr, val, mask); 423 rtw89_write_rf(rtwdev, path, addr, mask, val); 424 425 return count; 426 } 427 428 static 429 ssize_t rtw89_debug_priv_rf_reg_dump_get(struct rtw89_dev *rtwdev, 430 struct rtw89_debugfs_priv *debugfs_priv, 431 char *buf, size_t bufsz) 432 { 433 const struct rtw89_chip_info *chip = rtwdev->chip; 434 char *p = buf, *end = buf + bufsz; 435 u32 addr, offset, data; 436 u8 path; 437 438 for (path = 0; path < chip->rf_path_num; path++) { 439 p += scnprintf(p, end - p, "RF path %d:\n\n", path); 440 for (addr = 0; addr < 0x100; addr += 4) { 441 p += scnprintf(p, end - p, "0x%08x: ", addr); 442 for (offset = 0; offset < 4; offset++) { 443 data = rtw89_read_rf(rtwdev, path, 444 addr + offset, RFREG_MASK); 445 p += scnprintf(p, end - p, "0x%05x ", data); 446 } 447 p += scnprintf(p, end - p, "\n"); 448 } 449 p += scnprintf(p, end - p, "\n"); 450 } 451 452 return p - buf; 453 } 454 455 struct txpwr_ent { 456 bool nested; 457 union { 458 const char *txt; 459 const struct txpwr_ent *ptr; 460 }; 461 u8 len; 462 }; 463 464 struct txpwr_map { 465 const struct txpwr_ent *ent; 466 u8 size; 467 u32 addr_from; 468 u32 addr_to; 469 u32 addr_to_1ss; 470 }; 471 472 #define __GEN_TXPWR_ENT_NESTED(_e) \ 473 { .nested = true, .ptr = __txpwr_ent_##_e, \ 474 .len = ARRAY_SIZE(__txpwr_ent_##_e) } 475 476 #define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t } 477 478 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 479 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 480 481 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 482 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 483 484 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 485 { .len = 8, .txt = _t "\t- " \ 486 _e0 " " _e1 " " _e2 " " _e3 " " \ 487 _e4 " " _e5 " " _e6 " " _e7 } 488 489 static const struct txpwr_ent __txpwr_ent_byr_ax[] = { 490 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 491 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 492 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 493 /* 1NSS */ 494 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 495 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 496 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 497 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 498 /* 2NSS */ 499 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 500 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 501 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 502 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 503 }; 504 505 static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) == 506 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 507 508 static const struct txpwr_map __txpwr_map_byr_ax = { 509 .ent = __txpwr_ent_byr_ax, 510 .size = ARRAY_SIZE(__txpwr_ent_byr_ax), 511 .addr_from = R_AX_PWR_BY_RATE, 512 .addr_to = R_AX_PWR_BY_RATE_MAX, 513 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX, 514 }; 515 516 static const struct txpwr_ent __txpwr_ent_lmt_ax[] = { 517 /* 1TX */ 518 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 519 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 520 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 521 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 522 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 523 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 524 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 525 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 526 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 527 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 528 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 529 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 530 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 531 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 532 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 533 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 534 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 535 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 536 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 537 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 538 /* 2TX */ 539 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 540 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 541 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 542 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 543 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 544 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 545 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 546 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 547 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 548 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 549 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 550 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 551 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 552 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 553 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 554 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 555 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 556 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 557 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 558 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 559 }; 560 561 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) == 562 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 563 564 static const struct txpwr_map __txpwr_map_lmt_ax = { 565 .ent = __txpwr_ent_lmt_ax, 566 .size = ARRAY_SIZE(__txpwr_ent_lmt_ax), 567 .addr_from = R_AX_PWR_LMT, 568 .addr_to = R_AX_PWR_LMT_MAX, 569 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX, 570 }; 571 572 static const struct txpwr_ent __txpwr_ent_lmt_ru_ax[] = { 573 /* 1TX */ 574 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 575 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 576 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 577 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 578 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 579 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 580 /* 2TX */ 581 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 582 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 583 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 584 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 585 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 586 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 587 }; 588 589 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) == 590 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 591 592 static const struct txpwr_map __txpwr_map_lmt_ru_ax = { 593 .ent = __txpwr_ent_lmt_ru_ax, 594 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_ax), 595 .addr_from = R_AX_PWR_RU_LMT, 596 .addr_to = R_AX_PWR_RU_LMT_MAX, 597 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX, 598 }; 599 600 static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = { 601 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 602 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 603 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 604 __GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"), 605 __GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 606 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 607 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 608 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 609 __GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"), 610 __GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 611 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 612 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 613 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 614 __GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"), 615 __GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 616 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 617 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 618 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 619 __GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"), 620 __GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 621 }; 622 623 static const struct txpwr_ent __txpwr_ent_byr_be[] = { 624 __GEN_TXPWR_ENT0("BW20"), 625 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 626 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 627 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 628 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 629 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 630 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 631 632 __GEN_TXPWR_ENT0("BW40"), 633 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 634 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 635 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 636 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 637 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 638 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 639 640 /* there is no CCK section after BW80 */ 641 __GEN_TXPWR_ENT0("BW80"), 642 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 643 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 644 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 645 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 646 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 647 648 __GEN_TXPWR_ENT0("BW160"), 649 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 650 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 651 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 652 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 653 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 654 655 __GEN_TXPWR_ENT0("BW320"), 656 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 657 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 658 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 659 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 660 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 661 }; 662 663 static const struct txpwr_map __txpwr_map_byr_be = { 664 .ent = __txpwr_ent_byr_be, 665 .size = ARRAY_SIZE(__txpwr_ent_byr_be), 666 .addr_from = R_BE_PWR_BY_RATE, 667 .addr_to = R_BE_PWR_BY_RATE_MAX, 668 .addr_to_1ss = 0, /* not support */ 669 }; 670 671 static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = { 672 __GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"), 673 __GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"), 674 __GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"), 675 __GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"), 676 __GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"), 677 __GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"), 678 __GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"), 679 __GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"), 680 __GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"), 681 __GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"), 682 __GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"), 683 __GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"), 684 __GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"), 685 __GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"), 686 __GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"), 687 __GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"), 688 __GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"), 689 __GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"), 690 __GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"), 691 __GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"), 692 __GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"), 693 __GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"), 694 __GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"), 695 __GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"), 696 __GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"), 697 __GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"), 698 __GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"), 699 __GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"), 700 __GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"), 701 __GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"), 702 __GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"), 703 __GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"), 704 __GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"), 705 __GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"), 706 __GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"), 707 }; 708 709 static const struct txpwr_ent __txpwr_ent_lmt_be[] = { 710 __GEN_TXPWR_ENT0("1TX"), 711 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 712 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 713 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 714 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 715 716 __GEN_TXPWR_ENT0("2TX"), 717 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 718 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 719 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 720 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 721 }; 722 723 static const struct txpwr_map __txpwr_map_lmt_be = { 724 .ent = __txpwr_ent_lmt_be, 725 .size = ARRAY_SIZE(__txpwr_ent_lmt_be), 726 .addr_from = R_BE_PWR_LMT, 727 .addr_to = R_BE_PWR_LMT_MAX, 728 .addr_to_1ss = 0, /* not support */ 729 }; 730 731 static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = { 732 __GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 733 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 734 __GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 735 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 736 __GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 737 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 738 __GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 739 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 740 __GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 741 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 742 __GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 743 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 744 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 745 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 746 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 747 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 748 __GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 749 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 750 __GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 751 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 752 }; 753 754 static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = { 755 __GEN_TXPWR_ENT0("1TX"), 756 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 757 758 __GEN_TXPWR_ENT0("2TX"), 759 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 760 }; 761 762 static const struct txpwr_map __txpwr_map_lmt_ru_be = { 763 .ent = __txpwr_ent_lmt_ru_be, 764 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be), 765 .addr_from = R_BE_PWR_RU_LMT, 766 .addr_to = R_BE_PWR_RU_LMT_MAX, 767 .addr_to_1ss = 0, /* not support */ 768 }; 769 770 static const struct txpwr_ent __txpwr_ent_lmt_ru484_242_be[] = { 771 __GEN_TXPWR_ENT4("RU484_242 1TX ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 "), 772 __GEN_TXPWR_ENT4("RU484_242 2TX ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 "), 773 }; 774 775 static const struct txpwr_map __txpwr_map_lmt_ru484_242_be = { 776 .ent = __txpwr_ent_lmt_ru484_242_be, 777 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru484_242_be), 778 .addr_from = R_BE_TXAGC_MAX_1TX_RU484_242_0, 779 .addr_to = R_BE_TXAGC_MAX_1TX_RU484_242_0 + 4, 780 .addr_to_1ss = 0, /* not support */ 781 }; 782 783 static const struct txpwr_ent __txpwr_ent_lmt_ru996_484_be[] = { 784 __GEN_TXPWR_ENT2("RU996_484 1TX ", "IDX_0 ", "IDX_1 "), 785 __GEN_TXPWR_ENT2("RU996_484 2TX ", "IDX_0 ", "IDX_1 "), 786 }; 787 788 static const struct txpwr_map __txpwr_map_lmt_ru996_484_be = { 789 .ent = __txpwr_ent_lmt_ru996_484_be, 790 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru996_484_be), 791 .addr_from = R_BE_TXAGC_MAX_1TX_RU996_484_0, 792 .addr_to = R_BE_TXAGC_MAX_1TX_RU996_484_0, 793 .addr_to_1ss = 0, /* not support */ 794 }; 795 796 static const struct txpwr_ent __txpwr_ent_lmt_ru996_484_242_be[] = { 797 __GEN_TXPWR_ENT2("RU996_484_242 1TX ", "IDX_0 ", "IDX_1 "), 798 __GEN_TXPWR_ENT2("RU996_484_242 2TX ", "IDX_0 ", "IDX_1 "), 799 }; 800 801 static const struct txpwr_map __txpwr_map_lmt_ru996_484_242_be = { 802 .ent = __txpwr_ent_lmt_ru996_484_242_be, 803 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru996_484_242_be), 804 .addr_from = R_BE_TXAGC_MAX_1TX_RU996_484_242_0, 805 .addr_to = R_BE_TXAGC_MAX_1TX_RU996_484_242_0, 806 .addr_to_1ss = 0, /* not support */ 807 }; 808 809 static unsigned int 810 __print_txpwr_ent(char *buf, size_t bufsz, const struct txpwr_ent *ent, 811 const s8 *bufp, const unsigned int cur, unsigned int *ate) 812 { 813 char *p = buf, *end = buf + bufsz; 814 unsigned int cnt, i; 815 unsigned int eaten; 816 char *fmt; 817 818 if (ent->nested) { 819 for (cnt = 0, i = 0; i < ent->len; i++, cnt += eaten) 820 p += __print_txpwr_ent(p, end - p, ent->ptr + i, bufp, 821 cur + cnt, &eaten); 822 *ate = cnt; 823 goto out; 824 } 825 826 switch (ent->len) { 827 case 0: 828 p += scnprintf(p, end - p, "\t<< %s >>\n", ent->txt); 829 *ate = 0; 830 goto out; 831 case 2: 832 fmt = "%s\t| %3d, %3d,\t\tdBm\n"; 833 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 834 bufp[cur + 1]); 835 *ate = 2; 836 goto out; 837 case 4: 838 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 839 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 840 bufp[cur + 1], 841 bufp[cur + 2], bufp[cur + 3]); 842 *ate = 4; 843 goto out; 844 case 8: 845 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 846 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 847 bufp[cur + 1], 848 bufp[cur + 2], bufp[cur + 3], bufp[cur + 4], 849 bufp[cur + 5], bufp[cur + 6], bufp[cur + 7]); 850 *ate = 8; 851 goto out; 852 default: 853 return 0; 854 } 855 856 out: 857 return p - buf; 858 } 859 860 static ssize_t __print_txpwr_map(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 861 const struct txpwr_map *map) 862 { 863 u8 fct = rtwdev->chip->txpwr_factor_mac; 864 u8 path_num = rtwdev->chip->rf_path_num; 865 char *p = buf, *end = buf + bufsz; 866 unsigned int cur, i; 867 unsigned int eaten; 868 u32 max_valid_addr; 869 u32 val, addr; 870 s8 *bufp, tmp; 871 int ret; 872 873 if (path_num == 1) 874 max_valid_addr = map->addr_to_1ss; 875 else 876 max_valid_addr = map->addr_to; 877 878 if (max_valid_addr == 0) 879 return -EOPNOTSUPP; 880 881 bufp = vzalloc(map->addr_to - map->addr_from + 4); 882 if (!bufp) 883 return -ENOMEM; 884 885 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 886 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 887 if (ret) 888 val = MASKDWORD; 889 890 cur = addr - map->addr_from; 891 for (i = 0; i < 4; i++, val >>= 8) { 892 /* signed 7 bits, and reserved BIT(7) */ 893 tmp = sign_extend32(val, 6); 894 bufp[cur + i] = tmp >> fct; 895 } 896 } 897 898 for (cur = 0, i = 0; i < map->size; i++, cur += eaten) 899 p += __print_txpwr_ent(p, end - p, &map->ent[i], bufp, cur, &eaten); 900 901 vfree(bufp); 902 return p - buf; 903 } 904 905 static int __print_regd(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 906 const struct rtw89_chan *chan) 907 { 908 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 909 char *p = buf, *end = buf + bufsz; 910 u8 band = chan->band_type; 911 u8 regd = rtw89_regd_get(rtwdev, band); 912 913 p += scnprintf(p, end - p, "%s\n", rtw89_regd_get_string(regd)); 914 p += scnprintf(p, end - p, "\t(txpwr UK follow ETSI: %s)\n", 915 str_yes_no(regulatory->txpwr_uk_follow_etsi)); 916 917 return p - buf; 918 } 919 920 struct dbgfs_txpwr_table { 921 const struct txpwr_map *byr; 922 const struct txpwr_map *lmt; 923 const struct txpwr_map *lmt_ru; 924 const struct txpwr_map *lmt_ru484_242; 925 const struct txpwr_map *lmt_ru996_484; 926 const struct txpwr_map *lmt_ru996_484_242; 927 }; 928 929 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = { 930 .byr = &__txpwr_map_byr_ax, 931 .lmt = &__txpwr_map_lmt_ax, 932 .lmt_ru = &__txpwr_map_lmt_ru_ax, 933 }; 934 935 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = { 936 .byr = &__txpwr_map_byr_be, 937 .lmt = &__txpwr_map_lmt_be, 938 .lmt_ru = &__txpwr_map_lmt_ru_be, 939 .lmt_ru484_242 = &__txpwr_map_lmt_ru484_242_be, 940 .lmt_ru996_484 = &__txpwr_map_lmt_ru996_484_be, 941 .lmt_ru996_484_242 = &__txpwr_map_lmt_ru996_484_242_be, 942 }; 943 944 static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = { 945 [RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax, 946 [RTW89_CHIP_BE] = &dbgfs_txpwr_table_be, 947 }; 948 949 static 950 int rtw89_debug_priv_txpwr_table_get_regd(struct rtw89_dev *rtwdev, 951 char *buf, size_t bufsz, 952 const struct rtw89_chan *chan) 953 { 954 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 955 const struct rtw89_reg_6ghz_tpe *tpe6 = ®ulatory->reg_6ghz_tpe; 956 char *p = buf, *end = buf + bufsz; 957 958 p += scnprintf(p, end - p, "[Chanctx] band %u, ch %u, bw %u\n", 959 chan->band_type, chan->channel, chan->band_width); 960 961 p += scnprintf(p, end - p, "[Regulatory] "); 962 p += __print_regd(rtwdev, p, end - p, chan); 963 964 if (chan->band_type == RTW89_BAND_6G) { 965 p += scnprintf(p, end - p, "[reg6_pwr_type] %u\n", 966 regulatory->reg_6ghz_power); 967 968 if (tpe6->valid) 969 p += scnprintf(p, end - p, "[TPE] %d dBm\n", 970 tpe6->constraint); 971 } 972 973 return p - buf; 974 } 975 976 static 977 ssize_t rtw89_debug_priv_txpwr_table_get(struct rtw89_dev *rtwdev, 978 struct rtw89_debugfs_priv *debugfs_priv, 979 char *buf, size_t bufsz) 980 { 981 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 982 const struct rtw89_chip_info *chip = rtwdev->chip; 983 struct rtw89_hal *hal = &rtwdev->hal; 984 struct rtw89_sar_parm sar_parm = {}; 985 const struct dbgfs_txpwr_table *tbl; 986 const struct rtw89_chan *chan; 987 char *p = buf, *end = buf + bufsz; 988 ssize_t n; 989 990 lockdep_assert_wiphy(rtwdev->hw->wiphy); 991 992 rtw89_leave_ps_mode(rtwdev); 993 chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 994 sar_parm.center_freq = chan->freq; 995 996 p += rtw89_debug_priv_txpwr_table_get_regd(rtwdev, p, end - p, chan); 997 998 p += scnprintf(p, end - p, "[SAR]\n"); 999 p += rtw89_print_sar(rtwdev, p, end - p, &sar_parm); 1000 1001 p += scnprintf(p, end - p, "[TAS]\n"); 1002 p += rtw89_print_tas(rtwdev, p, end - p); 1003 1004 p += scnprintf(p, end - p, "[DAG]\n"); 1005 p += rtw89_print_ant_gain(rtwdev, p, end - p, chan); 1006 1007 tbl = dbgfs_txpwr_tables[chip_gen]; 1008 if (!tbl) 1009 return -EOPNOTSUPP; 1010 1011 p += scnprintf(p, end - p, "\n[TX power byrate]\n"); 1012 n = __print_txpwr_map(rtwdev, p, end - p, tbl->byr); 1013 if (n < 0) 1014 return n; 1015 p += n; 1016 1017 p += scnprintf(p, end - p, "\n[TX power limit]\n"); 1018 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt); 1019 if (n < 0) 1020 return n; 1021 p += n; 1022 1023 p += scnprintf(p, end - p, "\n[TX power limit_ru]\n"); 1024 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru); 1025 if (n < 0) 1026 return n; 1027 p += n; 1028 1029 switch (chip_gen) { 1030 case RTW89_CHIP_AX: 1031 goto out; 1032 case RTW89_CHIP_BE: 1033 if (!(chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7090)) 1034 goto out; 1035 break; 1036 default: 1037 return -EOPNOTSUPP; 1038 } 1039 1040 p += scnprintf(p, end - p, "\n[TX power limit_large_mru]\n"); 1041 1042 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru484_242); 1043 if (n < 0) 1044 return n; 1045 p += n; 1046 1047 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru996_484); 1048 if (n < 0) 1049 return n; 1050 p += n; 1051 1052 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru996_484_242); 1053 if (n < 0) 1054 return n; 1055 p += n; 1056 1057 out: 1058 return p - buf; 1059 } 1060 1061 static ssize_t 1062 rtw89_debug_priv_mac_reg_dump_select(struct rtw89_dev *rtwdev, 1063 struct rtw89_debugfs_priv *debugfs_priv, 1064 const char *buf, size_t count) 1065 { 1066 const struct rtw89_chip_info *chip = rtwdev->chip; 1067 int sel; 1068 int ret; 1069 1070 ret = kstrtoint(buf, 0, &sel); 1071 if (ret) 1072 return ret; 1073 1074 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 1075 rtw89_info(rtwdev, "invalid args: %d\n", sel); 1076 return -EINVAL; 1077 } 1078 1079 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 1080 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 1081 chip->chip_id); 1082 return -EINVAL; 1083 } 1084 1085 debugfs_priv->cb_data = sel; 1086 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 1087 1088 return count; 1089 } 1090 1091 #define RTW89_MAC_PAGE_SIZE 0x100 1092 1093 static 1094 ssize_t rtw89_debug_priv_mac_reg_dump_get(struct rtw89_dev *rtwdev, 1095 struct rtw89_debugfs_priv *debugfs_priv, 1096 char *buf, size_t bufsz) 1097 { 1098 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 1099 char *p = buf, *end = buf + bufsz; 1100 u32 start, end_addr; 1101 u32 i, j, k, page; 1102 u32 val; 1103 1104 switch (reg_sel) { 1105 case RTW89_DBG_SEL_MAC_00: 1106 p += scnprintf(p, end - p, "Debug selected MAC page 0x00\n"); 1107 start = 0x000; 1108 end_addr = 0x014; 1109 break; 1110 case RTW89_DBG_SEL_MAC_30: 1111 p += scnprintf(p, end - p, "Debug selected MAC page 0x30\n"); 1112 start = 0x030; 1113 end_addr = 0x033; 1114 break; 1115 case RTW89_DBG_SEL_MAC_40: 1116 p += scnprintf(p, end - p, "Debug selected MAC page 0x40\n"); 1117 start = 0x040; 1118 end_addr = 0x07f; 1119 break; 1120 case RTW89_DBG_SEL_MAC_80: 1121 p += scnprintf(p, end - p, "Debug selected MAC page 0x80\n"); 1122 start = 0x080; 1123 end_addr = 0x09f; 1124 break; 1125 case RTW89_DBG_SEL_MAC_C0: 1126 p += scnprintf(p, end - p, "Debug selected MAC page 0xc0\n"); 1127 start = 0x0c0; 1128 end_addr = 0x0df; 1129 break; 1130 case RTW89_DBG_SEL_MAC_E0: 1131 p += scnprintf(p, end - p, "Debug selected MAC page 0xe0\n"); 1132 start = 0x0e0; 1133 end_addr = 0x0ff; 1134 break; 1135 case RTW89_DBG_SEL_BB: 1136 p += scnprintf(p, end - p, "Debug selected BB register\n"); 1137 start = 0x100; 1138 end_addr = 0x17f; 1139 break; 1140 case RTW89_DBG_SEL_IQK: 1141 p += scnprintf(p, end - p, "Debug selected IQK register\n"); 1142 start = 0x180; 1143 end_addr = 0x1bf; 1144 break; 1145 case RTW89_DBG_SEL_RFC: 1146 p += scnprintf(p, end - p, "Debug selected RFC register\n"); 1147 start = 0x1c0; 1148 end_addr = 0x1ff; 1149 break; 1150 default: 1151 p += scnprintf(p, end - p, "Selected invalid register page\n"); 1152 return -EINVAL; 1153 } 1154 1155 for (i = start; i <= end_addr; i++) { 1156 page = i << 8; 1157 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 1158 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + j); 1159 for (k = 0; k < 4; k++) { 1160 val = rtw89_read32(rtwdev, j + (k << 2)); 1161 p += scnprintf(p, end - p, "%08x ", val); 1162 } 1163 p += scnprintf(p, end - p, "\n"); 1164 } 1165 } 1166 1167 return p - buf; 1168 } 1169 1170 static ssize_t 1171 rtw89_debug_priv_mac_mem_dump_select(struct rtw89_dev *rtwdev, 1172 struct rtw89_debugfs_priv *debugfs_priv, 1173 const char *buf, size_t count) 1174 { 1175 u32 sel, start_addr, len; 1176 int num; 1177 1178 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 1179 if (num != 3) { 1180 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 1181 return -EINVAL; 1182 } 1183 1184 debugfs_priv->mac_mem.sel = sel; 1185 debugfs_priv->mac_mem.start = start_addr; 1186 debugfs_priv->mac_mem.len = len; 1187 1188 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 1189 sel, start_addr, len); 1190 1191 return count; 1192 } 1193 1194 static int rtw89_debug_dump_mac_mem(struct rtw89_dev *rtwdev, 1195 char *buf, size_t bufsz, 1196 u8 sel, u32 start_addr, u32 len) 1197 { 1198 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1199 u32 filter_model_addr = mac->filter_model_addr; 1200 u32 indir_access_addr = mac->indir_access_addr; 1201 u32 mem_page_size = mac->mem_page_size; 1202 u32 base_addr, start_page, residue; 1203 char *p = buf, *end = buf + bufsz; 1204 u32 i, j, pp, pages; 1205 u32 dump_len, remain; 1206 u32 val; 1207 1208 remain = len; 1209 pages = len / mem_page_size + 1; 1210 start_page = start_addr / mem_page_size; 1211 residue = start_addr % mem_page_size; 1212 base_addr = rtw89_mac_mem_base_addrs(rtwdev, sel); 1213 base_addr += start_page * mem_page_size; 1214 1215 for (pp = 0; pp < pages; pp++) { 1216 dump_len = min_t(u32, remain, mem_page_size); 1217 rtw89_write32(rtwdev, filter_model_addr, base_addr); 1218 for (i = indir_access_addr + residue; 1219 i < indir_access_addr + dump_len;) { 1220 p += scnprintf(p, end - p, "%08xh:", i); 1221 for (j = 0; 1222 j < 4 && i < indir_access_addr + dump_len; 1223 j++, i += 4) { 1224 val = rtw89_read32(rtwdev, i); 1225 p += scnprintf(p, end - p, " %08x", val); 1226 remain -= 4; 1227 } 1228 p += scnprintf(p, end - p, "\n"); 1229 } 1230 base_addr += mem_page_size; 1231 } 1232 1233 return p - buf; 1234 } 1235 1236 static ssize_t 1237 rtw89_debug_priv_mac_mem_dump_get(struct rtw89_dev *rtwdev, 1238 struct rtw89_debugfs_priv *debugfs_priv, 1239 char *buf, size_t bufsz) 1240 { 1241 char *p = buf, *end = buf + bufsz; 1242 bool grant_read = false; 1243 1244 lockdep_assert_wiphy(rtwdev->hw->wiphy); 1245 1246 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 1247 return -ENOENT; 1248 1249 if (rtwdev->chip->chip_id == RTL8852C) { 1250 switch (debugfs_priv->mac_mem.sel) { 1251 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 1252 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 1253 case RTW89_MAC_MEM_TXDATA_FIFO_0: 1254 case RTW89_MAC_MEM_TXDATA_FIFO_1: 1255 grant_read = true; 1256 break; 1257 default: 1258 break; 1259 } 1260 } 1261 1262 rtw89_leave_ps_mode(rtwdev); 1263 if (grant_read) 1264 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1265 p += rtw89_debug_dump_mac_mem(rtwdev, p, end - p, 1266 debugfs_priv->mac_mem.sel, 1267 debugfs_priv->mac_mem.start, 1268 debugfs_priv->mac_mem.len); 1269 if (grant_read) 1270 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1271 1272 return p - buf; 1273 } 1274 1275 static ssize_t 1276 rtw89_debug_priv_mac_dbg_port_dump_select(struct rtw89_dev *rtwdev, 1277 struct rtw89_debugfs_priv *debugfs_priv, 1278 const char *buf, size_t count) 1279 { 1280 int sel, set; 1281 int num; 1282 bool enable; 1283 1284 num = sscanf(buf, "%d %d", &sel, &set); 1285 if (num != 2) { 1286 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 1287 return -EINVAL; 1288 } 1289 1290 enable = set != 0; 1291 switch (sel) { 1292 case 0: 1293 debugfs_priv->dbgpkg_en.ss_dbg = enable; 1294 break; 1295 case 1: 1296 debugfs_priv->dbgpkg_en.dle_dbg = enable; 1297 break; 1298 case 2: 1299 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 1300 break; 1301 case 3: 1302 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 1303 break; 1304 case 4: 1305 debugfs_priv->dbgpkg_en.dbg_port = enable; 1306 break; 1307 default: 1308 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 1309 return -EINVAL; 1310 } 1311 1312 rtw89_info(rtwdev, "%s debug port dump %d\n", 1313 enable ? "Enable" : "Disable", sel); 1314 1315 return count; 1316 } 1317 1318 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 1319 char *buf, size_t bufsz) 1320 { 1321 return 0; 1322 } 1323 1324 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 1325 char *buf, size_t bufsz) 1326 { 1327 #define DLE_DFI_DUMP(__type, __target, __sel) \ 1328 ({ \ 1329 u32 __ctrl; \ 1330 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 1331 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 1332 u32 __data, __val32; \ 1333 int __ret; \ 1334 \ 1335 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 1336 DLE_DFI_TYPE_##__target) | \ 1337 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 1338 B_AX_WDE_DFI_ACTIVE; \ 1339 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 1340 __ret = read_poll_timeout(rtw89_read32, __val32, \ 1341 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 1342 1000, 50000, false, \ 1343 rtwdev, __reg_ctrl); \ 1344 if (__ret) { \ 1345 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 1346 #__type, #__target, __sel); \ 1347 return __ret; \ 1348 } \ 1349 \ 1350 __data = rtw89_read32(rtwdev, __reg_data); \ 1351 __data; \ 1352 }) 1353 1354 #define DLE_DFI_FREE_PAGE_DUMP(__p, __end, __type) \ 1355 ({ \ 1356 u32 __freepg, __pubpg; \ 1357 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 1358 \ 1359 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 1360 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 1361 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 1362 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 1363 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 1364 __p += scnprintf(__p, __end - __p, "[%s] freepg head: %d\n", \ 1365 #__type, __freepg_head); \ 1366 __p += scnprintf(__p, __end - __p, "[%s] freepg tail: %d\n", \ 1367 #__type, __freepg_tail); \ 1368 __p += scnprintf(__p, __end - __p, "[%s] pubpg num : %d\n", \ 1369 #__type, __pubpg_num); \ 1370 }) 1371 1372 #define case_QUOTA(__p, __end, __type, __id) \ 1373 case __type##_QTAID_##__id: \ 1374 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 1375 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 1376 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 1377 __p += scnprintf(__p, __end - __p, "[%s][%s] rsv_pgnum: %d\n", \ 1378 #__type, #__id, rsv_pgnum); \ 1379 __p += scnprintf(__p, __end - __p, "[%s][%s] use_pgnum: %d\n", \ 1380 #__type, #__id, use_pgnum); \ 1381 break 1382 char *p = buf, *end = buf + bufsz; 1383 u32 quota_id; 1384 u32 val32; 1385 u16 rsv_pgnum, use_pgnum; 1386 int ret; 1387 1388 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1389 if (ret) { 1390 p += scnprintf(p, end - p, "[DLE] : DMAC not enabled\n"); 1391 goto out; 1392 } 1393 1394 DLE_DFI_FREE_PAGE_DUMP(p, end, WDE); 1395 DLE_DFI_FREE_PAGE_DUMP(p, end, PLE); 1396 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 1397 switch (quota_id) { 1398 case_QUOTA(p, end, WDE, HOST_IF); 1399 case_QUOTA(p, end, WDE, WLAN_CPU); 1400 case_QUOTA(p, end, WDE, DATA_CPU); 1401 case_QUOTA(p, end, WDE, PKTIN); 1402 case_QUOTA(p, end, WDE, CPUIO); 1403 } 1404 } 1405 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 1406 switch (quota_id) { 1407 case_QUOTA(p, end, PLE, B0_TXPL); 1408 case_QUOTA(p, end, PLE, B1_TXPL); 1409 case_QUOTA(p, end, PLE, C2H); 1410 case_QUOTA(p, end, PLE, H2C); 1411 case_QUOTA(p, end, PLE, WLAN_CPU); 1412 case_QUOTA(p, end, PLE, MPDU); 1413 case_QUOTA(p, end, PLE, CMAC0_RX); 1414 case_QUOTA(p, end, PLE, CMAC1_RX); 1415 case_QUOTA(p, end, PLE, CMAC1_BBRPT); 1416 case_QUOTA(p, end, PLE, WDRLS); 1417 case_QUOTA(p, end, PLE, CPUIO); 1418 } 1419 } 1420 1421 out: 1422 return p - buf; 1423 1424 #undef case_QUOTA 1425 #undef DLE_DFI_DUMP 1426 #undef DLE_DFI_FREE_PAGE_DUMP 1427 } 1428 1429 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 1430 char *buf, size_t bufsz) 1431 { 1432 const struct rtw89_chip_info *chip = rtwdev->chip; 1433 char *p = buf, *end = buf + bufsz; 1434 u32 dmac_err; 1435 int i, ret; 1436 1437 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1438 if (ret) { 1439 p += scnprintf(p, end - p, "[DMAC] : DMAC not enabled\n"); 1440 goto out; 1441 } 1442 1443 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1444 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1445 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1446 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1447 1448 if (dmac_err) { 1449 p += scnprintf(p, end - p, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1450 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1451 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1452 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1453 if (chip->chip_id == RTL8852C) { 1454 p += scnprintf(p, end - p, 1455 "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1456 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1457 p += scnprintf(p, end - p, 1458 "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1459 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1460 p += scnprintf(p, end - p, 1461 "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1462 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1463 p += scnprintf(p, end - p, 1464 "R_AX_PLE_DBGERR_STS=0x%08x\n", 1465 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1466 } 1467 } 1468 1469 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1470 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1471 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1472 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1473 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1474 if (chip->chip_id == RTL8852C) 1475 p += scnprintf(p, end - p, 1476 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1477 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1478 else 1479 p += scnprintf(p, end - p, 1480 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1481 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1482 } 1483 1484 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1485 if (chip->chip_id == RTL8852C) { 1486 p += scnprintf(p, end - p, 1487 "R_AX_SEC_ERR_IMR=0x%08x\n", 1488 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1489 p += scnprintf(p, end - p, 1490 "R_AX_SEC_ERR_ISR=0x%08x\n", 1491 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1492 p += scnprintf(p, end - p, 1493 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1494 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1495 p += scnprintf(p, end - p, 1496 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1497 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1498 p += scnprintf(p, end - p, 1499 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1500 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1501 p += scnprintf(p, end - p, 1502 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1503 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1504 p += scnprintf(p, end - p, "R_AX_SEC_DEBUG1=0x%08x\n", 1505 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1506 p += scnprintf(p, end - p, 1507 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1508 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1509 p += scnprintf(p, end - p, 1510 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1511 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1512 1513 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1514 B_AX_DBG_SEL0, 0x8B); 1515 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1516 B_AX_DBG_SEL1, 0x8B); 1517 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1518 B_AX_SEL_0XC0_MASK, 1); 1519 for (i = 0; i < 0x10; i++) { 1520 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1521 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1522 p += scnprintf(p, end - p, 1523 "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1524 i, 1525 rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1526 } 1527 } else { 1528 p += scnprintf(p, end - p, 1529 "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1530 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1531 p += scnprintf(p, end - p, 1532 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1533 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1534 p += scnprintf(p, end - p, 1535 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1536 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1537 p += scnprintf(p, end - p, 1538 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1539 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1540 p += scnprintf(p, end - p, 1541 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1542 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1543 p += scnprintf(p, end - p, 1544 "R_AX_SEC_CAM_WDATA=0x%08x\n", 1545 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1546 p += scnprintf(p, end - p, 1547 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1548 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1549 p += scnprintf(p, end - p, 1550 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1551 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1552 p += scnprintf(p, end - p, 1553 "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1554 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1555 p += scnprintf(p, end - p, 1556 "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1557 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1558 } 1559 } 1560 1561 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1562 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1563 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1564 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1565 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1566 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1567 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1568 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1569 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1570 } 1571 1572 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1573 p += scnprintf(p, end - p, 1574 "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1575 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1576 p += scnprintf(p, end - p, 1577 "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1578 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1579 } 1580 1581 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1582 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1583 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1584 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1585 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1586 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1587 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1588 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1589 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1590 } 1591 1592 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1593 if (chip->chip_id == RTL8852C) { 1594 p += scnprintf(p, end - p, 1595 "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1596 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1597 p += scnprintf(p, end - p, 1598 "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1599 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1600 p += scnprintf(p, end - p, 1601 "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1602 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1603 p += scnprintf(p, end - p, 1604 "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1605 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1606 } else { 1607 p += scnprintf(p, end - p, 1608 "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1609 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1610 p += scnprintf(p, end - p, 1611 "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1612 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1613 } 1614 } 1615 1616 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1617 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1618 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1619 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1620 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1621 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1622 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1623 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1624 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1625 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1626 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1627 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1628 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1629 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1630 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1631 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1632 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1633 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1634 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1635 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1636 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1637 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1638 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1639 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1640 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1641 if (chip->chip_id == RTL8852C) { 1642 p += scnprintf(p, end - p, "R_AX_RX_CTRL0=0x%08x\n", 1643 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1644 p += scnprintf(p, end - p, "R_AX_RX_CTRL1=0x%08x\n", 1645 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1646 p += scnprintf(p, end - p, "R_AX_RX_CTRL2=0x%08x\n", 1647 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1648 } else { 1649 p += scnprintf(p, end - p, 1650 "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1651 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1652 p += scnprintf(p, end - p, 1653 "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1654 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1655 p += scnprintf(p, end - p, 1656 "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1657 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1658 } 1659 } 1660 1661 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1662 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1663 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1664 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1665 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1666 } 1667 1668 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1669 p += scnprintf(p, end - p, 1670 "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1671 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1672 p += scnprintf(p, end - p, 1673 "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1674 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1675 p += scnprintf(p, end - p, 1676 "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1677 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1678 p += scnprintf(p, end - p, 1679 "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1680 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1681 p += scnprintf(p, end - p, 1682 "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1683 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1684 p += scnprintf(p, end - p, 1685 "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1686 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1687 } 1688 1689 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1690 if (chip->chip_id == RTL8852C) { 1691 p += scnprintf(p, end - p, 1692 "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1693 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1694 p += scnprintf(p, end - p, 1695 "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1696 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1697 p += scnprintf(p, end - p, 1698 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1699 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1700 p += scnprintf(p, end - p, 1701 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1702 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1703 p += scnprintf(p, end - p, 1704 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1705 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1706 p += scnprintf(p, end - p, 1707 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1708 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1709 } else { 1710 p += scnprintf(p, end - p, 1711 "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1712 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1713 p += scnprintf(p, end - p, 1714 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1715 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1716 p += scnprintf(p, end - p, 1717 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1718 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1719 p += scnprintf(p, end - p, 1720 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1721 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1722 p += scnprintf(p, end - p, 1723 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1724 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1725 } 1726 } 1727 1728 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1729 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1730 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1731 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1732 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1733 } 1734 1735 out: 1736 return p - buf; 1737 } 1738 1739 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1740 char *buf, size_t bufsz, 1741 enum rtw89_mac_idx band) 1742 { 1743 const struct rtw89_chip_info *chip = rtwdev->chip; 1744 char *p = buf, *end = buf + bufsz; 1745 u32 offset = 0; 1746 u32 cmac_err; 1747 int ret; 1748 1749 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1750 if (ret) { 1751 if (band) 1752 p += scnprintf(p, end - p, 1753 "[CMAC] : CMAC1 not enabled\n"); 1754 else 1755 p += scnprintf(p, end - p, 1756 "[CMAC] : CMAC0 not enabled\n"); 1757 goto out; 1758 } 1759 1760 if (band) 1761 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1762 1763 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1764 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1765 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1766 p += scnprintf(p, end - p, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1767 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1768 p += scnprintf(p, end - p, "R_AX_CK_EN [%d]=0x%08x\n", band, 1769 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1770 1771 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1772 p += scnprintf(p, end - p, 1773 "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1774 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1775 p += scnprintf(p, end - p, 1776 "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1777 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1778 } 1779 1780 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1781 p += scnprintf(p, end - p, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", 1782 band, 1783 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1784 p += scnprintf(p, end - p, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", 1785 band, 1786 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1787 } 1788 1789 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1790 if (chip->chip_id == RTL8852C) { 1791 p += scnprintf(p, end - p, 1792 "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1793 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1794 p += scnprintf(p, end - p, 1795 "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", 1796 band, 1797 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1798 } else { 1799 p += scnprintf(p, end - p, 1800 "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1801 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1802 } 1803 } 1804 1805 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1806 if (chip->chip_id == RTL8852C) { 1807 p += scnprintf(p, end - p, 1808 "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", 1809 band, 1810 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1811 p += scnprintf(p, end - p, 1812 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1813 band, 1814 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1815 } else { 1816 p += scnprintf(p, end - p, 1817 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1818 band, 1819 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1820 } 1821 } 1822 1823 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1824 p += scnprintf(p, end - p, "R_AX_TXPWR_IMR [%d]=0x%08x\n", 1825 band, 1826 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1827 p += scnprintf(p, end - p, "R_AX_TXPWR_ISR [%d]=0x%08x\n", 1828 band, 1829 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1830 } 1831 1832 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1833 if (chip->chip_id == RTL8852C) { 1834 p += scnprintf(p, end - p, 1835 "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", 1836 band, 1837 rtw89_read32(rtwdev, 1838 R_AX_TRXPTCL_ERROR_INDICA + offset)); 1839 p += scnprintf(p, end - p, 1840 "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", 1841 band, 1842 rtw89_read32(rtwdev, 1843 R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1844 } else { 1845 p += scnprintf(p, end - p, 1846 "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", 1847 band, 1848 rtw89_read32(rtwdev, 1849 R_AX_TMAC_ERR_IMR_ISR + offset)); 1850 } 1851 p += scnprintf(p, end - p, 1852 "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1853 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1854 } 1855 1856 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1857 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1858 1859 out: 1860 return p - buf; 1861 } 1862 1863 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1864 char *buf, size_t bufsz) 1865 { 1866 char *p = buf, *end = buf + bufsz; 1867 1868 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_0); 1869 if (rtwdev->dbcc_en) 1870 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_1); 1871 1872 return p - buf; 1873 } 1874 1875 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1876 .sel_addr = R_AX_PTCL_DBG, 1877 .sel_byte = 1, 1878 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1879 .srt = 0x00, 1880 .end = 0x3F, 1881 .rd_addr = R_AX_PTCL_DBG_INFO, 1882 .rd_byte = 4, 1883 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1884 }; 1885 1886 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1887 .sel_addr = R_AX_PTCL_DBG_C1, 1888 .sel_byte = 1, 1889 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1890 .srt = 0x00, 1891 .end = 0x3F, 1892 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1893 .rd_byte = 4, 1894 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1895 }; 1896 1897 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1898 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1899 .sel_byte = 2, 1900 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1901 .srt = 0x0, 1902 .end = 0xD, 1903 .rd_addr = R_AX_DBG_PORT_SEL, 1904 .rd_byte = 4, 1905 .rd_msk = B_AX_DEBUG_ST_MASK 1906 }; 1907 1908 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1909 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1910 .sel_byte = 2, 1911 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1912 .srt = 0x0, 1913 .end = 0x5, 1914 .rd_addr = R_AX_DBG_PORT_SEL, 1915 .rd_byte = 4, 1916 .rd_msk = B_AX_DEBUG_ST_MASK 1917 }; 1918 1919 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1920 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1921 .sel_byte = 2, 1922 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1923 .srt = 0x0, 1924 .end = 0x9, 1925 .rd_addr = R_AX_DBG_PORT_SEL, 1926 .rd_byte = 4, 1927 .rd_msk = B_AX_DEBUG_ST_MASK 1928 }; 1929 1930 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1931 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1932 .sel_byte = 2, 1933 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1934 .srt = 0x0, 1935 .end = 0x3, 1936 .rd_addr = R_AX_DBG_PORT_SEL, 1937 .rd_byte = 4, 1938 .rd_msk = B_AX_DEBUG_ST_MASK 1939 }; 1940 1941 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1942 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1943 .sel_byte = 2, 1944 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1945 .srt = 0x0, 1946 .end = 0x1, 1947 .rd_addr = R_AX_DBG_PORT_SEL, 1948 .rd_byte = 4, 1949 .rd_msk = B_AX_DEBUG_ST_MASK 1950 }; 1951 1952 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1953 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1954 .sel_byte = 2, 1955 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1956 .srt = 0x0, 1957 .end = 0x0, 1958 .rd_addr = R_AX_DBG_PORT_SEL, 1959 .rd_byte = 4, 1960 .rd_msk = B_AX_DEBUG_ST_MASK 1961 }; 1962 1963 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1964 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1965 .sel_byte = 2, 1966 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1967 .srt = 0x0, 1968 .end = 0xB, 1969 .rd_addr = R_AX_DBG_PORT_SEL, 1970 .rd_byte = 4, 1971 .rd_msk = B_AX_DEBUG_ST_MASK 1972 }; 1973 1974 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1975 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1976 .sel_byte = 2, 1977 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1978 .srt = 0x0, 1979 .end = 0x4, 1980 .rd_addr = R_AX_DBG_PORT_SEL, 1981 .rd_byte = 4, 1982 .rd_msk = B_AX_DEBUG_ST_MASK 1983 }; 1984 1985 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1986 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1987 .sel_byte = 2, 1988 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1989 .srt = 0x0, 1990 .end = 0x8, 1991 .rd_addr = R_AX_DBG_PORT_SEL, 1992 .rd_byte = 4, 1993 .rd_msk = B_AX_DEBUG_ST_MASK 1994 }; 1995 1996 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1997 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1998 .sel_byte = 2, 1999 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2000 .srt = 0x0, 2001 .end = 0x7, 2002 .rd_addr = R_AX_DBG_PORT_SEL, 2003 .rd_byte = 4, 2004 .rd_msk = B_AX_DEBUG_ST_MASK 2005 }; 2006 2007 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 2008 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2009 .sel_byte = 2, 2010 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2011 .srt = 0x0, 2012 .end = 0x1, 2013 .rd_addr = R_AX_DBG_PORT_SEL, 2014 .rd_byte = 4, 2015 .rd_msk = B_AX_DEBUG_ST_MASK 2016 }; 2017 2018 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 2019 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2020 .sel_byte = 2, 2021 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2022 .srt = 0x0, 2023 .end = 0x3, 2024 .rd_addr = R_AX_DBG_PORT_SEL, 2025 .rd_byte = 4, 2026 .rd_msk = B_AX_DEBUG_ST_MASK 2027 }; 2028 2029 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 2030 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2031 .sel_byte = 2, 2032 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2033 .srt = 0x0, 2034 .end = 0x0, 2035 .rd_addr = R_AX_DBG_PORT_SEL, 2036 .rd_byte = 4, 2037 .rd_msk = B_AX_DEBUG_ST_MASK 2038 }; 2039 2040 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 2041 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2042 .sel_byte = 2, 2043 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2044 .srt = 0x0, 2045 .end = 0x8, 2046 .rd_addr = R_AX_DBG_PORT_SEL, 2047 .rd_byte = 4, 2048 .rd_msk = B_AX_DEBUG_ST_MASK 2049 }; 2050 2051 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 2052 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2053 .sel_byte = 2, 2054 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2055 .srt = 0x0, 2056 .end = 0x0, 2057 .rd_addr = R_AX_DBG_PORT_SEL, 2058 .rd_byte = 4, 2059 .rd_msk = B_AX_DEBUG_ST_MASK 2060 }; 2061 2062 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 2063 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2064 .sel_byte = 2, 2065 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2066 .srt = 0x0, 2067 .end = 0x6, 2068 .rd_addr = R_AX_DBG_PORT_SEL, 2069 .rd_byte = 4, 2070 .rd_msk = B_AX_DEBUG_ST_MASK 2071 }; 2072 2073 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 2074 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2075 .sel_byte = 2, 2076 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2077 .srt = 0x0, 2078 .end = 0x0, 2079 .rd_addr = R_AX_DBG_PORT_SEL, 2080 .rd_byte = 4, 2081 .rd_msk = B_AX_DEBUG_ST_MASK 2082 }; 2083 2084 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 2085 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2086 .sel_byte = 2, 2087 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2088 .srt = 0x0, 2089 .end = 0x0, 2090 .rd_addr = R_AX_DBG_PORT_SEL, 2091 .rd_byte = 4, 2092 .rd_msk = B_AX_DEBUG_ST_MASK 2093 }; 2094 2095 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 2096 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2097 .sel_byte = 1, 2098 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2099 .srt = 0x0, 2100 .end = 0x3, 2101 .rd_addr = R_AX_DBG_PORT_SEL, 2102 .rd_byte = 4, 2103 .rd_msk = B_AX_DEBUG_ST_MASK 2104 }; 2105 2106 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 2107 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2108 .sel_byte = 1, 2109 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2110 .srt = 0x0, 2111 .end = 0x6, 2112 .rd_addr = R_AX_DBG_PORT_SEL, 2113 .rd_byte = 4, 2114 .rd_msk = B_AX_DEBUG_ST_MASK 2115 }; 2116 2117 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 2118 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2119 .sel_byte = 1, 2120 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2121 .srt = 0x0, 2122 .end = 0x0, 2123 .rd_addr = R_AX_DBG_PORT_SEL, 2124 .rd_byte = 4, 2125 .rd_msk = B_AX_DEBUG_ST_MASK 2126 }; 2127 2128 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 2129 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2130 .sel_byte = 1, 2131 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2132 .srt = 0x8, 2133 .end = 0xE, 2134 .rd_addr = R_AX_DBG_PORT_SEL, 2135 .rd_byte = 4, 2136 .rd_msk = B_AX_DEBUG_ST_MASK 2137 }; 2138 2139 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 2140 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2141 .sel_byte = 1, 2142 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2143 .srt = 0x0, 2144 .end = 0x5, 2145 .rd_addr = R_AX_DBG_PORT_SEL, 2146 .rd_byte = 4, 2147 .rd_msk = B_AX_DEBUG_ST_MASK 2148 }; 2149 2150 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 2151 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2152 .sel_byte = 1, 2153 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2154 .srt = 0x0, 2155 .end = 0x6, 2156 .rd_addr = R_AX_DBG_PORT_SEL, 2157 .rd_byte = 4, 2158 .rd_msk = B_AX_DEBUG_ST_MASK 2159 }; 2160 2161 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 2162 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2163 .sel_byte = 1, 2164 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2165 .srt = 0x0, 2166 .end = 0xF, 2167 .rd_addr = R_AX_DBG_PORT_SEL, 2168 .rd_byte = 4, 2169 .rd_msk = B_AX_DEBUG_ST_MASK 2170 }; 2171 2172 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 2173 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2174 .sel_byte = 1, 2175 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2176 .srt = 0x0, 2177 .end = 0x9, 2178 .rd_addr = R_AX_DBG_PORT_SEL, 2179 .rd_byte = 4, 2180 .rd_msk = B_AX_DEBUG_ST_MASK 2181 }; 2182 2183 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 2184 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2185 .sel_byte = 1, 2186 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2187 .srt = 0x0, 2188 .end = 0x3, 2189 .rd_addr = R_AX_DBG_PORT_SEL, 2190 .rd_byte = 4, 2191 .rd_msk = B_AX_DEBUG_ST_MASK 2192 }; 2193 2194 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 2195 .sel_addr = R_AX_SCH_DBG_SEL, 2196 .sel_byte = 1, 2197 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2198 .srt = 0x00, 2199 .end = 0x2F, 2200 .rd_addr = R_AX_SCH_DBG, 2201 .rd_byte = 4, 2202 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2203 }; 2204 2205 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 2206 .sel_addr = R_AX_SCH_DBG_SEL_C1, 2207 .sel_byte = 1, 2208 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2209 .srt = 0x00, 2210 .end = 0x2F, 2211 .rd_addr = R_AX_SCH_DBG_C1, 2212 .rd_byte = 4, 2213 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2214 }; 2215 2216 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 2217 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 2218 .sel_byte = 1, 2219 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2220 .srt = 0x00, 2221 .end = 0x19, 2222 .rd_addr = R_AX_DBG_PORT_SEL, 2223 .rd_byte = 4, 2224 .rd_msk = B_AX_DEBUG_ST_MASK 2225 }; 2226 2227 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 2228 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 2229 .sel_byte = 1, 2230 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2231 .srt = 0x00, 2232 .end = 0x19, 2233 .rd_addr = R_AX_DBG_PORT_SEL, 2234 .rd_byte = 4, 2235 .rd_msk = B_AX_DEBUG_ST_MASK 2236 }; 2237 2238 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 2239 .sel_addr = R_AX_RX_DEBUG_SELECT, 2240 .sel_byte = 1, 2241 .sel_msk = B_AX_DEBUG_SEL_MASK, 2242 .srt = 0x00, 2243 .end = 0x58, 2244 .rd_addr = R_AX_DBG_PORT_SEL, 2245 .rd_byte = 4, 2246 .rd_msk = B_AX_DEBUG_ST_MASK 2247 }; 2248 2249 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 2250 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 2251 .sel_byte = 1, 2252 .sel_msk = B_AX_DEBUG_SEL_MASK, 2253 .srt = 0x00, 2254 .end = 0x58, 2255 .rd_addr = R_AX_DBG_PORT_SEL, 2256 .rd_byte = 4, 2257 .rd_msk = B_AX_DEBUG_ST_MASK 2258 }; 2259 2260 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 2261 .sel_addr = R_AX_RX_STATE_MONITOR, 2262 .sel_byte = 1, 2263 .sel_msk = B_AX_STATE_SEL_MASK, 2264 .srt = 0x00, 2265 .end = 0x17, 2266 .rd_addr = R_AX_RX_STATE_MONITOR, 2267 .rd_byte = 4, 2268 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2269 }; 2270 2271 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 2272 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 2273 .sel_byte = 1, 2274 .sel_msk = B_AX_STATE_SEL_MASK, 2275 .srt = 0x00, 2276 .end = 0x17, 2277 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 2278 .rd_byte = 4, 2279 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2280 }; 2281 2282 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 2283 .sel_addr = R_AX_RMAC_PLCP_MON, 2284 .sel_byte = 4, 2285 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2286 .srt = 0x0, 2287 .end = 0xF, 2288 .rd_addr = R_AX_RMAC_PLCP_MON, 2289 .rd_byte = 4, 2290 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2291 }; 2292 2293 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 2294 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 2295 .sel_byte = 4, 2296 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2297 .srt = 0x0, 2298 .end = 0xF, 2299 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 2300 .rd_byte = 4, 2301 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2302 }; 2303 2304 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 2305 .sel_addr = R_AX_DBGSEL_TRXPTCL, 2306 .sel_byte = 1, 2307 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2308 .srt = 0x08, 2309 .end = 0x10, 2310 .rd_addr = R_AX_DBG_PORT_SEL, 2311 .rd_byte = 4, 2312 .rd_msk = B_AX_DEBUG_ST_MASK 2313 }; 2314 2315 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 2316 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 2317 .sel_byte = 1, 2318 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2319 .srt = 0x08, 2320 .end = 0x10, 2321 .rd_addr = R_AX_DBG_PORT_SEL, 2322 .rd_byte = 4, 2323 .rd_msk = B_AX_DEBUG_ST_MASK 2324 }; 2325 2326 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 2327 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2328 .sel_byte = 1, 2329 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2330 .srt = 0x00, 2331 .end = 0x07, 2332 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 2333 .rd_byte = 4, 2334 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2335 }; 2336 2337 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 2338 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2339 .sel_byte = 1, 2340 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2341 .srt = 0x00, 2342 .end = 0x07, 2343 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 2344 .rd_byte = 4, 2345 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2346 }; 2347 2348 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 2349 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2350 .sel_byte = 1, 2351 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2352 .srt = 0x00, 2353 .end = 0x07, 2354 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 2355 .rd_byte = 4, 2356 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2357 }; 2358 2359 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 2360 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2361 .sel_byte = 1, 2362 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2363 .srt = 0x00, 2364 .end = 0x07, 2365 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 2366 .rd_byte = 4, 2367 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2368 }; 2369 2370 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 2371 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2372 .sel_byte = 1, 2373 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2374 .srt = 0x00, 2375 .end = 0x04, 2376 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 2377 .rd_byte = 4, 2378 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2379 }; 2380 2381 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 2382 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2383 .sel_byte = 1, 2384 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2385 .srt = 0x00, 2386 .end = 0x04, 2387 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 2388 .rd_byte = 4, 2389 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2390 }; 2391 2392 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 2393 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2394 .sel_byte = 1, 2395 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2396 .srt = 0x00, 2397 .end = 0x04, 2398 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 2399 .rd_byte = 4, 2400 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2401 }; 2402 2403 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 2404 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2405 .sel_byte = 1, 2406 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2407 .srt = 0x00, 2408 .end = 0x04, 2409 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 2410 .rd_byte = 4, 2411 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2412 }; 2413 2414 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 2415 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2416 .sel_byte = 4, 2417 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2418 .srt = 0x80000000, 2419 .end = 0x80000001, 2420 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2421 .rd_byte = 4, 2422 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2423 }; 2424 2425 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 2426 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2427 .sel_byte = 4, 2428 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2429 .srt = 0x80010000, 2430 .end = 0x80010004, 2431 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2432 .rd_byte = 4, 2433 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2434 }; 2435 2436 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 2437 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2438 .sel_byte = 4, 2439 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2440 .srt = 0x80020000, 2441 .end = 0x80020FFF, 2442 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2443 .rd_byte = 4, 2444 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2445 }; 2446 2447 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 2448 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2449 .sel_byte = 4, 2450 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2451 .srt = 0x80030000, 2452 .end = 0x80030FFF, 2453 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2454 .rd_byte = 4, 2455 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2456 }; 2457 2458 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 2459 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2460 .sel_byte = 4, 2461 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2462 .srt = 0x80040000, 2463 .end = 0x80040FFF, 2464 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2465 .rd_byte = 4, 2466 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2467 }; 2468 2469 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 2470 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2471 .sel_byte = 4, 2472 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2473 .srt = 0x80050000, 2474 .end = 0x80050FFF, 2475 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2476 .rd_byte = 4, 2477 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2478 }; 2479 2480 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 2481 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2482 .sel_byte = 4, 2483 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2484 .srt = 0x80060000, 2485 .end = 0x80060453, 2486 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2487 .rd_byte = 4, 2488 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2489 }; 2490 2491 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 2492 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2493 .sel_byte = 4, 2494 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2495 .srt = 0x80070000, 2496 .end = 0x80070011, 2497 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2498 .rd_byte = 4, 2499 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2500 }; 2501 2502 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 2503 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2504 .sel_byte = 4, 2505 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2506 .srt = 0x80000000, 2507 .end = 0x80000001, 2508 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2509 .rd_byte = 4, 2510 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2511 }; 2512 2513 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 2514 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2515 .sel_byte = 4, 2516 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2517 .srt = 0x80010000, 2518 .end = 0x8001000A, 2519 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2520 .rd_byte = 4, 2521 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2522 }; 2523 2524 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2525 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2526 .sel_byte = 4, 2527 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2528 .srt = 0x80020000, 2529 .end = 0x80020DBF, 2530 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2531 .rd_byte = 4, 2532 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2533 }; 2534 2535 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2536 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2537 .sel_byte = 4, 2538 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2539 .srt = 0x80030000, 2540 .end = 0x80030DBF, 2541 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2542 .rd_byte = 4, 2543 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2544 }; 2545 2546 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2547 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2548 .sel_byte = 4, 2549 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2550 .srt = 0x80040000, 2551 .end = 0x80040DBF, 2552 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2553 .rd_byte = 4, 2554 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2555 }; 2556 2557 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2558 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2559 .sel_byte = 4, 2560 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2561 .srt = 0x80050000, 2562 .end = 0x80050DBF, 2563 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2564 .rd_byte = 4, 2565 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2566 }; 2567 2568 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2569 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2570 .sel_byte = 4, 2571 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2572 .srt = 0x80060000, 2573 .end = 0x80060041, 2574 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2575 .rd_byte = 4, 2576 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2577 }; 2578 2579 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2580 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2581 .sel_byte = 4, 2582 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2583 .srt = 0x80070000, 2584 .end = 0x80070001, 2585 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2586 .rd_byte = 4, 2587 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2588 }; 2589 2590 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2591 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2592 .sel_byte = 4, 2593 .sel_msk = B_AX_DFI_DATA_MASK, 2594 .srt = 0x80000000, 2595 .end = 0x8000017f, 2596 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2597 .rd_byte = 4, 2598 .rd_msk = B_AX_DFI_DATA_MASK 2599 }; 2600 2601 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2602 .sel_addr = R_AX_PCIE_DBG_CTRL, 2603 .sel_byte = 2, 2604 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2605 .srt = 0x00, 2606 .end = 0x03, 2607 .rd_addr = R_AX_DBG_PORT_SEL, 2608 .rd_byte = 4, 2609 .rd_msk = B_AX_DEBUG_ST_MASK 2610 }; 2611 2612 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2613 .sel_addr = R_AX_PCIE_DBG_CTRL, 2614 .sel_byte = 2, 2615 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2616 .srt = 0x00, 2617 .end = 0x04, 2618 .rd_addr = R_AX_DBG_PORT_SEL, 2619 .rd_byte = 4, 2620 .rd_msk = B_AX_DEBUG_ST_MASK 2621 }; 2622 2623 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2624 .sel_addr = R_AX_PCIE_DBG_CTRL, 2625 .sel_byte = 2, 2626 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2627 .srt = 0x00, 2628 .end = 0x01, 2629 .rd_addr = R_AX_DBG_PORT_SEL, 2630 .rd_byte = 4, 2631 .rd_msk = B_AX_DEBUG_ST_MASK 2632 }; 2633 2634 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2635 .sel_addr = R_AX_PCIE_DBG_CTRL, 2636 .sel_byte = 2, 2637 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2638 .srt = 0x00, 2639 .end = 0x05, 2640 .rd_addr = R_AX_DBG_PORT_SEL, 2641 .rd_byte = 4, 2642 .rd_msk = B_AX_DEBUG_ST_MASK 2643 }; 2644 2645 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2646 .sel_addr = R_AX_PCIE_DBG_CTRL, 2647 .sel_byte = 2, 2648 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2649 .srt = 0x00, 2650 .end = 0x05, 2651 .rd_addr = R_AX_DBG_PORT_SEL, 2652 .rd_byte = 4, 2653 .rd_msk = B_AX_DEBUG_ST_MASK 2654 }; 2655 2656 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2657 .sel_addr = R_AX_PCIE_DBG_CTRL, 2658 .sel_byte = 2, 2659 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2660 .srt = 0x00, 2661 .end = 0x06, 2662 .rd_addr = R_AX_DBG_PORT_SEL, 2663 .rd_byte = 4, 2664 .rd_msk = B_AX_DEBUG_ST_MASK 2665 }; 2666 2667 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2668 .sel_addr = R_AX_DBG_CTRL, 2669 .sel_byte = 1, 2670 .sel_msk = B_AX_DBG_SEL0, 2671 .srt = 0x34, 2672 .end = 0x3C, 2673 .rd_addr = R_AX_DBG_PORT_SEL, 2674 .rd_byte = 4, 2675 .rd_msk = B_AX_DEBUG_ST_MASK 2676 }; 2677 2678 static int 2679 rtw89_debug_mac_dbg_port_sel(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 2680 u32 sel, const struct rtw89_mac_dbg_port_info **ppinfo) 2681 { 2682 const struct rtw89_mac_dbg_port_info *info = NULL; 2683 char *p = buf, *end = buf + bufsz; 2684 u32 index; 2685 u32 val32; 2686 u16 val16; 2687 u8 val8; 2688 2689 switch (sel) { 2690 case RTW89_DBG_PORT_SEL_PTCL_C0: 2691 info = &dbg_port_ptcl_c0; 2692 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2693 val16 |= B_AX_PTCL_DBG_EN; 2694 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2695 p += scnprintf(p, end - p, "Enable PTCL C0 dbgport.\n"); 2696 break; 2697 case RTW89_DBG_PORT_SEL_PTCL_C1: 2698 info = &dbg_port_ptcl_c1; 2699 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2700 val16 |= B_AX_PTCL_DBG_EN; 2701 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2702 p += scnprintf(p, end - p, "Enable PTCL C1 dbgport.\n"); 2703 break; 2704 case RTW89_DBG_PORT_SEL_SCH_C0: 2705 info = &dbg_port_sch_c0; 2706 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2707 val32 |= B_AX_SCH_DBG_EN; 2708 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2709 p += scnprintf(p, end - p, "Enable SCH C0 dbgport.\n"); 2710 break; 2711 case RTW89_DBG_PORT_SEL_SCH_C1: 2712 info = &dbg_port_sch_c1; 2713 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2714 val32 |= B_AX_SCH_DBG_EN; 2715 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2716 p += scnprintf(p, end - p, "Enable SCH C1 dbgport.\n"); 2717 break; 2718 case RTW89_DBG_PORT_SEL_TMAC_C0: 2719 info = &dbg_port_tmac_c0; 2720 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2721 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2722 B_AX_DBGSEL_TRXPTCL_MASK); 2723 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2724 2725 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2726 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2727 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2728 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2729 2730 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2731 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2732 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2733 p += scnprintf(p, end - p, "Enable TMAC C0 dbgport.\n"); 2734 break; 2735 case RTW89_DBG_PORT_SEL_TMAC_C1: 2736 info = &dbg_port_tmac_c1; 2737 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2738 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2739 B_AX_DBGSEL_TRXPTCL_MASK); 2740 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2741 2742 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2743 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2744 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2745 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2746 2747 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2748 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2749 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2750 p += scnprintf(p, end - p, "Enable TMAC C1 dbgport.\n"); 2751 break; 2752 case RTW89_DBG_PORT_SEL_RMAC_C0: 2753 info = &dbg_port_rmac_c0; 2754 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2755 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2756 B_AX_DBGSEL_TRXPTCL_MASK); 2757 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2758 2759 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2760 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2761 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2762 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2763 2764 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2765 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2766 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2767 2768 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2769 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2770 B_AX_DBGSEL_TRXPTCL_MASK); 2771 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2772 p += scnprintf(p, end - p, "Enable RMAC C0 dbgport.\n"); 2773 break; 2774 case RTW89_DBG_PORT_SEL_RMAC_C1: 2775 info = &dbg_port_rmac_c1; 2776 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2777 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2778 B_AX_DBGSEL_TRXPTCL_MASK); 2779 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2780 2781 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2782 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2783 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2784 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2785 2786 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2787 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2788 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2789 2790 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2791 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2792 B_AX_DBGSEL_TRXPTCL_MASK); 2793 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2794 p += scnprintf(p, end - p, "Enable RMAC C1 dbgport.\n"); 2795 break; 2796 case RTW89_DBG_PORT_SEL_RMACST_C0: 2797 info = &dbg_port_rmacst_c0; 2798 p += scnprintf(p, end - p, "Enable RMAC state C0 dbgport.\n"); 2799 break; 2800 case RTW89_DBG_PORT_SEL_RMACST_C1: 2801 info = &dbg_port_rmacst_c1; 2802 p += scnprintf(p, end - p, "Enable RMAC state C1 dbgport.\n"); 2803 break; 2804 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2805 info = &dbg_port_rmac_plcp_c0; 2806 p += scnprintf(p, end - p, "Enable RMAC PLCP C0 dbgport.\n"); 2807 break; 2808 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2809 info = &dbg_port_rmac_plcp_c1; 2810 p += scnprintf(p, end - p, "Enable RMAC PLCP C1 dbgport.\n"); 2811 break; 2812 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2813 info = &dbg_port_trxptcl_c0; 2814 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2815 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2816 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2817 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2818 2819 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2820 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2821 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2822 p += scnprintf(p, end - p, "Enable TRXPTCL C0 dbgport.\n"); 2823 break; 2824 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2825 info = &dbg_port_trxptcl_c1; 2826 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2827 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2828 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2829 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2830 2831 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2832 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2833 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2834 p += scnprintf(p, end - p, "Enable TRXPTCL C1 dbgport.\n"); 2835 break; 2836 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2837 info = &dbg_port_tx_infol_c0; 2838 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2839 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2840 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2841 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2842 break; 2843 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2844 info = &dbg_port_tx_infoh_c0; 2845 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2846 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2847 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2848 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2849 break; 2850 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2851 info = &dbg_port_tx_infol_c1; 2852 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2853 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2854 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2855 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2856 break; 2857 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2858 info = &dbg_port_tx_infoh_c1; 2859 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2860 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2861 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2862 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2863 break; 2864 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2865 info = &dbg_port_txtf_infol_c0; 2866 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2867 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2868 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2869 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2870 break; 2871 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2872 info = &dbg_port_txtf_infoh_c0; 2873 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2874 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2875 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2876 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2877 break; 2878 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2879 info = &dbg_port_txtf_infol_c1; 2880 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2881 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2882 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2883 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2884 break; 2885 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2886 info = &dbg_port_txtf_infoh_c1; 2887 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2888 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2889 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2890 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2891 break; 2892 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2893 info = &dbg_port_wde_bufmgn_freepg; 2894 p += scnprintf(p, end - p, "Enable wde bufmgn freepg dump.\n"); 2895 break; 2896 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2897 info = &dbg_port_wde_bufmgn_quota; 2898 p += scnprintf(p, end - p, "Enable wde bufmgn quota dump.\n"); 2899 break; 2900 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2901 info = &dbg_port_wde_bufmgn_pagellt; 2902 p += scnprintf(p, end - p, 2903 "Enable wde bufmgn pagellt dump.\n"); 2904 break; 2905 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2906 info = &dbg_port_wde_bufmgn_pktinfo; 2907 p += scnprintf(p, end - p, 2908 "Enable wde bufmgn pktinfo dump.\n"); 2909 break; 2910 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2911 info = &dbg_port_wde_quemgn_prepkt; 2912 p += scnprintf(p, end - p, "Enable wde quemgn prepkt dump.\n"); 2913 break; 2914 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2915 info = &dbg_port_wde_quemgn_nxtpkt; 2916 p += scnprintf(p, end - p, "Enable wde quemgn nxtpkt dump.\n"); 2917 break; 2918 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2919 info = &dbg_port_wde_quemgn_qlnktbl; 2920 p += scnprintf(p, end - p, 2921 "Enable wde quemgn qlnktbl dump.\n"); 2922 break; 2923 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2924 info = &dbg_port_wde_quemgn_qempty; 2925 p += scnprintf(p, end - p, "Enable wde quemgn qempty dump.\n"); 2926 break; 2927 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2928 info = &dbg_port_ple_bufmgn_freepg; 2929 p += scnprintf(p, end - p, "Enable ple bufmgn freepg dump.\n"); 2930 break; 2931 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2932 info = &dbg_port_ple_bufmgn_quota; 2933 p += scnprintf(p, end - p, "Enable ple bufmgn quota dump.\n"); 2934 break; 2935 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2936 info = &dbg_port_ple_bufmgn_pagellt; 2937 p += scnprintf(p, end - p, 2938 "Enable ple bufmgn pagellt dump.\n"); 2939 break; 2940 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2941 info = &dbg_port_ple_bufmgn_pktinfo; 2942 p += scnprintf(p, end - p, 2943 "Enable ple bufmgn pktinfo dump.\n"); 2944 break; 2945 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2946 info = &dbg_port_ple_quemgn_prepkt; 2947 p += scnprintf(p, end - p, "Enable ple quemgn prepkt dump.\n"); 2948 break; 2949 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2950 info = &dbg_port_ple_quemgn_nxtpkt; 2951 p += scnprintf(p, end - p, "Enable ple quemgn nxtpkt dump.\n"); 2952 break; 2953 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2954 info = &dbg_port_ple_quemgn_qlnktbl; 2955 p += scnprintf(p, end - p, 2956 "Enable ple quemgn qlnktbl dump.\n"); 2957 break; 2958 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2959 info = &dbg_port_ple_quemgn_qempty; 2960 p += scnprintf(p, end - p, "Enable ple quemgn qempty dump.\n"); 2961 break; 2962 case RTW89_DBG_PORT_SEL_PKTINFO: 2963 info = &dbg_port_pktinfo; 2964 p += scnprintf(p, end - p, "Enable pktinfo dump.\n"); 2965 break; 2966 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2967 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2968 B_AX_DBG_SEL0, 0x80); 2969 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2970 B_AX_SEL_0XC0_MASK, 1); 2971 fallthrough; 2972 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2973 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2974 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2975 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2976 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2977 info = &dbg_port_dspt_hdt_tx0_5; 2978 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2979 rtw89_write16_mask(rtwdev, info->sel_addr, 2980 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2981 rtw89_write16_mask(rtwdev, info->sel_addr, 2982 B_AX_DISPATCHER_CH_SEL_MASK, index); 2983 p += scnprintf(p, end - p, 2984 "Enable Dispatcher hdt tx%x dump.\n", index); 2985 break; 2986 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2987 info = &dbg_port_dspt_hdt_tx6; 2988 rtw89_write16_mask(rtwdev, info->sel_addr, 2989 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2990 rtw89_write16_mask(rtwdev, info->sel_addr, 2991 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2992 p += scnprintf(p, end - p, 2993 "Enable Dispatcher hdt tx6 dump.\n"); 2994 break; 2995 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2996 info = &dbg_port_dspt_hdt_tx7; 2997 rtw89_write16_mask(rtwdev, info->sel_addr, 2998 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2999 rtw89_write16_mask(rtwdev, info->sel_addr, 3000 B_AX_DISPATCHER_CH_SEL_MASK, 7); 3001 p += scnprintf(p, end - p, 3002 "Enable Dispatcher hdt tx7 dump.\n"); 3003 break; 3004 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 3005 info = &dbg_port_dspt_hdt_tx8; 3006 rtw89_write16_mask(rtwdev, info->sel_addr, 3007 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 3008 rtw89_write16_mask(rtwdev, info->sel_addr, 3009 B_AX_DISPATCHER_CH_SEL_MASK, 8); 3010 p += scnprintf(p, end - p, 3011 "Enable Dispatcher hdt tx8 dump.\n"); 3012 break; 3013 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 3014 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 3015 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 3016 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 3017 info = &dbg_port_dspt_hdt_tx9_C; 3018 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 3019 rtw89_write16_mask(rtwdev, info->sel_addr, 3020 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 3021 rtw89_write16_mask(rtwdev, info->sel_addr, 3022 B_AX_DISPATCHER_CH_SEL_MASK, index); 3023 p += scnprintf(p, end - p, 3024 "Enable Dispatcher hdt tx%x dump.\n", index); 3025 break; 3026 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 3027 info = &dbg_port_dspt_hdt_txD; 3028 rtw89_write16_mask(rtwdev, info->sel_addr, 3029 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 3030 rtw89_write16_mask(rtwdev, info->sel_addr, 3031 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 3032 p += scnprintf(p, end - p, 3033 "Enable Dispatcher hdt txD dump.\n"); 3034 break; 3035 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 3036 info = &dbg_port_dspt_cdt_tx0; 3037 rtw89_write16_mask(rtwdev, info->sel_addr, 3038 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3039 rtw89_write16_mask(rtwdev, info->sel_addr, 3040 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3041 p += scnprintf(p, end - p, 3042 "Enable Dispatcher cdt tx0 dump.\n"); 3043 break; 3044 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 3045 info = &dbg_port_dspt_cdt_tx1; 3046 rtw89_write16_mask(rtwdev, info->sel_addr, 3047 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3048 rtw89_write16_mask(rtwdev, info->sel_addr, 3049 B_AX_DISPATCHER_CH_SEL_MASK, 1); 3050 p += scnprintf(p, end - p, 3051 "Enable Dispatcher cdt tx1 dump.\n"); 3052 break; 3053 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 3054 info = &dbg_port_dspt_cdt_tx3; 3055 rtw89_write16_mask(rtwdev, info->sel_addr, 3056 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3057 rtw89_write16_mask(rtwdev, info->sel_addr, 3058 B_AX_DISPATCHER_CH_SEL_MASK, 3); 3059 p += scnprintf(p, end - p, 3060 "Enable Dispatcher cdt tx3 dump.\n"); 3061 break; 3062 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 3063 info = &dbg_port_dspt_cdt_tx4; 3064 rtw89_write16_mask(rtwdev, info->sel_addr, 3065 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3066 rtw89_write16_mask(rtwdev, info->sel_addr, 3067 B_AX_DISPATCHER_CH_SEL_MASK, 4); 3068 p += scnprintf(p, end - p, 3069 "Enable Dispatcher cdt tx4 dump.\n"); 3070 break; 3071 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 3072 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 3073 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 3074 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 3075 info = &dbg_port_dspt_cdt_tx5_8; 3076 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 3077 rtw89_write16_mask(rtwdev, info->sel_addr, 3078 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3079 rtw89_write16_mask(rtwdev, info->sel_addr, 3080 B_AX_DISPATCHER_CH_SEL_MASK, index); 3081 p += scnprintf(p, end - p, 3082 "Enable Dispatcher cdt tx%x dump.\n", index); 3083 break; 3084 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 3085 info = &dbg_port_dspt_cdt_tx9; 3086 rtw89_write16_mask(rtwdev, info->sel_addr, 3087 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3088 rtw89_write16_mask(rtwdev, info->sel_addr, 3089 B_AX_DISPATCHER_CH_SEL_MASK, 9); 3090 p += scnprintf(p, end - p, 3091 "Enable Dispatcher cdt tx9 dump.\n"); 3092 break; 3093 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 3094 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 3095 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 3096 info = &dbg_port_dspt_cdt_txA_C; 3097 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 3098 rtw89_write16_mask(rtwdev, info->sel_addr, 3099 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3100 rtw89_write16_mask(rtwdev, info->sel_addr, 3101 B_AX_DISPATCHER_CH_SEL_MASK, index); 3102 p += scnprintf(p, end - p, 3103 "Enable Dispatcher cdt tx%x dump.\n", index); 3104 break; 3105 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 3106 info = &dbg_port_dspt_hdt_rx0; 3107 rtw89_write16_mask(rtwdev, info->sel_addr, 3108 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3109 rtw89_write16_mask(rtwdev, info->sel_addr, 3110 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3111 p += scnprintf(p, end - p, 3112 "Enable Dispatcher hdt rx0 dump.\n"); 3113 break; 3114 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 3115 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 3116 info = &dbg_port_dspt_hdt_rx1_2; 3117 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 3118 rtw89_write16_mask(rtwdev, info->sel_addr, 3119 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3120 rtw89_write16_mask(rtwdev, info->sel_addr, 3121 B_AX_DISPATCHER_CH_SEL_MASK, index); 3122 p += scnprintf(p, end - p, 3123 "Enable Dispatcher hdt rx%x dump.\n", index); 3124 break; 3125 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 3126 info = &dbg_port_dspt_hdt_rx3; 3127 rtw89_write16_mask(rtwdev, info->sel_addr, 3128 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3129 rtw89_write16_mask(rtwdev, info->sel_addr, 3130 B_AX_DISPATCHER_CH_SEL_MASK, 3); 3131 p += scnprintf(p, end - p, 3132 "Enable Dispatcher hdt rx3 dump.\n"); 3133 break; 3134 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 3135 info = &dbg_port_dspt_hdt_rx4; 3136 rtw89_write16_mask(rtwdev, info->sel_addr, 3137 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3138 rtw89_write16_mask(rtwdev, info->sel_addr, 3139 B_AX_DISPATCHER_CH_SEL_MASK, 4); 3140 p += scnprintf(p, end - p, 3141 "Enable Dispatcher hdt rx4 dump.\n"); 3142 break; 3143 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 3144 info = &dbg_port_dspt_hdt_rx5; 3145 rtw89_write16_mask(rtwdev, info->sel_addr, 3146 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3147 rtw89_write16_mask(rtwdev, info->sel_addr, 3148 B_AX_DISPATCHER_CH_SEL_MASK, 5); 3149 p += scnprintf(p, end - p, 3150 "Enable Dispatcher hdt rx5 dump.\n"); 3151 break; 3152 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 3153 info = &dbg_port_dspt_cdt_rx_p0_0; 3154 rtw89_write16_mask(rtwdev, info->sel_addr, 3155 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3156 rtw89_write16_mask(rtwdev, info->sel_addr, 3157 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3158 p += scnprintf(p, end - p, 3159 "Enable Dispatcher cdt rx part0 0 dump.\n"); 3160 break; 3161 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 3162 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 3163 info = &dbg_port_dspt_cdt_rx_p0_1; 3164 rtw89_write16_mask(rtwdev, info->sel_addr, 3165 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3166 rtw89_write16_mask(rtwdev, info->sel_addr, 3167 B_AX_DISPATCHER_CH_SEL_MASK, 1); 3168 p += scnprintf(p, end - p, 3169 "Enable Dispatcher cdt rx part0 1 dump.\n"); 3170 break; 3171 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 3172 info = &dbg_port_dspt_cdt_rx_p0_2; 3173 rtw89_write16_mask(rtwdev, info->sel_addr, 3174 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3175 rtw89_write16_mask(rtwdev, info->sel_addr, 3176 B_AX_DISPATCHER_CH_SEL_MASK, 2); 3177 p += scnprintf(p, end - p, 3178 "Enable Dispatcher cdt rx part0 2 dump.\n"); 3179 break; 3180 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 3181 info = &dbg_port_dspt_cdt_rx_p1; 3182 rtw89_write8_mask(rtwdev, info->sel_addr, 3183 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3184 p += scnprintf(p, end - p, 3185 "Enable Dispatcher cdt rx part1 dump.\n"); 3186 break; 3187 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 3188 info = &dbg_port_dspt_stf_ctrl; 3189 rtw89_write8_mask(rtwdev, info->sel_addr, 3190 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 3191 p += scnprintf(p, end - p, 3192 "Enable Dispatcher stf control dump.\n"); 3193 break; 3194 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 3195 info = &dbg_port_dspt_addr_ctrl; 3196 rtw89_write8_mask(rtwdev, info->sel_addr, 3197 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 3198 p += scnprintf(p, end - p, 3199 "Enable Dispatcher addr control dump.\n"); 3200 break; 3201 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 3202 info = &dbg_port_dspt_wde_intf; 3203 rtw89_write8_mask(rtwdev, info->sel_addr, 3204 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 3205 p += scnprintf(p, end - p, 3206 "Enable Dispatcher wde interface dump.\n"); 3207 break; 3208 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 3209 info = &dbg_port_dspt_ple_intf; 3210 rtw89_write8_mask(rtwdev, info->sel_addr, 3211 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 3212 p += scnprintf(p, end - p, 3213 "Enable Dispatcher ple interface dump.\n"); 3214 break; 3215 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 3216 info = &dbg_port_dspt_flow_ctrl; 3217 rtw89_write8_mask(rtwdev, info->sel_addr, 3218 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 3219 p += scnprintf(p, end - p, 3220 "Enable Dispatcher flow control dump.\n"); 3221 break; 3222 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 3223 info = &dbg_port_pcie_txdma; 3224 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3225 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 3226 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 3227 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3228 p += scnprintf(p, end - p, "Enable pcie txdma dump.\n"); 3229 break; 3230 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 3231 info = &dbg_port_pcie_rxdma; 3232 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3233 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 3234 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 3235 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3236 p += scnprintf(p, end - p, "Enable pcie rxdma dump.\n"); 3237 break; 3238 case RTW89_DBG_PORT_SEL_PCIE_CVT: 3239 info = &dbg_port_pcie_cvt; 3240 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3241 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 3242 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 3243 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3244 p += scnprintf(p, end - p, "Enable pcie cvt dump.\n"); 3245 break; 3246 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 3247 info = &dbg_port_pcie_cxpl; 3248 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3249 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 3250 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 3251 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3252 p += scnprintf(p, end - p, "Enable pcie cxpl dump.\n"); 3253 break; 3254 case RTW89_DBG_PORT_SEL_PCIE_IO: 3255 info = &dbg_port_pcie_io; 3256 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3257 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 3258 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 3259 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3260 p += scnprintf(p, end - p, "Enable pcie io dump.\n"); 3261 break; 3262 case RTW89_DBG_PORT_SEL_PCIE_MISC: 3263 info = &dbg_port_pcie_misc; 3264 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3265 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 3266 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 3267 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3268 p += scnprintf(p, end - p, "Enable pcie misc dump.\n"); 3269 break; 3270 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 3271 info = &dbg_port_pcie_misc2; 3272 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 3273 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 3274 B_AX_PCIE_DBG_SEL_MASK); 3275 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 3276 p += scnprintf(p, end - p, "Enable pcie misc2 dump.\n"); 3277 break; 3278 default: 3279 p += scnprintf(p, end - p, "Dbg port select err\n"); 3280 break; 3281 } 3282 3283 *ppinfo = info; 3284 3285 return p - buf; 3286 } 3287 3288 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 3289 { 3290 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 3291 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 3292 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 3293 return false; 3294 if (rtw89_is_rtl885xb(rtwdev) && 3295 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3296 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3297 return false; 3298 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3299 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 3300 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 3301 return false; 3302 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3303 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 3304 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 3305 return false; 3306 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 3307 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 3308 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 3309 return false; 3310 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 3311 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3312 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3313 return false; 3314 3315 return true; 3316 } 3317 3318 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 3319 char *buf, size_t bufsz, u32 sel) 3320 { 3321 const struct rtw89_mac_dbg_port_info *info = NULL; 3322 char *p = buf, *end = buf + bufsz; 3323 u32 val32; 3324 u16 val16; 3325 u8 val8; 3326 u32 i; 3327 3328 p += rtw89_debug_mac_dbg_port_sel(rtwdev, p, end - p, sel, &info); 3329 3330 if (!info) { 3331 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 3332 goto out; 3333 } 3334 3335 #define case_DBG_SEL(__sel) \ 3336 case RTW89_DBG_PORT_SEL_##__sel: \ 3337 p += scnprintf(p, end - p, "Dump debug port " #__sel ":\n"); \ 3338 break 3339 3340 switch (sel) { 3341 case_DBG_SEL(PTCL_C0); 3342 case_DBG_SEL(PTCL_C1); 3343 case_DBG_SEL(SCH_C0); 3344 case_DBG_SEL(SCH_C1); 3345 case_DBG_SEL(TMAC_C0); 3346 case_DBG_SEL(TMAC_C1); 3347 case_DBG_SEL(RMAC_C0); 3348 case_DBG_SEL(RMAC_C1); 3349 case_DBG_SEL(RMACST_C0); 3350 case_DBG_SEL(RMACST_C1); 3351 case_DBG_SEL(TRXPTCL_C0); 3352 case_DBG_SEL(TRXPTCL_C1); 3353 case_DBG_SEL(TX_INFOL_C0); 3354 case_DBG_SEL(TX_INFOH_C0); 3355 case_DBG_SEL(TX_INFOL_C1); 3356 case_DBG_SEL(TX_INFOH_C1); 3357 case_DBG_SEL(TXTF_INFOL_C0); 3358 case_DBG_SEL(TXTF_INFOH_C0); 3359 case_DBG_SEL(TXTF_INFOL_C1); 3360 case_DBG_SEL(TXTF_INFOH_C1); 3361 case_DBG_SEL(WDE_BUFMGN_FREEPG); 3362 case_DBG_SEL(WDE_BUFMGN_QUOTA); 3363 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 3364 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 3365 case_DBG_SEL(WDE_QUEMGN_PREPKT); 3366 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 3367 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 3368 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 3369 case_DBG_SEL(PLE_BUFMGN_FREEPG); 3370 case_DBG_SEL(PLE_BUFMGN_QUOTA); 3371 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 3372 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 3373 case_DBG_SEL(PLE_QUEMGN_PREPKT); 3374 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 3375 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 3376 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 3377 case_DBG_SEL(PKTINFO); 3378 case_DBG_SEL(DSPT_HDT_TX0); 3379 case_DBG_SEL(DSPT_HDT_TX1); 3380 case_DBG_SEL(DSPT_HDT_TX2); 3381 case_DBG_SEL(DSPT_HDT_TX3); 3382 case_DBG_SEL(DSPT_HDT_TX4); 3383 case_DBG_SEL(DSPT_HDT_TX5); 3384 case_DBG_SEL(DSPT_HDT_TX6); 3385 case_DBG_SEL(DSPT_HDT_TX7); 3386 case_DBG_SEL(DSPT_HDT_TX8); 3387 case_DBG_SEL(DSPT_HDT_TX9); 3388 case_DBG_SEL(DSPT_HDT_TXA); 3389 case_DBG_SEL(DSPT_HDT_TXB); 3390 case_DBG_SEL(DSPT_HDT_TXC); 3391 case_DBG_SEL(DSPT_HDT_TXD); 3392 case_DBG_SEL(DSPT_HDT_TXE); 3393 case_DBG_SEL(DSPT_HDT_TXF); 3394 case_DBG_SEL(DSPT_CDT_TX0); 3395 case_DBG_SEL(DSPT_CDT_TX1); 3396 case_DBG_SEL(DSPT_CDT_TX3); 3397 case_DBG_SEL(DSPT_CDT_TX4); 3398 case_DBG_SEL(DSPT_CDT_TX5); 3399 case_DBG_SEL(DSPT_CDT_TX6); 3400 case_DBG_SEL(DSPT_CDT_TX7); 3401 case_DBG_SEL(DSPT_CDT_TX8); 3402 case_DBG_SEL(DSPT_CDT_TX9); 3403 case_DBG_SEL(DSPT_CDT_TXA); 3404 case_DBG_SEL(DSPT_CDT_TXB); 3405 case_DBG_SEL(DSPT_CDT_TXC); 3406 case_DBG_SEL(DSPT_HDT_RX0); 3407 case_DBG_SEL(DSPT_HDT_RX1); 3408 case_DBG_SEL(DSPT_HDT_RX2); 3409 case_DBG_SEL(DSPT_HDT_RX3); 3410 case_DBG_SEL(DSPT_HDT_RX4); 3411 case_DBG_SEL(DSPT_HDT_RX5); 3412 case_DBG_SEL(DSPT_CDT_RX_P0); 3413 case_DBG_SEL(DSPT_CDT_RX_P0_0); 3414 case_DBG_SEL(DSPT_CDT_RX_P0_1); 3415 case_DBG_SEL(DSPT_CDT_RX_P0_2); 3416 case_DBG_SEL(DSPT_CDT_RX_P1); 3417 case_DBG_SEL(DSPT_STF_CTRL); 3418 case_DBG_SEL(DSPT_ADDR_CTRL); 3419 case_DBG_SEL(DSPT_WDE_INTF); 3420 case_DBG_SEL(DSPT_PLE_INTF); 3421 case_DBG_SEL(DSPT_FLOW_CTRL); 3422 case_DBG_SEL(PCIE_TXDMA); 3423 case_DBG_SEL(PCIE_RXDMA); 3424 case_DBG_SEL(PCIE_CVT); 3425 case_DBG_SEL(PCIE_CXPL); 3426 case_DBG_SEL(PCIE_IO); 3427 case_DBG_SEL(PCIE_MISC); 3428 case_DBG_SEL(PCIE_MISC2); 3429 } 3430 3431 #undef case_DBG_SEL 3432 3433 p += scnprintf(p, end - p, "Sel addr = 0x%X\n", info->sel_addr); 3434 p += scnprintf(p, end - p, "Read addr = 0x%X\n", info->rd_addr); 3435 3436 for (i = info->srt; i <= info->end; i++) { 3437 switch (info->sel_byte) { 3438 case 1: 3439 default: 3440 rtw89_write8_mask(rtwdev, info->sel_addr, 3441 info->sel_msk, i); 3442 p += scnprintf(p, end - p, "0x%02X: ", i); 3443 break; 3444 case 2: 3445 rtw89_write16_mask(rtwdev, info->sel_addr, 3446 info->sel_msk, i); 3447 p += scnprintf(p, end - p, "0x%04X: ", i); 3448 break; 3449 case 4: 3450 rtw89_write32_mask(rtwdev, info->sel_addr, 3451 info->sel_msk, i); 3452 p += scnprintf(p, end - p, "0x%04X: ", i); 3453 break; 3454 } 3455 3456 udelay(10); 3457 3458 switch (info->rd_byte) { 3459 case 1: 3460 default: 3461 val8 = rtw89_read8_mask(rtwdev, 3462 info->rd_addr, info->rd_msk); 3463 p += scnprintf(p, end - p, "0x%02X\n", val8); 3464 break; 3465 case 2: 3466 val16 = rtw89_read16_mask(rtwdev, 3467 info->rd_addr, info->rd_msk); 3468 p += scnprintf(p, end - p, "0x%04X\n", val16); 3469 break; 3470 case 4: 3471 val32 = rtw89_read32_mask(rtwdev, 3472 info->rd_addr, info->rd_msk); 3473 p += scnprintf(p, end - p, "0x%08X\n", val32); 3474 break; 3475 } 3476 } 3477 3478 out: 3479 return p - buf; 3480 } 3481 3482 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 3483 char *buf, size_t bufsz) 3484 { 3485 char *p = buf, *end = buf + bufsz; 3486 ssize_t n; 3487 u32 sel; 3488 3489 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 3490 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 3491 if (!is_dbg_port_valid(rtwdev, sel)) 3492 continue; 3493 n = rtw89_debug_mac_dbg_port_dump(rtwdev, p, end - p, sel); 3494 if (n < 0) { 3495 rtw89_err(rtwdev, 3496 "failed to dump debug port %d\n", sel); 3497 break; 3498 } 3499 p += n; 3500 } 3501 3502 return p - buf; 3503 } 3504 3505 static ssize_t 3506 rtw89_debug_priv_mac_dbg_port_dump_get(struct rtw89_dev *rtwdev, 3507 struct rtw89_debugfs_priv *debugfs_priv, 3508 char *buf, size_t bufsz) 3509 { 3510 char *p = buf, *end = buf + bufsz; 3511 3512 if (debugfs_priv->dbgpkg_en.ss_dbg) 3513 p += rtw89_debug_mac_dump_ss_dbg(rtwdev, p, end - p); 3514 if (debugfs_priv->dbgpkg_en.dle_dbg) 3515 p += rtw89_debug_mac_dump_dle_dbg(rtwdev, p, end - p); 3516 if (debugfs_priv->dbgpkg_en.dmac_dbg) 3517 p += rtw89_debug_mac_dump_dmac_dbg(rtwdev, p, end - p); 3518 if (debugfs_priv->dbgpkg_en.cmac_dbg) 3519 p += rtw89_debug_mac_dump_cmac_dbg(rtwdev, p, end - p); 3520 if (debugfs_priv->dbgpkg_en.dbg_port) 3521 p += rtw89_debug_mac_dump_dbg_port(rtwdev, p, end - p); 3522 3523 return p - buf; 3524 }; 3525 3526 static u8 *rtw89_hex2bin(struct rtw89_dev *rtwdev, const char *buf, size_t count) 3527 { 3528 u8 *bin; 3529 int num; 3530 int err = 0; 3531 3532 num = count / 2; 3533 bin = kmalloc(num, GFP_KERNEL); 3534 if (!bin) { 3535 err = -EFAULT; 3536 goto out; 3537 } 3538 3539 if (hex2bin(bin, buf, num)) { 3540 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 3541 kfree(bin); 3542 err = -EINVAL; 3543 } 3544 3545 out: 3546 return err ? ERR_PTR(err) : bin; 3547 } 3548 3549 static ssize_t rtw89_debug_priv_send_h2c_set(struct rtw89_dev *rtwdev, 3550 struct rtw89_debugfs_priv *debugfs_priv, 3551 const char *buf, size_t count) 3552 { 3553 u8 *h2c; 3554 int ret; 3555 u16 h2c_len = count / 2; 3556 3557 h2c = rtw89_hex2bin(rtwdev, buf, count); 3558 if (IS_ERR(h2c)) 3559 return -EFAULT; 3560 3561 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3562 3563 kfree(h2c); 3564 3565 return ret ? ret : count; 3566 } 3567 3568 static ssize_t 3569 rtw89_debug_priv_early_h2c_get(struct rtw89_dev *rtwdev, 3570 struct rtw89_debugfs_priv *debugfs_priv, 3571 char *buf, size_t bufsz) 3572 { 3573 struct rtw89_early_h2c *early_h2c; 3574 char *p = buf, *end = buf + bufsz; 3575 int seq = 0; 3576 3577 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3578 3579 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3580 p += scnprintf(p, end - p, "%d: %*ph\n", ++seq, 3581 early_h2c->h2c_len, early_h2c->h2c); 3582 3583 return p - buf; 3584 } 3585 3586 static ssize_t 3587 rtw89_debug_priv_early_h2c_set(struct rtw89_dev *rtwdev, 3588 struct rtw89_debugfs_priv *debugfs_priv, 3589 const char *buf, size_t count) 3590 { 3591 struct rtw89_early_h2c *early_h2c; 3592 u8 *h2c; 3593 u16 h2c_len = count / 2; 3594 3595 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3596 3597 h2c = rtw89_hex2bin(rtwdev, buf, count); 3598 if (IS_ERR(h2c)) 3599 return -EFAULT; 3600 3601 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3602 kfree(h2c); 3603 rtw89_fw_free_all_early_h2c(rtwdev); 3604 goto out; 3605 } 3606 3607 early_h2c = kmalloc_obj(*early_h2c); 3608 if (!early_h2c) { 3609 kfree(h2c); 3610 return -EFAULT; 3611 } 3612 3613 early_h2c->h2c = h2c; 3614 early_h2c->h2c_len = h2c_len; 3615 3616 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3617 3618 out: 3619 return count; 3620 } 3621 3622 static int rtw89_dbg_trigger_l1_error_ax(struct rtw89_dev *rtwdev) 3623 { 3624 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3625 struct rtw89_cpuio_ctrl ctrl_para = {}; 3626 u16 pkt_id; 3627 int ret; 3628 3629 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3630 if (ret) 3631 return ret; 3632 3633 /* intentionally, enqueue two pkt, but has only one pkt id */ 3634 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3635 ctrl_para.start_pktid = pkt_id; 3636 ctrl_para.end_pktid = pkt_id; 3637 ctrl_para.pkt_num = 1; /* start from 0 */ 3638 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3639 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3640 3641 if (mac->set_cpuio(rtwdev, &ctrl_para, true)) 3642 return -EFAULT; 3643 3644 return 0; 3645 } 3646 3647 static int rtw89_dbg_trigger_l1_error_be(struct rtw89_dev *rtwdev) 3648 { 3649 int ret; 3650 3651 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3652 if (ret) 3653 return ret; 3654 3655 rtw89_write32_set(rtwdev, R_BE_FW_TRIGGER_IDCT_ISR, 3656 B_BE_DMAC_FW_TRIG_IDCT | B_BE_DMAC_FW_ERR_IDCT_IMR); 3657 3658 return 0; 3659 } 3660 3661 static int rtw89_dbg_trigger_l1_error_by_halt_h2c(struct rtw89_dev *rtwdev) 3662 { 3663 if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3664 return -EBUSY; 3665 3666 return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RESET_FORCE); 3667 } 3668 3669 static int rtw89_dbg_trigger_l1_error(struct rtw89_dev *rtwdev) 3670 { 3671 const struct rtw89_chip_info *chip = rtwdev->chip; 3672 int (*sim_l1)(struct rtw89_dev *rtwdev); 3673 3674 switch (chip->chip_gen) { 3675 case RTW89_CHIP_AX: 3676 sim_l1 = rtw89_dbg_trigger_l1_error_ax; 3677 break; 3678 case RTW89_CHIP_BE: 3679 sim_l1 = rtw89_dbg_trigger_l1_error_be; 3680 break; 3681 default: 3682 return -EOPNOTSUPP; 3683 } 3684 3685 if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw)) 3686 return rtw89_dbg_trigger_l1_error_by_halt_h2c(rtwdev); 3687 3688 rtw89_leave_ps_mode(rtwdev); 3689 3690 return sim_l1(rtwdev); 3691 } 3692 3693 static int rtw89_dbg_trigger_l0_error_ax(struct rtw89_dev *rtwdev) 3694 { 3695 u16 val16; 3696 u8 val8; 3697 int ret; 3698 3699 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3700 if (ret) 3701 return ret; 3702 3703 val8 = rtw89_read8(rtwdev, R_AX_CMAC_FUNC_EN); 3704 rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8 & ~B_AX_TMAC_EN); 3705 mdelay(1); 3706 rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8); 3707 3708 val16 = rtw89_read16(rtwdev, R_AX_PTCL_IMR0); 3709 rtw89_write16(rtwdev, R_AX_PTCL_IMR0, val16 | B_AX_F2PCMD_EMPTY_ERR_INT_EN); 3710 rtw89_write16(rtwdev, R_AX_PTCL_IMR0, val16); 3711 3712 return 0; 3713 } 3714 3715 static int rtw89_dbg_trigger_l0_error_be(struct rtw89_dev *rtwdev) 3716 { 3717 int ret; 3718 3719 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3720 if (ret) 3721 return ret; 3722 3723 rtw89_write32_set(rtwdev, R_BE_CMAC_FW_TRIGGER_IDCT_ISR, 3724 B_BE_CMAC_FW_TRIG_IDCT | B_BE_CMAC_FW_ERR_IDCT_IMR); 3725 3726 return 0; 3727 } 3728 3729 static int rtw89_dbg_trigger_l0_error_by_halt_h2c(struct rtw89_dev *rtwdev) 3730 { 3731 if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3732 return -EBUSY; 3733 3734 return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L0_RESET_FORCE); 3735 } 3736 3737 static int rtw89_dbg_trigger_l0_error(struct rtw89_dev *rtwdev) 3738 { 3739 const struct rtw89_chip_info *chip = rtwdev->chip; 3740 int (*sim_l0)(struct rtw89_dev *rtwdev); 3741 3742 switch (chip->chip_gen) { 3743 case RTW89_CHIP_AX: 3744 sim_l0 = rtw89_dbg_trigger_l0_error_ax; 3745 break; 3746 case RTW89_CHIP_BE: 3747 sim_l0 = rtw89_dbg_trigger_l0_error_be; 3748 break; 3749 default: 3750 return -EOPNOTSUPP; 3751 } 3752 3753 if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw)) 3754 return rtw89_dbg_trigger_l0_error_by_halt_h2c(rtwdev); 3755 3756 rtw89_leave_ps_mode(rtwdev); 3757 3758 return sim_l0(rtwdev); 3759 } 3760 3761 static ssize_t 3762 rtw89_debug_priv_fw_crash_get(struct rtw89_dev *rtwdev, 3763 struct rtw89_debugfs_priv *debugfs_priv, 3764 char *buf, size_t bufsz) 3765 { 3766 char *p = buf, *end = buf + bufsz; 3767 3768 p += scnprintf(p, end - p, "%d\n", 3769 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3770 return p - buf; 3771 } 3772 3773 enum rtw89_dbg_crash_simulation_type { 3774 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3775 RTW89_DBG_SIM_L1_ERROR = 2, 3776 RTW89_DBG_SIM_L0_ERROR = 3, 3777 }; 3778 3779 static ssize_t 3780 rtw89_debug_priv_fw_crash_set(struct rtw89_dev *rtwdev, 3781 struct rtw89_debugfs_priv *debugfs_priv, 3782 const char *buf, size_t count) 3783 { 3784 int (*sim)(struct rtw89_dev *rtwdev); 3785 bool announce = true; 3786 u8 crash_type; 3787 int ret; 3788 3789 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3790 3791 ret = kstrtou8(buf, 0, &crash_type); 3792 if (ret) 3793 return -EINVAL; 3794 3795 switch (crash_type) { 3796 case RTW89_DBG_SIM_CPU_EXCEPTION: 3797 if (!RTW89_CHK_FW_FEATURE_GROUP(CRASH_TRIGGER, &rtwdev->fw)) 3798 return -EOPNOTSUPP; 3799 sim = rtw89_fw_h2c_trigger_cpu_exception; 3800 break; 3801 case RTW89_DBG_SIM_L1_ERROR: 3802 sim = rtw89_dbg_trigger_l1_error; 3803 break; 3804 case RTW89_DBG_SIM_L0_ERROR: 3805 sim = rtw89_dbg_trigger_l0_error; 3806 3807 /* Driver SER flow won't get involved; only FW will. */ 3808 announce = false; 3809 break; 3810 default: 3811 return -EINVAL; 3812 } 3813 3814 if (announce) 3815 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3816 3817 ret = sim(rtwdev); 3818 3819 if (ret) 3820 return ret; 3821 3822 return count; 3823 } 3824 3825 struct rtw89_dbg_ser_counters { 3826 unsigned int l0_sim; 3827 unsigned int l0; 3828 unsigned int l1; 3829 unsigned int l0_to_l1; 3830 }; 3831 3832 static void rtw89_dbg_get_ser_counters_ax(struct rtw89_dev *rtwdev, 3833 struct rtw89_dbg_ser_counters *cnt) 3834 { 3835 const u32 val = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 3836 3837 cnt->l0 = u32_get_bits(val, B_AX_SER_L0_COUNTER_MASK); 3838 cnt->l1 = u32_get_bits(val, B_AX_SER_L1_COUNTER_MASK); 3839 cnt->l0_to_l1 = u32_get_bits(val, B_AX_L0_TO_L1_EVENT_MASK); 3840 } 3841 3842 static void rtw89_dbg_get_ser_counters_be(struct rtw89_dev *rtwdev, 3843 struct rtw89_dbg_ser_counters *cnt) 3844 { 3845 const u32 val = rtw89_read32(rtwdev, R_BE_SER_DBG_INFO); 3846 3847 cnt->l0_sim = rtw89_read8(rtwdev, R_BE_SER_L0_DBG_CNT1 + 3); 3848 cnt->l0 = u32_get_bits(val, B_BE_SER_L0_COUNTER_MASK); 3849 cnt->l1 = u32_get_bits(val, B_BE_SER_L1_COUNTER_MASK); 3850 cnt->l0_to_l1 = u32_get_bits(val, B_BE_SER_L0_PROMOTE_L1_EVENT_MASK); 3851 } 3852 3853 static ssize_t rtw89_debug_priv_ser_counters_get(struct rtw89_dev *rtwdev, 3854 struct rtw89_debugfs_priv *debugfs_priv, 3855 char *buf, size_t bufsz) 3856 { 3857 const struct rtw89_ser_count *sw_cnt = &rtwdev->ser.sw_cnt; 3858 const struct rtw89_chip_info *chip = rtwdev->chip; 3859 struct rtw89_dbg_ser_counters cnt = {}; 3860 char *p = buf, *end = buf + bufsz; 3861 3862 rtw89_leave_ps_mode(rtwdev); 3863 3864 switch (chip->chip_gen) { 3865 case RTW89_CHIP_AX: 3866 rtw89_dbg_get_ser_counters_ax(rtwdev, &cnt); 3867 break; 3868 case RTW89_CHIP_BE: 3869 rtw89_dbg_get_ser_counters_be(rtwdev, &cnt); 3870 break; 3871 default: 3872 return -EOPNOTSUPP; 3873 } 3874 3875 p += scnprintf(p, end - p, "SER L1 SW Count: %u\n", sw_cnt->l1); 3876 p += scnprintf(p, end - p, "SER L2 SW Count: %u\n", sw_cnt->l2); 3877 3878 /* Some chipsets don't have dedicated cnt for SER simulation. */ 3879 p += scnprintf(p, end - p, "---\n"); 3880 p += scnprintf(p, end - p, "SER L0 Simulation Count: %d\n", cnt.l0_sim); 3881 3882 /* Some chipsets won't record SER simulation in HW cnt. */ 3883 p += scnprintf(p, end - p, "---\n"); 3884 p += scnprintf(p, end - p, "SER L0 Count: %d\n", cnt.l0); 3885 p += scnprintf(p, end - p, "SER L1 Count: %d\n", cnt.l1); 3886 p += scnprintf(p, end - p, "SER L0 promote event: %d\n", cnt.l0_to_l1); 3887 3888 return p - buf; 3889 } 3890 3891 static ssize_t rtw89_debug_priv_btc_info_get(struct rtw89_dev *rtwdev, 3892 struct rtw89_debugfs_priv *debugfs_priv, 3893 char *buf, size_t bufsz) 3894 { 3895 return rtw89_btc_dump_info(rtwdev, buf, bufsz); 3896 } 3897 3898 static ssize_t rtw89_debug_priv_btc_manual_set(struct rtw89_dev *rtwdev, 3899 struct rtw89_debugfs_priv *debugfs_priv, 3900 const char *buf, size_t count) 3901 { 3902 struct rtw89_btc *btc = &rtwdev->btc; 3903 const struct rtw89_btc_ver *ver = btc->ver; 3904 int ret; 3905 3906 ret = kstrtobool(buf, &btc->manual_ctrl); 3907 if (ret) 3908 return ret; 3909 3910 if (ver->fcxctrl == 7) 3911 btc->ctrl.ctrl_v7.manual = btc->manual_ctrl; 3912 else 3913 btc->ctrl.ctrl.manual = btc->manual_ctrl; 3914 3915 return count; 3916 } 3917 3918 static ssize_t rtw89_debug_priv_fw_log_manual_set(struct rtw89_dev *rtwdev, 3919 struct rtw89_debugfs_priv *debugfs_priv, 3920 const char *buf, size_t count) 3921 { 3922 struct rtw89_fw_log *log = &rtwdev->fw.log; 3923 bool fw_log_manual; 3924 3925 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3926 3927 if (kstrtobool(buf, &fw_log_manual)) 3928 goto out; 3929 3930 log->enable = fw_log_manual; 3931 if (log->enable) 3932 rtw89_fw_log_prepare(rtwdev); 3933 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3934 out: 3935 return count; 3936 } 3937 3938 static int rtw89_sta_link_info_get_iter(struct rtw89_dev *rtwdev, 3939 char *buf, size_t bufsz, 3940 struct rtw89_sta_link *rtwsta_link) 3941 { 3942 static const char * const he_gi_str[] = { 3943 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3944 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3945 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3946 }; 3947 static const char * const eht_gi_str[] = { 3948 [NL80211_RATE_INFO_EHT_GI_0_8] = "0.8", 3949 [NL80211_RATE_INFO_EHT_GI_1_6] = "1.6", 3950 [NL80211_RATE_INFO_EHT_GI_3_2] = "3.2", 3951 }; 3952 struct rate_info *rate = &rtwsta_link->ra_report.txrate; 3953 struct ieee80211_rx_status *status = &rtwsta_link->rx_status; 3954 struct rtw89_hal *hal = &rtwdev->hal; 3955 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3956 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3957 struct ieee80211_link_sta *link_sta; 3958 char *p = buf, *end = buf + bufsz; 3959 u8 evm_min, evm_max, evm_1ss; 3960 u16 max_rc_amsdu_len; 3961 u8 rssi; 3962 u8 snr; 3963 int i; 3964 3965 rcu_read_lock(); 3966 3967 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3968 max_rc_amsdu_len = link_sta->agg.max_rc_amsdu_len; 3969 3970 rcu_read_unlock(); 3971 3972 p += scnprintf(p, end - p, "TX rate [%u, %u]: ", rtwsta_link->mac_id, 3973 rtwsta_link->link_id); 3974 3975 if (rate->flags & RATE_INFO_FLAGS_MCS) 3976 p += scnprintf(p, end - p, "HT MCS-%d%s", rate->mcs, 3977 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3978 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3979 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", rate->nss, 3980 rate->mcs, 3981 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3982 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3983 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", rate->nss, 3984 rate->mcs, 3985 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3986 he_gi_str[rate->he_gi] : "N/A"); 3987 else if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) 3988 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", rate->nss, 3989 rate->mcs, 3990 rate->eht_gi < ARRAY_SIZE(eht_gi_str) ? 3991 eht_gi_str[rate->eht_gi] : "N/A"); 3992 else 3993 p += scnprintf(p, end - p, "Legacy %d", rate->legacy); 3994 p += scnprintf(p, end - p, "%s", 3995 rtwsta_link->ra_report.might_fallback_legacy ? " FB_G" : ""); 3996 p += scnprintf(p, end - p, " BW:%u", 3997 rtw89_rate_info_bw_to_mhz(rate->bw)); 3998 p += scnprintf(p, end - p, " (hw_rate=0x%x)", 3999 rtwsta_link->ra_report.hw_rate); 4000 p += scnprintf(p, end - p, " PER:%d", rtwsta_link->ra_report.retry_ratio); 4001 p += scnprintf(p, end - p, " ==> agg_wait=%d (%d)\n", 4002 rtwsta_link->max_agg_wait, 4003 max_rc_amsdu_len); 4004 4005 p += scnprintf(p, end - p, "RX rate [%u, %u]: ", rtwsta_link->mac_id, 4006 rtwsta_link->link_id); 4007 4008 switch (status->encoding) { 4009 case RX_ENC_LEGACY: 4010 p += scnprintf(p, end - p, "Legacy %d", status->rate_idx + 4011 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 4012 break; 4013 case RX_ENC_HT: 4014 p += scnprintf(p, end - p, "HT MCS-%d%s", status->rate_idx, 4015 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 4016 break; 4017 case RX_ENC_VHT: 4018 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", status->nss, 4019 status->rate_idx, 4020 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 4021 break; 4022 case RX_ENC_HE: 4023 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", 4024 status->nss, status->rate_idx, 4025 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 4026 he_gi_str[status->he_gi] : "N/A"); 4027 break; 4028 case RX_ENC_EHT: 4029 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", 4030 status->nss, status->rate_idx, 4031 status->eht.gi < ARRAY_SIZE(eht_gi_str) ? 4032 eht_gi_str[status->eht.gi] : "N/A"); 4033 break; 4034 } 4035 p += scnprintf(p, end - p, " BW:%u", 4036 rtw89_rate_info_bw_to_mhz(status->bw)); 4037 p += scnprintf(p, end - p, " (hw_rate=0x%x)\n", 4038 rtwsta_link->rx_hw_rate); 4039 4040 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi); 4041 p += scnprintf(p, end - p, "RSSI: %d dBm (raw=%d, prev=%d) [", 4042 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, 4043 rtwsta_link->prev_rssi); 4044 for (i = 0; i < ant_num; i++) { 4045 rssi = ewma_rssi_read(&rtwsta_link->rssi[i]); 4046 p += scnprintf(p, end - p, "%d%s%s", 4047 RTW89_RSSI_RAW_TO_DBM(rssi), 4048 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 4049 i + 1 == ant_num ? "" : ", "); 4050 } 4051 p += scnprintf(p, end - p, "]\n"); 4052 4053 evm_1ss = ewma_evm_read(&rtwsta_link->evm_1ss); 4054 p += scnprintf(p, end - p, "EVM: [%2u.%02u, ", evm_1ss >> 2, 4055 (evm_1ss & 0x3) * 25); 4056 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 4057 evm_min = ewma_evm_read(&rtwsta_link->evm_min[i]); 4058 evm_max = ewma_evm_read(&rtwsta_link->evm_max[i]); 4059 4060 p += scnprintf(p, end - p, "%s(%2u.%02u, %2u.%02u)", 4061 i == 0 ? "" : " ", 4062 evm_min >> 2, (evm_min & 0x3) * 25, 4063 evm_max >> 2, (evm_max & 0x3) * 25); 4064 } 4065 p += scnprintf(p, end - p, "]\t"); 4066 4067 snr = ewma_snr_read(&rtwsta_link->avg_snr); 4068 p += scnprintf(p, end - p, "SNR: %u\n", snr); 4069 4070 return p - buf; 4071 } 4072 4073 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 4074 { 4075 struct rtw89_debugfs_iter_data *iter_data = 4076 (struct rtw89_debugfs_iter_data *)data; 4077 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4078 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4079 struct rtw89_sta_link *rtwsta_link; 4080 size_t bufsz = iter_data->bufsz; 4081 char *buf = iter_data->buf; 4082 char *p = buf, *end = buf + bufsz; 4083 unsigned int link_id; 4084 4085 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 4086 p += rtw89_sta_link_info_get_iter(rtwdev, p, end - p, rtwsta_link); 4087 4088 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4089 } 4090 4091 static int 4092 rtw89_debug_append_rate(char *buf, size_t bufsz, const u32 *rate_cnt, 4093 int first_rate, int len) 4094 { 4095 char *p = buf, *end = buf + bufsz; 4096 int i; 4097 4098 for (i = 0; i < len; i++) 4099 p += scnprintf(p, end - p, "%s%u", i == 0 ? "" : ", ", 4100 rate_cnt[first_rate + i]); 4101 4102 return p - buf; 4103 } 4104 4105 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate} 4106 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate} 4107 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate} 4108 4109 static const struct rtw89_rx_rate_cnt_info { 4110 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM]; 4111 int len; 4112 int ext; 4113 const char *rate_mode; 4114 } rtw89_rx_rate_cnt_infos[] = { 4115 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"}, 4116 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"}, 4117 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"}, 4118 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"}, 4119 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"}, 4120 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"}, 4121 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"}, 4122 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"}, 4123 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"}, 4124 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"}, 4125 }; 4126 4127 static const struct rtw89_tx_rate_cnt_info { 4128 int first_rate; 4129 int len; 4130 const char *rate_mode; 4131 } rtw89_tx_rate_cnt_infos[] = { 4132 {0, 4, "Legacy:"}, 4133 {4, 8, "OFDM:"}, 4134 {12, 14, "MCS 1SS:"}, 4135 {26, 14, "MCS 2SS:"}, 4136 }; 4137 4138 static int rtw89_get_rx_pkt_stat(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb, 4139 char *buf, size_t bufsz) 4140 { 4141 struct rtw89_pkt_stat *pkt_stat = &bb->last_pkt_stat; 4142 const struct rtw89_chip_info *chip = rtwdev->chip; 4143 const struct rtw89_rx_rate_cnt_info *info; 4144 u8 rssi = ewma_rssi_read(&bb->bcn_rssi); 4145 char *p = buf, *end = buf + bufsz; 4146 enum rtw89_hw_rate first_rate; 4147 int i; 4148 4149 p += scnprintf(p, end - p, "Beacon: %u (%d dBm)\n", 4150 pkt_stat->beacon_nr, 4151 RTW89_RSSI_RAW_TO_DBM(rssi)); 4152 4153 p += scnprintf(p, end - p, "RX count:\n"); 4154 4155 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 4156 info = &rtw89_rx_rate_cnt_infos[i]; 4157 first_rate = info->first_rate[chip->chip_gen]; 4158 if (first_rate >= RTW89_HW_RATE_NR) 4159 continue; 4160 4161 p += scnprintf(p, end - p, "%10s [", info->rate_mode); 4162 p += rtw89_debug_append_rate(p, end - p, pkt_stat->rx_rate_cnt, 4163 first_rate, info->len); 4164 if (info->ext) { 4165 p += scnprintf(p, end - p, "]["); 4166 p += rtw89_debug_append_rate(p, end - p, pkt_stat->rx_rate_cnt, 4167 first_rate + info->len, 4168 info->ext); 4169 } 4170 p += scnprintf(p, end - p, "]\n"); 4171 } 4172 4173 return p - buf; 4174 } 4175 4176 static ssize_t rtw89_debug_priv_phy_info_get(struct rtw89_dev *rtwdev, 4177 struct rtw89_debugfs_priv *debugfs_priv, 4178 char *buf, size_t bufsz) 4179 { 4180 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4181 struct rtw89_debugfs_iter_data iter_data; 4182 struct rtw89_hal *hal = &rtwdev->hal; 4183 char *p = buf, *end = buf + bufsz; 4184 struct rtw89_bb_ctx *bb; 4185 4186 p += scnprintf(p, end - p, "TP TX: %u [%u] Mbps (lv: %d", 4187 stats->tx_throughput, stats->tx_throughput_raw, 4188 stats->tx_tfc_lv); 4189 if (hal->thermal_prot_lv) 4190 p += scnprintf(p, end - p, ", duty: %d%%", 4191 100 - hal->thermal_prot_lv * RTW89_THERMAL_PROT_STEP); 4192 p += scnprintf(p, end - p, "), RX: %u [%u] Mbps (lv: %d)\n", 4193 stats->rx_throughput, stats->rx_throughput_raw, 4194 stats->rx_tfc_lv); 4195 p += scnprintf(p, end - p, "Avg packet length: TX=%u, RX=%u\n", 4196 stats->tx_avg_len, 4197 stats->rx_avg_len); 4198 p += scnprintf(p, end - p, "TF: %u\n", stats->rx_tf_periodic); 4199 4200 rtw89_for_each_active_bb(rtwdev, bb) { 4201 p += scnprintf(p, end - p, "\n[PHY %u]\n", bb->phy_idx); 4202 p += rtw89_get_rx_pkt_stat(rtwdev, bb, p, end - p); 4203 } 4204 p += scnprintf(p, end - p, "\n"); 4205 4206 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4207 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, &iter_data); 4208 p += iter_data.written_sz; 4209 4210 return p - buf; 4211 } 4212 4213 static const char *const lcck[] = {"L_CCK"}; 4214 static const char *const scck[] = {"S_CCK"}; 4215 static const char *const ht_gf[] = {"HT_GF"}; 4216 static const char *const vht_mu[] = {"VHT_MU"}; 4217 static const char *const he_er_su[] = {"HE_ER_SU"}; 4218 static const char *const eht_tb[] = {"EHT_TB"}; 4219 static const char *const legacy_ax[] = {"LEGACY"}; 4220 static const char *const ht_ax[] = {"HT"}; 4221 static const char *const vht_su_ax[] = {"VHT_SU"}; 4222 static const char *const he_su_ax[] = {"HE_SU"}; 4223 static const char *const he_mu_ax[] = {"HE_MU"}; 4224 static const char *const he_tb_ax[] = {"HE_TB"}; 4225 static const char *const legacy_be[] = { 4226 "LEGACY", "LEGACY_DUP", "LEGACY_DUP_PUNC" 4227 }; 4228 4229 static const char *const ht_be[] = { 4230 "HT_MF", "HT_SND_NDP" 4231 }; 4232 4233 static const char *const vht_su_be[] = { 4234 "VHT_SU", "VHT_SND_NDP" 4235 }; 4236 4237 static const char *const he_su_be[] = { 4238 "HE_SU", "HE_SND_NDP", "HE_SND_NDP_PUNC", "HE_RANG_NDP" 4239 }; 4240 4241 static const char *const he_mu_be[] = { 4242 "HE_MU_RU", "HE_MU_MU", "HE_MU_RU_PUNC" 4243 }; 4244 4245 static const char *const he_tb_be[] = { 4246 "HE_TB", "HE_TB_FB_NDP", "HE_MU_RANG_NDP" 4247 }; 4248 4249 static const char *const eht_mu[] = { 4250 "EHT_MU_SU", "EHT_MU_ER", "EHT_MU_RU", "EHT_MU_MU", 4251 "EHT_MU_SND_NDP", "EHT_MU_SU_PUNC", "EHT_MU_RU_PUNC", 4252 "EHT_SND_NDP_PUNC", "EHT_MU_MU_PUNC" 4253 }; 4254 4255 #define PPDU_SAME(ppdu) \ 4256 {.str = {ppdu, ppdu}, \ 4257 .cnt = {ARRAY_SIZE(ppdu), ARRAY_SIZE(ppdu)} } 4258 #define PPDU_VARIANT(ppdu) \ 4259 {.str = {ppdu##_ax, ppdu##_be}, \ 4260 .cnt = {ARRAY_SIZE(ppdu##_ax), ARRAY_SIZE(ppdu##_be)} } 4261 #define PPDU_GEV1(ppdu) \ 4262 {.str = {NULL, ppdu}, \ 4263 .cnt = {0, ARRAY_SIZE(ppdu)} } 4264 4265 static const struct rtw89_ppdu_info { 4266 const char *const *str[RTW89_CHIP_GEN_NUM]; 4267 u8 cnt[RTW89_CHIP_GEN_NUM]; 4268 } rtw89_ppdu_infos[] = { 4269 [0] = PPDU_SAME(lcck), 4270 [1] = PPDU_SAME(scck), 4271 [2] = PPDU_VARIANT(legacy), 4272 [3] = PPDU_VARIANT(ht), 4273 [4] = PPDU_SAME(ht_gf), 4274 [5] = PPDU_VARIANT(vht_su), 4275 [6] = PPDU_SAME(vht_mu), 4276 [7] = PPDU_VARIANT(he_su), 4277 [8] = PPDU_SAME(he_er_su), 4278 [9] = PPDU_VARIANT(he_mu), 4279 [10] = PPDU_VARIANT(he_tb), 4280 [11] = PPDU_GEV1(eht_mu), 4281 [12] = PPDU_GEV1(eht_tb), 4282 }; 4283 4284 #define TXCMD_SAME(txcmd) {txcmd, txcmd} 4285 #define TXCMD_DIFF(txcmd, txcmd_v1) {txcmd, txcmd_v1} 4286 #define TXCMD_GEV1(txcmd) {"RSVD", txcmd} 4287 4288 static const struct rtw89_txcmd_info { 4289 const char *str[RTW89_CHIP_GEN_NUM]; 4290 } rtw89_txcmd_infos[] = { 4291 [0] = {TXCMD_SAME("DATA")}, 4292 [1] = {TXCMD_SAME("BCN")}, 4293 [2] = {TXCMD_SAME("HT_NDPA")}, 4294 [3] = {TXCMD_SAME("VHT_NDPA")}, 4295 [4] = {TXCMD_SAME("HE_NDPA")}, 4296 [5] = {TXCMD_GEV1("EHT_NDPA")}, 4297 [6] = {TXCMD_GEV1("11MC_FTM")}, 4298 [7] = {TXCMD_GEV1("11MC_FTM_ACK")}, 4299 [8] = {TXCMD_SAME("RTS")}, 4300 [9] = {TXCMD_SAME("CTS2S")}, 4301 [10] = {TXCMD_SAME("CF_END")}, 4302 [11] = {TXCMD_SAME("CMP_BAR")}, 4303 [12] = {TXCMD_SAME("BFRP")}, 4304 [13] = {TXCMD_SAME("NDP")}, 4305 [14] = {TXCMD_SAME("QoS_NULL")}, 4306 [15] = {TXCMD_GEV1("CTS_2_MURTS")}, 4307 [16] = {TXCMD_SAME("ACK")}, 4308 [17] = {TXCMD_SAME("CTS")}, 4309 [18] = {TXCMD_SAME("CMP_BA")}, 4310 [19] = {TXCMD_SAME("MSTA_BA")}, 4311 [20] = {TXCMD_SAME("HT_CSI")}, 4312 [21] = {TXCMD_SAME("VHT_CSI")}, 4313 [22] = {TXCMD_SAME("HE_CSI")}, 4314 [23] = {TXCMD_GEV1("EHT_CSI")}, 4315 [24] = {TXCMD_GEV1("NTB_I2R_NDPA")}, 4316 [25] = {TXCMD_GEV1("NTB_I2R_NDP")}, 4317 [26] = {TXCMD_GEV1("NTB_I2R_LMR")}, 4318 [27] = {TXCMD_GEV1("NTB_I2R_NDP")}, 4319 [28] = {TXCMD_GEV1("NTB_I2R_LMR")}, 4320 [29] = {TXCMD_GEV1("NTB_R2I_RANG_NDPA")}, 4321 [30] = {TXCMD_GEV1("NTB_R2I_NDP")}, 4322 [31] = {TXCMD_DIFF("TB_PPDU", "NTB_R2I_LMR")}, 4323 [32] = {TXCMD_SAME("TRIG_BASIC")}, 4324 [33] = {TXCMD_SAME("TRIG_BFRP")}, 4325 [34] = {TXCMD_SAME("TRIG_MUBAR")}, 4326 [35] = {TXCMD_SAME("TRIG_MURTS")}, 4327 [36] = {TXCMD_SAME("TRIG_BSRP")}, 4328 [37] = {TXCMD_SAME("TRIG_BQRP")}, 4329 [38] = {TXCMD_SAME("TRIG_NFRP")}, 4330 [39] = {TXCMD_GEV1("TRIG_BASIC_DATA")}, 4331 [40] = {TXCMD_GEV1("TRIG_RANG_POLL")}, 4332 [41] = {TXCMD_GEV1("TRIG_RANG_SNR")}, 4333 [42] = {TXCMD_GEV1("TRIG_RANG_LMR")}, 4334 [48] = {TXCMD_DIFF("TRIG_BASIC_DATA", "TRIG_TB_CSI")}, 4335 [49] = {TXCMD_GEV1("TRIG_TB_CBA")}, 4336 [50] = {TXCMD_GEV1("TRIG_TB_MBA")}, 4337 [51] = {TXCMD_GEV1("TRIG_TB_BSR")}, 4338 [52] = {TXCMD_GEV1("TRIG_TB_BQR")}, 4339 [53] = {TXCMD_GEV1("TRIG_TB_ACK")}, 4340 [54] = {TXCMD_GEV1("TRIG_TB_PPDU")}, 4341 [55] = {TXCMD_GEV1("TRIG_TB_I2R_CTS2S")}, 4342 [56] = {TXCMD_GEV1("TRIG_TB_I2R_NDP")}, 4343 [57] = {TXCMD_GEV1("TRIG_TB_I2R_LMR")}, 4344 }; 4345 4346 static const char *rtw89_ppdu_str(struct rtw89_dev *rtwdev, u8 type, u8 subtype) 4347 { 4348 const struct rtw89_chip_info *chip = rtwdev->chip; 4349 const struct rtw89_ppdu_info *ppdu_info; 4350 4351 if (type > ARRAY_SIZE(rtw89_ppdu_infos)) 4352 return "RSVD"; 4353 4354 ppdu_info = &rtw89_ppdu_infos[type]; 4355 4356 if (!ppdu_info->str[chip->chip_gen] || 4357 subtype >= ppdu_info->cnt[chip->chip_gen]) 4358 return "RSVD"; 4359 4360 return ppdu_info->str[chip->chip_gen][subtype]; 4361 } 4362 4363 static const char *rtw89_txcmd_str(struct rtw89_dev *rtwdev, u8 txcmd) 4364 { 4365 const struct rtw89_chip_info *chip = rtwdev->chip; 4366 4367 if (txcmd < ARRAY_SIZE(rtw89_txcmd_infos)) 4368 return rtw89_txcmd_infos[txcmd].str[chip->chip_gen] ?: "RSVD"; 4369 4370 return "RSVD"; 4371 } 4372 4373 static int rtw89_get_bb_stat(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb, 4374 char *buf, size_t bufsz) 4375 { 4376 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4377 struct rtw89_pkt_stat *pkt_stat = &bb->last_pkt_stat; 4378 const struct rtw89_physts_regs *physts = phy->physts; 4379 struct rtw89_pmac_stat_info *pmac = &bb->pmac_stat; 4380 struct rtw89_tx_stat_info *tx_stat = &bb->tx_stat; 4381 const struct rtw89_chip_info *chip = rtwdev->chip; 4382 char *p = buf, *end = buf + bufsz; 4383 u8 factor = chip->txpwr_factor_rf; 4384 u32 reg_nr; 4385 s32 val; 4386 int i; 4387 4388 p += scnprintf(p, end - p, "\n[PHY %u]\n", bb->phy_idx); 4389 4390 p += scnprintf(p, end - p, "== PMAC\n"); 4391 p += scnprintf(p, end - p, 4392 "TX [CCK_TXEN, CCK_TXON, OFDM_TXEN, OFDM_TXON]: [%d, %d, %d, %d]\n", 4393 pmac->cck_mac_txen, pmac->cck_phy_txon, 4394 pmac->ofdm_mac_txen, pmac->ofdm_phy_txon); 4395 p += scnprintf(p, end - p, "CRC [CCK, OFDM, HT, VHT, HE, EHT, ALL, MPDU]\n"); 4396 p += scnprintf(p, end - p, " ok: [%d, %d, %d, %d, %d, %d, %d, %d]\n", 4397 pmac->cnt_cck_crc32_ok, pmac->cnt_ofdm_crc32_ok, 4398 pmac->cnt_ht_crc32_ok, pmac->cnt_vht_crc32_ok, 4399 pmac->cnt_he_crc32_ok, pmac->cnt_eht_crc32_ok, 4400 pmac->cnt_crc32_ok_all, pmac->cnt_ampdu_crc_ok); 4401 p += scnprintf(p, end - p, "err: [%d, %d, %d, %d, %d, %d, %d, %d]\n", 4402 pmac->cnt_cck_crc32_error, pmac->cnt_ofdm_crc32_error, 4403 pmac->cnt_ht_crc32_error, pmac->cnt_vht_crc32_error, 4404 pmac->cnt_he_crc32_error, pmac->cnt_eht_crc32_error, 4405 pmac->cnt_crc32_error_all, pmac->cnt_ampdu_crc_error); 4406 p += scnprintf(p, end - p, "CCA [CCK, OFDM]: [%d, %d]\n", 4407 pmac->cnt_cck_cca, pmac->cnt_ofdm_cca); 4408 p += scnprintf(p, end - p, "FA [CCK, OFDM]: [%d, %d]\n", 4409 pmac->cnt_cck_fail, pmac->cnt_ofdm_fail); 4410 4411 p += scnprintf(p, end - p, "CCA spoofing [CCK, OFDM]: [%d, %d]\n", 4412 pmac->cnt_cck_spoofing, pmac->cnt_ofdm_spoofing); 4413 p += scnprintf(p, end - p, "CCK SFD: %d, SIG_GG: %d\n", 4414 pmac->cnt_sfd_gg, pmac->cnt_sig_gg); 4415 p += scnprintf(p, end - p, 4416 "OFDM Parity: %d, Rate: %d, LSIG_BRK_S: %d, LSIG_BRK_L: %d, SBD: %d\n", 4417 pmac->cnt_parity_fail, pmac->cnt_rate_illegal, 4418 pmac->cnt_lsig_brk_s_th, pmac->cnt_lsig_brk_l_th, 4419 pmac->cnt_sb_search_fail); 4420 p += scnprintf(p, end - p, "AMPDU miss: %d\n\n", pmac->cnt_ampdu_miss); 4421 4422 p += scnprintf(p, end - p, "== TX General\n"); 4423 p += scnprintf(p, end - p, "%s %s\n", 4424 rtw89_ppdu_str(rtwdev, tx_stat->type, tx_stat->subtype), 4425 rtw89_txcmd_str(rtwdev, tx_stat->txcmd)); 4426 4427 p += scnprintf(p, end - p, "BW: %d, TX_SC: %d, TX_PATH_EN: %d, PATH_MAP: 0x%x\n", 4428 20 << tx_stat->bw, tx_stat->txsc, 4429 tx_stat->tx_path_en, tx_stat->path_map); 4430 4431 val = sign_extend32(tx_stat->tmac_txpwr, 8); 4432 p += scnprintf(p, end - p, "TXPWR TMAC: %d,", val >> factor); 4433 4434 reg_nr = min(chip->rf_path_num, ARRAY_SIZE(tx_stat->txpwr)); 4435 for (i = 0; i < reg_nr; i++) { 4436 val = sign_extend32(tx_stat->txpwr[i], 8); 4437 p += scnprintf(p, end - p, " P%d: %d%s", 4438 i, val >> factor, (i < reg_nr - 1) ? "," : ""); 4439 } 4440 p += scnprintf(p, end - p, " dBm\n"); 4441 4442 p += scnprintf(p, end - p, "MCS: %d, STBC: %d\n", 4443 tx_stat->max_mcs, tx_stat->stbc); 4444 4445 p += scnprintf(p, end - p, "Info: ["); 4446 reg_nr = min(physts->tx_info.reg_nr, ARRAY_SIZE(tx_stat->info)); 4447 for (i = 0; i < reg_nr; i++) 4448 p += scnprintf(p, end - p, "0x%08x%s", 4449 tx_stat->info[i], (i < reg_nr - 1) ? ", " : ""); 4450 p += scnprintf(p, end - p, "]\n"); 4451 4452 p += scnprintf(p, end - p, "Common ctrl: ["); 4453 reg_nr = min(physts->tx_common_ctrl.reg_nr, ARRAY_SIZE(tx_stat->common_ctrl)); 4454 for (i = 0; i < reg_nr; i++) 4455 p += scnprintf(p, end - p, "0x%08x%s", 4456 tx_stat->common_ctrl[i], (i < reg_nr - 1) ? ", " : ""); 4457 p += scnprintf(p, end - p, "]\n\n"); 4458 4459 p += scnprintf(p, end - p, "== RX General\n"); 4460 p += scnprintf(p, end - p, 4461 "LDPC: %d, BCC: %d, STBC: %d, SU_NON_BF: %d, SU_BF: %d, MU: %d\n\n", 4462 pkt_stat->rx.ldpc, pkt_stat->rx.bcc, 4463 pkt_stat->rx.stbc, pkt_stat->rx.su_non_bf, 4464 pkt_stat->rx.su_bf, pkt_stat->rx.mu); 4465 4466 p += scnprintf(p, end - p, "== RSSI/RX Rate\n"); 4467 p += rtw89_get_rx_pkt_stat(rtwdev, bb, p, end - p); 4468 4469 return p - buf; 4470 } 4471 4472 static ssize_t 4473 rtw89_debug_priv_bb_info_get(struct rtw89_dev *rtwdev, 4474 struct rtw89_debugfs_priv *debugfs_priv, 4475 char *buf, size_t bufsz) 4476 { 4477 struct rtw89_bb_stat_cfg *bb_stat = &rtwdev->phy_info.bb_stat_cfg; 4478 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4479 const struct rtw89_chip_info *chip = rtwdev->chip; 4480 const struct rtw89_tx_rate_cnt_info *info; 4481 struct rtw89_debugfs_iter_data iter_data; 4482 char *p = buf, *end = buf + bufsz; 4483 struct rtw89_bb_ctx *bb; 4484 int i; 4485 4486 p += scnprintf(p, end - p, "TP TX: %u [%u] Mbps, RX: %u [%u] Mbps\n", 4487 stats->tx_throughput, stats->tx_throughput_raw, 4488 stats->rx_throughput, stats->rx_throughput_raw); 4489 p += scnprintf(p, end - p, "Avg packet length: TX=%u, RX=%u\n", 4490 stats->tx_avg_len, 4491 stats->rx_avg_len); 4492 p += scnprintf(p, end - p, "TF: %u\n", stats->rx_tf_periodic); 4493 4494 if (chip->chip_gen != RTW89_CHIP_AX) { 4495 p += scnprintf(p, end - p, 4496 "TX count [0x%x]:\n", bb_stat->mac_id); 4497 4498 for (i = 0; i < ARRAY_SIZE(rtw89_tx_rate_cnt_infos); i++) { 4499 info = &rtw89_tx_rate_cnt_infos[i]; 4500 4501 p += scnprintf(p, end - p, "%10s [", info->rate_mode); 4502 p += rtw89_debug_append_rate(p, end - p, 4503 rtwdev->phystat.tx_rate_cnt, 4504 info->first_rate, info->len); 4505 p += scnprintf(p, end - p, "]\n"); 4506 } 4507 } 4508 4509 rtw89_for_each_active_bb(rtwdev, bb) 4510 p += rtw89_get_bb_stat(rtwdev, bb, p, end - p); 4511 p += scnprintf(p, end - p, "\n"); 4512 4513 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4514 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, &iter_data); 4515 p += iter_data.written_sz; 4516 4517 return p - buf; 4518 } 4519 4520 static ssize_t 4521 rtw89_debug_priv_bb_info_set(struct rtw89_dev *rtwdev, 4522 struct rtw89_debugfs_priv *debugfs_priv, 4523 const char *buf, size_t count) 4524 { 4525 struct rtw89_bb_stat_cfg *bb_stat = &rtwdev->phy_info.bb_stat_cfg; 4526 int val; 4527 4528 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4529 4530 if (sscanf(buf, "enable %d", &val) == 1) 4531 bb_stat->enable = !!val; 4532 else if (sscanf(buf, "mac_id %x", &val) == 1) 4533 rtw89_fw_h2c_tx_history(rtwdev, val); 4534 else 4535 return -EINVAL; 4536 4537 return count; 4538 } 4539 4540 static int rtw89_dump_addr_cam(struct rtw89_dev *rtwdev, 4541 char *buf, size_t bufsz, 4542 struct rtw89_addr_cam_entry *addr_cam) 4543 { 4544 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4545 const struct rtw89_sec_cam_entry *sec_entry; 4546 char *p = buf, *end = buf + bufsz; 4547 u8 sec_cam_idx; 4548 int i; 4549 4550 p += scnprintf(p, end - p, "\taddr_cam_idx=%u\n", 4551 addr_cam->addr_cam_idx); 4552 p += scnprintf(p, end - p, "\t-> bssid_cam_idx=%u\n", 4553 addr_cam->bssid_cam_idx); 4554 p += scnprintf(p, end - p, "\tsec_cam_bitmap=%*ph\n", 4555 (int)sizeof(addr_cam->sec_cam_map), 4556 addr_cam->sec_cam_map); 4557 for_each_set_bit(i, addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM) { 4558 sec_cam_idx = addr_cam->sec_ent[i]; 4559 sec_entry = cam_info->sec_entries[sec_cam_idx]; 4560 if (!sec_entry) 4561 continue; 4562 p += scnprintf(p, end - p, "\tsec[%d]: sec_cam_idx %u", i, 4563 sec_entry->sec_cam_idx); 4564 if (sec_entry->ext_key) 4565 p += scnprintf(p, end - p, ", %u", 4566 sec_entry->sec_cam_idx + 1); 4567 p += scnprintf(p, end - p, "\n"); 4568 } 4569 4570 return p - buf; 4571 } 4572 4573 __printf(4, 5) 4574 static int rtw89_dump_pkt_offload(char *buf, size_t bufsz, struct list_head *pkt_list, 4575 const char *fmt, ...) 4576 { 4577 char *p = buf, *end = buf + bufsz; 4578 struct rtw89_pktofld_info *info; 4579 struct va_format vaf; 4580 va_list args; 4581 4582 if (list_empty(pkt_list)) 4583 return 0; 4584 4585 va_start(args, fmt); 4586 vaf.va = &args; 4587 vaf.fmt = fmt; 4588 4589 p += scnprintf(p, end - p, "%pV", &vaf); 4590 4591 va_end(args); 4592 4593 list_for_each_entry(info, pkt_list, list) 4594 p += scnprintf(p, end - p, "%d ", info->id); 4595 4596 p += scnprintf(p, end - p, "\n"); 4597 4598 return p - buf; 4599 } 4600 4601 static int rtw89_vif_link_ids_get(struct rtw89_dev *rtwdev, 4602 char *buf, size_t bufsz, u8 *mac, 4603 struct rtw89_vif_link *rtwvif_link, 4604 bool designated) 4605 { 4606 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif_link->bssid_cam; 4607 char *p = buf, *end = buf + bufsz; 4608 4609 p += scnprintf(p, end - p, " [%u] %pM\n", rtwvif_link->mac_id, 4610 rtwvif_link->mac_addr); 4611 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwvif_link->link_id, 4612 designated ? " (*)" : ""); 4613 p += scnprintf(p, end - p, "\tbssid_cam_idx=%u\n", 4614 bssid_cam->bssid_cam_idx); 4615 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwvif_link->addr_cam); 4616 p += rtw89_dump_pkt_offload(p, end - p, &rtwvif_link->general_pkt_list, 4617 "\tpkt_ofld[GENERAL]: "); 4618 4619 return p - buf; 4620 } 4621 4622 static 4623 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 4624 { 4625 struct rtw89_debugfs_iter_data *iter_data = 4626 (struct rtw89_debugfs_iter_data *)data; 4627 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 4628 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 4629 struct rtw89_vif_link *designated_link; 4630 struct rtw89_vif_link *rtwvif_link; 4631 size_t bufsz = iter_data->bufsz; 4632 char *buf = iter_data->buf; 4633 char *p = buf, *end = buf + bufsz; 4634 unsigned int link_id; 4635 4636 designated_link = rtw89_get_designated_link(rtwvif); 4637 4638 p += scnprintf(p, end - p, "VIF %pM\n", rtwvif->mac_addr); 4639 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4640 p += rtw89_vif_link_ids_get(rtwdev, p, end - p, mac, rtwvif_link, 4641 rtwvif_link == designated_link); 4642 4643 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4644 } 4645 4646 static int rtw89_dump_ba_cam(struct rtw89_dev *rtwdev, 4647 char *buf, size_t bufsz, 4648 struct rtw89_sta_link *rtwsta_link) 4649 { 4650 struct rtw89_ba_cam_entry *entry; 4651 char *p = buf, *end = buf + bufsz; 4652 bool first = true; 4653 4654 list_for_each_entry(entry, &rtwsta_link->ba_cam_list, list) { 4655 if (first) { 4656 p += scnprintf(p, end - p, "\tba_cam "); 4657 first = false; 4658 } else { 4659 p += scnprintf(p, end - p, ", "); 4660 } 4661 p += scnprintf(p, end - p, "tid[%u]=%d", entry->tid, 4662 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 4663 } 4664 p += scnprintf(p, end - p, "\n"); 4665 4666 return p - buf; 4667 } 4668 4669 static int rtw89_sta_link_ids_get(struct rtw89_dev *rtwdev, 4670 char *buf, size_t bufsz, 4671 struct rtw89_sta_link *rtwsta_link, 4672 bool designated) 4673 { 4674 struct ieee80211_link_sta *link_sta; 4675 char *p = buf, *end = buf + bufsz; 4676 4677 rcu_read_lock(); 4678 4679 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4680 4681 p += scnprintf(p, end - p, " [%u] %pM\n", rtwsta_link->mac_id, 4682 link_sta->addr); 4683 4684 rcu_read_unlock(); 4685 4686 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwsta_link->link_id, 4687 designated ? " (*)" : ""); 4688 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwsta_link->addr_cam); 4689 p += rtw89_dump_ba_cam(rtwdev, p, end - p, rtwsta_link); 4690 4691 return p - buf; 4692 } 4693 4694 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 4695 { 4696 struct rtw89_debugfs_iter_data *iter_data = 4697 (struct rtw89_debugfs_iter_data *)data; 4698 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4699 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4700 struct rtw89_sta_link *designated_link; 4701 struct rtw89_sta_link *rtwsta_link; 4702 size_t bufsz = iter_data->bufsz; 4703 char *buf = iter_data->buf; 4704 char *p = buf, *end = buf + bufsz; 4705 unsigned int link_id; 4706 4707 designated_link = rtw89_get_designated_link(rtwsta); 4708 4709 p += scnprintf(p, end - p, "STA %pM %s\n", sta->addr, 4710 sta->tdls ? "(TDLS)" : ""); 4711 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 4712 p += rtw89_sta_link_ids_get(rtwdev, p, end - p, rtwsta_link, 4713 rtwsta_link == designated_link); 4714 4715 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4716 } 4717 4718 static ssize_t rtw89_debug_priv_stations_get(struct rtw89_dev *rtwdev, 4719 struct rtw89_debugfs_priv *debugfs_priv, 4720 char *buf, size_t bufsz) 4721 { 4722 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4723 struct rtw89_debugfs_iter_data iter_data; 4724 char *p = buf, *end = buf + bufsz; 4725 u8 idx; 4726 4727 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4728 4729 p += scnprintf(p, end - p, "map:\n"); 4730 p += scnprintf(p, end - p, "\tmac_id: %*ph\n", 4731 (int)sizeof(rtwdev->mac_id_map), 4732 rtwdev->mac_id_map); 4733 p += scnprintf(p, end - p, "\taddr_cam: %*ph\n", 4734 (int)sizeof(cam_info->addr_cam_map), 4735 cam_info->addr_cam_map); 4736 p += scnprintf(p, end - p, "\tbssid_cam: %*ph\n", 4737 (int)sizeof(cam_info->bssid_cam_map), 4738 cam_info->bssid_cam_map); 4739 p += scnprintf(p, end - p, "\tsec_cam: %*ph\n", 4740 (int)sizeof(cam_info->sec_cam_map), 4741 cam_info->sec_cam_map); 4742 p += scnprintf(p, end - p, "\tba_cam: %*ph\n", 4743 (int)sizeof(cam_info->ba_cam_map), 4744 cam_info->ba_cam_map); 4745 p += scnprintf(p, end - p, "\tpkt_ofld: %*ph\n", 4746 (int)sizeof(rtwdev->pkt_offload), 4747 rtwdev->pkt_offload); 4748 4749 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 4750 if (!(rtwdev->chip->support_bands & BIT(idx))) 4751 continue; 4752 p += rtw89_dump_pkt_offload(p, end - p, &rtwdev->scan_info.pkt_list[idx], 4753 "\t\t[SCAN %u]: ", idx); 4754 } 4755 4756 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4757 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 4758 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, &iter_data); 4759 p += iter_data.written_sz; 4760 4761 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4762 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, &iter_data); 4763 p += iter_data.written_sz; 4764 4765 return p - buf; 4766 } 4767 4768 #define DM_INFO(type) {RTW89_DM_ ## type, #type} 4769 4770 static const struct rtw89_disabled_dm_info { 4771 enum rtw89_dm_type type; 4772 const char *name; 4773 } rtw89_disabled_dm_infos[] = { 4774 DM_INFO(DYNAMIC_EDCCA), 4775 DM_INFO(THERMAL_PROTECT), 4776 DM_INFO(TAS), 4777 DM_INFO(MLO), 4778 DM_INFO(HW_SCAN), 4779 DM_INFO(INACTIVE_PS), 4780 DM_INFO(DIG_PD), 4781 }; 4782 4783 static ssize_t 4784 rtw89_debug_priv_disable_dm_get(struct rtw89_dev *rtwdev, 4785 struct rtw89_debugfs_priv *debugfs_priv, 4786 char *buf, size_t bufsz) 4787 { 4788 const struct rtw89_disabled_dm_info *info; 4789 struct rtw89_hal *hal = &rtwdev->hal; 4790 char *p = buf, *end = buf + bufsz; 4791 u32 disabled; 4792 int i; 4793 4794 p += scnprintf(p, end - p, "Disabled DM: 0x%x\n", 4795 hal->disabled_dm_bitmap); 4796 4797 for (i = 0; i < ARRAY_SIZE(rtw89_disabled_dm_infos); i++) { 4798 info = &rtw89_disabled_dm_infos[i]; 4799 disabled = BIT(info->type) & hal->disabled_dm_bitmap; 4800 4801 p += scnprintf(p, end - p, "[%d] %s: %c\n", info->type, 4802 info->name, 4803 disabled ? 'X' : 'O'); 4804 } 4805 4806 return p - buf; 4807 } 4808 4809 static ssize_t 4810 rtw89_debug_priv_disable_dm_set(struct rtw89_dev *rtwdev, 4811 struct rtw89_debugfs_priv *debugfs_priv, 4812 const char *buf, size_t count) 4813 { 4814 u32 conf; 4815 int ret; 4816 4817 ret = kstrtou32(buf, 0, &conf); 4818 if (ret) 4819 return -EINVAL; 4820 4821 rtw89_core_dm_disable_cfg(rtwdev, conf); 4822 4823 return count; 4824 } 4825 4826 #define RTW89_DIG_PD_TH_MIN_DBM -102 4827 #define RTW89_DIG_PD_TH_MAX_DBM -40 4828 #define RTW89_DIG_PD_TH_STEP 2 4829 4830 static s8 rtw89_dig_pd_th_to_dbm(u8 reg_val) 4831 { 4832 return RTW89_DIG_PD_TH_MIN_DBM + RTW89_DIG_PD_TH_STEP * reg_val; 4833 } 4834 4835 static u8 rtw89_dig_pd_th_dbm_to_reg(s8 dbm) 4836 { 4837 return (dbm - RTW89_DIG_PD_TH_MIN_DBM) / RTW89_DIG_PD_TH_STEP; 4838 } 4839 4840 static ssize_t 4841 rtw89_debug_priv_static_pd_th_get(struct rtw89_dev *rtwdev, 4842 struct rtw89_debugfs_priv *debugfs_priv, 4843 char *buf, size_t bufsz) 4844 { 4845 struct rtw89_hal *hal = &rtwdev->hal; 4846 char *p = buf, *end = buf + bufsz; 4847 bool disabled; 4848 s8 pd_th_dbm; 4849 s8 cck_pd_th; 4850 4851 disabled = hal->disabled_dm_bitmap & BIT(RTW89_DM_DIG_PD); 4852 4853 if (disabled) { 4854 pd_th_dbm = rtw89_dig_pd_th_to_dbm(hal->fixed_dig_pd_th); 4855 cck_pd_th = hal->fixed_dig_cck_pd_th; 4856 4857 p += scnprintf(p, end - p, "DIG: static\n"); 4858 p += scnprintf(p, end - p, "OFDM PD threshold: %d dBm\n", pd_th_dbm); 4859 p += scnprintf(p, end - p, "CCK PD threshold: %d dBm\n", cck_pd_th); 4860 } else { 4861 p += scnprintf(p, end - p, "DIG: dynamic\n"); 4862 } 4863 4864 p += scnprintf(p, end - p, "\nUsage: echo <mode> [pd_th] > static_pd_th\n"); 4865 p += scnprintf(p, end - p, " mode: 0 = dynamic, 1 = static\n"); 4866 p += scnprintf(p, end - p, " pd_th: PD threshold in dBm (-102 ~ -40)\n"); 4867 4868 return p - buf; 4869 } 4870 4871 static ssize_t 4872 rtw89_debug_priv_static_pd_th_set(struct rtw89_dev *rtwdev, 4873 struct rtw89_debugfs_priv *debugfs_priv, 4874 const char *buf, size_t count) 4875 { 4876 struct rtw89_hal *hal = &rtwdev->hal; 4877 int ret; 4878 u32 mode; 4879 s32 pd_th_dbm; 4880 4881 ret = sscanf(buf, "%u %d", &mode, &pd_th_dbm); 4882 if (ret < 1) 4883 return -EINVAL; 4884 4885 if (mode > 1) 4886 return -EINVAL; 4887 4888 if (mode == 0) { 4889 rtw89_core_dm_disable_clr(rtwdev, RTW89_DM_DIG_PD); 4890 hal->fixed_dig_pd_th = 0; 4891 hal->fixed_dig_cck_pd_th = 0; 4892 4893 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4894 "DIG static mode disabled\n"); 4895 } else { 4896 if (ret < 2 || pd_th_dbm < RTW89_DIG_PD_TH_MIN_DBM || 4897 pd_th_dbm > RTW89_DIG_PD_TH_MAX_DBM) 4898 return -EINVAL; 4899 4900 rtw89_core_dm_disable_set(rtwdev, RTW89_DM_DIG_PD); 4901 hal->fixed_dig_pd_th = clamp(rtw89_dig_pd_th_dbm_to_reg(pd_th_dbm), 4902 0, 0x1f); 4903 /* CCK uses dBm directly */ 4904 hal->fixed_dig_cck_pd_th = pd_th_dbm; 4905 4906 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4907 "DIG static mode: PD=0x%02x (%d dBm), CCK=%d dBm\n", 4908 hal->fixed_dig_pd_th, 4909 rtw89_dig_pd_th_to_dbm(hal->fixed_dig_pd_th), 4910 hal->fixed_dig_cck_pd_th); 4911 } 4912 4913 return count; 4914 } 4915 4916 static void rtw89_debug_mlo_mode_set_mlsr(struct rtw89_dev *rtwdev, 4917 unsigned int link_id) 4918 { 4919 struct ieee80211_vif *vif; 4920 struct rtw89_vif *rtwvif; 4921 4922 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4923 vif = rtwvif_to_vif(rtwvif); 4924 if (!ieee80211_vif_is_mld(vif)) 4925 continue; 4926 4927 rtw89_core_mlsr_switch(rtwdev, rtwvif, link_id); 4928 } 4929 } 4930 4931 static ssize_t 4932 rtw89_debug_priv_mlo_mode_get(struct rtw89_dev *rtwdev, 4933 struct rtw89_debugfs_priv *debugfs_priv, 4934 char *buf, size_t bufsz) 4935 { 4936 bool mlo_dm_dis = rtwdev->hal.disabled_dm_bitmap & BIT(RTW89_DM_MLO); 4937 char *p = buf, *end = buf + bufsz; 4938 struct ieee80211_vif *vif; 4939 struct rtw89_vif *rtwvif; 4940 int count = 0; 4941 4942 p += scnprintf(p, end - p, "MLD(s) status: (MLO DM: %s)\n", 4943 str_disable_enable(mlo_dm_dis)); 4944 4945 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4946 vif = rtwvif_to_vif(rtwvif); 4947 if (!ieee80211_vif_is_mld(vif)) 4948 continue; 4949 4950 p += scnprintf(p, end - p, 4951 "\t#%u: MLO mode %x, valid 0x%x, active 0x%x\n", 4952 count++, rtwvif->mlo_mode, vif->valid_links, 4953 vif->active_links); 4954 } 4955 4956 if (count == 0) 4957 p += scnprintf(p, end - p, "\t(None)\n"); 4958 4959 return p - buf; 4960 } 4961 4962 static ssize_t 4963 rtw89_debug_priv_mlo_mode_set(struct rtw89_dev *rtwdev, 4964 struct rtw89_debugfs_priv *debugfs_priv, 4965 const char *buf, size_t count) 4966 { 4967 u8 num, mlo_mode; 4968 u32 argv; 4969 4970 num = sscanf(buf, "%hhx %u", &mlo_mode, &argv); 4971 if (num != 2) 4972 return -EINVAL; 4973 4974 rtw89_core_dm_disable_set(rtwdev, RTW89_DM_MLO); 4975 4976 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Set MLO mode to %x\n", mlo_mode); 4977 4978 switch (mlo_mode) { 4979 case RTW89_MLO_MODE_MLSR: 4980 rtw89_debug_mlo_mode_set_mlsr(rtwdev, argv); 4981 break; 4982 default: 4983 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Unsupported MLO mode\n"); 4984 rtw89_core_dm_disable_clr(rtwdev, RTW89_DM_MLO); 4985 4986 return -EOPNOTSUPP; 4987 } 4988 4989 return count; 4990 } 4991 4992 static int rtw89_get_beacon_info(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb, 4993 char *buf, size_t bufsz) 4994 { 4995 struct rtw89_pkt_stat *pkt_stat = &bb->last_pkt_stat; 4996 char *p = buf, *end = buf + bufsz; 4997 4998 p += scnprintf(p, end - p, "[PHY %u]\n", bb->phy_idx); 4999 p += scnprintf(p, end - p, "Beacon: %u\n", pkt_stat->beacon_nr); 5000 p += scnprintf(p, end - p, "raw rssi: %lu\n", ewma_rssi_read(&bb->bcn_rssi)); 5001 p += scnprintf(p, end - p, "hw rate: %u\n", pkt_stat->beacon_rate); 5002 p += scnprintf(p, end - p, "length: %u\n\n", pkt_stat->beacon_len); 5003 5004 return p - buf; 5005 } 5006 5007 static ssize_t 5008 rtw89_debug_priv_beacon_info_get(struct rtw89_dev *rtwdev, 5009 struct rtw89_debugfs_priv *debugfs_priv, 5010 char *buf, size_t bufsz) 5011 { 5012 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 5013 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 5014 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 5015 u16 upper, lower = bcn_stat->tbtt_tu_min; 5016 char *p = buf, *end = buf + bufsz; 5017 u16 *drift = bcn_stat->drift; 5018 u8 bcn_num = bcn_stat->num; 5019 struct rtw89_bb_ctx *bb; 5020 u8 count; 5021 u8 i; 5022 5023 rtw89_for_each_active_bb(rtwdev, bb) 5024 p += rtw89_get_beacon_info(rtwdev, bb, p, end - p); 5025 5026 p += scnprintf(p, end - p, "[Beacon info]\n"); 5027 p += scnprintf(p, end - p, "interval: %u\n", bcn_track->beacon_int); 5028 p += scnprintf(p, end - p, "dtim: %u\n", bcn_track->dtim); 5029 5030 p += scnprintf(p, end - p, "\n[Distribution]\n"); 5031 p += scnprintf(p, end - p, "tbtt\n"); 5032 for (i = 0; i < RTW89_BCN_TRACK_MAX_BIN_NUM; i++) { 5033 upper = lower + RTW89_BCN_TRACK_BIN_WIDTH - 1; 5034 if (i == RTW89_BCN_TRACK_MAX_BIN_NUM - 1) 5035 upper = max(upper, bcn_stat->tbtt_tu_max); 5036 5037 p += scnprintf(p, end - p, "%02u - %02u: %u\n", 5038 lower, upper, bcn_dist->bins[i]); 5039 5040 lower = upper + 1; 5041 } 5042 5043 p += scnprintf(p, end - p, "\ndrift\n"); 5044 5045 for (i = 0; i < bcn_num; i += count) { 5046 count = 1; 5047 while (i + count < bcn_num && drift[i] == drift[i + count]) 5048 count++; 5049 5050 p += scnprintf(p, end - p, "%u: %u\n", drift[i], count); 5051 } 5052 p += scnprintf(p, end - p, "\nlower bound: %u\n", bcn_dist->lower_bound); 5053 p += scnprintf(p, end - p, "upper bound: %u\n", bcn_dist->upper_bound); 5054 p += scnprintf(p, end - p, "outlier count: %u\n", bcn_dist->outlier_count); 5055 5056 p += scnprintf(p, end - p, "\n[Tracking]\n"); 5057 p += scnprintf(p, end - p, "tbtt offset: %u\n", bcn_track->tbtt_offset); 5058 p += scnprintf(p, end - p, "bcn timeout: %u\n", bcn_track->bcn_timeout); 5059 5060 return p - buf; 5061 } 5062 5063 enum __diag_mac_cmd { 5064 __CMD_EQUALV, 5065 __CMD_EQUALO, 5066 __CMD_NEQUALV, 5067 __CMD_NEQUALO, 5068 __CMD_SETEQUALV, 5069 __CMD_SETEQUALO, 5070 __CMD_CMPWCR, 5071 __CMD_CMPWWD, 5072 __CMD_NEQ_CMPWCR, 5073 __CMD_NEQ_CMPWWD, 5074 __CMD_INCREMENT, 5075 __CMD_MESSAGE, 5076 }; 5077 5078 enum __diag_mac_io { 5079 __IO_NORMAL, 5080 __IO_NORMAL_PCIE, 5081 __IO_NORMAL_USB, 5082 __IO_NORMAL_SDIO, 5083 __IO_PCIE_CFG, 5084 __IO_SDIO_CCCR, 5085 }; 5086 5087 struct __diag_mac_rule_header { 5088 u8 sheet; 5089 u8 cmd; 5090 u8 seq_major; 5091 u8 seq_minor; 5092 u8 io_band; 5093 #define __DIAG_MAC_IO GENMASK(3, 0) 5094 #define __DIAG_MAC_N_BAND BIT(4) 5095 #define __DIAG_MAC_HAS_BAND BIT(5) 5096 u8 len; /* include header. Unit: 4 bytes */ 5097 u8 rsvd[2]; 5098 } __packed; 5099 5100 struct __diag_mac_rule_equal { 5101 struct __diag_mac_rule_header header; 5102 __le32 addr; 5103 __le32 addr_name_offset; 5104 __le32 mask; 5105 __le32 val; 5106 __le32 msg_offset; 5107 u8 rsvd[4]; 5108 } __packed; 5109 5110 struct __diag_mac_rule_increment { 5111 struct __diag_mac_rule_header header; 5112 __le32 addr; 5113 __le32 addr_name_offset; 5114 __le32 mask; 5115 __le16 sel; 5116 __le16 delay; 5117 __le32 msg_offset; 5118 u8 rsvd[4]; 5119 } __packed; 5120 5121 struct __diag_mac_msg_buf { 5122 __le16 len; 5123 char string[]; 5124 } __packed; 5125 5126 static ssize_t rtw89_mac_diag_do_equalv(struct rtw89_dev *rtwdev, 5127 char *buf, size_t bufsz, 5128 const struct __diag_mac_rule_equal *r, 5129 const void *msg_start, 5130 u64 *positive_bmp) 5131 { 5132 const struct __diag_mac_msg_buf *name = msg_start + 5133 le32_to_cpu(r->addr_name_offset); 5134 const struct __diag_mac_msg_buf *msg = msg_start + 5135 le32_to_cpu(r->msg_offset); 5136 bool want_eq = r->header.cmd == __CMD_EQUALV; 5137 char *p = buf, *end = buf + bufsz; 5138 bool equal = false; 5139 u32 val; 5140 5141 *positive_bmp <<= 1; 5142 5143 if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG) 5144 val = rtw89_read32_pci_cfg(rtwdev, le32_to_cpu(r->addr)); 5145 else 5146 val = rtw89_read32(rtwdev, le32_to_cpu(r->addr)); 5147 5148 if ((val & le32_to_cpu(r->mask)) == le32_to_cpu(r->val)) 5149 equal = true; 5150 5151 if (want_eq == equal) { 5152 *positive_bmp |= BIT(0); 5153 return p - buf; 5154 } 5155 5156 p += scnprintf(p, end - p, "sheet: %d, cmd: %d, Reg: %.*s => %x, %.*s\n", 5157 r->header.sheet, r->header.cmd, le16_to_cpu(name->len), 5158 name->string, val, le16_to_cpu(msg->len), msg->string); 5159 5160 return p - buf; 5161 } 5162 5163 static ssize_t rtw89_mac_diag_do_increment(struct rtw89_dev *rtwdev, 5164 char *buf, size_t bufsz, 5165 const struct __diag_mac_rule_increment *r, 5166 const void *msg_start, 5167 u64 *positive_bmp) 5168 { 5169 const struct __diag_mac_msg_buf *name = msg_start + 5170 le32_to_cpu(r->addr_name_offset); 5171 const struct __diag_mac_msg_buf *msg = msg_start + 5172 le32_to_cpu(r->msg_offset); 5173 char *p = buf, *end = buf + bufsz; 5174 u32 addr = le32_to_cpu(r->addr); 5175 u32 mask = le32_to_cpu(r->mask); 5176 u16 sel = le16_to_cpu(r->sel); 5177 u32 val1, val2; 5178 5179 *positive_bmp <<= 1; 5180 5181 rtw89_write32(rtwdev, addr, sel); 5182 5183 if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG) 5184 val1 = rtw89_read32_pci_cfg(rtwdev, addr); 5185 else 5186 val1 = rtw89_read32(rtwdev, addr); 5187 5188 mdelay(le16_to_cpu(r->delay)); 5189 5190 if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG) 5191 val2 = rtw89_read32_pci_cfg(rtwdev, addr); 5192 else 5193 val2 = rtw89_read32(rtwdev, addr); 5194 5195 if ((val2 & mask) > (val1 & mask)) { 5196 *positive_bmp |= BIT(0); 5197 return p - buf; 5198 } 5199 5200 p += scnprintf(p, end - p, "sheet: %d, cmd: %d, Reg: %.*s [%d]=> %x, %.*s\n", 5201 r->header.sheet, r->header.cmd, le16_to_cpu(name->len), 5202 name->string, le16_to_cpu(r->sel), val1, 5203 le16_to_cpu(msg->len), msg->string); 5204 5205 return p - buf; 5206 } 5207 5208 static bool rtw89_mac_diag_match_hci(struct rtw89_dev *rtwdev, 5209 const struct __diag_mac_rule_header *rh) 5210 { 5211 switch (u8_get_bits(rh->io_band, __DIAG_MAC_IO)) { 5212 case __IO_NORMAL: 5213 default: 5214 return true; 5215 case __IO_NORMAL_PCIE: 5216 case __IO_PCIE_CFG: 5217 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) 5218 return true; 5219 break; 5220 case __IO_NORMAL_USB: 5221 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 5222 return true; 5223 break; 5224 case __IO_NORMAL_SDIO: 5225 case __IO_SDIO_CCCR: 5226 if (rtwdev->hci.type == RTW89_HCI_TYPE_SDIO) 5227 return true; 5228 break; 5229 } 5230 5231 return false; 5232 } 5233 5234 static bool rtw89_mac_diag_match_band(struct rtw89_dev *rtwdev, 5235 const struct __diag_mac_rule_header *rh) 5236 { 5237 u8 active_bands; 5238 bool has_band; 5239 u8 band; 5240 5241 has_band = u8_get_bits(rh->io_band, __DIAG_MAC_HAS_BAND); 5242 if (!has_band) 5243 return true; 5244 5245 band = u8_get_bits(rh->io_band, __DIAG_MAC_N_BAND); 5246 active_bands = rtw89_get_active_phy_bitmap(rtwdev); 5247 5248 if (active_bands & BIT(band)) 5249 return true; 5250 5251 return false; 5252 } 5253 5254 static ssize_t rtw89_mac_diag_iter_all(struct rtw89_dev *rtwdev, 5255 char *buf, size_t bufsz) 5256 { 5257 const struct rtw89_fw_element_hdr *elm = rtwdev->fw.elm_info.diag_mac; 5258 u32 n_plains = 0, n_rules = 0, n_positive = 0, n_ignore = 0; 5259 char *p = buf, *end = buf + bufsz, *p_rewind; 5260 const void *rule, *rule_end; 5261 u32 elm_size, rule_size; 5262 const void *msg_start; 5263 u64 positive_bmp = 0; 5264 u8 prev_sheet = 0; 5265 u8 prev_seq = 0; 5266 int limit; 5267 5268 if (!elm) { 5269 p += scnprintf(p, end - p, "No diag_mac entry\n"); 5270 goto out; 5271 } 5272 5273 rule_size = le32_to_cpu(elm->u.diag_mac.rule_size); 5274 elm_size = le32_to_cpu(elm->size); 5275 5276 if (ALIGN(rule_size, 16) > elm_size) { 5277 p += scnprintf(p, end - p, "rule size (%u) exceed elm_size (%u)\n", 5278 ALIGN(rule_size, 16), elm_size); 5279 goto out; 5280 } 5281 5282 rule = &elm->u.diag_mac.rules_and_msgs[0]; 5283 rule_end = &elm->u.diag_mac.rules_and_msgs[rule_size]; 5284 msg_start = &elm->u.diag_mac.rules_and_msgs[ALIGN(rule_size, 16)]; 5285 5286 for (limit = 0; limit < 5000 && rule < rule_end; limit++) { 5287 const struct __diag_mac_rule_header *rh = rule; 5288 u8 sheet = rh->sheet; 5289 u8 seq = rh->seq_major; 5290 5291 if (!rtw89_mac_diag_match_hci(rtwdev, rh) || 5292 !rtw89_mac_diag_match_band(rtwdev, rh)) { 5293 n_ignore++; 5294 goto next; 5295 } 5296 5297 if (!seq || prev_sheet != sheet || prev_seq != seq) { 5298 if (positive_bmp) { 5299 n_positive++; 5300 /* 5301 * discard output for negative results if one in 5302 * a sequence set is positive. 5303 */ 5304 if (p_rewind) 5305 p = p_rewind; 5306 } 5307 p_rewind = seq ? p : NULL; 5308 positive_bmp = 0; 5309 n_rules++; 5310 } 5311 5312 switch (rh->cmd) { 5313 case __CMD_EQUALV: 5314 case __CMD_NEQUALV: 5315 p += rtw89_mac_diag_do_equalv(rtwdev, p, end - p, rule, 5316 msg_start, &positive_bmp); 5317 break; 5318 case __CMD_INCREMENT: 5319 p += rtw89_mac_diag_do_increment(rtwdev, p, end - p, rule, 5320 msg_start, &positive_bmp); 5321 break; 5322 default: 5323 p += scnprintf(p, end - p, "unknown rule cmd %u\n", rh->cmd); 5324 break; 5325 } 5326 5327 next: 5328 n_plains++; 5329 rule += rh->len * 4; 5330 prev_seq = seq; 5331 prev_sheet = sheet; 5332 } 5333 5334 if (positive_bmp) { 5335 n_positive++; 5336 if (p_rewind) 5337 p = p_rewind; 5338 } 5339 5340 p += scnprintf(p, end - p, "\nPlain(Ignore)/Rules/Positive: %u(%u)/%u/%u\n", 5341 n_plains, n_ignore, n_rules, n_positive); 5342 5343 out: 5344 return p - buf; 5345 } 5346 5347 static ssize_t 5348 rtw89_debug_priv_diag_mac_get(struct rtw89_dev *rtwdev, 5349 struct rtw89_debugfs_priv *debugfs_priv, 5350 char *buf, size_t bufsz) 5351 { 5352 lockdep_assert_wiphy(rtwdev->hw->wiphy); 5353 5354 rtw89_leave_lps(rtwdev); 5355 5356 return rtw89_mac_diag_iter_all(rtwdev, buf, bufsz); 5357 } 5358 5359 static int rtw89_get_diag_bb(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb, 5360 char *buf, size_t bufsz) 5361 { 5362 struct rtw89_diag_bb *diag = &bb->diag; 5363 char *p = buf, *end = buf + bufsz; 5364 5365 p += scnprintf(p, end - p, "[PHY %u]\n", bb->phy_idx); 5366 p += scnprintf(p, end - p, "Diag bitmap = 0x%x\n", diag->diag_bb_bitmap); 5367 p += scnprintf(p, end - p, 5368 "Event{Hang, PD MAX, No RX, High FA, High EDCCA Ratio} = "); 5369 p += scnprintf(p, end - p, "{%d, %d, %d, %d, %d}\n", 5370 diag->diag_bb_cnt[RTW89_DIAG_BB_HANG], 5371 diag->diag_bb_cnt[RTW89_DIAG_BB_PD], 5372 diag->diag_bb_cnt[RTW89_DIAG_BB_NO_RX], 5373 diag->diag_bb_cnt[RTW89_DIAG_BB_FA], 5374 diag->diag_bb_cnt[RTW89_DIAG_BB_EDCCA]); 5375 p += scnprintf(p, end - p, 5376 "consecutive_no_tx_cnt=%d, consecutive_no_rx_cnt=%d\n\n", 5377 diag->consecutive_no_tx_cnt, 5378 diag->consecutive_no_rx_cnt); 5379 5380 return p - buf; 5381 } 5382 5383 static ssize_t 5384 rtw89_debug_priv_diag_bb_get(struct rtw89_dev *rtwdev, 5385 struct rtw89_debugfs_priv *debugfs_priv, 5386 char *buf, size_t bufsz) 5387 { 5388 char *p = buf, *end = buf + bufsz; 5389 struct rtw89_bb_ctx *bb; 5390 5391 lockdep_assert_wiphy(rtwdev->hw->wiphy); 5392 5393 rtw89_for_each_active_bb(rtwdev, bb) 5394 p += rtw89_get_diag_bb(rtwdev, bb, p, end - p); 5395 5396 return p - buf; 5397 } 5398 5399 static ssize_t 5400 rtw89_debug_priv_monitor_opts_get(struct rtw89_dev *rtwdev, 5401 struct rtw89_debugfs_priv *debugfs_priv, 5402 char *buf, size_t bufsz) 5403 { 5404 const struct rtw89_chip_info *chip = rtwdev->chip; 5405 char *p = buf, *end = buf + bufsz; 5406 u32 bss_color; 5407 u32 aid; 5408 5409 lockdep_assert_wiphy(rtwdev->hw->wiphy); 5410 5411 rtw89_leave_ps_mode(rtwdev); 5412 5413 bss_color = rtw89_phy_read32_idx(rtwdev, chip->bss_clr_map_reg, 5414 B_BSS_CLR_MAP_TGT, RTW89_PHY_0); 5415 aid = rtw89_phy_read32_idx(rtwdev, chip->bss_clr_map_reg, 5416 B_BSS_CLR_MAP_STAID, RTW89_PHY_0); 5417 5418 p += scnprintf(p, end - p, "bss_color=0x%x aid=0x%x\n", bss_color, aid); 5419 5420 return p - buf; 5421 } 5422 5423 static ssize_t 5424 rtw89_debug_priv_monitor_opts_set(struct rtw89_dev *rtwdev, 5425 struct rtw89_debugfs_priv *debugfs_priv, 5426 const char *buf, size_t count) 5427 { 5428 u32 bss_color; 5429 u32 aid; 5430 int num; 5431 5432 lockdep_assert_wiphy(rtwdev->hw->wiphy); 5433 5434 num = sscanf(buf, "%x %x", &bss_color, &aid); 5435 if (num != 2) { 5436 rtw89_info(rtwdev, "valid format: <bss color> <aid>\n"); 5437 return -EINVAL; 5438 } 5439 5440 rtw89_leave_ps_mode(rtwdev); 5441 5442 __rtw89_phy_set_bss_color(rtwdev, bss_color, aid, RTW89_PHY_0); 5443 5444 return count; 5445 } 5446 5447 #define rtw89_debug_priv_get(name, opts...) \ 5448 { \ 5449 .cb_read = rtw89_debug_priv_ ##name## _get, \ 5450 .opt = { opts }, \ 5451 } 5452 5453 #define rtw89_debug_priv_set(name, opts...) \ 5454 { \ 5455 .cb_write = rtw89_debug_priv_ ##name## _set, \ 5456 .opt = { opts }, \ 5457 } 5458 5459 #define rtw89_debug_priv_select_and_get(name, opts...) \ 5460 { \ 5461 .cb_write = rtw89_debug_priv_ ##name## _select, \ 5462 .cb_read = rtw89_debug_priv_ ##name## _get, \ 5463 .opt = { opts }, \ 5464 } 5465 5466 #define rtw89_debug_priv_set_and_get(name, opts...) \ 5467 { \ 5468 .cb_write = rtw89_debug_priv_ ##name## _set, \ 5469 .cb_read = rtw89_debug_priv_ ##name## _get, \ 5470 .opt = { opts }, \ 5471 } 5472 5473 #define RSIZE_8K .rsize = 0x2000 5474 #define RSIZE_12K .rsize = 0x3000 5475 #define RSIZE_16K .rsize = 0x4000 5476 #define RSIZE_20K .rsize = 0x5000 5477 #define RSIZE_32K .rsize = 0x8000 5478 #define RSIZE_64K .rsize = 0x10000 5479 #define RSIZE_128K .rsize = 0x20000 5480 #define RSIZE_1M .rsize = 0x100000 5481 #define RLOCK .rlock = 1 5482 #define WLOCK .wlock = 1 5483 #define RWLOCK RLOCK, WLOCK 5484 5485 static const struct rtw89_debugfs rtw89_debugfs_templ = { 5486 .read_reg = rtw89_debug_priv_select_and_get(read_reg), 5487 .write_reg = rtw89_debug_priv_set(write_reg), 5488 .read_rf = rtw89_debug_priv_select_and_get(read_rf, RLOCK), 5489 .write_rf = rtw89_debug_priv_set(write_rf, WLOCK), 5490 .rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump, RSIZE_8K, RLOCK), 5491 .txpwr_table = rtw89_debug_priv_get(txpwr_table, RSIZE_20K, RLOCK), 5492 .mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump, RSIZE_128K), 5493 .mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump, RSIZE_16K, RLOCK), 5494 .mac_dbg_port_dump = rtw89_debug_priv_select_and_get(mac_dbg_port_dump, RSIZE_1M), 5495 .send_h2c = rtw89_debug_priv_set(send_h2c), 5496 .early_h2c = rtw89_debug_priv_set_and_get(early_h2c, RWLOCK), 5497 .fw_crash = rtw89_debug_priv_set_and_get(fw_crash, WLOCK), 5498 .ser_counters = rtw89_debug_priv_get(ser_counters, RLOCK), 5499 .btc_info = rtw89_debug_priv_get(btc_info, RSIZE_12K), 5500 .btc_manual = rtw89_debug_priv_set(btc_manual), 5501 .fw_log_manual = rtw89_debug_priv_set(fw_log_manual, WLOCK), 5502 .phy_info = rtw89_debug_priv_get(phy_info), 5503 .bb_info = rtw89_debug_priv_set_and_get(bb_info, RWLOCK), 5504 .stations = rtw89_debug_priv_get(stations, RLOCK), 5505 .disable_dm = rtw89_debug_priv_set_and_get(disable_dm, RWLOCK), 5506 .static_pd_th = rtw89_debug_priv_set_and_get(static_pd_th, RWLOCK), 5507 .mlo_mode = rtw89_debug_priv_set_and_get(mlo_mode, RWLOCK), 5508 .beacon_info = rtw89_debug_priv_get(beacon_info), 5509 .diag_mac = rtw89_debug_priv_get(diag_mac, RSIZE_16K, RLOCK), 5510 .diag_bb = rtw89_debug_priv_get(diag_bb, RSIZE_8K, RLOCK), 5511 .monitor_opts = rtw89_debug_priv_set_and_get(monitor_opts, RWLOCK), 5512 }; 5513 5514 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 5515 do { \ 5516 struct rtw89_debugfs_priv *priv = &rtwdev->debugfs->name; \ 5517 priv->rtwdev = rtwdev; \ 5518 if (IS_ERR(debugfs_create_file(#name, mode, parent, priv, \ 5519 &file_ops_ ##fopname))) \ 5520 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 5521 } while (0) 5522 5523 #define rtw89_debugfs_add_w(name) \ 5524 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 5525 #define rtw89_debugfs_add_rw(name) \ 5526 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 5527 #define rtw89_debugfs_add_r(name) \ 5528 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 5529 5530 static 5531 void rtw89_debugfs_add_sec0(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 5532 { 5533 rtw89_debugfs_add_rw(read_reg); 5534 rtw89_debugfs_add_w(write_reg); 5535 rtw89_debugfs_add_rw(read_rf); 5536 rtw89_debugfs_add_w(write_rf); 5537 rtw89_debugfs_add_r(rf_reg_dump); 5538 rtw89_debugfs_add_r(txpwr_table); 5539 rtw89_debugfs_add_rw(mac_reg_dump); 5540 rtw89_debugfs_add_rw(mac_mem_dump); 5541 rtw89_debugfs_add_rw(mac_dbg_port_dump); 5542 } 5543 5544 static 5545 void rtw89_debugfs_add_sec1(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 5546 { 5547 rtw89_debugfs_add_w(send_h2c); 5548 rtw89_debugfs_add_rw(early_h2c); 5549 rtw89_debugfs_add_rw(fw_crash); 5550 rtw89_debugfs_add_r(ser_counters); 5551 rtw89_debugfs_add_r(btc_info); 5552 rtw89_debugfs_add_w(btc_manual); 5553 rtw89_debugfs_add_w(fw_log_manual); 5554 rtw89_debugfs_add_r(phy_info); 5555 rtw89_debugfs_add_rw(bb_info); 5556 rtw89_debugfs_add_r(stations); 5557 } 5558 5559 static 5560 void rtw89_debugfs_add_sec2(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 5561 { 5562 rtw89_debugfs_add_rw(disable_dm); 5563 rtw89_debugfs_add_rw(static_pd_th); 5564 rtw89_debugfs_add_rw(mlo_mode); 5565 rtw89_debugfs_add_r(beacon_info); 5566 rtw89_debugfs_add_r(diag_mac); 5567 rtw89_debugfs_add_r(diag_bb); 5568 rtw89_debugfs_add_rw(monitor_opts); 5569 } 5570 5571 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 5572 { 5573 struct dentry *debugfs_topdir; 5574 5575 rtwdev->debugfs = kmemdup(&rtw89_debugfs_templ, 5576 sizeof(rtw89_debugfs_templ), GFP_KERNEL); 5577 if (!rtwdev->debugfs) 5578 return; 5579 5580 debugfs_topdir = debugfs_create_dir("rtw89", 5581 rtwdev->hw->wiphy->debugfsdir); 5582 5583 rtw89_debugfs_add_sec0(rtwdev, debugfs_topdir); 5584 rtw89_debugfs_add_sec1(rtwdev, debugfs_topdir); 5585 rtw89_debugfs_add_sec2(rtwdev, debugfs_topdir); 5586 } 5587 5588 void rtw89_debugfs_deinit(struct rtw89_dev *rtwdev) 5589 { 5590 kfree(rtwdev->debugfs); 5591 } 5592 #endif 5593 5594 #ifdef CONFIG_RTW89_DEBUGMSG 5595 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, 5596 const char *fmt, ...) 5597 { 5598 struct va_format vaf = { 5599 .fmt = fmt, 5600 }; 5601 5602 va_list args; 5603 5604 va_start(args, fmt); 5605 vaf.va = &args; 5606 5607 if (rtw89_debug_mask & mask) 5608 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 5609 5610 va_end(args); 5611 } 5612 EXPORT_SYMBOL(rtw89_debug); 5613 #endif 5614