1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/vmalloc.h> 6 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "phy.h" 13 #include "ps.h" 14 #include "reg.h" 15 #include "sar.h" 16 #include "util.h" 17 18 #ifdef CONFIG_RTW89_DEBUGMSG 19 unsigned int rtw89_debug_mask; 20 EXPORT_SYMBOL(rtw89_debug_mask); 21 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 22 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 23 #endif 24 25 #ifdef CONFIG_RTW89_DEBUGFS 26 struct rtw89_debugfs_priv_opt { 27 bool rlock:1; 28 bool wlock:1; 29 size_t rsize; 30 }; 31 32 struct rtw89_debugfs_priv { 33 struct rtw89_dev *rtwdev; 34 ssize_t (*cb_read)(struct rtw89_dev *rtwdev, 35 struct rtw89_debugfs_priv *debugfs_priv, 36 char *buf, size_t bufsz); 37 ssize_t (*cb_write)(struct rtw89_dev *rtwdev, 38 struct rtw89_debugfs_priv *debugfs_priv, 39 const char *buf, size_t count); 40 struct rtw89_debugfs_priv_opt opt; 41 union { 42 u32 cb_data; 43 struct { 44 u32 addr; 45 u32 len; 46 } read_reg; 47 struct { 48 u32 addr; 49 u32 mask; 50 u8 path; 51 } read_rf; 52 struct { 53 u8 ss_dbg:1; 54 u8 dle_dbg:1; 55 u8 dmac_dbg:1; 56 u8 cmac_dbg:1; 57 u8 dbg_port:1; 58 } dbgpkg_en; 59 struct { 60 u32 start; 61 u32 len; 62 u8 sel; 63 } mac_mem; 64 }; 65 ssize_t rused; 66 char *rbuf; 67 }; 68 69 struct rtw89_debugfs { 70 struct rtw89_debugfs_priv read_reg; 71 struct rtw89_debugfs_priv write_reg; 72 struct rtw89_debugfs_priv read_rf; 73 struct rtw89_debugfs_priv write_rf; 74 struct rtw89_debugfs_priv rf_reg_dump; 75 struct rtw89_debugfs_priv txpwr_table; 76 struct rtw89_debugfs_priv mac_reg_dump; 77 struct rtw89_debugfs_priv mac_mem_dump; 78 struct rtw89_debugfs_priv mac_dbg_port_dump; 79 struct rtw89_debugfs_priv send_h2c; 80 struct rtw89_debugfs_priv early_h2c; 81 struct rtw89_debugfs_priv fw_crash; 82 struct rtw89_debugfs_priv btc_info; 83 struct rtw89_debugfs_priv btc_manual; 84 struct rtw89_debugfs_priv fw_log_manual; 85 struct rtw89_debugfs_priv phy_info; 86 struct rtw89_debugfs_priv stations; 87 struct rtw89_debugfs_priv disable_dm; 88 struct rtw89_debugfs_priv mlo_mode; 89 }; 90 91 struct rtw89_debugfs_iter_data { 92 char *buf; 93 size_t bufsz; 94 int written_sz; 95 }; 96 97 static void rtw89_debugfs_iter_data_setup(struct rtw89_debugfs_iter_data *iter_data, 98 char *buf, size_t bufsz) 99 { 100 iter_data->buf = buf; 101 iter_data->bufsz = bufsz; 102 iter_data->written_sz = 0; 103 } 104 105 static void rtw89_debugfs_iter_data_next(struct rtw89_debugfs_iter_data *iter_data, 106 char *buf, size_t bufsz, int written_sz) 107 { 108 iter_data->buf = buf; 109 iter_data->bufsz = bufsz; 110 iter_data->written_sz += written_sz; 111 } 112 113 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 114 [RATE_INFO_BW_20] = 20, 115 [RATE_INFO_BW_40] = 40, 116 [RATE_INFO_BW_80] = 80, 117 [RATE_INFO_BW_160] = 160, 118 [RATE_INFO_BW_320] = 320, 119 }; 120 121 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 122 { 123 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 124 return rtw89_rate_info_bw_to_mhz_map[bw]; 125 126 return 0; 127 } 128 129 static ssize_t rtw89_debugfs_file_read_helper(struct wiphy *wiphy, struct file *file, 130 char *buf, size_t bufsz, void *data) 131 { 132 struct rtw89_debugfs_priv *debugfs_priv = data; 133 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 134 ssize_t n; 135 136 n = debugfs_priv->cb_read(rtwdev, debugfs_priv, buf, bufsz); 137 rtw89_might_trailing_ellipsis(buf, bufsz, n); 138 139 return n; 140 } 141 142 static ssize_t rtw89_debugfs_file_read(struct file *file, char __user *userbuf, 143 size_t count, loff_t *ppos) 144 { 145 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 146 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 147 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 148 size_t bufsz = opt->rsize ? opt->rsize : PAGE_SIZE; 149 char *buf; 150 ssize_t n; 151 152 if (!debugfs_priv->rbuf) 153 debugfs_priv->rbuf = devm_kzalloc(rtwdev->dev, bufsz, GFP_KERNEL); 154 155 buf = debugfs_priv->rbuf; 156 if (!buf) 157 return -ENOMEM; 158 159 if (*ppos) { 160 n = debugfs_priv->rused; 161 goto out; 162 } 163 164 if (opt->rlock) { 165 n = wiphy_locked_debugfs_read(rtwdev->hw->wiphy, file, buf, bufsz, 166 userbuf, count, ppos, 167 rtw89_debugfs_file_read_helper, 168 debugfs_priv); 169 debugfs_priv->rused = n; 170 171 return n; 172 } 173 174 n = rtw89_debugfs_file_read_helper(rtwdev->hw->wiphy, file, buf, bufsz, 175 debugfs_priv); 176 debugfs_priv->rused = n; 177 178 out: 179 return simple_read_from_buffer(userbuf, count, ppos, buf, n); 180 } 181 182 static ssize_t rtw89_debugfs_file_write_helper(struct wiphy *wiphy, struct file *file, 183 char *buf, size_t count, void *data) 184 { 185 struct rtw89_debugfs_priv *debugfs_priv = data; 186 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 187 188 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 189 } 190 191 static ssize_t rtw89_debugfs_file_write(struct file *file, 192 const char __user *userbuf, 193 size_t count, loff_t *loff) 194 { 195 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 196 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 197 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 198 char *buf __free(kfree) = kmalloc(count + 1, GFP_KERNEL); 199 ssize_t n; 200 201 if (!buf) 202 return -ENOMEM; 203 204 if (opt->wlock) { 205 n = wiphy_locked_debugfs_write(rtwdev->hw->wiphy, 206 file, buf, count + 1, 207 userbuf, count, 208 rtw89_debugfs_file_write_helper, 209 debugfs_priv); 210 return n; 211 } 212 213 if (copy_from_user(buf, userbuf, count)) 214 return -EFAULT; 215 216 buf[count] = '\0'; 217 218 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 219 } 220 221 static const struct debugfs_short_fops file_ops_single_r = { 222 .read = rtw89_debugfs_file_read, 223 .llseek = generic_file_llseek, 224 }; 225 226 static const struct debugfs_short_fops file_ops_common_rw = { 227 .read = rtw89_debugfs_file_read, 228 .write = rtw89_debugfs_file_write, 229 .llseek = generic_file_llseek, 230 }; 231 232 static const struct debugfs_short_fops file_ops_single_w = { 233 .write = rtw89_debugfs_file_write, 234 .llseek = generic_file_llseek, 235 }; 236 237 static ssize_t 238 rtw89_debug_priv_read_reg_select(struct rtw89_dev *rtwdev, 239 struct rtw89_debugfs_priv *debugfs_priv, 240 const char *buf, size_t count) 241 { 242 u32 addr, len; 243 int num; 244 245 num = sscanf(buf, "%x %x", &addr, &len); 246 if (num != 2) { 247 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 248 return -EINVAL; 249 } 250 251 debugfs_priv->read_reg.addr = addr; 252 debugfs_priv->read_reg.len = len; 253 254 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 255 256 return count; 257 } 258 259 static 260 ssize_t rtw89_debug_priv_read_reg_get(struct rtw89_dev *rtwdev, 261 struct rtw89_debugfs_priv *debugfs_priv, 262 char *buf, size_t bufsz) 263 { 264 char *p = buf, *end = buf + bufsz; 265 u32 addr, addr_end, data, k; 266 u32 len; 267 268 len = debugfs_priv->read_reg.len; 269 addr = debugfs_priv->read_reg.addr; 270 271 if (len > 4) 272 goto ndata; 273 274 switch (len) { 275 case 1: 276 data = rtw89_read8(rtwdev, addr); 277 break; 278 case 2: 279 data = rtw89_read16(rtwdev, addr); 280 break; 281 case 4: 282 data = rtw89_read32(rtwdev, addr); 283 break; 284 default: 285 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 286 return -EINVAL; 287 } 288 289 p += scnprintf(p, end - p, "get %d bytes at 0x%08x=0x%08x\n", len, 290 addr, data); 291 292 return p - buf; 293 294 ndata: 295 addr_end = addr + len; 296 297 for (; addr < addr_end; addr += 16) { 298 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + addr); 299 for (k = 0; k < 16; k += 4) { 300 data = rtw89_read32(rtwdev, addr + k); 301 p += scnprintf(p, end - p, "%08x ", data); 302 } 303 p += scnprintf(p, end - p, "\n"); 304 } 305 306 return p - buf; 307 } 308 309 static 310 ssize_t rtw89_debug_priv_write_reg_set(struct rtw89_dev *rtwdev, 311 struct rtw89_debugfs_priv *debugfs_priv, 312 const char *buf, size_t count) 313 { 314 u32 addr, val, len; 315 int num; 316 317 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 318 if (num != 3) { 319 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 320 return -EINVAL; 321 } 322 323 switch (len) { 324 case 1: 325 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 326 rtw89_write8(rtwdev, addr, (u8)val); 327 break; 328 case 2: 329 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 330 rtw89_write16(rtwdev, addr, (u16)val); 331 break; 332 case 4: 333 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 334 rtw89_write32(rtwdev, addr, (u32)val); 335 break; 336 default: 337 rtw89_info(rtwdev, "invalid read write len %d\n", len); 338 break; 339 } 340 341 return count; 342 } 343 344 static ssize_t 345 rtw89_debug_priv_read_rf_select(struct rtw89_dev *rtwdev, 346 struct rtw89_debugfs_priv *debugfs_priv, 347 const char *buf, size_t count) 348 { 349 u32 addr, mask; 350 u8 path; 351 int num; 352 353 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 354 if (num != 3) { 355 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 356 return -EINVAL; 357 } 358 359 if (path >= rtwdev->chip->rf_path_num) { 360 rtw89_info(rtwdev, "wrong rf path\n"); 361 return -EINVAL; 362 } 363 debugfs_priv->read_rf.addr = addr; 364 debugfs_priv->read_rf.mask = mask; 365 debugfs_priv->read_rf.path = path; 366 367 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 368 369 return count; 370 } 371 372 static 373 ssize_t rtw89_debug_priv_read_rf_get(struct rtw89_dev *rtwdev, 374 struct rtw89_debugfs_priv *debugfs_priv, 375 char *buf, size_t bufsz) 376 { 377 char *p = buf, *end = buf + bufsz; 378 u32 addr, data, mask; 379 u8 path; 380 381 addr = debugfs_priv->read_rf.addr; 382 mask = debugfs_priv->read_rf.mask; 383 path = debugfs_priv->read_rf.path; 384 385 data = rtw89_read_rf(rtwdev, path, addr, mask); 386 387 p += scnprintf(p, end - p, "path %d, rf register 0x%08x=0x%08x\n", 388 path, addr, data); 389 390 return p - buf; 391 } 392 393 static 394 ssize_t rtw89_debug_priv_write_rf_set(struct rtw89_dev *rtwdev, 395 struct rtw89_debugfs_priv *debugfs_priv, 396 const char *buf, size_t count) 397 { 398 u32 addr, val, mask; 399 u8 path; 400 int num; 401 402 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 403 if (num != 4) { 404 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 405 return -EINVAL; 406 } 407 408 if (path >= rtwdev->chip->rf_path_num) { 409 rtw89_info(rtwdev, "wrong rf path\n"); 410 return -EINVAL; 411 } 412 413 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 414 path, addr, val, mask); 415 rtw89_write_rf(rtwdev, path, addr, mask, val); 416 417 return count; 418 } 419 420 static 421 ssize_t rtw89_debug_priv_rf_reg_dump_get(struct rtw89_dev *rtwdev, 422 struct rtw89_debugfs_priv *debugfs_priv, 423 char *buf, size_t bufsz) 424 { 425 const struct rtw89_chip_info *chip = rtwdev->chip; 426 char *p = buf, *end = buf + bufsz; 427 u32 addr, offset, data; 428 u8 path; 429 430 for (path = 0; path < chip->rf_path_num; path++) { 431 p += scnprintf(p, end - p, "RF path %d:\n\n", path); 432 for (addr = 0; addr < 0x100; addr += 4) { 433 p += scnprintf(p, end - p, "0x%08x: ", addr); 434 for (offset = 0; offset < 4; offset++) { 435 data = rtw89_read_rf(rtwdev, path, 436 addr + offset, RFREG_MASK); 437 p += scnprintf(p, end - p, "0x%05x ", data); 438 } 439 p += scnprintf(p, end - p, "\n"); 440 } 441 p += scnprintf(p, end - p, "\n"); 442 } 443 444 return p - buf; 445 } 446 447 struct txpwr_ent { 448 bool nested; 449 union { 450 const char *txt; 451 const struct txpwr_ent *ptr; 452 }; 453 u8 len; 454 }; 455 456 struct txpwr_map { 457 const struct txpwr_ent *ent; 458 u8 size; 459 u32 addr_from; 460 u32 addr_to; 461 u32 addr_to_1ss; 462 }; 463 464 #define __GEN_TXPWR_ENT_NESTED(_e) \ 465 { .nested = true, .ptr = __txpwr_ent_##_e, \ 466 .len = ARRAY_SIZE(__txpwr_ent_##_e) } 467 468 #define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t } 469 470 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 471 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 472 473 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 474 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 475 476 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 477 { .len = 8, .txt = _t "\t- " \ 478 _e0 " " _e1 " " _e2 " " _e3 " " \ 479 _e4 " " _e5 " " _e6 " " _e7 } 480 481 static const struct txpwr_ent __txpwr_ent_byr_ax[] = { 482 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 483 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 484 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 485 /* 1NSS */ 486 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 487 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 488 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 489 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 490 /* 2NSS */ 491 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 492 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 493 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 494 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 495 }; 496 497 static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) == 498 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 499 500 static const struct txpwr_map __txpwr_map_byr_ax = { 501 .ent = __txpwr_ent_byr_ax, 502 .size = ARRAY_SIZE(__txpwr_ent_byr_ax), 503 .addr_from = R_AX_PWR_BY_RATE, 504 .addr_to = R_AX_PWR_BY_RATE_MAX, 505 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX, 506 }; 507 508 static const struct txpwr_ent __txpwr_ent_lmt_ax[] = { 509 /* 1TX */ 510 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 511 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 512 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 513 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 514 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 515 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 516 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 517 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 518 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 519 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 520 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 521 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 522 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 523 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 524 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 525 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 526 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 527 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 528 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 529 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 530 /* 2TX */ 531 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 532 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 533 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 534 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 535 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 536 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 537 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 538 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 539 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 540 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 541 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 542 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 543 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 544 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 545 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 546 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 547 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 548 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 549 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 550 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 551 }; 552 553 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) == 554 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 555 556 static const struct txpwr_map __txpwr_map_lmt_ax = { 557 .ent = __txpwr_ent_lmt_ax, 558 .size = ARRAY_SIZE(__txpwr_ent_lmt_ax), 559 .addr_from = R_AX_PWR_LMT, 560 .addr_to = R_AX_PWR_LMT_MAX, 561 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX, 562 }; 563 564 static const struct txpwr_ent __txpwr_ent_lmt_ru_ax[] = { 565 /* 1TX */ 566 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 567 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 568 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 569 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 570 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 571 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 572 /* 2TX */ 573 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 574 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 575 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 576 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 577 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 578 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 579 }; 580 581 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) == 582 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 583 584 static const struct txpwr_map __txpwr_map_lmt_ru_ax = { 585 .ent = __txpwr_ent_lmt_ru_ax, 586 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_ax), 587 .addr_from = R_AX_PWR_RU_LMT, 588 .addr_to = R_AX_PWR_RU_LMT_MAX, 589 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX, 590 }; 591 592 static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = { 593 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 594 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 595 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 596 __GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"), 597 __GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 598 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 599 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 600 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 601 __GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"), 602 __GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 603 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 604 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 605 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 606 __GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"), 607 __GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 608 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 609 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 610 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 611 __GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"), 612 __GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 613 }; 614 615 static const struct txpwr_ent __txpwr_ent_byr_be[] = { 616 __GEN_TXPWR_ENT0("BW20"), 617 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 618 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 619 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 620 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 621 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 622 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 623 624 __GEN_TXPWR_ENT0("BW40"), 625 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 626 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 627 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 628 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 629 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 630 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 631 632 /* there is no CCK section after BW80 */ 633 __GEN_TXPWR_ENT0("BW80"), 634 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 635 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 636 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 637 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 638 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 639 640 __GEN_TXPWR_ENT0("BW160"), 641 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 642 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 643 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 644 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 645 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 646 647 __GEN_TXPWR_ENT0("BW320"), 648 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 649 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 650 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 651 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 652 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 653 }; 654 655 static const struct txpwr_map __txpwr_map_byr_be = { 656 .ent = __txpwr_ent_byr_be, 657 .size = ARRAY_SIZE(__txpwr_ent_byr_be), 658 .addr_from = R_BE_PWR_BY_RATE, 659 .addr_to = R_BE_PWR_BY_RATE_MAX, 660 .addr_to_1ss = 0, /* not support */ 661 }; 662 663 static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = { 664 __GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"), 665 __GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"), 666 __GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"), 667 __GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"), 668 __GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"), 669 __GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"), 670 __GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"), 671 __GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"), 672 __GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"), 673 __GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"), 674 __GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"), 675 __GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"), 676 __GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"), 677 __GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"), 678 __GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"), 679 __GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"), 680 __GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"), 681 __GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"), 682 __GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"), 683 __GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"), 684 __GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"), 685 __GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"), 686 __GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"), 687 __GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"), 688 __GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"), 689 __GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"), 690 __GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"), 691 __GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"), 692 __GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"), 693 __GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"), 694 __GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"), 695 __GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"), 696 __GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"), 697 __GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"), 698 __GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"), 699 }; 700 701 static const struct txpwr_ent __txpwr_ent_lmt_be[] = { 702 __GEN_TXPWR_ENT0("1TX"), 703 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 704 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 705 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 706 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 707 708 __GEN_TXPWR_ENT0("2TX"), 709 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 710 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 711 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 712 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 713 }; 714 715 static const struct txpwr_map __txpwr_map_lmt_be = { 716 .ent = __txpwr_ent_lmt_be, 717 .size = ARRAY_SIZE(__txpwr_ent_lmt_be), 718 .addr_from = R_BE_PWR_LMT, 719 .addr_to = R_BE_PWR_LMT_MAX, 720 .addr_to_1ss = 0, /* not support */ 721 }; 722 723 static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = { 724 __GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 725 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 726 __GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 727 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 728 __GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 729 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 730 __GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 731 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 732 __GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 733 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 734 __GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 735 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 736 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 737 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 738 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 739 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 740 __GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 741 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 742 __GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 743 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 744 }; 745 746 static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = { 747 __GEN_TXPWR_ENT0("1TX"), 748 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 749 750 __GEN_TXPWR_ENT0("2TX"), 751 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 752 }; 753 754 static const struct txpwr_map __txpwr_map_lmt_ru_be = { 755 .ent = __txpwr_ent_lmt_ru_be, 756 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be), 757 .addr_from = R_BE_PWR_RU_LMT, 758 .addr_to = R_BE_PWR_RU_LMT_MAX, 759 .addr_to_1ss = 0, /* not support */ 760 }; 761 762 static unsigned int 763 __print_txpwr_ent(char *buf, size_t bufsz, const struct txpwr_ent *ent, 764 const s8 *bufp, const unsigned int cur, unsigned int *ate) 765 { 766 char *p = buf, *end = buf + bufsz; 767 unsigned int cnt, i; 768 unsigned int eaten; 769 char *fmt; 770 771 if (ent->nested) { 772 for (cnt = 0, i = 0; i < ent->len; i++, cnt += eaten) 773 p += __print_txpwr_ent(p, end - p, ent->ptr + i, bufp, 774 cur + cnt, &eaten); 775 *ate = cnt; 776 goto out; 777 } 778 779 switch (ent->len) { 780 case 0: 781 p += scnprintf(p, end - p, "\t<< %s >>\n", ent->txt); 782 *ate = 0; 783 goto out; 784 case 2: 785 fmt = "%s\t| %3d, %3d,\t\tdBm\n"; 786 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 787 bufp[cur + 1]); 788 *ate = 2; 789 goto out; 790 case 4: 791 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 792 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 793 bufp[cur + 1], 794 bufp[cur + 2], bufp[cur + 3]); 795 *ate = 4; 796 goto out; 797 case 8: 798 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 799 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 800 bufp[cur + 1], 801 bufp[cur + 2], bufp[cur + 3], bufp[cur + 4], 802 bufp[cur + 5], bufp[cur + 6], bufp[cur + 7]); 803 *ate = 8; 804 goto out; 805 default: 806 return 0; 807 } 808 809 out: 810 return p - buf; 811 } 812 813 static ssize_t __print_txpwr_map(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 814 const struct txpwr_map *map) 815 { 816 u8 fct = rtwdev->chip->txpwr_factor_mac; 817 u8 path_num = rtwdev->chip->rf_path_num; 818 char *p = buf, *end = buf + bufsz; 819 unsigned int cur, i; 820 unsigned int eaten; 821 u32 max_valid_addr; 822 u32 val, addr; 823 s8 *bufp, tmp; 824 int ret; 825 826 bufp = vzalloc(map->addr_to - map->addr_from + 4); 827 if (!bufp) 828 return -ENOMEM; 829 830 if (path_num == 1) 831 max_valid_addr = map->addr_to_1ss; 832 else 833 max_valid_addr = map->addr_to; 834 835 if (max_valid_addr == 0) 836 return -EOPNOTSUPP; 837 838 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 839 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 840 if (ret) 841 val = MASKDWORD; 842 843 cur = addr - map->addr_from; 844 for (i = 0; i < 4; i++, val >>= 8) { 845 /* signed 7 bits, and reserved BIT(7) */ 846 tmp = sign_extend32(val, 6); 847 bufp[cur + i] = tmp >> fct; 848 } 849 } 850 851 for (cur = 0, i = 0; i < map->size; i++, cur += eaten) 852 p += __print_txpwr_ent(p, end - p, &map->ent[i], bufp, cur, &eaten); 853 854 vfree(bufp); 855 return p - buf; 856 } 857 858 static int __print_regd(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 859 const struct rtw89_chan *chan) 860 { 861 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 862 char *p = buf, *end = buf + bufsz; 863 u8 band = chan->band_type; 864 u8 regd = rtw89_regd_get(rtwdev, band); 865 866 p += scnprintf(p, end - p, "%s\n", rtw89_regd_get_string(regd)); 867 p += scnprintf(p, end - p, "\t(txpwr UK follow ETSI: %s)\n", 868 str_yes_no(regulatory->txpwr_uk_follow_etsi)); 869 870 return p - buf; 871 } 872 873 struct dbgfs_txpwr_table { 874 const struct txpwr_map *byr; 875 const struct txpwr_map *lmt; 876 const struct txpwr_map *lmt_ru; 877 }; 878 879 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = { 880 .byr = &__txpwr_map_byr_ax, 881 .lmt = &__txpwr_map_lmt_ax, 882 .lmt_ru = &__txpwr_map_lmt_ru_ax, 883 }; 884 885 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = { 886 .byr = &__txpwr_map_byr_be, 887 .lmt = &__txpwr_map_lmt_be, 888 .lmt_ru = &__txpwr_map_lmt_ru_be, 889 }; 890 891 static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = { 892 [RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax, 893 [RTW89_CHIP_BE] = &dbgfs_txpwr_table_be, 894 }; 895 896 static 897 int rtw89_debug_priv_txpwr_table_get_regd(struct rtw89_dev *rtwdev, 898 char *buf, size_t bufsz, 899 const struct rtw89_chan *chan) 900 { 901 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 902 const struct rtw89_reg_6ghz_tpe *tpe6 = ®ulatory->reg_6ghz_tpe; 903 char *p = buf, *end = buf + bufsz; 904 905 p += scnprintf(p, end - p, "[Chanctx] band %u, ch %u, bw %u\n", 906 chan->band_type, chan->channel, chan->band_width); 907 908 p += scnprintf(p, end - p, "[Regulatory] "); 909 p += __print_regd(rtwdev, p, end - p, chan); 910 911 if (chan->band_type == RTW89_BAND_6G) { 912 p += scnprintf(p, end - p, "[reg6_pwr_type] %u\n", 913 regulatory->reg_6ghz_power); 914 915 if (tpe6->valid) 916 p += scnprintf(p, end - p, "[TPE] %d dBm\n", 917 tpe6->constraint); 918 } 919 920 return p - buf; 921 } 922 923 static 924 ssize_t rtw89_debug_priv_txpwr_table_get(struct rtw89_dev *rtwdev, 925 struct rtw89_debugfs_priv *debugfs_priv, 926 char *buf, size_t bufsz) 927 { 928 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 929 struct rtw89_sar_parm sar_parm = {}; 930 const struct dbgfs_txpwr_table *tbl; 931 const struct rtw89_chan *chan; 932 char *p = buf, *end = buf + bufsz; 933 ssize_t n; 934 935 lockdep_assert_wiphy(rtwdev->hw->wiphy); 936 937 rtw89_leave_ps_mode(rtwdev); 938 chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 939 sar_parm.center_freq = chan->freq; 940 941 p += rtw89_debug_priv_txpwr_table_get_regd(rtwdev, p, end - p, chan); 942 943 p += scnprintf(p, end - p, "[SAR]\n"); 944 p += rtw89_print_sar(rtwdev, p, end - p, &sar_parm); 945 946 p += scnprintf(p, end - p, "[TAS]\n"); 947 p += rtw89_print_tas(rtwdev, p, end - p); 948 949 p += scnprintf(p, end - p, "[DAG]\n"); 950 p += rtw89_print_ant_gain(rtwdev, p, end - p, chan); 951 952 tbl = dbgfs_txpwr_tables[chip_gen]; 953 if (!tbl) 954 return -EOPNOTSUPP; 955 956 p += scnprintf(p, end - p, "\n[TX power byrate]\n"); 957 n = __print_txpwr_map(rtwdev, p, end - p, tbl->byr); 958 if (n < 0) 959 return n; 960 p += n; 961 962 p += scnprintf(p, end - p, "\n[TX power limit]\n"); 963 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt); 964 if (n < 0) 965 return n; 966 p += n; 967 968 p += scnprintf(p, end - p, "\n[TX power limit_ru]\n"); 969 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru); 970 if (n < 0) 971 return n; 972 p += n; 973 974 return p - buf; 975 } 976 977 static ssize_t 978 rtw89_debug_priv_mac_reg_dump_select(struct rtw89_dev *rtwdev, 979 struct rtw89_debugfs_priv *debugfs_priv, 980 const char *buf, size_t count) 981 { 982 const struct rtw89_chip_info *chip = rtwdev->chip; 983 int sel; 984 int ret; 985 986 ret = kstrtoint(buf, 0, &sel); 987 if (ret) 988 return ret; 989 990 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 991 rtw89_info(rtwdev, "invalid args: %d\n", sel); 992 return -EINVAL; 993 } 994 995 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 996 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 997 chip->chip_id); 998 return -EINVAL; 999 } 1000 1001 debugfs_priv->cb_data = sel; 1002 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 1003 1004 return count; 1005 } 1006 1007 #define RTW89_MAC_PAGE_SIZE 0x100 1008 1009 static 1010 ssize_t rtw89_debug_priv_mac_reg_dump_get(struct rtw89_dev *rtwdev, 1011 struct rtw89_debugfs_priv *debugfs_priv, 1012 char *buf, size_t bufsz) 1013 { 1014 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 1015 char *p = buf, *end = buf + bufsz; 1016 u32 start, end_addr; 1017 u32 i, j, k, page; 1018 u32 val; 1019 1020 switch (reg_sel) { 1021 case RTW89_DBG_SEL_MAC_00: 1022 p += scnprintf(p, end - p, "Debug selected MAC page 0x00\n"); 1023 start = 0x000; 1024 end_addr = 0x014; 1025 break; 1026 case RTW89_DBG_SEL_MAC_30: 1027 p += scnprintf(p, end - p, "Debug selected MAC page 0x30\n"); 1028 start = 0x030; 1029 end_addr = 0x033; 1030 break; 1031 case RTW89_DBG_SEL_MAC_40: 1032 p += scnprintf(p, end - p, "Debug selected MAC page 0x40\n"); 1033 start = 0x040; 1034 end_addr = 0x07f; 1035 break; 1036 case RTW89_DBG_SEL_MAC_80: 1037 p += scnprintf(p, end - p, "Debug selected MAC page 0x80\n"); 1038 start = 0x080; 1039 end_addr = 0x09f; 1040 break; 1041 case RTW89_DBG_SEL_MAC_C0: 1042 p += scnprintf(p, end - p, "Debug selected MAC page 0xc0\n"); 1043 start = 0x0c0; 1044 end_addr = 0x0df; 1045 break; 1046 case RTW89_DBG_SEL_MAC_E0: 1047 p += scnprintf(p, end - p, "Debug selected MAC page 0xe0\n"); 1048 start = 0x0e0; 1049 end_addr = 0x0ff; 1050 break; 1051 case RTW89_DBG_SEL_BB: 1052 p += scnprintf(p, end - p, "Debug selected BB register\n"); 1053 start = 0x100; 1054 end_addr = 0x17f; 1055 break; 1056 case RTW89_DBG_SEL_IQK: 1057 p += scnprintf(p, end - p, "Debug selected IQK register\n"); 1058 start = 0x180; 1059 end_addr = 0x1bf; 1060 break; 1061 case RTW89_DBG_SEL_RFC: 1062 p += scnprintf(p, end - p, "Debug selected RFC register\n"); 1063 start = 0x1c0; 1064 end_addr = 0x1ff; 1065 break; 1066 default: 1067 p += scnprintf(p, end - p, "Selected invalid register page\n"); 1068 return -EINVAL; 1069 } 1070 1071 for (i = start; i <= end_addr; i++) { 1072 page = i << 8; 1073 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 1074 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + j); 1075 for (k = 0; k < 4; k++) { 1076 val = rtw89_read32(rtwdev, j + (k << 2)); 1077 p += scnprintf(p, end - p, "%08x ", val); 1078 } 1079 p += scnprintf(p, end - p, "\n"); 1080 } 1081 } 1082 1083 return p - buf; 1084 } 1085 1086 static ssize_t 1087 rtw89_debug_priv_mac_mem_dump_select(struct rtw89_dev *rtwdev, 1088 struct rtw89_debugfs_priv *debugfs_priv, 1089 const char *buf, size_t count) 1090 { 1091 u32 sel, start_addr, len; 1092 int num; 1093 1094 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 1095 if (num != 3) { 1096 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 1097 return -EINVAL; 1098 } 1099 1100 debugfs_priv->mac_mem.sel = sel; 1101 debugfs_priv->mac_mem.start = start_addr; 1102 debugfs_priv->mac_mem.len = len; 1103 1104 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 1105 sel, start_addr, len); 1106 1107 return count; 1108 } 1109 1110 static int rtw89_debug_dump_mac_mem(struct rtw89_dev *rtwdev, 1111 char *buf, size_t bufsz, 1112 u8 sel, u32 start_addr, u32 len) 1113 { 1114 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1115 u32 filter_model_addr = mac->filter_model_addr; 1116 u32 indir_access_addr = mac->indir_access_addr; 1117 u32 mem_page_size = mac->mem_page_size; 1118 u32 base_addr, start_page, residue; 1119 char *p = buf, *end = buf + bufsz; 1120 u32 i, j, pp, pages; 1121 u32 dump_len, remain; 1122 u32 val; 1123 1124 remain = len; 1125 pages = len / mem_page_size + 1; 1126 start_page = start_addr / mem_page_size; 1127 residue = start_addr % mem_page_size; 1128 base_addr = mac->mem_base_addrs[sel]; 1129 base_addr += start_page * mem_page_size; 1130 1131 for (pp = 0; pp < pages; pp++) { 1132 dump_len = min_t(u32, remain, mem_page_size); 1133 rtw89_write32(rtwdev, filter_model_addr, base_addr); 1134 for (i = indir_access_addr + residue; 1135 i < indir_access_addr + dump_len;) { 1136 p += scnprintf(p, end - p, "%08xh:", i); 1137 for (j = 0; 1138 j < 4 && i < indir_access_addr + dump_len; 1139 j++, i += 4) { 1140 val = rtw89_read32(rtwdev, i); 1141 p += scnprintf(p, end - p, " %08x", val); 1142 remain -= 4; 1143 } 1144 p += scnprintf(p, end - p, "\n"); 1145 } 1146 base_addr += mem_page_size; 1147 } 1148 1149 return p - buf; 1150 } 1151 1152 static ssize_t 1153 rtw89_debug_priv_mac_mem_dump_get(struct rtw89_dev *rtwdev, 1154 struct rtw89_debugfs_priv *debugfs_priv, 1155 char *buf, size_t bufsz) 1156 { 1157 char *p = buf, *end = buf + bufsz; 1158 bool grant_read = false; 1159 1160 lockdep_assert_wiphy(rtwdev->hw->wiphy); 1161 1162 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 1163 return -ENOENT; 1164 1165 if (rtwdev->chip->chip_id == RTL8852C) { 1166 switch (debugfs_priv->mac_mem.sel) { 1167 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 1168 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 1169 case RTW89_MAC_MEM_TXDATA_FIFO_0: 1170 case RTW89_MAC_MEM_TXDATA_FIFO_1: 1171 grant_read = true; 1172 break; 1173 default: 1174 break; 1175 } 1176 } 1177 1178 rtw89_leave_ps_mode(rtwdev); 1179 if (grant_read) 1180 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1181 p += rtw89_debug_dump_mac_mem(rtwdev, p, end - p, 1182 debugfs_priv->mac_mem.sel, 1183 debugfs_priv->mac_mem.start, 1184 debugfs_priv->mac_mem.len); 1185 if (grant_read) 1186 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1187 1188 return p - buf; 1189 } 1190 1191 static ssize_t 1192 rtw89_debug_priv_mac_dbg_port_dump_select(struct rtw89_dev *rtwdev, 1193 struct rtw89_debugfs_priv *debugfs_priv, 1194 const char *buf, size_t count) 1195 { 1196 int sel, set; 1197 int num; 1198 bool enable; 1199 1200 num = sscanf(buf, "%d %d", &sel, &set); 1201 if (num != 2) { 1202 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 1203 return -EINVAL; 1204 } 1205 1206 enable = set != 0; 1207 switch (sel) { 1208 case 0: 1209 debugfs_priv->dbgpkg_en.ss_dbg = enable; 1210 break; 1211 case 1: 1212 debugfs_priv->dbgpkg_en.dle_dbg = enable; 1213 break; 1214 case 2: 1215 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 1216 break; 1217 case 3: 1218 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 1219 break; 1220 case 4: 1221 debugfs_priv->dbgpkg_en.dbg_port = enable; 1222 break; 1223 default: 1224 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 1225 return -EINVAL; 1226 } 1227 1228 rtw89_info(rtwdev, "%s debug port dump %d\n", 1229 enable ? "Enable" : "Disable", sel); 1230 1231 return count; 1232 } 1233 1234 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 1235 char *buf, size_t bufsz) 1236 { 1237 return 0; 1238 } 1239 1240 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 1241 char *buf, size_t bufsz) 1242 { 1243 #define DLE_DFI_DUMP(__type, __target, __sel) \ 1244 ({ \ 1245 u32 __ctrl; \ 1246 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 1247 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 1248 u32 __data, __val32; \ 1249 int __ret; \ 1250 \ 1251 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 1252 DLE_DFI_TYPE_##__target) | \ 1253 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 1254 B_AX_WDE_DFI_ACTIVE; \ 1255 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 1256 __ret = read_poll_timeout(rtw89_read32, __val32, \ 1257 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 1258 1000, 50000, false, \ 1259 rtwdev, __reg_ctrl); \ 1260 if (__ret) { \ 1261 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 1262 #__type, #__target, __sel); \ 1263 return __ret; \ 1264 } \ 1265 \ 1266 __data = rtw89_read32(rtwdev, __reg_data); \ 1267 __data; \ 1268 }) 1269 1270 #define DLE_DFI_FREE_PAGE_DUMP(__p, __end, __type) \ 1271 ({ \ 1272 u32 __freepg, __pubpg; \ 1273 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 1274 \ 1275 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 1276 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 1277 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 1278 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 1279 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 1280 __p += scnprintf(__p, __end - __p, "[%s] freepg head: %d\n", \ 1281 #__type, __freepg_head); \ 1282 __p += scnprintf(__p, __end - __p, "[%s] freepg tail: %d\n", \ 1283 #__type, __freepg_tail); \ 1284 __p += scnprintf(__p, __end - __p, "[%s] pubpg num : %d\n", \ 1285 #__type, __pubpg_num); \ 1286 }) 1287 1288 #define case_QUOTA(__p, __end, __type, __id) \ 1289 case __type##_QTAID_##__id: \ 1290 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 1291 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 1292 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 1293 __p += scnprintf(__p, __end - __p, "[%s][%s] rsv_pgnum: %d\n", \ 1294 #__type, #__id, rsv_pgnum); \ 1295 __p += scnprintf(__p, __end - __p, "[%s][%s] use_pgnum: %d\n", \ 1296 #__type, #__id, use_pgnum); \ 1297 break 1298 char *p = buf, *end = buf + bufsz; 1299 u32 quota_id; 1300 u32 val32; 1301 u16 rsv_pgnum, use_pgnum; 1302 int ret; 1303 1304 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1305 if (ret) { 1306 p += scnprintf(p, end - p, "[DLE] : DMAC not enabled\n"); 1307 goto out; 1308 } 1309 1310 DLE_DFI_FREE_PAGE_DUMP(p, end, WDE); 1311 DLE_DFI_FREE_PAGE_DUMP(p, end, PLE); 1312 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 1313 switch (quota_id) { 1314 case_QUOTA(p, end, WDE, HOST_IF); 1315 case_QUOTA(p, end, WDE, WLAN_CPU); 1316 case_QUOTA(p, end, WDE, DATA_CPU); 1317 case_QUOTA(p, end, WDE, PKTIN); 1318 case_QUOTA(p, end, WDE, CPUIO); 1319 } 1320 } 1321 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 1322 switch (quota_id) { 1323 case_QUOTA(p, end, PLE, B0_TXPL); 1324 case_QUOTA(p, end, PLE, B1_TXPL); 1325 case_QUOTA(p, end, PLE, C2H); 1326 case_QUOTA(p, end, PLE, H2C); 1327 case_QUOTA(p, end, PLE, WLAN_CPU); 1328 case_QUOTA(p, end, PLE, MPDU); 1329 case_QUOTA(p, end, PLE, CMAC0_RX); 1330 case_QUOTA(p, end, PLE, CMAC1_RX); 1331 case_QUOTA(p, end, PLE, CMAC1_BBRPT); 1332 case_QUOTA(p, end, PLE, WDRLS); 1333 case_QUOTA(p, end, PLE, CPUIO); 1334 } 1335 } 1336 1337 out: 1338 return p - buf; 1339 1340 #undef case_QUOTA 1341 #undef DLE_DFI_DUMP 1342 #undef DLE_DFI_FREE_PAGE_DUMP 1343 } 1344 1345 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 1346 char *buf, size_t bufsz) 1347 { 1348 const struct rtw89_chip_info *chip = rtwdev->chip; 1349 char *p = buf, *end = buf + bufsz; 1350 u32 dmac_err; 1351 int i, ret; 1352 1353 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1354 if (ret) { 1355 p += scnprintf(p, end - p, "[DMAC] : DMAC not enabled\n"); 1356 goto out; 1357 } 1358 1359 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1360 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1361 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1362 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1363 1364 if (dmac_err) { 1365 p += scnprintf(p, end - p, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1366 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1367 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1368 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1369 if (chip->chip_id == RTL8852C) { 1370 p += scnprintf(p, end - p, 1371 "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1372 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1373 p += scnprintf(p, end - p, 1374 "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1375 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1376 p += scnprintf(p, end - p, 1377 "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1378 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1379 p += scnprintf(p, end - p, 1380 "R_AX_PLE_DBGERR_STS=0x%08x\n", 1381 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1382 } 1383 } 1384 1385 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1386 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1387 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1388 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1389 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1390 if (chip->chip_id == RTL8852C) 1391 p += scnprintf(p, end - p, 1392 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1393 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1394 else 1395 p += scnprintf(p, end - p, 1396 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1397 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1398 } 1399 1400 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1401 if (chip->chip_id == RTL8852C) { 1402 p += scnprintf(p, end - p, 1403 "R_AX_SEC_ERR_IMR=0x%08x\n", 1404 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1405 p += scnprintf(p, end - p, 1406 "R_AX_SEC_ERR_ISR=0x%08x\n", 1407 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1408 p += scnprintf(p, end - p, 1409 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1410 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1411 p += scnprintf(p, end - p, 1412 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1413 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1414 p += scnprintf(p, end - p, 1415 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1416 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1417 p += scnprintf(p, end - p, 1418 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1419 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1420 p += scnprintf(p, end - p, "R_AX_SEC_DEBUG1=0x%08x\n", 1421 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1422 p += scnprintf(p, end - p, 1423 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1424 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1425 p += scnprintf(p, end - p, 1426 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1427 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1428 1429 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1430 B_AX_DBG_SEL0, 0x8B); 1431 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1432 B_AX_DBG_SEL1, 0x8B); 1433 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1434 B_AX_SEL_0XC0_MASK, 1); 1435 for (i = 0; i < 0x10; i++) { 1436 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1437 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1438 p += scnprintf(p, end - p, 1439 "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1440 i, 1441 rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1442 } 1443 } else { 1444 p += scnprintf(p, end - p, 1445 "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1446 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1447 p += scnprintf(p, end - p, 1448 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1449 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1450 p += scnprintf(p, end - p, 1451 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1452 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1453 p += scnprintf(p, end - p, 1454 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1455 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1456 p += scnprintf(p, end - p, 1457 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1458 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1459 p += scnprintf(p, end - p, 1460 "R_AX_SEC_CAM_WDATA=0x%08x\n", 1461 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1462 p += scnprintf(p, end - p, 1463 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1464 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1465 p += scnprintf(p, end - p, 1466 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1467 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1468 p += scnprintf(p, end - p, 1469 "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1470 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1471 p += scnprintf(p, end - p, 1472 "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1473 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1474 } 1475 } 1476 1477 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1478 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1479 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1480 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1481 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1482 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1483 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1484 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1485 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1486 } 1487 1488 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1489 p += scnprintf(p, end - p, 1490 "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1491 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1492 p += scnprintf(p, end - p, 1493 "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1494 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1495 } 1496 1497 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1498 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1499 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1500 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1501 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1502 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1503 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1504 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1505 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1506 } 1507 1508 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1509 if (chip->chip_id == RTL8852C) { 1510 p += scnprintf(p, end - p, 1511 "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1512 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1513 p += scnprintf(p, end - p, 1514 "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1515 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1516 p += scnprintf(p, end - p, 1517 "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1518 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1519 p += scnprintf(p, end - p, 1520 "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1521 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1522 } else { 1523 p += scnprintf(p, end - p, 1524 "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1525 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1526 p += scnprintf(p, end - p, 1527 "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1528 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1529 } 1530 } 1531 1532 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1533 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1534 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1535 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1536 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1537 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1538 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1539 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1540 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1541 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1542 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1543 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1544 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1545 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1546 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1547 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1548 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1549 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1550 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1551 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1552 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1553 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1554 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1555 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1556 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1557 if (chip->chip_id == RTL8852C) { 1558 p += scnprintf(p, end - p, "R_AX_RX_CTRL0=0x%08x\n", 1559 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1560 p += scnprintf(p, end - p, "R_AX_RX_CTRL1=0x%08x\n", 1561 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1562 p += scnprintf(p, end - p, "R_AX_RX_CTRL2=0x%08x\n", 1563 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1564 } else { 1565 p += scnprintf(p, end - p, 1566 "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1567 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1568 p += scnprintf(p, end - p, 1569 "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1570 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1571 p += scnprintf(p, end - p, 1572 "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1573 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1574 } 1575 } 1576 1577 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1578 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1579 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1580 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1581 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1582 } 1583 1584 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1585 p += scnprintf(p, end - p, 1586 "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1587 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1588 p += scnprintf(p, end - p, 1589 "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1590 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1591 p += scnprintf(p, end - p, 1592 "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1593 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1594 p += scnprintf(p, end - p, 1595 "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1596 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1597 p += scnprintf(p, end - p, 1598 "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1599 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1600 p += scnprintf(p, end - p, 1601 "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1602 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1603 } 1604 1605 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1606 if (chip->chip_id == RTL8852C) { 1607 p += scnprintf(p, end - p, 1608 "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1609 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1610 p += scnprintf(p, end - p, 1611 "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1612 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1613 p += scnprintf(p, end - p, 1614 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1615 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1616 p += scnprintf(p, end - p, 1617 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1618 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1619 p += scnprintf(p, end - p, 1620 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1621 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1622 p += scnprintf(p, end - p, 1623 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1624 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1625 } else { 1626 p += scnprintf(p, end - p, 1627 "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1628 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1629 p += scnprintf(p, end - p, 1630 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1631 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1632 p += scnprintf(p, end - p, 1633 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1634 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1635 p += scnprintf(p, end - p, 1636 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1637 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1638 p += scnprintf(p, end - p, 1639 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1640 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1641 } 1642 } 1643 1644 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1645 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1646 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1647 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1648 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1649 } 1650 1651 out: 1652 return p - buf; 1653 } 1654 1655 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1656 char *buf, size_t bufsz, 1657 enum rtw89_mac_idx band) 1658 { 1659 const struct rtw89_chip_info *chip = rtwdev->chip; 1660 char *p = buf, *end = buf + bufsz; 1661 u32 offset = 0; 1662 u32 cmac_err; 1663 int ret; 1664 1665 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1666 if (ret) { 1667 if (band) 1668 p += scnprintf(p, end - p, 1669 "[CMAC] : CMAC1 not enabled\n"); 1670 else 1671 p += scnprintf(p, end - p, 1672 "[CMAC] : CMAC0 not enabled\n"); 1673 goto out; 1674 } 1675 1676 if (band) 1677 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1678 1679 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1680 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1681 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1682 p += scnprintf(p, end - p, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1683 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1684 p += scnprintf(p, end - p, "R_AX_CK_EN [%d]=0x%08x\n", band, 1685 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1686 1687 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1688 p += scnprintf(p, end - p, 1689 "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1690 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1691 p += scnprintf(p, end - p, 1692 "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1693 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1694 } 1695 1696 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1697 p += scnprintf(p, end - p, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", 1698 band, 1699 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1700 p += scnprintf(p, end - p, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", 1701 band, 1702 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1703 } 1704 1705 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1706 if (chip->chip_id == RTL8852C) { 1707 p += scnprintf(p, end - p, 1708 "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1709 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1710 p += scnprintf(p, end - p, 1711 "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", 1712 band, 1713 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1714 } else { 1715 p += scnprintf(p, end - p, 1716 "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1717 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1718 } 1719 } 1720 1721 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1722 if (chip->chip_id == RTL8852C) { 1723 p += scnprintf(p, end - p, 1724 "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", 1725 band, 1726 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1727 p += scnprintf(p, end - p, 1728 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1729 band, 1730 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1731 } else { 1732 p += scnprintf(p, end - p, 1733 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1734 band, 1735 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1736 } 1737 } 1738 1739 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1740 p += scnprintf(p, end - p, "R_AX_TXPWR_IMR [%d]=0x%08x\n", 1741 band, 1742 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1743 p += scnprintf(p, end - p, "R_AX_TXPWR_ISR [%d]=0x%08x\n", 1744 band, 1745 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1746 } 1747 1748 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1749 if (chip->chip_id == RTL8852C) { 1750 p += scnprintf(p, end - p, 1751 "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", 1752 band, 1753 rtw89_read32(rtwdev, 1754 R_AX_TRXPTCL_ERROR_INDICA + offset)); 1755 p += scnprintf(p, end - p, 1756 "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", 1757 band, 1758 rtw89_read32(rtwdev, 1759 R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1760 } else { 1761 p += scnprintf(p, end - p, 1762 "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", 1763 band, 1764 rtw89_read32(rtwdev, 1765 R_AX_TMAC_ERR_IMR_ISR + offset)); 1766 } 1767 p += scnprintf(p, end - p, 1768 "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1769 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1770 } 1771 1772 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1773 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1774 1775 out: 1776 return p - buf; 1777 } 1778 1779 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1780 char *buf, size_t bufsz) 1781 { 1782 char *p = buf, *end = buf + bufsz; 1783 1784 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_0); 1785 if (rtwdev->dbcc_en) 1786 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_1); 1787 1788 return p - buf; 1789 } 1790 1791 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1792 .sel_addr = R_AX_PTCL_DBG, 1793 .sel_byte = 1, 1794 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1795 .srt = 0x00, 1796 .end = 0x3F, 1797 .rd_addr = R_AX_PTCL_DBG_INFO, 1798 .rd_byte = 4, 1799 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1800 }; 1801 1802 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1803 .sel_addr = R_AX_PTCL_DBG_C1, 1804 .sel_byte = 1, 1805 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1806 .srt = 0x00, 1807 .end = 0x3F, 1808 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1809 .rd_byte = 4, 1810 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1811 }; 1812 1813 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1814 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1815 .sel_byte = 2, 1816 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1817 .srt = 0x0, 1818 .end = 0xD, 1819 .rd_addr = R_AX_DBG_PORT_SEL, 1820 .rd_byte = 4, 1821 .rd_msk = B_AX_DEBUG_ST_MASK 1822 }; 1823 1824 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1825 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1826 .sel_byte = 2, 1827 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1828 .srt = 0x0, 1829 .end = 0x5, 1830 .rd_addr = R_AX_DBG_PORT_SEL, 1831 .rd_byte = 4, 1832 .rd_msk = B_AX_DEBUG_ST_MASK 1833 }; 1834 1835 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1836 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1837 .sel_byte = 2, 1838 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1839 .srt = 0x0, 1840 .end = 0x9, 1841 .rd_addr = R_AX_DBG_PORT_SEL, 1842 .rd_byte = 4, 1843 .rd_msk = B_AX_DEBUG_ST_MASK 1844 }; 1845 1846 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1847 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1848 .sel_byte = 2, 1849 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1850 .srt = 0x0, 1851 .end = 0x3, 1852 .rd_addr = R_AX_DBG_PORT_SEL, 1853 .rd_byte = 4, 1854 .rd_msk = B_AX_DEBUG_ST_MASK 1855 }; 1856 1857 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1858 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1859 .sel_byte = 2, 1860 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1861 .srt = 0x0, 1862 .end = 0x1, 1863 .rd_addr = R_AX_DBG_PORT_SEL, 1864 .rd_byte = 4, 1865 .rd_msk = B_AX_DEBUG_ST_MASK 1866 }; 1867 1868 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1869 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1870 .sel_byte = 2, 1871 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1872 .srt = 0x0, 1873 .end = 0x0, 1874 .rd_addr = R_AX_DBG_PORT_SEL, 1875 .rd_byte = 4, 1876 .rd_msk = B_AX_DEBUG_ST_MASK 1877 }; 1878 1879 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1880 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1881 .sel_byte = 2, 1882 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1883 .srt = 0x0, 1884 .end = 0xB, 1885 .rd_addr = R_AX_DBG_PORT_SEL, 1886 .rd_byte = 4, 1887 .rd_msk = B_AX_DEBUG_ST_MASK 1888 }; 1889 1890 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1891 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1892 .sel_byte = 2, 1893 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1894 .srt = 0x0, 1895 .end = 0x4, 1896 .rd_addr = R_AX_DBG_PORT_SEL, 1897 .rd_byte = 4, 1898 .rd_msk = B_AX_DEBUG_ST_MASK 1899 }; 1900 1901 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1902 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1903 .sel_byte = 2, 1904 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1905 .srt = 0x0, 1906 .end = 0x8, 1907 .rd_addr = R_AX_DBG_PORT_SEL, 1908 .rd_byte = 4, 1909 .rd_msk = B_AX_DEBUG_ST_MASK 1910 }; 1911 1912 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1913 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1914 .sel_byte = 2, 1915 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1916 .srt = 0x0, 1917 .end = 0x7, 1918 .rd_addr = R_AX_DBG_PORT_SEL, 1919 .rd_byte = 4, 1920 .rd_msk = B_AX_DEBUG_ST_MASK 1921 }; 1922 1923 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 1924 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1925 .sel_byte = 2, 1926 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1927 .srt = 0x0, 1928 .end = 0x1, 1929 .rd_addr = R_AX_DBG_PORT_SEL, 1930 .rd_byte = 4, 1931 .rd_msk = B_AX_DEBUG_ST_MASK 1932 }; 1933 1934 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 1935 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1936 .sel_byte = 2, 1937 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1938 .srt = 0x0, 1939 .end = 0x3, 1940 .rd_addr = R_AX_DBG_PORT_SEL, 1941 .rd_byte = 4, 1942 .rd_msk = B_AX_DEBUG_ST_MASK 1943 }; 1944 1945 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 1946 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1947 .sel_byte = 2, 1948 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1949 .srt = 0x0, 1950 .end = 0x0, 1951 .rd_addr = R_AX_DBG_PORT_SEL, 1952 .rd_byte = 4, 1953 .rd_msk = B_AX_DEBUG_ST_MASK 1954 }; 1955 1956 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 1957 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1958 .sel_byte = 2, 1959 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1960 .srt = 0x0, 1961 .end = 0x8, 1962 .rd_addr = R_AX_DBG_PORT_SEL, 1963 .rd_byte = 4, 1964 .rd_msk = B_AX_DEBUG_ST_MASK 1965 }; 1966 1967 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 1968 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1969 .sel_byte = 2, 1970 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1971 .srt = 0x0, 1972 .end = 0x0, 1973 .rd_addr = R_AX_DBG_PORT_SEL, 1974 .rd_byte = 4, 1975 .rd_msk = B_AX_DEBUG_ST_MASK 1976 }; 1977 1978 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 1979 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1980 .sel_byte = 2, 1981 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1982 .srt = 0x0, 1983 .end = 0x6, 1984 .rd_addr = R_AX_DBG_PORT_SEL, 1985 .rd_byte = 4, 1986 .rd_msk = B_AX_DEBUG_ST_MASK 1987 }; 1988 1989 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 1990 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1991 .sel_byte = 2, 1992 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1993 .srt = 0x0, 1994 .end = 0x0, 1995 .rd_addr = R_AX_DBG_PORT_SEL, 1996 .rd_byte = 4, 1997 .rd_msk = B_AX_DEBUG_ST_MASK 1998 }; 1999 2000 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 2001 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2002 .sel_byte = 2, 2003 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2004 .srt = 0x0, 2005 .end = 0x0, 2006 .rd_addr = R_AX_DBG_PORT_SEL, 2007 .rd_byte = 4, 2008 .rd_msk = B_AX_DEBUG_ST_MASK 2009 }; 2010 2011 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 2012 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2013 .sel_byte = 1, 2014 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2015 .srt = 0x0, 2016 .end = 0x3, 2017 .rd_addr = R_AX_DBG_PORT_SEL, 2018 .rd_byte = 4, 2019 .rd_msk = B_AX_DEBUG_ST_MASK 2020 }; 2021 2022 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 2023 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2024 .sel_byte = 1, 2025 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2026 .srt = 0x0, 2027 .end = 0x6, 2028 .rd_addr = R_AX_DBG_PORT_SEL, 2029 .rd_byte = 4, 2030 .rd_msk = B_AX_DEBUG_ST_MASK 2031 }; 2032 2033 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 2034 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2035 .sel_byte = 1, 2036 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2037 .srt = 0x0, 2038 .end = 0x0, 2039 .rd_addr = R_AX_DBG_PORT_SEL, 2040 .rd_byte = 4, 2041 .rd_msk = B_AX_DEBUG_ST_MASK 2042 }; 2043 2044 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 2045 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2046 .sel_byte = 1, 2047 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2048 .srt = 0x8, 2049 .end = 0xE, 2050 .rd_addr = R_AX_DBG_PORT_SEL, 2051 .rd_byte = 4, 2052 .rd_msk = B_AX_DEBUG_ST_MASK 2053 }; 2054 2055 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 2056 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2057 .sel_byte = 1, 2058 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2059 .srt = 0x0, 2060 .end = 0x5, 2061 .rd_addr = R_AX_DBG_PORT_SEL, 2062 .rd_byte = 4, 2063 .rd_msk = B_AX_DEBUG_ST_MASK 2064 }; 2065 2066 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 2067 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2068 .sel_byte = 1, 2069 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2070 .srt = 0x0, 2071 .end = 0x6, 2072 .rd_addr = R_AX_DBG_PORT_SEL, 2073 .rd_byte = 4, 2074 .rd_msk = B_AX_DEBUG_ST_MASK 2075 }; 2076 2077 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 2078 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2079 .sel_byte = 1, 2080 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2081 .srt = 0x0, 2082 .end = 0xF, 2083 .rd_addr = R_AX_DBG_PORT_SEL, 2084 .rd_byte = 4, 2085 .rd_msk = B_AX_DEBUG_ST_MASK 2086 }; 2087 2088 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 2089 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2090 .sel_byte = 1, 2091 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2092 .srt = 0x0, 2093 .end = 0x9, 2094 .rd_addr = R_AX_DBG_PORT_SEL, 2095 .rd_byte = 4, 2096 .rd_msk = B_AX_DEBUG_ST_MASK 2097 }; 2098 2099 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 2100 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2101 .sel_byte = 1, 2102 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2103 .srt = 0x0, 2104 .end = 0x3, 2105 .rd_addr = R_AX_DBG_PORT_SEL, 2106 .rd_byte = 4, 2107 .rd_msk = B_AX_DEBUG_ST_MASK 2108 }; 2109 2110 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 2111 .sel_addr = R_AX_SCH_DBG_SEL, 2112 .sel_byte = 1, 2113 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2114 .srt = 0x00, 2115 .end = 0x2F, 2116 .rd_addr = R_AX_SCH_DBG, 2117 .rd_byte = 4, 2118 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2119 }; 2120 2121 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 2122 .sel_addr = R_AX_SCH_DBG_SEL_C1, 2123 .sel_byte = 1, 2124 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2125 .srt = 0x00, 2126 .end = 0x2F, 2127 .rd_addr = R_AX_SCH_DBG_C1, 2128 .rd_byte = 4, 2129 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2130 }; 2131 2132 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 2133 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 2134 .sel_byte = 1, 2135 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2136 .srt = 0x00, 2137 .end = 0x19, 2138 .rd_addr = R_AX_DBG_PORT_SEL, 2139 .rd_byte = 4, 2140 .rd_msk = B_AX_DEBUG_ST_MASK 2141 }; 2142 2143 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 2144 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 2145 .sel_byte = 1, 2146 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2147 .srt = 0x00, 2148 .end = 0x19, 2149 .rd_addr = R_AX_DBG_PORT_SEL, 2150 .rd_byte = 4, 2151 .rd_msk = B_AX_DEBUG_ST_MASK 2152 }; 2153 2154 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 2155 .sel_addr = R_AX_RX_DEBUG_SELECT, 2156 .sel_byte = 1, 2157 .sel_msk = B_AX_DEBUG_SEL_MASK, 2158 .srt = 0x00, 2159 .end = 0x58, 2160 .rd_addr = R_AX_DBG_PORT_SEL, 2161 .rd_byte = 4, 2162 .rd_msk = B_AX_DEBUG_ST_MASK 2163 }; 2164 2165 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 2166 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 2167 .sel_byte = 1, 2168 .sel_msk = B_AX_DEBUG_SEL_MASK, 2169 .srt = 0x00, 2170 .end = 0x58, 2171 .rd_addr = R_AX_DBG_PORT_SEL, 2172 .rd_byte = 4, 2173 .rd_msk = B_AX_DEBUG_ST_MASK 2174 }; 2175 2176 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 2177 .sel_addr = R_AX_RX_STATE_MONITOR, 2178 .sel_byte = 1, 2179 .sel_msk = B_AX_STATE_SEL_MASK, 2180 .srt = 0x00, 2181 .end = 0x17, 2182 .rd_addr = R_AX_RX_STATE_MONITOR, 2183 .rd_byte = 4, 2184 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2185 }; 2186 2187 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 2188 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 2189 .sel_byte = 1, 2190 .sel_msk = B_AX_STATE_SEL_MASK, 2191 .srt = 0x00, 2192 .end = 0x17, 2193 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 2194 .rd_byte = 4, 2195 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2196 }; 2197 2198 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 2199 .sel_addr = R_AX_RMAC_PLCP_MON, 2200 .sel_byte = 4, 2201 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2202 .srt = 0x0, 2203 .end = 0xF, 2204 .rd_addr = R_AX_RMAC_PLCP_MON, 2205 .rd_byte = 4, 2206 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2207 }; 2208 2209 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 2210 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 2211 .sel_byte = 4, 2212 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2213 .srt = 0x0, 2214 .end = 0xF, 2215 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 2216 .rd_byte = 4, 2217 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2218 }; 2219 2220 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 2221 .sel_addr = R_AX_DBGSEL_TRXPTCL, 2222 .sel_byte = 1, 2223 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2224 .srt = 0x08, 2225 .end = 0x10, 2226 .rd_addr = R_AX_DBG_PORT_SEL, 2227 .rd_byte = 4, 2228 .rd_msk = B_AX_DEBUG_ST_MASK 2229 }; 2230 2231 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 2232 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 2233 .sel_byte = 1, 2234 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2235 .srt = 0x08, 2236 .end = 0x10, 2237 .rd_addr = R_AX_DBG_PORT_SEL, 2238 .rd_byte = 4, 2239 .rd_msk = B_AX_DEBUG_ST_MASK 2240 }; 2241 2242 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 2243 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2244 .sel_byte = 1, 2245 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2246 .srt = 0x00, 2247 .end = 0x07, 2248 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 2249 .rd_byte = 4, 2250 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2251 }; 2252 2253 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 2254 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2255 .sel_byte = 1, 2256 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2257 .srt = 0x00, 2258 .end = 0x07, 2259 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 2260 .rd_byte = 4, 2261 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2262 }; 2263 2264 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 2265 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2266 .sel_byte = 1, 2267 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2268 .srt = 0x00, 2269 .end = 0x07, 2270 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 2271 .rd_byte = 4, 2272 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2273 }; 2274 2275 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 2276 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2277 .sel_byte = 1, 2278 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2279 .srt = 0x00, 2280 .end = 0x07, 2281 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 2282 .rd_byte = 4, 2283 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2284 }; 2285 2286 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 2287 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2288 .sel_byte = 1, 2289 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2290 .srt = 0x00, 2291 .end = 0x04, 2292 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 2293 .rd_byte = 4, 2294 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2295 }; 2296 2297 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 2298 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2299 .sel_byte = 1, 2300 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2301 .srt = 0x00, 2302 .end = 0x04, 2303 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 2304 .rd_byte = 4, 2305 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2306 }; 2307 2308 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 2309 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2310 .sel_byte = 1, 2311 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2312 .srt = 0x00, 2313 .end = 0x04, 2314 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 2315 .rd_byte = 4, 2316 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2317 }; 2318 2319 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 2320 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2321 .sel_byte = 1, 2322 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2323 .srt = 0x00, 2324 .end = 0x04, 2325 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 2326 .rd_byte = 4, 2327 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2328 }; 2329 2330 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 2331 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2332 .sel_byte = 4, 2333 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2334 .srt = 0x80000000, 2335 .end = 0x80000001, 2336 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2337 .rd_byte = 4, 2338 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2339 }; 2340 2341 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 2342 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2343 .sel_byte = 4, 2344 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2345 .srt = 0x80010000, 2346 .end = 0x80010004, 2347 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2348 .rd_byte = 4, 2349 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2350 }; 2351 2352 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 2353 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2354 .sel_byte = 4, 2355 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2356 .srt = 0x80020000, 2357 .end = 0x80020FFF, 2358 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2359 .rd_byte = 4, 2360 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2361 }; 2362 2363 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 2364 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2365 .sel_byte = 4, 2366 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2367 .srt = 0x80030000, 2368 .end = 0x80030FFF, 2369 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2370 .rd_byte = 4, 2371 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2372 }; 2373 2374 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 2375 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2376 .sel_byte = 4, 2377 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2378 .srt = 0x80040000, 2379 .end = 0x80040FFF, 2380 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2381 .rd_byte = 4, 2382 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2383 }; 2384 2385 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 2386 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2387 .sel_byte = 4, 2388 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2389 .srt = 0x80050000, 2390 .end = 0x80050FFF, 2391 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2392 .rd_byte = 4, 2393 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2394 }; 2395 2396 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 2397 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2398 .sel_byte = 4, 2399 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2400 .srt = 0x80060000, 2401 .end = 0x80060453, 2402 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2403 .rd_byte = 4, 2404 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2405 }; 2406 2407 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 2408 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2409 .sel_byte = 4, 2410 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2411 .srt = 0x80070000, 2412 .end = 0x80070011, 2413 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2414 .rd_byte = 4, 2415 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2416 }; 2417 2418 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 2419 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2420 .sel_byte = 4, 2421 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2422 .srt = 0x80000000, 2423 .end = 0x80000001, 2424 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2425 .rd_byte = 4, 2426 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2427 }; 2428 2429 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 2430 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2431 .sel_byte = 4, 2432 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2433 .srt = 0x80010000, 2434 .end = 0x8001000A, 2435 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2436 .rd_byte = 4, 2437 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2438 }; 2439 2440 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2441 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2442 .sel_byte = 4, 2443 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2444 .srt = 0x80020000, 2445 .end = 0x80020DBF, 2446 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2447 .rd_byte = 4, 2448 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2449 }; 2450 2451 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2452 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2453 .sel_byte = 4, 2454 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2455 .srt = 0x80030000, 2456 .end = 0x80030DBF, 2457 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2458 .rd_byte = 4, 2459 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2460 }; 2461 2462 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2463 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2464 .sel_byte = 4, 2465 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2466 .srt = 0x80040000, 2467 .end = 0x80040DBF, 2468 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2469 .rd_byte = 4, 2470 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2471 }; 2472 2473 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2474 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2475 .sel_byte = 4, 2476 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2477 .srt = 0x80050000, 2478 .end = 0x80050DBF, 2479 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2480 .rd_byte = 4, 2481 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2482 }; 2483 2484 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2485 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2486 .sel_byte = 4, 2487 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2488 .srt = 0x80060000, 2489 .end = 0x80060041, 2490 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2491 .rd_byte = 4, 2492 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2493 }; 2494 2495 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2496 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2497 .sel_byte = 4, 2498 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2499 .srt = 0x80070000, 2500 .end = 0x80070001, 2501 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2502 .rd_byte = 4, 2503 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2504 }; 2505 2506 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2507 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2508 .sel_byte = 4, 2509 .sel_msk = B_AX_DFI_DATA_MASK, 2510 .srt = 0x80000000, 2511 .end = 0x8000017f, 2512 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2513 .rd_byte = 4, 2514 .rd_msk = B_AX_DFI_DATA_MASK 2515 }; 2516 2517 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2518 .sel_addr = R_AX_PCIE_DBG_CTRL, 2519 .sel_byte = 2, 2520 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2521 .srt = 0x00, 2522 .end = 0x03, 2523 .rd_addr = R_AX_DBG_PORT_SEL, 2524 .rd_byte = 4, 2525 .rd_msk = B_AX_DEBUG_ST_MASK 2526 }; 2527 2528 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2529 .sel_addr = R_AX_PCIE_DBG_CTRL, 2530 .sel_byte = 2, 2531 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2532 .srt = 0x00, 2533 .end = 0x04, 2534 .rd_addr = R_AX_DBG_PORT_SEL, 2535 .rd_byte = 4, 2536 .rd_msk = B_AX_DEBUG_ST_MASK 2537 }; 2538 2539 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2540 .sel_addr = R_AX_PCIE_DBG_CTRL, 2541 .sel_byte = 2, 2542 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2543 .srt = 0x00, 2544 .end = 0x01, 2545 .rd_addr = R_AX_DBG_PORT_SEL, 2546 .rd_byte = 4, 2547 .rd_msk = B_AX_DEBUG_ST_MASK 2548 }; 2549 2550 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2551 .sel_addr = R_AX_PCIE_DBG_CTRL, 2552 .sel_byte = 2, 2553 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2554 .srt = 0x00, 2555 .end = 0x05, 2556 .rd_addr = R_AX_DBG_PORT_SEL, 2557 .rd_byte = 4, 2558 .rd_msk = B_AX_DEBUG_ST_MASK 2559 }; 2560 2561 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2562 .sel_addr = R_AX_PCIE_DBG_CTRL, 2563 .sel_byte = 2, 2564 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2565 .srt = 0x00, 2566 .end = 0x05, 2567 .rd_addr = R_AX_DBG_PORT_SEL, 2568 .rd_byte = 4, 2569 .rd_msk = B_AX_DEBUG_ST_MASK 2570 }; 2571 2572 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2573 .sel_addr = R_AX_PCIE_DBG_CTRL, 2574 .sel_byte = 2, 2575 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2576 .srt = 0x00, 2577 .end = 0x06, 2578 .rd_addr = R_AX_DBG_PORT_SEL, 2579 .rd_byte = 4, 2580 .rd_msk = B_AX_DEBUG_ST_MASK 2581 }; 2582 2583 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2584 .sel_addr = R_AX_DBG_CTRL, 2585 .sel_byte = 1, 2586 .sel_msk = B_AX_DBG_SEL0, 2587 .srt = 0x34, 2588 .end = 0x3C, 2589 .rd_addr = R_AX_DBG_PORT_SEL, 2590 .rd_byte = 4, 2591 .rd_msk = B_AX_DEBUG_ST_MASK 2592 }; 2593 2594 static int 2595 rtw89_debug_mac_dbg_port_sel(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 2596 u32 sel, const struct rtw89_mac_dbg_port_info **ppinfo) 2597 { 2598 const struct rtw89_mac_dbg_port_info *info = NULL; 2599 char *p = buf, *end = buf + bufsz; 2600 u32 index; 2601 u32 val32; 2602 u16 val16; 2603 u8 val8; 2604 2605 switch (sel) { 2606 case RTW89_DBG_PORT_SEL_PTCL_C0: 2607 info = &dbg_port_ptcl_c0; 2608 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2609 val16 |= B_AX_PTCL_DBG_EN; 2610 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2611 p += scnprintf(p, end - p, "Enable PTCL C0 dbgport.\n"); 2612 break; 2613 case RTW89_DBG_PORT_SEL_PTCL_C1: 2614 info = &dbg_port_ptcl_c1; 2615 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2616 val16 |= B_AX_PTCL_DBG_EN; 2617 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2618 p += scnprintf(p, end - p, "Enable PTCL C1 dbgport.\n"); 2619 break; 2620 case RTW89_DBG_PORT_SEL_SCH_C0: 2621 info = &dbg_port_sch_c0; 2622 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2623 val32 |= B_AX_SCH_DBG_EN; 2624 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2625 p += scnprintf(p, end - p, "Enable SCH C0 dbgport.\n"); 2626 break; 2627 case RTW89_DBG_PORT_SEL_SCH_C1: 2628 info = &dbg_port_sch_c1; 2629 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2630 val32 |= B_AX_SCH_DBG_EN; 2631 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2632 p += scnprintf(p, end - p, "Enable SCH C1 dbgport.\n"); 2633 break; 2634 case RTW89_DBG_PORT_SEL_TMAC_C0: 2635 info = &dbg_port_tmac_c0; 2636 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2637 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2638 B_AX_DBGSEL_TRXPTCL_MASK); 2639 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2640 2641 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2642 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2643 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2644 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2645 2646 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2647 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2648 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2649 p += scnprintf(p, end - p, "Enable TMAC C0 dbgport.\n"); 2650 break; 2651 case RTW89_DBG_PORT_SEL_TMAC_C1: 2652 info = &dbg_port_tmac_c1; 2653 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2654 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2655 B_AX_DBGSEL_TRXPTCL_MASK); 2656 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2657 2658 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2659 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2660 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2661 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2662 2663 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2664 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2665 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2666 p += scnprintf(p, end - p, "Enable TMAC C1 dbgport.\n"); 2667 break; 2668 case RTW89_DBG_PORT_SEL_RMAC_C0: 2669 info = &dbg_port_rmac_c0; 2670 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2671 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2672 B_AX_DBGSEL_TRXPTCL_MASK); 2673 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2674 2675 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2676 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2677 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2678 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2679 2680 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2681 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2682 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2683 2684 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2685 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2686 B_AX_DBGSEL_TRXPTCL_MASK); 2687 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2688 p += scnprintf(p, end - p, "Enable RMAC C0 dbgport.\n"); 2689 break; 2690 case RTW89_DBG_PORT_SEL_RMAC_C1: 2691 info = &dbg_port_rmac_c1; 2692 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2693 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2694 B_AX_DBGSEL_TRXPTCL_MASK); 2695 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2696 2697 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2698 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2699 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2700 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2701 2702 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2703 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2704 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2705 2706 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2707 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2708 B_AX_DBGSEL_TRXPTCL_MASK); 2709 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2710 p += scnprintf(p, end - p, "Enable RMAC C1 dbgport.\n"); 2711 break; 2712 case RTW89_DBG_PORT_SEL_RMACST_C0: 2713 info = &dbg_port_rmacst_c0; 2714 p += scnprintf(p, end - p, "Enable RMAC state C0 dbgport.\n"); 2715 break; 2716 case RTW89_DBG_PORT_SEL_RMACST_C1: 2717 info = &dbg_port_rmacst_c1; 2718 p += scnprintf(p, end - p, "Enable RMAC state C1 dbgport.\n"); 2719 break; 2720 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2721 info = &dbg_port_rmac_plcp_c0; 2722 p += scnprintf(p, end - p, "Enable RMAC PLCP C0 dbgport.\n"); 2723 break; 2724 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2725 info = &dbg_port_rmac_plcp_c1; 2726 p += scnprintf(p, end - p, "Enable RMAC PLCP C1 dbgport.\n"); 2727 break; 2728 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2729 info = &dbg_port_trxptcl_c0; 2730 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2731 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2732 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2733 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2734 2735 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2736 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2737 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2738 p += scnprintf(p, end - p, "Enable TRXPTCL C0 dbgport.\n"); 2739 break; 2740 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2741 info = &dbg_port_trxptcl_c1; 2742 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2743 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2744 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2745 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2746 2747 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2748 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2749 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2750 p += scnprintf(p, end - p, "Enable TRXPTCL C1 dbgport.\n"); 2751 break; 2752 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2753 info = &dbg_port_tx_infol_c0; 2754 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2755 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2756 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2757 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2758 break; 2759 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2760 info = &dbg_port_tx_infoh_c0; 2761 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2762 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2763 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2764 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2765 break; 2766 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2767 info = &dbg_port_tx_infol_c1; 2768 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2769 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2770 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2771 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2772 break; 2773 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2774 info = &dbg_port_tx_infoh_c1; 2775 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2776 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2777 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2778 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2779 break; 2780 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2781 info = &dbg_port_txtf_infol_c0; 2782 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2783 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2784 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2785 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2786 break; 2787 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2788 info = &dbg_port_txtf_infoh_c0; 2789 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2790 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2791 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2792 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2793 break; 2794 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2795 info = &dbg_port_txtf_infol_c1; 2796 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2797 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2798 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2799 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2800 break; 2801 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2802 info = &dbg_port_txtf_infoh_c1; 2803 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2804 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2805 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2806 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2807 break; 2808 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2809 info = &dbg_port_wde_bufmgn_freepg; 2810 p += scnprintf(p, end - p, "Enable wde bufmgn freepg dump.\n"); 2811 break; 2812 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2813 info = &dbg_port_wde_bufmgn_quota; 2814 p += scnprintf(p, end - p, "Enable wde bufmgn quota dump.\n"); 2815 break; 2816 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2817 info = &dbg_port_wde_bufmgn_pagellt; 2818 p += scnprintf(p, end - p, 2819 "Enable wde bufmgn pagellt dump.\n"); 2820 break; 2821 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2822 info = &dbg_port_wde_bufmgn_pktinfo; 2823 p += scnprintf(p, end - p, 2824 "Enable wde bufmgn pktinfo dump.\n"); 2825 break; 2826 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2827 info = &dbg_port_wde_quemgn_prepkt; 2828 p += scnprintf(p, end - p, "Enable wde quemgn prepkt dump.\n"); 2829 break; 2830 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2831 info = &dbg_port_wde_quemgn_nxtpkt; 2832 p += scnprintf(p, end - p, "Enable wde quemgn nxtpkt dump.\n"); 2833 break; 2834 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2835 info = &dbg_port_wde_quemgn_qlnktbl; 2836 p += scnprintf(p, end - p, 2837 "Enable wde quemgn qlnktbl dump.\n"); 2838 break; 2839 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2840 info = &dbg_port_wde_quemgn_qempty; 2841 p += scnprintf(p, end - p, "Enable wde quemgn qempty dump.\n"); 2842 break; 2843 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2844 info = &dbg_port_ple_bufmgn_freepg; 2845 p += scnprintf(p, end - p, "Enable ple bufmgn freepg dump.\n"); 2846 break; 2847 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2848 info = &dbg_port_ple_bufmgn_quota; 2849 p += scnprintf(p, end - p, "Enable ple bufmgn quota dump.\n"); 2850 break; 2851 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2852 info = &dbg_port_ple_bufmgn_pagellt; 2853 p += scnprintf(p, end - p, 2854 "Enable ple bufmgn pagellt dump.\n"); 2855 break; 2856 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2857 info = &dbg_port_ple_bufmgn_pktinfo; 2858 p += scnprintf(p, end - p, 2859 "Enable ple bufmgn pktinfo dump.\n"); 2860 break; 2861 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2862 info = &dbg_port_ple_quemgn_prepkt; 2863 p += scnprintf(p, end - p, "Enable ple quemgn prepkt dump.\n"); 2864 break; 2865 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2866 info = &dbg_port_ple_quemgn_nxtpkt; 2867 p += scnprintf(p, end - p, "Enable ple quemgn nxtpkt dump.\n"); 2868 break; 2869 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2870 info = &dbg_port_ple_quemgn_qlnktbl; 2871 p += scnprintf(p, end - p, 2872 "Enable ple quemgn qlnktbl dump.\n"); 2873 break; 2874 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2875 info = &dbg_port_ple_quemgn_qempty; 2876 p += scnprintf(p, end - p, "Enable ple quemgn qempty dump.\n"); 2877 break; 2878 case RTW89_DBG_PORT_SEL_PKTINFO: 2879 info = &dbg_port_pktinfo; 2880 p += scnprintf(p, end - p, "Enable pktinfo dump.\n"); 2881 break; 2882 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2883 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2884 B_AX_DBG_SEL0, 0x80); 2885 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2886 B_AX_SEL_0XC0_MASK, 1); 2887 fallthrough; 2888 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2889 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2890 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2891 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2892 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2893 info = &dbg_port_dspt_hdt_tx0_5; 2894 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2895 rtw89_write16_mask(rtwdev, info->sel_addr, 2896 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2897 rtw89_write16_mask(rtwdev, info->sel_addr, 2898 B_AX_DISPATCHER_CH_SEL_MASK, index); 2899 p += scnprintf(p, end - p, 2900 "Enable Dispatcher hdt tx%x dump.\n", index); 2901 break; 2902 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2903 info = &dbg_port_dspt_hdt_tx6; 2904 rtw89_write16_mask(rtwdev, info->sel_addr, 2905 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2906 rtw89_write16_mask(rtwdev, info->sel_addr, 2907 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2908 p += scnprintf(p, end - p, 2909 "Enable Dispatcher hdt tx6 dump.\n"); 2910 break; 2911 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2912 info = &dbg_port_dspt_hdt_tx7; 2913 rtw89_write16_mask(rtwdev, info->sel_addr, 2914 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2915 rtw89_write16_mask(rtwdev, info->sel_addr, 2916 B_AX_DISPATCHER_CH_SEL_MASK, 7); 2917 p += scnprintf(p, end - p, 2918 "Enable Dispatcher hdt tx7 dump.\n"); 2919 break; 2920 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 2921 info = &dbg_port_dspt_hdt_tx8; 2922 rtw89_write16_mask(rtwdev, info->sel_addr, 2923 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2924 rtw89_write16_mask(rtwdev, info->sel_addr, 2925 B_AX_DISPATCHER_CH_SEL_MASK, 8); 2926 p += scnprintf(p, end - p, 2927 "Enable Dispatcher hdt tx8 dump.\n"); 2928 break; 2929 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 2930 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 2931 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 2932 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 2933 info = &dbg_port_dspt_hdt_tx9_C; 2934 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 2935 rtw89_write16_mask(rtwdev, info->sel_addr, 2936 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2937 rtw89_write16_mask(rtwdev, info->sel_addr, 2938 B_AX_DISPATCHER_CH_SEL_MASK, index); 2939 p += scnprintf(p, end - p, 2940 "Enable Dispatcher hdt tx%x dump.\n", index); 2941 break; 2942 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 2943 info = &dbg_port_dspt_hdt_txD; 2944 rtw89_write16_mask(rtwdev, info->sel_addr, 2945 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2946 rtw89_write16_mask(rtwdev, info->sel_addr, 2947 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 2948 p += scnprintf(p, end - p, 2949 "Enable Dispatcher hdt txD dump.\n"); 2950 break; 2951 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 2952 info = &dbg_port_dspt_cdt_tx0; 2953 rtw89_write16_mask(rtwdev, info->sel_addr, 2954 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2955 rtw89_write16_mask(rtwdev, info->sel_addr, 2956 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2957 p += scnprintf(p, end - p, 2958 "Enable Dispatcher cdt tx0 dump.\n"); 2959 break; 2960 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 2961 info = &dbg_port_dspt_cdt_tx1; 2962 rtw89_write16_mask(rtwdev, info->sel_addr, 2963 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2964 rtw89_write16_mask(rtwdev, info->sel_addr, 2965 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2966 p += scnprintf(p, end - p, 2967 "Enable Dispatcher cdt tx1 dump.\n"); 2968 break; 2969 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 2970 info = &dbg_port_dspt_cdt_tx3; 2971 rtw89_write16_mask(rtwdev, info->sel_addr, 2972 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2973 rtw89_write16_mask(rtwdev, info->sel_addr, 2974 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2975 p += scnprintf(p, end - p, 2976 "Enable Dispatcher cdt tx3 dump.\n"); 2977 break; 2978 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 2979 info = &dbg_port_dspt_cdt_tx4; 2980 rtw89_write16_mask(rtwdev, info->sel_addr, 2981 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2982 rtw89_write16_mask(rtwdev, info->sel_addr, 2983 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2984 p += scnprintf(p, end - p, 2985 "Enable Dispatcher cdt tx4 dump.\n"); 2986 break; 2987 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 2988 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 2989 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 2990 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 2991 info = &dbg_port_dspt_cdt_tx5_8; 2992 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 2993 rtw89_write16_mask(rtwdev, info->sel_addr, 2994 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2995 rtw89_write16_mask(rtwdev, info->sel_addr, 2996 B_AX_DISPATCHER_CH_SEL_MASK, index); 2997 p += scnprintf(p, end - p, 2998 "Enable Dispatcher cdt tx%x dump.\n", index); 2999 break; 3000 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 3001 info = &dbg_port_dspt_cdt_tx9; 3002 rtw89_write16_mask(rtwdev, info->sel_addr, 3003 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3004 rtw89_write16_mask(rtwdev, info->sel_addr, 3005 B_AX_DISPATCHER_CH_SEL_MASK, 9); 3006 p += scnprintf(p, end - p, 3007 "Enable Dispatcher cdt tx9 dump.\n"); 3008 break; 3009 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 3010 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 3011 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 3012 info = &dbg_port_dspt_cdt_txA_C; 3013 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 3014 rtw89_write16_mask(rtwdev, info->sel_addr, 3015 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3016 rtw89_write16_mask(rtwdev, info->sel_addr, 3017 B_AX_DISPATCHER_CH_SEL_MASK, index); 3018 p += scnprintf(p, end - p, 3019 "Enable Dispatcher cdt tx%x dump.\n", index); 3020 break; 3021 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 3022 info = &dbg_port_dspt_hdt_rx0; 3023 rtw89_write16_mask(rtwdev, info->sel_addr, 3024 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3025 rtw89_write16_mask(rtwdev, info->sel_addr, 3026 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3027 p += scnprintf(p, end - p, 3028 "Enable Dispatcher hdt rx0 dump.\n"); 3029 break; 3030 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 3031 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 3032 info = &dbg_port_dspt_hdt_rx1_2; 3033 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 3034 rtw89_write16_mask(rtwdev, info->sel_addr, 3035 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3036 rtw89_write16_mask(rtwdev, info->sel_addr, 3037 B_AX_DISPATCHER_CH_SEL_MASK, index); 3038 p += scnprintf(p, end - p, 3039 "Enable Dispatcher hdt rx%x dump.\n", index); 3040 break; 3041 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 3042 info = &dbg_port_dspt_hdt_rx3; 3043 rtw89_write16_mask(rtwdev, info->sel_addr, 3044 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3045 rtw89_write16_mask(rtwdev, info->sel_addr, 3046 B_AX_DISPATCHER_CH_SEL_MASK, 3); 3047 p += scnprintf(p, end - p, 3048 "Enable Dispatcher hdt rx3 dump.\n"); 3049 break; 3050 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 3051 info = &dbg_port_dspt_hdt_rx4; 3052 rtw89_write16_mask(rtwdev, info->sel_addr, 3053 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3054 rtw89_write16_mask(rtwdev, info->sel_addr, 3055 B_AX_DISPATCHER_CH_SEL_MASK, 4); 3056 p += scnprintf(p, end - p, 3057 "Enable Dispatcher hdt rx4 dump.\n"); 3058 break; 3059 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 3060 info = &dbg_port_dspt_hdt_rx5; 3061 rtw89_write16_mask(rtwdev, info->sel_addr, 3062 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3063 rtw89_write16_mask(rtwdev, info->sel_addr, 3064 B_AX_DISPATCHER_CH_SEL_MASK, 5); 3065 p += scnprintf(p, end - p, 3066 "Enable Dispatcher hdt rx5 dump.\n"); 3067 break; 3068 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 3069 info = &dbg_port_dspt_cdt_rx_p0_0; 3070 rtw89_write16_mask(rtwdev, info->sel_addr, 3071 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3072 rtw89_write16_mask(rtwdev, info->sel_addr, 3073 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3074 p += scnprintf(p, end - p, 3075 "Enable Dispatcher cdt rx part0 0 dump.\n"); 3076 break; 3077 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 3078 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 3079 info = &dbg_port_dspt_cdt_rx_p0_1; 3080 rtw89_write16_mask(rtwdev, info->sel_addr, 3081 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3082 rtw89_write16_mask(rtwdev, info->sel_addr, 3083 B_AX_DISPATCHER_CH_SEL_MASK, 1); 3084 p += scnprintf(p, end - p, 3085 "Enable Dispatcher cdt rx part0 1 dump.\n"); 3086 break; 3087 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 3088 info = &dbg_port_dspt_cdt_rx_p0_2; 3089 rtw89_write16_mask(rtwdev, info->sel_addr, 3090 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3091 rtw89_write16_mask(rtwdev, info->sel_addr, 3092 B_AX_DISPATCHER_CH_SEL_MASK, 2); 3093 p += scnprintf(p, end - p, 3094 "Enable Dispatcher cdt rx part0 2 dump.\n"); 3095 break; 3096 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 3097 info = &dbg_port_dspt_cdt_rx_p1; 3098 rtw89_write8_mask(rtwdev, info->sel_addr, 3099 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3100 p += scnprintf(p, end - p, 3101 "Enable Dispatcher cdt rx part1 dump.\n"); 3102 break; 3103 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 3104 info = &dbg_port_dspt_stf_ctrl; 3105 rtw89_write8_mask(rtwdev, info->sel_addr, 3106 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 3107 p += scnprintf(p, end - p, 3108 "Enable Dispatcher stf control dump.\n"); 3109 break; 3110 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 3111 info = &dbg_port_dspt_addr_ctrl; 3112 rtw89_write8_mask(rtwdev, info->sel_addr, 3113 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 3114 p += scnprintf(p, end - p, 3115 "Enable Dispatcher addr control dump.\n"); 3116 break; 3117 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 3118 info = &dbg_port_dspt_wde_intf; 3119 rtw89_write8_mask(rtwdev, info->sel_addr, 3120 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 3121 p += scnprintf(p, end - p, 3122 "Enable Dispatcher wde interface dump.\n"); 3123 break; 3124 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 3125 info = &dbg_port_dspt_ple_intf; 3126 rtw89_write8_mask(rtwdev, info->sel_addr, 3127 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 3128 p += scnprintf(p, end - p, 3129 "Enable Dispatcher ple interface dump.\n"); 3130 break; 3131 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 3132 info = &dbg_port_dspt_flow_ctrl; 3133 rtw89_write8_mask(rtwdev, info->sel_addr, 3134 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 3135 p += scnprintf(p, end - p, 3136 "Enable Dispatcher flow control dump.\n"); 3137 break; 3138 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 3139 info = &dbg_port_pcie_txdma; 3140 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3141 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 3142 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 3143 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3144 p += scnprintf(p, end - p, "Enable pcie txdma dump.\n"); 3145 break; 3146 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 3147 info = &dbg_port_pcie_rxdma; 3148 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3149 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 3150 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 3151 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3152 p += scnprintf(p, end - p, "Enable pcie rxdma dump.\n"); 3153 break; 3154 case RTW89_DBG_PORT_SEL_PCIE_CVT: 3155 info = &dbg_port_pcie_cvt; 3156 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3157 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 3158 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 3159 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3160 p += scnprintf(p, end - p, "Enable pcie cvt dump.\n"); 3161 break; 3162 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 3163 info = &dbg_port_pcie_cxpl; 3164 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3165 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 3166 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 3167 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3168 p += scnprintf(p, end - p, "Enable pcie cxpl dump.\n"); 3169 break; 3170 case RTW89_DBG_PORT_SEL_PCIE_IO: 3171 info = &dbg_port_pcie_io; 3172 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3173 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 3174 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 3175 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3176 p += scnprintf(p, end - p, "Enable pcie io dump.\n"); 3177 break; 3178 case RTW89_DBG_PORT_SEL_PCIE_MISC: 3179 info = &dbg_port_pcie_misc; 3180 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3181 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 3182 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 3183 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3184 p += scnprintf(p, end - p, "Enable pcie misc dump.\n"); 3185 break; 3186 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 3187 info = &dbg_port_pcie_misc2; 3188 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 3189 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 3190 B_AX_PCIE_DBG_SEL_MASK); 3191 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 3192 p += scnprintf(p, end - p, "Enable pcie misc2 dump.\n"); 3193 break; 3194 default: 3195 p += scnprintf(p, end - p, "Dbg port select err\n"); 3196 break; 3197 } 3198 3199 *ppinfo = info; 3200 3201 return p - buf; 3202 } 3203 3204 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 3205 { 3206 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 3207 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 3208 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 3209 return false; 3210 if (rtw89_is_rtl885xb(rtwdev) && 3211 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3212 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3213 return false; 3214 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3215 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 3216 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 3217 return false; 3218 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3219 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 3220 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 3221 return false; 3222 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 3223 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 3224 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 3225 return false; 3226 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 3227 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3228 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3229 return false; 3230 3231 return true; 3232 } 3233 3234 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 3235 char *buf, size_t bufsz, u32 sel) 3236 { 3237 const struct rtw89_mac_dbg_port_info *info = NULL; 3238 char *p = buf, *end = buf + bufsz; 3239 u32 val32; 3240 u16 val16; 3241 u8 val8; 3242 u32 i; 3243 3244 p += rtw89_debug_mac_dbg_port_sel(rtwdev, p, end - p, sel, &info); 3245 3246 if (!info) { 3247 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 3248 goto out; 3249 } 3250 3251 #define case_DBG_SEL(__sel) \ 3252 case RTW89_DBG_PORT_SEL_##__sel: \ 3253 p += scnprintf(p, end - p, "Dump debug port " #__sel ":\n"); \ 3254 break 3255 3256 switch (sel) { 3257 case_DBG_SEL(PTCL_C0); 3258 case_DBG_SEL(PTCL_C1); 3259 case_DBG_SEL(SCH_C0); 3260 case_DBG_SEL(SCH_C1); 3261 case_DBG_SEL(TMAC_C0); 3262 case_DBG_SEL(TMAC_C1); 3263 case_DBG_SEL(RMAC_C0); 3264 case_DBG_SEL(RMAC_C1); 3265 case_DBG_SEL(RMACST_C0); 3266 case_DBG_SEL(RMACST_C1); 3267 case_DBG_SEL(TRXPTCL_C0); 3268 case_DBG_SEL(TRXPTCL_C1); 3269 case_DBG_SEL(TX_INFOL_C0); 3270 case_DBG_SEL(TX_INFOH_C0); 3271 case_DBG_SEL(TX_INFOL_C1); 3272 case_DBG_SEL(TX_INFOH_C1); 3273 case_DBG_SEL(TXTF_INFOL_C0); 3274 case_DBG_SEL(TXTF_INFOH_C0); 3275 case_DBG_SEL(TXTF_INFOL_C1); 3276 case_DBG_SEL(TXTF_INFOH_C1); 3277 case_DBG_SEL(WDE_BUFMGN_FREEPG); 3278 case_DBG_SEL(WDE_BUFMGN_QUOTA); 3279 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 3280 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 3281 case_DBG_SEL(WDE_QUEMGN_PREPKT); 3282 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 3283 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 3284 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 3285 case_DBG_SEL(PLE_BUFMGN_FREEPG); 3286 case_DBG_SEL(PLE_BUFMGN_QUOTA); 3287 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 3288 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 3289 case_DBG_SEL(PLE_QUEMGN_PREPKT); 3290 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 3291 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 3292 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 3293 case_DBG_SEL(PKTINFO); 3294 case_DBG_SEL(DSPT_HDT_TX0); 3295 case_DBG_SEL(DSPT_HDT_TX1); 3296 case_DBG_SEL(DSPT_HDT_TX2); 3297 case_DBG_SEL(DSPT_HDT_TX3); 3298 case_DBG_SEL(DSPT_HDT_TX4); 3299 case_DBG_SEL(DSPT_HDT_TX5); 3300 case_DBG_SEL(DSPT_HDT_TX6); 3301 case_DBG_SEL(DSPT_HDT_TX7); 3302 case_DBG_SEL(DSPT_HDT_TX8); 3303 case_DBG_SEL(DSPT_HDT_TX9); 3304 case_DBG_SEL(DSPT_HDT_TXA); 3305 case_DBG_SEL(DSPT_HDT_TXB); 3306 case_DBG_SEL(DSPT_HDT_TXC); 3307 case_DBG_SEL(DSPT_HDT_TXD); 3308 case_DBG_SEL(DSPT_HDT_TXE); 3309 case_DBG_SEL(DSPT_HDT_TXF); 3310 case_DBG_SEL(DSPT_CDT_TX0); 3311 case_DBG_SEL(DSPT_CDT_TX1); 3312 case_DBG_SEL(DSPT_CDT_TX3); 3313 case_DBG_SEL(DSPT_CDT_TX4); 3314 case_DBG_SEL(DSPT_CDT_TX5); 3315 case_DBG_SEL(DSPT_CDT_TX6); 3316 case_DBG_SEL(DSPT_CDT_TX7); 3317 case_DBG_SEL(DSPT_CDT_TX8); 3318 case_DBG_SEL(DSPT_CDT_TX9); 3319 case_DBG_SEL(DSPT_CDT_TXA); 3320 case_DBG_SEL(DSPT_CDT_TXB); 3321 case_DBG_SEL(DSPT_CDT_TXC); 3322 case_DBG_SEL(DSPT_HDT_RX0); 3323 case_DBG_SEL(DSPT_HDT_RX1); 3324 case_DBG_SEL(DSPT_HDT_RX2); 3325 case_DBG_SEL(DSPT_HDT_RX3); 3326 case_DBG_SEL(DSPT_HDT_RX4); 3327 case_DBG_SEL(DSPT_HDT_RX5); 3328 case_DBG_SEL(DSPT_CDT_RX_P0); 3329 case_DBG_SEL(DSPT_CDT_RX_P0_0); 3330 case_DBG_SEL(DSPT_CDT_RX_P0_1); 3331 case_DBG_SEL(DSPT_CDT_RX_P0_2); 3332 case_DBG_SEL(DSPT_CDT_RX_P1); 3333 case_DBG_SEL(DSPT_STF_CTRL); 3334 case_DBG_SEL(DSPT_ADDR_CTRL); 3335 case_DBG_SEL(DSPT_WDE_INTF); 3336 case_DBG_SEL(DSPT_PLE_INTF); 3337 case_DBG_SEL(DSPT_FLOW_CTRL); 3338 case_DBG_SEL(PCIE_TXDMA); 3339 case_DBG_SEL(PCIE_RXDMA); 3340 case_DBG_SEL(PCIE_CVT); 3341 case_DBG_SEL(PCIE_CXPL); 3342 case_DBG_SEL(PCIE_IO); 3343 case_DBG_SEL(PCIE_MISC); 3344 case_DBG_SEL(PCIE_MISC2); 3345 } 3346 3347 #undef case_DBG_SEL 3348 3349 p += scnprintf(p, end - p, "Sel addr = 0x%X\n", info->sel_addr); 3350 p += scnprintf(p, end - p, "Read addr = 0x%X\n", info->rd_addr); 3351 3352 for (i = info->srt; i <= info->end; i++) { 3353 switch (info->sel_byte) { 3354 case 1: 3355 default: 3356 rtw89_write8_mask(rtwdev, info->sel_addr, 3357 info->sel_msk, i); 3358 p += scnprintf(p, end - p, "0x%02X: ", i); 3359 break; 3360 case 2: 3361 rtw89_write16_mask(rtwdev, info->sel_addr, 3362 info->sel_msk, i); 3363 p += scnprintf(p, end - p, "0x%04X: ", i); 3364 break; 3365 case 4: 3366 rtw89_write32_mask(rtwdev, info->sel_addr, 3367 info->sel_msk, i); 3368 p += scnprintf(p, end - p, "0x%04X: ", i); 3369 break; 3370 } 3371 3372 udelay(10); 3373 3374 switch (info->rd_byte) { 3375 case 1: 3376 default: 3377 val8 = rtw89_read8_mask(rtwdev, 3378 info->rd_addr, info->rd_msk); 3379 p += scnprintf(p, end - p, "0x%02X\n", val8); 3380 break; 3381 case 2: 3382 val16 = rtw89_read16_mask(rtwdev, 3383 info->rd_addr, info->rd_msk); 3384 p += scnprintf(p, end - p, "0x%04X\n", val16); 3385 break; 3386 case 4: 3387 val32 = rtw89_read32_mask(rtwdev, 3388 info->rd_addr, info->rd_msk); 3389 p += scnprintf(p, end - p, "0x%08X\n", val32); 3390 break; 3391 } 3392 } 3393 3394 out: 3395 return p - buf; 3396 } 3397 3398 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 3399 char *buf, size_t bufsz) 3400 { 3401 char *p = buf, *end = buf + bufsz; 3402 ssize_t n; 3403 u32 sel; 3404 3405 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 3406 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 3407 if (!is_dbg_port_valid(rtwdev, sel)) 3408 continue; 3409 n = rtw89_debug_mac_dbg_port_dump(rtwdev, p, end - p, sel); 3410 if (n < 0) { 3411 rtw89_err(rtwdev, 3412 "failed to dump debug port %d\n", sel); 3413 break; 3414 } 3415 p += n; 3416 } 3417 3418 return p - buf; 3419 } 3420 3421 static ssize_t 3422 rtw89_debug_priv_mac_dbg_port_dump_get(struct rtw89_dev *rtwdev, 3423 struct rtw89_debugfs_priv *debugfs_priv, 3424 char *buf, size_t bufsz) 3425 { 3426 char *p = buf, *end = buf + bufsz; 3427 3428 if (debugfs_priv->dbgpkg_en.ss_dbg) 3429 p += rtw89_debug_mac_dump_ss_dbg(rtwdev, p, end - p); 3430 if (debugfs_priv->dbgpkg_en.dle_dbg) 3431 p += rtw89_debug_mac_dump_dle_dbg(rtwdev, p, end - p); 3432 if (debugfs_priv->dbgpkg_en.dmac_dbg) 3433 p += rtw89_debug_mac_dump_dmac_dbg(rtwdev, p, end - p); 3434 if (debugfs_priv->dbgpkg_en.cmac_dbg) 3435 p += rtw89_debug_mac_dump_cmac_dbg(rtwdev, p, end - p); 3436 if (debugfs_priv->dbgpkg_en.dbg_port) 3437 p += rtw89_debug_mac_dump_dbg_port(rtwdev, p, end - p); 3438 3439 return p - buf; 3440 }; 3441 3442 static u8 *rtw89_hex2bin(struct rtw89_dev *rtwdev, const char *buf, size_t count) 3443 { 3444 u8 *bin; 3445 int num; 3446 int err = 0; 3447 3448 num = count / 2; 3449 bin = kmalloc(num, GFP_KERNEL); 3450 if (!bin) { 3451 err = -EFAULT; 3452 goto out; 3453 } 3454 3455 if (hex2bin(bin, buf, num)) { 3456 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 3457 kfree(bin); 3458 err = -EINVAL; 3459 } 3460 3461 out: 3462 return err ? ERR_PTR(err) : bin; 3463 } 3464 3465 static ssize_t rtw89_debug_priv_send_h2c_set(struct rtw89_dev *rtwdev, 3466 struct rtw89_debugfs_priv *debugfs_priv, 3467 const char *buf, size_t count) 3468 { 3469 u8 *h2c; 3470 int ret; 3471 u16 h2c_len = count / 2; 3472 3473 h2c = rtw89_hex2bin(rtwdev, buf, count); 3474 if (IS_ERR(h2c)) 3475 return -EFAULT; 3476 3477 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3478 3479 kfree(h2c); 3480 3481 return ret ? ret : count; 3482 } 3483 3484 static ssize_t 3485 rtw89_debug_priv_early_h2c_get(struct rtw89_dev *rtwdev, 3486 struct rtw89_debugfs_priv *debugfs_priv, 3487 char *buf, size_t bufsz) 3488 { 3489 struct rtw89_early_h2c *early_h2c; 3490 char *p = buf, *end = buf + bufsz; 3491 int seq = 0; 3492 3493 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3494 3495 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3496 p += scnprintf(p, end - p, "%d: %*ph\n", ++seq, 3497 early_h2c->h2c_len, early_h2c->h2c); 3498 3499 return p - buf; 3500 } 3501 3502 static ssize_t 3503 rtw89_debug_priv_early_h2c_set(struct rtw89_dev *rtwdev, 3504 struct rtw89_debugfs_priv *debugfs_priv, 3505 const char *buf, size_t count) 3506 { 3507 struct rtw89_early_h2c *early_h2c; 3508 u8 *h2c; 3509 u16 h2c_len = count / 2; 3510 3511 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3512 3513 h2c = rtw89_hex2bin(rtwdev, buf, count); 3514 if (IS_ERR(h2c)) 3515 return -EFAULT; 3516 3517 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3518 kfree(h2c); 3519 rtw89_fw_free_all_early_h2c(rtwdev); 3520 goto out; 3521 } 3522 3523 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 3524 if (!early_h2c) { 3525 kfree(h2c); 3526 return -EFAULT; 3527 } 3528 3529 early_h2c->h2c = h2c; 3530 early_h2c->h2c_len = h2c_len; 3531 3532 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3533 3534 out: 3535 return count; 3536 } 3537 3538 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 3539 { 3540 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3541 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3542 u16 pkt_id; 3543 int ret; 3544 3545 rtw89_leave_ps_mode(rtwdev); 3546 3547 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3548 if (ret) 3549 return ret; 3550 3551 /* intentionally, enqueue two pkt, but has only one pkt id */ 3552 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3553 ctrl_para.start_pktid = pkt_id; 3554 ctrl_para.end_pktid = pkt_id; 3555 ctrl_para.pkt_num = 1; /* start from 0 */ 3556 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3557 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3558 3559 if (mac->set_cpuio(rtwdev, &ctrl_para, true)) 3560 return -EFAULT; 3561 3562 return 0; 3563 } 3564 3565 static ssize_t 3566 rtw89_debug_priv_fw_crash_get(struct rtw89_dev *rtwdev, 3567 struct rtw89_debugfs_priv *debugfs_priv, 3568 char *buf, size_t bufsz) 3569 { 3570 char *p = buf, *end = buf + bufsz; 3571 3572 p += scnprintf(p, end - p, "%d\n", 3573 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3574 return p - buf; 3575 } 3576 3577 enum rtw89_dbg_crash_simulation_type { 3578 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3579 RTW89_DBG_SIM_CTRL_ERROR = 2, 3580 }; 3581 3582 static ssize_t 3583 rtw89_debug_priv_fw_crash_set(struct rtw89_dev *rtwdev, 3584 struct rtw89_debugfs_priv *debugfs_priv, 3585 const char *buf, size_t count) 3586 { 3587 int (*sim)(struct rtw89_dev *rtwdev); 3588 u8 crash_type; 3589 int ret; 3590 3591 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3592 3593 ret = kstrtou8(buf, 0, &crash_type); 3594 if (ret) 3595 return -EINVAL; 3596 3597 switch (crash_type) { 3598 case RTW89_DBG_SIM_CPU_EXCEPTION: 3599 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw)) 3600 return -EOPNOTSUPP; 3601 sim = rtw89_fw_h2c_trigger_cpu_exception; 3602 break; 3603 case RTW89_DBG_SIM_CTRL_ERROR: 3604 sim = rtw89_dbg_trigger_ctrl_error; 3605 break; 3606 default: 3607 return -EINVAL; 3608 } 3609 3610 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3611 ret = sim(rtwdev); 3612 3613 if (ret) 3614 return ret; 3615 3616 return count; 3617 } 3618 3619 static ssize_t rtw89_debug_priv_btc_info_get(struct rtw89_dev *rtwdev, 3620 struct rtw89_debugfs_priv *debugfs_priv, 3621 char *buf, size_t bufsz) 3622 { 3623 return rtw89_btc_dump_info(rtwdev, buf, bufsz); 3624 } 3625 3626 static ssize_t rtw89_debug_priv_btc_manual_set(struct rtw89_dev *rtwdev, 3627 struct rtw89_debugfs_priv *debugfs_priv, 3628 const char *buf, size_t count) 3629 { 3630 struct rtw89_btc *btc = &rtwdev->btc; 3631 const struct rtw89_btc_ver *ver = btc->ver; 3632 int ret; 3633 3634 ret = kstrtobool(buf, &btc->manual_ctrl); 3635 if (ret) 3636 return ret; 3637 3638 if (ver->fcxctrl == 7) 3639 btc->ctrl.ctrl_v7.manual = btc->manual_ctrl; 3640 else 3641 btc->ctrl.ctrl.manual = btc->manual_ctrl; 3642 3643 return count; 3644 } 3645 3646 static ssize_t rtw89_debug_priv_fw_log_manual_set(struct rtw89_dev *rtwdev, 3647 struct rtw89_debugfs_priv *debugfs_priv, 3648 const char *buf, size_t count) 3649 { 3650 struct rtw89_fw_log *log = &rtwdev->fw.log; 3651 bool fw_log_manual; 3652 3653 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3654 3655 if (kstrtobool(buf, &fw_log_manual)) 3656 goto out; 3657 3658 log->enable = fw_log_manual; 3659 if (log->enable) 3660 rtw89_fw_log_prepare(rtwdev); 3661 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3662 out: 3663 return count; 3664 } 3665 3666 static int rtw89_sta_link_info_get_iter(struct rtw89_dev *rtwdev, 3667 char *buf, size_t bufsz, 3668 struct rtw89_sta_link *rtwsta_link) 3669 { 3670 static const char * const he_gi_str[] = { 3671 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3672 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3673 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3674 }; 3675 static const char * const eht_gi_str[] = { 3676 [NL80211_RATE_INFO_EHT_GI_0_8] = "0.8", 3677 [NL80211_RATE_INFO_EHT_GI_1_6] = "1.6", 3678 [NL80211_RATE_INFO_EHT_GI_3_2] = "3.2", 3679 }; 3680 struct rate_info *rate = &rtwsta_link->ra_report.txrate; 3681 struct ieee80211_rx_status *status = &rtwsta_link->rx_status; 3682 struct rtw89_hal *hal = &rtwdev->hal; 3683 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3684 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3685 struct ieee80211_link_sta *link_sta; 3686 char *p = buf, *end = buf + bufsz; 3687 u8 evm_min, evm_max, evm_1ss; 3688 u16 max_rc_amsdu_len; 3689 u8 rssi; 3690 u8 snr; 3691 int i; 3692 3693 rcu_read_lock(); 3694 3695 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3696 max_rc_amsdu_len = link_sta->agg.max_rc_amsdu_len; 3697 3698 rcu_read_unlock(); 3699 3700 p += scnprintf(p, end - p, "TX rate [%u, %u]: ", rtwsta_link->mac_id, 3701 rtwsta_link->link_id); 3702 3703 if (rate->flags & RATE_INFO_FLAGS_MCS) 3704 p += scnprintf(p, end - p, "HT MCS-%d%s", rate->mcs, 3705 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3706 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3707 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", rate->nss, 3708 rate->mcs, 3709 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3710 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3711 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", rate->nss, 3712 rate->mcs, 3713 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3714 he_gi_str[rate->he_gi] : "N/A"); 3715 else if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) 3716 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", rate->nss, 3717 rate->mcs, 3718 rate->eht_gi < ARRAY_SIZE(eht_gi_str) ? 3719 eht_gi_str[rate->eht_gi] : "N/A"); 3720 else 3721 p += scnprintf(p, end - p, "Legacy %d", rate->legacy); 3722 p += scnprintf(p, end - p, "%s", 3723 rtwsta_link->ra_report.might_fallback_legacy ? " FB_G" : ""); 3724 p += scnprintf(p, end - p, " BW:%u", 3725 rtw89_rate_info_bw_to_mhz(rate->bw)); 3726 p += scnprintf(p, end - p, " (hw_rate=0x%x)", 3727 rtwsta_link->ra_report.hw_rate); 3728 p += scnprintf(p, end - p, " ==> agg_wait=%d (%d)\n", 3729 rtwsta_link->max_agg_wait, 3730 max_rc_amsdu_len); 3731 3732 p += scnprintf(p, end - p, "RX rate [%u, %u]: ", rtwsta_link->mac_id, 3733 rtwsta_link->link_id); 3734 3735 switch (status->encoding) { 3736 case RX_ENC_LEGACY: 3737 p += scnprintf(p, end - p, "Legacy %d", status->rate_idx + 3738 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 3739 break; 3740 case RX_ENC_HT: 3741 p += scnprintf(p, end - p, "HT MCS-%d%s", status->rate_idx, 3742 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3743 break; 3744 case RX_ENC_VHT: 3745 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", status->nss, 3746 status->rate_idx, 3747 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3748 break; 3749 case RX_ENC_HE: 3750 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", 3751 status->nss, status->rate_idx, 3752 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3753 he_gi_str[status->he_gi] : "N/A"); 3754 break; 3755 case RX_ENC_EHT: 3756 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", 3757 status->nss, status->rate_idx, 3758 status->eht.gi < ARRAY_SIZE(eht_gi_str) ? 3759 eht_gi_str[status->eht.gi] : "N/A"); 3760 break; 3761 } 3762 p += scnprintf(p, end - p, " BW:%u", 3763 rtw89_rate_info_bw_to_mhz(status->bw)); 3764 p += scnprintf(p, end - p, " (hw_rate=0x%x)\n", 3765 rtwsta_link->rx_hw_rate); 3766 3767 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi); 3768 p += scnprintf(p, end - p, "RSSI: %d dBm (raw=%d, prev=%d) [", 3769 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, 3770 rtwsta_link->prev_rssi); 3771 for (i = 0; i < ant_num; i++) { 3772 rssi = ewma_rssi_read(&rtwsta_link->rssi[i]); 3773 p += scnprintf(p, end - p, "%d%s%s", 3774 RTW89_RSSI_RAW_TO_DBM(rssi), 3775 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 3776 i + 1 == ant_num ? "" : ", "); 3777 } 3778 p += scnprintf(p, end - p, "]\n"); 3779 3780 evm_1ss = ewma_evm_read(&rtwsta_link->evm_1ss); 3781 p += scnprintf(p, end - p, "EVM: [%2u.%02u, ", evm_1ss >> 2, 3782 (evm_1ss & 0x3) * 25); 3783 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 3784 evm_min = ewma_evm_read(&rtwsta_link->evm_min[i]); 3785 evm_max = ewma_evm_read(&rtwsta_link->evm_max[i]); 3786 3787 p += scnprintf(p, end - p, "%s(%2u.%02u, %2u.%02u)", 3788 i == 0 ? "" : " ", 3789 evm_min >> 2, (evm_min & 0x3) * 25, 3790 evm_max >> 2, (evm_max & 0x3) * 25); 3791 } 3792 p += scnprintf(p, end - p, "]\t"); 3793 3794 snr = ewma_snr_read(&rtwsta_link->avg_snr); 3795 p += scnprintf(p, end - p, "SNR: %u\n", snr); 3796 3797 return p - buf; 3798 } 3799 3800 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 3801 { 3802 struct rtw89_debugfs_iter_data *iter_data = 3803 (struct rtw89_debugfs_iter_data *)data; 3804 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3805 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3806 struct rtw89_sta_link *rtwsta_link; 3807 size_t bufsz = iter_data->bufsz; 3808 char *buf = iter_data->buf; 3809 char *p = buf, *end = buf + bufsz; 3810 unsigned int link_id; 3811 3812 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 3813 p += rtw89_sta_link_info_get_iter(rtwdev, p, end - p, rtwsta_link); 3814 3815 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 3816 } 3817 3818 static int 3819 rtw89_debug_append_rx_rate(char *buf, size_t bufsz, struct rtw89_pkt_stat *pkt_stat, 3820 enum rtw89_hw_rate first_rate, int len) 3821 { 3822 char *p = buf, *end = buf + bufsz; 3823 int i; 3824 3825 for (i = 0; i < len; i++) 3826 p += scnprintf(p, end - p, "%s%u", i == 0 ? "" : ", ", 3827 pkt_stat->rx_rate_cnt[first_rate + i]); 3828 3829 return p - buf; 3830 } 3831 3832 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate} 3833 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate} 3834 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate} 3835 3836 static const struct rtw89_rx_rate_cnt_info { 3837 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM]; 3838 int len; 3839 int ext; 3840 const char *rate_mode; 3841 } rtw89_rx_rate_cnt_infos[] = { 3842 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"}, 3843 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"}, 3844 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"}, 3845 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"}, 3846 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"}, 3847 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"}, 3848 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"}, 3849 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"}, 3850 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"}, 3851 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"}, 3852 }; 3853 3854 static ssize_t rtw89_debug_priv_phy_info_get(struct rtw89_dev *rtwdev, 3855 struct rtw89_debugfs_priv *debugfs_priv, 3856 char *buf, size_t bufsz) 3857 { 3858 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3859 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 3860 const struct rtw89_chip_info *chip = rtwdev->chip; 3861 struct rtw89_debugfs_iter_data iter_data; 3862 const struct rtw89_rx_rate_cnt_info *info; 3863 struct rtw89_hal *hal = &rtwdev->hal; 3864 char *p = buf, *end = buf + bufsz; 3865 enum rtw89_hw_rate first_rate; 3866 u8 rssi; 3867 int i; 3868 3869 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 3870 3871 p += scnprintf(p, end - p, "TP TX: %u [%u] Mbps (lv: %d", 3872 stats->tx_throughput, stats->tx_throughput_raw, 3873 stats->tx_tfc_lv); 3874 if (hal->thermal_prot_lv) 3875 p += scnprintf(p, end - p, ", duty: %d%%", 3876 100 - hal->thermal_prot_lv * RTW89_THERMAL_PROT_STEP); 3877 p += scnprintf(p, end - p, "), RX: %u [%u] Mbps (lv: %d)\n", 3878 stats->rx_throughput, stats->rx_throughput_raw, 3879 stats->rx_tfc_lv); 3880 p += scnprintf(p, end - p, "Beacon: %u (%d dBm), TF: %u\n", 3881 pkt_stat->beacon_nr, 3882 RTW89_RSSI_RAW_TO_DBM(rssi), stats->rx_tf_periodic); 3883 p += scnprintf(p, end - p, "Avg packet length: TX=%u, RX=%u\n", 3884 stats->tx_avg_len, 3885 stats->rx_avg_len); 3886 3887 p += scnprintf(p, end - p, "RX count:\n"); 3888 3889 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 3890 info = &rtw89_rx_rate_cnt_infos[i]; 3891 first_rate = info->first_rate[chip->chip_gen]; 3892 if (first_rate >= RTW89_HW_RATE_NR) 3893 continue; 3894 3895 p += scnprintf(p, end - p, "%10s [", info->rate_mode); 3896 p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat, 3897 first_rate, info->len); 3898 if (info->ext) { 3899 p += scnprintf(p, end - p, "]["); 3900 p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat, 3901 first_rate + info->len, info->ext); 3902 } 3903 p += scnprintf(p, end - p, "]\n"); 3904 } 3905 3906 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 3907 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, &iter_data); 3908 p += iter_data.written_sz; 3909 3910 return p - buf; 3911 } 3912 3913 static int rtw89_dump_addr_cam(struct rtw89_dev *rtwdev, 3914 char *buf, size_t bufsz, 3915 struct rtw89_addr_cam_entry *addr_cam) 3916 { 3917 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3918 const struct rtw89_sec_cam_entry *sec_entry; 3919 char *p = buf, *end = buf + bufsz; 3920 u8 sec_cam_idx; 3921 int i; 3922 3923 p += scnprintf(p, end - p, "\taddr_cam_idx=%u\n", 3924 addr_cam->addr_cam_idx); 3925 p += scnprintf(p, end - p, "\t-> bssid_cam_idx=%u\n", 3926 addr_cam->bssid_cam_idx); 3927 p += scnprintf(p, end - p, "\tsec_cam_bitmap=%*ph\n", 3928 (int)sizeof(addr_cam->sec_cam_map), 3929 addr_cam->sec_cam_map); 3930 for_each_set_bit(i, addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM) { 3931 sec_cam_idx = addr_cam->sec_ent[i]; 3932 sec_entry = cam_info->sec_entries[sec_cam_idx]; 3933 if (!sec_entry) 3934 continue; 3935 p += scnprintf(p, end - p, "\tsec[%d]: sec_cam_idx %u", i, 3936 sec_entry->sec_cam_idx); 3937 if (sec_entry->ext_key) 3938 p += scnprintf(p, end - p, ", %u", 3939 sec_entry->sec_cam_idx + 1); 3940 p += scnprintf(p, end - p, "\n"); 3941 } 3942 3943 return p - buf; 3944 } 3945 3946 __printf(4, 5) 3947 static int rtw89_dump_pkt_offload(char *buf, size_t bufsz, struct list_head *pkt_list, 3948 const char *fmt, ...) 3949 { 3950 char *p = buf, *end = buf + bufsz; 3951 struct rtw89_pktofld_info *info; 3952 struct va_format vaf; 3953 va_list args; 3954 3955 if (list_empty(pkt_list)) 3956 return 0; 3957 3958 va_start(args, fmt); 3959 vaf.va = &args; 3960 vaf.fmt = fmt; 3961 3962 p += scnprintf(p, end - p, "%pV", &vaf); 3963 3964 va_end(args); 3965 3966 list_for_each_entry(info, pkt_list, list) 3967 p += scnprintf(p, end - p, "%d ", info->id); 3968 3969 p += scnprintf(p, end - p, "\n"); 3970 3971 return p - buf; 3972 } 3973 3974 static int rtw89_vif_link_ids_get(struct rtw89_dev *rtwdev, 3975 char *buf, size_t bufsz, u8 *mac, 3976 struct rtw89_vif_link *rtwvif_link, 3977 bool designated) 3978 { 3979 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif_link->bssid_cam; 3980 char *p = buf, *end = buf + bufsz; 3981 3982 p += scnprintf(p, end - p, " [%u] %pM\n", rtwvif_link->mac_id, 3983 rtwvif_link->mac_addr); 3984 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwvif_link->link_id, 3985 designated ? " (*)" : ""); 3986 p += scnprintf(p, end - p, "\tbssid_cam_idx=%u\n", 3987 bssid_cam->bssid_cam_idx); 3988 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwvif_link->addr_cam); 3989 p += rtw89_dump_pkt_offload(p, end - p, &rtwvif_link->general_pkt_list, 3990 "\tpkt_ofld[GENERAL]: "); 3991 3992 return p - buf; 3993 } 3994 3995 static 3996 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 3997 { 3998 struct rtw89_debugfs_iter_data *iter_data = 3999 (struct rtw89_debugfs_iter_data *)data; 4000 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 4001 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 4002 struct rtw89_vif_link *designated_link; 4003 struct rtw89_vif_link *rtwvif_link; 4004 size_t bufsz = iter_data->bufsz; 4005 char *buf = iter_data->buf; 4006 char *p = buf, *end = buf + bufsz; 4007 unsigned int link_id; 4008 4009 designated_link = rtw89_get_designated_link(rtwvif); 4010 4011 p += scnprintf(p, end - p, "VIF %pM\n", rtwvif->mac_addr); 4012 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4013 p += rtw89_vif_link_ids_get(rtwdev, p, end - p, mac, rtwvif_link, 4014 rtwvif_link == designated_link); 4015 4016 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4017 } 4018 4019 static int rtw89_dump_ba_cam(struct rtw89_dev *rtwdev, 4020 char *buf, size_t bufsz, 4021 struct rtw89_sta_link *rtwsta_link) 4022 { 4023 struct rtw89_ba_cam_entry *entry; 4024 char *p = buf, *end = buf + bufsz; 4025 bool first = true; 4026 4027 list_for_each_entry(entry, &rtwsta_link->ba_cam_list, list) { 4028 if (first) { 4029 p += scnprintf(p, end - p, "\tba_cam "); 4030 first = false; 4031 } else { 4032 p += scnprintf(p, end - p, ", "); 4033 } 4034 p += scnprintf(p, end - p, "tid[%u]=%d", entry->tid, 4035 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 4036 } 4037 p += scnprintf(p, end - p, "\n"); 4038 4039 return p - buf; 4040 } 4041 4042 static int rtw89_sta_link_ids_get(struct rtw89_dev *rtwdev, 4043 char *buf, size_t bufsz, 4044 struct rtw89_sta_link *rtwsta_link, 4045 bool designated) 4046 { 4047 struct ieee80211_link_sta *link_sta; 4048 char *p = buf, *end = buf + bufsz; 4049 4050 rcu_read_lock(); 4051 4052 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4053 4054 p += scnprintf(p, end - p, " [%u] %pM\n", rtwsta_link->mac_id, 4055 link_sta->addr); 4056 4057 rcu_read_unlock(); 4058 4059 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwsta_link->link_id, 4060 designated ? " (*)" : ""); 4061 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwsta_link->addr_cam); 4062 p += rtw89_dump_ba_cam(rtwdev, p, end - p, rtwsta_link); 4063 4064 return p - buf; 4065 } 4066 4067 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 4068 { 4069 struct rtw89_debugfs_iter_data *iter_data = 4070 (struct rtw89_debugfs_iter_data *)data; 4071 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4072 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4073 struct rtw89_sta_link *designated_link; 4074 struct rtw89_sta_link *rtwsta_link; 4075 size_t bufsz = iter_data->bufsz; 4076 char *buf = iter_data->buf; 4077 char *p = buf, *end = buf + bufsz; 4078 unsigned int link_id; 4079 4080 designated_link = rtw89_get_designated_link(rtwsta); 4081 4082 p += scnprintf(p, end - p, "STA %pM %s\n", sta->addr, 4083 sta->tdls ? "(TDLS)" : ""); 4084 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 4085 p += rtw89_sta_link_ids_get(rtwdev, p, end - p, rtwsta_link, 4086 rtwsta_link == designated_link); 4087 4088 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4089 } 4090 4091 static ssize_t rtw89_debug_priv_stations_get(struct rtw89_dev *rtwdev, 4092 struct rtw89_debugfs_priv *debugfs_priv, 4093 char *buf, size_t bufsz) 4094 { 4095 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4096 struct rtw89_debugfs_iter_data iter_data; 4097 char *p = buf, *end = buf + bufsz; 4098 u8 idx; 4099 4100 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4101 4102 p += scnprintf(p, end - p, "map:\n"); 4103 p += scnprintf(p, end - p, "\tmac_id: %*ph\n", 4104 (int)sizeof(rtwdev->mac_id_map), 4105 rtwdev->mac_id_map); 4106 p += scnprintf(p, end - p, "\taddr_cam: %*ph\n", 4107 (int)sizeof(cam_info->addr_cam_map), 4108 cam_info->addr_cam_map); 4109 p += scnprintf(p, end - p, "\tbssid_cam: %*ph\n", 4110 (int)sizeof(cam_info->bssid_cam_map), 4111 cam_info->bssid_cam_map); 4112 p += scnprintf(p, end - p, "\tsec_cam: %*ph\n", 4113 (int)sizeof(cam_info->sec_cam_map), 4114 cam_info->sec_cam_map); 4115 p += scnprintf(p, end - p, "\tba_cam: %*ph\n", 4116 (int)sizeof(cam_info->ba_cam_map), 4117 cam_info->ba_cam_map); 4118 p += scnprintf(p, end - p, "\tpkt_ofld: %*ph\n", 4119 (int)sizeof(rtwdev->pkt_offload), 4120 rtwdev->pkt_offload); 4121 4122 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 4123 if (!(rtwdev->chip->support_bands & BIT(idx))) 4124 continue; 4125 p += rtw89_dump_pkt_offload(p, end - p, &rtwdev->scan_info.pkt_list[idx], 4126 "\t\t[SCAN %u]: ", idx); 4127 } 4128 4129 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4130 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 4131 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, &iter_data); 4132 p += iter_data.written_sz; 4133 4134 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4135 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, &iter_data); 4136 p += iter_data.written_sz; 4137 4138 return p - buf; 4139 } 4140 4141 static void rtw89_debug_disable_dm_cfg_bmap(struct rtw89_dev *rtwdev, u32 new) 4142 { 4143 struct rtw89_hal *hal = &rtwdev->hal; 4144 u32 old = hal->disabled_dm_bitmap; 4145 4146 if (new == old) 4147 return; 4148 4149 hal->disabled_dm_bitmap = new; 4150 4151 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable DM: 0x%x -> 0x%x\n", old, new); 4152 } 4153 4154 static void rtw89_debug_disable_dm_set_flag(struct rtw89_dev *rtwdev, u8 flag) 4155 { 4156 struct rtw89_hal *hal = &rtwdev->hal; 4157 u32 cur = hal->disabled_dm_bitmap; 4158 4159 rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur | BIT(flag)); 4160 } 4161 4162 static void rtw89_debug_disable_dm_clr_flag(struct rtw89_dev *rtwdev, u8 flag) 4163 { 4164 struct rtw89_hal *hal = &rtwdev->hal; 4165 u32 cur = hal->disabled_dm_bitmap; 4166 4167 rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur & ~BIT(flag)); 4168 } 4169 4170 #define DM_INFO(type) {RTW89_DM_ ## type, #type} 4171 4172 static const struct rtw89_disabled_dm_info { 4173 enum rtw89_dm_type type; 4174 const char *name; 4175 } rtw89_disabled_dm_infos[] = { 4176 DM_INFO(DYNAMIC_EDCCA), 4177 DM_INFO(THERMAL_PROTECT), 4178 DM_INFO(TAS), 4179 DM_INFO(MLO), 4180 }; 4181 4182 static ssize_t 4183 rtw89_debug_priv_disable_dm_get(struct rtw89_dev *rtwdev, 4184 struct rtw89_debugfs_priv *debugfs_priv, 4185 char *buf, size_t bufsz) 4186 { 4187 const struct rtw89_disabled_dm_info *info; 4188 struct rtw89_hal *hal = &rtwdev->hal; 4189 char *p = buf, *end = buf + bufsz; 4190 u32 disabled; 4191 int i; 4192 4193 p += scnprintf(p, end - p, "Disabled DM: 0x%x\n", 4194 hal->disabled_dm_bitmap); 4195 4196 for (i = 0; i < ARRAY_SIZE(rtw89_disabled_dm_infos); i++) { 4197 info = &rtw89_disabled_dm_infos[i]; 4198 disabled = BIT(info->type) & hal->disabled_dm_bitmap; 4199 4200 p += scnprintf(p, end - p, "[%d] %s: %c\n", info->type, 4201 info->name, 4202 disabled ? 'X' : 'O'); 4203 } 4204 4205 return p - buf; 4206 } 4207 4208 static ssize_t 4209 rtw89_debug_priv_disable_dm_set(struct rtw89_dev *rtwdev, 4210 struct rtw89_debugfs_priv *debugfs_priv, 4211 const char *buf, size_t count) 4212 { 4213 u32 conf; 4214 int ret; 4215 4216 ret = kstrtou32(buf, 0, &conf); 4217 if (ret) 4218 return -EINVAL; 4219 4220 rtw89_debug_disable_dm_cfg_bmap(rtwdev, conf); 4221 4222 return count; 4223 } 4224 4225 static void rtw89_debug_mlo_mode_set_mlsr(struct rtw89_dev *rtwdev, 4226 unsigned int link_id) 4227 { 4228 struct ieee80211_vif *vif; 4229 struct rtw89_vif *rtwvif; 4230 4231 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4232 vif = rtwvif_to_vif(rtwvif); 4233 if (!ieee80211_vif_is_mld(vif)) 4234 continue; 4235 4236 rtw89_core_mlsr_switch(rtwdev, rtwvif, link_id); 4237 } 4238 } 4239 4240 static ssize_t 4241 rtw89_debug_priv_mlo_mode_get(struct rtw89_dev *rtwdev, 4242 struct rtw89_debugfs_priv *debugfs_priv, 4243 char *buf, size_t bufsz) 4244 { 4245 bool mlo_dm_dis = rtwdev->hal.disabled_dm_bitmap & BIT(RTW89_DM_MLO); 4246 char *p = buf, *end = buf + bufsz; 4247 struct ieee80211_vif *vif; 4248 struct rtw89_vif *rtwvif; 4249 int count = 0; 4250 4251 p += scnprintf(p, end - p, "MLD(s) status: (MLO DM: %s)\n", 4252 str_disable_enable(mlo_dm_dis)); 4253 4254 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4255 vif = rtwvif_to_vif(rtwvif); 4256 if (!ieee80211_vif_is_mld(vif)) 4257 continue; 4258 4259 p += scnprintf(p, end - p, 4260 "\t#%u: MLO mode %x, valid 0x%x, active 0x%x\n", 4261 count++, rtwvif->mlo_mode, vif->valid_links, 4262 vif->active_links); 4263 } 4264 4265 if (count == 0) 4266 p += scnprintf(p, end - p, "\t(None)\n"); 4267 4268 return p - buf; 4269 } 4270 4271 static ssize_t 4272 rtw89_debug_priv_mlo_mode_set(struct rtw89_dev *rtwdev, 4273 struct rtw89_debugfs_priv *debugfs_priv, 4274 const char *buf, size_t count) 4275 { 4276 u8 num, mlo_mode; 4277 u32 argv; 4278 4279 num = sscanf(buf, "%hhx %u", &mlo_mode, &argv); 4280 if (num != 2) 4281 return -EINVAL; 4282 4283 rtw89_debug_disable_dm_set_flag(rtwdev, RTW89_DM_MLO); 4284 4285 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Set MLO mode to %x\n", mlo_mode); 4286 4287 switch (mlo_mode) { 4288 case RTW89_MLO_MODE_MLSR: 4289 rtw89_debug_mlo_mode_set_mlsr(rtwdev, argv); 4290 break; 4291 default: 4292 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Unsupported MLO mode\n"); 4293 rtw89_debug_disable_dm_clr_flag(rtwdev, RTW89_DM_MLO); 4294 4295 return -EOPNOTSUPP; 4296 } 4297 4298 return count; 4299 } 4300 4301 #define rtw89_debug_priv_get(name, opts...) \ 4302 { \ 4303 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4304 .opt = { opts }, \ 4305 } 4306 4307 #define rtw89_debug_priv_set(name, opts...) \ 4308 { \ 4309 .cb_write = rtw89_debug_priv_ ##name## _set, \ 4310 .opt = { opts }, \ 4311 } 4312 4313 #define rtw89_debug_priv_select_and_get(name, opts...) \ 4314 { \ 4315 .cb_write = rtw89_debug_priv_ ##name## _select, \ 4316 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4317 .opt = { opts }, \ 4318 } 4319 4320 #define rtw89_debug_priv_set_and_get(name, opts...) \ 4321 { \ 4322 .cb_write = rtw89_debug_priv_ ##name## _set, \ 4323 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4324 .opt = { opts }, \ 4325 } 4326 4327 #define RSIZE_8K .rsize = 0x2000 4328 #define RSIZE_12K .rsize = 0x3000 4329 #define RSIZE_16K .rsize = 0x4000 4330 #define RSIZE_20K .rsize = 0x5000 4331 #define RSIZE_32K .rsize = 0x8000 4332 #define RSIZE_64K .rsize = 0x10000 4333 #define RSIZE_128K .rsize = 0x20000 4334 #define RSIZE_1M .rsize = 0x100000 4335 #define RLOCK .rlock = 1 4336 #define WLOCK .wlock = 1 4337 #define RWLOCK RLOCK, WLOCK 4338 4339 static const struct rtw89_debugfs rtw89_debugfs_templ = { 4340 .read_reg = rtw89_debug_priv_select_and_get(read_reg), 4341 .write_reg = rtw89_debug_priv_set(write_reg), 4342 .read_rf = rtw89_debug_priv_select_and_get(read_rf), 4343 .write_rf = rtw89_debug_priv_set(write_rf), 4344 .rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump, RSIZE_8K), 4345 .txpwr_table = rtw89_debug_priv_get(txpwr_table, RSIZE_20K, RLOCK), 4346 .mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump, RSIZE_128K), 4347 .mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump, RSIZE_16K, RLOCK), 4348 .mac_dbg_port_dump = rtw89_debug_priv_select_and_get(mac_dbg_port_dump, RSIZE_1M), 4349 .send_h2c = rtw89_debug_priv_set(send_h2c), 4350 .early_h2c = rtw89_debug_priv_set_and_get(early_h2c, RWLOCK), 4351 .fw_crash = rtw89_debug_priv_set_and_get(fw_crash, WLOCK), 4352 .btc_info = rtw89_debug_priv_get(btc_info, RSIZE_12K), 4353 .btc_manual = rtw89_debug_priv_set(btc_manual), 4354 .fw_log_manual = rtw89_debug_priv_set(fw_log_manual, WLOCK), 4355 .phy_info = rtw89_debug_priv_get(phy_info), 4356 .stations = rtw89_debug_priv_get(stations, RLOCK), 4357 .disable_dm = rtw89_debug_priv_set_and_get(disable_dm, RWLOCK), 4358 .mlo_mode = rtw89_debug_priv_set_and_get(mlo_mode, RWLOCK), 4359 }; 4360 4361 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 4362 do { \ 4363 struct rtw89_debugfs_priv *priv = &rtwdev->debugfs->name; \ 4364 priv->rtwdev = rtwdev; \ 4365 if (IS_ERR(debugfs_create_file(#name, mode, parent, priv, \ 4366 &file_ops_ ##fopname))) \ 4367 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 4368 } while (0) 4369 4370 #define rtw89_debugfs_add_w(name) \ 4371 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 4372 #define rtw89_debugfs_add_rw(name) \ 4373 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 4374 #define rtw89_debugfs_add_r(name) \ 4375 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 4376 4377 static 4378 void rtw89_debugfs_add_sec0(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4379 { 4380 rtw89_debugfs_add_rw(read_reg); 4381 rtw89_debugfs_add_w(write_reg); 4382 rtw89_debugfs_add_rw(read_rf); 4383 rtw89_debugfs_add_w(write_rf); 4384 rtw89_debugfs_add_r(rf_reg_dump); 4385 rtw89_debugfs_add_r(txpwr_table); 4386 rtw89_debugfs_add_rw(mac_reg_dump); 4387 rtw89_debugfs_add_rw(mac_mem_dump); 4388 rtw89_debugfs_add_rw(mac_dbg_port_dump); 4389 } 4390 4391 static 4392 void rtw89_debugfs_add_sec1(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4393 { 4394 rtw89_debugfs_add_w(send_h2c); 4395 rtw89_debugfs_add_rw(early_h2c); 4396 rtw89_debugfs_add_rw(fw_crash); 4397 rtw89_debugfs_add_r(btc_info); 4398 rtw89_debugfs_add_w(btc_manual); 4399 rtw89_debugfs_add_w(fw_log_manual); 4400 rtw89_debugfs_add_r(phy_info); 4401 rtw89_debugfs_add_r(stations); 4402 rtw89_debugfs_add_rw(disable_dm); 4403 rtw89_debugfs_add_rw(mlo_mode); 4404 } 4405 4406 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 4407 { 4408 struct dentry *debugfs_topdir; 4409 4410 rtwdev->debugfs = kmemdup(&rtw89_debugfs_templ, 4411 sizeof(rtw89_debugfs_templ), GFP_KERNEL); 4412 if (!rtwdev->debugfs) 4413 return; 4414 4415 debugfs_topdir = debugfs_create_dir("rtw89", 4416 rtwdev->hw->wiphy->debugfsdir); 4417 4418 rtw89_debugfs_add_sec0(rtwdev, debugfs_topdir); 4419 rtw89_debugfs_add_sec1(rtwdev, debugfs_topdir); 4420 } 4421 4422 void rtw89_debugfs_deinit(struct rtw89_dev *rtwdev) 4423 { 4424 kfree(rtwdev->debugfs); 4425 } 4426 #endif 4427 4428 #ifdef CONFIG_RTW89_DEBUGMSG 4429 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, 4430 const char *fmt, ...) 4431 { 4432 struct va_format vaf = { 4433 .fmt = fmt, 4434 }; 4435 4436 va_list args; 4437 4438 va_start(args, fmt); 4439 vaf.va = &args; 4440 4441 if (rtw89_debug_mask & mask) 4442 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 4443 4444 va_end(args); 4445 } 4446 EXPORT_SYMBOL(rtw89_debug); 4447 #endif 4448