1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/vmalloc.h> 6 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "phy.h" 13 #include "ps.h" 14 #include "reg.h" 15 #include "sar.h" 16 #include "util.h" 17 18 #ifdef CONFIG_RTW89_DEBUGMSG 19 unsigned int rtw89_debug_mask; 20 EXPORT_SYMBOL(rtw89_debug_mask); 21 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 22 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 23 #endif 24 25 #ifdef CONFIG_RTW89_DEBUGFS 26 struct rtw89_debugfs_priv_opt { 27 bool rlock:1; 28 bool wlock:1; 29 size_t rsize; 30 }; 31 32 struct rtw89_debugfs_priv { 33 struct rtw89_dev *rtwdev; 34 ssize_t (*cb_read)(struct rtw89_dev *rtwdev, 35 struct rtw89_debugfs_priv *debugfs_priv, 36 char *buf, size_t bufsz); 37 ssize_t (*cb_write)(struct rtw89_dev *rtwdev, 38 struct rtw89_debugfs_priv *debugfs_priv, 39 const char *buf, size_t count); 40 struct rtw89_debugfs_priv_opt opt; 41 union { 42 u32 cb_data; 43 struct { 44 u32 addr; 45 u32 len; 46 } read_reg; 47 struct { 48 u32 addr; 49 u32 mask; 50 u8 path; 51 } read_rf; 52 struct { 53 u8 ss_dbg:1; 54 u8 dle_dbg:1; 55 u8 dmac_dbg:1; 56 u8 cmac_dbg:1; 57 u8 dbg_port:1; 58 } dbgpkg_en; 59 struct { 60 u32 start; 61 u32 len; 62 u8 sel; 63 } mac_mem; 64 }; 65 ssize_t rused; 66 char *rbuf; 67 }; 68 69 struct rtw89_debugfs { 70 struct rtw89_debugfs_priv read_reg; 71 struct rtw89_debugfs_priv write_reg; 72 struct rtw89_debugfs_priv read_rf; 73 struct rtw89_debugfs_priv write_rf; 74 struct rtw89_debugfs_priv rf_reg_dump; 75 struct rtw89_debugfs_priv txpwr_table; 76 struct rtw89_debugfs_priv mac_reg_dump; 77 struct rtw89_debugfs_priv mac_mem_dump; 78 struct rtw89_debugfs_priv mac_dbg_port_dump; 79 struct rtw89_debugfs_priv send_h2c; 80 struct rtw89_debugfs_priv early_h2c; 81 struct rtw89_debugfs_priv fw_crash; 82 struct rtw89_debugfs_priv btc_info; 83 struct rtw89_debugfs_priv btc_manual; 84 struct rtw89_debugfs_priv fw_log_manual; 85 struct rtw89_debugfs_priv phy_info; 86 struct rtw89_debugfs_priv stations; 87 struct rtw89_debugfs_priv disable_dm; 88 struct rtw89_debugfs_priv mlo_mode; 89 }; 90 91 struct rtw89_debugfs_iter_data { 92 char *buf; 93 size_t bufsz; 94 int written_sz; 95 }; 96 97 static void rtw89_debugfs_iter_data_setup(struct rtw89_debugfs_iter_data *iter_data, 98 char *buf, size_t bufsz) 99 { 100 iter_data->buf = buf; 101 iter_data->bufsz = bufsz; 102 iter_data->written_sz = 0; 103 } 104 105 static void rtw89_debugfs_iter_data_next(struct rtw89_debugfs_iter_data *iter_data, 106 char *buf, size_t bufsz, int written_sz) 107 { 108 iter_data->buf = buf; 109 iter_data->bufsz = bufsz; 110 iter_data->written_sz += written_sz; 111 } 112 113 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 114 [RATE_INFO_BW_20] = 20, 115 [RATE_INFO_BW_40] = 40, 116 [RATE_INFO_BW_80] = 80, 117 [RATE_INFO_BW_160] = 160, 118 [RATE_INFO_BW_320] = 320, 119 }; 120 121 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 122 { 123 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 124 return rtw89_rate_info_bw_to_mhz_map[bw]; 125 126 return 0; 127 } 128 129 static ssize_t rtw89_debugfs_file_read_helper(struct wiphy *wiphy, struct file *file, 130 char *buf, size_t bufsz, void *data) 131 { 132 struct rtw89_debugfs_priv *debugfs_priv = data; 133 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 134 ssize_t n; 135 136 n = debugfs_priv->cb_read(rtwdev, debugfs_priv, buf, bufsz); 137 rtw89_might_trailing_ellipsis(buf, bufsz, n); 138 139 return n; 140 } 141 142 static ssize_t rtw89_debugfs_file_read(struct file *file, char __user *userbuf, 143 size_t count, loff_t *ppos) 144 { 145 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 146 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 147 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 148 size_t bufsz = opt->rsize ? opt->rsize : PAGE_SIZE; 149 char *buf; 150 ssize_t n; 151 152 if (!debugfs_priv->rbuf) 153 debugfs_priv->rbuf = devm_kzalloc(rtwdev->dev, bufsz, GFP_KERNEL); 154 155 buf = debugfs_priv->rbuf; 156 if (!buf) 157 return -ENOMEM; 158 159 if (*ppos) { 160 n = debugfs_priv->rused; 161 goto out; 162 } 163 164 if (opt->rlock) { 165 n = wiphy_locked_debugfs_read(rtwdev->hw->wiphy, file, buf, bufsz, 166 userbuf, count, ppos, 167 rtw89_debugfs_file_read_helper, 168 debugfs_priv); 169 debugfs_priv->rused = n; 170 171 return n; 172 } 173 174 n = rtw89_debugfs_file_read_helper(rtwdev->hw->wiphy, file, buf, bufsz, 175 debugfs_priv); 176 debugfs_priv->rused = n; 177 178 out: 179 return simple_read_from_buffer(userbuf, count, ppos, buf, n); 180 } 181 182 static ssize_t rtw89_debugfs_file_write_helper(struct wiphy *wiphy, struct file *file, 183 char *buf, size_t count, void *data) 184 { 185 struct rtw89_debugfs_priv *debugfs_priv = data; 186 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 187 188 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 189 } 190 191 static ssize_t rtw89_debugfs_file_write(struct file *file, 192 const char __user *userbuf, 193 size_t count, loff_t *loff) 194 { 195 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 196 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 197 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 198 char *buf __free(kfree) = kmalloc(count + 1, GFP_KERNEL); 199 ssize_t n; 200 201 if (!buf) 202 return -ENOMEM; 203 204 if (opt->wlock) { 205 n = wiphy_locked_debugfs_write(rtwdev->hw->wiphy, 206 file, buf, count + 1, 207 userbuf, count, 208 rtw89_debugfs_file_write_helper, 209 debugfs_priv); 210 return n; 211 } 212 213 if (copy_from_user(buf, userbuf, count)) 214 return -EFAULT; 215 216 buf[count] = '\0'; 217 218 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 219 } 220 221 static const struct debugfs_short_fops file_ops_single_r = { 222 .read = rtw89_debugfs_file_read, 223 .llseek = generic_file_llseek, 224 }; 225 226 static const struct debugfs_short_fops file_ops_common_rw = { 227 .read = rtw89_debugfs_file_read, 228 .write = rtw89_debugfs_file_write, 229 .llseek = generic_file_llseek, 230 }; 231 232 static const struct debugfs_short_fops file_ops_single_w = { 233 .write = rtw89_debugfs_file_write, 234 .llseek = generic_file_llseek, 235 }; 236 237 static ssize_t 238 rtw89_debug_priv_read_reg_select(struct rtw89_dev *rtwdev, 239 struct rtw89_debugfs_priv *debugfs_priv, 240 const char *buf, size_t count) 241 { 242 u32 addr, len; 243 int num; 244 245 num = sscanf(buf, "%x %x", &addr, &len); 246 if (num != 2) { 247 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 248 return -EINVAL; 249 } 250 251 debugfs_priv->read_reg.addr = addr; 252 debugfs_priv->read_reg.len = len; 253 254 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 255 256 return count; 257 } 258 259 static 260 ssize_t rtw89_debug_priv_read_reg_get(struct rtw89_dev *rtwdev, 261 struct rtw89_debugfs_priv *debugfs_priv, 262 char *buf, size_t bufsz) 263 { 264 char *p = buf, *end = buf + bufsz; 265 u32 addr, addr_end, data, k; 266 u32 len; 267 268 len = debugfs_priv->read_reg.len; 269 addr = debugfs_priv->read_reg.addr; 270 271 if (len > 4) 272 goto ndata; 273 274 switch (len) { 275 case 1: 276 data = rtw89_read8(rtwdev, addr); 277 break; 278 case 2: 279 data = rtw89_read16(rtwdev, addr); 280 break; 281 case 4: 282 data = rtw89_read32(rtwdev, addr); 283 break; 284 default: 285 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 286 return -EINVAL; 287 } 288 289 p += scnprintf(p, end - p, "get %d bytes at 0x%08x=0x%08x\n", len, 290 addr, data); 291 292 return p - buf; 293 294 ndata: 295 addr_end = addr + len; 296 297 for (; addr < addr_end; addr += 16) { 298 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + addr); 299 for (k = 0; k < 16; k += 4) { 300 data = rtw89_read32(rtwdev, addr + k); 301 p += scnprintf(p, end - p, "%08x ", data); 302 } 303 p += scnprintf(p, end - p, "\n"); 304 } 305 306 return p - buf; 307 } 308 309 static 310 ssize_t rtw89_debug_priv_write_reg_set(struct rtw89_dev *rtwdev, 311 struct rtw89_debugfs_priv *debugfs_priv, 312 const char *buf, size_t count) 313 { 314 u32 addr, val, len; 315 int num; 316 317 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 318 if (num != 3) { 319 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 320 return -EINVAL; 321 } 322 323 switch (len) { 324 case 1: 325 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 326 rtw89_write8(rtwdev, addr, (u8)val); 327 break; 328 case 2: 329 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 330 rtw89_write16(rtwdev, addr, (u16)val); 331 break; 332 case 4: 333 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 334 rtw89_write32(rtwdev, addr, (u32)val); 335 break; 336 default: 337 rtw89_info(rtwdev, "invalid read write len %d\n", len); 338 break; 339 } 340 341 return count; 342 } 343 344 static ssize_t 345 rtw89_debug_priv_read_rf_select(struct rtw89_dev *rtwdev, 346 struct rtw89_debugfs_priv *debugfs_priv, 347 const char *buf, size_t count) 348 { 349 u32 addr, mask; 350 u8 path; 351 int num; 352 353 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 354 if (num != 3) { 355 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 356 return -EINVAL; 357 } 358 359 if (path >= rtwdev->chip->rf_path_num) { 360 rtw89_info(rtwdev, "wrong rf path\n"); 361 return -EINVAL; 362 } 363 debugfs_priv->read_rf.addr = addr; 364 debugfs_priv->read_rf.mask = mask; 365 debugfs_priv->read_rf.path = path; 366 367 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 368 369 return count; 370 } 371 372 static 373 ssize_t rtw89_debug_priv_read_rf_get(struct rtw89_dev *rtwdev, 374 struct rtw89_debugfs_priv *debugfs_priv, 375 char *buf, size_t bufsz) 376 { 377 char *p = buf, *end = buf + bufsz; 378 u32 addr, data, mask; 379 u8 path; 380 381 addr = debugfs_priv->read_rf.addr; 382 mask = debugfs_priv->read_rf.mask; 383 path = debugfs_priv->read_rf.path; 384 385 data = rtw89_read_rf(rtwdev, path, addr, mask); 386 387 p += scnprintf(p, end - p, "path %d, rf register 0x%08x=0x%08x\n", 388 path, addr, data); 389 390 return p - buf; 391 } 392 393 static 394 ssize_t rtw89_debug_priv_write_rf_set(struct rtw89_dev *rtwdev, 395 struct rtw89_debugfs_priv *debugfs_priv, 396 const char *buf, size_t count) 397 { 398 u32 addr, val, mask; 399 u8 path; 400 int num; 401 402 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 403 if (num != 4) { 404 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 405 return -EINVAL; 406 } 407 408 if (path >= rtwdev->chip->rf_path_num) { 409 rtw89_info(rtwdev, "wrong rf path\n"); 410 return -EINVAL; 411 } 412 413 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 414 path, addr, val, mask); 415 rtw89_write_rf(rtwdev, path, addr, mask, val); 416 417 return count; 418 } 419 420 static 421 ssize_t rtw89_debug_priv_rf_reg_dump_get(struct rtw89_dev *rtwdev, 422 struct rtw89_debugfs_priv *debugfs_priv, 423 char *buf, size_t bufsz) 424 { 425 const struct rtw89_chip_info *chip = rtwdev->chip; 426 char *p = buf, *end = buf + bufsz; 427 u32 addr, offset, data; 428 u8 path; 429 430 for (path = 0; path < chip->rf_path_num; path++) { 431 p += scnprintf(p, end - p, "RF path %d:\n\n", path); 432 for (addr = 0; addr < 0x100; addr += 4) { 433 p += scnprintf(p, end - p, "0x%08x: ", addr); 434 for (offset = 0; offset < 4; offset++) { 435 data = rtw89_read_rf(rtwdev, path, 436 addr + offset, RFREG_MASK); 437 p += scnprintf(p, end - p, "0x%05x ", data); 438 } 439 p += scnprintf(p, end - p, "\n"); 440 } 441 p += scnprintf(p, end - p, "\n"); 442 } 443 444 return p - buf; 445 } 446 447 struct txpwr_ent { 448 bool nested; 449 union { 450 const char *txt; 451 const struct txpwr_ent *ptr; 452 }; 453 u8 len; 454 }; 455 456 struct txpwr_map { 457 const struct txpwr_ent *ent; 458 u8 size; 459 u32 addr_from; 460 u32 addr_to; 461 u32 addr_to_1ss; 462 }; 463 464 #define __GEN_TXPWR_ENT_NESTED(_e) \ 465 { .nested = true, .ptr = __txpwr_ent_##_e, \ 466 .len = ARRAY_SIZE(__txpwr_ent_##_e) } 467 468 #define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t } 469 470 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 471 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 472 473 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 474 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 475 476 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 477 { .len = 8, .txt = _t "\t- " \ 478 _e0 " " _e1 " " _e2 " " _e3 " " \ 479 _e4 " " _e5 " " _e6 " " _e7 } 480 481 static const struct txpwr_ent __txpwr_ent_byr_ax[] = { 482 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 483 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 484 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 485 /* 1NSS */ 486 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 487 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 488 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 489 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 490 /* 2NSS */ 491 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 492 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 493 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 494 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 495 }; 496 497 static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) == 498 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 499 500 static const struct txpwr_map __txpwr_map_byr_ax = { 501 .ent = __txpwr_ent_byr_ax, 502 .size = ARRAY_SIZE(__txpwr_ent_byr_ax), 503 .addr_from = R_AX_PWR_BY_RATE, 504 .addr_to = R_AX_PWR_BY_RATE_MAX, 505 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX, 506 }; 507 508 static const struct txpwr_ent __txpwr_ent_lmt_ax[] = { 509 /* 1TX */ 510 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 511 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 512 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 513 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 514 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 515 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 516 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 517 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 518 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 519 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 520 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 521 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 522 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 523 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 524 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 525 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 526 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 527 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 528 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 529 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 530 /* 2TX */ 531 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 532 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 533 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 534 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 535 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 536 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 537 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 538 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 539 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 540 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 541 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 542 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 543 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 544 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 545 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 546 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 547 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 548 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 549 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 550 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 551 }; 552 553 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) == 554 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 555 556 static const struct txpwr_map __txpwr_map_lmt_ax = { 557 .ent = __txpwr_ent_lmt_ax, 558 .size = ARRAY_SIZE(__txpwr_ent_lmt_ax), 559 .addr_from = R_AX_PWR_LMT, 560 .addr_to = R_AX_PWR_LMT_MAX, 561 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX, 562 }; 563 564 static const struct txpwr_ent __txpwr_ent_lmt_ru_ax[] = { 565 /* 1TX */ 566 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 567 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 568 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 569 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 570 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 571 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 572 /* 2TX */ 573 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 574 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 575 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 576 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 577 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 578 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 579 }; 580 581 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) == 582 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 583 584 static const struct txpwr_map __txpwr_map_lmt_ru_ax = { 585 .ent = __txpwr_ent_lmt_ru_ax, 586 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_ax), 587 .addr_from = R_AX_PWR_RU_LMT, 588 .addr_to = R_AX_PWR_RU_LMT_MAX, 589 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX, 590 }; 591 592 static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = { 593 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 594 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 595 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 596 __GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"), 597 __GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 598 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 599 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 600 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 601 __GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"), 602 __GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 603 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 604 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 605 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 606 __GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"), 607 __GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 608 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 609 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 610 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 611 __GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"), 612 __GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 613 }; 614 615 static const struct txpwr_ent __txpwr_ent_byr_be[] = { 616 __GEN_TXPWR_ENT0("BW20"), 617 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 618 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 619 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 620 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 621 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 622 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 623 624 __GEN_TXPWR_ENT0("BW40"), 625 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 626 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 627 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 628 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 629 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 630 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 631 632 /* there is no CCK section after BW80 */ 633 __GEN_TXPWR_ENT0("BW80"), 634 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 635 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 636 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 637 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 638 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 639 640 __GEN_TXPWR_ENT0("BW160"), 641 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 642 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 643 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 644 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 645 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 646 647 __GEN_TXPWR_ENT0("BW320"), 648 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 649 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 650 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 651 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 652 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 653 }; 654 655 static const struct txpwr_map __txpwr_map_byr_be = { 656 .ent = __txpwr_ent_byr_be, 657 .size = ARRAY_SIZE(__txpwr_ent_byr_be), 658 .addr_from = R_BE_PWR_BY_RATE, 659 .addr_to = R_BE_PWR_BY_RATE_MAX, 660 .addr_to_1ss = 0, /* not support */ 661 }; 662 663 static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = { 664 __GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"), 665 __GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"), 666 __GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"), 667 __GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"), 668 __GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"), 669 __GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"), 670 __GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"), 671 __GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"), 672 __GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"), 673 __GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"), 674 __GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"), 675 __GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"), 676 __GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"), 677 __GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"), 678 __GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"), 679 __GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"), 680 __GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"), 681 __GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"), 682 __GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"), 683 __GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"), 684 __GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"), 685 __GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"), 686 __GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"), 687 __GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"), 688 __GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"), 689 __GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"), 690 __GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"), 691 __GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"), 692 __GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"), 693 __GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"), 694 __GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"), 695 __GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"), 696 __GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"), 697 __GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"), 698 __GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"), 699 }; 700 701 static const struct txpwr_ent __txpwr_ent_lmt_be[] = { 702 __GEN_TXPWR_ENT0("1TX"), 703 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 704 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 705 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 706 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 707 708 __GEN_TXPWR_ENT0("2TX"), 709 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 710 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 711 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 712 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 713 }; 714 715 static const struct txpwr_map __txpwr_map_lmt_be = { 716 .ent = __txpwr_ent_lmt_be, 717 .size = ARRAY_SIZE(__txpwr_ent_lmt_be), 718 .addr_from = R_BE_PWR_LMT, 719 .addr_to = R_BE_PWR_LMT_MAX, 720 .addr_to_1ss = 0, /* not support */ 721 }; 722 723 static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = { 724 __GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 725 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 726 __GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 727 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 728 __GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 729 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 730 __GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 731 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 732 __GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 733 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 734 __GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 735 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 736 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 737 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 738 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 739 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 740 __GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 741 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 742 __GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 743 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 744 }; 745 746 static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = { 747 __GEN_TXPWR_ENT0("1TX"), 748 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 749 750 __GEN_TXPWR_ENT0("2TX"), 751 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 752 }; 753 754 static const struct txpwr_map __txpwr_map_lmt_ru_be = { 755 .ent = __txpwr_ent_lmt_ru_be, 756 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be), 757 .addr_from = R_BE_PWR_RU_LMT, 758 .addr_to = R_BE_PWR_RU_LMT_MAX, 759 .addr_to_1ss = 0, /* not support */ 760 }; 761 762 static unsigned int 763 __print_txpwr_ent(char *buf, size_t bufsz, const struct txpwr_ent *ent, 764 const s8 *bufp, const unsigned int cur, unsigned int *ate) 765 { 766 char *p = buf, *end = buf + bufsz; 767 unsigned int cnt, i; 768 unsigned int eaten; 769 char *fmt; 770 771 if (ent->nested) { 772 for (cnt = 0, i = 0; i < ent->len; i++, cnt += eaten) 773 p += __print_txpwr_ent(p, end - p, ent->ptr + i, bufp, 774 cur + cnt, &eaten); 775 *ate = cnt; 776 goto out; 777 } 778 779 switch (ent->len) { 780 case 0: 781 p += scnprintf(p, end - p, "\t<< %s >>\n", ent->txt); 782 *ate = 0; 783 goto out; 784 case 2: 785 fmt = "%s\t| %3d, %3d,\t\tdBm\n"; 786 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 787 bufp[cur + 1]); 788 *ate = 2; 789 goto out; 790 case 4: 791 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 792 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 793 bufp[cur + 1], 794 bufp[cur + 2], bufp[cur + 3]); 795 *ate = 4; 796 goto out; 797 case 8: 798 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 799 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 800 bufp[cur + 1], 801 bufp[cur + 2], bufp[cur + 3], bufp[cur + 4], 802 bufp[cur + 5], bufp[cur + 6], bufp[cur + 7]); 803 *ate = 8; 804 goto out; 805 default: 806 return 0; 807 } 808 809 out: 810 return p - buf; 811 } 812 813 static ssize_t __print_txpwr_map(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 814 const struct txpwr_map *map) 815 { 816 u8 fct = rtwdev->chip->txpwr_factor_mac; 817 u8 path_num = rtwdev->chip->rf_path_num; 818 char *p = buf, *end = buf + bufsz; 819 unsigned int cur, i; 820 unsigned int eaten; 821 u32 max_valid_addr; 822 u32 val, addr; 823 s8 *bufp, tmp; 824 int ret; 825 826 bufp = vzalloc(map->addr_to - map->addr_from + 4); 827 if (!bufp) 828 return -ENOMEM; 829 830 if (path_num == 1) 831 max_valid_addr = map->addr_to_1ss; 832 else 833 max_valid_addr = map->addr_to; 834 835 if (max_valid_addr == 0) 836 return -EOPNOTSUPP; 837 838 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 839 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 840 if (ret) 841 val = MASKDWORD; 842 843 cur = addr - map->addr_from; 844 for (i = 0; i < 4; i++, val >>= 8) { 845 /* signed 7 bits, and reserved BIT(7) */ 846 tmp = sign_extend32(val, 6); 847 bufp[cur + i] = tmp >> fct; 848 } 849 } 850 851 for (cur = 0, i = 0; i < map->size; i++, cur += eaten) 852 p += __print_txpwr_ent(p, end - p, &map->ent[i], bufp, cur, &eaten); 853 854 vfree(bufp); 855 return p - buf; 856 } 857 858 static int __print_regd(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 859 const struct rtw89_chan *chan) 860 { 861 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 862 char *p = buf, *end = buf + bufsz; 863 u8 band = chan->band_type; 864 u8 regd = rtw89_regd_get(rtwdev, band); 865 866 p += scnprintf(p, end - p, "%s\n", rtw89_regd_get_string(regd)); 867 p += scnprintf(p, end - p, "\t(txpwr UK follow ETSI: %s)\n", 868 str_yes_no(regulatory->txpwr_uk_follow_etsi)); 869 870 return p - buf; 871 } 872 873 struct dbgfs_txpwr_table { 874 const struct txpwr_map *byr; 875 const struct txpwr_map *lmt; 876 const struct txpwr_map *lmt_ru; 877 }; 878 879 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = { 880 .byr = &__txpwr_map_byr_ax, 881 .lmt = &__txpwr_map_lmt_ax, 882 .lmt_ru = &__txpwr_map_lmt_ru_ax, 883 }; 884 885 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = { 886 .byr = &__txpwr_map_byr_be, 887 .lmt = &__txpwr_map_lmt_be, 888 .lmt_ru = &__txpwr_map_lmt_ru_be, 889 }; 890 891 static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = { 892 [RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax, 893 [RTW89_CHIP_BE] = &dbgfs_txpwr_table_be, 894 }; 895 896 static 897 int rtw89_debug_priv_txpwr_table_get_regd(struct rtw89_dev *rtwdev, 898 char *buf, size_t bufsz, 899 const struct rtw89_chan *chan) 900 { 901 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 902 const struct rtw89_reg_6ghz_tpe *tpe6 = ®ulatory->reg_6ghz_tpe; 903 char *p = buf, *end = buf + bufsz; 904 905 p += scnprintf(p, end - p, "[Chanctx] band %u, ch %u, bw %u\n", 906 chan->band_type, chan->channel, chan->band_width); 907 908 p += scnprintf(p, end - p, "[Regulatory] "); 909 p += __print_regd(rtwdev, p, end - p, chan); 910 911 if (chan->band_type == RTW89_BAND_6G) { 912 p += scnprintf(p, end - p, "[reg6_pwr_type] %u\n", 913 regulatory->reg_6ghz_power); 914 915 if (tpe6->valid) 916 p += scnprintf(p, end - p, "[TPE] %d dBm\n", 917 tpe6->constraint); 918 } 919 920 return p - buf; 921 } 922 923 static 924 ssize_t rtw89_debug_priv_txpwr_table_get(struct rtw89_dev *rtwdev, 925 struct rtw89_debugfs_priv *debugfs_priv, 926 char *buf, size_t bufsz) 927 { 928 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 929 struct rtw89_sar_parm sar_parm = {}; 930 const struct dbgfs_txpwr_table *tbl; 931 const struct rtw89_chan *chan; 932 char *p = buf, *end = buf + bufsz; 933 ssize_t n; 934 935 lockdep_assert_wiphy(rtwdev->hw->wiphy); 936 937 rtw89_leave_ps_mode(rtwdev); 938 chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 939 sar_parm.center_freq = chan->freq; 940 941 p += rtw89_debug_priv_txpwr_table_get_regd(rtwdev, p, end - p, chan); 942 943 p += scnprintf(p, end - p, "[SAR]\n"); 944 p += rtw89_print_sar(rtwdev, p, end - p, &sar_parm); 945 946 p += scnprintf(p, end - p, "[TAS]\n"); 947 p += rtw89_print_tas(rtwdev, p, end - p); 948 949 p += scnprintf(p, end - p, "[DAG]\n"); 950 p += rtw89_print_ant_gain(rtwdev, p, end - p, chan); 951 952 tbl = dbgfs_txpwr_tables[chip_gen]; 953 if (!tbl) 954 return -EOPNOTSUPP; 955 956 p += scnprintf(p, end - p, "\n[TX power byrate]\n"); 957 n = __print_txpwr_map(rtwdev, p, end - p, tbl->byr); 958 if (n < 0) 959 return n; 960 p += n; 961 962 p += scnprintf(p, end - p, "\n[TX power limit]\n"); 963 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt); 964 if (n < 0) 965 return n; 966 p += n; 967 968 p += scnprintf(p, end - p, "\n[TX power limit_ru]\n"); 969 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru); 970 if (n < 0) 971 return n; 972 p += n; 973 974 return p - buf; 975 } 976 977 static ssize_t 978 rtw89_debug_priv_mac_reg_dump_select(struct rtw89_dev *rtwdev, 979 struct rtw89_debugfs_priv *debugfs_priv, 980 const char *buf, size_t count) 981 { 982 const struct rtw89_chip_info *chip = rtwdev->chip; 983 int sel; 984 int ret; 985 986 ret = kstrtoint(buf, 0, &sel); 987 if (ret) 988 return ret; 989 990 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 991 rtw89_info(rtwdev, "invalid args: %d\n", sel); 992 return -EINVAL; 993 } 994 995 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 996 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 997 chip->chip_id); 998 return -EINVAL; 999 } 1000 1001 debugfs_priv->cb_data = sel; 1002 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 1003 1004 return count; 1005 } 1006 1007 #define RTW89_MAC_PAGE_SIZE 0x100 1008 1009 static 1010 ssize_t rtw89_debug_priv_mac_reg_dump_get(struct rtw89_dev *rtwdev, 1011 struct rtw89_debugfs_priv *debugfs_priv, 1012 char *buf, size_t bufsz) 1013 { 1014 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 1015 char *p = buf, *end = buf + bufsz; 1016 u32 start, end_addr; 1017 u32 i, j, k, page; 1018 u32 val; 1019 1020 switch (reg_sel) { 1021 case RTW89_DBG_SEL_MAC_00: 1022 p += scnprintf(p, end - p, "Debug selected MAC page 0x00\n"); 1023 start = 0x000; 1024 end_addr = 0x014; 1025 break; 1026 case RTW89_DBG_SEL_MAC_30: 1027 p += scnprintf(p, end - p, "Debug selected MAC page 0x30\n"); 1028 start = 0x030; 1029 end_addr = 0x033; 1030 break; 1031 case RTW89_DBG_SEL_MAC_40: 1032 p += scnprintf(p, end - p, "Debug selected MAC page 0x40\n"); 1033 start = 0x040; 1034 end_addr = 0x07f; 1035 break; 1036 case RTW89_DBG_SEL_MAC_80: 1037 p += scnprintf(p, end - p, "Debug selected MAC page 0x80\n"); 1038 start = 0x080; 1039 end_addr = 0x09f; 1040 break; 1041 case RTW89_DBG_SEL_MAC_C0: 1042 p += scnprintf(p, end - p, "Debug selected MAC page 0xc0\n"); 1043 start = 0x0c0; 1044 end_addr = 0x0df; 1045 break; 1046 case RTW89_DBG_SEL_MAC_E0: 1047 p += scnprintf(p, end - p, "Debug selected MAC page 0xe0\n"); 1048 start = 0x0e0; 1049 end_addr = 0x0ff; 1050 break; 1051 case RTW89_DBG_SEL_BB: 1052 p += scnprintf(p, end - p, "Debug selected BB register\n"); 1053 start = 0x100; 1054 end_addr = 0x17f; 1055 break; 1056 case RTW89_DBG_SEL_IQK: 1057 p += scnprintf(p, end - p, "Debug selected IQK register\n"); 1058 start = 0x180; 1059 end_addr = 0x1bf; 1060 break; 1061 case RTW89_DBG_SEL_RFC: 1062 p += scnprintf(p, end - p, "Debug selected RFC register\n"); 1063 start = 0x1c0; 1064 end_addr = 0x1ff; 1065 break; 1066 default: 1067 p += scnprintf(p, end - p, "Selected invalid register page\n"); 1068 return -EINVAL; 1069 } 1070 1071 for (i = start; i <= end_addr; i++) { 1072 page = i << 8; 1073 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 1074 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + j); 1075 for (k = 0; k < 4; k++) { 1076 val = rtw89_read32(rtwdev, j + (k << 2)); 1077 p += scnprintf(p, end - p, "%08x ", val); 1078 } 1079 p += scnprintf(p, end - p, "\n"); 1080 } 1081 } 1082 1083 return p - buf; 1084 } 1085 1086 static ssize_t 1087 rtw89_debug_priv_mac_mem_dump_select(struct rtw89_dev *rtwdev, 1088 struct rtw89_debugfs_priv *debugfs_priv, 1089 const char *buf, size_t count) 1090 { 1091 u32 sel, start_addr, len; 1092 int num; 1093 1094 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 1095 if (num != 3) { 1096 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 1097 return -EINVAL; 1098 } 1099 1100 debugfs_priv->mac_mem.sel = sel; 1101 debugfs_priv->mac_mem.start = start_addr; 1102 debugfs_priv->mac_mem.len = len; 1103 1104 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 1105 sel, start_addr, len); 1106 1107 return count; 1108 } 1109 1110 static int rtw89_debug_dump_mac_mem(struct rtw89_dev *rtwdev, 1111 char *buf, size_t bufsz, 1112 u8 sel, u32 start_addr, u32 len) 1113 { 1114 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1115 u32 filter_model_addr = mac->filter_model_addr; 1116 u32 indir_access_addr = mac->indir_access_addr; 1117 u32 base_addr, start_page, residue; 1118 char *p = buf, *end = buf + bufsz; 1119 u32 i, j, pp, pages; 1120 u32 dump_len, remain; 1121 u32 val; 1122 1123 remain = len; 1124 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 1125 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 1126 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 1127 base_addr = mac->mem_base_addrs[sel]; 1128 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 1129 1130 for (pp = 0; pp < pages; pp++) { 1131 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 1132 rtw89_write32(rtwdev, filter_model_addr, base_addr); 1133 for (i = indir_access_addr + residue; 1134 i < indir_access_addr + dump_len;) { 1135 p += scnprintf(p, end - p, "%08xh:", i); 1136 for (j = 0; 1137 j < 4 && i < indir_access_addr + dump_len; 1138 j++, i += 4) { 1139 val = rtw89_read32(rtwdev, i); 1140 p += scnprintf(p, end - p, " %08x", val); 1141 remain -= 4; 1142 } 1143 p += scnprintf(p, end - p, "\n"); 1144 } 1145 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 1146 } 1147 1148 return p - buf; 1149 } 1150 1151 static ssize_t 1152 rtw89_debug_priv_mac_mem_dump_get(struct rtw89_dev *rtwdev, 1153 struct rtw89_debugfs_priv *debugfs_priv, 1154 char *buf, size_t bufsz) 1155 { 1156 char *p = buf, *end = buf + bufsz; 1157 bool grant_read = false; 1158 1159 lockdep_assert_wiphy(rtwdev->hw->wiphy); 1160 1161 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 1162 return -ENOENT; 1163 1164 if (rtwdev->chip->chip_id == RTL8852C) { 1165 switch (debugfs_priv->mac_mem.sel) { 1166 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 1167 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 1168 case RTW89_MAC_MEM_TXDATA_FIFO_0: 1169 case RTW89_MAC_MEM_TXDATA_FIFO_1: 1170 grant_read = true; 1171 break; 1172 default: 1173 break; 1174 } 1175 } 1176 1177 rtw89_leave_ps_mode(rtwdev); 1178 if (grant_read) 1179 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1180 p += rtw89_debug_dump_mac_mem(rtwdev, p, end - p, 1181 debugfs_priv->mac_mem.sel, 1182 debugfs_priv->mac_mem.start, 1183 debugfs_priv->mac_mem.len); 1184 if (grant_read) 1185 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1186 1187 return p - buf; 1188 } 1189 1190 static ssize_t 1191 rtw89_debug_priv_mac_dbg_port_dump_select(struct rtw89_dev *rtwdev, 1192 struct rtw89_debugfs_priv *debugfs_priv, 1193 const char *buf, size_t count) 1194 { 1195 int sel, set; 1196 int num; 1197 bool enable; 1198 1199 num = sscanf(buf, "%d %d", &sel, &set); 1200 if (num != 2) { 1201 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 1202 return -EINVAL; 1203 } 1204 1205 enable = set != 0; 1206 switch (sel) { 1207 case 0: 1208 debugfs_priv->dbgpkg_en.ss_dbg = enable; 1209 break; 1210 case 1: 1211 debugfs_priv->dbgpkg_en.dle_dbg = enable; 1212 break; 1213 case 2: 1214 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 1215 break; 1216 case 3: 1217 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 1218 break; 1219 case 4: 1220 debugfs_priv->dbgpkg_en.dbg_port = enable; 1221 break; 1222 default: 1223 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 1224 return -EINVAL; 1225 } 1226 1227 rtw89_info(rtwdev, "%s debug port dump %d\n", 1228 enable ? "Enable" : "Disable", sel); 1229 1230 return count; 1231 } 1232 1233 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 1234 char *buf, size_t bufsz) 1235 { 1236 return 0; 1237 } 1238 1239 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 1240 char *buf, size_t bufsz) 1241 { 1242 #define DLE_DFI_DUMP(__type, __target, __sel) \ 1243 ({ \ 1244 u32 __ctrl; \ 1245 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 1246 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 1247 u32 __data, __val32; \ 1248 int __ret; \ 1249 \ 1250 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 1251 DLE_DFI_TYPE_##__target) | \ 1252 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 1253 B_AX_WDE_DFI_ACTIVE; \ 1254 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 1255 __ret = read_poll_timeout(rtw89_read32, __val32, \ 1256 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 1257 1000, 50000, false, \ 1258 rtwdev, __reg_ctrl); \ 1259 if (__ret) { \ 1260 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 1261 #__type, #__target, __sel); \ 1262 return __ret; \ 1263 } \ 1264 \ 1265 __data = rtw89_read32(rtwdev, __reg_data); \ 1266 __data; \ 1267 }) 1268 1269 #define DLE_DFI_FREE_PAGE_DUMP(__p, __end, __type) \ 1270 ({ \ 1271 u32 __freepg, __pubpg; \ 1272 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 1273 \ 1274 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 1275 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 1276 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 1277 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 1278 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 1279 __p += scnprintf(__p, __end - __p, "[%s] freepg head: %d\n", \ 1280 #__type, __freepg_head); \ 1281 __p += scnprintf(__p, __end - __p, "[%s] freepg tail: %d\n", \ 1282 #__type, __freepg_tail); \ 1283 __p += scnprintf(__p, __end - __p, "[%s] pubpg num : %d\n", \ 1284 #__type, __pubpg_num); \ 1285 }) 1286 1287 #define case_QUOTA(__p, __end, __type, __id) \ 1288 case __type##_QTAID_##__id: \ 1289 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 1290 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 1291 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 1292 __p += scnprintf(__p, __end - __p, "[%s][%s] rsv_pgnum: %d\n", \ 1293 #__type, #__id, rsv_pgnum); \ 1294 __p += scnprintf(__p, __end - __p, "[%s][%s] use_pgnum: %d\n", \ 1295 #__type, #__id, use_pgnum); \ 1296 break 1297 char *p = buf, *end = buf + bufsz; 1298 u32 quota_id; 1299 u32 val32; 1300 u16 rsv_pgnum, use_pgnum; 1301 int ret; 1302 1303 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1304 if (ret) { 1305 p += scnprintf(p, end - p, "[DLE] : DMAC not enabled\n"); 1306 goto out; 1307 } 1308 1309 DLE_DFI_FREE_PAGE_DUMP(p, end, WDE); 1310 DLE_DFI_FREE_PAGE_DUMP(p, end, PLE); 1311 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 1312 switch (quota_id) { 1313 case_QUOTA(p, end, WDE, HOST_IF); 1314 case_QUOTA(p, end, WDE, WLAN_CPU); 1315 case_QUOTA(p, end, WDE, DATA_CPU); 1316 case_QUOTA(p, end, WDE, PKTIN); 1317 case_QUOTA(p, end, WDE, CPUIO); 1318 } 1319 } 1320 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 1321 switch (quota_id) { 1322 case_QUOTA(p, end, PLE, B0_TXPL); 1323 case_QUOTA(p, end, PLE, B1_TXPL); 1324 case_QUOTA(p, end, PLE, C2H); 1325 case_QUOTA(p, end, PLE, H2C); 1326 case_QUOTA(p, end, PLE, WLAN_CPU); 1327 case_QUOTA(p, end, PLE, MPDU); 1328 case_QUOTA(p, end, PLE, CMAC0_RX); 1329 case_QUOTA(p, end, PLE, CMAC1_RX); 1330 case_QUOTA(p, end, PLE, CMAC1_BBRPT); 1331 case_QUOTA(p, end, PLE, WDRLS); 1332 case_QUOTA(p, end, PLE, CPUIO); 1333 } 1334 } 1335 1336 out: 1337 return p - buf; 1338 1339 #undef case_QUOTA 1340 #undef DLE_DFI_DUMP 1341 #undef DLE_DFI_FREE_PAGE_DUMP 1342 } 1343 1344 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 1345 char *buf, size_t bufsz) 1346 { 1347 const struct rtw89_chip_info *chip = rtwdev->chip; 1348 char *p = buf, *end = buf + bufsz; 1349 u32 dmac_err; 1350 int i, ret; 1351 1352 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1353 if (ret) { 1354 p += scnprintf(p, end - p, "[DMAC] : DMAC not enabled\n"); 1355 goto out; 1356 } 1357 1358 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1359 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1360 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1361 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1362 1363 if (dmac_err) { 1364 p += scnprintf(p, end - p, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1365 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1366 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1367 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1368 if (chip->chip_id == RTL8852C) { 1369 p += scnprintf(p, end - p, 1370 "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1371 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1372 p += scnprintf(p, end - p, 1373 "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1374 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1375 p += scnprintf(p, end - p, 1376 "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1377 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1378 p += scnprintf(p, end - p, 1379 "R_AX_PLE_DBGERR_STS=0x%08x\n", 1380 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1381 } 1382 } 1383 1384 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1385 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1386 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1387 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1388 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1389 if (chip->chip_id == RTL8852C) 1390 p += scnprintf(p, end - p, 1391 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1392 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1393 else 1394 p += scnprintf(p, end - p, 1395 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1396 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1397 } 1398 1399 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1400 if (chip->chip_id == RTL8852C) { 1401 p += scnprintf(p, end - p, 1402 "R_AX_SEC_ERR_IMR=0x%08x\n", 1403 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1404 p += scnprintf(p, end - p, 1405 "R_AX_SEC_ERR_ISR=0x%08x\n", 1406 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1407 p += scnprintf(p, end - p, 1408 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1409 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1410 p += scnprintf(p, end - p, 1411 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1412 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1413 p += scnprintf(p, end - p, 1414 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1415 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1416 p += scnprintf(p, end - p, 1417 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1418 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1419 p += scnprintf(p, end - p, "R_AX_SEC_DEBUG1=0x%08x\n", 1420 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1421 p += scnprintf(p, end - p, 1422 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1423 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1424 p += scnprintf(p, end - p, 1425 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1426 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1427 1428 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1429 B_AX_DBG_SEL0, 0x8B); 1430 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1431 B_AX_DBG_SEL1, 0x8B); 1432 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1433 B_AX_SEL_0XC0_MASK, 1); 1434 for (i = 0; i < 0x10; i++) { 1435 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1436 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1437 p += scnprintf(p, end - p, 1438 "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1439 i, 1440 rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1441 } 1442 } else { 1443 p += scnprintf(p, end - p, 1444 "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1445 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1446 p += scnprintf(p, end - p, 1447 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1448 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1449 p += scnprintf(p, end - p, 1450 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1451 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1452 p += scnprintf(p, end - p, 1453 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1454 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1455 p += scnprintf(p, end - p, 1456 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1457 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1458 p += scnprintf(p, end - p, 1459 "R_AX_SEC_CAM_WDATA=0x%08x\n", 1460 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1461 p += scnprintf(p, end - p, 1462 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1463 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1464 p += scnprintf(p, end - p, 1465 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1466 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1467 p += scnprintf(p, end - p, 1468 "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1469 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1470 p += scnprintf(p, end - p, 1471 "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1472 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1473 } 1474 } 1475 1476 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1477 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1478 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1479 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1480 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1481 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1482 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1483 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1484 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1485 } 1486 1487 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1488 p += scnprintf(p, end - p, 1489 "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1490 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1491 p += scnprintf(p, end - p, 1492 "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1493 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1494 } 1495 1496 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1497 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1498 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1499 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1500 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1501 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1502 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1503 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1504 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1505 } 1506 1507 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1508 if (chip->chip_id == RTL8852C) { 1509 p += scnprintf(p, end - p, 1510 "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1511 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1512 p += scnprintf(p, end - p, 1513 "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1514 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1515 p += scnprintf(p, end - p, 1516 "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1517 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1518 p += scnprintf(p, end - p, 1519 "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1520 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1521 } else { 1522 p += scnprintf(p, end - p, 1523 "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1524 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1525 p += scnprintf(p, end - p, 1526 "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1527 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1528 } 1529 } 1530 1531 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1532 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1533 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1534 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1535 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1536 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1537 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1538 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1539 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1540 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1541 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1542 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1543 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1544 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1545 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1546 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1547 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1548 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1549 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1550 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1551 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1552 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1553 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1554 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1555 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1556 if (chip->chip_id == RTL8852C) { 1557 p += scnprintf(p, end - p, "R_AX_RX_CTRL0=0x%08x\n", 1558 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1559 p += scnprintf(p, end - p, "R_AX_RX_CTRL1=0x%08x\n", 1560 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1561 p += scnprintf(p, end - p, "R_AX_RX_CTRL2=0x%08x\n", 1562 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1563 } else { 1564 p += scnprintf(p, end - p, 1565 "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1566 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1567 p += scnprintf(p, end - p, 1568 "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1569 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1570 p += scnprintf(p, end - p, 1571 "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1572 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1573 } 1574 } 1575 1576 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1577 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1578 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1579 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1580 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1581 } 1582 1583 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1584 p += scnprintf(p, end - p, 1585 "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1586 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1587 p += scnprintf(p, end - p, 1588 "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1589 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1590 p += scnprintf(p, end - p, 1591 "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1592 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1593 p += scnprintf(p, end - p, 1594 "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1595 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1596 p += scnprintf(p, end - p, 1597 "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1598 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1599 p += scnprintf(p, end - p, 1600 "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1601 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1602 } 1603 1604 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1605 if (chip->chip_id == RTL8852C) { 1606 p += scnprintf(p, end - p, 1607 "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1608 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1609 p += scnprintf(p, end - p, 1610 "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1611 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1612 p += scnprintf(p, end - p, 1613 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1614 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1615 p += scnprintf(p, end - p, 1616 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1617 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1618 p += scnprintf(p, end - p, 1619 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1620 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1621 p += scnprintf(p, end - p, 1622 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1623 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1624 } else { 1625 p += scnprintf(p, end - p, 1626 "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1627 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1628 p += scnprintf(p, end - p, 1629 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1630 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1631 p += scnprintf(p, end - p, 1632 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1633 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1634 p += scnprintf(p, end - p, 1635 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1636 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1637 p += scnprintf(p, end - p, 1638 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1639 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1640 } 1641 } 1642 1643 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1644 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1645 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1646 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1647 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1648 } 1649 1650 out: 1651 return p - buf; 1652 } 1653 1654 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1655 char *buf, size_t bufsz, 1656 enum rtw89_mac_idx band) 1657 { 1658 const struct rtw89_chip_info *chip = rtwdev->chip; 1659 char *p = buf, *end = buf + bufsz; 1660 u32 offset = 0; 1661 u32 cmac_err; 1662 int ret; 1663 1664 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1665 if (ret) { 1666 if (band) 1667 p += scnprintf(p, end - p, 1668 "[CMAC] : CMAC1 not enabled\n"); 1669 else 1670 p += scnprintf(p, end - p, 1671 "[CMAC] : CMAC0 not enabled\n"); 1672 goto out; 1673 } 1674 1675 if (band) 1676 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1677 1678 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1679 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1680 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1681 p += scnprintf(p, end - p, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1682 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1683 p += scnprintf(p, end - p, "R_AX_CK_EN [%d]=0x%08x\n", band, 1684 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1685 1686 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1687 p += scnprintf(p, end - p, 1688 "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1689 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1690 p += scnprintf(p, end - p, 1691 "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1692 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1693 } 1694 1695 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1696 p += scnprintf(p, end - p, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", 1697 band, 1698 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1699 p += scnprintf(p, end - p, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", 1700 band, 1701 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1702 } 1703 1704 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1705 if (chip->chip_id == RTL8852C) { 1706 p += scnprintf(p, end - p, 1707 "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1708 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1709 p += scnprintf(p, end - p, 1710 "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", 1711 band, 1712 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1713 } else { 1714 p += scnprintf(p, end - p, 1715 "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1716 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1717 } 1718 } 1719 1720 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1721 if (chip->chip_id == RTL8852C) { 1722 p += scnprintf(p, end - p, 1723 "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", 1724 band, 1725 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1726 p += scnprintf(p, end - p, 1727 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1728 band, 1729 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1730 } else { 1731 p += scnprintf(p, end - p, 1732 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1733 band, 1734 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1735 } 1736 } 1737 1738 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1739 p += scnprintf(p, end - p, "R_AX_TXPWR_IMR [%d]=0x%08x\n", 1740 band, 1741 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1742 p += scnprintf(p, end - p, "R_AX_TXPWR_ISR [%d]=0x%08x\n", 1743 band, 1744 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1745 } 1746 1747 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1748 if (chip->chip_id == RTL8852C) { 1749 p += scnprintf(p, end - p, 1750 "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", 1751 band, 1752 rtw89_read32(rtwdev, 1753 R_AX_TRXPTCL_ERROR_INDICA + offset)); 1754 p += scnprintf(p, end - p, 1755 "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", 1756 band, 1757 rtw89_read32(rtwdev, 1758 R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1759 } else { 1760 p += scnprintf(p, end - p, 1761 "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", 1762 band, 1763 rtw89_read32(rtwdev, 1764 R_AX_TMAC_ERR_IMR_ISR + offset)); 1765 } 1766 p += scnprintf(p, end - p, 1767 "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1768 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1769 } 1770 1771 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1772 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1773 1774 out: 1775 return p - buf; 1776 } 1777 1778 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1779 char *buf, size_t bufsz) 1780 { 1781 char *p = buf, *end = buf + bufsz; 1782 1783 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_0); 1784 if (rtwdev->dbcc_en) 1785 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_1); 1786 1787 return p - buf; 1788 } 1789 1790 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1791 .sel_addr = R_AX_PTCL_DBG, 1792 .sel_byte = 1, 1793 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1794 .srt = 0x00, 1795 .end = 0x3F, 1796 .rd_addr = R_AX_PTCL_DBG_INFO, 1797 .rd_byte = 4, 1798 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1799 }; 1800 1801 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1802 .sel_addr = R_AX_PTCL_DBG_C1, 1803 .sel_byte = 1, 1804 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1805 .srt = 0x00, 1806 .end = 0x3F, 1807 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1808 .rd_byte = 4, 1809 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1810 }; 1811 1812 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1813 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1814 .sel_byte = 2, 1815 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1816 .srt = 0x0, 1817 .end = 0xD, 1818 .rd_addr = R_AX_DBG_PORT_SEL, 1819 .rd_byte = 4, 1820 .rd_msk = B_AX_DEBUG_ST_MASK 1821 }; 1822 1823 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1824 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1825 .sel_byte = 2, 1826 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1827 .srt = 0x0, 1828 .end = 0x5, 1829 .rd_addr = R_AX_DBG_PORT_SEL, 1830 .rd_byte = 4, 1831 .rd_msk = B_AX_DEBUG_ST_MASK 1832 }; 1833 1834 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1835 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1836 .sel_byte = 2, 1837 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1838 .srt = 0x0, 1839 .end = 0x9, 1840 .rd_addr = R_AX_DBG_PORT_SEL, 1841 .rd_byte = 4, 1842 .rd_msk = B_AX_DEBUG_ST_MASK 1843 }; 1844 1845 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1846 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1847 .sel_byte = 2, 1848 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1849 .srt = 0x0, 1850 .end = 0x3, 1851 .rd_addr = R_AX_DBG_PORT_SEL, 1852 .rd_byte = 4, 1853 .rd_msk = B_AX_DEBUG_ST_MASK 1854 }; 1855 1856 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1857 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1858 .sel_byte = 2, 1859 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1860 .srt = 0x0, 1861 .end = 0x1, 1862 .rd_addr = R_AX_DBG_PORT_SEL, 1863 .rd_byte = 4, 1864 .rd_msk = B_AX_DEBUG_ST_MASK 1865 }; 1866 1867 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1868 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1869 .sel_byte = 2, 1870 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1871 .srt = 0x0, 1872 .end = 0x0, 1873 .rd_addr = R_AX_DBG_PORT_SEL, 1874 .rd_byte = 4, 1875 .rd_msk = B_AX_DEBUG_ST_MASK 1876 }; 1877 1878 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1879 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1880 .sel_byte = 2, 1881 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1882 .srt = 0x0, 1883 .end = 0xB, 1884 .rd_addr = R_AX_DBG_PORT_SEL, 1885 .rd_byte = 4, 1886 .rd_msk = B_AX_DEBUG_ST_MASK 1887 }; 1888 1889 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1890 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1891 .sel_byte = 2, 1892 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1893 .srt = 0x0, 1894 .end = 0x4, 1895 .rd_addr = R_AX_DBG_PORT_SEL, 1896 .rd_byte = 4, 1897 .rd_msk = B_AX_DEBUG_ST_MASK 1898 }; 1899 1900 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1901 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1902 .sel_byte = 2, 1903 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1904 .srt = 0x0, 1905 .end = 0x8, 1906 .rd_addr = R_AX_DBG_PORT_SEL, 1907 .rd_byte = 4, 1908 .rd_msk = B_AX_DEBUG_ST_MASK 1909 }; 1910 1911 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1912 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1913 .sel_byte = 2, 1914 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1915 .srt = 0x0, 1916 .end = 0x7, 1917 .rd_addr = R_AX_DBG_PORT_SEL, 1918 .rd_byte = 4, 1919 .rd_msk = B_AX_DEBUG_ST_MASK 1920 }; 1921 1922 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 1923 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1924 .sel_byte = 2, 1925 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1926 .srt = 0x0, 1927 .end = 0x1, 1928 .rd_addr = R_AX_DBG_PORT_SEL, 1929 .rd_byte = 4, 1930 .rd_msk = B_AX_DEBUG_ST_MASK 1931 }; 1932 1933 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 1934 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1935 .sel_byte = 2, 1936 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1937 .srt = 0x0, 1938 .end = 0x3, 1939 .rd_addr = R_AX_DBG_PORT_SEL, 1940 .rd_byte = 4, 1941 .rd_msk = B_AX_DEBUG_ST_MASK 1942 }; 1943 1944 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 1945 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1946 .sel_byte = 2, 1947 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1948 .srt = 0x0, 1949 .end = 0x0, 1950 .rd_addr = R_AX_DBG_PORT_SEL, 1951 .rd_byte = 4, 1952 .rd_msk = B_AX_DEBUG_ST_MASK 1953 }; 1954 1955 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 1956 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1957 .sel_byte = 2, 1958 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1959 .srt = 0x0, 1960 .end = 0x8, 1961 .rd_addr = R_AX_DBG_PORT_SEL, 1962 .rd_byte = 4, 1963 .rd_msk = B_AX_DEBUG_ST_MASK 1964 }; 1965 1966 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 1967 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1968 .sel_byte = 2, 1969 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1970 .srt = 0x0, 1971 .end = 0x0, 1972 .rd_addr = R_AX_DBG_PORT_SEL, 1973 .rd_byte = 4, 1974 .rd_msk = B_AX_DEBUG_ST_MASK 1975 }; 1976 1977 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 1978 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1979 .sel_byte = 2, 1980 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1981 .srt = 0x0, 1982 .end = 0x6, 1983 .rd_addr = R_AX_DBG_PORT_SEL, 1984 .rd_byte = 4, 1985 .rd_msk = B_AX_DEBUG_ST_MASK 1986 }; 1987 1988 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 1989 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1990 .sel_byte = 2, 1991 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1992 .srt = 0x0, 1993 .end = 0x0, 1994 .rd_addr = R_AX_DBG_PORT_SEL, 1995 .rd_byte = 4, 1996 .rd_msk = B_AX_DEBUG_ST_MASK 1997 }; 1998 1999 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 2000 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2001 .sel_byte = 2, 2002 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2003 .srt = 0x0, 2004 .end = 0x0, 2005 .rd_addr = R_AX_DBG_PORT_SEL, 2006 .rd_byte = 4, 2007 .rd_msk = B_AX_DEBUG_ST_MASK 2008 }; 2009 2010 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 2011 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2012 .sel_byte = 1, 2013 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2014 .srt = 0x0, 2015 .end = 0x3, 2016 .rd_addr = R_AX_DBG_PORT_SEL, 2017 .rd_byte = 4, 2018 .rd_msk = B_AX_DEBUG_ST_MASK 2019 }; 2020 2021 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 2022 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2023 .sel_byte = 1, 2024 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2025 .srt = 0x0, 2026 .end = 0x6, 2027 .rd_addr = R_AX_DBG_PORT_SEL, 2028 .rd_byte = 4, 2029 .rd_msk = B_AX_DEBUG_ST_MASK 2030 }; 2031 2032 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 2033 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2034 .sel_byte = 1, 2035 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2036 .srt = 0x0, 2037 .end = 0x0, 2038 .rd_addr = R_AX_DBG_PORT_SEL, 2039 .rd_byte = 4, 2040 .rd_msk = B_AX_DEBUG_ST_MASK 2041 }; 2042 2043 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 2044 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2045 .sel_byte = 1, 2046 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2047 .srt = 0x8, 2048 .end = 0xE, 2049 .rd_addr = R_AX_DBG_PORT_SEL, 2050 .rd_byte = 4, 2051 .rd_msk = B_AX_DEBUG_ST_MASK 2052 }; 2053 2054 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 2055 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2056 .sel_byte = 1, 2057 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2058 .srt = 0x0, 2059 .end = 0x5, 2060 .rd_addr = R_AX_DBG_PORT_SEL, 2061 .rd_byte = 4, 2062 .rd_msk = B_AX_DEBUG_ST_MASK 2063 }; 2064 2065 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 2066 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2067 .sel_byte = 1, 2068 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2069 .srt = 0x0, 2070 .end = 0x6, 2071 .rd_addr = R_AX_DBG_PORT_SEL, 2072 .rd_byte = 4, 2073 .rd_msk = B_AX_DEBUG_ST_MASK 2074 }; 2075 2076 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 2077 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2078 .sel_byte = 1, 2079 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2080 .srt = 0x0, 2081 .end = 0xF, 2082 .rd_addr = R_AX_DBG_PORT_SEL, 2083 .rd_byte = 4, 2084 .rd_msk = B_AX_DEBUG_ST_MASK 2085 }; 2086 2087 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 2088 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2089 .sel_byte = 1, 2090 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2091 .srt = 0x0, 2092 .end = 0x9, 2093 .rd_addr = R_AX_DBG_PORT_SEL, 2094 .rd_byte = 4, 2095 .rd_msk = B_AX_DEBUG_ST_MASK 2096 }; 2097 2098 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 2099 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2100 .sel_byte = 1, 2101 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2102 .srt = 0x0, 2103 .end = 0x3, 2104 .rd_addr = R_AX_DBG_PORT_SEL, 2105 .rd_byte = 4, 2106 .rd_msk = B_AX_DEBUG_ST_MASK 2107 }; 2108 2109 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 2110 .sel_addr = R_AX_SCH_DBG_SEL, 2111 .sel_byte = 1, 2112 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2113 .srt = 0x00, 2114 .end = 0x2F, 2115 .rd_addr = R_AX_SCH_DBG, 2116 .rd_byte = 4, 2117 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2118 }; 2119 2120 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 2121 .sel_addr = R_AX_SCH_DBG_SEL_C1, 2122 .sel_byte = 1, 2123 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2124 .srt = 0x00, 2125 .end = 0x2F, 2126 .rd_addr = R_AX_SCH_DBG_C1, 2127 .rd_byte = 4, 2128 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2129 }; 2130 2131 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 2132 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 2133 .sel_byte = 1, 2134 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2135 .srt = 0x00, 2136 .end = 0x19, 2137 .rd_addr = R_AX_DBG_PORT_SEL, 2138 .rd_byte = 4, 2139 .rd_msk = B_AX_DEBUG_ST_MASK 2140 }; 2141 2142 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 2143 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 2144 .sel_byte = 1, 2145 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2146 .srt = 0x00, 2147 .end = 0x19, 2148 .rd_addr = R_AX_DBG_PORT_SEL, 2149 .rd_byte = 4, 2150 .rd_msk = B_AX_DEBUG_ST_MASK 2151 }; 2152 2153 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 2154 .sel_addr = R_AX_RX_DEBUG_SELECT, 2155 .sel_byte = 1, 2156 .sel_msk = B_AX_DEBUG_SEL_MASK, 2157 .srt = 0x00, 2158 .end = 0x58, 2159 .rd_addr = R_AX_DBG_PORT_SEL, 2160 .rd_byte = 4, 2161 .rd_msk = B_AX_DEBUG_ST_MASK 2162 }; 2163 2164 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 2165 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 2166 .sel_byte = 1, 2167 .sel_msk = B_AX_DEBUG_SEL_MASK, 2168 .srt = 0x00, 2169 .end = 0x58, 2170 .rd_addr = R_AX_DBG_PORT_SEL, 2171 .rd_byte = 4, 2172 .rd_msk = B_AX_DEBUG_ST_MASK 2173 }; 2174 2175 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 2176 .sel_addr = R_AX_RX_STATE_MONITOR, 2177 .sel_byte = 1, 2178 .sel_msk = B_AX_STATE_SEL_MASK, 2179 .srt = 0x00, 2180 .end = 0x17, 2181 .rd_addr = R_AX_RX_STATE_MONITOR, 2182 .rd_byte = 4, 2183 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2184 }; 2185 2186 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 2187 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 2188 .sel_byte = 1, 2189 .sel_msk = B_AX_STATE_SEL_MASK, 2190 .srt = 0x00, 2191 .end = 0x17, 2192 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 2193 .rd_byte = 4, 2194 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2195 }; 2196 2197 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 2198 .sel_addr = R_AX_RMAC_PLCP_MON, 2199 .sel_byte = 4, 2200 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2201 .srt = 0x0, 2202 .end = 0xF, 2203 .rd_addr = R_AX_RMAC_PLCP_MON, 2204 .rd_byte = 4, 2205 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2206 }; 2207 2208 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 2209 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 2210 .sel_byte = 4, 2211 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2212 .srt = 0x0, 2213 .end = 0xF, 2214 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 2215 .rd_byte = 4, 2216 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2217 }; 2218 2219 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 2220 .sel_addr = R_AX_DBGSEL_TRXPTCL, 2221 .sel_byte = 1, 2222 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2223 .srt = 0x08, 2224 .end = 0x10, 2225 .rd_addr = R_AX_DBG_PORT_SEL, 2226 .rd_byte = 4, 2227 .rd_msk = B_AX_DEBUG_ST_MASK 2228 }; 2229 2230 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 2231 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 2232 .sel_byte = 1, 2233 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2234 .srt = 0x08, 2235 .end = 0x10, 2236 .rd_addr = R_AX_DBG_PORT_SEL, 2237 .rd_byte = 4, 2238 .rd_msk = B_AX_DEBUG_ST_MASK 2239 }; 2240 2241 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 2242 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2243 .sel_byte = 1, 2244 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2245 .srt = 0x00, 2246 .end = 0x07, 2247 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 2248 .rd_byte = 4, 2249 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2250 }; 2251 2252 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 2253 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2254 .sel_byte = 1, 2255 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2256 .srt = 0x00, 2257 .end = 0x07, 2258 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 2259 .rd_byte = 4, 2260 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2261 }; 2262 2263 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 2264 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2265 .sel_byte = 1, 2266 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2267 .srt = 0x00, 2268 .end = 0x07, 2269 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 2270 .rd_byte = 4, 2271 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2272 }; 2273 2274 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 2275 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2276 .sel_byte = 1, 2277 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2278 .srt = 0x00, 2279 .end = 0x07, 2280 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 2281 .rd_byte = 4, 2282 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2283 }; 2284 2285 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 2286 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2287 .sel_byte = 1, 2288 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2289 .srt = 0x00, 2290 .end = 0x04, 2291 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 2292 .rd_byte = 4, 2293 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2294 }; 2295 2296 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 2297 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2298 .sel_byte = 1, 2299 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2300 .srt = 0x00, 2301 .end = 0x04, 2302 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 2303 .rd_byte = 4, 2304 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2305 }; 2306 2307 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 2308 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2309 .sel_byte = 1, 2310 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2311 .srt = 0x00, 2312 .end = 0x04, 2313 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 2314 .rd_byte = 4, 2315 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2316 }; 2317 2318 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 2319 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2320 .sel_byte = 1, 2321 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2322 .srt = 0x00, 2323 .end = 0x04, 2324 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 2325 .rd_byte = 4, 2326 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2327 }; 2328 2329 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 2330 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2331 .sel_byte = 4, 2332 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2333 .srt = 0x80000000, 2334 .end = 0x80000001, 2335 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2336 .rd_byte = 4, 2337 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2338 }; 2339 2340 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 2341 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2342 .sel_byte = 4, 2343 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2344 .srt = 0x80010000, 2345 .end = 0x80010004, 2346 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2347 .rd_byte = 4, 2348 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2349 }; 2350 2351 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 2352 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2353 .sel_byte = 4, 2354 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2355 .srt = 0x80020000, 2356 .end = 0x80020FFF, 2357 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2358 .rd_byte = 4, 2359 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2360 }; 2361 2362 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 2363 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2364 .sel_byte = 4, 2365 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2366 .srt = 0x80030000, 2367 .end = 0x80030FFF, 2368 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2369 .rd_byte = 4, 2370 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2371 }; 2372 2373 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 2374 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2375 .sel_byte = 4, 2376 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2377 .srt = 0x80040000, 2378 .end = 0x80040FFF, 2379 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2380 .rd_byte = 4, 2381 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2382 }; 2383 2384 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 2385 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2386 .sel_byte = 4, 2387 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2388 .srt = 0x80050000, 2389 .end = 0x80050FFF, 2390 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2391 .rd_byte = 4, 2392 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2393 }; 2394 2395 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 2396 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2397 .sel_byte = 4, 2398 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2399 .srt = 0x80060000, 2400 .end = 0x80060453, 2401 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2402 .rd_byte = 4, 2403 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2404 }; 2405 2406 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 2407 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2408 .sel_byte = 4, 2409 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2410 .srt = 0x80070000, 2411 .end = 0x80070011, 2412 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2413 .rd_byte = 4, 2414 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2415 }; 2416 2417 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 2418 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2419 .sel_byte = 4, 2420 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2421 .srt = 0x80000000, 2422 .end = 0x80000001, 2423 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2424 .rd_byte = 4, 2425 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2426 }; 2427 2428 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 2429 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2430 .sel_byte = 4, 2431 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2432 .srt = 0x80010000, 2433 .end = 0x8001000A, 2434 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2435 .rd_byte = 4, 2436 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2437 }; 2438 2439 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2440 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2441 .sel_byte = 4, 2442 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2443 .srt = 0x80020000, 2444 .end = 0x80020DBF, 2445 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2446 .rd_byte = 4, 2447 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2448 }; 2449 2450 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2451 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2452 .sel_byte = 4, 2453 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2454 .srt = 0x80030000, 2455 .end = 0x80030DBF, 2456 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2457 .rd_byte = 4, 2458 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2459 }; 2460 2461 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2462 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2463 .sel_byte = 4, 2464 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2465 .srt = 0x80040000, 2466 .end = 0x80040DBF, 2467 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2468 .rd_byte = 4, 2469 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2470 }; 2471 2472 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2473 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2474 .sel_byte = 4, 2475 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2476 .srt = 0x80050000, 2477 .end = 0x80050DBF, 2478 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2479 .rd_byte = 4, 2480 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2481 }; 2482 2483 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2484 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2485 .sel_byte = 4, 2486 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2487 .srt = 0x80060000, 2488 .end = 0x80060041, 2489 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2490 .rd_byte = 4, 2491 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2492 }; 2493 2494 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2495 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2496 .sel_byte = 4, 2497 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2498 .srt = 0x80070000, 2499 .end = 0x80070001, 2500 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2501 .rd_byte = 4, 2502 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2503 }; 2504 2505 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2506 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2507 .sel_byte = 4, 2508 .sel_msk = B_AX_DFI_DATA_MASK, 2509 .srt = 0x80000000, 2510 .end = 0x8000017f, 2511 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2512 .rd_byte = 4, 2513 .rd_msk = B_AX_DFI_DATA_MASK 2514 }; 2515 2516 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2517 .sel_addr = R_AX_PCIE_DBG_CTRL, 2518 .sel_byte = 2, 2519 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2520 .srt = 0x00, 2521 .end = 0x03, 2522 .rd_addr = R_AX_DBG_PORT_SEL, 2523 .rd_byte = 4, 2524 .rd_msk = B_AX_DEBUG_ST_MASK 2525 }; 2526 2527 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2528 .sel_addr = R_AX_PCIE_DBG_CTRL, 2529 .sel_byte = 2, 2530 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2531 .srt = 0x00, 2532 .end = 0x04, 2533 .rd_addr = R_AX_DBG_PORT_SEL, 2534 .rd_byte = 4, 2535 .rd_msk = B_AX_DEBUG_ST_MASK 2536 }; 2537 2538 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2539 .sel_addr = R_AX_PCIE_DBG_CTRL, 2540 .sel_byte = 2, 2541 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2542 .srt = 0x00, 2543 .end = 0x01, 2544 .rd_addr = R_AX_DBG_PORT_SEL, 2545 .rd_byte = 4, 2546 .rd_msk = B_AX_DEBUG_ST_MASK 2547 }; 2548 2549 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2550 .sel_addr = R_AX_PCIE_DBG_CTRL, 2551 .sel_byte = 2, 2552 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2553 .srt = 0x00, 2554 .end = 0x05, 2555 .rd_addr = R_AX_DBG_PORT_SEL, 2556 .rd_byte = 4, 2557 .rd_msk = B_AX_DEBUG_ST_MASK 2558 }; 2559 2560 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2561 .sel_addr = R_AX_PCIE_DBG_CTRL, 2562 .sel_byte = 2, 2563 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2564 .srt = 0x00, 2565 .end = 0x05, 2566 .rd_addr = R_AX_DBG_PORT_SEL, 2567 .rd_byte = 4, 2568 .rd_msk = B_AX_DEBUG_ST_MASK 2569 }; 2570 2571 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2572 .sel_addr = R_AX_PCIE_DBG_CTRL, 2573 .sel_byte = 2, 2574 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2575 .srt = 0x00, 2576 .end = 0x06, 2577 .rd_addr = R_AX_DBG_PORT_SEL, 2578 .rd_byte = 4, 2579 .rd_msk = B_AX_DEBUG_ST_MASK 2580 }; 2581 2582 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2583 .sel_addr = R_AX_DBG_CTRL, 2584 .sel_byte = 1, 2585 .sel_msk = B_AX_DBG_SEL0, 2586 .srt = 0x34, 2587 .end = 0x3C, 2588 .rd_addr = R_AX_DBG_PORT_SEL, 2589 .rd_byte = 4, 2590 .rd_msk = B_AX_DEBUG_ST_MASK 2591 }; 2592 2593 static int 2594 rtw89_debug_mac_dbg_port_sel(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 2595 u32 sel, const struct rtw89_mac_dbg_port_info **ppinfo) 2596 { 2597 const struct rtw89_mac_dbg_port_info *info = NULL; 2598 char *p = buf, *end = buf + bufsz; 2599 u32 index; 2600 u32 val32; 2601 u16 val16; 2602 u8 val8; 2603 2604 switch (sel) { 2605 case RTW89_DBG_PORT_SEL_PTCL_C0: 2606 info = &dbg_port_ptcl_c0; 2607 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2608 val16 |= B_AX_PTCL_DBG_EN; 2609 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2610 p += scnprintf(p, end - p, "Enable PTCL C0 dbgport.\n"); 2611 break; 2612 case RTW89_DBG_PORT_SEL_PTCL_C1: 2613 info = &dbg_port_ptcl_c1; 2614 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2615 val16 |= B_AX_PTCL_DBG_EN; 2616 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2617 p += scnprintf(p, end - p, "Enable PTCL C1 dbgport.\n"); 2618 break; 2619 case RTW89_DBG_PORT_SEL_SCH_C0: 2620 info = &dbg_port_sch_c0; 2621 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2622 val32 |= B_AX_SCH_DBG_EN; 2623 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2624 p += scnprintf(p, end - p, "Enable SCH C0 dbgport.\n"); 2625 break; 2626 case RTW89_DBG_PORT_SEL_SCH_C1: 2627 info = &dbg_port_sch_c1; 2628 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2629 val32 |= B_AX_SCH_DBG_EN; 2630 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2631 p += scnprintf(p, end - p, "Enable SCH C1 dbgport.\n"); 2632 break; 2633 case RTW89_DBG_PORT_SEL_TMAC_C0: 2634 info = &dbg_port_tmac_c0; 2635 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2636 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2637 B_AX_DBGSEL_TRXPTCL_MASK); 2638 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2639 2640 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2641 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2642 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2643 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2644 2645 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2646 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2647 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2648 p += scnprintf(p, end - p, "Enable TMAC C0 dbgport.\n"); 2649 break; 2650 case RTW89_DBG_PORT_SEL_TMAC_C1: 2651 info = &dbg_port_tmac_c1; 2652 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2653 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2654 B_AX_DBGSEL_TRXPTCL_MASK); 2655 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2656 2657 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2658 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2659 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2660 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2661 2662 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2663 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2664 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2665 p += scnprintf(p, end - p, "Enable TMAC C1 dbgport.\n"); 2666 break; 2667 case RTW89_DBG_PORT_SEL_RMAC_C0: 2668 info = &dbg_port_rmac_c0; 2669 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2670 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2671 B_AX_DBGSEL_TRXPTCL_MASK); 2672 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2673 2674 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2675 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2676 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2677 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2678 2679 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2680 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2681 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2682 2683 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2684 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2685 B_AX_DBGSEL_TRXPTCL_MASK); 2686 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2687 p += scnprintf(p, end - p, "Enable RMAC C0 dbgport.\n"); 2688 break; 2689 case RTW89_DBG_PORT_SEL_RMAC_C1: 2690 info = &dbg_port_rmac_c1; 2691 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2692 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2693 B_AX_DBGSEL_TRXPTCL_MASK); 2694 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2695 2696 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2697 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2698 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2699 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2700 2701 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2702 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2703 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2704 2705 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2706 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2707 B_AX_DBGSEL_TRXPTCL_MASK); 2708 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2709 p += scnprintf(p, end - p, "Enable RMAC C1 dbgport.\n"); 2710 break; 2711 case RTW89_DBG_PORT_SEL_RMACST_C0: 2712 info = &dbg_port_rmacst_c0; 2713 p += scnprintf(p, end - p, "Enable RMAC state C0 dbgport.\n"); 2714 break; 2715 case RTW89_DBG_PORT_SEL_RMACST_C1: 2716 info = &dbg_port_rmacst_c1; 2717 p += scnprintf(p, end - p, "Enable RMAC state C1 dbgport.\n"); 2718 break; 2719 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2720 info = &dbg_port_rmac_plcp_c0; 2721 p += scnprintf(p, end - p, "Enable RMAC PLCP C0 dbgport.\n"); 2722 break; 2723 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2724 info = &dbg_port_rmac_plcp_c1; 2725 p += scnprintf(p, end - p, "Enable RMAC PLCP C1 dbgport.\n"); 2726 break; 2727 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2728 info = &dbg_port_trxptcl_c0; 2729 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2730 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2731 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2732 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2733 2734 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2735 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2736 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2737 p += scnprintf(p, end - p, "Enable TRXPTCL C0 dbgport.\n"); 2738 break; 2739 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2740 info = &dbg_port_trxptcl_c1; 2741 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2742 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2743 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2744 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2745 2746 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2747 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2748 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2749 p += scnprintf(p, end - p, "Enable TRXPTCL C1 dbgport.\n"); 2750 break; 2751 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2752 info = &dbg_port_tx_infol_c0; 2753 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2754 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2755 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2756 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2757 break; 2758 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2759 info = &dbg_port_tx_infoh_c0; 2760 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2761 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2762 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2763 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2764 break; 2765 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2766 info = &dbg_port_tx_infol_c1; 2767 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2768 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2769 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2770 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2771 break; 2772 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2773 info = &dbg_port_tx_infoh_c1; 2774 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2775 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2776 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2777 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2778 break; 2779 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2780 info = &dbg_port_txtf_infol_c0; 2781 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2782 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2783 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2784 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2785 break; 2786 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2787 info = &dbg_port_txtf_infoh_c0; 2788 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2789 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2790 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2791 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2792 break; 2793 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2794 info = &dbg_port_txtf_infol_c1; 2795 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2796 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2797 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2798 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2799 break; 2800 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2801 info = &dbg_port_txtf_infoh_c1; 2802 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2803 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2804 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2805 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2806 break; 2807 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2808 info = &dbg_port_wde_bufmgn_freepg; 2809 p += scnprintf(p, end - p, "Enable wde bufmgn freepg dump.\n"); 2810 break; 2811 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2812 info = &dbg_port_wde_bufmgn_quota; 2813 p += scnprintf(p, end - p, "Enable wde bufmgn quota dump.\n"); 2814 break; 2815 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2816 info = &dbg_port_wde_bufmgn_pagellt; 2817 p += scnprintf(p, end - p, 2818 "Enable wde bufmgn pagellt dump.\n"); 2819 break; 2820 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2821 info = &dbg_port_wde_bufmgn_pktinfo; 2822 p += scnprintf(p, end - p, 2823 "Enable wde bufmgn pktinfo dump.\n"); 2824 break; 2825 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2826 info = &dbg_port_wde_quemgn_prepkt; 2827 p += scnprintf(p, end - p, "Enable wde quemgn prepkt dump.\n"); 2828 break; 2829 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2830 info = &dbg_port_wde_quemgn_nxtpkt; 2831 p += scnprintf(p, end - p, "Enable wde quemgn nxtpkt dump.\n"); 2832 break; 2833 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2834 info = &dbg_port_wde_quemgn_qlnktbl; 2835 p += scnprintf(p, end - p, 2836 "Enable wde quemgn qlnktbl dump.\n"); 2837 break; 2838 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2839 info = &dbg_port_wde_quemgn_qempty; 2840 p += scnprintf(p, end - p, "Enable wde quemgn qempty dump.\n"); 2841 break; 2842 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2843 info = &dbg_port_ple_bufmgn_freepg; 2844 p += scnprintf(p, end - p, "Enable ple bufmgn freepg dump.\n"); 2845 break; 2846 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2847 info = &dbg_port_ple_bufmgn_quota; 2848 p += scnprintf(p, end - p, "Enable ple bufmgn quota dump.\n"); 2849 break; 2850 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2851 info = &dbg_port_ple_bufmgn_pagellt; 2852 p += scnprintf(p, end - p, 2853 "Enable ple bufmgn pagellt dump.\n"); 2854 break; 2855 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2856 info = &dbg_port_ple_bufmgn_pktinfo; 2857 p += scnprintf(p, end - p, 2858 "Enable ple bufmgn pktinfo dump.\n"); 2859 break; 2860 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2861 info = &dbg_port_ple_quemgn_prepkt; 2862 p += scnprintf(p, end - p, "Enable ple quemgn prepkt dump.\n"); 2863 break; 2864 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2865 info = &dbg_port_ple_quemgn_nxtpkt; 2866 p += scnprintf(p, end - p, "Enable ple quemgn nxtpkt dump.\n"); 2867 break; 2868 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2869 info = &dbg_port_ple_quemgn_qlnktbl; 2870 p += scnprintf(p, end - p, 2871 "Enable ple quemgn qlnktbl dump.\n"); 2872 break; 2873 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2874 info = &dbg_port_ple_quemgn_qempty; 2875 p += scnprintf(p, end - p, "Enable ple quemgn qempty dump.\n"); 2876 break; 2877 case RTW89_DBG_PORT_SEL_PKTINFO: 2878 info = &dbg_port_pktinfo; 2879 p += scnprintf(p, end - p, "Enable pktinfo dump.\n"); 2880 break; 2881 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2882 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2883 B_AX_DBG_SEL0, 0x80); 2884 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2885 B_AX_SEL_0XC0_MASK, 1); 2886 fallthrough; 2887 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2888 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2889 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2890 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2891 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2892 info = &dbg_port_dspt_hdt_tx0_5; 2893 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2894 rtw89_write16_mask(rtwdev, info->sel_addr, 2895 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2896 rtw89_write16_mask(rtwdev, info->sel_addr, 2897 B_AX_DISPATCHER_CH_SEL_MASK, index); 2898 p += scnprintf(p, end - p, 2899 "Enable Dispatcher hdt tx%x dump.\n", index); 2900 break; 2901 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2902 info = &dbg_port_dspt_hdt_tx6; 2903 rtw89_write16_mask(rtwdev, info->sel_addr, 2904 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2905 rtw89_write16_mask(rtwdev, info->sel_addr, 2906 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2907 p += scnprintf(p, end - p, 2908 "Enable Dispatcher hdt tx6 dump.\n"); 2909 break; 2910 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2911 info = &dbg_port_dspt_hdt_tx7; 2912 rtw89_write16_mask(rtwdev, info->sel_addr, 2913 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2914 rtw89_write16_mask(rtwdev, info->sel_addr, 2915 B_AX_DISPATCHER_CH_SEL_MASK, 7); 2916 p += scnprintf(p, end - p, 2917 "Enable Dispatcher hdt tx7 dump.\n"); 2918 break; 2919 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 2920 info = &dbg_port_dspt_hdt_tx8; 2921 rtw89_write16_mask(rtwdev, info->sel_addr, 2922 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2923 rtw89_write16_mask(rtwdev, info->sel_addr, 2924 B_AX_DISPATCHER_CH_SEL_MASK, 8); 2925 p += scnprintf(p, end - p, 2926 "Enable Dispatcher hdt tx8 dump.\n"); 2927 break; 2928 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 2929 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 2930 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 2931 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 2932 info = &dbg_port_dspt_hdt_tx9_C; 2933 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 2934 rtw89_write16_mask(rtwdev, info->sel_addr, 2935 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2936 rtw89_write16_mask(rtwdev, info->sel_addr, 2937 B_AX_DISPATCHER_CH_SEL_MASK, index); 2938 p += scnprintf(p, end - p, 2939 "Enable Dispatcher hdt tx%x dump.\n", index); 2940 break; 2941 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 2942 info = &dbg_port_dspt_hdt_txD; 2943 rtw89_write16_mask(rtwdev, info->sel_addr, 2944 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2945 rtw89_write16_mask(rtwdev, info->sel_addr, 2946 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 2947 p += scnprintf(p, end - p, 2948 "Enable Dispatcher hdt txD dump.\n"); 2949 break; 2950 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 2951 info = &dbg_port_dspt_cdt_tx0; 2952 rtw89_write16_mask(rtwdev, info->sel_addr, 2953 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2954 rtw89_write16_mask(rtwdev, info->sel_addr, 2955 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2956 p += scnprintf(p, end - p, 2957 "Enable Dispatcher cdt tx0 dump.\n"); 2958 break; 2959 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 2960 info = &dbg_port_dspt_cdt_tx1; 2961 rtw89_write16_mask(rtwdev, info->sel_addr, 2962 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2963 rtw89_write16_mask(rtwdev, info->sel_addr, 2964 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2965 p += scnprintf(p, end - p, 2966 "Enable Dispatcher cdt tx1 dump.\n"); 2967 break; 2968 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 2969 info = &dbg_port_dspt_cdt_tx3; 2970 rtw89_write16_mask(rtwdev, info->sel_addr, 2971 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2972 rtw89_write16_mask(rtwdev, info->sel_addr, 2973 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2974 p += scnprintf(p, end - p, 2975 "Enable Dispatcher cdt tx3 dump.\n"); 2976 break; 2977 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 2978 info = &dbg_port_dspt_cdt_tx4; 2979 rtw89_write16_mask(rtwdev, info->sel_addr, 2980 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2981 rtw89_write16_mask(rtwdev, info->sel_addr, 2982 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2983 p += scnprintf(p, end - p, 2984 "Enable Dispatcher cdt tx4 dump.\n"); 2985 break; 2986 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 2987 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 2988 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 2989 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 2990 info = &dbg_port_dspt_cdt_tx5_8; 2991 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 2992 rtw89_write16_mask(rtwdev, info->sel_addr, 2993 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2994 rtw89_write16_mask(rtwdev, info->sel_addr, 2995 B_AX_DISPATCHER_CH_SEL_MASK, index); 2996 p += scnprintf(p, end - p, 2997 "Enable Dispatcher cdt tx%x dump.\n", index); 2998 break; 2999 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 3000 info = &dbg_port_dspt_cdt_tx9; 3001 rtw89_write16_mask(rtwdev, info->sel_addr, 3002 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3003 rtw89_write16_mask(rtwdev, info->sel_addr, 3004 B_AX_DISPATCHER_CH_SEL_MASK, 9); 3005 p += scnprintf(p, end - p, 3006 "Enable Dispatcher cdt tx9 dump.\n"); 3007 break; 3008 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 3009 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 3010 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 3011 info = &dbg_port_dspt_cdt_txA_C; 3012 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 3013 rtw89_write16_mask(rtwdev, info->sel_addr, 3014 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3015 rtw89_write16_mask(rtwdev, info->sel_addr, 3016 B_AX_DISPATCHER_CH_SEL_MASK, index); 3017 p += scnprintf(p, end - p, 3018 "Enable Dispatcher cdt tx%x dump.\n", index); 3019 break; 3020 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 3021 info = &dbg_port_dspt_hdt_rx0; 3022 rtw89_write16_mask(rtwdev, info->sel_addr, 3023 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3024 rtw89_write16_mask(rtwdev, info->sel_addr, 3025 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3026 p += scnprintf(p, end - p, 3027 "Enable Dispatcher hdt rx0 dump.\n"); 3028 break; 3029 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 3030 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 3031 info = &dbg_port_dspt_hdt_rx1_2; 3032 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 3033 rtw89_write16_mask(rtwdev, info->sel_addr, 3034 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3035 rtw89_write16_mask(rtwdev, info->sel_addr, 3036 B_AX_DISPATCHER_CH_SEL_MASK, index); 3037 p += scnprintf(p, end - p, 3038 "Enable Dispatcher hdt rx%x dump.\n", index); 3039 break; 3040 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 3041 info = &dbg_port_dspt_hdt_rx3; 3042 rtw89_write16_mask(rtwdev, info->sel_addr, 3043 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3044 rtw89_write16_mask(rtwdev, info->sel_addr, 3045 B_AX_DISPATCHER_CH_SEL_MASK, 3); 3046 p += scnprintf(p, end - p, 3047 "Enable Dispatcher hdt rx3 dump.\n"); 3048 break; 3049 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 3050 info = &dbg_port_dspt_hdt_rx4; 3051 rtw89_write16_mask(rtwdev, info->sel_addr, 3052 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3053 rtw89_write16_mask(rtwdev, info->sel_addr, 3054 B_AX_DISPATCHER_CH_SEL_MASK, 4); 3055 p += scnprintf(p, end - p, 3056 "Enable Dispatcher hdt rx4 dump.\n"); 3057 break; 3058 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 3059 info = &dbg_port_dspt_hdt_rx5; 3060 rtw89_write16_mask(rtwdev, info->sel_addr, 3061 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3062 rtw89_write16_mask(rtwdev, info->sel_addr, 3063 B_AX_DISPATCHER_CH_SEL_MASK, 5); 3064 p += scnprintf(p, end - p, 3065 "Enable Dispatcher hdt rx5 dump.\n"); 3066 break; 3067 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 3068 info = &dbg_port_dspt_cdt_rx_p0_0; 3069 rtw89_write16_mask(rtwdev, info->sel_addr, 3070 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3071 rtw89_write16_mask(rtwdev, info->sel_addr, 3072 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3073 p += scnprintf(p, end - p, 3074 "Enable Dispatcher cdt rx part0 0 dump.\n"); 3075 break; 3076 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 3077 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 3078 info = &dbg_port_dspt_cdt_rx_p0_1; 3079 rtw89_write16_mask(rtwdev, info->sel_addr, 3080 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3081 rtw89_write16_mask(rtwdev, info->sel_addr, 3082 B_AX_DISPATCHER_CH_SEL_MASK, 1); 3083 p += scnprintf(p, end - p, 3084 "Enable Dispatcher cdt rx part0 1 dump.\n"); 3085 break; 3086 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 3087 info = &dbg_port_dspt_cdt_rx_p0_2; 3088 rtw89_write16_mask(rtwdev, info->sel_addr, 3089 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3090 rtw89_write16_mask(rtwdev, info->sel_addr, 3091 B_AX_DISPATCHER_CH_SEL_MASK, 2); 3092 p += scnprintf(p, end - p, 3093 "Enable Dispatcher cdt rx part0 2 dump.\n"); 3094 break; 3095 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 3096 info = &dbg_port_dspt_cdt_rx_p1; 3097 rtw89_write8_mask(rtwdev, info->sel_addr, 3098 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3099 p += scnprintf(p, end - p, 3100 "Enable Dispatcher cdt rx part1 dump.\n"); 3101 break; 3102 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 3103 info = &dbg_port_dspt_stf_ctrl; 3104 rtw89_write8_mask(rtwdev, info->sel_addr, 3105 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 3106 p += scnprintf(p, end - p, 3107 "Enable Dispatcher stf control dump.\n"); 3108 break; 3109 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 3110 info = &dbg_port_dspt_addr_ctrl; 3111 rtw89_write8_mask(rtwdev, info->sel_addr, 3112 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 3113 p += scnprintf(p, end - p, 3114 "Enable Dispatcher addr control dump.\n"); 3115 break; 3116 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 3117 info = &dbg_port_dspt_wde_intf; 3118 rtw89_write8_mask(rtwdev, info->sel_addr, 3119 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 3120 p += scnprintf(p, end - p, 3121 "Enable Dispatcher wde interface dump.\n"); 3122 break; 3123 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 3124 info = &dbg_port_dspt_ple_intf; 3125 rtw89_write8_mask(rtwdev, info->sel_addr, 3126 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 3127 p += scnprintf(p, end - p, 3128 "Enable Dispatcher ple interface dump.\n"); 3129 break; 3130 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 3131 info = &dbg_port_dspt_flow_ctrl; 3132 rtw89_write8_mask(rtwdev, info->sel_addr, 3133 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 3134 p += scnprintf(p, end - p, 3135 "Enable Dispatcher flow control dump.\n"); 3136 break; 3137 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 3138 info = &dbg_port_pcie_txdma; 3139 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3140 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 3141 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 3142 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3143 p += scnprintf(p, end - p, "Enable pcie txdma dump.\n"); 3144 break; 3145 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 3146 info = &dbg_port_pcie_rxdma; 3147 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3148 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 3149 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 3150 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3151 p += scnprintf(p, end - p, "Enable pcie rxdma dump.\n"); 3152 break; 3153 case RTW89_DBG_PORT_SEL_PCIE_CVT: 3154 info = &dbg_port_pcie_cvt; 3155 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3156 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 3157 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 3158 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3159 p += scnprintf(p, end - p, "Enable pcie cvt dump.\n"); 3160 break; 3161 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 3162 info = &dbg_port_pcie_cxpl; 3163 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3164 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 3165 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 3166 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3167 p += scnprintf(p, end - p, "Enable pcie cxpl dump.\n"); 3168 break; 3169 case RTW89_DBG_PORT_SEL_PCIE_IO: 3170 info = &dbg_port_pcie_io; 3171 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3172 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 3173 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 3174 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3175 p += scnprintf(p, end - p, "Enable pcie io dump.\n"); 3176 break; 3177 case RTW89_DBG_PORT_SEL_PCIE_MISC: 3178 info = &dbg_port_pcie_misc; 3179 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3180 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 3181 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 3182 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3183 p += scnprintf(p, end - p, "Enable pcie misc dump.\n"); 3184 break; 3185 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 3186 info = &dbg_port_pcie_misc2; 3187 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 3188 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 3189 B_AX_PCIE_DBG_SEL_MASK); 3190 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 3191 p += scnprintf(p, end - p, "Enable pcie misc2 dump.\n"); 3192 break; 3193 default: 3194 p += scnprintf(p, end - p, "Dbg port select err\n"); 3195 break; 3196 } 3197 3198 *ppinfo = info; 3199 3200 return p - buf; 3201 } 3202 3203 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 3204 { 3205 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 3206 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 3207 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 3208 return false; 3209 if (rtw89_is_rtl885xb(rtwdev) && 3210 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3211 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3212 return false; 3213 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3214 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 3215 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 3216 return false; 3217 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3218 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 3219 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 3220 return false; 3221 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 3222 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 3223 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 3224 return false; 3225 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 3226 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3227 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3228 return false; 3229 3230 return true; 3231 } 3232 3233 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 3234 char *buf, size_t bufsz, u32 sel) 3235 { 3236 const struct rtw89_mac_dbg_port_info *info = NULL; 3237 char *p = buf, *end = buf + bufsz; 3238 u32 val32; 3239 u16 val16; 3240 u8 val8; 3241 u32 i; 3242 3243 p += rtw89_debug_mac_dbg_port_sel(rtwdev, p, end - p, sel, &info); 3244 3245 if (!info) { 3246 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 3247 goto out; 3248 } 3249 3250 #define case_DBG_SEL(__sel) \ 3251 case RTW89_DBG_PORT_SEL_##__sel: \ 3252 p += scnprintf(p, end - p, "Dump debug port " #__sel ":\n"); \ 3253 break 3254 3255 switch (sel) { 3256 case_DBG_SEL(PTCL_C0); 3257 case_DBG_SEL(PTCL_C1); 3258 case_DBG_SEL(SCH_C0); 3259 case_DBG_SEL(SCH_C1); 3260 case_DBG_SEL(TMAC_C0); 3261 case_DBG_SEL(TMAC_C1); 3262 case_DBG_SEL(RMAC_C0); 3263 case_DBG_SEL(RMAC_C1); 3264 case_DBG_SEL(RMACST_C0); 3265 case_DBG_SEL(RMACST_C1); 3266 case_DBG_SEL(TRXPTCL_C0); 3267 case_DBG_SEL(TRXPTCL_C1); 3268 case_DBG_SEL(TX_INFOL_C0); 3269 case_DBG_SEL(TX_INFOH_C0); 3270 case_DBG_SEL(TX_INFOL_C1); 3271 case_DBG_SEL(TX_INFOH_C1); 3272 case_DBG_SEL(TXTF_INFOL_C0); 3273 case_DBG_SEL(TXTF_INFOH_C0); 3274 case_DBG_SEL(TXTF_INFOL_C1); 3275 case_DBG_SEL(TXTF_INFOH_C1); 3276 case_DBG_SEL(WDE_BUFMGN_FREEPG); 3277 case_DBG_SEL(WDE_BUFMGN_QUOTA); 3278 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 3279 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 3280 case_DBG_SEL(WDE_QUEMGN_PREPKT); 3281 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 3282 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 3283 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 3284 case_DBG_SEL(PLE_BUFMGN_FREEPG); 3285 case_DBG_SEL(PLE_BUFMGN_QUOTA); 3286 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 3287 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 3288 case_DBG_SEL(PLE_QUEMGN_PREPKT); 3289 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 3290 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 3291 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 3292 case_DBG_SEL(PKTINFO); 3293 case_DBG_SEL(DSPT_HDT_TX0); 3294 case_DBG_SEL(DSPT_HDT_TX1); 3295 case_DBG_SEL(DSPT_HDT_TX2); 3296 case_DBG_SEL(DSPT_HDT_TX3); 3297 case_DBG_SEL(DSPT_HDT_TX4); 3298 case_DBG_SEL(DSPT_HDT_TX5); 3299 case_DBG_SEL(DSPT_HDT_TX6); 3300 case_DBG_SEL(DSPT_HDT_TX7); 3301 case_DBG_SEL(DSPT_HDT_TX8); 3302 case_DBG_SEL(DSPT_HDT_TX9); 3303 case_DBG_SEL(DSPT_HDT_TXA); 3304 case_DBG_SEL(DSPT_HDT_TXB); 3305 case_DBG_SEL(DSPT_HDT_TXC); 3306 case_DBG_SEL(DSPT_HDT_TXD); 3307 case_DBG_SEL(DSPT_HDT_TXE); 3308 case_DBG_SEL(DSPT_HDT_TXF); 3309 case_DBG_SEL(DSPT_CDT_TX0); 3310 case_DBG_SEL(DSPT_CDT_TX1); 3311 case_DBG_SEL(DSPT_CDT_TX3); 3312 case_DBG_SEL(DSPT_CDT_TX4); 3313 case_DBG_SEL(DSPT_CDT_TX5); 3314 case_DBG_SEL(DSPT_CDT_TX6); 3315 case_DBG_SEL(DSPT_CDT_TX7); 3316 case_DBG_SEL(DSPT_CDT_TX8); 3317 case_DBG_SEL(DSPT_CDT_TX9); 3318 case_DBG_SEL(DSPT_CDT_TXA); 3319 case_DBG_SEL(DSPT_CDT_TXB); 3320 case_DBG_SEL(DSPT_CDT_TXC); 3321 case_DBG_SEL(DSPT_HDT_RX0); 3322 case_DBG_SEL(DSPT_HDT_RX1); 3323 case_DBG_SEL(DSPT_HDT_RX2); 3324 case_DBG_SEL(DSPT_HDT_RX3); 3325 case_DBG_SEL(DSPT_HDT_RX4); 3326 case_DBG_SEL(DSPT_HDT_RX5); 3327 case_DBG_SEL(DSPT_CDT_RX_P0); 3328 case_DBG_SEL(DSPT_CDT_RX_P0_0); 3329 case_DBG_SEL(DSPT_CDT_RX_P0_1); 3330 case_DBG_SEL(DSPT_CDT_RX_P0_2); 3331 case_DBG_SEL(DSPT_CDT_RX_P1); 3332 case_DBG_SEL(DSPT_STF_CTRL); 3333 case_DBG_SEL(DSPT_ADDR_CTRL); 3334 case_DBG_SEL(DSPT_WDE_INTF); 3335 case_DBG_SEL(DSPT_PLE_INTF); 3336 case_DBG_SEL(DSPT_FLOW_CTRL); 3337 case_DBG_SEL(PCIE_TXDMA); 3338 case_DBG_SEL(PCIE_RXDMA); 3339 case_DBG_SEL(PCIE_CVT); 3340 case_DBG_SEL(PCIE_CXPL); 3341 case_DBG_SEL(PCIE_IO); 3342 case_DBG_SEL(PCIE_MISC); 3343 case_DBG_SEL(PCIE_MISC2); 3344 } 3345 3346 #undef case_DBG_SEL 3347 3348 p += scnprintf(p, end - p, "Sel addr = 0x%X\n", info->sel_addr); 3349 p += scnprintf(p, end - p, "Read addr = 0x%X\n", info->rd_addr); 3350 3351 for (i = info->srt; i <= info->end; i++) { 3352 switch (info->sel_byte) { 3353 case 1: 3354 default: 3355 rtw89_write8_mask(rtwdev, info->sel_addr, 3356 info->sel_msk, i); 3357 p += scnprintf(p, end - p, "0x%02X: ", i); 3358 break; 3359 case 2: 3360 rtw89_write16_mask(rtwdev, info->sel_addr, 3361 info->sel_msk, i); 3362 p += scnprintf(p, end - p, "0x%04X: ", i); 3363 break; 3364 case 4: 3365 rtw89_write32_mask(rtwdev, info->sel_addr, 3366 info->sel_msk, i); 3367 p += scnprintf(p, end - p, "0x%04X: ", i); 3368 break; 3369 } 3370 3371 udelay(10); 3372 3373 switch (info->rd_byte) { 3374 case 1: 3375 default: 3376 val8 = rtw89_read8_mask(rtwdev, 3377 info->rd_addr, info->rd_msk); 3378 p += scnprintf(p, end - p, "0x%02X\n", val8); 3379 break; 3380 case 2: 3381 val16 = rtw89_read16_mask(rtwdev, 3382 info->rd_addr, info->rd_msk); 3383 p += scnprintf(p, end - p, "0x%04X\n", val16); 3384 break; 3385 case 4: 3386 val32 = rtw89_read32_mask(rtwdev, 3387 info->rd_addr, info->rd_msk); 3388 p += scnprintf(p, end - p, "0x%08X\n", val32); 3389 break; 3390 } 3391 } 3392 3393 out: 3394 return p - buf; 3395 } 3396 3397 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 3398 char *buf, size_t bufsz) 3399 { 3400 char *p = buf, *end = buf + bufsz; 3401 ssize_t n; 3402 u32 sel; 3403 3404 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 3405 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 3406 if (!is_dbg_port_valid(rtwdev, sel)) 3407 continue; 3408 n = rtw89_debug_mac_dbg_port_dump(rtwdev, p, end - p, sel); 3409 if (n < 0) { 3410 rtw89_err(rtwdev, 3411 "failed to dump debug port %d\n", sel); 3412 break; 3413 } 3414 p += n; 3415 } 3416 3417 return p - buf; 3418 } 3419 3420 static ssize_t 3421 rtw89_debug_priv_mac_dbg_port_dump_get(struct rtw89_dev *rtwdev, 3422 struct rtw89_debugfs_priv *debugfs_priv, 3423 char *buf, size_t bufsz) 3424 { 3425 char *p = buf, *end = buf + bufsz; 3426 3427 if (debugfs_priv->dbgpkg_en.ss_dbg) 3428 p += rtw89_debug_mac_dump_ss_dbg(rtwdev, p, end - p); 3429 if (debugfs_priv->dbgpkg_en.dle_dbg) 3430 p += rtw89_debug_mac_dump_dle_dbg(rtwdev, p, end - p); 3431 if (debugfs_priv->dbgpkg_en.dmac_dbg) 3432 p += rtw89_debug_mac_dump_dmac_dbg(rtwdev, p, end - p); 3433 if (debugfs_priv->dbgpkg_en.cmac_dbg) 3434 p += rtw89_debug_mac_dump_cmac_dbg(rtwdev, p, end - p); 3435 if (debugfs_priv->dbgpkg_en.dbg_port) 3436 p += rtw89_debug_mac_dump_dbg_port(rtwdev, p, end - p); 3437 3438 return p - buf; 3439 }; 3440 3441 static u8 *rtw89_hex2bin(struct rtw89_dev *rtwdev, const char *buf, size_t count) 3442 { 3443 u8 *bin; 3444 int num; 3445 int err = 0; 3446 3447 num = count / 2; 3448 bin = kmalloc(num, GFP_KERNEL); 3449 if (!bin) { 3450 err = -EFAULT; 3451 goto out; 3452 } 3453 3454 if (hex2bin(bin, buf, num)) { 3455 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 3456 kfree(bin); 3457 err = -EINVAL; 3458 } 3459 3460 out: 3461 return err ? ERR_PTR(err) : bin; 3462 } 3463 3464 static ssize_t rtw89_debug_priv_send_h2c_set(struct rtw89_dev *rtwdev, 3465 struct rtw89_debugfs_priv *debugfs_priv, 3466 const char *buf, size_t count) 3467 { 3468 u8 *h2c; 3469 int ret; 3470 u16 h2c_len = count / 2; 3471 3472 h2c = rtw89_hex2bin(rtwdev, buf, count); 3473 if (IS_ERR(h2c)) 3474 return -EFAULT; 3475 3476 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3477 3478 kfree(h2c); 3479 3480 return ret ? ret : count; 3481 } 3482 3483 static ssize_t 3484 rtw89_debug_priv_early_h2c_get(struct rtw89_dev *rtwdev, 3485 struct rtw89_debugfs_priv *debugfs_priv, 3486 char *buf, size_t bufsz) 3487 { 3488 struct rtw89_early_h2c *early_h2c; 3489 char *p = buf, *end = buf + bufsz; 3490 int seq = 0; 3491 3492 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3493 3494 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3495 p += scnprintf(p, end - p, "%d: %*ph\n", ++seq, 3496 early_h2c->h2c_len, early_h2c->h2c); 3497 3498 return p - buf; 3499 } 3500 3501 static ssize_t 3502 rtw89_debug_priv_early_h2c_set(struct rtw89_dev *rtwdev, 3503 struct rtw89_debugfs_priv *debugfs_priv, 3504 const char *buf, size_t count) 3505 { 3506 struct rtw89_early_h2c *early_h2c; 3507 u8 *h2c; 3508 u16 h2c_len = count / 2; 3509 3510 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3511 3512 h2c = rtw89_hex2bin(rtwdev, buf, count); 3513 if (IS_ERR(h2c)) 3514 return -EFAULT; 3515 3516 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3517 kfree(h2c); 3518 rtw89_fw_free_all_early_h2c(rtwdev); 3519 goto out; 3520 } 3521 3522 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 3523 if (!early_h2c) { 3524 kfree(h2c); 3525 return -EFAULT; 3526 } 3527 3528 early_h2c->h2c = h2c; 3529 early_h2c->h2c_len = h2c_len; 3530 3531 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3532 3533 out: 3534 return count; 3535 } 3536 3537 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 3538 { 3539 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3540 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3541 u16 pkt_id; 3542 int ret; 3543 3544 rtw89_leave_ps_mode(rtwdev); 3545 3546 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3547 if (ret) 3548 return ret; 3549 3550 /* intentionally, enqueue two pkt, but has only one pkt id */ 3551 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3552 ctrl_para.start_pktid = pkt_id; 3553 ctrl_para.end_pktid = pkt_id; 3554 ctrl_para.pkt_num = 1; /* start from 0 */ 3555 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3556 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3557 3558 if (mac->set_cpuio(rtwdev, &ctrl_para, true)) 3559 return -EFAULT; 3560 3561 return 0; 3562 } 3563 3564 static ssize_t 3565 rtw89_debug_priv_fw_crash_get(struct rtw89_dev *rtwdev, 3566 struct rtw89_debugfs_priv *debugfs_priv, 3567 char *buf, size_t bufsz) 3568 { 3569 char *p = buf, *end = buf + bufsz; 3570 3571 p += scnprintf(p, end - p, "%d\n", 3572 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3573 return p - buf; 3574 } 3575 3576 enum rtw89_dbg_crash_simulation_type { 3577 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3578 RTW89_DBG_SIM_CTRL_ERROR = 2, 3579 }; 3580 3581 static ssize_t 3582 rtw89_debug_priv_fw_crash_set(struct rtw89_dev *rtwdev, 3583 struct rtw89_debugfs_priv *debugfs_priv, 3584 const char *buf, size_t count) 3585 { 3586 int (*sim)(struct rtw89_dev *rtwdev); 3587 u8 crash_type; 3588 int ret; 3589 3590 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3591 3592 ret = kstrtou8(buf, 0, &crash_type); 3593 if (ret) 3594 return -EINVAL; 3595 3596 switch (crash_type) { 3597 case RTW89_DBG_SIM_CPU_EXCEPTION: 3598 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw)) 3599 return -EOPNOTSUPP; 3600 sim = rtw89_fw_h2c_trigger_cpu_exception; 3601 break; 3602 case RTW89_DBG_SIM_CTRL_ERROR: 3603 sim = rtw89_dbg_trigger_ctrl_error; 3604 break; 3605 default: 3606 return -EINVAL; 3607 } 3608 3609 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3610 ret = sim(rtwdev); 3611 3612 if (ret) 3613 return ret; 3614 3615 return count; 3616 } 3617 3618 static ssize_t rtw89_debug_priv_btc_info_get(struct rtw89_dev *rtwdev, 3619 struct rtw89_debugfs_priv *debugfs_priv, 3620 char *buf, size_t bufsz) 3621 { 3622 return rtw89_btc_dump_info(rtwdev, buf, bufsz); 3623 } 3624 3625 static ssize_t rtw89_debug_priv_btc_manual_set(struct rtw89_dev *rtwdev, 3626 struct rtw89_debugfs_priv *debugfs_priv, 3627 const char *buf, size_t count) 3628 { 3629 struct rtw89_btc *btc = &rtwdev->btc; 3630 const struct rtw89_btc_ver *ver = btc->ver; 3631 int ret; 3632 3633 ret = kstrtobool(buf, &btc->manual_ctrl); 3634 if (ret) 3635 return ret; 3636 3637 if (ver->fcxctrl == 7) 3638 btc->ctrl.ctrl_v7.manual = btc->manual_ctrl; 3639 else 3640 btc->ctrl.ctrl.manual = btc->manual_ctrl; 3641 3642 return count; 3643 } 3644 3645 static ssize_t rtw89_debug_priv_fw_log_manual_set(struct rtw89_dev *rtwdev, 3646 struct rtw89_debugfs_priv *debugfs_priv, 3647 const char *buf, size_t count) 3648 { 3649 struct rtw89_fw_log *log = &rtwdev->fw.log; 3650 bool fw_log_manual; 3651 3652 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3653 3654 if (kstrtobool(buf, &fw_log_manual)) 3655 goto out; 3656 3657 log->enable = fw_log_manual; 3658 if (log->enable) 3659 rtw89_fw_log_prepare(rtwdev); 3660 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3661 out: 3662 return count; 3663 } 3664 3665 static int rtw89_sta_link_info_get_iter(struct rtw89_dev *rtwdev, 3666 char *buf, size_t bufsz, 3667 struct rtw89_sta_link *rtwsta_link) 3668 { 3669 static const char * const he_gi_str[] = { 3670 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3671 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3672 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3673 }; 3674 static const char * const eht_gi_str[] = { 3675 [NL80211_RATE_INFO_EHT_GI_0_8] = "0.8", 3676 [NL80211_RATE_INFO_EHT_GI_1_6] = "1.6", 3677 [NL80211_RATE_INFO_EHT_GI_3_2] = "3.2", 3678 }; 3679 struct rate_info *rate = &rtwsta_link->ra_report.txrate; 3680 struct ieee80211_rx_status *status = &rtwsta_link->rx_status; 3681 struct rtw89_hal *hal = &rtwdev->hal; 3682 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3683 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3684 struct ieee80211_link_sta *link_sta; 3685 char *p = buf, *end = buf + bufsz; 3686 u8 evm_min, evm_max, evm_1ss; 3687 u16 max_rc_amsdu_len; 3688 u8 rssi; 3689 u8 snr; 3690 int i; 3691 3692 rcu_read_lock(); 3693 3694 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3695 max_rc_amsdu_len = link_sta->agg.max_rc_amsdu_len; 3696 3697 rcu_read_unlock(); 3698 3699 p += scnprintf(p, end - p, "TX rate [%u, %u]: ", rtwsta_link->mac_id, 3700 rtwsta_link->link_id); 3701 3702 if (rate->flags & RATE_INFO_FLAGS_MCS) 3703 p += scnprintf(p, end - p, "HT MCS-%d%s", rate->mcs, 3704 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3705 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3706 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", rate->nss, 3707 rate->mcs, 3708 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3709 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3710 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", rate->nss, 3711 rate->mcs, 3712 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3713 he_gi_str[rate->he_gi] : "N/A"); 3714 else if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) 3715 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", rate->nss, 3716 rate->mcs, 3717 rate->eht_gi < ARRAY_SIZE(eht_gi_str) ? 3718 eht_gi_str[rate->eht_gi] : "N/A"); 3719 else 3720 p += scnprintf(p, end - p, "Legacy %d", rate->legacy); 3721 p += scnprintf(p, end - p, "%s", 3722 rtwsta_link->ra_report.might_fallback_legacy ? " FB_G" : ""); 3723 p += scnprintf(p, end - p, " BW:%u", 3724 rtw89_rate_info_bw_to_mhz(rate->bw)); 3725 p += scnprintf(p, end - p, " (hw_rate=0x%x)", 3726 rtwsta_link->ra_report.hw_rate); 3727 p += scnprintf(p, end - p, " ==> agg_wait=%d (%d)\n", 3728 rtwsta_link->max_agg_wait, 3729 max_rc_amsdu_len); 3730 3731 p += scnprintf(p, end - p, "RX rate [%u, %u]: ", rtwsta_link->mac_id, 3732 rtwsta_link->link_id); 3733 3734 switch (status->encoding) { 3735 case RX_ENC_LEGACY: 3736 p += scnprintf(p, end - p, "Legacy %d", status->rate_idx + 3737 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 3738 break; 3739 case RX_ENC_HT: 3740 p += scnprintf(p, end - p, "HT MCS-%d%s", status->rate_idx, 3741 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3742 break; 3743 case RX_ENC_VHT: 3744 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", status->nss, 3745 status->rate_idx, 3746 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3747 break; 3748 case RX_ENC_HE: 3749 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", 3750 status->nss, status->rate_idx, 3751 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3752 he_gi_str[status->he_gi] : "N/A"); 3753 break; 3754 case RX_ENC_EHT: 3755 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", 3756 status->nss, status->rate_idx, 3757 status->eht.gi < ARRAY_SIZE(eht_gi_str) ? 3758 eht_gi_str[status->eht.gi] : "N/A"); 3759 break; 3760 } 3761 p += scnprintf(p, end - p, " BW:%u", 3762 rtw89_rate_info_bw_to_mhz(status->bw)); 3763 p += scnprintf(p, end - p, " (hw_rate=0x%x)\n", 3764 rtwsta_link->rx_hw_rate); 3765 3766 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi); 3767 p += scnprintf(p, end - p, "RSSI: %d dBm (raw=%d, prev=%d) [", 3768 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, 3769 rtwsta_link->prev_rssi); 3770 for (i = 0; i < ant_num; i++) { 3771 rssi = ewma_rssi_read(&rtwsta_link->rssi[i]); 3772 p += scnprintf(p, end - p, "%d%s%s", 3773 RTW89_RSSI_RAW_TO_DBM(rssi), 3774 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 3775 i + 1 == ant_num ? "" : ", "); 3776 } 3777 p += scnprintf(p, end - p, "]\n"); 3778 3779 evm_1ss = ewma_evm_read(&rtwsta_link->evm_1ss); 3780 p += scnprintf(p, end - p, "EVM: [%2u.%02u, ", evm_1ss >> 2, 3781 (evm_1ss & 0x3) * 25); 3782 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 3783 evm_min = ewma_evm_read(&rtwsta_link->evm_min[i]); 3784 evm_max = ewma_evm_read(&rtwsta_link->evm_max[i]); 3785 3786 p += scnprintf(p, end - p, "%s(%2u.%02u, %2u.%02u)", 3787 i == 0 ? "" : " ", 3788 evm_min >> 2, (evm_min & 0x3) * 25, 3789 evm_max >> 2, (evm_max & 0x3) * 25); 3790 } 3791 p += scnprintf(p, end - p, "]\t"); 3792 3793 snr = ewma_snr_read(&rtwsta_link->avg_snr); 3794 p += scnprintf(p, end - p, "SNR: %u\n", snr); 3795 3796 return p - buf; 3797 } 3798 3799 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 3800 { 3801 struct rtw89_debugfs_iter_data *iter_data = 3802 (struct rtw89_debugfs_iter_data *)data; 3803 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3804 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3805 struct rtw89_sta_link *rtwsta_link; 3806 size_t bufsz = iter_data->bufsz; 3807 char *buf = iter_data->buf; 3808 char *p = buf, *end = buf + bufsz; 3809 unsigned int link_id; 3810 3811 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 3812 p += rtw89_sta_link_info_get_iter(rtwdev, p, end - p, rtwsta_link); 3813 3814 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 3815 } 3816 3817 static int 3818 rtw89_debug_append_rx_rate(char *buf, size_t bufsz, struct rtw89_pkt_stat *pkt_stat, 3819 enum rtw89_hw_rate first_rate, int len) 3820 { 3821 char *p = buf, *end = buf + bufsz; 3822 int i; 3823 3824 for (i = 0; i < len; i++) 3825 p += scnprintf(p, end - p, "%s%u", i == 0 ? "" : ", ", 3826 pkt_stat->rx_rate_cnt[first_rate + i]); 3827 3828 return p - buf; 3829 } 3830 3831 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate} 3832 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate} 3833 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate} 3834 3835 static const struct rtw89_rx_rate_cnt_info { 3836 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM]; 3837 int len; 3838 int ext; 3839 const char *rate_mode; 3840 } rtw89_rx_rate_cnt_infos[] = { 3841 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"}, 3842 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"}, 3843 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"}, 3844 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"}, 3845 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"}, 3846 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"}, 3847 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"}, 3848 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"}, 3849 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"}, 3850 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"}, 3851 }; 3852 3853 static ssize_t rtw89_debug_priv_phy_info_get(struct rtw89_dev *rtwdev, 3854 struct rtw89_debugfs_priv *debugfs_priv, 3855 char *buf, size_t bufsz) 3856 { 3857 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3858 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 3859 const struct rtw89_chip_info *chip = rtwdev->chip; 3860 struct rtw89_debugfs_iter_data iter_data; 3861 const struct rtw89_rx_rate_cnt_info *info; 3862 struct rtw89_hal *hal = &rtwdev->hal; 3863 char *p = buf, *end = buf + bufsz; 3864 enum rtw89_hw_rate first_rate; 3865 u8 rssi; 3866 int i; 3867 3868 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 3869 3870 p += scnprintf(p, end - p, "TP TX: %u [%u] Mbps (lv: %d", 3871 stats->tx_throughput, stats->tx_throughput_raw, 3872 stats->tx_tfc_lv); 3873 if (hal->thermal_prot_lv) 3874 p += scnprintf(p, end - p, ", duty: %d%%", 3875 100 - hal->thermal_prot_lv * RTW89_THERMAL_PROT_STEP); 3876 p += scnprintf(p, end - p, "), RX: %u [%u] Mbps (lv: %d)\n", 3877 stats->rx_throughput, stats->rx_throughput_raw, 3878 stats->rx_tfc_lv); 3879 p += scnprintf(p, end - p, "Beacon: %u (%d dBm), TF: %u\n", 3880 pkt_stat->beacon_nr, 3881 RTW89_RSSI_RAW_TO_DBM(rssi), stats->rx_tf_periodic); 3882 p += scnprintf(p, end - p, "Avg packet length: TX=%u, RX=%u\n", 3883 stats->tx_avg_len, 3884 stats->rx_avg_len); 3885 3886 p += scnprintf(p, end - p, "RX count:\n"); 3887 3888 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 3889 info = &rtw89_rx_rate_cnt_infos[i]; 3890 first_rate = info->first_rate[chip->chip_gen]; 3891 if (first_rate >= RTW89_HW_RATE_NR) 3892 continue; 3893 3894 p += scnprintf(p, end - p, "%10s [", info->rate_mode); 3895 p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat, 3896 first_rate, info->len); 3897 if (info->ext) { 3898 p += scnprintf(p, end - p, "]["); 3899 p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat, 3900 first_rate + info->len, info->ext); 3901 } 3902 p += scnprintf(p, end - p, "]\n"); 3903 } 3904 3905 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 3906 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, &iter_data); 3907 p += iter_data.written_sz; 3908 3909 return p - buf; 3910 } 3911 3912 static int rtw89_dump_addr_cam(struct rtw89_dev *rtwdev, 3913 char *buf, size_t bufsz, 3914 struct rtw89_addr_cam_entry *addr_cam) 3915 { 3916 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3917 const struct rtw89_sec_cam_entry *sec_entry; 3918 char *p = buf, *end = buf + bufsz; 3919 u8 sec_cam_idx; 3920 int i; 3921 3922 p += scnprintf(p, end - p, "\taddr_cam_idx=%u\n", 3923 addr_cam->addr_cam_idx); 3924 p += scnprintf(p, end - p, "\t-> bssid_cam_idx=%u\n", 3925 addr_cam->bssid_cam_idx); 3926 p += scnprintf(p, end - p, "\tsec_cam_bitmap=%*ph\n", 3927 (int)sizeof(addr_cam->sec_cam_map), 3928 addr_cam->sec_cam_map); 3929 for_each_set_bit(i, addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM) { 3930 sec_cam_idx = addr_cam->sec_ent[i]; 3931 sec_entry = cam_info->sec_entries[sec_cam_idx]; 3932 if (!sec_entry) 3933 continue; 3934 p += scnprintf(p, end - p, "\tsec[%d]: sec_cam_idx %u", i, 3935 sec_entry->sec_cam_idx); 3936 if (sec_entry->ext_key) 3937 p += scnprintf(p, end - p, ", %u", 3938 sec_entry->sec_cam_idx + 1); 3939 p += scnprintf(p, end - p, "\n"); 3940 } 3941 3942 return p - buf; 3943 } 3944 3945 __printf(4, 5) 3946 static int rtw89_dump_pkt_offload(char *buf, size_t bufsz, struct list_head *pkt_list, 3947 const char *fmt, ...) 3948 { 3949 char *p = buf, *end = buf + bufsz; 3950 struct rtw89_pktofld_info *info; 3951 struct va_format vaf; 3952 va_list args; 3953 3954 if (list_empty(pkt_list)) 3955 return 0; 3956 3957 va_start(args, fmt); 3958 vaf.va = &args; 3959 vaf.fmt = fmt; 3960 3961 p += scnprintf(p, end - p, "%pV", &vaf); 3962 3963 va_end(args); 3964 3965 list_for_each_entry(info, pkt_list, list) 3966 p += scnprintf(p, end - p, "%d ", info->id); 3967 3968 p += scnprintf(p, end - p, "\n"); 3969 3970 return p - buf; 3971 } 3972 3973 static int rtw89_vif_link_ids_get(struct rtw89_dev *rtwdev, 3974 char *buf, size_t bufsz, u8 *mac, 3975 struct rtw89_vif_link *rtwvif_link, 3976 bool designated) 3977 { 3978 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif_link->bssid_cam; 3979 char *p = buf, *end = buf + bufsz; 3980 3981 p += scnprintf(p, end - p, " [%u] %pM\n", rtwvif_link->mac_id, 3982 rtwvif_link->mac_addr); 3983 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwvif_link->link_id, 3984 designated ? " (*)" : ""); 3985 p += scnprintf(p, end - p, "\tbssid_cam_idx=%u\n", 3986 bssid_cam->bssid_cam_idx); 3987 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwvif_link->addr_cam); 3988 p += rtw89_dump_pkt_offload(p, end - p, &rtwvif_link->general_pkt_list, 3989 "\tpkt_ofld[GENERAL]: "); 3990 3991 return p - buf; 3992 } 3993 3994 static 3995 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 3996 { 3997 struct rtw89_debugfs_iter_data *iter_data = 3998 (struct rtw89_debugfs_iter_data *)data; 3999 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 4000 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 4001 struct rtw89_vif_link *designated_link; 4002 struct rtw89_vif_link *rtwvif_link; 4003 size_t bufsz = iter_data->bufsz; 4004 char *buf = iter_data->buf; 4005 char *p = buf, *end = buf + bufsz; 4006 unsigned int link_id; 4007 4008 designated_link = rtw89_get_designated_link(rtwvif); 4009 4010 p += scnprintf(p, end - p, "VIF %pM\n", rtwvif->mac_addr); 4011 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4012 p += rtw89_vif_link_ids_get(rtwdev, p, end - p, mac, rtwvif_link, 4013 rtwvif_link == designated_link); 4014 4015 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4016 } 4017 4018 static int rtw89_dump_ba_cam(struct rtw89_dev *rtwdev, 4019 char *buf, size_t bufsz, 4020 struct rtw89_sta_link *rtwsta_link) 4021 { 4022 struct rtw89_ba_cam_entry *entry; 4023 char *p = buf, *end = buf + bufsz; 4024 bool first = true; 4025 4026 list_for_each_entry(entry, &rtwsta_link->ba_cam_list, list) { 4027 if (first) { 4028 p += scnprintf(p, end - p, "\tba_cam "); 4029 first = false; 4030 } else { 4031 p += scnprintf(p, end - p, ", "); 4032 } 4033 p += scnprintf(p, end - p, "tid[%u]=%d", entry->tid, 4034 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 4035 } 4036 p += scnprintf(p, end - p, "\n"); 4037 4038 return p - buf; 4039 } 4040 4041 static int rtw89_sta_link_ids_get(struct rtw89_dev *rtwdev, 4042 char *buf, size_t bufsz, 4043 struct rtw89_sta_link *rtwsta_link, 4044 bool designated) 4045 { 4046 struct ieee80211_link_sta *link_sta; 4047 char *p = buf, *end = buf + bufsz; 4048 4049 rcu_read_lock(); 4050 4051 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4052 4053 p += scnprintf(p, end - p, " [%u] %pM\n", rtwsta_link->mac_id, 4054 link_sta->addr); 4055 4056 rcu_read_unlock(); 4057 4058 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwsta_link->link_id, 4059 designated ? " (*)" : ""); 4060 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwsta_link->addr_cam); 4061 p += rtw89_dump_ba_cam(rtwdev, p, end - p, rtwsta_link); 4062 4063 return p - buf; 4064 } 4065 4066 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 4067 { 4068 struct rtw89_debugfs_iter_data *iter_data = 4069 (struct rtw89_debugfs_iter_data *)data; 4070 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4071 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4072 struct rtw89_sta_link *designated_link; 4073 struct rtw89_sta_link *rtwsta_link; 4074 size_t bufsz = iter_data->bufsz; 4075 char *buf = iter_data->buf; 4076 char *p = buf, *end = buf + bufsz; 4077 unsigned int link_id; 4078 4079 designated_link = rtw89_get_designated_link(rtwsta); 4080 4081 p += scnprintf(p, end - p, "STA %pM %s\n", sta->addr, 4082 sta->tdls ? "(TDLS)" : ""); 4083 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 4084 p += rtw89_sta_link_ids_get(rtwdev, p, end - p, rtwsta_link, 4085 rtwsta_link == designated_link); 4086 4087 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4088 } 4089 4090 static ssize_t rtw89_debug_priv_stations_get(struct rtw89_dev *rtwdev, 4091 struct rtw89_debugfs_priv *debugfs_priv, 4092 char *buf, size_t bufsz) 4093 { 4094 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4095 struct rtw89_debugfs_iter_data iter_data; 4096 char *p = buf, *end = buf + bufsz; 4097 u8 idx; 4098 4099 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4100 4101 p += scnprintf(p, end - p, "map:\n"); 4102 p += scnprintf(p, end - p, "\tmac_id: %*ph\n", 4103 (int)sizeof(rtwdev->mac_id_map), 4104 rtwdev->mac_id_map); 4105 p += scnprintf(p, end - p, "\taddr_cam: %*ph\n", 4106 (int)sizeof(cam_info->addr_cam_map), 4107 cam_info->addr_cam_map); 4108 p += scnprintf(p, end - p, "\tbssid_cam: %*ph\n", 4109 (int)sizeof(cam_info->bssid_cam_map), 4110 cam_info->bssid_cam_map); 4111 p += scnprintf(p, end - p, "\tsec_cam: %*ph\n", 4112 (int)sizeof(cam_info->sec_cam_map), 4113 cam_info->sec_cam_map); 4114 p += scnprintf(p, end - p, "\tba_cam: %*ph\n", 4115 (int)sizeof(cam_info->ba_cam_map), 4116 cam_info->ba_cam_map); 4117 p += scnprintf(p, end - p, "\tpkt_ofld: %*ph\n", 4118 (int)sizeof(rtwdev->pkt_offload), 4119 rtwdev->pkt_offload); 4120 4121 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 4122 if (!(rtwdev->chip->support_bands & BIT(idx))) 4123 continue; 4124 p += rtw89_dump_pkt_offload(p, end - p, &rtwdev->scan_info.pkt_list[idx], 4125 "\t\t[SCAN %u]: ", idx); 4126 } 4127 4128 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4129 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 4130 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, &iter_data); 4131 p += iter_data.written_sz; 4132 4133 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4134 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, &iter_data); 4135 p += iter_data.written_sz; 4136 4137 return p - buf; 4138 } 4139 4140 static void rtw89_debug_disable_dm_cfg_bmap(struct rtw89_dev *rtwdev, u32 new) 4141 { 4142 struct rtw89_hal *hal = &rtwdev->hal; 4143 u32 old = hal->disabled_dm_bitmap; 4144 4145 if (new == old) 4146 return; 4147 4148 hal->disabled_dm_bitmap = new; 4149 4150 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable DM: 0x%x -> 0x%x\n", old, new); 4151 } 4152 4153 static void rtw89_debug_disable_dm_set_flag(struct rtw89_dev *rtwdev, u8 flag) 4154 { 4155 struct rtw89_hal *hal = &rtwdev->hal; 4156 u32 cur = hal->disabled_dm_bitmap; 4157 4158 rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur | BIT(flag)); 4159 } 4160 4161 static void rtw89_debug_disable_dm_clr_flag(struct rtw89_dev *rtwdev, u8 flag) 4162 { 4163 struct rtw89_hal *hal = &rtwdev->hal; 4164 u32 cur = hal->disabled_dm_bitmap; 4165 4166 rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur & ~BIT(flag)); 4167 } 4168 4169 #define DM_INFO(type) {RTW89_DM_ ## type, #type} 4170 4171 static const struct rtw89_disabled_dm_info { 4172 enum rtw89_dm_type type; 4173 const char *name; 4174 } rtw89_disabled_dm_infos[] = { 4175 DM_INFO(DYNAMIC_EDCCA), 4176 DM_INFO(THERMAL_PROTECT), 4177 DM_INFO(TAS), 4178 DM_INFO(MLO), 4179 }; 4180 4181 static ssize_t 4182 rtw89_debug_priv_disable_dm_get(struct rtw89_dev *rtwdev, 4183 struct rtw89_debugfs_priv *debugfs_priv, 4184 char *buf, size_t bufsz) 4185 { 4186 const struct rtw89_disabled_dm_info *info; 4187 struct rtw89_hal *hal = &rtwdev->hal; 4188 char *p = buf, *end = buf + bufsz; 4189 u32 disabled; 4190 int i; 4191 4192 p += scnprintf(p, end - p, "Disabled DM: 0x%x\n", 4193 hal->disabled_dm_bitmap); 4194 4195 for (i = 0; i < ARRAY_SIZE(rtw89_disabled_dm_infos); i++) { 4196 info = &rtw89_disabled_dm_infos[i]; 4197 disabled = BIT(info->type) & hal->disabled_dm_bitmap; 4198 4199 p += scnprintf(p, end - p, "[%d] %s: %c\n", info->type, 4200 info->name, 4201 disabled ? 'X' : 'O'); 4202 } 4203 4204 return p - buf; 4205 } 4206 4207 static ssize_t 4208 rtw89_debug_priv_disable_dm_set(struct rtw89_dev *rtwdev, 4209 struct rtw89_debugfs_priv *debugfs_priv, 4210 const char *buf, size_t count) 4211 { 4212 u32 conf; 4213 int ret; 4214 4215 ret = kstrtou32(buf, 0, &conf); 4216 if (ret) 4217 return -EINVAL; 4218 4219 rtw89_debug_disable_dm_cfg_bmap(rtwdev, conf); 4220 4221 return count; 4222 } 4223 4224 static void rtw89_debug_mlo_mode_set_mlsr(struct rtw89_dev *rtwdev, 4225 unsigned int link_id) 4226 { 4227 struct ieee80211_vif *vif; 4228 struct rtw89_vif *rtwvif; 4229 4230 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4231 vif = rtwvif_to_vif(rtwvif); 4232 if (!ieee80211_vif_is_mld(vif)) 4233 continue; 4234 4235 rtw89_core_mlsr_switch(rtwdev, rtwvif, link_id); 4236 } 4237 } 4238 4239 static ssize_t 4240 rtw89_debug_priv_mlo_mode_get(struct rtw89_dev *rtwdev, 4241 struct rtw89_debugfs_priv *debugfs_priv, 4242 char *buf, size_t bufsz) 4243 { 4244 bool mlo_dm_dis = rtwdev->hal.disabled_dm_bitmap & BIT(RTW89_DM_MLO); 4245 char *p = buf, *end = buf + bufsz; 4246 struct ieee80211_vif *vif; 4247 struct rtw89_vif *rtwvif; 4248 int count = 0; 4249 4250 p += scnprintf(p, end - p, "MLD(s) status: (MLO DM: %s)\n", 4251 str_disable_enable(mlo_dm_dis)); 4252 4253 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4254 vif = rtwvif_to_vif(rtwvif); 4255 if (!ieee80211_vif_is_mld(vif)) 4256 continue; 4257 4258 p += scnprintf(p, end - p, 4259 "\t#%u: MLO mode %x, valid 0x%x, active 0x%x\n", 4260 count++, rtwvif->mlo_mode, vif->valid_links, 4261 vif->active_links); 4262 } 4263 4264 if (count == 0) 4265 p += scnprintf(p, end - p, "\t(None)\n"); 4266 4267 return p - buf; 4268 } 4269 4270 static ssize_t 4271 rtw89_debug_priv_mlo_mode_set(struct rtw89_dev *rtwdev, 4272 struct rtw89_debugfs_priv *debugfs_priv, 4273 const char *buf, size_t count) 4274 { 4275 u8 num, mlo_mode; 4276 u32 argv; 4277 4278 num = sscanf(buf, "%hhx %u", &mlo_mode, &argv); 4279 if (num != 2) 4280 return -EINVAL; 4281 4282 rtw89_debug_disable_dm_set_flag(rtwdev, RTW89_DM_MLO); 4283 4284 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Set MLO mode to %x\n", mlo_mode); 4285 4286 switch (mlo_mode) { 4287 case RTW89_MLO_MODE_MLSR: 4288 rtw89_debug_mlo_mode_set_mlsr(rtwdev, argv); 4289 break; 4290 default: 4291 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Unsupported MLO mode\n"); 4292 rtw89_debug_disable_dm_clr_flag(rtwdev, RTW89_DM_MLO); 4293 4294 return -EOPNOTSUPP; 4295 } 4296 4297 return count; 4298 } 4299 4300 #define rtw89_debug_priv_get(name, opts...) \ 4301 { \ 4302 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4303 .opt = { opts }, \ 4304 } 4305 4306 #define rtw89_debug_priv_set(name, opts...) \ 4307 { \ 4308 .cb_write = rtw89_debug_priv_ ##name## _set, \ 4309 .opt = { opts }, \ 4310 } 4311 4312 #define rtw89_debug_priv_select_and_get(name, opts...) \ 4313 { \ 4314 .cb_write = rtw89_debug_priv_ ##name## _select, \ 4315 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4316 .opt = { opts }, \ 4317 } 4318 4319 #define rtw89_debug_priv_set_and_get(name, opts...) \ 4320 { \ 4321 .cb_write = rtw89_debug_priv_ ##name## _set, \ 4322 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4323 .opt = { opts }, \ 4324 } 4325 4326 #define RSIZE_8K .rsize = 0x2000 4327 #define RSIZE_12K .rsize = 0x3000 4328 #define RSIZE_16K .rsize = 0x4000 4329 #define RSIZE_20K .rsize = 0x5000 4330 #define RSIZE_32K .rsize = 0x8000 4331 #define RSIZE_64K .rsize = 0x10000 4332 #define RSIZE_128K .rsize = 0x20000 4333 #define RSIZE_1M .rsize = 0x100000 4334 #define RLOCK .rlock = 1 4335 #define WLOCK .wlock = 1 4336 #define RWLOCK RLOCK, WLOCK 4337 4338 static const struct rtw89_debugfs rtw89_debugfs_templ = { 4339 .read_reg = rtw89_debug_priv_select_and_get(read_reg), 4340 .write_reg = rtw89_debug_priv_set(write_reg), 4341 .read_rf = rtw89_debug_priv_select_and_get(read_rf), 4342 .write_rf = rtw89_debug_priv_set(write_rf), 4343 .rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump, RSIZE_8K), 4344 .txpwr_table = rtw89_debug_priv_get(txpwr_table, RSIZE_20K, RLOCK), 4345 .mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump, RSIZE_128K), 4346 .mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump, RSIZE_16K, RLOCK), 4347 .mac_dbg_port_dump = rtw89_debug_priv_select_and_get(mac_dbg_port_dump, RSIZE_1M), 4348 .send_h2c = rtw89_debug_priv_set(send_h2c), 4349 .early_h2c = rtw89_debug_priv_set_and_get(early_h2c, RWLOCK), 4350 .fw_crash = rtw89_debug_priv_set_and_get(fw_crash, WLOCK), 4351 .btc_info = rtw89_debug_priv_get(btc_info, RSIZE_12K), 4352 .btc_manual = rtw89_debug_priv_set(btc_manual), 4353 .fw_log_manual = rtw89_debug_priv_set(fw_log_manual, WLOCK), 4354 .phy_info = rtw89_debug_priv_get(phy_info), 4355 .stations = rtw89_debug_priv_get(stations, RLOCK), 4356 .disable_dm = rtw89_debug_priv_set_and_get(disable_dm, RWLOCK), 4357 .mlo_mode = rtw89_debug_priv_set_and_get(mlo_mode, RWLOCK), 4358 }; 4359 4360 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 4361 do { \ 4362 struct rtw89_debugfs_priv *priv = &rtwdev->debugfs->name; \ 4363 priv->rtwdev = rtwdev; \ 4364 if (IS_ERR(debugfs_create_file(#name, mode, parent, priv, \ 4365 &file_ops_ ##fopname))) \ 4366 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 4367 } while (0) 4368 4369 #define rtw89_debugfs_add_w(name) \ 4370 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 4371 #define rtw89_debugfs_add_rw(name) \ 4372 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 4373 #define rtw89_debugfs_add_r(name) \ 4374 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 4375 4376 static 4377 void rtw89_debugfs_add_sec0(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4378 { 4379 rtw89_debugfs_add_rw(read_reg); 4380 rtw89_debugfs_add_w(write_reg); 4381 rtw89_debugfs_add_rw(read_rf); 4382 rtw89_debugfs_add_w(write_rf); 4383 rtw89_debugfs_add_r(rf_reg_dump); 4384 rtw89_debugfs_add_r(txpwr_table); 4385 rtw89_debugfs_add_rw(mac_reg_dump); 4386 rtw89_debugfs_add_rw(mac_mem_dump); 4387 rtw89_debugfs_add_rw(mac_dbg_port_dump); 4388 } 4389 4390 static 4391 void rtw89_debugfs_add_sec1(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4392 { 4393 rtw89_debugfs_add_w(send_h2c); 4394 rtw89_debugfs_add_rw(early_h2c); 4395 rtw89_debugfs_add_rw(fw_crash); 4396 rtw89_debugfs_add_r(btc_info); 4397 rtw89_debugfs_add_w(btc_manual); 4398 rtw89_debugfs_add_w(fw_log_manual); 4399 rtw89_debugfs_add_r(phy_info); 4400 rtw89_debugfs_add_r(stations); 4401 rtw89_debugfs_add_rw(disable_dm); 4402 rtw89_debugfs_add_rw(mlo_mode); 4403 } 4404 4405 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 4406 { 4407 struct dentry *debugfs_topdir; 4408 4409 rtwdev->debugfs = kmemdup(&rtw89_debugfs_templ, 4410 sizeof(rtw89_debugfs_templ), GFP_KERNEL); 4411 if (!rtwdev->debugfs) 4412 return; 4413 4414 debugfs_topdir = debugfs_create_dir("rtw89", 4415 rtwdev->hw->wiphy->debugfsdir); 4416 4417 rtw89_debugfs_add_sec0(rtwdev, debugfs_topdir); 4418 rtw89_debugfs_add_sec1(rtwdev, debugfs_topdir); 4419 } 4420 4421 void rtw89_debugfs_deinit(struct rtw89_dev *rtwdev) 4422 { 4423 kfree(rtwdev->debugfs); 4424 } 4425 #endif 4426 4427 #ifdef CONFIG_RTW89_DEBUGMSG 4428 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, 4429 const char *fmt, ...) 4430 { 4431 struct va_format vaf = { 4432 .fmt = fmt, 4433 }; 4434 4435 va_list args; 4436 4437 va_start(args, fmt); 4438 vaf.va = &args; 4439 4440 if (rtw89_debug_mask & mask) 4441 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 4442 4443 va_end(args); 4444 } 4445 EXPORT_SYMBOL(rtw89_debug); 4446 #endif 4447