1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/vmalloc.h> 6 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "sar.h" 15 16 #ifdef CONFIG_RTW89_DEBUGMSG 17 unsigned int rtw89_debug_mask; 18 EXPORT_SYMBOL(rtw89_debug_mask); 19 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 20 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 21 #endif 22 23 #ifdef CONFIG_RTW89_DEBUGFS 24 struct rtw89_debugfs_priv { 25 struct rtw89_dev *rtwdev; 26 int (*cb_read)(struct seq_file *m, void *v); 27 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 28 size_t count, loff_t *loff); 29 union { 30 u32 cb_data; 31 struct { 32 u32 addr; 33 u32 len; 34 } read_reg; 35 struct { 36 u32 addr; 37 u32 mask; 38 u8 path; 39 } read_rf; 40 struct { 41 u8 ss_dbg:1; 42 u8 dle_dbg:1; 43 u8 dmac_dbg:1; 44 u8 cmac_dbg:1; 45 u8 dbg_port:1; 46 } dbgpkg_en; 47 struct { 48 u32 start; 49 u32 len; 50 u8 sel; 51 } mac_mem; 52 }; 53 }; 54 55 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 56 [RATE_INFO_BW_20] = 20, 57 [RATE_INFO_BW_40] = 40, 58 [RATE_INFO_BW_80] = 80, 59 [RATE_INFO_BW_160] = 160, 60 [RATE_INFO_BW_320] = 320, 61 }; 62 63 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 64 { 65 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 66 return rtw89_rate_info_bw_to_mhz_map[bw]; 67 68 return 0; 69 } 70 71 static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 72 { 73 struct rtw89_debugfs_priv *debugfs_priv = m->private; 74 75 return debugfs_priv->cb_read(m, v); 76 } 77 78 static ssize_t rtw89_debugfs_single_write(struct file *filp, 79 const char __user *buffer, 80 size_t count, loff_t *loff) 81 { 82 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 83 84 return debugfs_priv->cb_write(filp, buffer, count, loff); 85 } 86 87 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 88 const char __user *buffer, 89 size_t count, loff_t *loff) 90 { 91 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 92 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 93 94 return debugfs_priv->cb_write(filp, buffer, count, loff); 95 } 96 97 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 98 { 99 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 100 } 101 102 static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 103 { 104 return 0; 105 } 106 107 static const struct file_operations file_ops_single_r = { 108 .owner = THIS_MODULE, 109 .open = rtw89_debugfs_single_open, 110 .read = seq_read, 111 .llseek = seq_lseek, 112 .release = single_release, 113 }; 114 115 static const struct file_operations file_ops_common_rw = { 116 .owner = THIS_MODULE, 117 .open = rtw89_debugfs_single_open, 118 .release = single_release, 119 .read = seq_read, 120 .llseek = seq_lseek, 121 .write = rtw89_debugfs_seq_file_write, 122 }; 123 124 static const struct file_operations file_ops_single_w = { 125 .owner = THIS_MODULE, 126 .write = rtw89_debugfs_single_write, 127 .open = simple_open, 128 .release = rtw89_debugfs_close, 129 }; 130 131 static ssize_t 132 rtw89_debug_priv_read_reg_select(struct file *filp, 133 const char __user *user_buf, 134 size_t count, loff_t *loff) 135 { 136 struct seq_file *m = (struct seq_file *)filp->private_data; 137 struct rtw89_debugfs_priv *debugfs_priv = m->private; 138 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 139 char buf[32]; 140 size_t buf_size; 141 u32 addr, len; 142 int num; 143 144 buf_size = min(count, sizeof(buf) - 1); 145 if (copy_from_user(buf, user_buf, buf_size)) 146 return -EFAULT; 147 148 buf[buf_size] = '\0'; 149 num = sscanf(buf, "%x %x", &addr, &len); 150 if (num != 2) { 151 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 152 return -EINVAL; 153 } 154 155 debugfs_priv->read_reg.addr = addr; 156 debugfs_priv->read_reg.len = len; 157 158 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 159 160 return count; 161 } 162 163 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 164 { 165 struct rtw89_debugfs_priv *debugfs_priv = m->private; 166 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 167 u32 addr, end, data, k; 168 u32 len; 169 170 len = debugfs_priv->read_reg.len; 171 addr = debugfs_priv->read_reg.addr; 172 173 if (len > 4) 174 goto ndata; 175 176 switch (len) { 177 case 1: 178 data = rtw89_read8(rtwdev, addr); 179 break; 180 case 2: 181 data = rtw89_read16(rtwdev, addr); 182 break; 183 case 4: 184 data = rtw89_read32(rtwdev, addr); 185 break; 186 default: 187 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 188 return -EINVAL; 189 } 190 191 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 192 193 return 0; 194 195 ndata: 196 end = addr + len; 197 198 for (; addr < end; addr += 16) { 199 seq_printf(m, "%08xh : ", 0x18600000 + addr); 200 for (k = 0; k < 16; k += 4) { 201 data = rtw89_read32(rtwdev, addr + k); 202 seq_printf(m, "%08x ", data); 203 } 204 seq_puts(m, "\n"); 205 } 206 207 return 0; 208 } 209 210 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 211 const char __user *user_buf, 212 size_t count, loff_t *loff) 213 { 214 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 215 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 216 char buf[32]; 217 size_t buf_size; 218 u32 addr, val, len; 219 int num; 220 221 buf_size = min(count, sizeof(buf) - 1); 222 if (copy_from_user(buf, user_buf, buf_size)) 223 return -EFAULT; 224 225 buf[buf_size] = '\0'; 226 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 227 if (num != 3) { 228 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 229 return -EINVAL; 230 } 231 232 switch (len) { 233 case 1: 234 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 235 rtw89_write8(rtwdev, addr, (u8)val); 236 break; 237 case 2: 238 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 239 rtw89_write16(rtwdev, addr, (u16)val); 240 break; 241 case 4: 242 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 243 rtw89_write32(rtwdev, addr, (u32)val); 244 break; 245 default: 246 rtw89_info(rtwdev, "invalid read write len %d\n", len); 247 break; 248 } 249 250 return count; 251 } 252 253 static ssize_t 254 rtw89_debug_priv_read_rf_select(struct file *filp, 255 const char __user *user_buf, 256 size_t count, loff_t *loff) 257 { 258 struct seq_file *m = (struct seq_file *)filp->private_data; 259 struct rtw89_debugfs_priv *debugfs_priv = m->private; 260 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 261 char buf[32]; 262 size_t buf_size; 263 u32 addr, mask; 264 u8 path; 265 int num; 266 267 buf_size = min(count, sizeof(buf) - 1); 268 if (copy_from_user(buf, user_buf, buf_size)) 269 return -EFAULT; 270 271 buf[buf_size] = '\0'; 272 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 273 if (num != 3) { 274 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 275 return -EINVAL; 276 } 277 278 if (path >= rtwdev->chip->rf_path_num) { 279 rtw89_info(rtwdev, "wrong rf path\n"); 280 return -EINVAL; 281 } 282 debugfs_priv->read_rf.addr = addr; 283 debugfs_priv->read_rf.mask = mask; 284 debugfs_priv->read_rf.path = path; 285 286 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 287 288 return count; 289 } 290 291 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 292 { 293 struct rtw89_debugfs_priv *debugfs_priv = m->private; 294 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 295 u32 addr, data, mask; 296 u8 path; 297 298 addr = debugfs_priv->read_rf.addr; 299 mask = debugfs_priv->read_rf.mask; 300 path = debugfs_priv->read_rf.path; 301 302 data = rtw89_read_rf(rtwdev, path, addr, mask); 303 304 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 305 306 return 0; 307 } 308 309 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 310 const char __user *user_buf, 311 size_t count, loff_t *loff) 312 { 313 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 314 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 315 char buf[32]; 316 size_t buf_size; 317 u32 addr, val, mask; 318 u8 path; 319 int num; 320 321 buf_size = min(count, sizeof(buf) - 1); 322 if (copy_from_user(buf, user_buf, buf_size)) 323 return -EFAULT; 324 325 buf[buf_size] = '\0'; 326 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 327 if (num != 4) { 328 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 329 return -EINVAL; 330 } 331 332 if (path >= rtwdev->chip->rf_path_num) { 333 rtw89_info(rtwdev, "wrong rf path\n"); 334 return -EINVAL; 335 } 336 337 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 338 path, addr, val, mask); 339 rtw89_write_rf(rtwdev, path, addr, mask, val); 340 341 return count; 342 } 343 344 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 345 { 346 struct rtw89_debugfs_priv *debugfs_priv = m->private; 347 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 348 const struct rtw89_chip_info *chip = rtwdev->chip; 349 u32 addr, offset, data; 350 u8 path; 351 352 for (path = 0; path < chip->rf_path_num; path++) { 353 seq_printf(m, "RF path %d:\n\n", path); 354 for (addr = 0; addr < 0x100; addr += 4) { 355 seq_printf(m, "0x%08x: ", addr); 356 for (offset = 0; offset < 4; offset++) { 357 data = rtw89_read_rf(rtwdev, path, 358 addr + offset, RFREG_MASK); 359 seq_printf(m, "0x%05x ", data); 360 } 361 seq_puts(m, "\n"); 362 } 363 seq_puts(m, "\n"); 364 } 365 366 return 0; 367 } 368 369 struct txpwr_ent { 370 bool nested; 371 union { 372 const char *txt; 373 const struct txpwr_ent *ptr; 374 }; 375 u8 len; 376 }; 377 378 struct txpwr_map { 379 const struct txpwr_ent *ent; 380 u8 size; 381 u32 addr_from; 382 u32 addr_to; 383 u32 addr_to_1ss; 384 }; 385 386 #define __GEN_TXPWR_ENT_NESTED(_e) \ 387 { .nested = true, .ptr = __txpwr_ent_##_e, \ 388 .len = ARRAY_SIZE(__txpwr_ent_##_e) } 389 390 #define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t } 391 392 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 393 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 394 395 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 396 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 397 398 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 399 { .len = 8, .txt = _t "\t- " \ 400 _e0 " " _e1 " " _e2 " " _e3 " " \ 401 _e4 " " _e5 " " _e6 " " _e7 } 402 403 static const struct txpwr_ent __txpwr_ent_byr_ax[] = { 404 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 405 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 406 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 407 /* 1NSS */ 408 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 409 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 410 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 411 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 412 /* 2NSS */ 413 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 414 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 415 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 416 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 417 }; 418 419 static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) == 420 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 421 422 static const struct txpwr_map __txpwr_map_byr_ax = { 423 .ent = __txpwr_ent_byr_ax, 424 .size = ARRAY_SIZE(__txpwr_ent_byr_ax), 425 .addr_from = R_AX_PWR_BY_RATE, 426 .addr_to = R_AX_PWR_BY_RATE_MAX, 427 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX, 428 }; 429 430 static const struct txpwr_ent __txpwr_ent_lmt_ax[] = { 431 /* 1TX */ 432 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 433 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 434 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 435 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 436 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 437 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 438 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 439 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 440 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 441 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 442 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 443 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 444 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 445 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 446 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 447 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 448 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 449 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 450 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 451 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 452 /* 2TX */ 453 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 454 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 455 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 456 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 457 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 458 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 459 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 460 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 461 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 462 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 463 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 464 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 465 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 466 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 467 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 468 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 469 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 470 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 471 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 472 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 473 }; 474 475 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) == 476 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 477 478 static const struct txpwr_map __txpwr_map_lmt_ax = { 479 .ent = __txpwr_ent_lmt_ax, 480 .size = ARRAY_SIZE(__txpwr_ent_lmt_ax), 481 .addr_from = R_AX_PWR_LMT, 482 .addr_to = R_AX_PWR_LMT_MAX, 483 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX, 484 }; 485 486 static const struct txpwr_ent __txpwr_ent_lmt_ru_ax[] = { 487 /* 1TX */ 488 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 489 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 490 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 491 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 492 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 493 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 494 /* 2TX */ 495 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 496 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 497 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 498 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 499 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 500 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 501 }; 502 503 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) == 504 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 505 506 static const struct txpwr_map __txpwr_map_lmt_ru_ax = { 507 .ent = __txpwr_ent_lmt_ru_ax, 508 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_ax), 509 .addr_from = R_AX_PWR_RU_LMT, 510 .addr_to = R_AX_PWR_RU_LMT_MAX, 511 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX, 512 }; 513 514 static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = { 515 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 516 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 517 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 518 __GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"), 519 __GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 520 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 521 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 522 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 523 __GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"), 524 __GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 525 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 526 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 527 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 528 __GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"), 529 __GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 530 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 531 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 532 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 533 __GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"), 534 __GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 535 }; 536 537 static const struct txpwr_ent __txpwr_ent_byr_be[] = { 538 __GEN_TXPWR_ENT0("BW20"), 539 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 540 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 541 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 542 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 543 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 544 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 545 546 __GEN_TXPWR_ENT0("BW40"), 547 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 548 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 549 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 550 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 551 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 552 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 553 554 /* there is no CCK section after BW80 */ 555 __GEN_TXPWR_ENT0("BW80"), 556 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 557 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 558 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 559 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 560 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 561 562 __GEN_TXPWR_ENT0("BW160"), 563 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 564 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 565 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 566 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 567 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 568 569 __GEN_TXPWR_ENT0("BW320"), 570 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 571 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 572 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 573 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 574 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 575 }; 576 577 static const struct txpwr_map __txpwr_map_byr_be = { 578 .ent = __txpwr_ent_byr_be, 579 .size = ARRAY_SIZE(__txpwr_ent_byr_be), 580 .addr_from = R_BE_PWR_BY_RATE, 581 .addr_to = R_BE_PWR_BY_RATE_MAX, 582 .addr_to_1ss = 0, /* not support */ 583 }; 584 585 static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = { 586 __GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"), 587 __GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"), 588 __GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"), 589 __GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"), 590 __GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"), 591 __GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"), 592 __GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"), 593 __GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"), 594 __GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"), 595 __GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"), 596 __GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"), 597 __GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"), 598 __GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"), 599 __GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"), 600 __GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"), 601 __GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"), 602 __GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"), 603 __GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"), 604 __GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"), 605 __GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"), 606 __GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"), 607 __GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"), 608 __GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"), 609 __GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"), 610 __GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"), 611 __GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"), 612 __GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"), 613 __GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"), 614 __GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"), 615 __GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"), 616 __GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"), 617 __GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"), 618 __GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"), 619 __GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"), 620 __GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"), 621 }; 622 623 static const struct txpwr_ent __txpwr_ent_lmt_be[] = { 624 __GEN_TXPWR_ENT0("1TX"), 625 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 626 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 627 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 628 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 629 630 __GEN_TXPWR_ENT0("2TX"), 631 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 632 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 633 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 634 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 635 }; 636 637 static const struct txpwr_map __txpwr_map_lmt_be = { 638 .ent = __txpwr_ent_lmt_be, 639 .size = ARRAY_SIZE(__txpwr_ent_lmt_be), 640 .addr_from = R_BE_PWR_LMT, 641 .addr_to = R_BE_PWR_LMT_MAX, 642 .addr_to_1ss = 0, /* not support */ 643 }; 644 645 static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = { 646 __GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 647 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 648 __GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 649 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 650 __GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 651 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 652 __GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 653 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 654 __GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 655 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 656 __GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 657 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 658 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 659 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 660 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 661 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 662 __GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 663 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 664 __GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 665 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 666 }; 667 668 static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = { 669 __GEN_TXPWR_ENT0("1TX"), 670 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 671 672 __GEN_TXPWR_ENT0("2TX"), 673 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 674 }; 675 676 static const struct txpwr_map __txpwr_map_lmt_ru_be = { 677 .ent = __txpwr_ent_lmt_ru_be, 678 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be), 679 .addr_from = R_BE_PWR_RU_LMT, 680 .addr_to = R_BE_PWR_RU_LMT_MAX, 681 .addr_to_1ss = 0, /* not support */ 682 }; 683 684 static unsigned int 685 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 686 const s8 *buf, const unsigned int cur) 687 { 688 unsigned int cnt, i; 689 char *fmt; 690 691 if (ent->nested) { 692 for (cnt = 0, i = 0; i < ent->len; i++) 693 cnt += __print_txpwr_ent(m, ent->ptr + i, buf, 694 cur + cnt); 695 return cnt; 696 } 697 698 switch (ent->len) { 699 case 0: 700 seq_printf(m, "\t<< %s >>\n", ent->txt); 701 return 0; 702 case 2: 703 fmt = "%s\t| %3d, %3d,\t\tdBm\n"; 704 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 705 return 2; 706 case 4: 707 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 708 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 709 buf[cur + 2], buf[cur + 3]); 710 return 4; 711 case 8: 712 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 713 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 714 buf[cur + 2], buf[cur + 3], buf[cur + 4], 715 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 716 return 8; 717 default: 718 return 0; 719 } 720 } 721 722 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 723 const struct txpwr_map *map) 724 { 725 u8 fct = rtwdev->chip->txpwr_factor_mac; 726 u8 path_num = rtwdev->chip->rf_path_num; 727 unsigned int cur, i; 728 u32 max_valid_addr; 729 u32 val, addr; 730 s8 *buf, tmp; 731 int ret; 732 733 buf = vzalloc(map->addr_to - map->addr_from + 4); 734 if (!buf) 735 return -ENOMEM; 736 737 if (path_num == 1) 738 max_valid_addr = map->addr_to_1ss; 739 else 740 max_valid_addr = map->addr_to; 741 742 if (max_valid_addr == 0) 743 return -EOPNOTSUPP; 744 745 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 746 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 747 if (ret) 748 val = MASKDWORD; 749 750 cur = addr - map->addr_from; 751 for (i = 0; i < 4; i++, val >>= 8) { 752 /* signed 7 bits, and reserved BIT(7) */ 753 tmp = sign_extend32(val, 6); 754 buf[cur + i] = tmp >> fct; 755 } 756 } 757 758 for (cur = 0, i = 0; i < map->size; i++) 759 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 760 761 vfree(buf); 762 return 0; 763 } 764 765 #define case_REGD(_regd) \ 766 case RTW89_ ## _regd: \ 767 seq_puts(m, #_regd "\n"); \ 768 break 769 770 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev, 771 const struct rtw89_chan *chan) 772 { 773 u8 band = chan->band_type; 774 u8 regd = rtw89_regd_get(rtwdev, band); 775 776 switch (regd) { 777 default: 778 seq_printf(m, "UNKNOWN: %d\n", regd); 779 break; 780 case_REGD(WW); 781 case_REGD(ETSI); 782 case_REGD(FCC); 783 case_REGD(MKK); 784 case_REGD(NA); 785 case_REGD(IC); 786 case_REGD(KCC); 787 case_REGD(NCC); 788 case_REGD(CHILE); 789 case_REGD(ACMA); 790 case_REGD(MEXICO); 791 case_REGD(UKRAINE); 792 case_REGD(CN); 793 } 794 } 795 796 #undef case_REGD 797 798 struct dbgfs_txpwr_table { 799 const struct txpwr_map *byr; 800 const struct txpwr_map *lmt; 801 const struct txpwr_map *lmt_ru; 802 }; 803 804 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = { 805 .byr = &__txpwr_map_byr_ax, 806 .lmt = &__txpwr_map_lmt_ax, 807 .lmt_ru = &__txpwr_map_lmt_ru_ax, 808 }; 809 810 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = { 811 .byr = &__txpwr_map_byr_be, 812 .lmt = &__txpwr_map_lmt_be, 813 .lmt_ru = &__txpwr_map_lmt_ru_be, 814 }; 815 816 static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = { 817 [RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax, 818 [RTW89_CHIP_BE] = &dbgfs_txpwr_table_be, 819 }; 820 821 static 822 void rtw89_debug_priv_txpwr_table_get_regd(struct seq_file *m, 823 struct rtw89_dev *rtwdev, 824 const struct rtw89_chan *chan) 825 { 826 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 827 const struct rtw89_reg_6ghz_tpe *tpe6 = ®ulatory->reg_6ghz_tpe; 828 829 seq_printf(m, "[Chanctx] band %u, ch %u, bw %u\n", 830 chan->band_type, chan->channel, chan->band_width); 831 832 seq_puts(m, "[Regulatory] "); 833 __print_regd(m, rtwdev, chan); 834 835 if (chan->band_type == RTW89_BAND_6G) { 836 seq_printf(m, "[reg6_pwr_type] %u\n", regulatory->reg_6ghz_power); 837 838 if (tpe6->valid) 839 seq_printf(m, "[TPE] %d dBm\n", tpe6->constraint); 840 } 841 } 842 843 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 844 { 845 struct rtw89_debugfs_priv *debugfs_priv = m->private; 846 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 847 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 848 const struct dbgfs_txpwr_table *tbl; 849 const struct rtw89_chan *chan; 850 int ret = 0; 851 852 mutex_lock(&rtwdev->mutex); 853 rtw89_leave_ps_mode(rtwdev); 854 chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 855 856 rtw89_debug_priv_txpwr_table_get_regd(m, rtwdev, chan); 857 858 seq_puts(m, "[SAR]\n"); 859 rtw89_print_sar(m, rtwdev, chan->freq); 860 861 seq_puts(m, "[TAS]\n"); 862 rtw89_print_tas(m, rtwdev); 863 864 tbl = dbgfs_txpwr_tables[chip_gen]; 865 if (!tbl) { 866 ret = -EOPNOTSUPP; 867 goto err; 868 } 869 870 seq_puts(m, "\n[TX power byrate]\n"); 871 ret = __print_txpwr_map(m, rtwdev, tbl->byr); 872 if (ret) 873 goto err; 874 875 seq_puts(m, "\n[TX power limit]\n"); 876 ret = __print_txpwr_map(m, rtwdev, tbl->lmt); 877 if (ret) 878 goto err; 879 880 seq_puts(m, "\n[TX power limit_ru]\n"); 881 ret = __print_txpwr_map(m, rtwdev, tbl->lmt_ru); 882 if (ret) 883 goto err; 884 885 err: 886 mutex_unlock(&rtwdev->mutex); 887 return ret; 888 } 889 890 static ssize_t 891 rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 892 const char __user *user_buf, 893 size_t count, loff_t *loff) 894 { 895 struct seq_file *m = (struct seq_file *)filp->private_data; 896 struct rtw89_debugfs_priv *debugfs_priv = m->private; 897 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 898 const struct rtw89_chip_info *chip = rtwdev->chip; 899 char buf[32]; 900 size_t buf_size; 901 int sel; 902 int ret; 903 904 buf_size = min(count, sizeof(buf) - 1); 905 if (copy_from_user(buf, user_buf, buf_size)) 906 return -EFAULT; 907 908 buf[buf_size] = '\0'; 909 ret = kstrtoint(buf, 0, &sel); 910 if (ret) 911 return ret; 912 913 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 914 rtw89_info(rtwdev, "invalid args: %d\n", sel); 915 return -EINVAL; 916 } 917 918 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 919 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 920 chip->chip_id); 921 return -EINVAL; 922 } 923 924 debugfs_priv->cb_data = sel; 925 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 926 927 return count; 928 } 929 930 #define RTW89_MAC_PAGE_SIZE 0x100 931 932 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 933 { 934 struct rtw89_debugfs_priv *debugfs_priv = m->private; 935 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 936 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 937 u32 start, end; 938 u32 i, j, k, page; 939 u32 val; 940 941 switch (reg_sel) { 942 case RTW89_DBG_SEL_MAC_00: 943 seq_puts(m, "Debug selected MAC page 0x00\n"); 944 start = 0x000; 945 end = 0x014; 946 break; 947 case RTW89_DBG_SEL_MAC_30: 948 seq_puts(m, "Debug selected MAC page 0x30\n"); 949 start = 0x030; 950 end = 0x033; 951 break; 952 case RTW89_DBG_SEL_MAC_40: 953 seq_puts(m, "Debug selected MAC page 0x40\n"); 954 start = 0x040; 955 end = 0x07f; 956 break; 957 case RTW89_DBG_SEL_MAC_80: 958 seq_puts(m, "Debug selected MAC page 0x80\n"); 959 start = 0x080; 960 end = 0x09f; 961 break; 962 case RTW89_DBG_SEL_MAC_C0: 963 seq_puts(m, "Debug selected MAC page 0xc0\n"); 964 start = 0x0c0; 965 end = 0x0df; 966 break; 967 case RTW89_DBG_SEL_MAC_E0: 968 seq_puts(m, "Debug selected MAC page 0xe0\n"); 969 start = 0x0e0; 970 end = 0x0ff; 971 break; 972 case RTW89_DBG_SEL_BB: 973 seq_puts(m, "Debug selected BB register\n"); 974 start = 0x100; 975 end = 0x17f; 976 break; 977 case RTW89_DBG_SEL_IQK: 978 seq_puts(m, "Debug selected IQK register\n"); 979 start = 0x180; 980 end = 0x1bf; 981 break; 982 case RTW89_DBG_SEL_RFC: 983 seq_puts(m, "Debug selected RFC register\n"); 984 start = 0x1c0; 985 end = 0x1ff; 986 break; 987 default: 988 seq_puts(m, "Selected invalid register page\n"); 989 return -EINVAL; 990 } 991 992 for (i = start; i <= end; i++) { 993 page = i << 8; 994 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 995 seq_printf(m, "%08xh : ", 0x18600000 + j); 996 for (k = 0; k < 4; k++) { 997 val = rtw89_read32(rtwdev, j + (k << 2)); 998 seq_printf(m, "%08x ", val); 999 } 1000 seq_puts(m, "\n"); 1001 } 1002 } 1003 1004 return 0; 1005 } 1006 1007 static ssize_t 1008 rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 1009 const char __user *user_buf, 1010 size_t count, loff_t *loff) 1011 { 1012 struct seq_file *m = (struct seq_file *)filp->private_data; 1013 struct rtw89_debugfs_priv *debugfs_priv = m->private; 1014 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 1015 char buf[32]; 1016 size_t buf_size; 1017 u32 sel, start_addr, len; 1018 int num; 1019 1020 buf_size = min(count, sizeof(buf) - 1); 1021 if (copy_from_user(buf, user_buf, buf_size)) 1022 return -EFAULT; 1023 1024 buf[buf_size] = '\0'; 1025 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 1026 if (num != 3) { 1027 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 1028 return -EINVAL; 1029 } 1030 1031 debugfs_priv->mac_mem.sel = sel; 1032 debugfs_priv->mac_mem.start = start_addr; 1033 debugfs_priv->mac_mem.len = len; 1034 1035 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 1036 sel, start_addr, len); 1037 1038 return count; 1039 } 1040 1041 static void rtw89_debug_dump_mac_mem(struct seq_file *m, 1042 struct rtw89_dev *rtwdev, 1043 u8 sel, u32 start_addr, u32 len) 1044 { 1045 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1046 u32 filter_model_addr = mac->filter_model_addr; 1047 u32 indir_access_addr = mac->indir_access_addr; 1048 u32 base_addr, start_page, residue; 1049 u32 i, j, p, pages; 1050 u32 dump_len, remain; 1051 u32 val; 1052 1053 remain = len; 1054 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 1055 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 1056 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 1057 base_addr = mac->mem_base_addrs[sel]; 1058 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 1059 1060 for (p = 0; p < pages; p++) { 1061 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 1062 rtw89_write32(rtwdev, filter_model_addr, base_addr); 1063 for (i = indir_access_addr + residue; 1064 i < indir_access_addr + dump_len;) { 1065 seq_printf(m, "%08xh:", i); 1066 for (j = 0; 1067 j < 4 && i < indir_access_addr + dump_len; 1068 j++, i += 4) { 1069 val = rtw89_read32(rtwdev, i); 1070 seq_printf(m, " %08x", val); 1071 remain -= 4; 1072 } 1073 seq_puts(m, "\n"); 1074 } 1075 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 1076 } 1077 } 1078 1079 static int 1080 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 1081 { 1082 struct rtw89_debugfs_priv *debugfs_priv = m->private; 1083 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 1084 bool grant_read = false; 1085 1086 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 1087 return -ENOENT; 1088 1089 if (rtwdev->chip->chip_id == RTL8852C) { 1090 switch (debugfs_priv->mac_mem.sel) { 1091 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 1092 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 1093 case RTW89_MAC_MEM_TXDATA_FIFO_0: 1094 case RTW89_MAC_MEM_TXDATA_FIFO_1: 1095 grant_read = true; 1096 break; 1097 default: 1098 break; 1099 } 1100 } 1101 1102 mutex_lock(&rtwdev->mutex); 1103 rtw89_leave_ps_mode(rtwdev); 1104 if (grant_read) 1105 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1106 rtw89_debug_dump_mac_mem(m, rtwdev, 1107 debugfs_priv->mac_mem.sel, 1108 debugfs_priv->mac_mem.start, 1109 debugfs_priv->mac_mem.len); 1110 if (grant_read) 1111 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1112 mutex_unlock(&rtwdev->mutex); 1113 1114 return 0; 1115 } 1116 1117 static ssize_t 1118 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 1119 const char __user *user_buf, 1120 size_t count, loff_t *loff) 1121 { 1122 struct seq_file *m = (struct seq_file *)filp->private_data; 1123 struct rtw89_debugfs_priv *debugfs_priv = m->private; 1124 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 1125 char buf[32]; 1126 size_t buf_size; 1127 int sel, set; 1128 int num; 1129 bool enable; 1130 1131 buf_size = min(count, sizeof(buf) - 1); 1132 if (copy_from_user(buf, user_buf, buf_size)) 1133 return -EFAULT; 1134 1135 buf[buf_size] = '\0'; 1136 num = sscanf(buf, "%d %d", &sel, &set); 1137 if (num != 2) { 1138 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 1139 return -EINVAL; 1140 } 1141 1142 enable = set != 0; 1143 switch (sel) { 1144 case 0: 1145 debugfs_priv->dbgpkg_en.ss_dbg = enable; 1146 break; 1147 case 1: 1148 debugfs_priv->dbgpkg_en.dle_dbg = enable; 1149 break; 1150 case 2: 1151 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 1152 break; 1153 case 3: 1154 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 1155 break; 1156 case 4: 1157 debugfs_priv->dbgpkg_en.dbg_port = enable; 1158 break; 1159 default: 1160 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 1161 return -EINVAL; 1162 } 1163 1164 rtw89_info(rtwdev, "%s debug port dump %d\n", 1165 enable ? "Enable" : "Disable", sel); 1166 1167 return count; 1168 } 1169 1170 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 1171 struct seq_file *m) 1172 { 1173 return 0; 1174 } 1175 1176 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 1177 struct seq_file *m) 1178 { 1179 #define DLE_DFI_DUMP(__type, __target, __sel) \ 1180 ({ \ 1181 u32 __ctrl; \ 1182 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 1183 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 1184 u32 __data, __val32; \ 1185 int __ret; \ 1186 \ 1187 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 1188 DLE_DFI_TYPE_##__target) | \ 1189 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 1190 B_AX_WDE_DFI_ACTIVE; \ 1191 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 1192 __ret = read_poll_timeout(rtw89_read32, __val32, \ 1193 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 1194 1000, 50000, false, \ 1195 rtwdev, __reg_ctrl); \ 1196 if (__ret) { \ 1197 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 1198 #__type, #__target, __sel); \ 1199 return __ret; \ 1200 } \ 1201 \ 1202 __data = rtw89_read32(rtwdev, __reg_data); \ 1203 __data; \ 1204 }) 1205 1206 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 1207 ({ \ 1208 u32 __freepg, __pubpg; \ 1209 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 1210 \ 1211 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 1212 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 1213 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 1214 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 1215 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 1216 seq_printf(__m, "[%s] freepg head: %d\n", \ 1217 #__type, __freepg_head); \ 1218 seq_printf(__m, "[%s] freepg tail: %d\n", \ 1219 #__type, __freepg_tail); \ 1220 seq_printf(__m, "[%s] pubpg num : %d\n", \ 1221 #__type, __pubpg_num); \ 1222 }) 1223 1224 #define case_QUOTA(__m, __type, __id) \ 1225 case __type##_QTAID_##__id: \ 1226 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 1227 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 1228 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 1229 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 1230 #__type, #__id, rsv_pgnum); \ 1231 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 1232 #__type, #__id, use_pgnum); \ 1233 break 1234 u32 quota_id; 1235 u32 val32; 1236 u16 rsv_pgnum, use_pgnum; 1237 int ret; 1238 1239 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1240 if (ret) { 1241 seq_puts(m, "[DLE] : DMAC not enabled\n"); 1242 return ret; 1243 } 1244 1245 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 1246 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 1247 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 1248 switch (quota_id) { 1249 case_QUOTA(m, WDE, HOST_IF); 1250 case_QUOTA(m, WDE, WLAN_CPU); 1251 case_QUOTA(m, WDE, DATA_CPU); 1252 case_QUOTA(m, WDE, PKTIN); 1253 case_QUOTA(m, WDE, CPUIO); 1254 } 1255 } 1256 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 1257 switch (quota_id) { 1258 case_QUOTA(m, PLE, B0_TXPL); 1259 case_QUOTA(m, PLE, B1_TXPL); 1260 case_QUOTA(m, PLE, C2H); 1261 case_QUOTA(m, PLE, H2C); 1262 case_QUOTA(m, PLE, WLAN_CPU); 1263 case_QUOTA(m, PLE, MPDU); 1264 case_QUOTA(m, PLE, CMAC0_RX); 1265 case_QUOTA(m, PLE, CMAC1_RX); 1266 case_QUOTA(m, PLE, CMAC1_BBRPT); 1267 case_QUOTA(m, PLE, WDRLS); 1268 case_QUOTA(m, PLE, CPUIO); 1269 } 1270 } 1271 1272 return 0; 1273 1274 #undef case_QUOTA 1275 #undef DLE_DFI_DUMP 1276 #undef DLE_DFI_FREE_PAGE_DUMP 1277 } 1278 1279 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 1280 struct seq_file *m) 1281 { 1282 const struct rtw89_chip_info *chip = rtwdev->chip; 1283 u32 dmac_err; 1284 int i, ret; 1285 1286 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1287 if (ret) { 1288 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 1289 return ret; 1290 } 1291 1292 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1293 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1294 seq_printf(m, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1295 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1296 1297 if (dmac_err) { 1298 seq_printf(m, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1299 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1300 seq_printf(m, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1301 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1302 if (chip->chip_id == RTL8852C) { 1303 seq_printf(m, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1304 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1305 seq_printf(m, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1306 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1307 seq_printf(m, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1308 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1309 seq_printf(m, "R_AX_PLE_DBGERR_STS=0x%08x\n", 1310 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1311 } 1312 } 1313 1314 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1315 seq_printf(m, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1316 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1317 seq_printf(m, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1318 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1319 if (chip->chip_id == RTL8852C) 1320 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1321 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1322 else 1323 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1324 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1325 } 1326 1327 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1328 if (chip->chip_id == RTL8852C) { 1329 seq_printf(m, "R_AX_SEC_ERR_IMR=0x%08x\n", 1330 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1331 seq_printf(m, "R_AX_SEC_ERR_ISR=0x%08x\n", 1332 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1333 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1334 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1335 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1336 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1337 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1338 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1339 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1340 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1341 seq_printf(m, "R_AX_SEC_DEBUG1=0x%08x\n", 1342 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1343 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1344 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1345 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1346 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1347 1348 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1349 B_AX_DBG_SEL0, 0x8B); 1350 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1351 B_AX_DBG_SEL1, 0x8B); 1352 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1353 B_AX_SEL_0XC0_MASK, 1); 1354 for (i = 0; i < 0x10; i++) { 1355 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1356 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1357 seq_printf(m, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1358 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1359 } 1360 } else { 1361 seq_printf(m, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1362 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1363 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1364 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1365 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1366 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1367 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1368 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1369 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1370 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1371 seq_printf(m, "R_AX_SEC_CAM_WDATA=0x%08x\n", 1372 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1373 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1374 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1375 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1376 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1377 seq_printf(m, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1378 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1379 seq_printf(m, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1380 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1381 } 1382 } 1383 1384 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1385 seq_printf(m, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1386 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1387 seq_printf(m, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1388 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1389 seq_printf(m, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1390 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1391 seq_printf(m, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1392 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1393 } 1394 1395 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1396 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1397 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1398 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1399 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1400 } 1401 1402 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1403 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1404 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1405 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1406 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1407 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1408 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1409 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1410 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1411 } 1412 1413 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1414 if (chip->chip_id == RTL8852C) { 1415 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1416 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1417 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1418 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1419 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1420 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1421 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1422 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1423 } else { 1424 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1425 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1426 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1427 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1428 } 1429 } 1430 1431 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1432 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1433 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1434 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1435 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1436 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1437 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1438 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1439 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1440 seq_printf(m, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1441 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1442 seq_printf(m, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1443 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1444 seq_printf(m, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1445 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1446 seq_printf(m, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1447 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1448 seq_printf(m, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1449 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1450 seq_printf(m, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1451 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1452 seq_printf(m, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1453 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1454 seq_printf(m, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1455 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1456 if (chip->chip_id == RTL8852C) { 1457 seq_printf(m, "R_AX_RX_CTRL0=0x%08x\n", 1458 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1459 seq_printf(m, "R_AX_RX_CTRL1=0x%08x\n", 1460 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1461 seq_printf(m, "R_AX_RX_CTRL2=0x%08x\n", 1462 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1463 } else { 1464 seq_printf(m, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1465 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1466 seq_printf(m, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1467 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1468 seq_printf(m, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1469 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1470 } 1471 } 1472 1473 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1474 seq_printf(m, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1475 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1476 seq_printf(m, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1477 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1478 } 1479 1480 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1481 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1482 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1483 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1484 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1485 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1486 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1487 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1488 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1489 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1490 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1491 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1492 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1493 } 1494 1495 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1496 if (chip->chip_id == RTL8852C) { 1497 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1498 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1499 seq_printf(m, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1500 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1501 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1502 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1503 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1504 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1505 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1506 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1507 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1508 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1509 } else { 1510 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1511 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1512 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1513 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1514 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1515 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1516 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1517 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1518 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1519 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1520 } 1521 } 1522 1523 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1524 seq_printf(m, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1525 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1526 seq_printf(m, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1527 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1528 } 1529 1530 return 0; 1531 } 1532 1533 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1534 struct seq_file *m, 1535 enum rtw89_mac_idx band) 1536 { 1537 const struct rtw89_chip_info *chip = rtwdev->chip; 1538 u32 offset = 0; 1539 u32 cmac_err; 1540 int ret; 1541 1542 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1543 if (ret) { 1544 if (band) 1545 seq_puts(m, "[CMAC] : CMAC1 not enabled\n"); 1546 else 1547 seq_puts(m, "[CMAC] : CMAC0 not enabled\n"); 1548 return ret; 1549 } 1550 1551 if (band) 1552 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1553 1554 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1555 seq_printf(m, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1556 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1557 seq_printf(m, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1558 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1559 seq_printf(m, "R_AX_CK_EN [%d]=0x%08x\n", band, 1560 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1561 1562 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1563 seq_printf(m, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1564 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1565 seq_printf(m, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1566 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1567 } 1568 1569 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1570 seq_printf(m, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 1571 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1572 seq_printf(m, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 1573 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1574 } 1575 1576 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1577 if (chip->chip_id == RTL8852C) { 1578 seq_printf(m, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1579 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1580 seq_printf(m, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 1581 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1582 } else { 1583 seq_printf(m, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1584 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1585 } 1586 } 1587 1588 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1589 if (chip->chip_id == RTL8852C) { 1590 seq_printf(m, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 1591 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1592 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1593 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1594 } else { 1595 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1596 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1597 } 1598 } 1599 1600 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1601 seq_printf(m, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 1602 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1603 seq_printf(m, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 1604 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1605 } 1606 1607 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1608 if (chip->chip_id == RTL8852C) { 1609 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 1610 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 1611 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 1612 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1613 } else { 1614 seq_printf(m, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 1615 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 1616 } 1617 seq_printf(m, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1618 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1619 } 1620 1621 seq_printf(m, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1622 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1623 1624 return 0; 1625 } 1626 1627 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1628 struct seq_file *m) 1629 { 1630 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_0); 1631 if (rtwdev->dbcc_en) 1632 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_1); 1633 1634 return 0; 1635 } 1636 1637 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1638 .sel_addr = R_AX_PTCL_DBG, 1639 .sel_byte = 1, 1640 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1641 .srt = 0x00, 1642 .end = 0x3F, 1643 .rd_addr = R_AX_PTCL_DBG_INFO, 1644 .rd_byte = 4, 1645 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1646 }; 1647 1648 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1649 .sel_addr = R_AX_PTCL_DBG_C1, 1650 .sel_byte = 1, 1651 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1652 .srt = 0x00, 1653 .end = 0x3F, 1654 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1655 .rd_byte = 4, 1656 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1657 }; 1658 1659 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1660 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1661 .sel_byte = 2, 1662 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1663 .srt = 0x0, 1664 .end = 0xD, 1665 .rd_addr = R_AX_DBG_PORT_SEL, 1666 .rd_byte = 4, 1667 .rd_msk = B_AX_DEBUG_ST_MASK 1668 }; 1669 1670 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1671 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1672 .sel_byte = 2, 1673 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1674 .srt = 0x0, 1675 .end = 0x5, 1676 .rd_addr = R_AX_DBG_PORT_SEL, 1677 .rd_byte = 4, 1678 .rd_msk = B_AX_DEBUG_ST_MASK 1679 }; 1680 1681 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1682 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1683 .sel_byte = 2, 1684 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1685 .srt = 0x0, 1686 .end = 0x9, 1687 .rd_addr = R_AX_DBG_PORT_SEL, 1688 .rd_byte = 4, 1689 .rd_msk = B_AX_DEBUG_ST_MASK 1690 }; 1691 1692 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1693 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1694 .sel_byte = 2, 1695 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1696 .srt = 0x0, 1697 .end = 0x3, 1698 .rd_addr = R_AX_DBG_PORT_SEL, 1699 .rd_byte = 4, 1700 .rd_msk = B_AX_DEBUG_ST_MASK 1701 }; 1702 1703 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1704 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1705 .sel_byte = 2, 1706 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1707 .srt = 0x0, 1708 .end = 0x1, 1709 .rd_addr = R_AX_DBG_PORT_SEL, 1710 .rd_byte = 4, 1711 .rd_msk = B_AX_DEBUG_ST_MASK 1712 }; 1713 1714 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1715 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1716 .sel_byte = 2, 1717 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1718 .srt = 0x0, 1719 .end = 0x0, 1720 .rd_addr = R_AX_DBG_PORT_SEL, 1721 .rd_byte = 4, 1722 .rd_msk = B_AX_DEBUG_ST_MASK 1723 }; 1724 1725 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1726 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1727 .sel_byte = 2, 1728 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1729 .srt = 0x0, 1730 .end = 0xB, 1731 .rd_addr = R_AX_DBG_PORT_SEL, 1732 .rd_byte = 4, 1733 .rd_msk = B_AX_DEBUG_ST_MASK 1734 }; 1735 1736 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1737 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1738 .sel_byte = 2, 1739 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1740 .srt = 0x0, 1741 .end = 0x4, 1742 .rd_addr = R_AX_DBG_PORT_SEL, 1743 .rd_byte = 4, 1744 .rd_msk = B_AX_DEBUG_ST_MASK 1745 }; 1746 1747 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1748 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1749 .sel_byte = 2, 1750 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1751 .srt = 0x0, 1752 .end = 0x8, 1753 .rd_addr = R_AX_DBG_PORT_SEL, 1754 .rd_byte = 4, 1755 .rd_msk = B_AX_DEBUG_ST_MASK 1756 }; 1757 1758 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1759 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1760 .sel_byte = 2, 1761 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1762 .srt = 0x0, 1763 .end = 0x7, 1764 .rd_addr = R_AX_DBG_PORT_SEL, 1765 .rd_byte = 4, 1766 .rd_msk = B_AX_DEBUG_ST_MASK 1767 }; 1768 1769 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 1770 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1771 .sel_byte = 2, 1772 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1773 .srt = 0x0, 1774 .end = 0x1, 1775 .rd_addr = R_AX_DBG_PORT_SEL, 1776 .rd_byte = 4, 1777 .rd_msk = B_AX_DEBUG_ST_MASK 1778 }; 1779 1780 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 1781 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1782 .sel_byte = 2, 1783 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1784 .srt = 0x0, 1785 .end = 0x3, 1786 .rd_addr = R_AX_DBG_PORT_SEL, 1787 .rd_byte = 4, 1788 .rd_msk = B_AX_DEBUG_ST_MASK 1789 }; 1790 1791 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 1792 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1793 .sel_byte = 2, 1794 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1795 .srt = 0x0, 1796 .end = 0x0, 1797 .rd_addr = R_AX_DBG_PORT_SEL, 1798 .rd_byte = 4, 1799 .rd_msk = B_AX_DEBUG_ST_MASK 1800 }; 1801 1802 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 1803 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1804 .sel_byte = 2, 1805 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1806 .srt = 0x0, 1807 .end = 0x8, 1808 .rd_addr = R_AX_DBG_PORT_SEL, 1809 .rd_byte = 4, 1810 .rd_msk = B_AX_DEBUG_ST_MASK 1811 }; 1812 1813 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 1814 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1815 .sel_byte = 2, 1816 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1817 .srt = 0x0, 1818 .end = 0x0, 1819 .rd_addr = R_AX_DBG_PORT_SEL, 1820 .rd_byte = 4, 1821 .rd_msk = B_AX_DEBUG_ST_MASK 1822 }; 1823 1824 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 1825 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1826 .sel_byte = 2, 1827 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1828 .srt = 0x0, 1829 .end = 0x6, 1830 .rd_addr = R_AX_DBG_PORT_SEL, 1831 .rd_byte = 4, 1832 .rd_msk = B_AX_DEBUG_ST_MASK 1833 }; 1834 1835 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 1836 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1837 .sel_byte = 2, 1838 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1839 .srt = 0x0, 1840 .end = 0x0, 1841 .rd_addr = R_AX_DBG_PORT_SEL, 1842 .rd_byte = 4, 1843 .rd_msk = B_AX_DEBUG_ST_MASK 1844 }; 1845 1846 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 1847 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1848 .sel_byte = 2, 1849 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1850 .srt = 0x0, 1851 .end = 0x0, 1852 .rd_addr = R_AX_DBG_PORT_SEL, 1853 .rd_byte = 4, 1854 .rd_msk = B_AX_DEBUG_ST_MASK 1855 }; 1856 1857 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 1858 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1859 .sel_byte = 1, 1860 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1861 .srt = 0x0, 1862 .end = 0x3, 1863 .rd_addr = R_AX_DBG_PORT_SEL, 1864 .rd_byte = 4, 1865 .rd_msk = B_AX_DEBUG_ST_MASK 1866 }; 1867 1868 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 1869 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1870 .sel_byte = 1, 1871 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1872 .srt = 0x0, 1873 .end = 0x6, 1874 .rd_addr = R_AX_DBG_PORT_SEL, 1875 .rd_byte = 4, 1876 .rd_msk = B_AX_DEBUG_ST_MASK 1877 }; 1878 1879 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 1880 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1881 .sel_byte = 1, 1882 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1883 .srt = 0x0, 1884 .end = 0x0, 1885 .rd_addr = R_AX_DBG_PORT_SEL, 1886 .rd_byte = 4, 1887 .rd_msk = B_AX_DEBUG_ST_MASK 1888 }; 1889 1890 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 1891 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1892 .sel_byte = 1, 1893 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1894 .srt = 0x8, 1895 .end = 0xE, 1896 .rd_addr = R_AX_DBG_PORT_SEL, 1897 .rd_byte = 4, 1898 .rd_msk = B_AX_DEBUG_ST_MASK 1899 }; 1900 1901 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 1902 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1903 .sel_byte = 1, 1904 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1905 .srt = 0x0, 1906 .end = 0x5, 1907 .rd_addr = R_AX_DBG_PORT_SEL, 1908 .rd_byte = 4, 1909 .rd_msk = B_AX_DEBUG_ST_MASK 1910 }; 1911 1912 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 1913 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1914 .sel_byte = 1, 1915 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1916 .srt = 0x0, 1917 .end = 0x6, 1918 .rd_addr = R_AX_DBG_PORT_SEL, 1919 .rd_byte = 4, 1920 .rd_msk = B_AX_DEBUG_ST_MASK 1921 }; 1922 1923 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 1924 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1925 .sel_byte = 1, 1926 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1927 .srt = 0x0, 1928 .end = 0xF, 1929 .rd_addr = R_AX_DBG_PORT_SEL, 1930 .rd_byte = 4, 1931 .rd_msk = B_AX_DEBUG_ST_MASK 1932 }; 1933 1934 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 1935 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1936 .sel_byte = 1, 1937 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1938 .srt = 0x0, 1939 .end = 0x9, 1940 .rd_addr = R_AX_DBG_PORT_SEL, 1941 .rd_byte = 4, 1942 .rd_msk = B_AX_DEBUG_ST_MASK 1943 }; 1944 1945 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 1946 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1947 .sel_byte = 1, 1948 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1949 .srt = 0x0, 1950 .end = 0x3, 1951 .rd_addr = R_AX_DBG_PORT_SEL, 1952 .rd_byte = 4, 1953 .rd_msk = B_AX_DEBUG_ST_MASK 1954 }; 1955 1956 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 1957 .sel_addr = R_AX_SCH_DBG_SEL, 1958 .sel_byte = 1, 1959 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1960 .srt = 0x00, 1961 .end = 0x2F, 1962 .rd_addr = R_AX_SCH_DBG, 1963 .rd_byte = 4, 1964 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1965 }; 1966 1967 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 1968 .sel_addr = R_AX_SCH_DBG_SEL_C1, 1969 .sel_byte = 1, 1970 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1971 .srt = 0x00, 1972 .end = 0x2F, 1973 .rd_addr = R_AX_SCH_DBG_C1, 1974 .rd_byte = 4, 1975 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1976 }; 1977 1978 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 1979 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 1980 .sel_byte = 1, 1981 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1982 .srt = 0x00, 1983 .end = 0x19, 1984 .rd_addr = R_AX_DBG_PORT_SEL, 1985 .rd_byte = 4, 1986 .rd_msk = B_AX_DEBUG_ST_MASK 1987 }; 1988 1989 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 1990 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 1991 .sel_byte = 1, 1992 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1993 .srt = 0x00, 1994 .end = 0x19, 1995 .rd_addr = R_AX_DBG_PORT_SEL, 1996 .rd_byte = 4, 1997 .rd_msk = B_AX_DEBUG_ST_MASK 1998 }; 1999 2000 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 2001 .sel_addr = R_AX_RX_DEBUG_SELECT, 2002 .sel_byte = 1, 2003 .sel_msk = B_AX_DEBUG_SEL_MASK, 2004 .srt = 0x00, 2005 .end = 0x58, 2006 .rd_addr = R_AX_DBG_PORT_SEL, 2007 .rd_byte = 4, 2008 .rd_msk = B_AX_DEBUG_ST_MASK 2009 }; 2010 2011 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 2012 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 2013 .sel_byte = 1, 2014 .sel_msk = B_AX_DEBUG_SEL_MASK, 2015 .srt = 0x00, 2016 .end = 0x58, 2017 .rd_addr = R_AX_DBG_PORT_SEL, 2018 .rd_byte = 4, 2019 .rd_msk = B_AX_DEBUG_ST_MASK 2020 }; 2021 2022 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 2023 .sel_addr = R_AX_RX_STATE_MONITOR, 2024 .sel_byte = 1, 2025 .sel_msk = B_AX_STATE_SEL_MASK, 2026 .srt = 0x00, 2027 .end = 0x17, 2028 .rd_addr = R_AX_RX_STATE_MONITOR, 2029 .rd_byte = 4, 2030 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2031 }; 2032 2033 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 2034 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 2035 .sel_byte = 1, 2036 .sel_msk = B_AX_STATE_SEL_MASK, 2037 .srt = 0x00, 2038 .end = 0x17, 2039 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 2040 .rd_byte = 4, 2041 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2042 }; 2043 2044 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 2045 .sel_addr = R_AX_RMAC_PLCP_MON, 2046 .sel_byte = 4, 2047 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2048 .srt = 0x0, 2049 .end = 0xF, 2050 .rd_addr = R_AX_RMAC_PLCP_MON, 2051 .rd_byte = 4, 2052 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2053 }; 2054 2055 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 2056 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 2057 .sel_byte = 4, 2058 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2059 .srt = 0x0, 2060 .end = 0xF, 2061 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 2062 .rd_byte = 4, 2063 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2064 }; 2065 2066 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 2067 .sel_addr = R_AX_DBGSEL_TRXPTCL, 2068 .sel_byte = 1, 2069 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2070 .srt = 0x08, 2071 .end = 0x10, 2072 .rd_addr = R_AX_DBG_PORT_SEL, 2073 .rd_byte = 4, 2074 .rd_msk = B_AX_DEBUG_ST_MASK 2075 }; 2076 2077 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 2078 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 2079 .sel_byte = 1, 2080 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2081 .srt = 0x08, 2082 .end = 0x10, 2083 .rd_addr = R_AX_DBG_PORT_SEL, 2084 .rd_byte = 4, 2085 .rd_msk = B_AX_DEBUG_ST_MASK 2086 }; 2087 2088 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 2089 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2090 .sel_byte = 1, 2091 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2092 .srt = 0x00, 2093 .end = 0x07, 2094 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 2095 .rd_byte = 4, 2096 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2097 }; 2098 2099 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 2100 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2101 .sel_byte = 1, 2102 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2103 .srt = 0x00, 2104 .end = 0x07, 2105 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 2106 .rd_byte = 4, 2107 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2108 }; 2109 2110 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 2111 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2112 .sel_byte = 1, 2113 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2114 .srt = 0x00, 2115 .end = 0x07, 2116 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 2117 .rd_byte = 4, 2118 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2119 }; 2120 2121 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 2122 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2123 .sel_byte = 1, 2124 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2125 .srt = 0x00, 2126 .end = 0x07, 2127 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 2128 .rd_byte = 4, 2129 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2130 }; 2131 2132 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 2133 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2134 .sel_byte = 1, 2135 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2136 .srt = 0x00, 2137 .end = 0x04, 2138 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 2139 .rd_byte = 4, 2140 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2141 }; 2142 2143 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 2144 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2145 .sel_byte = 1, 2146 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2147 .srt = 0x00, 2148 .end = 0x04, 2149 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 2150 .rd_byte = 4, 2151 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2152 }; 2153 2154 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 2155 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2156 .sel_byte = 1, 2157 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2158 .srt = 0x00, 2159 .end = 0x04, 2160 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 2161 .rd_byte = 4, 2162 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2163 }; 2164 2165 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 2166 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2167 .sel_byte = 1, 2168 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2169 .srt = 0x00, 2170 .end = 0x04, 2171 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 2172 .rd_byte = 4, 2173 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2174 }; 2175 2176 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 2177 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2178 .sel_byte = 4, 2179 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2180 .srt = 0x80000000, 2181 .end = 0x80000001, 2182 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2183 .rd_byte = 4, 2184 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2185 }; 2186 2187 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 2188 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2189 .sel_byte = 4, 2190 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2191 .srt = 0x80010000, 2192 .end = 0x80010004, 2193 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2194 .rd_byte = 4, 2195 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2196 }; 2197 2198 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 2199 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2200 .sel_byte = 4, 2201 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2202 .srt = 0x80020000, 2203 .end = 0x80020FFF, 2204 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2205 .rd_byte = 4, 2206 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2207 }; 2208 2209 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 2210 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2211 .sel_byte = 4, 2212 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2213 .srt = 0x80030000, 2214 .end = 0x80030FFF, 2215 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2216 .rd_byte = 4, 2217 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2218 }; 2219 2220 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 2221 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2222 .sel_byte = 4, 2223 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2224 .srt = 0x80040000, 2225 .end = 0x80040FFF, 2226 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2227 .rd_byte = 4, 2228 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2229 }; 2230 2231 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 2232 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2233 .sel_byte = 4, 2234 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2235 .srt = 0x80050000, 2236 .end = 0x80050FFF, 2237 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2238 .rd_byte = 4, 2239 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2240 }; 2241 2242 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 2243 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2244 .sel_byte = 4, 2245 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2246 .srt = 0x80060000, 2247 .end = 0x80060453, 2248 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2249 .rd_byte = 4, 2250 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2251 }; 2252 2253 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 2254 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2255 .sel_byte = 4, 2256 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2257 .srt = 0x80070000, 2258 .end = 0x80070011, 2259 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2260 .rd_byte = 4, 2261 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2262 }; 2263 2264 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 2265 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2266 .sel_byte = 4, 2267 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2268 .srt = 0x80000000, 2269 .end = 0x80000001, 2270 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2271 .rd_byte = 4, 2272 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2273 }; 2274 2275 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 2276 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2277 .sel_byte = 4, 2278 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2279 .srt = 0x80010000, 2280 .end = 0x8001000A, 2281 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2282 .rd_byte = 4, 2283 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2284 }; 2285 2286 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2287 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2288 .sel_byte = 4, 2289 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2290 .srt = 0x80020000, 2291 .end = 0x80020DBF, 2292 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2293 .rd_byte = 4, 2294 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2295 }; 2296 2297 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2298 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2299 .sel_byte = 4, 2300 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2301 .srt = 0x80030000, 2302 .end = 0x80030DBF, 2303 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2304 .rd_byte = 4, 2305 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2306 }; 2307 2308 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2309 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2310 .sel_byte = 4, 2311 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2312 .srt = 0x80040000, 2313 .end = 0x80040DBF, 2314 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2315 .rd_byte = 4, 2316 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2317 }; 2318 2319 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2320 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2321 .sel_byte = 4, 2322 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2323 .srt = 0x80050000, 2324 .end = 0x80050DBF, 2325 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2326 .rd_byte = 4, 2327 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2328 }; 2329 2330 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2331 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2332 .sel_byte = 4, 2333 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2334 .srt = 0x80060000, 2335 .end = 0x80060041, 2336 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2337 .rd_byte = 4, 2338 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2339 }; 2340 2341 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2342 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2343 .sel_byte = 4, 2344 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2345 .srt = 0x80070000, 2346 .end = 0x80070001, 2347 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2348 .rd_byte = 4, 2349 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2350 }; 2351 2352 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2353 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2354 .sel_byte = 4, 2355 .sel_msk = B_AX_DFI_DATA_MASK, 2356 .srt = 0x80000000, 2357 .end = 0x8000017f, 2358 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2359 .rd_byte = 4, 2360 .rd_msk = B_AX_DFI_DATA_MASK 2361 }; 2362 2363 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2364 .sel_addr = R_AX_PCIE_DBG_CTRL, 2365 .sel_byte = 2, 2366 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2367 .srt = 0x00, 2368 .end = 0x03, 2369 .rd_addr = R_AX_DBG_PORT_SEL, 2370 .rd_byte = 4, 2371 .rd_msk = B_AX_DEBUG_ST_MASK 2372 }; 2373 2374 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2375 .sel_addr = R_AX_PCIE_DBG_CTRL, 2376 .sel_byte = 2, 2377 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2378 .srt = 0x00, 2379 .end = 0x04, 2380 .rd_addr = R_AX_DBG_PORT_SEL, 2381 .rd_byte = 4, 2382 .rd_msk = B_AX_DEBUG_ST_MASK 2383 }; 2384 2385 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2386 .sel_addr = R_AX_PCIE_DBG_CTRL, 2387 .sel_byte = 2, 2388 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2389 .srt = 0x00, 2390 .end = 0x01, 2391 .rd_addr = R_AX_DBG_PORT_SEL, 2392 .rd_byte = 4, 2393 .rd_msk = B_AX_DEBUG_ST_MASK 2394 }; 2395 2396 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2397 .sel_addr = R_AX_PCIE_DBG_CTRL, 2398 .sel_byte = 2, 2399 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2400 .srt = 0x00, 2401 .end = 0x05, 2402 .rd_addr = R_AX_DBG_PORT_SEL, 2403 .rd_byte = 4, 2404 .rd_msk = B_AX_DEBUG_ST_MASK 2405 }; 2406 2407 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2408 .sel_addr = R_AX_PCIE_DBG_CTRL, 2409 .sel_byte = 2, 2410 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2411 .srt = 0x00, 2412 .end = 0x05, 2413 .rd_addr = R_AX_DBG_PORT_SEL, 2414 .rd_byte = 4, 2415 .rd_msk = B_AX_DEBUG_ST_MASK 2416 }; 2417 2418 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2419 .sel_addr = R_AX_PCIE_DBG_CTRL, 2420 .sel_byte = 2, 2421 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2422 .srt = 0x00, 2423 .end = 0x06, 2424 .rd_addr = R_AX_DBG_PORT_SEL, 2425 .rd_byte = 4, 2426 .rd_msk = B_AX_DEBUG_ST_MASK 2427 }; 2428 2429 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2430 .sel_addr = R_AX_DBG_CTRL, 2431 .sel_byte = 1, 2432 .sel_msk = B_AX_DBG_SEL0, 2433 .srt = 0x34, 2434 .end = 0x3C, 2435 .rd_addr = R_AX_DBG_PORT_SEL, 2436 .rd_byte = 4, 2437 .rd_msk = B_AX_DEBUG_ST_MASK 2438 }; 2439 2440 static const struct rtw89_mac_dbg_port_info * 2441 rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 2442 struct rtw89_dev *rtwdev, u32 sel) 2443 { 2444 const struct rtw89_mac_dbg_port_info *info; 2445 u32 index; 2446 u32 val32; 2447 u16 val16; 2448 u8 val8; 2449 2450 switch (sel) { 2451 case RTW89_DBG_PORT_SEL_PTCL_C0: 2452 info = &dbg_port_ptcl_c0; 2453 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2454 val16 |= B_AX_PTCL_DBG_EN; 2455 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2456 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 2457 break; 2458 case RTW89_DBG_PORT_SEL_PTCL_C1: 2459 info = &dbg_port_ptcl_c1; 2460 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2461 val16 |= B_AX_PTCL_DBG_EN; 2462 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2463 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 2464 break; 2465 case RTW89_DBG_PORT_SEL_SCH_C0: 2466 info = &dbg_port_sch_c0; 2467 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2468 val32 |= B_AX_SCH_DBG_EN; 2469 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2470 seq_puts(m, "Enable SCH C0 dbgport.\n"); 2471 break; 2472 case RTW89_DBG_PORT_SEL_SCH_C1: 2473 info = &dbg_port_sch_c1; 2474 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2475 val32 |= B_AX_SCH_DBG_EN; 2476 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2477 seq_puts(m, "Enable SCH C1 dbgport.\n"); 2478 break; 2479 case RTW89_DBG_PORT_SEL_TMAC_C0: 2480 info = &dbg_port_tmac_c0; 2481 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2482 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2483 B_AX_DBGSEL_TRXPTCL_MASK); 2484 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2485 2486 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2487 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2488 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2489 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2490 2491 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2492 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2493 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2494 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 2495 break; 2496 case RTW89_DBG_PORT_SEL_TMAC_C1: 2497 info = &dbg_port_tmac_c1; 2498 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2499 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2500 B_AX_DBGSEL_TRXPTCL_MASK); 2501 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2502 2503 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2504 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2505 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2506 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2507 2508 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2509 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2510 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2511 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 2512 break; 2513 case RTW89_DBG_PORT_SEL_RMAC_C0: 2514 info = &dbg_port_rmac_c0; 2515 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2516 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2517 B_AX_DBGSEL_TRXPTCL_MASK); 2518 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2519 2520 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2521 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2522 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2523 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2524 2525 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2526 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2527 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2528 2529 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2530 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2531 B_AX_DBGSEL_TRXPTCL_MASK); 2532 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2533 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 2534 break; 2535 case RTW89_DBG_PORT_SEL_RMAC_C1: 2536 info = &dbg_port_rmac_c1; 2537 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2538 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2539 B_AX_DBGSEL_TRXPTCL_MASK); 2540 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2541 2542 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2543 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2544 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2545 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2546 2547 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2548 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2549 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2550 2551 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2552 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2553 B_AX_DBGSEL_TRXPTCL_MASK); 2554 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2555 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 2556 break; 2557 case RTW89_DBG_PORT_SEL_RMACST_C0: 2558 info = &dbg_port_rmacst_c0; 2559 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 2560 break; 2561 case RTW89_DBG_PORT_SEL_RMACST_C1: 2562 info = &dbg_port_rmacst_c1; 2563 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 2564 break; 2565 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2566 info = &dbg_port_rmac_plcp_c0; 2567 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 2568 break; 2569 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2570 info = &dbg_port_rmac_plcp_c1; 2571 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 2572 break; 2573 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2574 info = &dbg_port_trxptcl_c0; 2575 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2576 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2577 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2578 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2579 2580 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2581 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2582 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2583 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 2584 break; 2585 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2586 info = &dbg_port_trxptcl_c1; 2587 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2588 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2589 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2590 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2591 2592 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2593 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2594 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2595 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 2596 break; 2597 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2598 info = &dbg_port_tx_infol_c0; 2599 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2600 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2601 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2602 seq_puts(m, "Enable tx infol dump.\n"); 2603 break; 2604 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2605 info = &dbg_port_tx_infoh_c0; 2606 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2607 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2608 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2609 seq_puts(m, "Enable tx infoh dump.\n"); 2610 break; 2611 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2612 info = &dbg_port_tx_infol_c1; 2613 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2614 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2615 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2616 seq_puts(m, "Enable tx infol dump.\n"); 2617 break; 2618 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2619 info = &dbg_port_tx_infoh_c1; 2620 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2621 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2622 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2623 seq_puts(m, "Enable tx infoh dump.\n"); 2624 break; 2625 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2626 info = &dbg_port_txtf_infol_c0; 2627 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2628 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2629 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2630 seq_puts(m, "Enable tx tf infol dump.\n"); 2631 break; 2632 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2633 info = &dbg_port_txtf_infoh_c0; 2634 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2635 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2636 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2637 seq_puts(m, "Enable tx tf infoh dump.\n"); 2638 break; 2639 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2640 info = &dbg_port_txtf_infol_c1; 2641 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2642 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2643 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2644 seq_puts(m, "Enable tx tf infol dump.\n"); 2645 break; 2646 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2647 info = &dbg_port_txtf_infoh_c1; 2648 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2649 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2650 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2651 seq_puts(m, "Enable tx tf infoh dump.\n"); 2652 break; 2653 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2654 info = &dbg_port_wde_bufmgn_freepg; 2655 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 2656 break; 2657 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2658 info = &dbg_port_wde_bufmgn_quota; 2659 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 2660 break; 2661 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2662 info = &dbg_port_wde_bufmgn_pagellt; 2663 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 2664 break; 2665 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2666 info = &dbg_port_wde_bufmgn_pktinfo; 2667 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 2668 break; 2669 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2670 info = &dbg_port_wde_quemgn_prepkt; 2671 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 2672 break; 2673 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2674 info = &dbg_port_wde_quemgn_nxtpkt; 2675 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 2676 break; 2677 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2678 info = &dbg_port_wde_quemgn_qlnktbl; 2679 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 2680 break; 2681 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2682 info = &dbg_port_wde_quemgn_qempty; 2683 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 2684 break; 2685 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2686 info = &dbg_port_ple_bufmgn_freepg; 2687 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 2688 break; 2689 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2690 info = &dbg_port_ple_bufmgn_quota; 2691 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 2692 break; 2693 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2694 info = &dbg_port_ple_bufmgn_pagellt; 2695 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 2696 break; 2697 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2698 info = &dbg_port_ple_bufmgn_pktinfo; 2699 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 2700 break; 2701 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2702 info = &dbg_port_ple_quemgn_prepkt; 2703 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 2704 break; 2705 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2706 info = &dbg_port_ple_quemgn_nxtpkt; 2707 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 2708 break; 2709 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2710 info = &dbg_port_ple_quemgn_qlnktbl; 2711 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 2712 break; 2713 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2714 info = &dbg_port_ple_quemgn_qempty; 2715 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 2716 break; 2717 case RTW89_DBG_PORT_SEL_PKTINFO: 2718 info = &dbg_port_pktinfo; 2719 seq_puts(m, "Enable pktinfo dump.\n"); 2720 break; 2721 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2722 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2723 B_AX_DBG_SEL0, 0x80); 2724 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2725 B_AX_SEL_0XC0_MASK, 1); 2726 fallthrough; 2727 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2728 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2729 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2730 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2731 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2732 info = &dbg_port_dspt_hdt_tx0_5; 2733 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2734 rtw89_write16_mask(rtwdev, info->sel_addr, 2735 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2736 rtw89_write16_mask(rtwdev, info->sel_addr, 2737 B_AX_DISPATCHER_CH_SEL_MASK, index); 2738 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2739 break; 2740 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2741 info = &dbg_port_dspt_hdt_tx6; 2742 rtw89_write16_mask(rtwdev, info->sel_addr, 2743 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2744 rtw89_write16_mask(rtwdev, info->sel_addr, 2745 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2746 seq_puts(m, "Enable Dispatcher hdt tx6 dump.\n"); 2747 break; 2748 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2749 info = &dbg_port_dspt_hdt_tx7; 2750 rtw89_write16_mask(rtwdev, info->sel_addr, 2751 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2752 rtw89_write16_mask(rtwdev, info->sel_addr, 2753 B_AX_DISPATCHER_CH_SEL_MASK, 7); 2754 seq_puts(m, "Enable Dispatcher hdt tx7 dump.\n"); 2755 break; 2756 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 2757 info = &dbg_port_dspt_hdt_tx8; 2758 rtw89_write16_mask(rtwdev, info->sel_addr, 2759 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2760 rtw89_write16_mask(rtwdev, info->sel_addr, 2761 B_AX_DISPATCHER_CH_SEL_MASK, 8); 2762 seq_puts(m, "Enable Dispatcher hdt tx8 dump.\n"); 2763 break; 2764 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 2765 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 2766 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 2767 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 2768 info = &dbg_port_dspt_hdt_tx9_C; 2769 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 2770 rtw89_write16_mask(rtwdev, info->sel_addr, 2771 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2772 rtw89_write16_mask(rtwdev, info->sel_addr, 2773 B_AX_DISPATCHER_CH_SEL_MASK, index); 2774 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2775 break; 2776 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 2777 info = &dbg_port_dspt_hdt_txD; 2778 rtw89_write16_mask(rtwdev, info->sel_addr, 2779 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2780 rtw89_write16_mask(rtwdev, info->sel_addr, 2781 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 2782 seq_puts(m, "Enable Dispatcher hdt txD dump.\n"); 2783 break; 2784 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 2785 info = &dbg_port_dspt_cdt_tx0; 2786 rtw89_write16_mask(rtwdev, info->sel_addr, 2787 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2788 rtw89_write16_mask(rtwdev, info->sel_addr, 2789 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2790 seq_puts(m, "Enable Dispatcher cdt tx0 dump.\n"); 2791 break; 2792 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 2793 info = &dbg_port_dspt_cdt_tx1; 2794 rtw89_write16_mask(rtwdev, info->sel_addr, 2795 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2796 rtw89_write16_mask(rtwdev, info->sel_addr, 2797 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2798 seq_puts(m, "Enable Dispatcher cdt tx1 dump.\n"); 2799 break; 2800 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 2801 info = &dbg_port_dspt_cdt_tx3; 2802 rtw89_write16_mask(rtwdev, info->sel_addr, 2803 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2804 rtw89_write16_mask(rtwdev, info->sel_addr, 2805 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2806 seq_puts(m, "Enable Dispatcher cdt tx3 dump.\n"); 2807 break; 2808 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 2809 info = &dbg_port_dspt_cdt_tx4; 2810 rtw89_write16_mask(rtwdev, info->sel_addr, 2811 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2812 rtw89_write16_mask(rtwdev, info->sel_addr, 2813 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2814 seq_puts(m, "Enable Dispatcher cdt tx4 dump.\n"); 2815 break; 2816 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 2817 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 2818 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 2819 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 2820 info = &dbg_port_dspt_cdt_tx5_8; 2821 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 2822 rtw89_write16_mask(rtwdev, info->sel_addr, 2823 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2824 rtw89_write16_mask(rtwdev, info->sel_addr, 2825 B_AX_DISPATCHER_CH_SEL_MASK, index); 2826 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2827 break; 2828 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 2829 info = &dbg_port_dspt_cdt_tx9; 2830 rtw89_write16_mask(rtwdev, info->sel_addr, 2831 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2832 rtw89_write16_mask(rtwdev, info->sel_addr, 2833 B_AX_DISPATCHER_CH_SEL_MASK, 9); 2834 seq_puts(m, "Enable Dispatcher cdt tx9 dump.\n"); 2835 break; 2836 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 2837 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 2838 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 2839 info = &dbg_port_dspt_cdt_txA_C; 2840 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 2841 rtw89_write16_mask(rtwdev, info->sel_addr, 2842 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2843 rtw89_write16_mask(rtwdev, info->sel_addr, 2844 B_AX_DISPATCHER_CH_SEL_MASK, index); 2845 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2846 break; 2847 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 2848 info = &dbg_port_dspt_hdt_rx0; 2849 rtw89_write16_mask(rtwdev, info->sel_addr, 2850 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2851 rtw89_write16_mask(rtwdev, info->sel_addr, 2852 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2853 seq_puts(m, "Enable Dispatcher hdt rx0 dump.\n"); 2854 break; 2855 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 2856 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 2857 info = &dbg_port_dspt_hdt_rx1_2; 2858 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 2859 rtw89_write16_mask(rtwdev, info->sel_addr, 2860 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2861 rtw89_write16_mask(rtwdev, info->sel_addr, 2862 B_AX_DISPATCHER_CH_SEL_MASK, index); 2863 seq_printf(m, "Enable Dispatcher hdt rx%x dump.\n", index); 2864 break; 2865 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 2866 info = &dbg_port_dspt_hdt_rx3; 2867 rtw89_write16_mask(rtwdev, info->sel_addr, 2868 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2869 rtw89_write16_mask(rtwdev, info->sel_addr, 2870 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2871 seq_puts(m, "Enable Dispatcher hdt rx3 dump.\n"); 2872 break; 2873 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 2874 info = &dbg_port_dspt_hdt_rx4; 2875 rtw89_write16_mask(rtwdev, info->sel_addr, 2876 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2877 rtw89_write16_mask(rtwdev, info->sel_addr, 2878 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2879 seq_puts(m, "Enable Dispatcher hdt rx4 dump.\n"); 2880 break; 2881 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 2882 info = &dbg_port_dspt_hdt_rx5; 2883 rtw89_write16_mask(rtwdev, info->sel_addr, 2884 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2885 rtw89_write16_mask(rtwdev, info->sel_addr, 2886 B_AX_DISPATCHER_CH_SEL_MASK, 5); 2887 seq_puts(m, "Enable Dispatcher hdt rx5 dump.\n"); 2888 break; 2889 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 2890 info = &dbg_port_dspt_cdt_rx_p0_0; 2891 rtw89_write16_mask(rtwdev, info->sel_addr, 2892 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2893 rtw89_write16_mask(rtwdev, info->sel_addr, 2894 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2895 seq_puts(m, "Enable Dispatcher cdt rx part0 0 dump.\n"); 2896 break; 2897 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 2898 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 2899 info = &dbg_port_dspt_cdt_rx_p0_1; 2900 rtw89_write16_mask(rtwdev, info->sel_addr, 2901 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2902 rtw89_write16_mask(rtwdev, info->sel_addr, 2903 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2904 seq_puts(m, "Enable Dispatcher cdt rx part0 1 dump.\n"); 2905 break; 2906 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 2907 info = &dbg_port_dspt_cdt_rx_p0_2; 2908 rtw89_write16_mask(rtwdev, info->sel_addr, 2909 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2910 rtw89_write16_mask(rtwdev, info->sel_addr, 2911 B_AX_DISPATCHER_CH_SEL_MASK, 2); 2912 seq_puts(m, "Enable Dispatcher cdt rx part0 2 dump.\n"); 2913 break; 2914 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 2915 info = &dbg_port_dspt_cdt_rx_p1; 2916 rtw89_write8_mask(rtwdev, info->sel_addr, 2917 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2918 seq_puts(m, "Enable Dispatcher cdt rx part1 dump.\n"); 2919 break; 2920 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 2921 info = &dbg_port_dspt_stf_ctrl; 2922 rtw89_write8_mask(rtwdev, info->sel_addr, 2923 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 2924 seq_puts(m, "Enable Dispatcher stf control dump.\n"); 2925 break; 2926 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 2927 info = &dbg_port_dspt_addr_ctrl; 2928 rtw89_write8_mask(rtwdev, info->sel_addr, 2929 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 2930 seq_puts(m, "Enable Dispatcher addr control dump.\n"); 2931 break; 2932 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 2933 info = &dbg_port_dspt_wde_intf; 2934 rtw89_write8_mask(rtwdev, info->sel_addr, 2935 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 2936 seq_puts(m, "Enable Dispatcher wde interface dump.\n"); 2937 break; 2938 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 2939 info = &dbg_port_dspt_ple_intf; 2940 rtw89_write8_mask(rtwdev, info->sel_addr, 2941 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 2942 seq_puts(m, "Enable Dispatcher ple interface dump.\n"); 2943 break; 2944 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 2945 info = &dbg_port_dspt_flow_ctrl; 2946 rtw89_write8_mask(rtwdev, info->sel_addr, 2947 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 2948 seq_puts(m, "Enable Dispatcher flow control dump.\n"); 2949 break; 2950 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 2951 info = &dbg_port_pcie_txdma; 2952 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2953 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 2954 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 2955 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2956 seq_puts(m, "Enable pcie txdma dump.\n"); 2957 break; 2958 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 2959 info = &dbg_port_pcie_rxdma; 2960 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2961 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 2962 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 2963 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2964 seq_puts(m, "Enable pcie rxdma dump.\n"); 2965 break; 2966 case RTW89_DBG_PORT_SEL_PCIE_CVT: 2967 info = &dbg_port_pcie_cvt; 2968 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2969 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 2970 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 2971 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2972 seq_puts(m, "Enable pcie cvt dump.\n"); 2973 break; 2974 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 2975 info = &dbg_port_pcie_cxpl; 2976 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2977 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 2978 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 2979 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2980 seq_puts(m, "Enable pcie cxpl dump.\n"); 2981 break; 2982 case RTW89_DBG_PORT_SEL_PCIE_IO: 2983 info = &dbg_port_pcie_io; 2984 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2985 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 2986 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 2987 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2988 seq_puts(m, "Enable pcie io dump.\n"); 2989 break; 2990 case RTW89_DBG_PORT_SEL_PCIE_MISC: 2991 info = &dbg_port_pcie_misc; 2992 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2993 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 2994 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 2995 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2996 seq_puts(m, "Enable pcie misc dump.\n"); 2997 break; 2998 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 2999 info = &dbg_port_pcie_misc2; 3000 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 3001 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 3002 B_AX_PCIE_DBG_SEL_MASK); 3003 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 3004 seq_puts(m, "Enable pcie misc2 dump.\n"); 3005 break; 3006 default: 3007 seq_puts(m, "Dbg port select err\n"); 3008 return NULL; 3009 } 3010 3011 return info; 3012 } 3013 3014 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 3015 { 3016 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 3017 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 3018 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 3019 return false; 3020 if (rtw89_is_rtl885xb(rtwdev) && 3021 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3022 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3023 return false; 3024 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3025 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 3026 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 3027 return false; 3028 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3029 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 3030 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 3031 return false; 3032 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 3033 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 3034 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 3035 return false; 3036 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 3037 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3038 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3039 return false; 3040 3041 return true; 3042 } 3043 3044 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 3045 struct seq_file *m, u32 sel) 3046 { 3047 const struct rtw89_mac_dbg_port_info *info; 3048 u8 val8; 3049 u16 val16; 3050 u32 val32; 3051 u32 i; 3052 3053 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 3054 if (!info) { 3055 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 3056 return -EINVAL; 3057 } 3058 3059 #define case_DBG_SEL(__sel) \ 3060 case RTW89_DBG_PORT_SEL_##__sel: \ 3061 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 3062 break 3063 3064 switch (sel) { 3065 case_DBG_SEL(PTCL_C0); 3066 case_DBG_SEL(PTCL_C1); 3067 case_DBG_SEL(SCH_C0); 3068 case_DBG_SEL(SCH_C1); 3069 case_DBG_SEL(TMAC_C0); 3070 case_DBG_SEL(TMAC_C1); 3071 case_DBG_SEL(RMAC_C0); 3072 case_DBG_SEL(RMAC_C1); 3073 case_DBG_SEL(RMACST_C0); 3074 case_DBG_SEL(RMACST_C1); 3075 case_DBG_SEL(TRXPTCL_C0); 3076 case_DBG_SEL(TRXPTCL_C1); 3077 case_DBG_SEL(TX_INFOL_C0); 3078 case_DBG_SEL(TX_INFOH_C0); 3079 case_DBG_SEL(TX_INFOL_C1); 3080 case_DBG_SEL(TX_INFOH_C1); 3081 case_DBG_SEL(TXTF_INFOL_C0); 3082 case_DBG_SEL(TXTF_INFOH_C0); 3083 case_DBG_SEL(TXTF_INFOL_C1); 3084 case_DBG_SEL(TXTF_INFOH_C1); 3085 case_DBG_SEL(WDE_BUFMGN_FREEPG); 3086 case_DBG_SEL(WDE_BUFMGN_QUOTA); 3087 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 3088 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 3089 case_DBG_SEL(WDE_QUEMGN_PREPKT); 3090 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 3091 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 3092 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 3093 case_DBG_SEL(PLE_BUFMGN_FREEPG); 3094 case_DBG_SEL(PLE_BUFMGN_QUOTA); 3095 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 3096 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 3097 case_DBG_SEL(PLE_QUEMGN_PREPKT); 3098 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 3099 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 3100 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 3101 case_DBG_SEL(PKTINFO); 3102 case_DBG_SEL(DSPT_HDT_TX0); 3103 case_DBG_SEL(DSPT_HDT_TX1); 3104 case_DBG_SEL(DSPT_HDT_TX2); 3105 case_DBG_SEL(DSPT_HDT_TX3); 3106 case_DBG_SEL(DSPT_HDT_TX4); 3107 case_DBG_SEL(DSPT_HDT_TX5); 3108 case_DBG_SEL(DSPT_HDT_TX6); 3109 case_DBG_SEL(DSPT_HDT_TX7); 3110 case_DBG_SEL(DSPT_HDT_TX8); 3111 case_DBG_SEL(DSPT_HDT_TX9); 3112 case_DBG_SEL(DSPT_HDT_TXA); 3113 case_DBG_SEL(DSPT_HDT_TXB); 3114 case_DBG_SEL(DSPT_HDT_TXC); 3115 case_DBG_SEL(DSPT_HDT_TXD); 3116 case_DBG_SEL(DSPT_HDT_TXE); 3117 case_DBG_SEL(DSPT_HDT_TXF); 3118 case_DBG_SEL(DSPT_CDT_TX0); 3119 case_DBG_SEL(DSPT_CDT_TX1); 3120 case_DBG_SEL(DSPT_CDT_TX3); 3121 case_DBG_SEL(DSPT_CDT_TX4); 3122 case_DBG_SEL(DSPT_CDT_TX5); 3123 case_DBG_SEL(DSPT_CDT_TX6); 3124 case_DBG_SEL(DSPT_CDT_TX7); 3125 case_DBG_SEL(DSPT_CDT_TX8); 3126 case_DBG_SEL(DSPT_CDT_TX9); 3127 case_DBG_SEL(DSPT_CDT_TXA); 3128 case_DBG_SEL(DSPT_CDT_TXB); 3129 case_DBG_SEL(DSPT_CDT_TXC); 3130 case_DBG_SEL(DSPT_HDT_RX0); 3131 case_DBG_SEL(DSPT_HDT_RX1); 3132 case_DBG_SEL(DSPT_HDT_RX2); 3133 case_DBG_SEL(DSPT_HDT_RX3); 3134 case_DBG_SEL(DSPT_HDT_RX4); 3135 case_DBG_SEL(DSPT_HDT_RX5); 3136 case_DBG_SEL(DSPT_CDT_RX_P0); 3137 case_DBG_SEL(DSPT_CDT_RX_P0_0); 3138 case_DBG_SEL(DSPT_CDT_RX_P0_1); 3139 case_DBG_SEL(DSPT_CDT_RX_P0_2); 3140 case_DBG_SEL(DSPT_CDT_RX_P1); 3141 case_DBG_SEL(DSPT_STF_CTRL); 3142 case_DBG_SEL(DSPT_ADDR_CTRL); 3143 case_DBG_SEL(DSPT_WDE_INTF); 3144 case_DBG_SEL(DSPT_PLE_INTF); 3145 case_DBG_SEL(DSPT_FLOW_CTRL); 3146 case_DBG_SEL(PCIE_TXDMA); 3147 case_DBG_SEL(PCIE_RXDMA); 3148 case_DBG_SEL(PCIE_CVT); 3149 case_DBG_SEL(PCIE_CXPL); 3150 case_DBG_SEL(PCIE_IO); 3151 case_DBG_SEL(PCIE_MISC); 3152 case_DBG_SEL(PCIE_MISC2); 3153 } 3154 3155 #undef case_DBG_SEL 3156 3157 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 3158 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 3159 3160 for (i = info->srt; i <= info->end; i++) { 3161 switch (info->sel_byte) { 3162 case 1: 3163 default: 3164 rtw89_write8_mask(rtwdev, info->sel_addr, 3165 info->sel_msk, i); 3166 seq_printf(m, "0x%02X: ", i); 3167 break; 3168 case 2: 3169 rtw89_write16_mask(rtwdev, info->sel_addr, 3170 info->sel_msk, i); 3171 seq_printf(m, "0x%04X: ", i); 3172 break; 3173 case 4: 3174 rtw89_write32_mask(rtwdev, info->sel_addr, 3175 info->sel_msk, i); 3176 seq_printf(m, "0x%04X: ", i); 3177 break; 3178 } 3179 3180 udelay(10); 3181 3182 switch (info->rd_byte) { 3183 case 1: 3184 default: 3185 val8 = rtw89_read8_mask(rtwdev, 3186 info->rd_addr, info->rd_msk); 3187 seq_printf(m, "0x%02X\n", val8); 3188 break; 3189 case 2: 3190 val16 = rtw89_read16_mask(rtwdev, 3191 info->rd_addr, info->rd_msk); 3192 seq_printf(m, "0x%04X\n", val16); 3193 break; 3194 case 4: 3195 val32 = rtw89_read32_mask(rtwdev, 3196 info->rd_addr, info->rd_msk); 3197 seq_printf(m, "0x%08X\n", val32); 3198 break; 3199 } 3200 } 3201 3202 return 0; 3203 } 3204 3205 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 3206 struct seq_file *m) 3207 { 3208 u32 sel; 3209 int ret = 0; 3210 3211 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 3212 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 3213 if (!is_dbg_port_valid(rtwdev, sel)) 3214 continue; 3215 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 3216 if (ret) { 3217 rtw89_err(rtwdev, 3218 "failed to dump debug port %d\n", sel); 3219 break; 3220 } 3221 } 3222 3223 return ret; 3224 } 3225 3226 static int 3227 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 3228 { 3229 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3230 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3231 3232 if (debugfs_priv->dbgpkg_en.ss_dbg) 3233 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 3234 if (debugfs_priv->dbgpkg_en.dle_dbg) 3235 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 3236 if (debugfs_priv->dbgpkg_en.dmac_dbg) 3237 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 3238 if (debugfs_priv->dbgpkg_en.cmac_dbg) 3239 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 3240 if (debugfs_priv->dbgpkg_en.dbg_port) 3241 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 3242 3243 return 0; 3244 }; 3245 3246 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 3247 const char __user *user_buf, size_t count) 3248 { 3249 char *buf; 3250 u8 *bin; 3251 int num; 3252 int err = 0; 3253 3254 buf = memdup_user(user_buf, count); 3255 if (IS_ERR(buf)) 3256 return buf; 3257 3258 num = count / 2; 3259 bin = kmalloc(num, GFP_KERNEL); 3260 if (!bin) { 3261 err = -EFAULT; 3262 goto out; 3263 } 3264 3265 if (hex2bin(bin, buf, num)) { 3266 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 3267 kfree(bin); 3268 err = -EINVAL; 3269 } 3270 3271 out: 3272 kfree(buf); 3273 3274 return err ? ERR_PTR(err) : bin; 3275 } 3276 3277 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 3278 const char __user *user_buf, 3279 size_t count, loff_t *loff) 3280 { 3281 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3282 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3283 u8 *h2c; 3284 int ret; 3285 u16 h2c_len = count / 2; 3286 3287 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3288 if (IS_ERR(h2c)) 3289 return -EFAULT; 3290 3291 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3292 3293 kfree(h2c); 3294 3295 return ret ? ret : count; 3296 } 3297 3298 static int 3299 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 3300 { 3301 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3302 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3303 struct rtw89_early_h2c *early_h2c; 3304 int seq = 0; 3305 3306 mutex_lock(&rtwdev->mutex); 3307 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3308 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 3309 mutex_unlock(&rtwdev->mutex); 3310 3311 return 0; 3312 } 3313 3314 static ssize_t 3315 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 3316 size_t count, loff_t *loff) 3317 { 3318 struct seq_file *m = (struct seq_file *)filp->private_data; 3319 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3320 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3321 struct rtw89_early_h2c *early_h2c; 3322 u8 *h2c; 3323 u16 h2c_len = count / 2; 3324 3325 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3326 if (IS_ERR(h2c)) 3327 return -EFAULT; 3328 3329 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3330 kfree(h2c); 3331 rtw89_fw_free_all_early_h2c(rtwdev); 3332 goto out; 3333 } 3334 3335 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 3336 if (!early_h2c) { 3337 kfree(h2c); 3338 return -EFAULT; 3339 } 3340 3341 early_h2c->h2c = h2c; 3342 early_h2c->h2c_len = h2c_len; 3343 3344 mutex_lock(&rtwdev->mutex); 3345 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3346 mutex_unlock(&rtwdev->mutex); 3347 3348 out: 3349 return count; 3350 } 3351 3352 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 3353 { 3354 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3355 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3356 u16 pkt_id; 3357 int ret; 3358 3359 rtw89_leave_ps_mode(rtwdev); 3360 3361 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3362 if (ret) 3363 return ret; 3364 3365 /* intentionally, enqueue two pkt, but has only one pkt id */ 3366 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3367 ctrl_para.start_pktid = pkt_id; 3368 ctrl_para.end_pktid = pkt_id; 3369 ctrl_para.pkt_num = 1; /* start from 0 */ 3370 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3371 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3372 3373 if (mac->set_cpuio(rtwdev, &ctrl_para, true)) 3374 return -EFAULT; 3375 3376 return 0; 3377 } 3378 3379 static int 3380 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v) 3381 { 3382 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3383 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3384 3385 seq_printf(m, "%d\n", 3386 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3387 return 0; 3388 } 3389 3390 enum rtw89_dbg_crash_simulation_type { 3391 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3392 RTW89_DBG_SIM_CTRL_ERROR = 2, 3393 }; 3394 3395 static ssize_t 3396 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf, 3397 size_t count, loff_t *loff) 3398 { 3399 struct seq_file *m = (struct seq_file *)filp->private_data; 3400 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3401 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3402 int (*sim)(struct rtw89_dev *rtwdev); 3403 u8 crash_type; 3404 int ret; 3405 3406 ret = kstrtou8_from_user(user_buf, count, 0, &crash_type); 3407 if (ret) 3408 return -EINVAL; 3409 3410 switch (crash_type) { 3411 case RTW89_DBG_SIM_CPU_EXCEPTION: 3412 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw)) 3413 return -EOPNOTSUPP; 3414 sim = rtw89_fw_h2c_trigger_cpu_exception; 3415 break; 3416 case RTW89_DBG_SIM_CTRL_ERROR: 3417 sim = rtw89_dbg_trigger_ctrl_error; 3418 break; 3419 default: 3420 return -EINVAL; 3421 } 3422 3423 mutex_lock(&rtwdev->mutex); 3424 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3425 ret = sim(rtwdev); 3426 mutex_unlock(&rtwdev->mutex); 3427 3428 if (ret) 3429 return ret; 3430 3431 return count; 3432 } 3433 3434 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 3435 { 3436 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3437 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3438 3439 rtw89_btc_dump_info(rtwdev, m); 3440 3441 return 0; 3442 } 3443 3444 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 3445 const char __user *user_buf, 3446 size_t count, loff_t *loff) 3447 { 3448 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3449 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3450 struct rtw89_btc *btc = &rtwdev->btc; 3451 const struct rtw89_btc_ver *ver = btc->ver; 3452 int ret; 3453 3454 ret = kstrtobool_from_user(user_buf, count, &btc->manual_ctrl); 3455 if (ret) 3456 return ret; 3457 3458 if (ver->fcxctrl == 7) 3459 btc->ctrl.ctrl_v7.manual = btc->manual_ctrl; 3460 else 3461 btc->ctrl.ctrl.manual = btc->manual_ctrl; 3462 3463 return count; 3464 } 3465 3466 static ssize_t rtw89_debug_fw_log_manual_set(struct file *filp, 3467 const char __user *user_buf, 3468 size_t count, loff_t *loff) 3469 { 3470 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3471 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3472 struct rtw89_fw_log *log = &rtwdev->fw.log; 3473 bool fw_log_manual; 3474 3475 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 3476 goto out; 3477 3478 mutex_lock(&rtwdev->mutex); 3479 log->enable = fw_log_manual; 3480 if (log->enable) 3481 rtw89_fw_log_prepare(rtwdev); 3482 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3483 mutex_unlock(&rtwdev->mutex); 3484 out: 3485 return count; 3486 } 3487 3488 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 3489 { 3490 static const char * const he_gi_str[] = { 3491 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3492 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3493 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3494 }; 3495 static const char * const eht_gi_str[] = { 3496 [NL80211_RATE_INFO_EHT_GI_0_8] = "0.8", 3497 [NL80211_RATE_INFO_EHT_GI_1_6] = "1.6", 3498 [NL80211_RATE_INFO_EHT_GI_3_2] = "3.2", 3499 }; 3500 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3501 struct rate_info *rate = &rtwsta->ra_report.txrate; 3502 struct ieee80211_rx_status *status = &rtwsta->rx_status; 3503 struct seq_file *m = (struct seq_file *)data; 3504 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3505 struct rtw89_hal *hal = &rtwdev->hal; 3506 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3507 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3508 u8 evm_min, evm_max; 3509 u8 rssi; 3510 u8 snr; 3511 int i; 3512 3513 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id); 3514 3515 if (rate->flags & RATE_INFO_FLAGS_MCS) 3516 seq_printf(m, "HT MCS-%d%s", rate->mcs, 3517 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3518 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3519 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 3520 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3521 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3522 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 3523 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3524 he_gi_str[rate->he_gi] : "N/A"); 3525 else if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) 3526 seq_printf(m, "EHT %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 3527 rate->eht_gi < ARRAY_SIZE(eht_gi_str) ? 3528 eht_gi_str[rate->eht_gi] : "N/A"); 3529 else 3530 seq_printf(m, "Legacy %d", rate->legacy); 3531 seq_printf(m, "%s", rtwsta->ra_report.might_fallback_legacy ? " FB_G" : ""); 3532 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(rate->bw)); 3533 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate); 3534 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait, 3535 sta->deflink.agg.max_rc_amsdu_len); 3536 3537 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id); 3538 3539 switch (status->encoding) { 3540 case RX_ENC_LEGACY: 3541 seq_printf(m, "Legacy %d", status->rate_idx + 3542 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 3543 break; 3544 case RX_ENC_HT: 3545 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 3546 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3547 break; 3548 case RX_ENC_VHT: 3549 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 3550 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3551 break; 3552 case RX_ENC_HE: 3553 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 3554 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3555 he_gi_str[status->he_gi] : "N/A"); 3556 break; 3557 case RX_ENC_EHT: 3558 seq_printf(m, "EHT %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 3559 status->eht.gi < ARRAY_SIZE(eht_gi_str) ? 3560 eht_gi_str[status->eht.gi] : "N/A"); 3561 break; 3562 } 3563 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(status->bw)); 3564 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate); 3565 3566 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 3567 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d) [", 3568 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi); 3569 for (i = 0; i < ant_num; i++) { 3570 rssi = ewma_rssi_read(&rtwsta->rssi[i]); 3571 seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi), 3572 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 3573 i + 1 == ant_num ? "" : ", "); 3574 } 3575 seq_puts(m, "]\n"); 3576 3577 seq_puts(m, "EVM: ["); 3578 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 3579 evm_min = ewma_evm_read(&rtwsta->evm_min[i]); 3580 evm_max = ewma_evm_read(&rtwsta->evm_max[i]); 3581 3582 seq_printf(m, "%s(%2u.%02u, %2u.%02u)", i == 0 ? "" : " ", 3583 evm_min >> 2, (evm_min & 0x3) * 25, 3584 evm_max >> 2, (evm_max & 0x3) * 25); 3585 } 3586 seq_puts(m, "]\t"); 3587 3588 snr = ewma_snr_read(&rtwsta->avg_snr); 3589 seq_printf(m, "SNR: %u\n", snr); 3590 } 3591 3592 static void 3593 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 3594 enum rtw89_hw_rate first_rate, int len) 3595 { 3596 int i; 3597 3598 for (i = 0; i < len; i++) 3599 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 3600 pkt_stat->rx_rate_cnt[first_rate + i]); 3601 } 3602 3603 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate} 3604 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate} 3605 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate} 3606 3607 static const struct rtw89_rx_rate_cnt_info { 3608 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM]; 3609 int len; 3610 int ext; 3611 const char *rate_mode; 3612 } rtw89_rx_rate_cnt_infos[] = { 3613 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"}, 3614 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"}, 3615 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"}, 3616 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"}, 3617 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"}, 3618 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"}, 3619 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"}, 3620 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"}, 3621 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"}, 3622 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"}, 3623 }; 3624 3625 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 3626 { 3627 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3628 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3629 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3630 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 3631 const struct rtw89_chip_info *chip = rtwdev->chip; 3632 const struct rtw89_rx_rate_cnt_info *info; 3633 enum rtw89_hw_rate first_rate; 3634 int i; 3635 3636 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n", 3637 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv, 3638 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 3639 seq_printf(m, "Beacon: %u, TF: %u\n", pkt_stat->beacon_nr, 3640 stats->rx_tf_periodic); 3641 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 3642 stats->rx_avg_len); 3643 3644 seq_puts(m, "RX count:\n"); 3645 3646 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 3647 info = &rtw89_rx_rate_cnt_infos[i]; 3648 first_rate = info->first_rate[chip->chip_gen]; 3649 if (first_rate >= RTW89_HW_RATE_NR) 3650 continue; 3651 3652 seq_printf(m, "%10s [", info->rate_mode); 3653 rtw89_debug_append_rx_rate(m, pkt_stat, 3654 first_rate, info->len); 3655 if (info->ext) { 3656 seq_puts(m, "]["); 3657 rtw89_debug_append_rx_rate(m, pkt_stat, 3658 first_rate + info->len, info->ext); 3659 } 3660 seq_puts(m, "]\n"); 3661 } 3662 3663 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 3664 3665 return 0; 3666 } 3667 3668 static void rtw89_dump_addr_cam(struct seq_file *m, 3669 struct rtw89_dev *rtwdev, 3670 struct rtw89_addr_cam_entry *addr_cam) 3671 { 3672 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3673 const struct rtw89_sec_cam_entry *sec_entry; 3674 u8 sec_cam_idx; 3675 int i; 3676 3677 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx); 3678 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx); 3679 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map), 3680 addr_cam->sec_cam_map); 3681 for_each_set_bit(i, addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM) { 3682 sec_cam_idx = addr_cam->sec_ent[i]; 3683 sec_entry = cam_info->sec_entries[sec_cam_idx]; 3684 if (!sec_entry) 3685 continue; 3686 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx); 3687 if (sec_entry->ext_key) 3688 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1); 3689 seq_puts(m, "\n"); 3690 } 3691 } 3692 3693 __printf(3, 4) 3694 static void rtw89_dump_pkt_offload(struct seq_file *m, struct list_head *pkt_list, 3695 const char *fmt, ...) 3696 { 3697 struct rtw89_pktofld_info *info; 3698 struct va_format vaf; 3699 va_list args; 3700 3701 if (list_empty(pkt_list)) 3702 return; 3703 3704 va_start(args, fmt); 3705 vaf.va = &args; 3706 vaf.fmt = fmt; 3707 3708 seq_printf(m, "%pV", &vaf); 3709 3710 va_end(args); 3711 3712 list_for_each_entry(info, pkt_list, list) 3713 seq_printf(m, "%d ", info->id); 3714 3715 seq_puts(m, "\n"); 3716 } 3717 3718 static 3719 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 3720 { 3721 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3722 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3723 struct seq_file *m = (struct seq_file *)data; 3724 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; 3725 3726 seq_printf(m, "VIF [%d] %pM\n", rtwvif->mac_id, rtwvif->mac_addr); 3727 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx); 3728 rtw89_dump_addr_cam(m, rtwdev, &rtwvif->addr_cam); 3729 rtw89_dump_pkt_offload(m, &rtwvif->general_pkt_list, "\tpkt_ofld[GENERAL]: "); 3730 } 3731 3732 static void rtw89_dump_ba_cam(struct seq_file *m, struct rtw89_sta *rtwsta) 3733 { 3734 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 3735 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3736 struct rtw89_ba_cam_entry *entry; 3737 bool first = true; 3738 3739 list_for_each_entry(entry, &rtwsta->ba_cam_list, list) { 3740 if (first) { 3741 seq_puts(m, "\tba_cam "); 3742 first = false; 3743 } else { 3744 seq_puts(m, ", "); 3745 } 3746 seq_printf(m, "tid[%u]=%d", entry->tid, 3747 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 3748 } 3749 seq_puts(m, "\n"); 3750 } 3751 3752 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 3753 { 3754 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3755 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3756 struct seq_file *m = (struct seq_file *)data; 3757 3758 seq_printf(m, "STA [%d] %pM %s\n", rtwsta->mac_id, sta->addr, 3759 sta->tdls ? "(TDLS)" : ""); 3760 rtw89_dump_addr_cam(m, rtwdev, &rtwsta->addr_cam); 3761 rtw89_dump_ba_cam(m, rtwsta); 3762 } 3763 3764 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v) 3765 { 3766 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3767 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3768 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3769 u8 idx; 3770 3771 mutex_lock(&rtwdev->mutex); 3772 3773 seq_puts(m, "map:\n"); 3774 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map), 3775 rtwdev->mac_id_map); 3776 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map), 3777 cam_info->addr_cam_map); 3778 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map), 3779 cam_info->bssid_cam_map); 3780 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map), 3781 cam_info->sec_cam_map); 3782 seq_printf(m, "\tba_cam: %*ph\n", (int)sizeof(cam_info->ba_cam_map), 3783 cam_info->ba_cam_map); 3784 seq_printf(m, "\tpkt_ofld: %*ph\n", (int)sizeof(rtwdev->pkt_offload), 3785 rtwdev->pkt_offload); 3786 3787 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 3788 if (!(rtwdev->chip->support_bands & BIT(idx))) 3789 continue; 3790 rtw89_dump_pkt_offload(m, &rtwdev->scan_info.pkt_list[idx], 3791 "\t\t[SCAN %u]: ", idx); 3792 } 3793 3794 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 3795 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m); 3796 3797 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m); 3798 3799 mutex_unlock(&rtwdev->mutex); 3800 3801 return 0; 3802 } 3803 3804 #define DM_INFO(type) {RTW89_DM_ ## type, #type} 3805 3806 static const struct rtw89_disabled_dm_info { 3807 enum rtw89_dm_type type; 3808 const char *name; 3809 } rtw89_disabled_dm_infos[] = { 3810 DM_INFO(DYNAMIC_EDCCA), 3811 }; 3812 3813 static int 3814 rtw89_debug_priv_disable_dm_get(struct seq_file *m, void *v) 3815 { 3816 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3817 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3818 const struct rtw89_disabled_dm_info *info; 3819 struct rtw89_hal *hal = &rtwdev->hal; 3820 u32 disabled; 3821 int i; 3822 3823 seq_printf(m, "Disabled DM: 0x%x\n", hal->disabled_dm_bitmap); 3824 3825 for (i = 0; i < ARRAY_SIZE(rtw89_disabled_dm_infos); i++) { 3826 info = &rtw89_disabled_dm_infos[i]; 3827 disabled = BIT(info->type) & hal->disabled_dm_bitmap; 3828 3829 seq_printf(m, "[%d] %s: %c\n", info->type, info->name, 3830 disabled ? 'X' : 'O'); 3831 } 3832 3833 return 0; 3834 } 3835 3836 static ssize_t 3837 rtw89_debug_priv_disable_dm_set(struct file *filp, const char __user *user_buf, 3838 size_t count, loff_t *loff) 3839 { 3840 struct seq_file *m = (struct seq_file *)filp->private_data; 3841 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3842 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3843 struct rtw89_hal *hal = &rtwdev->hal; 3844 u32 conf; 3845 int ret; 3846 3847 ret = kstrtou32_from_user(user_buf, count, 0, &conf); 3848 if (ret) 3849 return -EINVAL; 3850 3851 hal->disabled_dm_bitmap = conf; 3852 3853 return count; 3854 } 3855 3856 static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = { 3857 .cb_read = rtw89_debug_priv_read_reg_get, 3858 .cb_write = rtw89_debug_priv_read_reg_select, 3859 }; 3860 3861 static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = { 3862 .cb_write = rtw89_debug_priv_write_reg_set, 3863 }; 3864 3865 static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = { 3866 .cb_read = rtw89_debug_priv_read_rf_get, 3867 .cb_write = rtw89_debug_priv_read_rf_select, 3868 }; 3869 3870 static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = { 3871 .cb_write = rtw89_debug_priv_write_rf_set, 3872 }; 3873 3874 static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = { 3875 .cb_read = rtw89_debug_priv_rf_reg_dump_get, 3876 }; 3877 3878 static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = { 3879 .cb_read = rtw89_debug_priv_txpwr_table_get, 3880 }; 3881 3882 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = { 3883 .cb_read = rtw89_debug_priv_mac_reg_dump_get, 3884 .cb_write = rtw89_debug_priv_mac_reg_dump_select, 3885 }; 3886 3887 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = { 3888 .cb_read = rtw89_debug_priv_mac_mem_dump_get, 3889 .cb_write = rtw89_debug_priv_mac_mem_dump_select, 3890 }; 3891 3892 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = { 3893 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get, 3894 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select, 3895 }; 3896 3897 static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = { 3898 .cb_write = rtw89_debug_priv_send_h2c_set, 3899 }; 3900 3901 static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = { 3902 .cb_read = rtw89_debug_priv_early_h2c_get, 3903 .cb_write = rtw89_debug_priv_early_h2c_set, 3904 }; 3905 3906 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_crash = { 3907 .cb_read = rtw89_debug_priv_fw_crash_get, 3908 .cb_write = rtw89_debug_priv_fw_crash_set, 3909 }; 3910 3911 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = { 3912 .cb_read = rtw89_debug_priv_btc_info_get, 3913 }; 3914 3915 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = { 3916 .cb_write = rtw89_debug_priv_btc_manual_set, 3917 }; 3918 3919 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = { 3920 .cb_write = rtw89_debug_fw_log_manual_set, 3921 }; 3922 3923 static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = { 3924 .cb_read = rtw89_debug_priv_phy_info_get, 3925 }; 3926 3927 static struct rtw89_debugfs_priv rtw89_debug_priv_stations = { 3928 .cb_read = rtw89_debug_priv_stations_get, 3929 }; 3930 3931 static struct rtw89_debugfs_priv rtw89_debug_priv_disable_dm = { 3932 .cb_read = rtw89_debug_priv_disable_dm_get, 3933 .cb_write = rtw89_debug_priv_disable_dm_set, 3934 }; 3935 3936 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 3937 do { \ 3938 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \ 3939 if (!debugfs_create_file(#name, mode, \ 3940 parent, &rtw89_debug_priv_ ##name, \ 3941 &file_ops_ ##fopname)) \ 3942 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 3943 } while (0) 3944 3945 #define rtw89_debugfs_add_w(name) \ 3946 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 3947 #define rtw89_debugfs_add_rw(name) \ 3948 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 3949 #define rtw89_debugfs_add_r(name) \ 3950 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 3951 3952 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 3953 { 3954 struct dentry *debugfs_topdir; 3955 3956 debugfs_topdir = debugfs_create_dir("rtw89", 3957 rtwdev->hw->wiphy->debugfsdir); 3958 3959 rtw89_debugfs_add_rw(read_reg); 3960 rtw89_debugfs_add_w(write_reg); 3961 rtw89_debugfs_add_rw(read_rf); 3962 rtw89_debugfs_add_w(write_rf); 3963 rtw89_debugfs_add_r(rf_reg_dump); 3964 rtw89_debugfs_add_r(txpwr_table); 3965 rtw89_debugfs_add_rw(mac_reg_dump); 3966 rtw89_debugfs_add_rw(mac_mem_dump); 3967 rtw89_debugfs_add_rw(mac_dbg_port_dump); 3968 rtw89_debugfs_add_w(send_h2c); 3969 rtw89_debugfs_add_rw(early_h2c); 3970 rtw89_debugfs_add_rw(fw_crash); 3971 rtw89_debugfs_add_r(btc_info); 3972 rtw89_debugfs_add_w(btc_manual); 3973 rtw89_debugfs_add_w(fw_log_manual); 3974 rtw89_debugfs_add_r(phy_info); 3975 rtw89_debugfs_add_r(stations); 3976 rtw89_debugfs_add_rw(disable_dm); 3977 } 3978 #endif 3979 3980 #ifdef CONFIG_RTW89_DEBUGMSG 3981 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, 3982 const char *fmt, ...) 3983 { 3984 struct va_format vaf = { 3985 .fmt = fmt, 3986 }; 3987 3988 va_list args; 3989 3990 va_start(args, fmt); 3991 vaf.va = &args; 3992 3993 if (rtw89_debug_mask & mask) 3994 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 3995 3996 va_end(args); 3997 } 3998 EXPORT_SYMBOL(rtw89_debug); 3999 #endif 4000