1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/vmalloc.h> 6 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "phy.h" 13 #include "ps.h" 14 #include "reg.h" 15 #include "sar.h" 16 #include "util.h" 17 18 #ifdef CONFIG_RTW89_DEBUGMSG 19 unsigned int rtw89_debug_mask; 20 EXPORT_SYMBOL(rtw89_debug_mask); 21 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 22 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 23 #endif 24 25 #ifdef CONFIG_RTW89_DEBUGFS 26 struct rtw89_debugfs_priv_opt { 27 bool rlock:1; 28 bool wlock:1; 29 size_t rsize; 30 }; 31 32 struct rtw89_debugfs_priv { 33 struct rtw89_dev *rtwdev; 34 ssize_t (*cb_read)(struct rtw89_dev *rtwdev, 35 struct rtw89_debugfs_priv *debugfs_priv, 36 char *buf, size_t bufsz); 37 ssize_t (*cb_write)(struct rtw89_dev *rtwdev, 38 struct rtw89_debugfs_priv *debugfs_priv, 39 const char *buf, size_t count); 40 struct rtw89_debugfs_priv_opt opt; 41 union { 42 u32 cb_data; 43 struct { 44 u32 addr; 45 u32 len; 46 } read_reg; 47 struct { 48 u32 addr; 49 u32 mask; 50 u8 path; 51 } read_rf; 52 struct { 53 u8 ss_dbg:1; 54 u8 dle_dbg:1; 55 u8 dmac_dbg:1; 56 u8 cmac_dbg:1; 57 u8 dbg_port:1; 58 } dbgpkg_en; 59 struct { 60 u32 start; 61 u32 len; 62 u8 sel; 63 } mac_mem; 64 }; 65 ssize_t rused; 66 char *rbuf; 67 }; 68 69 struct rtw89_debugfs { 70 struct rtw89_debugfs_priv read_reg; 71 struct rtw89_debugfs_priv write_reg; 72 struct rtw89_debugfs_priv read_rf; 73 struct rtw89_debugfs_priv write_rf; 74 struct rtw89_debugfs_priv rf_reg_dump; 75 struct rtw89_debugfs_priv txpwr_table; 76 struct rtw89_debugfs_priv mac_reg_dump; 77 struct rtw89_debugfs_priv mac_mem_dump; 78 struct rtw89_debugfs_priv mac_dbg_port_dump; 79 struct rtw89_debugfs_priv send_h2c; 80 struct rtw89_debugfs_priv early_h2c; 81 struct rtw89_debugfs_priv fw_crash; 82 struct rtw89_debugfs_priv ser_counters; 83 struct rtw89_debugfs_priv btc_info; 84 struct rtw89_debugfs_priv btc_manual; 85 struct rtw89_debugfs_priv fw_log_manual; 86 struct rtw89_debugfs_priv phy_info; 87 struct rtw89_debugfs_priv stations; 88 struct rtw89_debugfs_priv disable_dm; 89 struct rtw89_debugfs_priv mlo_mode; 90 struct rtw89_debugfs_priv beacon_info; 91 struct rtw89_debugfs_priv diag_mac; 92 }; 93 94 struct rtw89_debugfs_iter_data { 95 char *buf; 96 size_t bufsz; 97 int written_sz; 98 }; 99 100 static void rtw89_debugfs_iter_data_setup(struct rtw89_debugfs_iter_data *iter_data, 101 char *buf, size_t bufsz) 102 { 103 iter_data->buf = buf; 104 iter_data->bufsz = bufsz; 105 iter_data->written_sz = 0; 106 } 107 108 static void rtw89_debugfs_iter_data_next(struct rtw89_debugfs_iter_data *iter_data, 109 char *buf, size_t bufsz, int written_sz) 110 { 111 iter_data->buf = buf; 112 iter_data->bufsz = bufsz; 113 iter_data->written_sz += written_sz; 114 } 115 116 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 117 [RATE_INFO_BW_20] = 20, 118 [RATE_INFO_BW_40] = 40, 119 [RATE_INFO_BW_80] = 80, 120 [RATE_INFO_BW_160] = 160, 121 [RATE_INFO_BW_320] = 320, 122 }; 123 124 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 125 { 126 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 127 return rtw89_rate_info_bw_to_mhz_map[bw]; 128 129 return 0; 130 } 131 132 static ssize_t rtw89_debugfs_file_read_helper(struct wiphy *wiphy, struct file *file, 133 char *buf, size_t bufsz, void *data) 134 { 135 struct rtw89_debugfs_priv *debugfs_priv = data; 136 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 137 ssize_t n; 138 139 n = debugfs_priv->cb_read(rtwdev, debugfs_priv, buf, bufsz); 140 rtw89_might_trailing_ellipsis(buf, bufsz, n); 141 142 return n; 143 } 144 145 static ssize_t rtw89_debugfs_file_read(struct file *file, char __user *userbuf, 146 size_t count, loff_t *ppos) 147 { 148 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 149 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 150 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 151 size_t bufsz = opt->rsize ? opt->rsize : PAGE_SIZE; 152 char *buf; 153 ssize_t n; 154 155 if (!debugfs_priv->rbuf) 156 debugfs_priv->rbuf = devm_kzalloc(rtwdev->dev, bufsz, GFP_KERNEL); 157 158 buf = debugfs_priv->rbuf; 159 if (!buf) 160 return -ENOMEM; 161 162 if (*ppos) { 163 n = debugfs_priv->rused; 164 goto out; 165 } 166 167 if (opt->rlock) { 168 n = wiphy_locked_debugfs_read(rtwdev->hw->wiphy, file, buf, bufsz, 169 userbuf, count, ppos, 170 rtw89_debugfs_file_read_helper, 171 debugfs_priv); 172 debugfs_priv->rused = n; 173 174 return n; 175 } 176 177 n = rtw89_debugfs_file_read_helper(rtwdev->hw->wiphy, file, buf, bufsz, 178 debugfs_priv); 179 debugfs_priv->rused = n; 180 181 out: 182 return simple_read_from_buffer(userbuf, count, ppos, buf, n); 183 } 184 185 static ssize_t rtw89_debugfs_file_write_helper(struct wiphy *wiphy, struct file *file, 186 char *buf, size_t count, void *data) 187 { 188 struct rtw89_debugfs_priv *debugfs_priv = data; 189 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 190 191 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 192 } 193 194 static ssize_t rtw89_debugfs_file_write(struct file *file, 195 const char __user *userbuf, 196 size_t count, loff_t *loff) 197 { 198 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 199 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 200 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 201 char *buf __free(kfree) = kmalloc(count + 1, GFP_KERNEL); 202 ssize_t n; 203 204 if (!buf) 205 return -ENOMEM; 206 207 if (opt->wlock) { 208 n = wiphy_locked_debugfs_write(rtwdev->hw->wiphy, 209 file, buf, count + 1, 210 userbuf, count, 211 rtw89_debugfs_file_write_helper, 212 debugfs_priv); 213 return n; 214 } 215 216 if (copy_from_user(buf, userbuf, count)) 217 return -EFAULT; 218 219 buf[count] = '\0'; 220 221 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 222 } 223 224 static const struct debugfs_short_fops file_ops_single_r = { 225 .read = rtw89_debugfs_file_read, 226 .llseek = generic_file_llseek, 227 }; 228 229 static const struct debugfs_short_fops file_ops_common_rw = { 230 .read = rtw89_debugfs_file_read, 231 .write = rtw89_debugfs_file_write, 232 .llseek = generic_file_llseek, 233 }; 234 235 static const struct debugfs_short_fops file_ops_single_w = { 236 .write = rtw89_debugfs_file_write, 237 .llseek = generic_file_llseek, 238 }; 239 240 static ssize_t 241 rtw89_debug_priv_read_reg_select(struct rtw89_dev *rtwdev, 242 struct rtw89_debugfs_priv *debugfs_priv, 243 const char *buf, size_t count) 244 { 245 u32 addr, len; 246 int num; 247 248 num = sscanf(buf, "%x %x", &addr, &len); 249 if (num != 2) { 250 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 251 return -EINVAL; 252 } 253 254 debugfs_priv->read_reg.addr = addr; 255 debugfs_priv->read_reg.len = len; 256 257 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 258 259 return count; 260 } 261 262 static 263 ssize_t rtw89_debug_priv_read_reg_get(struct rtw89_dev *rtwdev, 264 struct rtw89_debugfs_priv *debugfs_priv, 265 char *buf, size_t bufsz) 266 { 267 char *p = buf, *end = buf + bufsz; 268 u32 addr, addr_end, data, k; 269 u32 len; 270 271 len = debugfs_priv->read_reg.len; 272 addr = debugfs_priv->read_reg.addr; 273 274 if (len > 4) 275 goto ndata; 276 277 switch (len) { 278 case 1: 279 data = rtw89_read8(rtwdev, addr); 280 break; 281 case 2: 282 data = rtw89_read16(rtwdev, addr); 283 break; 284 case 4: 285 data = rtw89_read32(rtwdev, addr); 286 break; 287 default: 288 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 289 return -EINVAL; 290 } 291 292 p += scnprintf(p, end - p, "get %d bytes at 0x%08x=0x%08x\n", len, 293 addr, data); 294 295 return p - buf; 296 297 ndata: 298 addr_end = addr + len; 299 300 for (; addr < addr_end; addr += 16) { 301 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + addr); 302 for (k = 0; k < 16; k += 4) { 303 data = rtw89_read32(rtwdev, addr + k); 304 p += scnprintf(p, end - p, "%08x ", data); 305 } 306 p += scnprintf(p, end - p, "\n"); 307 } 308 309 return p - buf; 310 } 311 312 static 313 ssize_t rtw89_debug_priv_write_reg_set(struct rtw89_dev *rtwdev, 314 struct rtw89_debugfs_priv *debugfs_priv, 315 const char *buf, size_t count) 316 { 317 u32 addr, val, len; 318 int num; 319 320 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 321 if (num != 3) { 322 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 323 return -EINVAL; 324 } 325 326 switch (len) { 327 case 1: 328 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 329 rtw89_write8(rtwdev, addr, (u8)val); 330 break; 331 case 2: 332 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 333 rtw89_write16(rtwdev, addr, (u16)val); 334 break; 335 case 4: 336 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 337 rtw89_write32(rtwdev, addr, (u32)val); 338 break; 339 default: 340 rtw89_info(rtwdev, "invalid read write len %d\n", len); 341 break; 342 } 343 344 return count; 345 } 346 347 static ssize_t 348 rtw89_debug_priv_read_rf_select(struct rtw89_dev *rtwdev, 349 struct rtw89_debugfs_priv *debugfs_priv, 350 const char *buf, size_t count) 351 { 352 u32 addr, mask; 353 u8 path; 354 int num; 355 356 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 357 if (num != 3) { 358 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 359 return -EINVAL; 360 } 361 362 if (path >= rtwdev->chip->rf_path_num) { 363 rtw89_info(rtwdev, "wrong rf path\n"); 364 return -EINVAL; 365 } 366 debugfs_priv->read_rf.addr = addr; 367 debugfs_priv->read_rf.mask = mask; 368 debugfs_priv->read_rf.path = path; 369 370 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 371 372 return count; 373 } 374 375 static 376 ssize_t rtw89_debug_priv_read_rf_get(struct rtw89_dev *rtwdev, 377 struct rtw89_debugfs_priv *debugfs_priv, 378 char *buf, size_t bufsz) 379 { 380 char *p = buf, *end = buf + bufsz; 381 u32 addr, data, mask; 382 u8 path; 383 384 addr = debugfs_priv->read_rf.addr; 385 mask = debugfs_priv->read_rf.mask; 386 path = debugfs_priv->read_rf.path; 387 388 data = rtw89_read_rf(rtwdev, path, addr, mask); 389 390 p += scnprintf(p, end - p, "path %d, rf register 0x%08x=0x%08x\n", 391 path, addr, data); 392 393 return p - buf; 394 } 395 396 static 397 ssize_t rtw89_debug_priv_write_rf_set(struct rtw89_dev *rtwdev, 398 struct rtw89_debugfs_priv *debugfs_priv, 399 const char *buf, size_t count) 400 { 401 u32 addr, val, mask; 402 u8 path; 403 int num; 404 405 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 406 if (num != 4) { 407 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 408 return -EINVAL; 409 } 410 411 if (path >= rtwdev->chip->rf_path_num) { 412 rtw89_info(rtwdev, "wrong rf path\n"); 413 return -EINVAL; 414 } 415 416 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 417 path, addr, val, mask); 418 rtw89_write_rf(rtwdev, path, addr, mask, val); 419 420 return count; 421 } 422 423 static 424 ssize_t rtw89_debug_priv_rf_reg_dump_get(struct rtw89_dev *rtwdev, 425 struct rtw89_debugfs_priv *debugfs_priv, 426 char *buf, size_t bufsz) 427 { 428 const struct rtw89_chip_info *chip = rtwdev->chip; 429 char *p = buf, *end = buf + bufsz; 430 u32 addr, offset, data; 431 u8 path; 432 433 for (path = 0; path < chip->rf_path_num; path++) { 434 p += scnprintf(p, end - p, "RF path %d:\n\n", path); 435 for (addr = 0; addr < 0x100; addr += 4) { 436 p += scnprintf(p, end - p, "0x%08x: ", addr); 437 for (offset = 0; offset < 4; offset++) { 438 data = rtw89_read_rf(rtwdev, path, 439 addr + offset, RFREG_MASK); 440 p += scnprintf(p, end - p, "0x%05x ", data); 441 } 442 p += scnprintf(p, end - p, "\n"); 443 } 444 p += scnprintf(p, end - p, "\n"); 445 } 446 447 return p - buf; 448 } 449 450 struct txpwr_ent { 451 bool nested; 452 union { 453 const char *txt; 454 const struct txpwr_ent *ptr; 455 }; 456 u8 len; 457 }; 458 459 struct txpwr_map { 460 const struct txpwr_ent *ent; 461 u8 size; 462 u32 addr_from; 463 u32 addr_to; 464 u32 addr_to_1ss; 465 }; 466 467 #define __GEN_TXPWR_ENT_NESTED(_e) \ 468 { .nested = true, .ptr = __txpwr_ent_##_e, \ 469 .len = ARRAY_SIZE(__txpwr_ent_##_e) } 470 471 #define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t } 472 473 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 474 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 475 476 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 477 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 478 479 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 480 { .len = 8, .txt = _t "\t- " \ 481 _e0 " " _e1 " " _e2 " " _e3 " " \ 482 _e4 " " _e5 " " _e6 " " _e7 } 483 484 static const struct txpwr_ent __txpwr_ent_byr_ax[] = { 485 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 486 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 487 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 488 /* 1NSS */ 489 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 490 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 491 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 492 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 493 /* 2NSS */ 494 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 495 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 496 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 497 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 498 }; 499 500 static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) == 501 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 502 503 static const struct txpwr_map __txpwr_map_byr_ax = { 504 .ent = __txpwr_ent_byr_ax, 505 .size = ARRAY_SIZE(__txpwr_ent_byr_ax), 506 .addr_from = R_AX_PWR_BY_RATE, 507 .addr_to = R_AX_PWR_BY_RATE_MAX, 508 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX, 509 }; 510 511 static const struct txpwr_ent __txpwr_ent_lmt_ax[] = { 512 /* 1TX */ 513 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 514 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 515 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 516 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 517 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 518 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 519 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 520 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 521 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 522 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 523 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 524 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 525 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 526 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 527 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 528 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 529 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 530 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 531 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 532 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 533 /* 2TX */ 534 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 535 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 536 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 537 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 538 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 539 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 540 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 541 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 542 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 543 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 544 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 545 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 546 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 547 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 548 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 549 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 550 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 551 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 552 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 553 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 554 }; 555 556 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) == 557 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 558 559 static const struct txpwr_map __txpwr_map_lmt_ax = { 560 .ent = __txpwr_ent_lmt_ax, 561 .size = ARRAY_SIZE(__txpwr_ent_lmt_ax), 562 .addr_from = R_AX_PWR_LMT, 563 .addr_to = R_AX_PWR_LMT_MAX, 564 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX, 565 }; 566 567 static const struct txpwr_ent __txpwr_ent_lmt_ru_ax[] = { 568 /* 1TX */ 569 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 570 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 571 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 572 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 573 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 574 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 575 /* 2TX */ 576 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 577 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 578 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 579 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 580 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 581 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 582 }; 583 584 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) == 585 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 586 587 static const struct txpwr_map __txpwr_map_lmt_ru_ax = { 588 .ent = __txpwr_ent_lmt_ru_ax, 589 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_ax), 590 .addr_from = R_AX_PWR_RU_LMT, 591 .addr_to = R_AX_PWR_RU_LMT_MAX, 592 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX, 593 }; 594 595 static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = { 596 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 597 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 598 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 599 __GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"), 600 __GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 601 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 602 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 603 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 604 __GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"), 605 __GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 606 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 607 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 608 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 609 __GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"), 610 __GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 611 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 612 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 613 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 614 __GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"), 615 __GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 616 }; 617 618 static const struct txpwr_ent __txpwr_ent_byr_be[] = { 619 __GEN_TXPWR_ENT0("BW20"), 620 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 621 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 622 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 623 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 624 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 625 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 626 627 __GEN_TXPWR_ENT0("BW40"), 628 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 629 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 630 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 631 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 632 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 633 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 634 635 /* there is no CCK section after BW80 */ 636 __GEN_TXPWR_ENT0("BW80"), 637 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 638 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 639 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 640 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 641 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 642 643 __GEN_TXPWR_ENT0("BW160"), 644 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 645 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 646 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 647 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 648 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 649 650 __GEN_TXPWR_ENT0("BW320"), 651 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 652 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 653 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 654 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 655 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 656 }; 657 658 static const struct txpwr_map __txpwr_map_byr_be = { 659 .ent = __txpwr_ent_byr_be, 660 .size = ARRAY_SIZE(__txpwr_ent_byr_be), 661 .addr_from = R_BE_PWR_BY_RATE, 662 .addr_to = R_BE_PWR_BY_RATE_MAX, 663 .addr_to_1ss = 0, /* not support */ 664 }; 665 666 static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = { 667 __GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"), 668 __GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"), 669 __GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"), 670 __GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"), 671 __GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"), 672 __GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"), 673 __GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"), 674 __GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"), 675 __GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"), 676 __GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"), 677 __GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"), 678 __GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"), 679 __GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"), 680 __GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"), 681 __GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"), 682 __GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"), 683 __GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"), 684 __GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"), 685 __GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"), 686 __GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"), 687 __GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"), 688 __GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"), 689 __GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"), 690 __GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"), 691 __GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"), 692 __GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"), 693 __GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"), 694 __GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"), 695 __GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"), 696 __GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"), 697 __GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"), 698 __GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"), 699 __GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"), 700 __GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"), 701 __GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"), 702 }; 703 704 static const struct txpwr_ent __txpwr_ent_lmt_be[] = { 705 __GEN_TXPWR_ENT0("1TX"), 706 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 707 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 708 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 709 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 710 711 __GEN_TXPWR_ENT0("2TX"), 712 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 713 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 714 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 715 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 716 }; 717 718 static const struct txpwr_map __txpwr_map_lmt_be = { 719 .ent = __txpwr_ent_lmt_be, 720 .size = ARRAY_SIZE(__txpwr_ent_lmt_be), 721 .addr_from = R_BE_PWR_LMT, 722 .addr_to = R_BE_PWR_LMT_MAX, 723 .addr_to_1ss = 0, /* not support */ 724 }; 725 726 static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = { 727 __GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 728 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 729 __GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 730 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 731 __GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 732 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 733 __GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 734 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 735 __GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 736 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 737 __GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 738 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 739 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 740 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 741 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 742 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 743 __GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 744 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 745 __GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 746 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 747 }; 748 749 static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = { 750 __GEN_TXPWR_ENT0("1TX"), 751 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 752 753 __GEN_TXPWR_ENT0("2TX"), 754 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 755 }; 756 757 static const struct txpwr_map __txpwr_map_lmt_ru_be = { 758 .ent = __txpwr_ent_lmt_ru_be, 759 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be), 760 .addr_from = R_BE_PWR_RU_LMT, 761 .addr_to = R_BE_PWR_RU_LMT_MAX, 762 .addr_to_1ss = 0, /* not support */ 763 }; 764 765 static unsigned int 766 __print_txpwr_ent(char *buf, size_t bufsz, const struct txpwr_ent *ent, 767 const s8 *bufp, const unsigned int cur, unsigned int *ate) 768 { 769 char *p = buf, *end = buf + bufsz; 770 unsigned int cnt, i; 771 unsigned int eaten; 772 char *fmt; 773 774 if (ent->nested) { 775 for (cnt = 0, i = 0; i < ent->len; i++, cnt += eaten) 776 p += __print_txpwr_ent(p, end - p, ent->ptr + i, bufp, 777 cur + cnt, &eaten); 778 *ate = cnt; 779 goto out; 780 } 781 782 switch (ent->len) { 783 case 0: 784 p += scnprintf(p, end - p, "\t<< %s >>\n", ent->txt); 785 *ate = 0; 786 goto out; 787 case 2: 788 fmt = "%s\t| %3d, %3d,\t\tdBm\n"; 789 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 790 bufp[cur + 1]); 791 *ate = 2; 792 goto out; 793 case 4: 794 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 795 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 796 bufp[cur + 1], 797 bufp[cur + 2], bufp[cur + 3]); 798 *ate = 4; 799 goto out; 800 case 8: 801 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 802 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 803 bufp[cur + 1], 804 bufp[cur + 2], bufp[cur + 3], bufp[cur + 4], 805 bufp[cur + 5], bufp[cur + 6], bufp[cur + 7]); 806 *ate = 8; 807 goto out; 808 default: 809 return 0; 810 } 811 812 out: 813 return p - buf; 814 } 815 816 static ssize_t __print_txpwr_map(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 817 const struct txpwr_map *map) 818 { 819 u8 fct = rtwdev->chip->txpwr_factor_mac; 820 u8 path_num = rtwdev->chip->rf_path_num; 821 char *p = buf, *end = buf + bufsz; 822 unsigned int cur, i; 823 unsigned int eaten; 824 u32 max_valid_addr; 825 u32 val, addr; 826 s8 *bufp, tmp; 827 int ret; 828 829 if (path_num == 1) 830 max_valid_addr = map->addr_to_1ss; 831 else 832 max_valid_addr = map->addr_to; 833 834 if (max_valid_addr == 0) 835 return -EOPNOTSUPP; 836 837 bufp = vzalloc(map->addr_to - map->addr_from + 4); 838 if (!bufp) 839 return -ENOMEM; 840 841 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 842 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 843 if (ret) 844 val = MASKDWORD; 845 846 cur = addr - map->addr_from; 847 for (i = 0; i < 4; i++, val >>= 8) { 848 /* signed 7 bits, and reserved BIT(7) */ 849 tmp = sign_extend32(val, 6); 850 bufp[cur + i] = tmp >> fct; 851 } 852 } 853 854 for (cur = 0, i = 0; i < map->size; i++, cur += eaten) 855 p += __print_txpwr_ent(p, end - p, &map->ent[i], bufp, cur, &eaten); 856 857 vfree(bufp); 858 return p - buf; 859 } 860 861 static int __print_regd(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 862 const struct rtw89_chan *chan) 863 { 864 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 865 char *p = buf, *end = buf + bufsz; 866 u8 band = chan->band_type; 867 u8 regd = rtw89_regd_get(rtwdev, band); 868 869 p += scnprintf(p, end - p, "%s\n", rtw89_regd_get_string(regd)); 870 p += scnprintf(p, end - p, "\t(txpwr UK follow ETSI: %s)\n", 871 str_yes_no(regulatory->txpwr_uk_follow_etsi)); 872 873 return p - buf; 874 } 875 876 struct dbgfs_txpwr_table { 877 const struct txpwr_map *byr; 878 const struct txpwr_map *lmt; 879 const struct txpwr_map *lmt_ru; 880 }; 881 882 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = { 883 .byr = &__txpwr_map_byr_ax, 884 .lmt = &__txpwr_map_lmt_ax, 885 .lmt_ru = &__txpwr_map_lmt_ru_ax, 886 }; 887 888 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = { 889 .byr = &__txpwr_map_byr_be, 890 .lmt = &__txpwr_map_lmt_be, 891 .lmt_ru = &__txpwr_map_lmt_ru_be, 892 }; 893 894 static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = { 895 [RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax, 896 [RTW89_CHIP_BE] = &dbgfs_txpwr_table_be, 897 }; 898 899 static 900 int rtw89_debug_priv_txpwr_table_get_regd(struct rtw89_dev *rtwdev, 901 char *buf, size_t bufsz, 902 const struct rtw89_chan *chan) 903 { 904 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 905 const struct rtw89_reg_6ghz_tpe *tpe6 = ®ulatory->reg_6ghz_tpe; 906 char *p = buf, *end = buf + bufsz; 907 908 p += scnprintf(p, end - p, "[Chanctx] band %u, ch %u, bw %u\n", 909 chan->band_type, chan->channel, chan->band_width); 910 911 p += scnprintf(p, end - p, "[Regulatory] "); 912 p += __print_regd(rtwdev, p, end - p, chan); 913 914 if (chan->band_type == RTW89_BAND_6G) { 915 p += scnprintf(p, end - p, "[reg6_pwr_type] %u\n", 916 regulatory->reg_6ghz_power); 917 918 if (tpe6->valid) 919 p += scnprintf(p, end - p, "[TPE] %d dBm\n", 920 tpe6->constraint); 921 } 922 923 return p - buf; 924 } 925 926 static 927 ssize_t rtw89_debug_priv_txpwr_table_get(struct rtw89_dev *rtwdev, 928 struct rtw89_debugfs_priv *debugfs_priv, 929 char *buf, size_t bufsz) 930 { 931 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 932 struct rtw89_sar_parm sar_parm = {}; 933 const struct dbgfs_txpwr_table *tbl; 934 const struct rtw89_chan *chan; 935 char *p = buf, *end = buf + bufsz; 936 ssize_t n; 937 938 lockdep_assert_wiphy(rtwdev->hw->wiphy); 939 940 rtw89_leave_ps_mode(rtwdev); 941 chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 942 sar_parm.center_freq = chan->freq; 943 944 p += rtw89_debug_priv_txpwr_table_get_regd(rtwdev, p, end - p, chan); 945 946 p += scnprintf(p, end - p, "[SAR]\n"); 947 p += rtw89_print_sar(rtwdev, p, end - p, &sar_parm); 948 949 p += scnprintf(p, end - p, "[TAS]\n"); 950 p += rtw89_print_tas(rtwdev, p, end - p); 951 952 p += scnprintf(p, end - p, "[DAG]\n"); 953 p += rtw89_print_ant_gain(rtwdev, p, end - p, chan); 954 955 tbl = dbgfs_txpwr_tables[chip_gen]; 956 if (!tbl) 957 return -EOPNOTSUPP; 958 959 p += scnprintf(p, end - p, "\n[TX power byrate]\n"); 960 n = __print_txpwr_map(rtwdev, p, end - p, tbl->byr); 961 if (n < 0) 962 return n; 963 p += n; 964 965 p += scnprintf(p, end - p, "\n[TX power limit]\n"); 966 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt); 967 if (n < 0) 968 return n; 969 p += n; 970 971 p += scnprintf(p, end - p, "\n[TX power limit_ru]\n"); 972 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru); 973 if (n < 0) 974 return n; 975 p += n; 976 977 return p - buf; 978 } 979 980 static ssize_t 981 rtw89_debug_priv_mac_reg_dump_select(struct rtw89_dev *rtwdev, 982 struct rtw89_debugfs_priv *debugfs_priv, 983 const char *buf, size_t count) 984 { 985 const struct rtw89_chip_info *chip = rtwdev->chip; 986 int sel; 987 int ret; 988 989 ret = kstrtoint(buf, 0, &sel); 990 if (ret) 991 return ret; 992 993 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 994 rtw89_info(rtwdev, "invalid args: %d\n", sel); 995 return -EINVAL; 996 } 997 998 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 999 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 1000 chip->chip_id); 1001 return -EINVAL; 1002 } 1003 1004 debugfs_priv->cb_data = sel; 1005 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 1006 1007 return count; 1008 } 1009 1010 #define RTW89_MAC_PAGE_SIZE 0x100 1011 1012 static 1013 ssize_t rtw89_debug_priv_mac_reg_dump_get(struct rtw89_dev *rtwdev, 1014 struct rtw89_debugfs_priv *debugfs_priv, 1015 char *buf, size_t bufsz) 1016 { 1017 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 1018 char *p = buf, *end = buf + bufsz; 1019 u32 start, end_addr; 1020 u32 i, j, k, page; 1021 u32 val; 1022 1023 switch (reg_sel) { 1024 case RTW89_DBG_SEL_MAC_00: 1025 p += scnprintf(p, end - p, "Debug selected MAC page 0x00\n"); 1026 start = 0x000; 1027 end_addr = 0x014; 1028 break; 1029 case RTW89_DBG_SEL_MAC_30: 1030 p += scnprintf(p, end - p, "Debug selected MAC page 0x30\n"); 1031 start = 0x030; 1032 end_addr = 0x033; 1033 break; 1034 case RTW89_DBG_SEL_MAC_40: 1035 p += scnprintf(p, end - p, "Debug selected MAC page 0x40\n"); 1036 start = 0x040; 1037 end_addr = 0x07f; 1038 break; 1039 case RTW89_DBG_SEL_MAC_80: 1040 p += scnprintf(p, end - p, "Debug selected MAC page 0x80\n"); 1041 start = 0x080; 1042 end_addr = 0x09f; 1043 break; 1044 case RTW89_DBG_SEL_MAC_C0: 1045 p += scnprintf(p, end - p, "Debug selected MAC page 0xc0\n"); 1046 start = 0x0c0; 1047 end_addr = 0x0df; 1048 break; 1049 case RTW89_DBG_SEL_MAC_E0: 1050 p += scnprintf(p, end - p, "Debug selected MAC page 0xe0\n"); 1051 start = 0x0e0; 1052 end_addr = 0x0ff; 1053 break; 1054 case RTW89_DBG_SEL_BB: 1055 p += scnprintf(p, end - p, "Debug selected BB register\n"); 1056 start = 0x100; 1057 end_addr = 0x17f; 1058 break; 1059 case RTW89_DBG_SEL_IQK: 1060 p += scnprintf(p, end - p, "Debug selected IQK register\n"); 1061 start = 0x180; 1062 end_addr = 0x1bf; 1063 break; 1064 case RTW89_DBG_SEL_RFC: 1065 p += scnprintf(p, end - p, "Debug selected RFC register\n"); 1066 start = 0x1c0; 1067 end_addr = 0x1ff; 1068 break; 1069 default: 1070 p += scnprintf(p, end - p, "Selected invalid register page\n"); 1071 return -EINVAL; 1072 } 1073 1074 for (i = start; i <= end_addr; i++) { 1075 page = i << 8; 1076 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 1077 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + j); 1078 for (k = 0; k < 4; k++) { 1079 val = rtw89_read32(rtwdev, j + (k << 2)); 1080 p += scnprintf(p, end - p, "%08x ", val); 1081 } 1082 p += scnprintf(p, end - p, "\n"); 1083 } 1084 } 1085 1086 return p - buf; 1087 } 1088 1089 static ssize_t 1090 rtw89_debug_priv_mac_mem_dump_select(struct rtw89_dev *rtwdev, 1091 struct rtw89_debugfs_priv *debugfs_priv, 1092 const char *buf, size_t count) 1093 { 1094 u32 sel, start_addr, len; 1095 int num; 1096 1097 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 1098 if (num != 3) { 1099 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 1100 return -EINVAL; 1101 } 1102 1103 debugfs_priv->mac_mem.sel = sel; 1104 debugfs_priv->mac_mem.start = start_addr; 1105 debugfs_priv->mac_mem.len = len; 1106 1107 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 1108 sel, start_addr, len); 1109 1110 return count; 1111 } 1112 1113 static int rtw89_debug_dump_mac_mem(struct rtw89_dev *rtwdev, 1114 char *buf, size_t bufsz, 1115 u8 sel, u32 start_addr, u32 len) 1116 { 1117 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1118 u32 filter_model_addr = mac->filter_model_addr; 1119 u32 indir_access_addr = mac->indir_access_addr; 1120 u32 mem_page_size = mac->mem_page_size; 1121 u32 base_addr, start_page, residue; 1122 char *p = buf, *end = buf + bufsz; 1123 u32 i, j, pp, pages; 1124 u32 dump_len, remain; 1125 u32 val; 1126 1127 remain = len; 1128 pages = len / mem_page_size + 1; 1129 start_page = start_addr / mem_page_size; 1130 residue = start_addr % mem_page_size; 1131 base_addr = mac->mem_base_addrs[sel]; 1132 base_addr += start_page * mem_page_size; 1133 1134 for (pp = 0; pp < pages; pp++) { 1135 dump_len = min_t(u32, remain, mem_page_size); 1136 rtw89_write32(rtwdev, filter_model_addr, base_addr); 1137 for (i = indir_access_addr + residue; 1138 i < indir_access_addr + dump_len;) { 1139 p += scnprintf(p, end - p, "%08xh:", i); 1140 for (j = 0; 1141 j < 4 && i < indir_access_addr + dump_len; 1142 j++, i += 4) { 1143 val = rtw89_read32(rtwdev, i); 1144 p += scnprintf(p, end - p, " %08x", val); 1145 remain -= 4; 1146 } 1147 p += scnprintf(p, end - p, "\n"); 1148 } 1149 base_addr += mem_page_size; 1150 } 1151 1152 return p - buf; 1153 } 1154 1155 static ssize_t 1156 rtw89_debug_priv_mac_mem_dump_get(struct rtw89_dev *rtwdev, 1157 struct rtw89_debugfs_priv *debugfs_priv, 1158 char *buf, size_t bufsz) 1159 { 1160 char *p = buf, *end = buf + bufsz; 1161 bool grant_read = false; 1162 1163 lockdep_assert_wiphy(rtwdev->hw->wiphy); 1164 1165 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 1166 return -ENOENT; 1167 1168 if (rtwdev->chip->chip_id == RTL8852C) { 1169 switch (debugfs_priv->mac_mem.sel) { 1170 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 1171 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 1172 case RTW89_MAC_MEM_TXDATA_FIFO_0: 1173 case RTW89_MAC_MEM_TXDATA_FIFO_1: 1174 grant_read = true; 1175 break; 1176 default: 1177 break; 1178 } 1179 } 1180 1181 rtw89_leave_ps_mode(rtwdev); 1182 if (grant_read) 1183 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1184 p += rtw89_debug_dump_mac_mem(rtwdev, p, end - p, 1185 debugfs_priv->mac_mem.sel, 1186 debugfs_priv->mac_mem.start, 1187 debugfs_priv->mac_mem.len); 1188 if (grant_read) 1189 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1190 1191 return p - buf; 1192 } 1193 1194 static ssize_t 1195 rtw89_debug_priv_mac_dbg_port_dump_select(struct rtw89_dev *rtwdev, 1196 struct rtw89_debugfs_priv *debugfs_priv, 1197 const char *buf, size_t count) 1198 { 1199 int sel, set; 1200 int num; 1201 bool enable; 1202 1203 num = sscanf(buf, "%d %d", &sel, &set); 1204 if (num != 2) { 1205 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 1206 return -EINVAL; 1207 } 1208 1209 enable = set != 0; 1210 switch (sel) { 1211 case 0: 1212 debugfs_priv->dbgpkg_en.ss_dbg = enable; 1213 break; 1214 case 1: 1215 debugfs_priv->dbgpkg_en.dle_dbg = enable; 1216 break; 1217 case 2: 1218 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 1219 break; 1220 case 3: 1221 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 1222 break; 1223 case 4: 1224 debugfs_priv->dbgpkg_en.dbg_port = enable; 1225 break; 1226 default: 1227 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 1228 return -EINVAL; 1229 } 1230 1231 rtw89_info(rtwdev, "%s debug port dump %d\n", 1232 enable ? "Enable" : "Disable", sel); 1233 1234 return count; 1235 } 1236 1237 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 1238 char *buf, size_t bufsz) 1239 { 1240 return 0; 1241 } 1242 1243 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 1244 char *buf, size_t bufsz) 1245 { 1246 #define DLE_DFI_DUMP(__type, __target, __sel) \ 1247 ({ \ 1248 u32 __ctrl; \ 1249 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 1250 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 1251 u32 __data, __val32; \ 1252 int __ret; \ 1253 \ 1254 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 1255 DLE_DFI_TYPE_##__target) | \ 1256 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 1257 B_AX_WDE_DFI_ACTIVE; \ 1258 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 1259 __ret = read_poll_timeout(rtw89_read32, __val32, \ 1260 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 1261 1000, 50000, false, \ 1262 rtwdev, __reg_ctrl); \ 1263 if (__ret) { \ 1264 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 1265 #__type, #__target, __sel); \ 1266 return __ret; \ 1267 } \ 1268 \ 1269 __data = rtw89_read32(rtwdev, __reg_data); \ 1270 __data; \ 1271 }) 1272 1273 #define DLE_DFI_FREE_PAGE_DUMP(__p, __end, __type) \ 1274 ({ \ 1275 u32 __freepg, __pubpg; \ 1276 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 1277 \ 1278 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 1279 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 1280 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 1281 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 1282 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 1283 __p += scnprintf(__p, __end - __p, "[%s] freepg head: %d\n", \ 1284 #__type, __freepg_head); \ 1285 __p += scnprintf(__p, __end - __p, "[%s] freepg tail: %d\n", \ 1286 #__type, __freepg_tail); \ 1287 __p += scnprintf(__p, __end - __p, "[%s] pubpg num : %d\n", \ 1288 #__type, __pubpg_num); \ 1289 }) 1290 1291 #define case_QUOTA(__p, __end, __type, __id) \ 1292 case __type##_QTAID_##__id: \ 1293 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 1294 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 1295 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 1296 __p += scnprintf(__p, __end - __p, "[%s][%s] rsv_pgnum: %d\n", \ 1297 #__type, #__id, rsv_pgnum); \ 1298 __p += scnprintf(__p, __end - __p, "[%s][%s] use_pgnum: %d\n", \ 1299 #__type, #__id, use_pgnum); \ 1300 break 1301 char *p = buf, *end = buf + bufsz; 1302 u32 quota_id; 1303 u32 val32; 1304 u16 rsv_pgnum, use_pgnum; 1305 int ret; 1306 1307 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1308 if (ret) { 1309 p += scnprintf(p, end - p, "[DLE] : DMAC not enabled\n"); 1310 goto out; 1311 } 1312 1313 DLE_DFI_FREE_PAGE_DUMP(p, end, WDE); 1314 DLE_DFI_FREE_PAGE_DUMP(p, end, PLE); 1315 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 1316 switch (quota_id) { 1317 case_QUOTA(p, end, WDE, HOST_IF); 1318 case_QUOTA(p, end, WDE, WLAN_CPU); 1319 case_QUOTA(p, end, WDE, DATA_CPU); 1320 case_QUOTA(p, end, WDE, PKTIN); 1321 case_QUOTA(p, end, WDE, CPUIO); 1322 } 1323 } 1324 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 1325 switch (quota_id) { 1326 case_QUOTA(p, end, PLE, B0_TXPL); 1327 case_QUOTA(p, end, PLE, B1_TXPL); 1328 case_QUOTA(p, end, PLE, C2H); 1329 case_QUOTA(p, end, PLE, H2C); 1330 case_QUOTA(p, end, PLE, WLAN_CPU); 1331 case_QUOTA(p, end, PLE, MPDU); 1332 case_QUOTA(p, end, PLE, CMAC0_RX); 1333 case_QUOTA(p, end, PLE, CMAC1_RX); 1334 case_QUOTA(p, end, PLE, CMAC1_BBRPT); 1335 case_QUOTA(p, end, PLE, WDRLS); 1336 case_QUOTA(p, end, PLE, CPUIO); 1337 } 1338 } 1339 1340 out: 1341 return p - buf; 1342 1343 #undef case_QUOTA 1344 #undef DLE_DFI_DUMP 1345 #undef DLE_DFI_FREE_PAGE_DUMP 1346 } 1347 1348 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 1349 char *buf, size_t bufsz) 1350 { 1351 const struct rtw89_chip_info *chip = rtwdev->chip; 1352 char *p = buf, *end = buf + bufsz; 1353 u32 dmac_err; 1354 int i, ret; 1355 1356 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1357 if (ret) { 1358 p += scnprintf(p, end - p, "[DMAC] : DMAC not enabled\n"); 1359 goto out; 1360 } 1361 1362 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1363 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1364 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1365 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1366 1367 if (dmac_err) { 1368 p += scnprintf(p, end - p, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1369 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1370 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1371 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1372 if (chip->chip_id == RTL8852C) { 1373 p += scnprintf(p, end - p, 1374 "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1375 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1376 p += scnprintf(p, end - p, 1377 "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1378 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1379 p += scnprintf(p, end - p, 1380 "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1381 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1382 p += scnprintf(p, end - p, 1383 "R_AX_PLE_DBGERR_STS=0x%08x\n", 1384 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1385 } 1386 } 1387 1388 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1389 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1390 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1391 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1392 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1393 if (chip->chip_id == RTL8852C) 1394 p += scnprintf(p, end - p, 1395 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1396 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1397 else 1398 p += scnprintf(p, end - p, 1399 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1400 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1401 } 1402 1403 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1404 if (chip->chip_id == RTL8852C) { 1405 p += scnprintf(p, end - p, 1406 "R_AX_SEC_ERR_IMR=0x%08x\n", 1407 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1408 p += scnprintf(p, end - p, 1409 "R_AX_SEC_ERR_ISR=0x%08x\n", 1410 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1411 p += scnprintf(p, end - p, 1412 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1413 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1414 p += scnprintf(p, end - p, 1415 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1416 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1417 p += scnprintf(p, end - p, 1418 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1419 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1420 p += scnprintf(p, end - p, 1421 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1422 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1423 p += scnprintf(p, end - p, "R_AX_SEC_DEBUG1=0x%08x\n", 1424 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1425 p += scnprintf(p, end - p, 1426 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1427 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1428 p += scnprintf(p, end - p, 1429 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1430 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1431 1432 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1433 B_AX_DBG_SEL0, 0x8B); 1434 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1435 B_AX_DBG_SEL1, 0x8B); 1436 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1437 B_AX_SEL_0XC0_MASK, 1); 1438 for (i = 0; i < 0x10; i++) { 1439 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1440 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1441 p += scnprintf(p, end - p, 1442 "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1443 i, 1444 rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1445 } 1446 } else { 1447 p += scnprintf(p, end - p, 1448 "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1449 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1450 p += scnprintf(p, end - p, 1451 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1452 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1453 p += scnprintf(p, end - p, 1454 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1455 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1456 p += scnprintf(p, end - p, 1457 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1458 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1459 p += scnprintf(p, end - p, 1460 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1461 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1462 p += scnprintf(p, end - p, 1463 "R_AX_SEC_CAM_WDATA=0x%08x\n", 1464 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1465 p += scnprintf(p, end - p, 1466 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1467 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1468 p += scnprintf(p, end - p, 1469 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1470 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1471 p += scnprintf(p, end - p, 1472 "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1473 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1474 p += scnprintf(p, end - p, 1475 "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1476 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1477 } 1478 } 1479 1480 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1481 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1482 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1483 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1484 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1485 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1486 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1487 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1488 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1489 } 1490 1491 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1492 p += scnprintf(p, end - p, 1493 "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1494 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1495 p += scnprintf(p, end - p, 1496 "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1497 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1498 } 1499 1500 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1501 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1502 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1503 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1504 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1505 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1506 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1507 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1508 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1509 } 1510 1511 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1512 if (chip->chip_id == RTL8852C) { 1513 p += scnprintf(p, end - p, 1514 "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1515 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1516 p += scnprintf(p, end - p, 1517 "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1518 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1519 p += scnprintf(p, end - p, 1520 "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1521 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1522 p += scnprintf(p, end - p, 1523 "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1524 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1525 } else { 1526 p += scnprintf(p, end - p, 1527 "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1528 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1529 p += scnprintf(p, end - p, 1530 "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1531 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1532 } 1533 } 1534 1535 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1536 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1537 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1538 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1539 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1540 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1541 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1542 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1543 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1544 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1545 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1546 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1547 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1548 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1549 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1550 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1551 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1552 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1553 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1554 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1555 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1556 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1557 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1558 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1559 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1560 if (chip->chip_id == RTL8852C) { 1561 p += scnprintf(p, end - p, "R_AX_RX_CTRL0=0x%08x\n", 1562 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1563 p += scnprintf(p, end - p, "R_AX_RX_CTRL1=0x%08x\n", 1564 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1565 p += scnprintf(p, end - p, "R_AX_RX_CTRL2=0x%08x\n", 1566 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1567 } else { 1568 p += scnprintf(p, end - p, 1569 "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1570 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1571 p += scnprintf(p, end - p, 1572 "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1573 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1574 p += scnprintf(p, end - p, 1575 "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1576 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1577 } 1578 } 1579 1580 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1581 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1582 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1583 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1584 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1585 } 1586 1587 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1588 p += scnprintf(p, end - p, 1589 "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1590 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1591 p += scnprintf(p, end - p, 1592 "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1593 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1594 p += scnprintf(p, end - p, 1595 "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1596 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1597 p += scnprintf(p, end - p, 1598 "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1599 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1600 p += scnprintf(p, end - p, 1601 "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1602 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1603 p += scnprintf(p, end - p, 1604 "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1605 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1606 } 1607 1608 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1609 if (chip->chip_id == RTL8852C) { 1610 p += scnprintf(p, end - p, 1611 "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1612 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1613 p += scnprintf(p, end - p, 1614 "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1615 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1616 p += scnprintf(p, end - p, 1617 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1618 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1619 p += scnprintf(p, end - p, 1620 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1621 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1622 p += scnprintf(p, end - p, 1623 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1624 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1625 p += scnprintf(p, end - p, 1626 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1627 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1628 } else { 1629 p += scnprintf(p, end - p, 1630 "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1631 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1632 p += scnprintf(p, end - p, 1633 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1634 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1635 p += scnprintf(p, end - p, 1636 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1637 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1638 p += scnprintf(p, end - p, 1639 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1640 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1641 p += scnprintf(p, end - p, 1642 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1643 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1644 } 1645 } 1646 1647 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1648 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1649 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1650 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1651 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1652 } 1653 1654 out: 1655 return p - buf; 1656 } 1657 1658 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1659 char *buf, size_t bufsz, 1660 enum rtw89_mac_idx band) 1661 { 1662 const struct rtw89_chip_info *chip = rtwdev->chip; 1663 char *p = buf, *end = buf + bufsz; 1664 u32 offset = 0; 1665 u32 cmac_err; 1666 int ret; 1667 1668 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1669 if (ret) { 1670 if (band) 1671 p += scnprintf(p, end - p, 1672 "[CMAC] : CMAC1 not enabled\n"); 1673 else 1674 p += scnprintf(p, end - p, 1675 "[CMAC] : CMAC0 not enabled\n"); 1676 goto out; 1677 } 1678 1679 if (band) 1680 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1681 1682 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1683 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1684 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1685 p += scnprintf(p, end - p, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1686 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1687 p += scnprintf(p, end - p, "R_AX_CK_EN [%d]=0x%08x\n", band, 1688 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1689 1690 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1691 p += scnprintf(p, end - p, 1692 "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1693 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1694 p += scnprintf(p, end - p, 1695 "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1696 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1697 } 1698 1699 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1700 p += scnprintf(p, end - p, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", 1701 band, 1702 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1703 p += scnprintf(p, end - p, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", 1704 band, 1705 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1706 } 1707 1708 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1709 if (chip->chip_id == RTL8852C) { 1710 p += scnprintf(p, end - p, 1711 "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1712 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1713 p += scnprintf(p, end - p, 1714 "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", 1715 band, 1716 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1717 } else { 1718 p += scnprintf(p, end - p, 1719 "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1720 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1721 } 1722 } 1723 1724 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1725 if (chip->chip_id == RTL8852C) { 1726 p += scnprintf(p, end - p, 1727 "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", 1728 band, 1729 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1730 p += scnprintf(p, end - p, 1731 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1732 band, 1733 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1734 } else { 1735 p += scnprintf(p, end - p, 1736 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1737 band, 1738 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1739 } 1740 } 1741 1742 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1743 p += scnprintf(p, end - p, "R_AX_TXPWR_IMR [%d]=0x%08x\n", 1744 band, 1745 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1746 p += scnprintf(p, end - p, "R_AX_TXPWR_ISR [%d]=0x%08x\n", 1747 band, 1748 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1749 } 1750 1751 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1752 if (chip->chip_id == RTL8852C) { 1753 p += scnprintf(p, end - p, 1754 "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", 1755 band, 1756 rtw89_read32(rtwdev, 1757 R_AX_TRXPTCL_ERROR_INDICA + offset)); 1758 p += scnprintf(p, end - p, 1759 "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", 1760 band, 1761 rtw89_read32(rtwdev, 1762 R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1763 } else { 1764 p += scnprintf(p, end - p, 1765 "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", 1766 band, 1767 rtw89_read32(rtwdev, 1768 R_AX_TMAC_ERR_IMR_ISR + offset)); 1769 } 1770 p += scnprintf(p, end - p, 1771 "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1772 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1773 } 1774 1775 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1776 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1777 1778 out: 1779 return p - buf; 1780 } 1781 1782 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1783 char *buf, size_t bufsz) 1784 { 1785 char *p = buf, *end = buf + bufsz; 1786 1787 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_0); 1788 if (rtwdev->dbcc_en) 1789 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_1); 1790 1791 return p - buf; 1792 } 1793 1794 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1795 .sel_addr = R_AX_PTCL_DBG, 1796 .sel_byte = 1, 1797 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1798 .srt = 0x00, 1799 .end = 0x3F, 1800 .rd_addr = R_AX_PTCL_DBG_INFO, 1801 .rd_byte = 4, 1802 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1803 }; 1804 1805 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1806 .sel_addr = R_AX_PTCL_DBG_C1, 1807 .sel_byte = 1, 1808 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1809 .srt = 0x00, 1810 .end = 0x3F, 1811 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1812 .rd_byte = 4, 1813 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1814 }; 1815 1816 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1817 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1818 .sel_byte = 2, 1819 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1820 .srt = 0x0, 1821 .end = 0xD, 1822 .rd_addr = R_AX_DBG_PORT_SEL, 1823 .rd_byte = 4, 1824 .rd_msk = B_AX_DEBUG_ST_MASK 1825 }; 1826 1827 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1828 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1829 .sel_byte = 2, 1830 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1831 .srt = 0x0, 1832 .end = 0x5, 1833 .rd_addr = R_AX_DBG_PORT_SEL, 1834 .rd_byte = 4, 1835 .rd_msk = B_AX_DEBUG_ST_MASK 1836 }; 1837 1838 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1839 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1840 .sel_byte = 2, 1841 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1842 .srt = 0x0, 1843 .end = 0x9, 1844 .rd_addr = R_AX_DBG_PORT_SEL, 1845 .rd_byte = 4, 1846 .rd_msk = B_AX_DEBUG_ST_MASK 1847 }; 1848 1849 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1850 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1851 .sel_byte = 2, 1852 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1853 .srt = 0x0, 1854 .end = 0x3, 1855 .rd_addr = R_AX_DBG_PORT_SEL, 1856 .rd_byte = 4, 1857 .rd_msk = B_AX_DEBUG_ST_MASK 1858 }; 1859 1860 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1861 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1862 .sel_byte = 2, 1863 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1864 .srt = 0x0, 1865 .end = 0x1, 1866 .rd_addr = R_AX_DBG_PORT_SEL, 1867 .rd_byte = 4, 1868 .rd_msk = B_AX_DEBUG_ST_MASK 1869 }; 1870 1871 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1872 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1873 .sel_byte = 2, 1874 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1875 .srt = 0x0, 1876 .end = 0x0, 1877 .rd_addr = R_AX_DBG_PORT_SEL, 1878 .rd_byte = 4, 1879 .rd_msk = B_AX_DEBUG_ST_MASK 1880 }; 1881 1882 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1883 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1884 .sel_byte = 2, 1885 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1886 .srt = 0x0, 1887 .end = 0xB, 1888 .rd_addr = R_AX_DBG_PORT_SEL, 1889 .rd_byte = 4, 1890 .rd_msk = B_AX_DEBUG_ST_MASK 1891 }; 1892 1893 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1894 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1895 .sel_byte = 2, 1896 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1897 .srt = 0x0, 1898 .end = 0x4, 1899 .rd_addr = R_AX_DBG_PORT_SEL, 1900 .rd_byte = 4, 1901 .rd_msk = B_AX_DEBUG_ST_MASK 1902 }; 1903 1904 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1905 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1906 .sel_byte = 2, 1907 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1908 .srt = 0x0, 1909 .end = 0x8, 1910 .rd_addr = R_AX_DBG_PORT_SEL, 1911 .rd_byte = 4, 1912 .rd_msk = B_AX_DEBUG_ST_MASK 1913 }; 1914 1915 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1916 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1917 .sel_byte = 2, 1918 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1919 .srt = 0x0, 1920 .end = 0x7, 1921 .rd_addr = R_AX_DBG_PORT_SEL, 1922 .rd_byte = 4, 1923 .rd_msk = B_AX_DEBUG_ST_MASK 1924 }; 1925 1926 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 1927 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1928 .sel_byte = 2, 1929 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1930 .srt = 0x0, 1931 .end = 0x1, 1932 .rd_addr = R_AX_DBG_PORT_SEL, 1933 .rd_byte = 4, 1934 .rd_msk = B_AX_DEBUG_ST_MASK 1935 }; 1936 1937 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 1938 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1939 .sel_byte = 2, 1940 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1941 .srt = 0x0, 1942 .end = 0x3, 1943 .rd_addr = R_AX_DBG_PORT_SEL, 1944 .rd_byte = 4, 1945 .rd_msk = B_AX_DEBUG_ST_MASK 1946 }; 1947 1948 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 1949 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1950 .sel_byte = 2, 1951 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1952 .srt = 0x0, 1953 .end = 0x0, 1954 .rd_addr = R_AX_DBG_PORT_SEL, 1955 .rd_byte = 4, 1956 .rd_msk = B_AX_DEBUG_ST_MASK 1957 }; 1958 1959 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 1960 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1961 .sel_byte = 2, 1962 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1963 .srt = 0x0, 1964 .end = 0x8, 1965 .rd_addr = R_AX_DBG_PORT_SEL, 1966 .rd_byte = 4, 1967 .rd_msk = B_AX_DEBUG_ST_MASK 1968 }; 1969 1970 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 1971 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1972 .sel_byte = 2, 1973 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1974 .srt = 0x0, 1975 .end = 0x0, 1976 .rd_addr = R_AX_DBG_PORT_SEL, 1977 .rd_byte = 4, 1978 .rd_msk = B_AX_DEBUG_ST_MASK 1979 }; 1980 1981 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 1982 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1983 .sel_byte = 2, 1984 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1985 .srt = 0x0, 1986 .end = 0x6, 1987 .rd_addr = R_AX_DBG_PORT_SEL, 1988 .rd_byte = 4, 1989 .rd_msk = B_AX_DEBUG_ST_MASK 1990 }; 1991 1992 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 1993 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1994 .sel_byte = 2, 1995 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1996 .srt = 0x0, 1997 .end = 0x0, 1998 .rd_addr = R_AX_DBG_PORT_SEL, 1999 .rd_byte = 4, 2000 .rd_msk = B_AX_DEBUG_ST_MASK 2001 }; 2002 2003 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 2004 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2005 .sel_byte = 2, 2006 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2007 .srt = 0x0, 2008 .end = 0x0, 2009 .rd_addr = R_AX_DBG_PORT_SEL, 2010 .rd_byte = 4, 2011 .rd_msk = B_AX_DEBUG_ST_MASK 2012 }; 2013 2014 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 2015 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2016 .sel_byte = 1, 2017 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2018 .srt = 0x0, 2019 .end = 0x3, 2020 .rd_addr = R_AX_DBG_PORT_SEL, 2021 .rd_byte = 4, 2022 .rd_msk = B_AX_DEBUG_ST_MASK 2023 }; 2024 2025 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 2026 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2027 .sel_byte = 1, 2028 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2029 .srt = 0x0, 2030 .end = 0x6, 2031 .rd_addr = R_AX_DBG_PORT_SEL, 2032 .rd_byte = 4, 2033 .rd_msk = B_AX_DEBUG_ST_MASK 2034 }; 2035 2036 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 2037 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2038 .sel_byte = 1, 2039 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2040 .srt = 0x0, 2041 .end = 0x0, 2042 .rd_addr = R_AX_DBG_PORT_SEL, 2043 .rd_byte = 4, 2044 .rd_msk = B_AX_DEBUG_ST_MASK 2045 }; 2046 2047 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 2048 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2049 .sel_byte = 1, 2050 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2051 .srt = 0x8, 2052 .end = 0xE, 2053 .rd_addr = R_AX_DBG_PORT_SEL, 2054 .rd_byte = 4, 2055 .rd_msk = B_AX_DEBUG_ST_MASK 2056 }; 2057 2058 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 2059 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2060 .sel_byte = 1, 2061 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2062 .srt = 0x0, 2063 .end = 0x5, 2064 .rd_addr = R_AX_DBG_PORT_SEL, 2065 .rd_byte = 4, 2066 .rd_msk = B_AX_DEBUG_ST_MASK 2067 }; 2068 2069 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 2070 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2071 .sel_byte = 1, 2072 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2073 .srt = 0x0, 2074 .end = 0x6, 2075 .rd_addr = R_AX_DBG_PORT_SEL, 2076 .rd_byte = 4, 2077 .rd_msk = B_AX_DEBUG_ST_MASK 2078 }; 2079 2080 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 2081 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2082 .sel_byte = 1, 2083 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2084 .srt = 0x0, 2085 .end = 0xF, 2086 .rd_addr = R_AX_DBG_PORT_SEL, 2087 .rd_byte = 4, 2088 .rd_msk = B_AX_DEBUG_ST_MASK 2089 }; 2090 2091 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 2092 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2093 .sel_byte = 1, 2094 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2095 .srt = 0x0, 2096 .end = 0x9, 2097 .rd_addr = R_AX_DBG_PORT_SEL, 2098 .rd_byte = 4, 2099 .rd_msk = B_AX_DEBUG_ST_MASK 2100 }; 2101 2102 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 2103 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2104 .sel_byte = 1, 2105 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2106 .srt = 0x0, 2107 .end = 0x3, 2108 .rd_addr = R_AX_DBG_PORT_SEL, 2109 .rd_byte = 4, 2110 .rd_msk = B_AX_DEBUG_ST_MASK 2111 }; 2112 2113 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 2114 .sel_addr = R_AX_SCH_DBG_SEL, 2115 .sel_byte = 1, 2116 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2117 .srt = 0x00, 2118 .end = 0x2F, 2119 .rd_addr = R_AX_SCH_DBG, 2120 .rd_byte = 4, 2121 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2122 }; 2123 2124 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 2125 .sel_addr = R_AX_SCH_DBG_SEL_C1, 2126 .sel_byte = 1, 2127 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2128 .srt = 0x00, 2129 .end = 0x2F, 2130 .rd_addr = R_AX_SCH_DBG_C1, 2131 .rd_byte = 4, 2132 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2133 }; 2134 2135 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 2136 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 2137 .sel_byte = 1, 2138 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2139 .srt = 0x00, 2140 .end = 0x19, 2141 .rd_addr = R_AX_DBG_PORT_SEL, 2142 .rd_byte = 4, 2143 .rd_msk = B_AX_DEBUG_ST_MASK 2144 }; 2145 2146 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 2147 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 2148 .sel_byte = 1, 2149 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2150 .srt = 0x00, 2151 .end = 0x19, 2152 .rd_addr = R_AX_DBG_PORT_SEL, 2153 .rd_byte = 4, 2154 .rd_msk = B_AX_DEBUG_ST_MASK 2155 }; 2156 2157 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 2158 .sel_addr = R_AX_RX_DEBUG_SELECT, 2159 .sel_byte = 1, 2160 .sel_msk = B_AX_DEBUG_SEL_MASK, 2161 .srt = 0x00, 2162 .end = 0x58, 2163 .rd_addr = R_AX_DBG_PORT_SEL, 2164 .rd_byte = 4, 2165 .rd_msk = B_AX_DEBUG_ST_MASK 2166 }; 2167 2168 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 2169 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 2170 .sel_byte = 1, 2171 .sel_msk = B_AX_DEBUG_SEL_MASK, 2172 .srt = 0x00, 2173 .end = 0x58, 2174 .rd_addr = R_AX_DBG_PORT_SEL, 2175 .rd_byte = 4, 2176 .rd_msk = B_AX_DEBUG_ST_MASK 2177 }; 2178 2179 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 2180 .sel_addr = R_AX_RX_STATE_MONITOR, 2181 .sel_byte = 1, 2182 .sel_msk = B_AX_STATE_SEL_MASK, 2183 .srt = 0x00, 2184 .end = 0x17, 2185 .rd_addr = R_AX_RX_STATE_MONITOR, 2186 .rd_byte = 4, 2187 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2188 }; 2189 2190 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 2191 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 2192 .sel_byte = 1, 2193 .sel_msk = B_AX_STATE_SEL_MASK, 2194 .srt = 0x00, 2195 .end = 0x17, 2196 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 2197 .rd_byte = 4, 2198 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2199 }; 2200 2201 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 2202 .sel_addr = R_AX_RMAC_PLCP_MON, 2203 .sel_byte = 4, 2204 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2205 .srt = 0x0, 2206 .end = 0xF, 2207 .rd_addr = R_AX_RMAC_PLCP_MON, 2208 .rd_byte = 4, 2209 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2210 }; 2211 2212 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 2213 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 2214 .sel_byte = 4, 2215 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2216 .srt = 0x0, 2217 .end = 0xF, 2218 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 2219 .rd_byte = 4, 2220 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2221 }; 2222 2223 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 2224 .sel_addr = R_AX_DBGSEL_TRXPTCL, 2225 .sel_byte = 1, 2226 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2227 .srt = 0x08, 2228 .end = 0x10, 2229 .rd_addr = R_AX_DBG_PORT_SEL, 2230 .rd_byte = 4, 2231 .rd_msk = B_AX_DEBUG_ST_MASK 2232 }; 2233 2234 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 2235 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 2236 .sel_byte = 1, 2237 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2238 .srt = 0x08, 2239 .end = 0x10, 2240 .rd_addr = R_AX_DBG_PORT_SEL, 2241 .rd_byte = 4, 2242 .rd_msk = B_AX_DEBUG_ST_MASK 2243 }; 2244 2245 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 2246 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2247 .sel_byte = 1, 2248 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2249 .srt = 0x00, 2250 .end = 0x07, 2251 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 2252 .rd_byte = 4, 2253 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2254 }; 2255 2256 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 2257 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2258 .sel_byte = 1, 2259 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2260 .srt = 0x00, 2261 .end = 0x07, 2262 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 2263 .rd_byte = 4, 2264 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2265 }; 2266 2267 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 2268 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2269 .sel_byte = 1, 2270 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2271 .srt = 0x00, 2272 .end = 0x07, 2273 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 2274 .rd_byte = 4, 2275 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2276 }; 2277 2278 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 2279 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2280 .sel_byte = 1, 2281 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2282 .srt = 0x00, 2283 .end = 0x07, 2284 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 2285 .rd_byte = 4, 2286 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2287 }; 2288 2289 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 2290 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2291 .sel_byte = 1, 2292 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2293 .srt = 0x00, 2294 .end = 0x04, 2295 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 2296 .rd_byte = 4, 2297 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2298 }; 2299 2300 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 2301 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2302 .sel_byte = 1, 2303 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2304 .srt = 0x00, 2305 .end = 0x04, 2306 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 2307 .rd_byte = 4, 2308 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2309 }; 2310 2311 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 2312 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2313 .sel_byte = 1, 2314 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2315 .srt = 0x00, 2316 .end = 0x04, 2317 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 2318 .rd_byte = 4, 2319 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2320 }; 2321 2322 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 2323 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2324 .sel_byte = 1, 2325 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2326 .srt = 0x00, 2327 .end = 0x04, 2328 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 2329 .rd_byte = 4, 2330 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2331 }; 2332 2333 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 2334 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2335 .sel_byte = 4, 2336 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2337 .srt = 0x80000000, 2338 .end = 0x80000001, 2339 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2340 .rd_byte = 4, 2341 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2342 }; 2343 2344 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 2345 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2346 .sel_byte = 4, 2347 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2348 .srt = 0x80010000, 2349 .end = 0x80010004, 2350 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2351 .rd_byte = 4, 2352 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2353 }; 2354 2355 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 2356 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2357 .sel_byte = 4, 2358 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2359 .srt = 0x80020000, 2360 .end = 0x80020FFF, 2361 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2362 .rd_byte = 4, 2363 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2364 }; 2365 2366 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 2367 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2368 .sel_byte = 4, 2369 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2370 .srt = 0x80030000, 2371 .end = 0x80030FFF, 2372 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2373 .rd_byte = 4, 2374 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2375 }; 2376 2377 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 2378 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2379 .sel_byte = 4, 2380 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2381 .srt = 0x80040000, 2382 .end = 0x80040FFF, 2383 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2384 .rd_byte = 4, 2385 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2386 }; 2387 2388 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 2389 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2390 .sel_byte = 4, 2391 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2392 .srt = 0x80050000, 2393 .end = 0x80050FFF, 2394 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2395 .rd_byte = 4, 2396 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2397 }; 2398 2399 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 2400 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2401 .sel_byte = 4, 2402 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2403 .srt = 0x80060000, 2404 .end = 0x80060453, 2405 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2406 .rd_byte = 4, 2407 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2408 }; 2409 2410 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 2411 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2412 .sel_byte = 4, 2413 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2414 .srt = 0x80070000, 2415 .end = 0x80070011, 2416 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2417 .rd_byte = 4, 2418 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2419 }; 2420 2421 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 2422 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2423 .sel_byte = 4, 2424 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2425 .srt = 0x80000000, 2426 .end = 0x80000001, 2427 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2428 .rd_byte = 4, 2429 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2430 }; 2431 2432 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 2433 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2434 .sel_byte = 4, 2435 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2436 .srt = 0x80010000, 2437 .end = 0x8001000A, 2438 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2439 .rd_byte = 4, 2440 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2441 }; 2442 2443 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2444 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2445 .sel_byte = 4, 2446 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2447 .srt = 0x80020000, 2448 .end = 0x80020DBF, 2449 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2450 .rd_byte = 4, 2451 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2452 }; 2453 2454 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2455 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2456 .sel_byte = 4, 2457 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2458 .srt = 0x80030000, 2459 .end = 0x80030DBF, 2460 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2461 .rd_byte = 4, 2462 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2463 }; 2464 2465 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2466 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2467 .sel_byte = 4, 2468 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2469 .srt = 0x80040000, 2470 .end = 0x80040DBF, 2471 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2472 .rd_byte = 4, 2473 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2474 }; 2475 2476 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2477 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2478 .sel_byte = 4, 2479 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2480 .srt = 0x80050000, 2481 .end = 0x80050DBF, 2482 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2483 .rd_byte = 4, 2484 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2485 }; 2486 2487 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2488 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2489 .sel_byte = 4, 2490 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2491 .srt = 0x80060000, 2492 .end = 0x80060041, 2493 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2494 .rd_byte = 4, 2495 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2496 }; 2497 2498 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2499 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2500 .sel_byte = 4, 2501 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2502 .srt = 0x80070000, 2503 .end = 0x80070001, 2504 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2505 .rd_byte = 4, 2506 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2507 }; 2508 2509 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2510 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2511 .sel_byte = 4, 2512 .sel_msk = B_AX_DFI_DATA_MASK, 2513 .srt = 0x80000000, 2514 .end = 0x8000017f, 2515 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2516 .rd_byte = 4, 2517 .rd_msk = B_AX_DFI_DATA_MASK 2518 }; 2519 2520 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2521 .sel_addr = R_AX_PCIE_DBG_CTRL, 2522 .sel_byte = 2, 2523 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2524 .srt = 0x00, 2525 .end = 0x03, 2526 .rd_addr = R_AX_DBG_PORT_SEL, 2527 .rd_byte = 4, 2528 .rd_msk = B_AX_DEBUG_ST_MASK 2529 }; 2530 2531 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2532 .sel_addr = R_AX_PCIE_DBG_CTRL, 2533 .sel_byte = 2, 2534 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2535 .srt = 0x00, 2536 .end = 0x04, 2537 .rd_addr = R_AX_DBG_PORT_SEL, 2538 .rd_byte = 4, 2539 .rd_msk = B_AX_DEBUG_ST_MASK 2540 }; 2541 2542 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2543 .sel_addr = R_AX_PCIE_DBG_CTRL, 2544 .sel_byte = 2, 2545 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2546 .srt = 0x00, 2547 .end = 0x01, 2548 .rd_addr = R_AX_DBG_PORT_SEL, 2549 .rd_byte = 4, 2550 .rd_msk = B_AX_DEBUG_ST_MASK 2551 }; 2552 2553 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2554 .sel_addr = R_AX_PCIE_DBG_CTRL, 2555 .sel_byte = 2, 2556 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2557 .srt = 0x00, 2558 .end = 0x05, 2559 .rd_addr = R_AX_DBG_PORT_SEL, 2560 .rd_byte = 4, 2561 .rd_msk = B_AX_DEBUG_ST_MASK 2562 }; 2563 2564 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2565 .sel_addr = R_AX_PCIE_DBG_CTRL, 2566 .sel_byte = 2, 2567 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2568 .srt = 0x00, 2569 .end = 0x05, 2570 .rd_addr = R_AX_DBG_PORT_SEL, 2571 .rd_byte = 4, 2572 .rd_msk = B_AX_DEBUG_ST_MASK 2573 }; 2574 2575 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2576 .sel_addr = R_AX_PCIE_DBG_CTRL, 2577 .sel_byte = 2, 2578 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2579 .srt = 0x00, 2580 .end = 0x06, 2581 .rd_addr = R_AX_DBG_PORT_SEL, 2582 .rd_byte = 4, 2583 .rd_msk = B_AX_DEBUG_ST_MASK 2584 }; 2585 2586 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2587 .sel_addr = R_AX_DBG_CTRL, 2588 .sel_byte = 1, 2589 .sel_msk = B_AX_DBG_SEL0, 2590 .srt = 0x34, 2591 .end = 0x3C, 2592 .rd_addr = R_AX_DBG_PORT_SEL, 2593 .rd_byte = 4, 2594 .rd_msk = B_AX_DEBUG_ST_MASK 2595 }; 2596 2597 static int 2598 rtw89_debug_mac_dbg_port_sel(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 2599 u32 sel, const struct rtw89_mac_dbg_port_info **ppinfo) 2600 { 2601 const struct rtw89_mac_dbg_port_info *info = NULL; 2602 char *p = buf, *end = buf + bufsz; 2603 u32 index; 2604 u32 val32; 2605 u16 val16; 2606 u8 val8; 2607 2608 switch (sel) { 2609 case RTW89_DBG_PORT_SEL_PTCL_C0: 2610 info = &dbg_port_ptcl_c0; 2611 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2612 val16 |= B_AX_PTCL_DBG_EN; 2613 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2614 p += scnprintf(p, end - p, "Enable PTCL C0 dbgport.\n"); 2615 break; 2616 case RTW89_DBG_PORT_SEL_PTCL_C1: 2617 info = &dbg_port_ptcl_c1; 2618 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2619 val16 |= B_AX_PTCL_DBG_EN; 2620 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2621 p += scnprintf(p, end - p, "Enable PTCL C1 dbgport.\n"); 2622 break; 2623 case RTW89_DBG_PORT_SEL_SCH_C0: 2624 info = &dbg_port_sch_c0; 2625 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2626 val32 |= B_AX_SCH_DBG_EN; 2627 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2628 p += scnprintf(p, end - p, "Enable SCH C0 dbgport.\n"); 2629 break; 2630 case RTW89_DBG_PORT_SEL_SCH_C1: 2631 info = &dbg_port_sch_c1; 2632 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2633 val32 |= B_AX_SCH_DBG_EN; 2634 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2635 p += scnprintf(p, end - p, "Enable SCH C1 dbgport.\n"); 2636 break; 2637 case RTW89_DBG_PORT_SEL_TMAC_C0: 2638 info = &dbg_port_tmac_c0; 2639 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2640 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2641 B_AX_DBGSEL_TRXPTCL_MASK); 2642 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2643 2644 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2645 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2646 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2647 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2648 2649 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2650 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2651 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2652 p += scnprintf(p, end - p, "Enable TMAC C0 dbgport.\n"); 2653 break; 2654 case RTW89_DBG_PORT_SEL_TMAC_C1: 2655 info = &dbg_port_tmac_c1; 2656 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2657 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2658 B_AX_DBGSEL_TRXPTCL_MASK); 2659 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2660 2661 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2662 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2663 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2664 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2665 2666 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2667 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2668 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2669 p += scnprintf(p, end - p, "Enable TMAC C1 dbgport.\n"); 2670 break; 2671 case RTW89_DBG_PORT_SEL_RMAC_C0: 2672 info = &dbg_port_rmac_c0; 2673 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2674 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2675 B_AX_DBGSEL_TRXPTCL_MASK); 2676 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2677 2678 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2679 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2680 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2681 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2682 2683 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2684 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2685 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2686 2687 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2688 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2689 B_AX_DBGSEL_TRXPTCL_MASK); 2690 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2691 p += scnprintf(p, end - p, "Enable RMAC C0 dbgport.\n"); 2692 break; 2693 case RTW89_DBG_PORT_SEL_RMAC_C1: 2694 info = &dbg_port_rmac_c1; 2695 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2696 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2697 B_AX_DBGSEL_TRXPTCL_MASK); 2698 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2699 2700 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2701 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2702 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2703 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2704 2705 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2706 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2707 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2708 2709 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2710 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2711 B_AX_DBGSEL_TRXPTCL_MASK); 2712 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2713 p += scnprintf(p, end - p, "Enable RMAC C1 dbgport.\n"); 2714 break; 2715 case RTW89_DBG_PORT_SEL_RMACST_C0: 2716 info = &dbg_port_rmacst_c0; 2717 p += scnprintf(p, end - p, "Enable RMAC state C0 dbgport.\n"); 2718 break; 2719 case RTW89_DBG_PORT_SEL_RMACST_C1: 2720 info = &dbg_port_rmacst_c1; 2721 p += scnprintf(p, end - p, "Enable RMAC state C1 dbgport.\n"); 2722 break; 2723 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2724 info = &dbg_port_rmac_plcp_c0; 2725 p += scnprintf(p, end - p, "Enable RMAC PLCP C0 dbgport.\n"); 2726 break; 2727 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2728 info = &dbg_port_rmac_plcp_c1; 2729 p += scnprintf(p, end - p, "Enable RMAC PLCP C1 dbgport.\n"); 2730 break; 2731 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2732 info = &dbg_port_trxptcl_c0; 2733 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2734 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2735 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2736 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2737 2738 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2739 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2740 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2741 p += scnprintf(p, end - p, "Enable TRXPTCL C0 dbgport.\n"); 2742 break; 2743 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2744 info = &dbg_port_trxptcl_c1; 2745 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2746 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2747 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2748 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2749 2750 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2751 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2752 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2753 p += scnprintf(p, end - p, "Enable TRXPTCL C1 dbgport.\n"); 2754 break; 2755 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2756 info = &dbg_port_tx_infol_c0; 2757 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2758 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2759 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2760 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2761 break; 2762 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2763 info = &dbg_port_tx_infoh_c0; 2764 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2765 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2766 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2767 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2768 break; 2769 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2770 info = &dbg_port_tx_infol_c1; 2771 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2772 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2773 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2774 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2775 break; 2776 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2777 info = &dbg_port_tx_infoh_c1; 2778 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2779 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2780 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2781 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2782 break; 2783 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2784 info = &dbg_port_txtf_infol_c0; 2785 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2786 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2787 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2788 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2789 break; 2790 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2791 info = &dbg_port_txtf_infoh_c0; 2792 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2793 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2794 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2795 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2796 break; 2797 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2798 info = &dbg_port_txtf_infol_c1; 2799 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2800 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2801 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2802 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2803 break; 2804 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2805 info = &dbg_port_txtf_infoh_c1; 2806 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2807 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2808 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2809 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2810 break; 2811 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2812 info = &dbg_port_wde_bufmgn_freepg; 2813 p += scnprintf(p, end - p, "Enable wde bufmgn freepg dump.\n"); 2814 break; 2815 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2816 info = &dbg_port_wde_bufmgn_quota; 2817 p += scnprintf(p, end - p, "Enable wde bufmgn quota dump.\n"); 2818 break; 2819 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2820 info = &dbg_port_wde_bufmgn_pagellt; 2821 p += scnprintf(p, end - p, 2822 "Enable wde bufmgn pagellt dump.\n"); 2823 break; 2824 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2825 info = &dbg_port_wde_bufmgn_pktinfo; 2826 p += scnprintf(p, end - p, 2827 "Enable wde bufmgn pktinfo dump.\n"); 2828 break; 2829 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2830 info = &dbg_port_wde_quemgn_prepkt; 2831 p += scnprintf(p, end - p, "Enable wde quemgn prepkt dump.\n"); 2832 break; 2833 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2834 info = &dbg_port_wde_quemgn_nxtpkt; 2835 p += scnprintf(p, end - p, "Enable wde quemgn nxtpkt dump.\n"); 2836 break; 2837 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2838 info = &dbg_port_wde_quemgn_qlnktbl; 2839 p += scnprintf(p, end - p, 2840 "Enable wde quemgn qlnktbl dump.\n"); 2841 break; 2842 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2843 info = &dbg_port_wde_quemgn_qempty; 2844 p += scnprintf(p, end - p, "Enable wde quemgn qempty dump.\n"); 2845 break; 2846 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2847 info = &dbg_port_ple_bufmgn_freepg; 2848 p += scnprintf(p, end - p, "Enable ple bufmgn freepg dump.\n"); 2849 break; 2850 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2851 info = &dbg_port_ple_bufmgn_quota; 2852 p += scnprintf(p, end - p, "Enable ple bufmgn quota dump.\n"); 2853 break; 2854 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2855 info = &dbg_port_ple_bufmgn_pagellt; 2856 p += scnprintf(p, end - p, 2857 "Enable ple bufmgn pagellt dump.\n"); 2858 break; 2859 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2860 info = &dbg_port_ple_bufmgn_pktinfo; 2861 p += scnprintf(p, end - p, 2862 "Enable ple bufmgn pktinfo dump.\n"); 2863 break; 2864 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2865 info = &dbg_port_ple_quemgn_prepkt; 2866 p += scnprintf(p, end - p, "Enable ple quemgn prepkt dump.\n"); 2867 break; 2868 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2869 info = &dbg_port_ple_quemgn_nxtpkt; 2870 p += scnprintf(p, end - p, "Enable ple quemgn nxtpkt dump.\n"); 2871 break; 2872 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2873 info = &dbg_port_ple_quemgn_qlnktbl; 2874 p += scnprintf(p, end - p, 2875 "Enable ple quemgn qlnktbl dump.\n"); 2876 break; 2877 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2878 info = &dbg_port_ple_quemgn_qempty; 2879 p += scnprintf(p, end - p, "Enable ple quemgn qempty dump.\n"); 2880 break; 2881 case RTW89_DBG_PORT_SEL_PKTINFO: 2882 info = &dbg_port_pktinfo; 2883 p += scnprintf(p, end - p, "Enable pktinfo dump.\n"); 2884 break; 2885 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2886 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2887 B_AX_DBG_SEL0, 0x80); 2888 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2889 B_AX_SEL_0XC0_MASK, 1); 2890 fallthrough; 2891 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2892 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2893 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2894 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2895 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2896 info = &dbg_port_dspt_hdt_tx0_5; 2897 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2898 rtw89_write16_mask(rtwdev, info->sel_addr, 2899 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2900 rtw89_write16_mask(rtwdev, info->sel_addr, 2901 B_AX_DISPATCHER_CH_SEL_MASK, index); 2902 p += scnprintf(p, end - p, 2903 "Enable Dispatcher hdt tx%x dump.\n", index); 2904 break; 2905 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2906 info = &dbg_port_dspt_hdt_tx6; 2907 rtw89_write16_mask(rtwdev, info->sel_addr, 2908 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2909 rtw89_write16_mask(rtwdev, info->sel_addr, 2910 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2911 p += scnprintf(p, end - p, 2912 "Enable Dispatcher hdt tx6 dump.\n"); 2913 break; 2914 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2915 info = &dbg_port_dspt_hdt_tx7; 2916 rtw89_write16_mask(rtwdev, info->sel_addr, 2917 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2918 rtw89_write16_mask(rtwdev, info->sel_addr, 2919 B_AX_DISPATCHER_CH_SEL_MASK, 7); 2920 p += scnprintf(p, end - p, 2921 "Enable Dispatcher hdt tx7 dump.\n"); 2922 break; 2923 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 2924 info = &dbg_port_dspt_hdt_tx8; 2925 rtw89_write16_mask(rtwdev, info->sel_addr, 2926 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2927 rtw89_write16_mask(rtwdev, info->sel_addr, 2928 B_AX_DISPATCHER_CH_SEL_MASK, 8); 2929 p += scnprintf(p, end - p, 2930 "Enable Dispatcher hdt tx8 dump.\n"); 2931 break; 2932 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 2933 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 2934 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 2935 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 2936 info = &dbg_port_dspt_hdt_tx9_C; 2937 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 2938 rtw89_write16_mask(rtwdev, info->sel_addr, 2939 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2940 rtw89_write16_mask(rtwdev, info->sel_addr, 2941 B_AX_DISPATCHER_CH_SEL_MASK, index); 2942 p += scnprintf(p, end - p, 2943 "Enable Dispatcher hdt tx%x dump.\n", index); 2944 break; 2945 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 2946 info = &dbg_port_dspt_hdt_txD; 2947 rtw89_write16_mask(rtwdev, info->sel_addr, 2948 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2949 rtw89_write16_mask(rtwdev, info->sel_addr, 2950 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 2951 p += scnprintf(p, end - p, 2952 "Enable Dispatcher hdt txD dump.\n"); 2953 break; 2954 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 2955 info = &dbg_port_dspt_cdt_tx0; 2956 rtw89_write16_mask(rtwdev, info->sel_addr, 2957 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2958 rtw89_write16_mask(rtwdev, info->sel_addr, 2959 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2960 p += scnprintf(p, end - p, 2961 "Enable Dispatcher cdt tx0 dump.\n"); 2962 break; 2963 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 2964 info = &dbg_port_dspt_cdt_tx1; 2965 rtw89_write16_mask(rtwdev, info->sel_addr, 2966 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2967 rtw89_write16_mask(rtwdev, info->sel_addr, 2968 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2969 p += scnprintf(p, end - p, 2970 "Enable Dispatcher cdt tx1 dump.\n"); 2971 break; 2972 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 2973 info = &dbg_port_dspt_cdt_tx3; 2974 rtw89_write16_mask(rtwdev, info->sel_addr, 2975 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2976 rtw89_write16_mask(rtwdev, info->sel_addr, 2977 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2978 p += scnprintf(p, end - p, 2979 "Enable Dispatcher cdt tx3 dump.\n"); 2980 break; 2981 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 2982 info = &dbg_port_dspt_cdt_tx4; 2983 rtw89_write16_mask(rtwdev, info->sel_addr, 2984 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2985 rtw89_write16_mask(rtwdev, info->sel_addr, 2986 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2987 p += scnprintf(p, end - p, 2988 "Enable Dispatcher cdt tx4 dump.\n"); 2989 break; 2990 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 2991 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 2992 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 2993 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 2994 info = &dbg_port_dspt_cdt_tx5_8; 2995 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 2996 rtw89_write16_mask(rtwdev, info->sel_addr, 2997 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2998 rtw89_write16_mask(rtwdev, info->sel_addr, 2999 B_AX_DISPATCHER_CH_SEL_MASK, index); 3000 p += scnprintf(p, end - p, 3001 "Enable Dispatcher cdt tx%x dump.\n", index); 3002 break; 3003 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 3004 info = &dbg_port_dspt_cdt_tx9; 3005 rtw89_write16_mask(rtwdev, info->sel_addr, 3006 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3007 rtw89_write16_mask(rtwdev, info->sel_addr, 3008 B_AX_DISPATCHER_CH_SEL_MASK, 9); 3009 p += scnprintf(p, end - p, 3010 "Enable Dispatcher cdt tx9 dump.\n"); 3011 break; 3012 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 3013 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 3014 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 3015 info = &dbg_port_dspt_cdt_txA_C; 3016 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 3017 rtw89_write16_mask(rtwdev, info->sel_addr, 3018 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3019 rtw89_write16_mask(rtwdev, info->sel_addr, 3020 B_AX_DISPATCHER_CH_SEL_MASK, index); 3021 p += scnprintf(p, end - p, 3022 "Enable Dispatcher cdt tx%x dump.\n", index); 3023 break; 3024 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 3025 info = &dbg_port_dspt_hdt_rx0; 3026 rtw89_write16_mask(rtwdev, info->sel_addr, 3027 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3028 rtw89_write16_mask(rtwdev, info->sel_addr, 3029 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3030 p += scnprintf(p, end - p, 3031 "Enable Dispatcher hdt rx0 dump.\n"); 3032 break; 3033 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 3034 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 3035 info = &dbg_port_dspt_hdt_rx1_2; 3036 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 3037 rtw89_write16_mask(rtwdev, info->sel_addr, 3038 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3039 rtw89_write16_mask(rtwdev, info->sel_addr, 3040 B_AX_DISPATCHER_CH_SEL_MASK, index); 3041 p += scnprintf(p, end - p, 3042 "Enable Dispatcher hdt rx%x dump.\n", index); 3043 break; 3044 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 3045 info = &dbg_port_dspt_hdt_rx3; 3046 rtw89_write16_mask(rtwdev, info->sel_addr, 3047 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3048 rtw89_write16_mask(rtwdev, info->sel_addr, 3049 B_AX_DISPATCHER_CH_SEL_MASK, 3); 3050 p += scnprintf(p, end - p, 3051 "Enable Dispatcher hdt rx3 dump.\n"); 3052 break; 3053 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 3054 info = &dbg_port_dspt_hdt_rx4; 3055 rtw89_write16_mask(rtwdev, info->sel_addr, 3056 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3057 rtw89_write16_mask(rtwdev, info->sel_addr, 3058 B_AX_DISPATCHER_CH_SEL_MASK, 4); 3059 p += scnprintf(p, end - p, 3060 "Enable Dispatcher hdt rx4 dump.\n"); 3061 break; 3062 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 3063 info = &dbg_port_dspt_hdt_rx5; 3064 rtw89_write16_mask(rtwdev, info->sel_addr, 3065 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3066 rtw89_write16_mask(rtwdev, info->sel_addr, 3067 B_AX_DISPATCHER_CH_SEL_MASK, 5); 3068 p += scnprintf(p, end - p, 3069 "Enable Dispatcher hdt rx5 dump.\n"); 3070 break; 3071 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 3072 info = &dbg_port_dspt_cdt_rx_p0_0; 3073 rtw89_write16_mask(rtwdev, info->sel_addr, 3074 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3075 rtw89_write16_mask(rtwdev, info->sel_addr, 3076 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3077 p += scnprintf(p, end - p, 3078 "Enable Dispatcher cdt rx part0 0 dump.\n"); 3079 break; 3080 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 3081 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 3082 info = &dbg_port_dspt_cdt_rx_p0_1; 3083 rtw89_write16_mask(rtwdev, info->sel_addr, 3084 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3085 rtw89_write16_mask(rtwdev, info->sel_addr, 3086 B_AX_DISPATCHER_CH_SEL_MASK, 1); 3087 p += scnprintf(p, end - p, 3088 "Enable Dispatcher cdt rx part0 1 dump.\n"); 3089 break; 3090 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 3091 info = &dbg_port_dspt_cdt_rx_p0_2; 3092 rtw89_write16_mask(rtwdev, info->sel_addr, 3093 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3094 rtw89_write16_mask(rtwdev, info->sel_addr, 3095 B_AX_DISPATCHER_CH_SEL_MASK, 2); 3096 p += scnprintf(p, end - p, 3097 "Enable Dispatcher cdt rx part0 2 dump.\n"); 3098 break; 3099 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 3100 info = &dbg_port_dspt_cdt_rx_p1; 3101 rtw89_write8_mask(rtwdev, info->sel_addr, 3102 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3103 p += scnprintf(p, end - p, 3104 "Enable Dispatcher cdt rx part1 dump.\n"); 3105 break; 3106 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 3107 info = &dbg_port_dspt_stf_ctrl; 3108 rtw89_write8_mask(rtwdev, info->sel_addr, 3109 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 3110 p += scnprintf(p, end - p, 3111 "Enable Dispatcher stf control dump.\n"); 3112 break; 3113 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 3114 info = &dbg_port_dspt_addr_ctrl; 3115 rtw89_write8_mask(rtwdev, info->sel_addr, 3116 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 3117 p += scnprintf(p, end - p, 3118 "Enable Dispatcher addr control dump.\n"); 3119 break; 3120 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 3121 info = &dbg_port_dspt_wde_intf; 3122 rtw89_write8_mask(rtwdev, info->sel_addr, 3123 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 3124 p += scnprintf(p, end - p, 3125 "Enable Dispatcher wde interface dump.\n"); 3126 break; 3127 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 3128 info = &dbg_port_dspt_ple_intf; 3129 rtw89_write8_mask(rtwdev, info->sel_addr, 3130 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 3131 p += scnprintf(p, end - p, 3132 "Enable Dispatcher ple interface dump.\n"); 3133 break; 3134 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 3135 info = &dbg_port_dspt_flow_ctrl; 3136 rtw89_write8_mask(rtwdev, info->sel_addr, 3137 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 3138 p += scnprintf(p, end - p, 3139 "Enable Dispatcher flow control dump.\n"); 3140 break; 3141 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 3142 info = &dbg_port_pcie_txdma; 3143 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3144 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 3145 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 3146 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3147 p += scnprintf(p, end - p, "Enable pcie txdma dump.\n"); 3148 break; 3149 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 3150 info = &dbg_port_pcie_rxdma; 3151 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3152 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 3153 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 3154 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3155 p += scnprintf(p, end - p, "Enable pcie rxdma dump.\n"); 3156 break; 3157 case RTW89_DBG_PORT_SEL_PCIE_CVT: 3158 info = &dbg_port_pcie_cvt; 3159 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3160 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 3161 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 3162 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3163 p += scnprintf(p, end - p, "Enable pcie cvt dump.\n"); 3164 break; 3165 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 3166 info = &dbg_port_pcie_cxpl; 3167 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3168 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 3169 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 3170 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3171 p += scnprintf(p, end - p, "Enable pcie cxpl dump.\n"); 3172 break; 3173 case RTW89_DBG_PORT_SEL_PCIE_IO: 3174 info = &dbg_port_pcie_io; 3175 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3176 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 3177 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 3178 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3179 p += scnprintf(p, end - p, "Enable pcie io dump.\n"); 3180 break; 3181 case RTW89_DBG_PORT_SEL_PCIE_MISC: 3182 info = &dbg_port_pcie_misc; 3183 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3184 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 3185 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 3186 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3187 p += scnprintf(p, end - p, "Enable pcie misc dump.\n"); 3188 break; 3189 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 3190 info = &dbg_port_pcie_misc2; 3191 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 3192 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 3193 B_AX_PCIE_DBG_SEL_MASK); 3194 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 3195 p += scnprintf(p, end - p, "Enable pcie misc2 dump.\n"); 3196 break; 3197 default: 3198 p += scnprintf(p, end - p, "Dbg port select err\n"); 3199 break; 3200 } 3201 3202 *ppinfo = info; 3203 3204 return p - buf; 3205 } 3206 3207 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 3208 { 3209 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 3210 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 3211 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 3212 return false; 3213 if (rtw89_is_rtl885xb(rtwdev) && 3214 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3215 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3216 return false; 3217 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3218 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 3219 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 3220 return false; 3221 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3222 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 3223 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 3224 return false; 3225 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 3226 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 3227 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 3228 return false; 3229 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 3230 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3231 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3232 return false; 3233 3234 return true; 3235 } 3236 3237 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 3238 char *buf, size_t bufsz, u32 sel) 3239 { 3240 const struct rtw89_mac_dbg_port_info *info = NULL; 3241 char *p = buf, *end = buf + bufsz; 3242 u32 val32; 3243 u16 val16; 3244 u8 val8; 3245 u32 i; 3246 3247 p += rtw89_debug_mac_dbg_port_sel(rtwdev, p, end - p, sel, &info); 3248 3249 if (!info) { 3250 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 3251 goto out; 3252 } 3253 3254 #define case_DBG_SEL(__sel) \ 3255 case RTW89_DBG_PORT_SEL_##__sel: \ 3256 p += scnprintf(p, end - p, "Dump debug port " #__sel ":\n"); \ 3257 break 3258 3259 switch (sel) { 3260 case_DBG_SEL(PTCL_C0); 3261 case_DBG_SEL(PTCL_C1); 3262 case_DBG_SEL(SCH_C0); 3263 case_DBG_SEL(SCH_C1); 3264 case_DBG_SEL(TMAC_C0); 3265 case_DBG_SEL(TMAC_C1); 3266 case_DBG_SEL(RMAC_C0); 3267 case_DBG_SEL(RMAC_C1); 3268 case_DBG_SEL(RMACST_C0); 3269 case_DBG_SEL(RMACST_C1); 3270 case_DBG_SEL(TRXPTCL_C0); 3271 case_DBG_SEL(TRXPTCL_C1); 3272 case_DBG_SEL(TX_INFOL_C0); 3273 case_DBG_SEL(TX_INFOH_C0); 3274 case_DBG_SEL(TX_INFOL_C1); 3275 case_DBG_SEL(TX_INFOH_C1); 3276 case_DBG_SEL(TXTF_INFOL_C0); 3277 case_DBG_SEL(TXTF_INFOH_C0); 3278 case_DBG_SEL(TXTF_INFOL_C1); 3279 case_DBG_SEL(TXTF_INFOH_C1); 3280 case_DBG_SEL(WDE_BUFMGN_FREEPG); 3281 case_DBG_SEL(WDE_BUFMGN_QUOTA); 3282 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 3283 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 3284 case_DBG_SEL(WDE_QUEMGN_PREPKT); 3285 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 3286 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 3287 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 3288 case_DBG_SEL(PLE_BUFMGN_FREEPG); 3289 case_DBG_SEL(PLE_BUFMGN_QUOTA); 3290 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 3291 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 3292 case_DBG_SEL(PLE_QUEMGN_PREPKT); 3293 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 3294 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 3295 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 3296 case_DBG_SEL(PKTINFO); 3297 case_DBG_SEL(DSPT_HDT_TX0); 3298 case_DBG_SEL(DSPT_HDT_TX1); 3299 case_DBG_SEL(DSPT_HDT_TX2); 3300 case_DBG_SEL(DSPT_HDT_TX3); 3301 case_DBG_SEL(DSPT_HDT_TX4); 3302 case_DBG_SEL(DSPT_HDT_TX5); 3303 case_DBG_SEL(DSPT_HDT_TX6); 3304 case_DBG_SEL(DSPT_HDT_TX7); 3305 case_DBG_SEL(DSPT_HDT_TX8); 3306 case_DBG_SEL(DSPT_HDT_TX9); 3307 case_DBG_SEL(DSPT_HDT_TXA); 3308 case_DBG_SEL(DSPT_HDT_TXB); 3309 case_DBG_SEL(DSPT_HDT_TXC); 3310 case_DBG_SEL(DSPT_HDT_TXD); 3311 case_DBG_SEL(DSPT_HDT_TXE); 3312 case_DBG_SEL(DSPT_HDT_TXF); 3313 case_DBG_SEL(DSPT_CDT_TX0); 3314 case_DBG_SEL(DSPT_CDT_TX1); 3315 case_DBG_SEL(DSPT_CDT_TX3); 3316 case_DBG_SEL(DSPT_CDT_TX4); 3317 case_DBG_SEL(DSPT_CDT_TX5); 3318 case_DBG_SEL(DSPT_CDT_TX6); 3319 case_DBG_SEL(DSPT_CDT_TX7); 3320 case_DBG_SEL(DSPT_CDT_TX8); 3321 case_DBG_SEL(DSPT_CDT_TX9); 3322 case_DBG_SEL(DSPT_CDT_TXA); 3323 case_DBG_SEL(DSPT_CDT_TXB); 3324 case_DBG_SEL(DSPT_CDT_TXC); 3325 case_DBG_SEL(DSPT_HDT_RX0); 3326 case_DBG_SEL(DSPT_HDT_RX1); 3327 case_DBG_SEL(DSPT_HDT_RX2); 3328 case_DBG_SEL(DSPT_HDT_RX3); 3329 case_DBG_SEL(DSPT_HDT_RX4); 3330 case_DBG_SEL(DSPT_HDT_RX5); 3331 case_DBG_SEL(DSPT_CDT_RX_P0); 3332 case_DBG_SEL(DSPT_CDT_RX_P0_0); 3333 case_DBG_SEL(DSPT_CDT_RX_P0_1); 3334 case_DBG_SEL(DSPT_CDT_RX_P0_2); 3335 case_DBG_SEL(DSPT_CDT_RX_P1); 3336 case_DBG_SEL(DSPT_STF_CTRL); 3337 case_DBG_SEL(DSPT_ADDR_CTRL); 3338 case_DBG_SEL(DSPT_WDE_INTF); 3339 case_DBG_SEL(DSPT_PLE_INTF); 3340 case_DBG_SEL(DSPT_FLOW_CTRL); 3341 case_DBG_SEL(PCIE_TXDMA); 3342 case_DBG_SEL(PCIE_RXDMA); 3343 case_DBG_SEL(PCIE_CVT); 3344 case_DBG_SEL(PCIE_CXPL); 3345 case_DBG_SEL(PCIE_IO); 3346 case_DBG_SEL(PCIE_MISC); 3347 case_DBG_SEL(PCIE_MISC2); 3348 } 3349 3350 #undef case_DBG_SEL 3351 3352 p += scnprintf(p, end - p, "Sel addr = 0x%X\n", info->sel_addr); 3353 p += scnprintf(p, end - p, "Read addr = 0x%X\n", info->rd_addr); 3354 3355 for (i = info->srt; i <= info->end; i++) { 3356 switch (info->sel_byte) { 3357 case 1: 3358 default: 3359 rtw89_write8_mask(rtwdev, info->sel_addr, 3360 info->sel_msk, i); 3361 p += scnprintf(p, end - p, "0x%02X: ", i); 3362 break; 3363 case 2: 3364 rtw89_write16_mask(rtwdev, info->sel_addr, 3365 info->sel_msk, i); 3366 p += scnprintf(p, end - p, "0x%04X: ", i); 3367 break; 3368 case 4: 3369 rtw89_write32_mask(rtwdev, info->sel_addr, 3370 info->sel_msk, i); 3371 p += scnprintf(p, end - p, "0x%04X: ", i); 3372 break; 3373 } 3374 3375 udelay(10); 3376 3377 switch (info->rd_byte) { 3378 case 1: 3379 default: 3380 val8 = rtw89_read8_mask(rtwdev, 3381 info->rd_addr, info->rd_msk); 3382 p += scnprintf(p, end - p, "0x%02X\n", val8); 3383 break; 3384 case 2: 3385 val16 = rtw89_read16_mask(rtwdev, 3386 info->rd_addr, info->rd_msk); 3387 p += scnprintf(p, end - p, "0x%04X\n", val16); 3388 break; 3389 case 4: 3390 val32 = rtw89_read32_mask(rtwdev, 3391 info->rd_addr, info->rd_msk); 3392 p += scnprintf(p, end - p, "0x%08X\n", val32); 3393 break; 3394 } 3395 } 3396 3397 out: 3398 return p - buf; 3399 } 3400 3401 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 3402 char *buf, size_t bufsz) 3403 { 3404 char *p = buf, *end = buf + bufsz; 3405 ssize_t n; 3406 u32 sel; 3407 3408 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 3409 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 3410 if (!is_dbg_port_valid(rtwdev, sel)) 3411 continue; 3412 n = rtw89_debug_mac_dbg_port_dump(rtwdev, p, end - p, sel); 3413 if (n < 0) { 3414 rtw89_err(rtwdev, 3415 "failed to dump debug port %d\n", sel); 3416 break; 3417 } 3418 p += n; 3419 } 3420 3421 return p - buf; 3422 } 3423 3424 static ssize_t 3425 rtw89_debug_priv_mac_dbg_port_dump_get(struct rtw89_dev *rtwdev, 3426 struct rtw89_debugfs_priv *debugfs_priv, 3427 char *buf, size_t bufsz) 3428 { 3429 char *p = buf, *end = buf + bufsz; 3430 3431 if (debugfs_priv->dbgpkg_en.ss_dbg) 3432 p += rtw89_debug_mac_dump_ss_dbg(rtwdev, p, end - p); 3433 if (debugfs_priv->dbgpkg_en.dle_dbg) 3434 p += rtw89_debug_mac_dump_dle_dbg(rtwdev, p, end - p); 3435 if (debugfs_priv->dbgpkg_en.dmac_dbg) 3436 p += rtw89_debug_mac_dump_dmac_dbg(rtwdev, p, end - p); 3437 if (debugfs_priv->dbgpkg_en.cmac_dbg) 3438 p += rtw89_debug_mac_dump_cmac_dbg(rtwdev, p, end - p); 3439 if (debugfs_priv->dbgpkg_en.dbg_port) 3440 p += rtw89_debug_mac_dump_dbg_port(rtwdev, p, end - p); 3441 3442 return p - buf; 3443 }; 3444 3445 static u8 *rtw89_hex2bin(struct rtw89_dev *rtwdev, const char *buf, size_t count) 3446 { 3447 u8 *bin; 3448 int num; 3449 int err = 0; 3450 3451 num = count / 2; 3452 bin = kmalloc(num, GFP_KERNEL); 3453 if (!bin) { 3454 err = -EFAULT; 3455 goto out; 3456 } 3457 3458 if (hex2bin(bin, buf, num)) { 3459 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 3460 kfree(bin); 3461 err = -EINVAL; 3462 } 3463 3464 out: 3465 return err ? ERR_PTR(err) : bin; 3466 } 3467 3468 static ssize_t rtw89_debug_priv_send_h2c_set(struct rtw89_dev *rtwdev, 3469 struct rtw89_debugfs_priv *debugfs_priv, 3470 const char *buf, size_t count) 3471 { 3472 u8 *h2c; 3473 int ret; 3474 u16 h2c_len = count / 2; 3475 3476 h2c = rtw89_hex2bin(rtwdev, buf, count); 3477 if (IS_ERR(h2c)) 3478 return -EFAULT; 3479 3480 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3481 3482 kfree(h2c); 3483 3484 return ret ? ret : count; 3485 } 3486 3487 static ssize_t 3488 rtw89_debug_priv_early_h2c_get(struct rtw89_dev *rtwdev, 3489 struct rtw89_debugfs_priv *debugfs_priv, 3490 char *buf, size_t bufsz) 3491 { 3492 struct rtw89_early_h2c *early_h2c; 3493 char *p = buf, *end = buf + bufsz; 3494 int seq = 0; 3495 3496 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3497 3498 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3499 p += scnprintf(p, end - p, "%d: %*ph\n", ++seq, 3500 early_h2c->h2c_len, early_h2c->h2c); 3501 3502 return p - buf; 3503 } 3504 3505 static ssize_t 3506 rtw89_debug_priv_early_h2c_set(struct rtw89_dev *rtwdev, 3507 struct rtw89_debugfs_priv *debugfs_priv, 3508 const char *buf, size_t count) 3509 { 3510 struct rtw89_early_h2c *early_h2c; 3511 u8 *h2c; 3512 u16 h2c_len = count / 2; 3513 3514 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3515 3516 h2c = rtw89_hex2bin(rtwdev, buf, count); 3517 if (IS_ERR(h2c)) 3518 return -EFAULT; 3519 3520 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3521 kfree(h2c); 3522 rtw89_fw_free_all_early_h2c(rtwdev); 3523 goto out; 3524 } 3525 3526 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 3527 if (!early_h2c) { 3528 kfree(h2c); 3529 return -EFAULT; 3530 } 3531 3532 early_h2c->h2c = h2c; 3533 early_h2c->h2c_len = h2c_len; 3534 3535 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3536 3537 out: 3538 return count; 3539 } 3540 3541 static int rtw89_dbg_trigger_l1_error_by_halt_h2c_ax(struct rtw89_dev *rtwdev) 3542 { 3543 if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3544 return -EBUSY; 3545 3546 return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RESET_FORCE); 3547 } 3548 3549 static int rtw89_dbg_trigger_l1_error_by_halt_h2c_be(struct rtw89_dev *rtwdev) 3550 { 3551 if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3552 return -EBUSY; 3553 3554 rtw89_write32_set(rtwdev, R_BE_FW_TRIGGER_IDCT_ISR, 3555 B_BE_DMAC_FW_TRIG_IDCT | B_BE_DMAC_FW_ERR_IDCT_IMR); 3556 3557 return 0; 3558 } 3559 3560 static int rtw89_dbg_trigger_l1_error_by_halt_h2c(struct rtw89_dev *rtwdev) 3561 { 3562 const struct rtw89_chip_info *chip = rtwdev->chip; 3563 3564 switch (chip->chip_gen) { 3565 case RTW89_CHIP_AX: 3566 return rtw89_dbg_trigger_l1_error_by_halt_h2c_ax(rtwdev); 3567 case RTW89_CHIP_BE: 3568 return rtw89_dbg_trigger_l1_error_by_halt_h2c_be(rtwdev); 3569 default: 3570 return -EOPNOTSUPP; 3571 } 3572 } 3573 3574 static int rtw89_dbg_trigger_l1_error(struct rtw89_dev *rtwdev) 3575 { 3576 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3577 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3578 u16 pkt_id; 3579 int ret; 3580 3581 if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw)) 3582 return rtw89_dbg_trigger_l1_error_by_halt_h2c(rtwdev); 3583 3584 rtw89_leave_ps_mode(rtwdev); 3585 3586 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3587 if (ret) 3588 return ret; 3589 3590 /* intentionally, enqueue two pkt, but has only one pkt id */ 3591 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3592 ctrl_para.start_pktid = pkt_id; 3593 ctrl_para.end_pktid = pkt_id; 3594 ctrl_para.pkt_num = 1; /* start from 0 */ 3595 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3596 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3597 3598 if (mac->set_cpuio(rtwdev, &ctrl_para, true)) 3599 return -EFAULT; 3600 3601 return 0; 3602 } 3603 3604 static int rtw89_dbg_trigger_l0_error_ax(struct rtw89_dev *rtwdev) 3605 { 3606 u16 val16; 3607 u8 val8; 3608 int ret; 3609 3610 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3611 if (ret) 3612 return ret; 3613 3614 val8 = rtw89_read8(rtwdev, R_AX_CMAC_FUNC_EN); 3615 rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8 & ~B_AX_TMAC_EN); 3616 mdelay(1); 3617 rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8); 3618 3619 val16 = rtw89_read16(rtwdev, R_AX_PTCL_IMR0); 3620 rtw89_write16(rtwdev, R_AX_PTCL_IMR0, val16 | B_AX_F2PCMD_EMPTY_ERR_INT_EN); 3621 rtw89_write16(rtwdev, R_AX_PTCL_IMR0, val16); 3622 3623 return 0; 3624 } 3625 3626 static int rtw89_dbg_trigger_l0_error_be(struct rtw89_dev *rtwdev) 3627 { 3628 u8 val8; 3629 int ret; 3630 3631 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3632 if (ret) 3633 return ret; 3634 3635 val8 = rtw89_read8(rtwdev, R_BE_CMAC_FUNC_EN); 3636 rtw89_write8(rtwdev, R_BE_CMAC_FUNC_EN, val8 & ~B_BE_TMAC_EN); 3637 mdelay(1); 3638 rtw89_write8(rtwdev, R_BE_CMAC_FUNC_EN, val8); 3639 3640 return 0; 3641 } 3642 3643 static int rtw89_dbg_trigger_l0_error_by_halt_h2c_ax(struct rtw89_dev *rtwdev) 3644 { 3645 if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3646 return -EBUSY; 3647 3648 return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L0_RESET_FORCE); 3649 } 3650 3651 static int rtw89_dbg_trigger_l0_error_by_halt_h2c_be(struct rtw89_dev *rtwdev) 3652 { 3653 if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3654 return -EBUSY; 3655 3656 rtw89_write32_set(rtwdev, R_BE_CMAC_FW_TRIGGER_IDCT_ISR, 3657 B_BE_CMAC_FW_TRIG_IDCT | B_BE_CMAC_FW_ERR_IDCT_IMR); 3658 3659 return 0; 3660 } 3661 3662 static int rtw89_dbg_trigger_l0_error(struct rtw89_dev *rtwdev) 3663 { 3664 const struct rtw89_chip_info *chip = rtwdev->chip; 3665 int (*sim_l0_by_halt_h2c)(struct rtw89_dev *rtwdev); 3666 int (*sim_l0)(struct rtw89_dev *rtwdev); 3667 3668 switch (chip->chip_gen) { 3669 case RTW89_CHIP_AX: 3670 sim_l0_by_halt_h2c = rtw89_dbg_trigger_l0_error_by_halt_h2c_ax; 3671 sim_l0 = rtw89_dbg_trigger_l0_error_ax; 3672 break; 3673 case RTW89_CHIP_BE: 3674 sim_l0_by_halt_h2c = rtw89_dbg_trigger_l0_error_by_halt_h2c_be; 3675 sim_l0 = rtw89_dbg_trigger_l0_error_be; 3676 break; 3677 default: 3678 return -EOPNOTSUPP; 3679 } 3680 3681 if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw)) 3682 return sim_l0_by_halt_h2c(rtwdev); 3683 3684 rtw89_leave_ps_mode(rtwdev); 3685 3686 return sim_l0(rtwdev); 3687 } 3688 3689 static ssize_t 3690 rtw89_debug_priv_fw_crash_get(struct rtw89_dev *rtwdev, 3691 struct rtw89_debugfs_priv *debugfs_priv, 3692 char *buf, size_t bufsz) 3693 { 3694 char *p = buf, *end = buf + bufsz; 3695 3696 p += scnprintf(p, end - p, "%d\n", 3697 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3698 return p - buf; 3699 } 3700 3701 enum rtw89_dbg_crash_simulation_type { 3702 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3703 RTW89_DBG_SIM_L1_ERROR = 2, 3704 RTW89_DBG_SIM_L0_ERROR = 3, 3705 }; 3706 3707 static ssize_t 3708 rtw89_debug_priv_fw_crash_set(struct rtw89_dev *rtwdev, 3709 struct rtw89_debugfs_priv *debugfs_priv, 3710 const char *buf, size_t count) 3711 { 3712 int (*sim)(struct rtw89_dev *rtwdev); 3713 bool announce = true; 3714 u8 crash_type; 3715 int ret; 3716 3717 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3718 3719 ret = kstrtou8(buf, 0, &crash_type); 3720 if (ret) 3721 return -EINVAL; 3722 3723 switch (crash_type) { 3724 case RTW89_DBG_SIM_CPU_EXCEPTION: 3725 if (!RTW89_CHK_FW_FEATURE_GROUP(CRASH_TRIGGER, &rtwdev->fw)) 3726 return -EOPNOTSUPP; 3727 sim = rtw89_fw_h2c_trigger_cpu_exception; 3728 break; 3729 case RTW89_DBG_SIM_L1_ERROR: 3730 sim = rtw89_dbg_trigger_l1_error; 3731 break; 3732 case RTW89_DBG_SIM_L0_ERROR: 3733 sim = rtw89_dbg_trigger_l0_error; 3734 3735 /* Driver SER flow won't get involved; only FW will. */ 3736 announce = false; 3737 break; 3738 default: 3739 return -EINVAL; 3740 } 3741 3742 if (announce) 3743 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3744 3745 ret = sim(rtwdev); 3746 3747 if (ret) 3748 return ret; 3749 3750 return count; 3751 } 3752 3753 struct rtw89_dbg_ser_counters { 3754 unsigned int l0; 3755 unsigned int l1; 3756 unsigned int l0_to_l1; 3757 }; 3758 3759 static void rtw89_dbg_get_ser_counters_ax(struct rtw89_dev *rtwdev, 3760 struct rtw89_dbg_ser_counters *cnt) 3761 { 3762 const u32 val = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 3763 3764 cnt->l0 = u32_get_bits(val, B_AX_SER_L0_COUNTER_MASK); 3765 cnt->l1 = u32_get_bits(val, B_AX_SER_L1_COUNTER_MASK); 3766 cnt->l0_to_l1 = u32_get_bits(val, B_AX_L0_TO_L1_EVENT_MASK); 3767 } 3768 3769 static void rtw89_dbg_get_ser_counters_be(struct rtw89_dev *rtwdev, 3770 struct rtw89_dbg_ser_counters *cnt) 3771 { 3772 const u32 val = rtw89_read32(rtwdev, R_BE_SER_DBG_INFO); 3773 3774 cnt->l0 = u32_get_bits(val, B_BE_SER_L0_COUNTER_MASK); 3775 cnt->l1 = u32_get_bits(val, B_BE_SER_L1_COUNTER_MASK); 3776 cnt->l0_to_l1 = u32_get_bits(val, B_BE_SER_L0_PROMOTE_L1_EVENT_MASK); 3777 } 3778 3779 static ssize_t rtw89_debug_priv_ser_counters_get(struct rtw89_dev *rtwdev, 3780 struct rtw89_debugfs_priv *debugfs_priv, 3781 char *buf, size_t bufsz) 3782 { 3783 const struct rtw89_chip_info *chip = rtwdev->chip; 3784 struct rtw89_dbg_ser_counters cnt = {}; 3785 char *p = buf, *end = buf + bufsz; 3786 3787 rtw89_leave_ps_mode(rtwdev); 3788 3789 switch (chip->chip_gen) { 3790 case RTW89_CHIP_AX: 3791 rtw89_dbg_get_ser_counters_ax(rtwdev, &cnt); 3792 break; 3793 case RTW89_CHIP_BE: 3794 rtw89_dbg_get_ser_counters_be(rtwdev, &cnt); 3795 break; 3796 default: 3797 return -EOPNOTSUPP; 3798 } 3799 3800 p += scnprintf(p, end - p, "SER L0 Count: %d\n", cnt.l0); 3801 p += scnprintf(p, end - p, "SER L1 Count: %d\n", cnt.l1); 3802 p += scnprintf(p, end - p, "SER L0 promote event: %d\n", cnt.l0_to_l1); 3803 3804 return p - buf; 3805 } 3806 3807 static ssize_t rtw89_debug_priv_btc_info_get(struct rtw89_dev *rtwdev, 3808 struct rtw89_debugfs_priv *debugfs_priv, 3809 char *buf, size_t bufsz) 3810 { 3811 return rtw89_btc_dump_info(rtwdev, buf, bufsz); 3812 } 3813 3814 static ssize_t rtw89_debug_priv_btc_manual_set(struct rtw89_dev *rtwdev, 3815 struct rtw89_debugfs_priv *debugfs_priv, 3816 const char *buf, size_t count) 3817 { 3818 struct rtw89_btc *btc = &rtwdev->btc; 3819 const struct rtw89_btc_ver *ver = btc->ver; 3820 int ret; 3821 3822 ret = kstrtobool(buf, &btc->manual_ctrl); 3823 if (ret) 3824 return ret; 3825 3826 if (ver->fcxctrl == 7) 3827 btc->ctrl.ctrl_v7.manual = btc->manual_ctrl; 3828 else 3829 btc->ctrl.ctrl.manual = btc->manual_ctrl; 3830 3831 return count; 3832 } 3833 3834 static ssize_t rtw89_debug_priv_fw_log_manual_set(struct rtw89_dev *rtwdev, 3835 struct rtw89_debugfs_priv *debugfs_priv, 3836 const char *buf, size_t count) 3837 { 3838 struct rtw89_fw_log *log = &rtwdev->fw.log; 3839 bool fw_log_manual; 3840 3841 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3842 3843 if (kstrtobool(buf, &fw_log_manual)) 3844 goto out; 3845 3846 log->enable = fw_log_manual; 3847 if (log->enable) 3848 rtw89_fw_log_prepare(rtwdev); 3849 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3850 out: 3851 return count; 3852 } 3853 3854 static int rtw89_sta_link_info_get_iter(struct rtw89_dev *rtwdev, 3855 char *buf, size_t bufsz, 3856 struct rtw89_sta_link *rtwsta_link) 3857 { 3858 static const char * const he_gi_str[] = { 3859 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3860 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3861 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3862 }; 3863 static const char * const eht_gi_str[] = { 3864 [NL80211_RATE_INFO_EHT_GI_0_8] = "0.8", 3865 [NL80211_RATE_INFO_EHT_GI_1_6] = "1.6", 3866 [NL80211_RATE_INFO_EHT_GI_3_2] = "3.2", 3867 }; 3868 struct rate_info *rate = &rtwsta_link->ra_report.txrate; 3869 struct ieee80211_rx_status *status = &rtwsta_link->rx_status; 3870 struct rtw89_hal *hal = &rtwdev->hal; 3871 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3872 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3873 struct ieee80211_link_sta *link_sta; 3874 char *p = buf, *end = buf + bufsz; 3875 u8 evm_min, evm_max, evm_1ss; 3876 u16 max_rc_amsdu_len; 3877 u8 rssi; 3878 u8 snr; 3879 int i; 3880 3881 rcu_read_lock(); 3882 3883 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3884 max_rc_amsdu_len = link_sta->agg.max_rc_amsdu_len; 3885 3886 rcu_read_unlock(); 3887 3888 p += scnprintf(p, end - p, "TX rate [%u, %u]: ", rtwsta_link->mac_id, 3889 rtwsta_link->link_id); 3890 3891 if (rate->flags & RATE_INFO_FLAGS_MCS) 3892 p += scnprintf(p, end - p, "HT MCS-%d%s", rate->mcs, 3893 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3894 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3895 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", rate->nss, 3896 rate->mcs, 3897 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3898 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3899 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", rate->nss, 3900 rate->mcs, 3901 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3902 he_gi_str[rate->he_gi] : "N/A"); 3903 else if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) 3904 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", rate->nss, 3905 rate->mcs, 3906 rate->eht_gi < ARRAY_SIZE(eht_gi_str) ? 3907 eht_gi_str[rate->eht_gi] : "N/A"); 3908 else 3909 p += scnprintf(p, end - p, "Legacy %d", rate->legacy); 3910 p += scnprintf(p, end - p, "%s", 3911 rtwsta_link->ra_report.might_fallback_legacy ? " FB_G" : ""); 3912 p += scnprintf(p, end - p, " BW:%u", 3913 rtw89_rate_info_bw_to_mhz(rate->bw)); 3914 p += scnprintf(p, end - p, " (hw_rate=0x%x)", 3915 rtwsta_link->ra_report.hw_rate); 3916 p += scnprintf(p, end - p, " ==> agg_wait=%d (%d)\n", 3917 rtwsta_link->max_agg_wait, 3918 max_rc_amsdu_len); 3919 3920 p += scnprintf(p, end - p, "RX rate [%u, %u]: ", rtwsta_link->mac_id, 3921 rtwsta_link->link_id); 3922 3923 switch (status->encoding) { 3924 case RX_ENC_LEGACY: 3925 p += scnprintf(p, end - p, "Legacy %d", status->rate_idx + 3926 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 3927 break; 3928 case RX_ENC_HT: 3929 p += scnprintf(p, end - p, "HT MCS-%d%s", status->rate_idx, 3930 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3931 break; 3932 case RX_ENC_VHT: 3933 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", status->nss, 3934 status->rate_idx, 3935 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3936 break; 3937 case RX_ENC_HE: 3938 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", 3939 status->nss, status->rate_idx, 3940 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3941 he_gi_str[status->he_gi] : "N/A"); 3942 break; 3943 case RX_ENC_EHT: 3944 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", 3945 status->nss, status->rate_idx, 3946 status->eht.gi < ARRAY_SIZE(eht_gi_str) ? 3947 eht_gi_str[status->eht.gi] : "N/A"); 3948 break; 3949 } 3950 p += scnprintf(p, end - p, " BW:%u", 3951 rtw89_rate_info_bw_to_mhz(status->bw)); 3952 p += scnprintf(p, end - p, " (hw_rate=0x%x)\n", 3953 rtwsta_link->rx_hw_rate); 3954 3955 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi); 3956 p += scnprintf(p, end - p, "RSSI: %d dBm (raw=%d, prev=%d) [", 3957 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, 3958 rtwsta_link->prev_rssi); 3959 for (i = 0; i < ant_num; i++) { 3960 rssi = ewma_rssi_read(&rtwsta_link->rssi[i]); 3961 p += scnprintf(p, end - p, "%d%s%s", 3962 RTW89_RSSI_RAW_TO_DBM(rssi), 3963 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 3964 i + 1 == ant_num ? "" : ", "); 3965 } 3966 p += scnprintf(p, end - p, "]\n"); 3967 3968 evm_1ss = ewma_evm_read(&rtwsta_link->evm_1ss); 3969 p += scnprintf(p, end - p, "EVM: [%2u.%02u, ", evm_1ss >> 2, 3970 (evm_1ss & 0x3) * 25); 3971 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 3972 evm_min = ewma_evm_read(&rtwsta_link->evm_min[i]); 3973 evm_max = ewma_evm_read(&rtwsta_link->evm_max[i]); 3974 3975 p += scnprintf(p, end - p, "%s(%2u.%02u, %2u.%02u)", 3976 i == 0 ? "" : " ", 3977 evm_min >> 2, (evm_min & 0x3) * 25, 3978 evm_max >> 2, (evm_max & 0x3) * 25); 3979 } 3980 p += scnprintf(p, end - p, "]\t"); 3981 3982 snr = ewma_snr_read(&rtwsta_link->avg_snr); 3983 p += scnprintf(p, end - p, "SNR: %u\n", snr); 3984 3985 return p - buf; 3986 } 3987 3988 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 3989 { 3990 struct rtw89_debugfs_iter_data *iter_data = 3991 (struct rtw89_debugfs_iter_data *)data; 3992 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3993 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3994 struct rtw89_sta_link *rtwsta_link; 3995 size_t bufsz = iter_data->bufsz; 3996 char *buf = iter_data->buf; 3997 char *p = buf, *end = buf + bufsz; 3998 unsigned int link_id; 3999 4000 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 4001 p += rtw89_sta_link_info_get_iter(rtwdev, p, end - p, rtwsta_link); 4002 4003 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4004 } 4005 4006 static int 4007 rtw89_debug_append_rx_rate(char *buf, size_t bufsz, struct rtw89_pkt_stat *pkt_stat, 4008 enum rtw89_hw_rate first_rate, int len) 4009 { 4010 char *p = buf, *end = buf + bufsz; 4011 int i; 4012 4013 for (i = 0; i < len; i++) 4014 p += scnprintf(p, end - p, "%s%u", i == 0 ? "" : ", ", 4015 pkt_stat->rx_rate_cnt[first_rate + i]); 4016 4017 return p - buf; 4018 } 4019 4020 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate} 4021 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate} 4022 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate} 4023 4024 static const struct rtw89_rx_rate_cnt_info { 4025 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM]; 4026 int len; 4027 int ext; 4028 const char *rate_mode; 4029 } rtw89_rx_rate_cnt_infos[] = { 4030 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"}, 4031 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"}, 4032 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"}, 4033 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"}, 4034 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"}, 4035 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"}, 4036 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"}, 4037 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"}, 4038 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"}, 4039 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"}, 4040 }; 4041 4042 static ssize_t rtw89_debug_priv_phy_info_get(struct rtw89_dev *rtwdev, 4043 struct rtw89_debugfs_priv *debugfs_priv, 4044 char *buf, size_t bufsz) 4045 { 4046 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4047 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 4048 const struct rtw89_chip_info *chip = rtwdev->chip; 4049 struct rtw89_debugfs_iter_data iter_data; 4050 const struct rtw89_rx_rate_cnt_info *info; 4051 struct rtw89_hal *hal = &rtwdev->hal; 4052 char *p = buf, *end = buf + bufsz; 4053 enum rtw89_hw_rate first_rate; 4054 u8 rssi; 4055 int i; 4056 4057 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 4058 4059 p += scnprintf(p, end - p, "TP TX: %u [%u] Mbps (lv: %d", 4060 stats->tx_throughput, stats->tx_throughput_raw, 4061 stats->tx_tfc_lv); 4062 if (hal->thermal_prot_lv) 4063 p += scnprintf(p, end - p, ", duty: %d%%", 4064 100 - hal->thermal_prot_lv * RTW89_THERMAL_PROT_STEP); 4065 p += scnprintf(p, end - p, "), RX: %u [%u] Mbps (lv: %d)\n", 4066 stats->rx_throughput, stats->rx_throughput_raw, 4067 stats->rx_tfc_lv); 4068 p += scnprintf(p, end - p, "Beacon: %u (%d dBm), TF: %u\n", 4069 pkt_stat->beacon_nr, 4070 RTW89_RSSI_RAW_TO_DBM(rssi), stats->rx_tf_periodic); 4071 p += scnprintf(p, end - p, "Avg packet length: TX=%u, RX=%u\n", 4072 stats->tx_avg_len, 4073 stats->rx_avg_len); 4074 4075 p += scnprintf(p, end - p, "RX count:\n"); 4076 4077 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 4078 info = &rtw89_rx_rate_cnt_infos[i]; 4079 first_rate = info->first_rate[chip->chip_gen]; 4080 if (first_rate >= RTW89_HW_RATE_NR) 4081 continue; 4082 4083 p += scnprintf(p, end - p, "%10s [", info->rate_mode); 4084 p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat, 4085 first_rate, info->len); 4086 if (info->ext) { 4087 p += scnprintf(p, end - p, "]["); 4088 p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat, 4089 first_rate + info->len, info->ext); 4090 } 4091 p += scnprintf(p, end - p, "]\n"); 4092 } 4093 4094 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4095 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, &iter_data); 4096 p += iter_data.written_sz; 4097 4098 return p - buf; 4099 } 4100 4101 static int rtw89_dump_addr_cam(struct rtw89_dev *rtwdev, 4102 char *buf, size_t bufsz, 4103 struct rtw89_addr_cam_entry *addr_cam) 4104 { 4105 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4106 const struct rtw89_sec_cam_entry *sec_entry; 4107 char *p = buf, *end = buf + bufsz; 4108 u8 sec_cam_idx; 4109 int i; 4110 4111 p += scnprintf(p, end - p, "\taddr_cam_idx=%u\n", 4112 addr_cam->addr_cam_idx); 4113 p += scnprintf(p, end - p, "\t-> bssid_cam_idx=%u\n", 4114 addr_cam->bssid_cam_idx); 4115 p += scnprintf(p, end - p, "\tsec_cam_bitmap=%*ph\n", 4116 (int)sizeof(addr_cam->sec_cam_map), 4117 addr_cam->sec_cam_map); 4118 for_each_set_bit(i, addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM) { 4119 sec_cam_idx = addr_cam->sec_ent[i]; 4120 sec_entry = cam_info->sec_entries[sec_cam_idx]; 4121 if (!sec_entry) 4122 continue; 4123 p += scnprintf(p, end - p, "\tsec[%d]: sec_cam_idx %u", i, 4124 sec_entry->sec_cam_idx); 4125 if (sec_entry->ext_key) 4126 p += scnprintf(p, end - p, ", %u", 4127 sec_entry->sec_cam_idx + 1); 4128 p += scnprintf(p, end - p, "\n"); 4129 } 4130 4131 return p - buf; 4132 } 4133 4134 __printf(4, 5) 4135 static int rtw89_dump_pkt_offload(char *buf, size_t bufsz, struct list_head *pkt_list, 4136 const char *fmt, ...) 4137 { 4138 char *p = buf, *end = buf + bufsz; 4139 struct rtw89_pktofld_info *info; 4140 struct va_format vaf; 4141 va_list args; 4142 4143 if (list_empty(pkt_list)) 4144 return 0; 4145 4146 va_start(args, fmt); 4147 vaf.va = &args; 4148 vaf.fmt = fmt; 4149 4150 p += scnprintf(p, end - p, "%pV", &vaf); 4151 4152 va_end(args); 4153 4154 list_for_each_entry(info, pkt_list, list) 4155 p += scnprintf(p, end - p, "%d ", info->id); 4156 4157 p += scnprintf(p, end - p, "\n"); 4158 4159 return p - buf; 4160 } 4161 4162 static int rtw89_vif_link_ids_get(struct rtw89_dev *rtwdev, 4163 char *buf, size_t bufsz, u8 *mac, 4164 struct rtw89_vif_link *rtwvif_link, 4165 bool designated) 4166 { 4167 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif_link->bssid_cam; 4168 char *p = buf, *end = buf + bufsz; 4169 4170 p += scnprintf(p, end - p, " [%u] %pM\n", rtwvif_link->mac_id, 4171 rtwvif_link->mac_addr); 4172 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwvif_link->link_id, 4173 designated ? " (*)" : ""); 4174 p += scnprintf(p, end - p, "\tbssid_cam_idx=%u\n", 4175 bssid_cam->bssid_cam_idx); 4176 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwvif_link->addr_cam); 4177 p += rtw89_dump_pkt_offload(p, end - p, &rtwvif_link->general_pkt_list, 4178 "\tpkt_ofld[GENERAL]: "); 4179 4180 return p - buf; 4181 } 4182 4183 static 4184 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 4185 { 4186 struct rtw89_debugfs_iter_data *iter_data = 4187 (struct rtw89_debugfs_iter_data *)data; 4188 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 4189 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 4190 struct rtw89_vif_link *designated_link; 4191 struct rtw89_vif_link *rtwvif_link; 4192 size_t bufsz = iter_data->bufsz; 4193 char *buf = iter_data->buf; 4194 char *p = buf, *end = buf + bufsz; 4195 unsigned int link_id; 4196 4197 designated_link = rtw89_get_designated_link(rtwvif); 4198 4199 p += scnprintf(p, end - p, "VIF %pM\n", rtwvif->mac_addr); 4200 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4201 p += rtw89_vif_link_ids_get(rtwdev, p, end - p, mac, rtwvif_link, 4202 rtwvif_link == designated_link); 4203 4204 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4205 } 4206 4207 static int rtw89_dump_ba_cam(struct rtw89_dev *rtwdev, 4208 char *buf, size_t bufsz, 4209 struct rtw89_sta_link *rtwsta_link) 4210 { 4211 struct rtw89_ba_cam_entry *entry; 4212 char *p = buf, *end = buf + bufsz; 4213 bool first = true; 4214 4215 list_for_each_entry(entry, &rtwsta_link->ba_cam_list, list) { 4216 if (first) { 4217 p += scnprintf(p, end - p, "\tba_cam "); 4218 first = false; 4219 } else { 4220 p += scnprintf(p, end - p, ", "); 4221 } 4222 p += scnprintf(p, end - p, "tid[%u]=%d", entry->tid, 4223 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 4224 } 4225 p += scnprintf(p, end - p, "\n"); 4226 4227 return p - buf; 4228 } 4229 4230 static int rtw89_sta_link_ids_get(struct rtw89_dev *rtwdev, 4231 char *buf, size_t bufsz, 4232 struct rtw89_sta_link *rtwsta_link, 4233 bool designated) 4234 { 4235 struct ieee80211_link_sta *link_sta; 4236 char *p = buf, *end = buf + bufsz; 4237 4238 rcu_read_lock(); 4239 4240 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4241 4242 p += scnprintf(p, end - p, " [%u] %pM\n", rtwsta_link->mac_id, 4243 link_sta->addr); 4244 4245 rcu_read_unlock(); 4246 4247 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwsta_link->link_id, 4248 designated ? " (*)" : ""); 4249 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwsta_link->addr_cam); 4250 p += rtw89_dump_ba_cam(rtwdev, p, end - p, rtwsta_link); 4251 4252 return p - buf; 4253 } 4254 4255 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 4256 { 4257 struct rtw89_debugfs_iter_data *iter_data = 4258 (struct rtw89_debugfs_iter_data *)data; 4259 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4260 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4261 struct rtw89_sta_link *designated_link; 4262 struct rtw89_sta_link *rtwsta_link; 4263 size_t bufsz = iter_data->bufsz; 4264 char *buf = iter_data->buf; 4265 char *p = buf, *end = buf + bufsz; 4266 unsigned int link_id; 4267 4268 designated_link = rtw89_get_designated_link(rtwsta); 4269 4270 p += scnprintf(p, end - p, "STA %pM %s\n", sta->addr, 4271 sta->tdls ? "(TDLS)" : ""); 4272 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 4273 p += rtw89_sta_link_ids_get(rtwdev, p, end - p, rtwsta_link, 4274 rtwsta_link == designated_link); 4275 4276 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4277 } 4278 4279 static ssize_t rtw89_debug_priv_stations_get(struct rtw89_dev *rtwdev, 4280 struct rtw89_debugfs_priv *debugfs_priv, 4281 char *buf, size_t bufsz) 4282 { 4283 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4284 struct rtw89_debugfs_iter_data iter_data; 4285 char *p = buf, *end = buf + bufsz; 4286 u8 idx; 4287 4288 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4289 4290 p += scnprintf(p, end - p, "map:\n"); 4291 p += scnprintf(p, end - p, "\tmac_id: %*ph\n", 4292 (int)sizeof(rtwdev->mac_id_map), 4293 rtwdev->mac_id_map); 4294 p += scnprintf(p, end - p, "\taddr_cam: %*ph\n", 4295 (int)sizeof(cam_info->addr_cam_map), 4296 cam_info->addr_cam_map); 4297 p += scnprintf(p, end - p, "\tbssid_cam: %*ph\n", 4298 (int)sizeof(cam_info->bssid_cam_map), 4299 cam_info->bssid_cam_map); 4300 p += scnprintf(p, end - p, "\tsec_cam: %*ph\n", 4301 (int)sizeof(cam_info->sec_cam_map), 4302 cam_info->sec_cam_map); 4303 p += scnprintf(p, end - p, "\tba_cam: %*ph\n", 4304 (int)sizeof(cam_info->ba_cam_map), 4305 cam_info->ba_cam_map); 4306 p += scnprintf(p, end - p, "\tpkt_ofld: %*ph\n", 4307 (int)sizeof(rtwdev->pkt_offload), 4308 rtwdev->pkt_offload); 4309 4310 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 4311 if (!(rtwdev->chip->support_bands & BIT(idx))) 4312 continue; 4313 p += rtw89_dump_pkt_offload(p, end - p, &rtwdev->scan_info.pkt_list[idx], 4314 "\t\t[SCAN %u]: ", idx); 4315 } 4316 4317 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4318 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 4319 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, &iter_data); 4320 p += iter_data.written_sz; 4321 4322 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4323 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, &iter_data); 4324 p += iter_data.written_sz; 4325 4326 return p - buf; 4327 } 4328 4329 static void rtw89_debug_disable_dm_cfg_bmap(struct rtw89_dev *rtwdev, u32 new) 4330 { 4331 struct rtw89_hal *hal = &rtwdev->hal; 4332 u32 old = hal->disabled_dm_bitmap; 4333 4334 if (new == old) 4335 return; 4336 4337 hal->disabled_dm_bitmap = new; 4338 4339 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable DM: 0x%x -> 0x%x\n", old, new); 4340 } 4341 4342 static void rtw89_debug_disable_dm_set_flag(struct rtw89_dev *rtwdev, u8 flag) 4343 { 4344 struct rtw89_hal *hal = &rtwdev->hal; 4345 u32 cur = hal->disabled_dm_bitmap; 4346 4347 rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur | BIT(flag)); 4348 } 4349 4350 static void rtw89_debug_disable_dm_clr_flag(struct rtw89_dev *rtwdev, u8 flag) 4351 { 4352 struct rtw89_hal *hal = &rtwdev->hal; 4353 u32 cur = hal->disabled_dm_bitmap; 4354 4355 rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur & ~BIT(flag)); 4356 } 4357 4358 #define DM_INFO(type) {RTW89_DM_ ## type, #type} 4359 4360 static const struct rtw89_disabled_dm_info { 4361 enum rtw89_dm_type type; 4362 const char *name; 4363 } rtw89_disabled_dm_infos[] = { 4364 DM_INFO(DYNAMIC_EDCCA), 4365 DM_INFO(THERMAL_PROTECT), 4366 DM_INFO(TAS), 4367 DM_INFO(MLO), 4368 }; 4369 4370 static ssize_t 4371 rtw89_debug_priv_disable_dm_get(struct rtw89_dev *rtwdev, 4372 struct rtw89_debugfs_priv *debugfs_priv, 4373 char *buf, size_t bufsz) 4374 { 4375 const struct rtw89_disabled_dm_info *info; 4376 struct rtw89_hal *hal = &rtwdev->hal; 4377 char *p = buf, *end = buf + bufsz; 4378 u32 disabled; 4379 int i; 4380 4381 p += scnprintf(p, end - p, "Disabled DM: 0x%x\n", 4382 hal->disabled_dm_bitmap); 4383 4384 for (i = 0; i < ARRAY_SIZE(rtw89_disabled_dm_infos); i++) { 4385 info = &rtw89_disabled_dm_infos[i]; 4386 disabled = BIT(info->type) & hal->disabled_dm_bitmap; 4387 4388 p += scnprintf(p, end - p, "[%d] %s: %c\n", info->type, 4389 info->name, 4390 disabled ? 'X' : 'O'); 4391 } 4392 4393 return p - buf; 4394 } 4395 4396 static ssize_t 4397 rtw89_debug_priv_disable_dm_set(struct rtw89_dev *rtwdev, 4398 struct rtw89_debugfs_priv *debugfs_priv, 4399 const char *buf, size_t count) 4400 { 4401 u32 conf; 4402 int ret; 4403 4404 ret = kstrtou32(buf, 0, &conf); 4405 if (ret) 4406 return -EINVAL; 4407 4408 rtw89_debug_disable_dm_cfg_bmap(rtwdev, conf); 4409 4410 return count; 4411 } 4412 4413 static void rtw89_debug_mlo_mode_set_mlsr(struct rtw89_dev *rtwdev, 4414 unsigned int link_id) 4415 { 4416 struct ieee80211_vif *vif; 4417 struct rtw89_vif *rtwvif; 4418 4419 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4420 vif = rtwvif_to_vif(rtwvif); 4421 if (!ieee80211_vif_is_mld(vif)) 4422 continue; 4423 4424 rtw89_core_mlsr_switch(rtwdev, rtwvif, link_id); 4425 } 4426 } 4427 4428 static ssize_t 4429 rtw89_debug_priv_mlo_mode_get(struct rtw89_dev *rtwdev, 4430 struct rtw89_debugfs_priv *debugfs_priv, 4431 char *buf, size_t bufsz) 4432 { 4433 bool mlo_dm_dis = rtwdev->hal.disabled_dm_bitmap & BIT(RTW89_DM_MLO); 4434 char *p = buf, *end = buf + bufsz; 4435 struct ieee80211_vif *vif; 4436 struct rtw89_vif *rtwvif; 4437 int count = 0; 4438 4439 p += scnprintf(p, end - p, "MLD(s) status: (MLO DM: %s)\n", 4440 str_disable_enable(mlo_dm_dis)); 4441 4442 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4443 vif = rtwvif_to_vif(rtwvif); 4444 if (!ieee80211_vif_is_mld(vif)) 4445 continue; 4446 4447 p += scnprintf(p, end - p, 4448 "\t#%u: MLO mode %x, valid 0x%x, active 0x%x\n", 4449 count++, rtwvif->mlo_mode, vif->valid_links, 4450 vif->active_links); 4451 } 4452 4453 if (count == 0) 4454 p += scnprintf(p, end - p, "\t(None)\n"); 4455 4456 return p - buf; 4457 } 4458 4459 static ssize_t 4460 rtw89_debug_priv_mlo_mode_set(struct rtw89_dev *rtwdev, 4461 struct rtw89_debugfs_priv *debugfs_priv, 4462 const char *buf, size_t count) 4463 { 4464 u8 num, mlo_mode; 4465 u32 argv; 4466 4467 num = sscanf(buf, "%hhx %u", &mlo_mode, &argv); 4468 if (num != 2) 4469 return -EINVAL; 4470 4471 rtw89_debug_disable_dm_set_flag(rtwdev, RTW89_DM_MLO); 4472 4473 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Set MLO mode to %x\n", mlo_mode); 4474 4475 switch (mlo_mode) { 4476 case RTW89_MLO_MODE_MLSR: 4477 rtw89_debug_mlo_mode_set_mlsr(rtwdev, argv); 4478 break; 4479 default: 4480 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Unsupported MLO mode\n"); 4481 rtw89_debug_disable_dm_clr_flag(rtwdev, RTW89_DM_MLO); 4482 4483 return -EOPNOTSUPP; 4484 } 4485 4486 return count; 4487 } 4488 4489 enum __diag_mac_cmd { 4490 __CMD_EQUALV, 4491 __CMD_EQUALO, 4492 __CMD_NEQUALV, 4493 __CMD_NEQUALO, 4494 __CMD_SETEQUALV, 4495 __CMD_SETEQUALO, 4496 __CMD_CMPWCR, 4497 __CMD_CMPWWD, 4498 __CMD_NEQ_CMPWCR, 4499 __CMD_NEQ_CMPWWD, 4500 __CMD_INCREMENT, 4501 __CMD_MESSAGE, 4502 }; 4503 4504 enum __diag_mac_io { 4505 __IO_NORMAL, 4506 __IO_NORMAL_PCIE, 4507 __IO_NORMAL_USB, 4508 __IO_NORMAL_SDIO, 4509 __IO_PCIE_CFG, 4510 __IO_SDIO_CCCR, 4511 }; 4512 4513 struct __diag_mac_rule_header { 4514 u8 sheet; 4515 u8 cmd; 4516 u8 seq_major; 4517 u8 seq_minor; 4518 u8 io_band; 4519 #define __DIAG_MAC_IO GENMASK(3, 0) 4520 #define __DIAG_MAC_N_BAND BIT(4) 4521 #define __DIAG_MAC_HAS_BAND BIT(5) 4522 u8 len; /* include header. Unit: 4 bytes */ 4523 u8 rsvd[2]; 4524 } __packed; 4525 4526 struct __diag_mac_rule_equal { 4527 struct __diag_mac_rule_header header; 4528 __le32 addr; 4529 __le32 addr_name_offset; 4530 __le32 mask; 4531 __le32 val; 4532 __le32 msg_offset; 4533 u8 rsvd[4]; 4534 } __packed; 4535 4536 struct __diag_mac_rule_increment { 4537 struct __diag_mac_rule_header header; 4538 __le32 addr; 4539 __le32 addr_name_offset; 4540 __le32 mask; 4541 __le16 sel; 4542 __le16 delay; 4543 __le32 msg_offset; 4544 u8 rsvd[4]; 4545 } __packed; 4546 4547 struct __diag_mac_msg_buf { 4548 __le16 len; 4549 char string[]; 4550 } __packed; 4551 4552 static ssize_t rtw89_mac_diag_do_equalv(struct rtw89_dev *rtwdev, 4553 char *buf, size_t bufsz, 4554 const struct __diag_mac_rule_equal *r, 4555 const void *msg_start, 4556 u64 *positive_bmp) 4557 { 4558 const struct __diag_mac_msg_buf *name = msg_start + 4559 le32_to_cpu(r->addr_name_offset); 4560 const struct __diag_mac_msg_buf *msg = msg_start + 4561 le32_to_cpu(r->msg_offset); 4562 bool want_eq = r->header.cmd == __CMD_EQUALV; 4563 char *p = buf, *end = buf + bufsz; 4564 bool equal = false; 4565 u32 val; 4566 4567 *positive_bmp <<= 1; 4568 4569 if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG) 4570 val = rtw89_read32_pci_cfg(rtwdev, le32_to_cpu(r->addr)); 4571 else 4572 val = rtw89_read32(rtwdev, le32_to_cpu(r->addr)); 4573 4574 if ((val & le32_to_cpu(r->mask)) == le32_to_cpu(r->val)) 4575 equal = true; 4576 4577 if (want_eq == equal) { 4578 *positive_bmp |= BIT(0); 4579 return p - buf; 4580 } 4581 4582 p += scnprintf(p, end - p, "sheet: %d, cmd: %d, Reg: %.*s => %x, %.*s\n", 4583 r->header.sheet, r->header.cmd, le16_to_cpu(name->len), 4584 name->string, val, le16_to_cpu(msg->len), msg->string); 4585 4586 return p - buf; 4587 } 4588 4589 static ssize_t rtw89_mac_diag_do_increment(struct rtw89_dev *rtwdev, 4590 char *buf, size_t bufsz, 4591 const struct __diag_mac_rule_increment *r, 4592 const void *msg_start, 4593 u64 *positive_bmp) 4594 { 4595 const struct __diag_mac_msg_buf *name = msg_start + 4596 le32_to_cpu(r->addr_name_offset); 4597 const struct __diag_mac_msg_buf *msg = msg_start + 4598 le32_to_cpu(r->msg_offset); 4599 char *p = buf, *end = buf + bufsz; 4600 u32 addr = le32_to_cpu(r->addr); 4601 u32 mask = le32_to_cpu(r->mask); 4602 u16 sel = le16_to_cpu(r->sel); 4603 u32 val1, val2; 4604 4605 *positive_bmp <<= 1; 4606 4607 rtw89_write32(rtwdev, addr, sel); 4608 4609 if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG) 4610 val1 = rtw89_read32_pci_cfg(rtwdev, addr); 4611 else 4612 val1 = rtw89_read32(rtwdev, addr); 4613 4614 mdelay(le16_to_cpu(r->delay)); 4615 4616 if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG) 4617 val2 = rtw89_read32_pci_cfg(rtwdev, addr); 4618 else 4619 val2 = rtw89_read32(rtwdev, addr); 4620 4621 if ((val2 & mask) > (val1 & mask)) { 4622 *positive_bmp |= BIT(0); 4623 return p - buf; 4624 } 4625 4626 p += scnprintf(p, end - p, "sheet: %d, cmd: %d, Reg: %.*s [%d]=> %x, %.*s\n", 4627 r->header.sheet, r->header.cmd, le16_to_cpu(name->len), 4628 name->string, le16_to_cpu(r->sel), val1, 4629 le16_to_cpu(msg->len), msg->string); 4630 4631 return p - buf; 4632 } 4633 4634 static bool rtw89_mac_diag_match_hci(struct rtw89_dev *rtwdev, 4635 const struct __diag_mac_rule_header *rh) 4636 { 4637 switch (u8_get_bits(rh->io_band, __DIAG_MAC_IO)) { 4638 case __IO_NORMAL: 4639 default: 4640 return true; 4641 case __IO_NORMAL_PCIE: 4642 case __IO_PCIE_CFG: 4643 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) 4644 return true; 4645 break; 4646 case __IO_NORMAL_USB: 4647 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 4648 return true; 4649 break; 4650 case __IO_NORMAL_SDIO: 4651 case __IO_SDIO_CCCR: 4652 if (rtwdev->hci.type == RTW89_HCI_TYPE_SDIO) 4653 return true; 4654 break; 4655 } 4656 4657 return false; 4658 } 4659 4660 static bool rtw89_mac_diag_match_band(struct rtw89_dev *rtwdev, 4661 const struct __diag_mac_rule_header *rh) 4662 { 4663 u8 active_bands; 4664 bool has_band; 4665 u8 band; 4666 4667 has_band = u8_get_bits(rh->io_band, __DIAG_MAC_HAS_BAND); 4668 if (!has_band) 4669 return true; 4670 4671 band = u8_get_bits(rh->io_band, __DIAG_MAC_N_BAND); 4672 active_bands = rtw89_get_active_phy_bitmap(rtwdev); 4673 4674 if (active_bands & BIT(band)) 4675 return true; 4676 4677 return false; 4678 } 4679 4680 static ssize_t rtw89_mac_diag_iter_all(struct rtw89_dev *rtwdev, 4681 char *buf, size_t bufsz) 4682 { 4683 const struct rtw89_fw_element_hdr *elm = rtwdev->fw.elm_info.diag_mac; 4684 u32 n_plains = 0, n_rules = 0, n_positive = 0, n_ignore = 0; 4685 char *p = buf, *end = buf + bufsz, *p_rewind; 4686 const void *rule, *rule_end; 4687 u32 elm_size, rule_size; 4688 const void *msg_start; 4689 u64 positive_bmp = 0; 4690 u8 prev_sheet = 0; 4691 u8 prev_seq = 0; 4692 int limit; 4693 4694 if (!elm) { 4695 p += scnprintf(p, end - p, "No diag_mac entry\n"); 4696 goto out; 4697 } 4698 4699 rule_size = le32_to_cpu(elm->u.diag_mac.rule_size); 4700 elm_size = le32_to_cpu(elm->size); 4701 4702 if (ALIGN(rule_size, 16) > elm_size) { 4703 p += scnprintf(p, end - p, "rule size (%u) exceed elm_size (%u)\n", 4704 ALIGN(rule_size, 16), elm_size); 4705 goto out; 4706 } 4707 4708 rule = &elm->u.diag_mac.rules_and_msgs[0]; 4709 rule_end = &elm->u.diag_mac.rules_and_msgs[rule_size]; 4710 msg_start = &elm->u.diag_mac.rules_and_msgs[ALIGN(rule_size, 16)]; 4711 4712 for (limit = 0; limit < 5000 && rule < rule_end; limit++) { 4713 const struct __diag_mac_rule_header *rh = rule; 4714 u8 sheet = rh->sheet; 4715 u8 seq = rh->seq_major; 4716 4717 if (!rtw89_mac_diag_match_hci(rtwdev, rh) || 4718 !rtw89_mac_diag_match_band(rtwdev, rh)) { 4719 n_ignore++; 4720 goto next; 4721 } 4722 4723 if (!seq || prev_sheet != sheet || prev_seq != seq) { 4724 if (positive_bmp) { 4725 n_positive++; 4726 /* 4727 * discard output for negative results if one in 4728 * a sequence set is positive. 4729 */ 4730 if (p_rewind) 4731 p = p_rewind; 4732 } 4733 p_rewind = seq ? p : NULL; 4734 positive_bmp = 0; 4735 n_rules++; 4736 } 4737 4738 switch (rh->cmd) { 4739 case __CMD_EQUALV: 4740 case __CMD_NEQUALV: 4741 p += rtw89_mac_diag_do_equalv(rtwdev, p, end - p, rule, 4742 msg_start, &positive_bmp); 4743 break; 4744 case __CMD_INCREMENT: 4745 p += rtw89_mac_diag_do_increment(rtwdev, p, end - p, rule, 4746 msg_start, &positive_bmp); 4747 break; 4748 default: 4749 p += scnprintf(p, end - p, "unknown rule cmd %u\n", rh->cmd); 4750 break; 4751 } 4752 4753 next: 4754 n_plains++; 4755 rule += rh->len * 4; 4756 prev_seq = seq; 4757 prev_sheet = sheet; 4758 } 4759 4760 if (positive_bmp) { 4761 n_positive++; 4762 if (p_rewind) 4763 p = p_rewind; 4764 } 4765 4766 p += scnprintf(p, end - p, "\nPlain(Ignore)/Rules/Positive: %u(%u)/%u/%u\n", 4767 n_plains, n_ignore, n_rules, n_positive); 4768 4769 out: 4770 return p - buf; 4771 } 4772 4773 static ssize_t 4774 rtw89_debug_priv_diag_mac_get(struct rtw89_dev *rtwdev, 4775 struct rtw89_debugfs_priv *debugfs_priv, 4776 char *buf, size_t bufsz) 4777 { 4778 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4779 4780 rtw89_leave_lps(rtwdev); 4781 4782 return rtw89_mac_diag_iter_all(rtwdev, buf, bufsz); 4783 } 4784 4785 static ssize_t 4786 rtw89_debug_priv_beacon_info_get(struct rtw89_dev *rtwdev, 4787 struct rtw89_debugfs_priv *debugfs_priv, 4788 char *buf, size_t bufsz) 4789 { 4790 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 4791 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 4792 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 4793 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 4794 u16 upper, lower = bcn_stat->tbtt_tu_min; 4795 char *p = buf, *end = buf + bufsz; 4796 u16 *drift = bcn_stat->drift; 4797 u8 bcn_num = bcn_stat->num; 4798 u8 count; 4799 u8 i; 4800 4801 p += scnprintf(p, end - p, "[Beacon info]\n"); 4802 p += scnprintf(p, end - p, "count: %u\n", pkt_stat->beacon_nr); 4803 p += scnprintf(p, end - p, "interval: %u\n", bcn_track->beacon_int); 4804 p += scnprintf(p, end - p, "dtim: %u\n", bcn_track->dtim); 4805 p += scnprintf(p, end - p, "raw rssi: %lu\n", 4806 ewma_rssi_read(&rtwdev->phystat.bcn_rssi)); 4807 p += scnprintf(p, end - p, "hw rate: %u\n", pkt_stat->beacon_rate); 4808 p += scnprintf(p, end - p, "length: %u\n", pkt_stat->beacon_len); 4809 4810 p += scnprintf(p, end - p, "\n[Distribution]\n"); 4811 p += scnprintf(p, end - p, "tbtt\n"); 4812 for (i = 0; i < RTW89_BCN_TRACK_MAX_BIN_NUM; i++) { 4813 upper = lower + RTW89_BCN_TRACK_BIN_WIDTH - 1; 4814 if (i == RTW89_BCN_TRACK_MAX_BIN_NUM - 1) 4815 upper = max(upper, bcn_stat->tbtt_tu_max); 4816 4817 p += scnprintf(p, end - p, "%02u - %02u: %u\n", 4818 lower, upper, bcn_dist->bins[i]); 4819 4820 lower = upper + 1; 4821 } 4822 4823 p += scnprintf(p, end - p, "\ndrift\n"); 4824 4825 for (i = 0; i < bcn_num; i += count) { 4826 count = 1; 4827 while (i + count < bcn_num && drift[i] == drift[i + count]) 4828 count++; 4829 4830 p += scnprintf(p, end - p, "%u: %u\n", drift[i], count); 4831 } 4832 p += scnprintf(p, end - p, "\nlower bound: %u\n", bcn_dist->lower_bound); 4833 p += scnprintf(p, end - p, "upper bound: %u\n", bcn_dist->upper_bound); 4834 p += scnprintf(p, end - p, "outlier count: %u\n", bcn_dist->outlier_count); 4835 4836 p += scnprintf(p, end - p, "\n[Tracking]\n"); 4837 p += scnprintf(p, end - p, "tbtt offset: %u\n", bcn_track->tbtt_offset); 4838 p += scnprintf(p, end - p, "bcn timeout: %u\n", bcn_track->bcn_timeout); 4839 4840 return p - buf; 4841 } 4842 4843 #define rtw89_debug_priv_get(name, opts...) \ 4844 { \ 4845 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4846 .opt = { opts }, \ 4847 } 4848 4849 #define rtw89_debug_priv_set(name, opts...) \ 4850 { \ 4851 .cb_write = rtw89_debug_priv_ ##name## _set, \ 4852 .opt = { opts }, \ 4853 } 4854 4855 #define rtw89_debug_priv_select_and_get(name, opts...) \ 4856 { \ 4857 .cb_write = rtw89_debug_priv_ ##name## _select, \ 4858 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4859 .opt = { opts }, \ 4860 } 4861 4862 #define rtw89_debug_priv_set_and_get(name, opts...) \ 4863 { \ 4864 .cb_write = rtw89_debug_priv_ ##name## _set, \ 4865 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4866 .opt = { opts }, \ 4867 } 4868 4869 #define RSIZE_8K .rsize = 0x2000 4870 #define RSIZE_12K .rsize = 0x3000 4871 #define RSIZE_16K .rsize = 0x4000 4872 #define RSIZE_20K .rsize = 0x5000 4873 #define RSIZE_32K .rsize = 0x8000 4874 #define RSIZE_64K .rsize = 0x10000 4875 #define RSIZE_128K .rsize = 0x20000 4876 #define RSIZE_1M .rsize = 0x100000 4877 #define RLOCK .rlock = 1 4878 #define WLOCK .wlock = 1 4879 #define RWLOCK RLOCK, WLOCK 4880 4881 static const struct rtw89_debugfs rtw89_debugfs_templ = { 4882 .read_reg = rtw89_debug_priv_select_and_get(read_reg), 4883 .write_reg = rtw89_debug_priv_set(write_reg), 4884 .read_rf = rtw89_debug_priv_select_and_get(read_rf), 4885 .write_rf = rtw89_debug_priv_set(write_rf), 4886 .rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump, RSIZE_8K), 4887 .txpwr_table = rtw89_debug_priv_get(txpwr_table, RSIZE_20K, RLOCK), 4888 .mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump, RSIZE_128K), 4889 .mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump, RSIZE_16K, RLOCK), 4890 .mac_dbg_port_dump = rtw89_debug_priv_select_and_get(mac_dbg_port_dump, RSIZE_1M), 4891 .send_h2c = rtw89_debug_priv_set(send_h2c), 4892 .early_h2c = rtw89_debug_priv_set_and_get(early_h2c, RWLOCK), 4893 .fw_crash = rtw89_debug_priv_set_and_get(fw_crash, WLOCK), 4894 .ser_counters = rtw89_debug_priv_get(ser_counters, RLOCK), 4895 .btc_info = rtw89_debug_priv_get(btc_info, RSIZE_12K), 4896 .btc_manual = rtw89_debug_priv_set(btc_manual), 4897 .fw_log_manual = rtw89_debug_priv_set(fw_log_manual, WLOCK), 4898 .phy_info = rtw89_debug_priv_get(phy_info), 4899 .stations = rtw89_debug_priv_get(stations, RLOCK), 4900 .disable_dm = rtw89_debug_priv_set_and_get(disable_dm, RWLOCK), 4901 .mlo_mode = rtw89_debug_priv_set_and_get(mlo_mode, RWLOCK), 4902 .beacon_info = rtw89_debug_priv_get(beacon_info), 4903 .diag_mac = rtw89_debug_priv_get(diag_mac, RSIZE_16K, RLOCK), 4904 }; 4905 4906 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 4907 do { \ 4908 struct rtw89_debugfs_priv *priv = &rtwdev->debugfs->name; \ 4909 priv->rtwdev = rtwdev; \ 4910 if (IS_ERR(debugfs_create_file(#name, mode, parent, priv, \ 4911 &file_ops_ ##fopname))) \ 4912 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 4913 } while (0) 4914 4915 #define rtw89_debugfs_add_w(name) \ 4916 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 4917 #define rtw89_debugfs_add_rw(name) \ 4918 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 4919 #define rtw89_debugfs_add_r(name) \ 4920 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 4921 4922 static 4923 void rtw89_debugfs_add_sec0(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4924 { 4925 rtw89_debugfs_add_rw(read_reg); 4926 rtw89_debugfs_add_w(write_reg); 4927 rtw89_debugfs_add_rw(read_rf); 4928 rtw89_debugfs_add_w(write_rf); 4929 rtw89_debugfs_add_r(rf_reg_dump); 4930 rtw89_debugfs_add_r(txpwr_table); 4931 rtw89_debugfs_add_rw(mac_reg_dump); 4932 rtw89_debugfs_add_rw(mac_mem_dump); 4933 rtw89_debugfs_add_rw(mac_dbg_port_dump); 4934 } 4935 4936 static 4937 void rtw89_debugfs_add_sec1(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4938 { 4939 rtw89_debugfs_add_w(send_h2c); 4940 rtw89_debugfs_add_rw(early_h2c); 4941 rtw89_debugfs_add_rw(fw_crash); 4942 rtw89_debugfs_add_r(ser_counters); 4943 rtw89_debugfs_add_r(btc_info); 4944 rtw89_debugfs_add_w(btc_manual); 4945 rtw89_debugfs_add_w(fw_log_manual); 4946 rtw89_debugfs_add_r(phy_info); 4947 rtw89_debugfs_add_r(stations); 4948 rtw89_debugfs_add_rw(disable_dm); 4949 rtw89_debugfs_add_rw(mlo_mode); 4950 rtw89_debugfs_add_r(beacon_info); 4951 rtw89_debugfs_add_r(diag_mac); 4952 } 4953 4954 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 4955 { 4956 struct dentry *debugfs_topdir; 4957 4958 rtwdev->debugfs = kmemdup(&rtw89_debugfs_templ, 4959 sizeof(rtw89_debugfs_templ), GFP_KERNEL); 4960 if (!rtwdev->debugfs) 4961 return; 4962 4963 debugfs_topdir = debugfs_create_dir("rtw89", 4964 rtwdev->hw->wiphy->debugfsdir); 4965 4966 rtw89_debugfs_add_sec0(rtwdev, debugfs_topdir); 4967 rtw89_debugfs_add_sec1(rtwdev, debugfs_topdir); 4968 } 4969 4970 void rtw89_debugfs_deinit(struct rtw89_dev *rtwdev) 4971 { 4972 kfree(rtwdev->debugfs); 4973 } 4974 #endif 4975 4976 #ifdef CONFIG_RTW89_DEBUGMSG 4977 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, 4978 const char *fmt, ...) 4979 { 4980 struct va_format vaf = { 4981 .fmt = fmt, 4982 }; 4983 4984 va_list args; 4985 4986 va_start(args, fmt); 4987 vaf.va = &args; 4988 4989 if (rtw89_debug_mask & mask) 4990 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 4991 4992 va_end(args); 4993 } 4994 EXPORT_SYMBOL(rtw89_debug); 4995 #endif 4996